diff options
| author | Jerry Jelinek <jerry.jelinek@joyent.com> | 2019-02-25 12:52:48 +0000 |
|---|---|---|
| committer | Jerry Jelinek <jerry.jelinek@joyent.com> | 2019-02-25 12:52:48 +0000 |
| commit | a23a88c8822def3a025fde613631b67191ea9ae0 (patch) | |
| tree | 8f52ea07a65ee949c88d9d0d98cbbb438f926229 | |
| parent | 540be08e437ce290999b29a244386a4283dca907 (diff) | |
| parent | 6a1a5bb98a625f9f7115565ac77e5c4170a030cc (diff) | |
| download | illumos-joyent-a23a88c8822def3a025fde613631b67191ea9ae0.tar.gz | |
[illumos-gate merge]
commit 6a1a5bb98a625f9f7115565ac77e5c4170a030cc
10133 smatch fixes for usr/src/cmd/fs.d
commit 86fec011b9215dec3869eac1fc39dc1aa9307340
10414 loader: move libzfs to libstand and clean up Makefiles
commit eef4f27b270242808b43b4b23bd161df52839361
8928 Want open source bnx
commit 57aea9348dbfeb813b16956eec292357525e2f66
10429 loader: dereferencing type-punned pointer will break strict-aliasing rules
commit 54bc10fe6ad8a64fc279dc5fba56eaafea7ec2c0
10421 bofi: cast between incompatible function types
commit 4bf63a956d4991cc5b0ead02fdea0b65bad10e78
10428 loader: really fix cd9660 dirmatch
commit f18d8787c0ba765f61b003e2aae78db90b48f833
7928 Add support for SMF_EXIT_NODAEMON
Conflicts:
usr/src/cmd/svc/startd/method.c
usr/src/cmd/nscd/svc-nscd
usr/src/cmd/dlmgmtd/svc-dlmgmtd
exception_lists/cstyle
137 files changed, 76063 insertions, 1633 deletions
diff --git a/exception_lists/closed-bins b/exception_lists/closed-bins index 10158a4d19..dd0a387f72 100644 --- a/exception_lists/closed-bins +++ b/exception_lists/closed-bins @@ -18,6 +18,8 @@ ./kernel/drv/atiatom ./kernel/drv/bcm_sata ./kernel/drv/bnx +./kernel/drv/bnx.conf +./kernel/drv/amd64/bnx ./kernel/drv/bnxe ./kernel/drv/bnxe.conf ./kernel/drv/amd64/bnxe diff --git a/exception_lists/cstyle b/exception_lists/cstyle index 61016e88f0..cbf5e23236 100644 --- a/exception_lists/cstyle +++ b/exception_lists/cstyle @@ -833,6 +833,8 @@ usr/src/uts/common/gssapi/mechs/krb5/mech/val_cred.c usr/src/uts/common/gssapi/mechs/krb5/mech/verify.c usr/src/uts/common/gssapi/mechs/krb5/mech/wrap_size_limit.c usr/src/uts/common/inet/ipf/ip_fil_solaris.c +usr/src/uts/common/io/bnx/570x/* +usr/src/uts/common/io/bnx/include/* usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_common.h usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h diff --git a/exception_lists/hdrchk b/exception_lists/hdrchk index c7fed052ea..5e70ee3eba 100644 --- a/exception_lists/hdrchk +++ b/exception_lists/hdrchk @@ -240,6 +240,8 @@ usr/src/uts/common/gssapi/mechs/krb5/include/old.h usr/src/uts/common/gssapi/mechs/krb5/include/raw.h usr/src/uts/common/gssapi/mechs/krb5/include/rsa-md4.h usr/src/uts/common/io/axf/ax88172reg.h +usr/src/uts/common/io/bnx/570x/* +usr/src/uts/common/io/bnx/include/* usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_common.h usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init.h diff --git a/usr/src/boot/lib/libstand/Makefile.inc b/usr/src/boot/lib/libstand/Makefile.inc index 3af130cdfd..1fb9e216f9 100644 --- a/usr/src/boot/lib/libstand/Makefile.inc +++ b/usr/src/boot/lib/libstand/Makefile.inc @@ -20,13 +20,13 @@ # # standalone components and stuff we have modified locally -SRCS= $(LIB_BASE)/libz/gzguts.h $(LIB_BASE)/libz/zutil.h -SRCS += $(LIBSTAND_SRC)/__main.c $(LIBSTAND_SRC)/assert.c -SRCS += $(LIBSTAND_SRC)/bcd.c $(LIBSTAND_SRC)/environment.c -SRCS += $(LIBSTAND_SRC)/getopt.c $(LIBSTAND_SRC)/strtol.c -SRCS += $(LIBSTAND_SRC)/strtoul.c $(LIBSTAND_SRC)/random.c -SRCS += $(LIBSTAND_SRC)/sbrk.c $(LIBSTAND_SRC)/twiddle.c -SRCS += $(LIBSTAND_SRC)/zalloc.c $(LIBSTAND_SRC)/zalloc_malloc.c +SRCS= $(LIBSRC)/libz/gzguts.h $(LIBSRC)/libz/zutil.h +SRCS += $(SASRC)/__main.c $(SASRC)/assert.c +SRCS += $(SASRC)/bcd.c $(SASRC)/environment.c +SRCS += $(SASRC)/getopt.c $(SASRC)/strtol.c +SRCS += $(SASRC)/strtoul.c $(SASRC)/random.c +SRCS += $(SASRC)/sbrk.c $(SASRC)/twiddle.c +SRCS += $(SASRC)/zalloc.c $(SASRC)/zalloc_malloc.c OBJS= __main.o assert.o bcd.o environment.o \ getopt.o gets.o globals.o pager.o printf.o \ @@ -34,32 +34,32 @@ OBJS= __main.o assert.o bcd.o environment.o \ sbrk.o twiddle.o zalloc.o zalloc_malloc.o # private (pruned) versions of libc string functions -SRCS += $(LIBSTAND_SRC)/strcasecmp.c +SRCS += $(SASRC)/strcasecmp.c OBJS += strcasecmp.o # from libc -SRCS += $(LIB_BASE)/libc/net/ntoh.c +SRCS += $(LIBSRC)/libc/net/ntoh.c OBJS += ntoh.o # string functions from libc -SRCS += $(LIB_BASE)/libc/string/bcmp.c $(LIB_BASE)/libc/string/bcopy.c -SRCS += $(LIB_BASE)/libc/string/bzero.c $(LIB_BASE)/libc/string/ffs.c -SRCS += $(LIB_BASE)/libc/string/fls.c $(LIB_BASE)/libc/string/memccpy.c -SRCS += $(LIB_BASE)/libc/string/memchr.c $(LIB_BASE)/libc/string/memcmp.c -SRCS += $(LIB_BASE)/libc/string/memcpy.c $(LIB_BASE)/libc/string/memmove.c -SRCS += $(LIB_BASE)/libc/string/memset.c $(LIB_BASE)/libc/string/strcat.c -SRCS += $(LIB_BASE)/libc/string/strchr.c $(LIB_BASE)/libc/string/strcmp.c -SRCS += $(LIB_BASE)/libc/string/strcpy.c $(LIB_BASE)/libc/string/stpcpy.c -SRCS += $(LIB_BASE)/libc/string/stpncpy.c $(LIB_BASE)/libc/string/strcspn.c -SRCS += $(LIB_BASE)/libc/string/strlcat.c $(LIB_BASE)/libc/string/strlcpy.c -SRCS += $(LIB_BASE)/libc/string/strlen.c $(LIB_BASE)/libc/string/strncat.c -SRCS += $(LIB_BASE)/libc/string/strncmp.c $(LIB_BASE)/libc/string/strncpy.c -SRCS += $(LIB_BASE)/libc/string/strpbrk.c $(LIB_BASE)/libc/string/strrchr.c -SRCS += $(LIB_BASE)/libc/string/strsep.c $(LIB_BASE)/libc/string/strspn.c -SRCS += $(LIB_BASE)/libc/string/strstr.c $(LIB_BASE)/libc/string/strtok.c -SRCS += $(LIB_BASE)/libc/string/swab.c - -SRCS += $(LIBSTAND_SRC)/qdivrem.c +SRCS += $(LIBSRC)/libc/string/bcmp.c $(LIBSRC)/libc/string/bcopy.c +SRCS += $(LIBSRC)/libc/string/bzero.c $(LIBSRC)/libc/string/ffs.c +SRCS += $(LIBSRC)/libc/string/fls.c $(LIBSRC)/libc/string/memccpy.c +SRCS += $(LIBSRC)/libc/string/memchr.c $(LIBSRC)/libc/string/memcmp.c +SRCS += $(LIBSRC)/libc/string/memcpy.c $(LIBSRC)/libc/string/memmove.c +SRCS += $(LIBSRC)/libc/string/memset.c $(LIBSRC)/libc/string/strcat.c +SRCS += $(LIBSRC)/libc/string/strchr.c $(LIBSRC)/libc/string/strcmp.c +SRCS += $(LIBSRC)/libc/string/strcpy.c $(LIBSRC)/libc/string/stpcpy.c +SRCS += $(LIBSRC)/libc/string/stpncpy.c $(LIBSRC)/libc/string/strcspn.c +SRCS += $(LIBSRC)/libc/string/strlcat.c $(LIBSRC)/libc/string/strlcpy.c +SRCS += $(LIBSRC)/libc/string/strlen.c $(LIBSRC)/libc/string/strncat.c +SRCS += $(LIBSRC)/libc/string/strncmp.c $(LIBSRC)/libc/string/strncpy.c +SRCS += $(LIBSRC)/libc/string/strpbrk.c $(LIBSRC)/libc/string/strrchr.c +SRCS += $(LIBSRC)/libc/string/strsep.c $(LIBSRC)/libc/string/strspn.c +SRCS += $(LIBSRC)/libc/string/strstr.c $(LIBSRC)/libc/string/strtok.c +SRCS += $(LIBSRC)/libc/string/swab.c + +SRCS += $(SASRC)/qdivrem.c OBJS += bcmp.o bcopy.o bzero.o ffs.o fls.o \ memccpy.o memchr.o memcmp.o memcpy.o memmove.o memset.o \ @@ -68,12 +68,12 @@ OBJS += bcmp.o bcopy.o bzero.o ffs.o fls.o \ strpbrk.o strrchr.o strsep.o strspn.o strstr.o strtok.o swab.o # uuid functions from libc -SRCS += $(LIB_BASE)/libc/uuid/uuid_create_nil.c -SRCS += $(LIB_BASE)/libc/uuid/uuid_equal.c -SRCS += $(LIB_BASE)/libc/uuid/uuid_is_nil.c +SRCS += $(LIBSRC)/libc/uuid/uuid_create_nil.c +SRCS += $(LIBSRC)/libc/uuid/uuid_equal.c +SRCS += $(LIBSRC)/libc/uuid/uuid_is_nil.c -SRCS += $(LIBSTAND_SRC)/uuid_from_string.c -SRCS += $(LIBSTAND_SRC)/uuid_to_string.c +SRCS += $(SASRC)/uuid_from_string.c +SRCS += $(SASRC)/uuid_to_string.c OBJS += uuid_create_nil.o uuid_equal.o uuid_from_string.o uuid_is_nil.o \ uuid_to_string.o @@ -108,28 +108,28 @@ libstand_bzlib_private.h: $(SRC)/common/bzip2/bzlib_private.h sed -e 's|<stdlib.h>|"stand.h"|' $^ > $@ # decompression functionality from libz -CFLAGS += -DHAVE_MEMCPY -I$(LIB_BASE)/libz -SRCS += $(LIB_BASE)/libz/adler32.c $(LIB_BASE)/libz/crc32.c \ +CFLAGS += -DHAVE_MEMCPY -I$(LIBSRC)/libz +SRCS += $(LIBSRC)/libz/adler32.c $(LIBSRC)/libz/crc32.c \ libstand_zutil.h libstand_gzguts.h OBJS += adler32.o crc32.o -_infback.c: $(LIB_BASE)/libz/infback.c +_infback.c: $(LIBSRC)/libz/infback.c sed -e "s|zutil\.h|libstand_zutil.h|" \ -e "s|gzguts\.h|libstand_gzguts.h|" \ $^ > $@ -_inffast.c: $(LIB_BASE)/libz/inffast.c +_inffast.c: $(LIBSRC)/libz/inffast.c sed -e "s|zutil\.h|libstand_zutil.h|" \ -e "s|gzguts\.h|libstand_gzguts.h|" \ $^ > $@ -_inflate.c: $(LIB_BASE)/libz/inflate.c +_inflate.c: $(LIBSRC)/libz/inflate.c sed -e "s|zutil\.h|libstand_zutil.h|" \ -e "s|gzguts\.h|libstand_gzguts.h|" \ $^ > $@ -_inftrees.c: $(LIB_BASE)/libz/inftrees.c +_inftrees.c: $(LIBSRC)/libz/inftrees.c sed -e "s|zutil\.h|libstand_zutil.h|" \ -e "s|gzguts\.h|libstand_gzguts.h|" \ $^ > $@ -_zutil.c: $(LIB_BASE)/libz/zutil.c +_zutil.c: $(LIBSRC)/libz/zutil.c sed -e "s|zutil\.h|libstand_zutil.h|" \ -e "s|gzguts\.h|libstand_gzguts.h|" \ $^ > $@ @@ -139,7 +139,7 @@ OBJS += _infback.o _inffast.o _inflate.o _inftrees.o _zutil.o CLEANFILES += _infback.c _inffast.c _inflate.c _inftrees.c _zutil.c # depend on stand.h being able to be included multiple times -libstand_zutil.h: $(LIB_BASE)/libz/zutil.h +libstand_zutil.h: $(LIBSRC)/libz/zutil.h sed -e 's|<fcntl.h>|"stand.h"|' \ -e 's|<stddef.h>|"stand.h"|' \ -e 's|<string.h>|"stand.h"|' \ @@ -147,7 +147,7 @@ libstand_zutil.h: $(LIB_BASE)/libz/zutil.h -e 's|<stdlib.h>|"stand.h"|' \ $^ > $@ -libstand_gzguts.h: $(LIB_BASE)/libz/gzguts.h +libstand_gzguts.h: $(LIBSRC)/libz/gzguts.h sed -e 's|<fcntl.h>|"stand.h"|' \ -e 's|<stddef.h>|"stand.h"|' \ -e 's|<string.h>|"stand.h"|' \ @@ -158,35 +158,35 @@ libstand_gzguts.h: $(LIB_BASE)/libz/gzguts.h CLEANFILES += libstand_zutil.h libstand_gzguts.h # io routines -SRCS += $(LIBSTAND_SRC)/closeall.c $(LIBSTAND_SRC)/dev.c \ - $(LIBSTAND_SRC)/ioctl.c $(LIBSTAND_SRC)/nullfs.c \ - $(LIBSTAND_SRC)/stat.c $(LIBSTAND_SRC)/fstat.c $(LIBSTAND_SRC)/close.c \ - $(LIBSTAND_SRC)/lseek.c $(LIBSTAND_SRC)/open.c $(LIBSTAND_SRC)/read.c \ - $(LIBSTAND_SRC)/write.c $(LIBSTAND_SRC)/readdir.c +SRCS += $(SASRC)/closeall.c $(SASRC)/dev.c \ + $(SASRC)/ioctl.c $(SASRC)/nullfs.c \ + $(SASRC)/stat.c $(SASRC)/fstat.c $(SASRC)/close.c \ + $(SASRC)/lseek.c $(SASRC)/open.c $(SASRC)/read.c \ + $(SASRC)/write.c $(SASRC)/readdir.c OBJS += closeall.o dev.o ioctl.o nullfs.o stat.o fstat.o close.o lseek.o \ open.o read.o write.o readdir.o # network routines -SRCS += $(LIBSTAND_SRC)/arp.c $(LIBSTAND_SRC)/ether.c $(LIBSTAND_SRC)/ip.c \ - $(LIBSTAND_SRC)/inet_ntoa.c $(LIBSTAND_SRC)/in_cksum.c \ - $(LIBSTAND_SRC)/net.c $(LIBSTAND_SRC)/udp.c $(LIBSTAND_SRC)/netif.c \ - $(LIBSTAND_SRC)/rpc.c +SRCS += $(SASRC)/arp.c $(SASRC)/ether.c $(SASRC)/ip.c \ + $(SASRC)/inet_ntoa.c $(SASRC)/in_cksum.c \ + $(SASRC)/net.c $(SASRC)/udp.c $(SASRC)/netif.c \ + $(SASRC)/rpc.c OBJS += arp.o ether.o ip.o inet_ntoa.o in_cksum.o net.o udp.o netif.o rpc.o # network info services: -SRCS += $(LIBSTAND_SRC)/bootp.c $(LIBSTAND_SRC)/rarp.c \ - $(LIBSTAND_SRC)/bootparam.c +SRCS += $(SASRC)/bootp.c $(SASRC)/rarp.c \ + $(SASRC)/bootparam.c OBJS += bootp.o rarp.o bootparam.o # boot filesystems -SRCS += $(LIBSTAND_SRC)/ufs.c -SRCS += $(LIBSTAND_SRC)/nfs.c -SRCS += $(LIBSTAND_SRC)/cd9660.c -SRCS += $(LIBSTAND_SRC)/tftp.c -SRCS += $(LIBSTAND_SRC)/gzipfs.c -SRCS += $(LIBSTAND_SRC)/bzipfs.c -SRCS += $(LIBSTAND_SRC)/dosfs.c +SRCS += $(SASRC)/ufs.c +SRCS += $(SASRC)/nfs.c +SRCS += $(SASRC)/cd9660.c +SRCS += $(SASRC)/tftp.c +SRCS += $(SASRC)/gzipfs.c +SRCS += $(SASRC)/bzipfs.c +SRCS += $(SASRC)/dosfs.c OBJS += ufs.o OBJS += nfs.o OBJS += cd9660.o @@ -195,3 +195,4 @@ OBJS += gzipfs.o OBJS += bzipfs.o OBJS += dosfs.o # +.PARALLEL: diff --git a/usr/src/boot/lib/libstand/cd9660.c b/usr/src/boot/lib/libstand/cd9660.c index 1e094450cd..487b994408 100644 --- a/usr/src/boot/lib/libstand/cd9660.c +++ b/usr/src/boot/lib/libstand/cd9660.c @@ -41,6 +41,7 @@ */ #include <sys/param.h> #include <string.h> +#include <stdbool.h> #include <sys/dirent.h> #include <fs/cd9660/iso.h> #include <fs/cd9660/cd9660_rrip.h> @@ -226,8 +227,8 @@ static int dirmatch(struct open_file *f, const char *path, struct iso_directory_record *dp, int use_rrip, int lenskip) { - size_t len; - char *cp; + size_t len, plen; + char *cp, *sep; int i, icase; if (use_rrip) @@ -241,7 +242,14 @@ dirmatch(struct open_file *f, const char *path, struct iso_directory_record *dp, } else icase = 0; - if (strlen(path) != len) + sep = strchr(path, '/'); + if (sep != NULL) { + plen = sep - path; + } else { + plen = strlen(path); + } + + if (plen != len) return (0); for (i = len; --i >= 0; path++, cp++) { @@ -283,6 +291,7 @@ cd9660_open(const char *path, struct open_file *f) struct iso_directory_record rec; struct iso_directory_record *dp = NULL; int rc, first, use_rrip, lenskip; + bool isdir = false; /* First find the volume descriptor */ buf = malloc(buf_size = ISO_DEFAULT_BLOCK_SIZE); @@ -372,7 +381,24 @@ cd9660_open(const char *path, struct open_file *f) rec = *dp; while (*path && *path != '/') /* look for next component */ path++; - if (*path) path++; /* skip '/' */ + + if (*path) /* this component was directory */ + isdir = true; + + while (*path == '/') + path++; /* skip '/' */ + + if (*path) /* We do have next component. */ + isdir = false; + } + + /* + * if the path had trailing / but the path does point to file, + * report the error ENOTDIR. + */ + if (isdir == true && (isonum_711(rec.flags) & 2) == 0) { + rc = ENOTDIR; + goto out; } /* allocate file system specific data structure */ diff --git a/usr/src/boot/lib/libstand/zfs/Makefile.inc b/usr/src/boot/lib/libstand/zfs/Makefile.inc new file mode 100644 index 0000000000..083b6f8d07 --- /dev/null +++ b/usr/src/boot/lib/libstand/zfs/Makefile.inc @@ -0,0 +1,44 @@ +# +# This file and its contents are supplied under the terms of the +# Common Development and Distribution License ("CDDL"), version 1.0. +# You may only use this file in accordance with the terms of version +# 1.0 of the CDDL. +# +# A full copy of the text of the CDDL should have accompanied this +# source. A copy of the CDDL is also available via the Internet at +# http://www.illumos.org/license/CDDL. +# + +# +# Copyright 2016 Toomas Soome <tsoome@me.com> +# + +SRCS += $(ZFSSRC)/zfs.c +SRCS += $(ZFSSRC)/gzip.c +SRCS += $(SRC)/common/crypto/edonr/edonr.c +SRCS += $(SRC)/common/crypto/skein/skein.c +SRCS += $(SRC)/common/crypto/skein/skein_iv.c +SRCS += $(SRC)/common/crypto/skein/skein_block.c +OBJS += zfs.o +OBJS += gzip.o +OBJS += edonr.o +OBJS += skein.o +OBJS += skein_iv.o +OBJS += skein_block.o + +zfs.o := CPPFLAGS += -I../../common +zfs.o := CPPFLAGS += -I../../../cddl/boot/zfs + +# Do not unroll skein loops, reduce code size +skein_block.o := CPPFLAGS += -DSKEIN_LOOP=111 + +%.o: $(ZFSSRC)/%.c + $(COMPILE.c) -o $@ $< + +%.o: $(SRC)/common/crypto/edonr/%.c + $(COMPILE.c) -o $@ $< + +%.o: $(SRC)/common/crypto/skein/%.c + $(COMPILE.c) -o $@ $< + +zfs.o: $(ZFSSRC)/zfsimpl.c diff --git a/usr/src/boot/sys/boot/zfs/devicename_stubs.c b/usr/src/boot/lib/libstand/zfs/devicename_stubs.c index 41bf907e0c..41bf907e0c 100644 --- a/usr/src/boot/sys/boot/zfs/devicename_stubs.c +++ b/usr/src/boot/lib/libstand/zfs/devicename_stubs.c diff --git a/usr/src/boot/sys/boot/zfs/gzip.c b/usr/src/boot/lib/libstand/zfs/gzip.c index 676d1cb87f..676d1cb87f 100644 --- a/usr/src/boot/sys/boot/zfs/gzip.c +++ b/usr/src/boot/lib/libstand/zfs/gzip.c diff --git a/usr/src/boot/sys/boot/zfs/libzfs.h b/usr/src/boot/lib/libstand/zfs/libzfs.h index a8430290f1..a8430290f1 100644 --- a/usr/src/boot/sys/boot/zfs/libzfs.h +++ b/usr/src/boot/lib/libstand/zfs/libzfs.h diff --git a/usr/src/boot/sys/boot/zfs/zfs.c b/usr/src/boot/lib/libstand/zfs/zfs.c index 471fd6b32f..471fd6b32f 100644 --- a/usr/src/boot/sys/boot/zfs/zfs.c +++ b/usr/src/boot/lib/libstand/zfs/zfs.c diff --git a/usr/src/boot/sys/boot/zfs/zfsimpl.c b/usr/src/boot/lib/libstand/zfs/zfsimpl.c index b3edf4653a..b3edf4653a 100644 --- a/usr/src/boot/sys/boot/zfs/zfsimpl.c +++ b/usr/src/boot/lib/libstand/zfs/zfsimpl.c diff --git a/usr/src/boot/sys/boot/Makefile b/usr/src/boot/sys/boot/Makefile index 8a93119cd2..dacf28287c 100644 --- a/usr/src/boot/sys/boot/Makefile +++ b/usr/src/boot/sys/boot/Makefile @@ -18,7 +18,7 @@ include $(SRC)/Makefile.master INSTDIRS = i386 efi -SUBDIRS = libstand libficl libcrypto zfs $(INSTDIRS) +SUBDIRS = libstand libficl libcrypto $(INSTDIRS) all := TARGET = all clean := TARGET = clean @@ -37,6 +37,8 @@ all clean clobber: $(SUBDIRS) # install: all .WAIT $(INSTDIRS) +.PARALLEL: libstand libficl libcrypto + $(SUBDIRS): FRC @cd $@; pwd; $(MAKE) $(MFLAGS) $(TARGET) diff --git a/usr/src/boot/sys/boot/Makefile.inc b/usr/src/boot/sys/boot/Makefile.inc index cf4f1681f2..f2e7ec05d2 100644 --- a/usr/src/boot/sys/boot/Makefile.inc +++ b/usr/src/boot/sys/boot/Makefile.inc @@ -13,6 +13,13 @@ # Copyright 2017 Toomas Soome <tsoome@me.com> # +# loader.help build needs better awk +AWK= /usr/xpg4/bin/awk +LD= $(GNU_ROOT)/bin/gld +OBJCOPY= $(GNU_ROOT)/bin/gobjcopy +OBJDUMP= $(GNU_ROOT)/bin/gobjdump +GSTRIP= $(GNU_ROOT)/bin/gstrip + # Default Console font setup. # We want it to be the same as kernel. # We build compressed, stripped down version of the default font, so we have @@ -22,6 +29,35 @@ FONT= 8x16 FONT_SRC= ter-u16n.bdf FONT_DIR= $(SRC)/data/consfonts +PNGLITE= $(SRC)/common/pnglite + +BOOTSRC= $(SRC)/boot/sys/boot +LIBSRC= $(SRC)/boot/lib +SASRC= $(LIBSRC)/libstand +ZFSSRC= $(SASRC)/zfs + +# set standard values +AS_CPPFLAGS= +CPPFLAGS= -D_STANDALONE -_gcc=-nostdinc +CFLAGS64= -_gcc=-mno-red-zone + +CFLAGS= -_gcc=-Os -_gcc=-fPIC -_gcc=-ffreestanding -_gcc=-fno-builtin +CFLAGS += -_gcc=-mno-mmx -_gcc=-mno-3dnow -_gcc=-mno-sse -_gcc=-mno-sse2 +CFLAGS += -_gcc=-mno-sse3 -_gcc=-msoft-float +CFLAGS += -_gcc=-mno-avx -_gcc=-mno-aes +CFLAGS += -_gcc=-Wall +CFLAGS += $(CCNOAUTOINLINE) $(CCNOREORDER) $(CSTD_GNU99) +CCASFLAGS= -fPIC -Wa,--divide +ASFLAGS= --divide + +COMPILE.S= $(CC) $(CCASFLAGS) $(CPPFLAGS) -c + +ROOT_BOOT= $(ROOT)/boot +ROOTBOOTPROG=$(PROG:%=$(ROOT_BOOT)/%) + +$(ROOT_BOOT)/%: % + $(INS.file) + #.if ${MACHINE_CPUARCH} == "arm" # Do not generate movt/movw, because the relocation fixup for them does not # translate to the -Bsymbolic -pie format required by self_reloc() in loader(8). diff --git a/usr/src/boot/sys/boot/efi/Makefile b/usr/src/boot/sys/boot/efi/Makefile index 14fc37fe35..db9c643e2c 100644 --- a/usr/src/boot/sys/boot/efi/Makefile +++ b/usr/src/boot/sys/boot/efi/Makefile @@ -19,13 +19,6 @@ include $(SRC)/Makefile.master SUBDIRS = libefi loader -#.if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "arm" -#.if ${MK_FDT} != "no" -#SUBDIRS+= fdt -#.endif -#.endif - - all install clean clobber: $(SUBDIRS) all := TARGET = all @@ -33,10 +26,9 @@ clean := TARGET = clean clobber := TARGET = clobber install := TARGET = install -# boot1 and loader both link against libefi -boot1: libefi loader: libefi +.PARALLEL: $(SUBDIRS): FRC @cd $@; pwd; $(MAKE) $(MFLAGS) $(TARGET) diff --git a/usr/src/boot/sys/boot/efi/Makefile.inc b/usr/src/boot/sys/boot/efi/Makefile.inc index 7fbe2a3393..4201600ac3 100644 --- a/usr/src/boot/sys/boot/efi/Makefile.inc +++ b/usr/src/boot/sys/boot/efi/Makefile.inc @@ -13,22 +13,7 @@ # Copyright 2015 Toomas Soome <tsoome@me.com> # -BINDIR= /boot -PNGLITE=$(SRC)/common/pnglite - # Options used when building app-specific efi components -# See conf/kern.mk for the correct set of these -CFLAGS += -fPIC -ffreestanding -Wformat -msoft-float -CFLAGS += -mno-mmx -mno-3dnow -mno-sse2 -mno-sse3 -mno-sse -CFLAGS += -mno-avx -fshort-wchar -mno-aes -CFLAGS += -std=gnu99 -Wno-pointer-sign -Wno-empty-body - -#CFLAGS += -Wsystem-headers -Werror -Wall -Wno-format-y2k -W -#CFLAGS += -Wno-unused-parameter -Wstrict-prototypes -Wmissing-prototypes -#CFLAGS += -Wpointer-arith -Wreturn-type -Wcast-qual -Wwrite-strings -#CFLAGS += -Wswitch -Wshadow -Wunused-parameter -Wcast-align -Wno-cast-qual -#CFLAGS += -Wchar-subscripts -Winline -Wnested-externs -Wredundant-decls -#CFLAGS += -Wold-style-definition +CFLAGS += -_gcc=-fshort-wchar -ASFLAGS += -fPIC -# include ../Makefile.inc +.PARALLEL: diff --git a/usr/src/boot/sys/boot/efi/libefi/Makefile b/usr/src/boot/sys/boot/efi/libefi/Makefile index 482bfd2b4d..c6603510cc 100644 --- a/usr/src/boot/sys/boot/efi/libefi/Makefile +++ b/usr/src/boot/sys/boot/efi/libefi/Makefile @@ -28,6 +28,7 @@ all clean clobber: $(SUBDIRS) install: all +.PARALLEL: $(SUBDIRS): FRC @cd $@; pwd; $(MAKE) $(MFLAGS) $(TARGET) diff --git a/usr/src/boot/sys/boot/efi/libefi/Makefile.com b/usr/src/boot/sys/boot/efi/libefi/Makefile.com index 4ba5dbf537..064a3f8276 100644 --- a/usr/src/boot/sys/boot/efi/libefi/Makefile.com +++ b/usr/src/boot/sys/boot/efi/libefi/Makefile.com @@ -14,8 +14,7 @@ # include $(SRC)/Makefile.master - -CC= $(GNUC_ROOT)/bin/gcc +include $(SRC)/boot/sys/boot/Makefile.inc install: @@ -39,17 +38,13 @@ SRCS += delay.c \ OBJS= $(SRCS:%.c=%.o) -PNGLITE=$(SRC)/common/pnglite - -CPPFLAGS= -D_STANDALONE -DEFI -CFLAGS = -Os - -CPPFLAGS += -nostdinc -I. -I../../../../../include -I../../../.. +CPPFLAGS += -DEFI +CPPFLAGS += -I. -I../../../../../include -I../../../.. CPPFLAGS += -I$(SRC)/common/ficl -I../../../libficl CPPFLAGS += -I../../include CPPFLAGS += -I../../include/$(MACHINE) CPPFLAGS += -I../../../../../lib/libstand -CPPFLAGS += -I../../../zfs +CPPFLAGS += -I$(ZFSSRC) CPPFLAGS += -I../../../../cddl/boot/zfs CPPFLAGS += -I../../../../../lib/libz CPPFLAGS += -I$(PNGLITE) diff --git a/usr/src/boot/sys/boot/efi/libefi/amd64/Makefile b/usr/src/boot/sys/boot/efi/libefi/amd64/Makefile index 5994a68d7a..6d247f44a5 100644 --- a/usr/src/boot/sys/boot/efi/libefi/amd64/Makefile +++ b/usr/src/boot/sys/boot/efi/libefi/amd64/Makefile @@ -15,14 +15,13 @@ # MACHINE= $(MACH64) -ASFLAGS= -m64 all: libefi.a SRCS= time.c include ../Makefile.com -CFLAGS += -m64 +CFLAGS += -m64 $(CFLAGS64) CLEANFILES += machine x86 diff --git a/usr/src/boot/sys/boot/efi/libefi/i386/Makefile b/usr/src/boot/sys/boot/efi/libefi/i386/Makefile index 8e9691699c..3d1c95feed 100644 --- a/usr/src/boot/sys/boot/efi/libefi/i386/Makefile +++ b/usr/src/boot/sys/boot/efi/libefi/i386/Makefile @@ -15,7 +15,6 @@ # MACHINE= $(MACH) -ASFLAGS= -m32 all: libefi.a diff --git a/usr/src/boot/sys/boot/efi/loader/Makefile b/usr/src/boot/sys/boot/efi/loader/Makefile index fa72aaecd7..698f498258 100644 --- a/usr/src/boot/sys/boot/efi/loader/Makefile +++ b/usr/src/boot/sys/boot/efi/loader/Makefile @@ -26,6 +26,8 @@ install := TARGET = install all clean clobber install: $(SUBDIRS) +.PARALLEL: + $(SUBDIRS): FRC @cd $@; pwd; $(MAKE) $(MFLAGS) $(TARGET) diff --git a/usr/src/boot/sys/boot/efi/loader/Makefile.com b/usr/src/boot/sys/boot/efi/loader/Makefile.com index 011ec84d52..4dfe547f01 100644 --- a/usr/src/boot/sys/boot/efi/loader/Makefile.com +++ b/usr/src/boot/sys/boot/efi/loader/Makefile.com @@ -19,15 +19,8 @@ include $(SRC)/Makefile.master include $(SRC)/boot/Makefile.version include $(SRC)/boot/sys/boot/Makefile.inc -CC= $(GNUC_ROOT)/bin/gcc -LD= $(GNU_ROOT)/bin/gld -OBJCOPY= $(GNU_ROOT)/bin/gobjcopy -OBJDUMP= $(GNU_ROOT)/bin/gobjdump - PROG= loader.sym -PNGLITE= $(SRC)/common/pnglite - # architecture-specific loader code SRCS= \ acpi.c \ @@ -69,8 +62,7 @@ OBJS= \ tem.o \ vers.o -CFLAGS= -Os -CPPFLAGS= -nostdinc -I../../../../../include -I../../..../ +CPPFLAGS += -I../../../../../include -I../../..../ CPPFLAGS += -I../../../../../lib/libstand CPPFLAGS += -I../../../../../lib/libz @@ -83,7 +75,7 @@ CPPFLAGS += -I../../include CPPFLAGS += -I../../include/$(MACHINE) CPPFLAGS += -I../../../.. CPPFLAGS += -I../../../i386/libi386 -CPPFLAGS += -I../../../zfs +CPPFLAGS += -I$(ZFSSRC) CPPFLAGS += -I../../../../cddl/boot/zfs CPPFLAGS += -I$(SRC)/uts/intel/sys/acpi CPPFLAGS += -I$(PNGLITE) @@ -106,14 +98,11 @@ smbios.o := CPPFLAGS += -DSMBIOS_LITTLE_ENDIAN_UUID LIBSTAND= ../../../libstand/$(MACHINE)/libstand.a BOOT_FORTH= yes -CPPFLAGS += -DBOOT_FORTH -D_STANDALONE +CPPFLAGS += -DBOOT_FORTH CPPFLAGS += -I$(SRC)/common/ficl CPPFLAGS += -I../../../libficl LIBFICL= ../../../libficl/$(MACHINE)/libficl.a -CPPFLAGS += -I../../../zfs -LIBZFSBOOT= ../../../zfs/$(MACHINE)/libzfsboot.a - # Always add MI sources include ../Makefile.common CPPFLAGS += -I../../../common @@ -158,10 +147,8 @@ loader.bin: loader.sym LIBEFI= ../../libefi/$(MACHINE)/libefi.a LIBCRYPTO= ../../../libcrypto/$(MACHINE)/libcrypto.a -DPADD= $(LIBFICL) $(LIBZFSBOOT) $(LIBEFI) $(LIBCRYPTO) $(LIBSTAND) \ - $(LDSCRIPT) -LDADD= $(LIBFICL) $(LIBZFSBOOT) $(LIBEFI) $(LIBCRYPTO) $(LIBSTAND) - +DPADD= $(LIBFICL) $(LIBEFI) $(LIBCRYPTO) $(LIBSTAND) $(LDSCRIPT) +LDADD= $(LIBFICL) $(LIBEFI) $(LIBCRYPTO) $(LIBSTAND) loader.sym: $(OBJS) $(DPADD) $(LD) $(LDFLAGS) -o $@ $(OBJS) $(LDADD) diff --git a/usr/src/boot/sys/boot/efi/loader/amd64/Makefile b/usr/src/boot/sys/boot/efi/loader/amd64/Makefile index 540894dce0..109d651772 100644 --- a/usr/src/boot/sys/boot/efi/loader/amd64/Makefile +++ b/usr/src/boot/sys/boot/efi/loader/amd64/Makefile @@ -15,7 +15,6 @@ # MACHINE= $(MACH64) -ASFLAGS= -m64 EFIPROG= loader64.efi all: $(EFIPROG) @@ -26,7 +25,8 @@ EFI_TARGET= pei-x86-64 LDFLAGS += -znocombreloc efi_main.o := CPPFLAGS += -DLOADER_EFI=L\"loader64.efi\" -CFLAGS += -m64 +CFLAGS += -m64 $(CFLAGS64) +CCASFLAGS += -m64 CLEANFILES += machine x86 $(EFIPROG) diff --git a/usr/src/boot/sys/boot/i386/Makefile b/usr/src/boot/sys/boot/i386/Makefile index cb6753d140..9c76eb1e4c 100644 --- a/usr/src/boot/sys/boot/i386/Makefile +++ b/usr/src/boot/sys/boot/i386/Makefile @@ -39,5 +39,6 @@ cdboot gptzfsboot loader pxeldr isoboot: btx FRC: +.PARALLEL: $(SUBDIRS): FRC @cd $@; pwd; $(MAKE) $(TARGET) diff --git a/usr/src/boot/sys/boot/i386/Makefile.inc b/usr/src/boot/sys/boot/i386/Makefile.inc index 5ef179f012..028eca2b1c 100644 --- a/usr/src/boot/sys/boot/i386/Makefile.inc +++ b/usr/src/boot/sys/boot/i386/Makefile.inc @@ -15,17 +15,10 @@ # Common defines for all of /sys/boot/i386/ -ROOT_BOOT= $(ROOT)/boot -ROOTBOOTPROG=$(PROG:%=$(ROOT_BOOT)/%) - LOADER_ADDRESS=0x200000 -CFLAGS += -m32 -ffreestanding -CFLAGS += -mno-mmx -mno-3dnow -mno-sse -mno-sse2 -mno-sse3 -msoft-float -CFLAGS += -std=gnu99 -LDFLAGS += -nostdlib - -ACFLAGS += -m32 -AFLAGS += --32 +CFLAGS += -m32 +CCASFLAGS += -m32 +ASFLAGS += --32 # BTX components BTXDIR= $(SRC)/boot/sys/boot/i386/btx @@ -33,5 +26,4 @@ BTXLDR= ${BTXDIR}/btxldr/btxldr BTXKERN= ${BTXDIR}/btx/btx BTXCRT= ${BTXDIR}/lib/crt0.o -$(ROOT_BOOT)/%: % - $(INS.file) +.PARALLEL: diff --git a/usr/src/boot/sys/boot/i386/btx/Makefile.inc b/usr/src/boot/sys/boot/i386/btx/Makefile.inc deleted file mode 100644 index 265f86d1ed..0000000000 --- a/usr/src/boot/sys/boot/i386/btx/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -# $FreeBSD$ - -.include "../Makefile.inc" diff --git a/usr/src/boot/sys/boot/i386/btx/btx/Makefile b/usr/src/boot/sys/boot/i386/btx/btx/Makefile index 8fe11ab569..a83818bab6 100644 --- a/usr/src/boot/sys/boot/i386/btx/btx/Makefile +++ b/usr/src/boot/sys/boot/i386/btx/btx/Makefile @@ -14,26 +14,21 @@ # include $(SRC)/Makefile.master +include $(SRC)/boot/sys/boot/Makefile.inc +include ../../Makefile.inc PROG= btx SRCS= btx.S OBJS= btx.o -AS= $(GNU_ROOT)/bin/gas -LD= $(GNU_ROOT)/bin/gld -CC= $(GNUC_ROOT)/bin/gcc - #.if defined(BOOT_BTX_NOHANG) #BOOT_BTX_FLAGS=0x1 #.else BOOT_BTX_FLAGS=0x0 #.endif -CFLAGS = -DBTX_FLAGS=${BOOT_BTX_FLAGS} -CFLAGS += -I./../../common -CFLAGS += -march=i386 -ffreestanding -mno-mmx -mno-3dnow -mno-sse -mno-sse2 -CFLAGS += -mno-sse3 -msoft-float -m32 -std=gnu99 -CFLAGS += -Wa,--divide +CPPFLAGS += -DBTX_FLAGS=${BOOT_BTX_FLAGS} +CPPFLAGS += -I./../../common #.if defined(BTX_SERIAL) #BOOT_COMCONSOLE_PORT?= 0x3f8 @@ -53,9 +48,6 @@ all install: $(PROG) $(PROG): $(OBJS) $(LD) $(LDFLAGS) -o $@ $(OBJS) -.S.o: - $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $< - clobber: clean clean: diff --git a/usr/src/boot/sys/boot/i386/btx/btxldr/Makefile b/usr/src/boot/sys/boot/i386/btx/btxldr/Makefile index 151c95f9ab..b68ebcafe4 100644 --- a/usr/src/boot/sys/boot/i386/btx/btxldr/Makefile +++ b/usr/src/boot/sys/boot/i386/btx/btxldr/Makefile @@ -14,21 +14,16 @@ # include $(SRC)/Makefile.master +include $(SRC)/boot/sys/boot/Makefile.inc +include ../../Makefile.inc PROG= btxldr SRCS= btxldr.S OBJS= btxldr.o -AS= $(GNU_ROOT)/bin/gas -LD= $(GNU_ROOT)/bin/gld -CC= $(GNUC_ROOT)/bin/gcc - -LOADER_ADDRESS=0x200000 -CPPFLAGS= -CFLAGS = -m32 -DLOADER_ADDRESS=${LOADER_ADDRESS} -CFLAGS += -I./../../common -CFLAGS += -Wa,--divide -CFLAGS += -DBTXLDR_VERBOSE +CPPFLAGS += -DLOADER_ADDRESS=${LOADER_ADDRESS} +CPPFLAGS += -DBTXLDR_VERBOSE +CPPFLAGS += -I./../../common LDFLAGS=-e start -Ttext ${LOADER_ADDRESS} -N -S --oformat binary @@ -37,9 +32,6 @@ all install: $(PROG) $(PROG): $(OBJS) $(LD) $(LDFLAGS) -o $@ $(OBJS) -.S.o: - $(COMPILE.S) $(CPPFLAGS) $(CFLAGS) -c -o $@ $< - clobber: clean clean: diff --git a/usr/src/boot/sys/boot/i386/btx/lib/Makefile b/usr/src/boot/sys/boot/i386/btx/lib/Makefile index bf89dbc619..0c797d37e5 100644 --- a/usr/src/boot/sys/boot/i386/btx/lib/Makefile +++ b/usr/src/boot/sys/boot/i386/btx/lib/Makefile @@ -14,30 +14,21 @@ # include $(SRC)/Makefile.master +include $(SRC)/boot/sys/boot/Makefile.inc +include ../../Makefile.inc -AS= $(GNU_ROOT)/bin/gas -LD= $(GNU_ROOT)/bin/gld -CC= $(GNUC_ROOT)/bin/gcc - -CPPFLAGS= -I./../../common -CFLAGS= -O2 -march=i386 -ffreestanding -mno-mmx -mno-3dnow -mno-sse -mno-sse2 -CFLAGS += -mno-sse3 -msoft-float -m32 -std=gnu99 -AS_CPPFLAGS= -ASFLAGS=--32 +CPPFLAGS += -I./../../common PROG= crt0.o SRCS= btxcsu.S btxsys.s btxv86.s OBJS= btxcsu.o btxsys.o btxv86.o -LDFLAGS=-Wl,-r -nostdlib +LDFLAGS =-r all install: $(PROG) $(PROG): $(OBJS) - $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $(OBJS) - -.S.o: - $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $< + $(LD) $(LDFLAGS) -o $@ $(OBJS) clobber: clean diff --git a/usr/src/boot/sys/boot/i386/cdboot/Makefile b/usr/src/boot/sys/boot/i386/cdboot/Makefile index f376595ad7..490029e558 100644 --- a/usr/src/boot/sys/boot/i386/cdboot/Makefile +++ b/usr/src/boot/sys/boot/i386/cdboot/Makefile @@ -14,28 +14,20 @@ # include $(SRC)/Makefile.master +include $(SRC)/boot/sys/boot/Makefile.inc +include ../Makefile.inc -ROOT_BOOT = $(ROOT)/boot - -LD= $(GNU_ROOT)/bin/gld -CC= $(GNUC_ROOT)/bin/gcc - -CFLAGS = -Os -I../common -march=i386 -ffreestanding -mno-mmx -mno-3dnow -CFLAGS += -mno-sse -mno-sse2 -mno-sse3 -msoft-float -std=gnu99 -m32 -CPPFLAGS= -CCASFLAGS= -Wa,--divide +CPPFLAGS += -I../common PROG= cdboot -STRIP= FILEMODE=0444 -MAN= SRCS= ${PROG}.S OBJS= $(SRCS:%.S=%.o) ORG= 0x7c00 -LDFLAGS=-e start -Ttext ${ORG} -N -S --oformat binary +LDFLAGS=-e start -Ttext $(ORG) -N -S --oformat binary all: ${PROG} @@ -48,8 +40,5 @@ clobber: clean clean: $(RM) $(PROG) $(OBJS) -.S.o: - $(CC) $(CFLAGS) $(CCASFLAGS) -c -o $@ $< - $(ROOT_BOOT)/%: % $(INS.file) diff --git a/usr/src/boot/sys/boot/i386/gptzfsboot/Makefile b/usr/src/boot/sys/boot/i386/gptzfsboot/Makefile index 303e8bede6..201ae6b609 100644 --- a/usr/src/boot/sys/boot/i386/gptzfsboot/Makefile +++ b/usr/src/boot/sys/boot/i386/gptzfsboot/Makefile @@ -18,11 +18,7 @@ include $(SRC)/Makefile.master include $(SRC)/boot/Makefile.version - -AS= $(GNU_ROOT)/bin/gas -LD= $(GNU_ROOT)/bin/gld -CC= $(GNUC_ROOT)/bin/gcc -OBJCOPY= $(GNU_ROOT)/bin/gobjcopy +include $(SRC)/boot/sys/boot/Makefile.inc PROG= gptzfsboot MAN= gptzfsboot.8 @@ -36,9 +32,7 @@ REL1= 0x700 ORG1= 0x7c00 ORG2= 0x0 -CPPFLAGS= -CFLAGS= -nostdinc -DBOOTPROG=\"gptzfsboot\" \ - -O1 \ +CPPFLAGS += -DBOOTPROG=\"gptzfsboot\" \ -DGPT -DBOOT2 \ -DLOADER_MBR_SUPPORT -DLOADER_GPT_SUPPORT \ -DSIOPRT=${BOOT_COMCONSOLE_PORT} \ @@ -49,23 +43,14 @@ CFLAGS= -nostdinc -DBOOTPROG=\"gptzfsboot\" \ -I../../../../lib/libz \ -I../../common \ -I../common \ - -I../../zfs \ + -I$(ZFSSRC) \ -I../../../cddl/boot/zfs \ -I../btx/lib -I. \ -I../../.. \ - -I../libi386 \ - -Wall -Waggregate-return -Wbad-function-cast -Wcast-align \ - -Wmissing-declarations -Wmissing-prototypes -Wnested-externs \ - -Wpointer-arith -Wshadow -Wwrite-strings \ - -Winline -Wno-unknown-pragmas - -CFLAGS += --param max-inline-insns-single=100 -CFLAGS += -fno-reorder-functions + -I../libi386 LD_FLAGS=-static -N --gc-sections -CCASFLAGS=-Wa,--divide LIBSTAND= ../../libstand/$(MACH)/libstand.a -LIBZFSBOOT= ../../zfs/$(MACH)/libzfsboot.a include ../Makefile.inc @@ -101,9 +86,8 @@ CLEANFILES += gptzfsboot.bin gptzfsboot.out gptzfsboot.bin: gptzfsboot.out ${OBJCOPY} -S -O binary gptzfsboot.out $@ -gptzfsboot.out: ${BTXCRT} ${OBJS} ${LIBZFSBOOT} ${LIBSTAND} - ${LD} ${LD_FLAGS} -Ttext ${ORG2} -o $@ ${BTXCRT} ${OBJS} \ - ${LIBZFSBOOT} ${LIBSTAND} +gptzfsboot.out: ${BTXCRT} ${OBJS} ${LIBSTAND} + ${LD} ${LD_FLAGS} -Ttext ${ORG2} -o $@ ${BTXCRT} ${OBJS} ${LIBSTAND} machine: $(RM) machine @@ -116,19 +100,16 @@ x86: $(OBJS): machine x86 %.o: ../common/%.c - $(COMPILE.c) -o $@ $< + $(COMPILE.c) $< %.o: ../../common/%.c - $(COMPILE.c) -o $@ $< + $(COMPILE.c) $< multiboot.o: ../../common/multiboot.S - $(CC) $(CFLAGS) $(CCASFLAGS) -c -o $@ ../../common/$*.S + $(COMPILE.S) ../../common/multiboot.S %.o: ../libi386/%.c - $(CC) $(CFLAGS) $(CPPFLAGS) -c -o $@ $< - -.S.o: - $(CC) $(CFLAGS) $(CCASFLAGS) -c -o $@ $< + $(COMPILE.c) $< clobber: clean diff --git a/usr/src/boot/sys/boot/i386/isoboot/Makefile b/usr/src/boot/sys/boot/i386/isoboot/Makefile index 5486aae03b..f6337bc3a9 100644 --- a/usr/src/boot/sys/boot/i386/isoboot/Makefile +++ b/usr/src/boot/sys/boot/i386/isoboot/Makefile @@ -15,11 +15,7 @@ include $(SRC)/Makefile.master include $(SRC)/boot/Makefile.version - -AS= $(GNU_ROOT)/bin/gas -LD= $(GNU_ROOT)/bin/gld -CC= $(GNUC_ROOT)/bin/gcc -OBJCOPY= $(GNU_ROOT)/bin/gobjcopy +include $(SRC)/boot/sys/boot/Makefile.inc PROG= isoboot FILEMODE=0444 @@ -33,9 +29,7 @@ ORG2= 0x0 ISOBOOTSIZE= 30720 -CPPFLAGS= -nostdinc -D_STANDALONE -CFLAGS= -DBOOTPROG=\"isoboot\" \ - -O1 \ +CPPFLAGS += -DBOOTPROG=\"isoboot\" \ -DSIOPRT=${BOOT_COMCONSOLE_PORT} \ -DSIOFMT=${B2SIOFMT} \ -DSIOSPD=${BOOT_COMCONSOLE_SPEED} \ @@ -46,18 +40,10 @@ CFLAGS= -DBOOTPROG=\"isoboot\" \ -I../common \ -I../btx/lib \ -I../../common \ - -I../gptzfsboot \ - -Wall -Waggregate-return -Wbad-function-cast -Wno-cast-align \ - -Wmissing-declarations -Wmissing-prototypes -Wnested-externs \ - -Wpointer-arith -Wshadow -Wstrict-prototypes -Wwrite-strings \ - -Winline -Wno-pointer-sign - -CFLAGS += --param max-inline-insns-single=100 -CFLAGS += -fno-reorder-functions + -I../gptzfsboot -LD_FLAGS= -static -N --gc-sections -CCASFLAGS= -Wa,--divide -LIBSTAND= ../../libstand/$(MACH)/libstand.a +LD_FLAGS= -static -N --gc-sections +LIBSTAND= ../../libstand/$(MACH)/libstand.a include ../Makefile.inc @@ -102,16 +88,16 @@ x86: $(OBJS): machine x86 %.o: ../gptzfsboot/%.S - $(CC) $(CFLAGS) $(CCASFLAGS) -c -o $@ $< + $(COMPILE.S) $< %.o: ../../common/%.S - $(CC) $(CFLAGS) $(CCASFLAGS) -c -o $@ $< + $(COMPILE.S) $< %.o: ../common/%.c - $(COMPILE.c) -o $@ $< + $(COMPILE.c) $< %.o: ../../common/%.c - $(COMPILE.c) -o $@ $< + $(COMPILE.c) $< clobber: clean diff --git a/usr/src/boot/sys/boot/i386/isoboot/cd9660read.c b/usr/src/boot/sys/boot/i386/isoboot/cd9660read.c index 6cfa8d304f..f1e43d7a74 100644 --- a/usr/src/boot/sys/boot/i386/isoboot/cd9660read.c +++ b/usr/src/boot/sys/boot/i386/isoboot/cd9660read.c @@ -245,7 +245,7 @@ cd9660_lookup(const char *path) break; } - rec = *(struct iso_directory_record *)vd->root_directory_record; + bcopy(vd->root_directory_record, &rec, sizeof (rec)); if (*path == '/') path++; /* eat leading '/' */ first = 1; diff --git a/usr/src/boot/sys/boot/i386/libi386/Makefile b/usr/src/boot/sys/boot/i386/libi386/Makefile index a17a4c72bd..3bf8f4920b 100644 --- a/usr/src/boot/sys/boot/i386/libi386/Makefile +++ b/usr/src/boot/sys/boot/i386/libi386/Makefile @@ -15,12 +15,11 @@ # include $(SRC)/Makefile.master +include $(SRC)/boot/sys/boot/Makefile.inc -CFLAGS= -Os -CPPFLAGS= -nostdinc -I../../../../include -I../../.. +CPPFLAGS += -I../../../../include -I../../.. CPPFLAGS += -I../../../../lib/libz -CPPFLAGS += -I../../zfs -CPPFLAGS += -D_STANDALONE +CPPFLAGS += -I$(ZFSSRC) all install: libi386.a @@ -28,14 +27,6 @@ clean: clobber clobber: $(RM) machine x86 $(OBJS) libi386.a -AS= $(GNU_ROOT)/bin/gas -CC= $(GNUC_ROOT)/bin/gcc -OBJCOPY= $(GNU_ROOT)/bin/gobjcopy -AS_FLAGS=--32 -ASFLAGS=-m32 -AS_CPPFLAGS= -COMPILE.s = $(AS) $(AS_FLAGS) - SRCS= \ amd64_tramp.S \ bio.c \ @@ -103,13 +94,12 @@ OBJS= \ vidconsole.o COMMON= ../../common -PNGLITE=$(SRC)/common/pnglite VGASUBR=$(SRC)/common/vga CPPFLAGS += -I$(PNGLITE) SRCS += $(COMMON)/gfx_fb.c $(PNGLITE)/pnglite.c OBJS += gfx_fb.o pnglite.o -LIBZFS= ../../zfs -SRCS += $(LIBZFS)/devicename_stubs.c + +SRCS += $(ZFSSRC)/devicename_stubs.c OBJS += devicename_stubs.o BOOT_COMCONSOLE_PORT= 0x3f8 @@ -168,7 +158,7 @@ $(OBJS): machine x86 libi386.a: $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) -%.o: $(LIBZFS)/%.c +%.o: $(ZFSSRC)/%.c $(COMPILE.c) -o $@ $< %.o: $(COMMON)/%.c diff --git a/usr/src/boot/sys/boot/i386/libi386/biospnp.c b/usr/src/boot/sys/boot/i386/libi386/biospnp.c index 30e55fc893..df64ba9582 100644 --- a/usr/src/boot/sys/boot/i386/libi386/biospnp.c +++ b/usr/src/boot/sys/boot/i386/libi386/biospnp.c @@ -1,4 +1,4 @@ -/*- +/* * Copyright (c) 1998 Michael Smith <msmith@freebsd.org> * All rights reserved. * @@ -25,7 +25,6 @@ */ #include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); /* * PnP BIOS enumerator. @@ -249,44 +248,47 @@ biospnp_call(int func, const char *fmt, ...) { va_list ap; const char *p; - u_int8_t *argp; - u_int32_t args[4]; - u_int32_t i; + uint8_t *argp; + uint16_t int16; + uint32_t args[4]; + uint32_t i; /* function number first */ - argp = (u_int8_t *)args; - *(u_int16_t *)argp = func; - argp += sizeof(u_int16_t); + argp = (uint8_t *)args; + int16 = func; + bcopy(&int16, argp, sizeof (int16)); + argp += sizeof(uint16_t); /* take args according to format */ va_start(ap, fmt); for (p = fmt; *p != 0; p++) { switch(*p) { - case 'w': - i = va_arg(ap, u_int); - *(u_int16_t *)argp = i; - argp += sizeof(u_int16_t); + i = va_arg(ap, uint32_t); + int16 = i; + bcopy(&int16, argp, sizeof (int16)); + argp += sizeof (uint16_t); break; case 'l': - i = va_arg(ap, u_int32_t); - *(u_int32_t *)argp = i; - argp += sizeof(u_int32_t); + i = va_arg(ap, uint32_t); + bcopy(&i, argp, sizeof (i)); + argp += sizeof (uint32_t); break; } } va_end(ap); /* BIOS segment last */ - *(u_int16_t *)argp = pnp_Icheck->pnp_rmds; - argp += sizeof(u_int16_t); + int16 = pnp_Icheck->pnp_rmds; + bcopy(&int16, argp, sizeof (int16)); + argp += sizeof(uint16_t); /* prepare for call */ v86.ctl = V86_ADDR | V86_CALLF; - v86.addr = ((u_int32_t)pnp_Icheck->pnp_rmcs << 16) + pnp_Icheck->pnp_rmip; + v86.addr = ((uint32_t)pnp_Icheck->pnp_rmcs << 16) + pnp_Icheck->pnp_rmip; /* call with packed stack and return */ v86bios(args[0], args[1], args[2], args[3]); - return(v86.eax & 0xffff); + return (v86.eax & 0xffff); } diff --git a/usr/src/boot/sys/boot/i386/libi386/bootinfo32.c b/usr/src/boot/sys/boot/i386/libi386/bootinfo32.c index adf5d514a5..fda7db76ad 100644 --- a/usr/src/boot/sys/boot/i386/libi386/bootinfo32.c +++ b/usr/src/boot/sys/boot/i386/libi386/bootinfo32.c @@ -233,10 +233,10 @@ bi_load32(char *args, int *howtop, int *bootdevp, vm_offset_t *bip, vm_offset_t ssym = esym = 0; md = file_findmetadata(kfp, MODINFOMD_SSYM); if (md != NULL) - ssym = *((vm_offset_t *)&(md->md_data)); + bcopy(&md->md_data, &ssym, sizeof (vm_offset_t)); md = file_findmetadata(kfp, MODINFOMD_ESYM); if (md != NULL) - esym = *((vm_offset_t *)&(md->md_data)); + bcopy(&md->md_data, &esym, sizeof (vm_offset_t)); if (ssym == 0 || esym == 0) ssym = esym = 0; /* sanity */ diff --git a/usr/src/boot/sys/boot/i386/loader/Makefile b/usr/src/boot/sys/boot/i386/loader/Makefile index b9d3705a00..a31d1155fe 100644 --- a/usr/src/boot/sys/boot/i386/loader/Makefile +++ b/usr/src/boot/sys/boot/i386/loader/Makefile @@ -18,25 +18,17 @@ include $(SRC)/Makefile.master include $(SRC)/boot/Makefile.version include $(SRC)/boot/sys/boot/Makefile.inc -CFLAGS= -Os -fno-reorder-functions -CPPFLAGS= -D_STANDALONE -nostdinc -I../../../../include -I../../.. +CPPFLAGS += -I../../../../include -I../../.. CPPFLAGS += -I$(SRC)/uts/intel/sys/acpi CPPFLAGS += -I../../../../lib/libz LOADER= loader NEWVERSWHAT= "ZFS enabled bootstrap loader" x86 # Set by loader Makefile -CPPFLAGS += -I../../zfs +CPPFLAGS += -I$(ZFSSRC) CPPFLAGS += -I../libi386 -LIBZFSBOOT= ../../zfs/$(MACH)/libzfsboot.a LIBI386= ../libi386/libi386.a -# loader.help build needs better awk -AWK= /usr/xpg4/bin/awk -LD= $(GNU_ROOT)/bin/gld -CC= $(GNUC_ROOT)/bin/gcc -OBJCOPY= $(GNU_ROOT)/bin/gobjcopy -GSTRIP= $(GNU_ROOT)/bin/gstrip ROOT_BOOT= $(ROOT)/boot ROOT_BOOT_DEFAULTS= $(ROOT)/boot/defaults ROOT_BOOT_FORTH= $(ROOT)/boot/forth @@ -92,7 +84,6 @@ CPPFLAGS += -I. CLEANFILES= vers.c ${LOADER} ${LOADER}.sym ${LOADER}.bin loader.help CLEANFILES += $(FONT).c -CFLAGS += -Wall LDFLAGS= -static -Ttext 0x0 # i386 standalone support library @@ -136,8 +127,8 @@ FORTH += menu.rc # XXX crt0.o needs to be first for pxeboot(8) to work -DPADD= ${LIBFICL} ${LIBZFSBOOT} ${LIBI386} ${LIBCRYPTO} ${LIBSTAND} -LDADD= ${LIBFICL} ${LIBZFSBOOT} ${LIBI386} ${LIBCRYPTO} ${LIBSTAND} +DPADD= ${LIBFICL} ${LIBI386} ${LIBCRYPTO} ${LIBSTAND} +LDADD= ${LIBFICL} ${LIBI386} ${LIBCRYPTO} ${LIBSTAND} CLEANFILES += machine x86 diff --git a/usr/src/boot/sys/boot/i386/pmbr/Makefile b/usr/src/boot/sys/boot/i386/pmbr/Makefile index a654ea2df2..0d24fd2e90 100644 --- a/usr/src/boot/sys/boot/i386/pmbr/Makefile +++ b/usr/src/boot/sys/boot/i386/pmbr/Makefile @@ -17,23 +17,17 @@ # x86 EFI pmbr build rules # include $(SRC)/Makefile.master - -ROOT_BOOT = $(ROOT)/boot +include $(SRC)/boot/sys/boot/Makefile.inc +include ../Makefile.inc PROG= pmbr -#AS= $(GNU_ROOT)/bin/gas -LD= $(GNU_ROOT)/bin/gld -STRIP= # no strip is needed FILEMODE=0444 -MAN= OBJS= pmbr.o SRCS= $(OBJS:%.o=%.s) ORG= 0x600 -AS_CPPFLAGS= # no CPP for now -ASFLAGS=--32 --divide LDFLAGS=-e start -Ttext ${ORG} -N -S --oformat binary all: $(PROG) diff --git a/usr/src/boot/sys/boot/i386/pxeldr/Makefile b/usr/src/boot/sys/boot/i386/pxeldr/Makefile index 6131daaf73..64701d15b5 100644 --- a/usr/src/boot/sys/boot/i386/pxeldr/Makefile +++ b/usr/src/boot/sys/boot/i386/pxeldr/Makefile @@ -14,18 +14,17 @@ # include $(SRC)/Makefile.master +include $(SRC)/boot/sys/boot/Makefile.inc ROOT_BOOT = $(ROOT)/boot -CC= $(GNUC_ROOT)/bin/gcc -LD= $(GNU_ROOT)/bin/gld -DD= /usr/bin/dd -CFLAGS= -Os -I../../.. +DD= /usr/bin/dd +CFLAGS += -I../../.. CCASFLAGS= -Wa,--divide include ../Makefile.inc -BTXDIR=../btx +BTXDIR= ../btx PROG= ${LDR} INTERNALPROG= @@ -47,7 +46,7 @@ FILEMODE=0444 #CFLAGS+=-DALWAYS_SERIAL #.endif -CFLAGS +=-I../common +CFLAGS += -I../common LOADERBIN= ../loader/loader.bin diff --git a/usr/src/boot/sys/boot/libcrypto/Makefile b/usr/src/boot/sys/boot/libcrypto/Makefile index 482bfd2b4d..3cedb28d09 100644 --- a/usr/src/boot/sys/boot/libcrypto/Makefile +++ b/usr/src/boot/sys/boot/libcrypto/Makefile @@ -28,6 +28,8 @@ all clean clobber: $(SUBDIRS) install: all +.PARALLEL: + $(SUBDIRS): FRC @cd $@; pwd; $(MAKE) $(MFLAGS) $(TARGET) diff --git a/usr/src/boot/sys/boot/libcrypto/Makefile.com b/usr/src/boot/sys/boot/libcrypto/Makefile.com index 6104257cd5..ce9ed268ac 100644 --- a/usr/src/boot/sys/boot/libcrypto/Makefile.com +++ b/usr/src/boot/sys/boot/libcrypto/Makefile.com @@ -14,8 +14,7 @@ # include $(SRC)/Makefile.master - -CC= $(GNUC_ROOT)/bin/gcc +include $(SRC)/boot/sys/boot/Makefile.inc COMDIR = ../../../../../common/crypto @@ -24,25 +23,17 @@ install: SRCS += sha1.c digest.c OBJS += sha1.o digest.o -CFLAGS = -Os -CFLAGS += -fPIC -ffreestanding -msoft-float -CFLAGS += -mno-mmx -mno-3dnow -mno-sse2 -mno-sse3 -mno-sse -CFLAGS += -mno-avx -mno-aes -std=gnu99 - -#.if ${MACHINE_CPUARCH} == "aarch64" -#CFLAGS+= -msoft-float -mgeneral-regs-only -#.endif - -CPPFLAGS = -nostdinc -I. -I../../../../include -I../../.. +CPPFLAGS += -I. -I../../../../include -I../../.. CPPFLAGS += -I../../../../lib/libstand # Pick up the bootstrap header for some interface items CPPFLAGS += -I../../common -CPPFLAGS += -D_STANDALONE # For multiboot2.h, must be last, to avoid conflicts CPPFLAGS += -I$(SRC)/uts/common +.PARALLEL: + libcrypto.a: $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) diff --git a/usr/src/boot/sys/boot/libcrypto/amd64/Makefile b/usr/src/boot/sys/boot/libcrypto/amd64/Makefile index f3c2b2e5df..847636d130 100644 --- a/usr/src/boot/sys/boot/libcrypto/amd64/Makefile +++ b/usr/src/boot/sys/boot/libcrypto/amd64/Makefile @@ -25,7 +25,7 @@ OBJS = sha1-x86_64.o include ../Makefile.com ASFLAGS = $(amd64_AS_XARCH) -I$(SRC)/uts/common -D_ASM -CFLAGS += -m64 +CFLAGS += -m64 $(CFLAGS64) CLEANFILES += machine x86 sha1-x86_64.s $(OBJS): machine x86 diff --git a/usr/src/boot/sys/boot/libcrypto/i386/Makefile b/usr/src/boot/sys/boot/libcrypto/i386/Makefile index 64630eaeef..999d173b6d 100644 --- a/usr/src/boot/sys/boot/libcrypto/i386/Makefile +++ b/usr/src/boot/sys/boot/libcrypto/i386/Makefile @@ -14,7 +14,6 @@ # MACHINE= $(MACH) -ASFLAGS= -m32 all: libcrypto.a diff --git a/usr/src/boot/sys/boot/libficl/Makefile b/usr/src/boot/sys/boot/libficl/Makefile index 51e6a20ed9..0f90a50467 100644 --- a/usr/src/boot/sys/boot/libficl/Makefile +++ b/usr/src/boot/sys/boot/libficl/Makefile @@ -25,6 +25,10 @@ clobber := TARGET = clobber all install: $(SUBDIRS) clean clobber: $(SUBDIRS) +$(MACH) $(MACH64): softcore + +.PARALLEL: + $(SUBDIRS): FRC @cd $@; pwd; $(MAKE) $(MFLAGS) $(TARGET) diff --git a/usr/src/boot/sys/boot/libficl/Makefile.com b/usr/src/boot/sys/boot/libficl/Makefile.com index 4d58aa5755..db77cdce2f 100644 --- a/usr/src/boot/sys/boot/libficl/Makefile.com +++ b/usr/src/boot/sys/boot/libficl/Makefile.com @@ -13,27 +13,28 @@ # Copyright 2016 Toomas Soome <tsoome@me.com> # +include $(SRC)/boot/sys/boot/Makefile.inc -CC= $(GNUC_ROOT)/bin/gcc FICLDIR= $(SRC)/common/ficl PNGLITE= $(SRC)/common/pnglite -CPPFLAGS= -nostdinc -D_STANDALONE -I. -I.. -I../../../../include +CPPFLAGS += -I. -I.. +CPPFLAGS += -I../../.. +CPPFLAGS += -I../../../../include CPPFLAGS += -I../../../../lib/libstand -CPPFLAGS += -I../../.. -I$(FICLDIR) -I../../common -I$(PNGLITE) +CPPFLAGS += -I$(FICLDIR) -I../../common -I$(PNGLITE) # For multiboot2.h, must be last, to avoid conflicts CPPFLAGS += -I$(SRC)/uts/common -CFLAGS= -Os -fPIC -Wall -ffreestanding -mno-mmx -mno-3dnow -mno-sse -CFLAGS += -mno-sse2 -mno-sse3 -msoft-float -std=gnu99 - OBJECTS= dictionary.o system.o fileaccess.o float.o double.o prefix.o search.o OBJECTS += softcore.o stack.o tools.o vm.o primitives.o unix.o utility.o OBJECTS += hash.o callback.o word.o loader.o HEADERS= $(FICLDIR)/ficl.h $(FICLDIR)/ficlplatform/unix.h ../ficllocal.h # +.PARALLEL: + MAJOR = 4 MINOR = 1.0 diff --git a/usr/src/boot/sys/boot/libficl/amd64/Makefile b/usr/src/boot/sys/boot/libficl/amd64/Makefile index bd9b9b4158..ef560fa39b 100644 --- a/usr/src/boot/sys/boot/libficl/amd64/Makefile +++ b/usr/src/boot/sys/boot/libficl/amd64/Makefile @@ -22,7 +22,7 @@ all install: lib include ../Makefile.com -CFLAGS += -m64 -mno-red-zone +CFLAGS += -m64 $(CFLAGS64) $(OBJECTS): machine x86 diff --git a/usr/src/boot/sys/boot/libstand/Makefile b/usr/src/boot/sys/boot/libstand/Makefile index b45ddb2f97..f4ea4e68e6 100644 --- a/usr/src/boot/sys/boot/libstand/Makefile +++ b/usr/src/boot/sys/boot/libstand/Makefile @@ -28,6 +28,8 @@ all clean clobber: $(SUBDIRS) install: all +.PARALLEL: + $(SUBDIRS): FRC @cd $@; pwd; $(MAKE) $(MFLAGS) $(TARGET) diff --git a/usr/src/boot/sys/boot/libstand/Makefile.com b/usr/src/boot/sys/boot/libstand/Makefile.com index 53b165a230..14be719770 100644 --- a/usr/src/boot/sys/boot/libstand/Makefile.com +++ b/usr/src/boot/sys/boot/libstand/Makefile.com @@ -14,27 +14,18 @@ # include $(SRC)/Makefile.master +include $(SRC)/boot/sys/boot/Makefile.inc -AS= $(GNU_ROOT)/bin/gas -LD= $(GNU_ROOT)/bin/gld -CC= $(GNUC_ROOT)/bin/gcc - -LIB_BASE= $(SRC)/boot/lib -LIBSTAND_SRC= $(LIB_BASE)/libstand - -ASFLAGS = -fPIC -CPPFLAGS = -nostdinc -I../../../../include -I$(LIBSTAND_SRC) -CPPFLAGS += -I../../.. -I../../../sys -I. -I$(SRC)/common/bzip2 -CPPFLAGS += -D_STANDALONE - -CFLAGS = -Os -fPIC -ffreestanding -Wformat -CFLAGS += -mno-mmx -mno-3dnow -mno-sse -mno-sse2 -mno-sse3 -msoft-float -CFLAGS += -Wall -Werror +CPPFLAGS += -I../../../../include -I$(SASRC) +CPPFLAGS += -I../../.. -I. -I$(SRC)/common/bzip2 $(LIBRARY): $(SRCS) $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) -include $(LIBSTAND_SRC)/Makefile.inc +include $(SASRC)/Makefile.inc +include $(ZFSSRC)/Makefile.inc + +CPPFLAGS += -I$(SRC)/uts/common clean: clobber clobber: @@ -48,17 +39,17 @@ x86: $(RM) x86 $(SYMLINK) ../../../x86/include x86 -%.o: $(LIBSTAND_SRC)/%.c +%.o: $(SASRC)/%.c $(COMPILE.c) $< -%.o: $(LIB_BASE)/libc/net/%.c +%.o: $(LIBSRC)/libc/net/%.c $(COMPILE.c) $< -%.o: $(LIB_BASE)/libc/string/%.c +%.o: $(LIBSRC)/libc/string/%.c $(COMPILE.c) $< -%.o: $(LIB_BASE)/libc/uuid/%.c +%.o: $(LIBSRC)/libc/uuid/%.c $(COMPILE.c) $< -%.o: $(LIB_BASE)/libz/%.c +%.o: $(LIBSRC)/libz/%.c $(COMPILE.c) $< diff --git a/usr/src/boot/sys/boot/libstand/amd64/Makefile b/usr/src/boot/sys/boot/libstand/amd64/Makefile index de2359271f..2171bc866b 100644 --- a/usr/src/boot/sys/boot/libstand/amd64/Makefile +++ b/usr/src/boot/sys/boot/libstand/amd64/Makefile @@ -21,18 +21,18 @@ all install: $(LIBRARY) include ../Makefile.com -CFLAGS += -m64 -mno-red-zone -ASFLAGS += -m64 +CFLAGS += -m64 $(CFLAGS64) +CCASFLAGS += -m64 CLEANFILES += x86 # _setjmp/_longjmp -SRCS += $(LIBSTAND_SRC)/amd64/_setjmp.S +SRCS += $(SASRC)/amd64/_setjmp.S OBJS += _setjmp.o $(LIBRARY): $(SRCS) $(OBJS) $(OBJS): machine x86 -%.o: $(LIBSTAND_SRC)/amd64/%.S +%.o: $(SASRC)/amd64/%.S $(COMPILE.S) $< diff --git a/usr/src/boot/sys/boot/libstand/i386/Makefile b/usr/src/boot/sys/boot/libstand/i386/Makefile index 8a26d7bc40..76ba41c582 100644 --- a/usr/src/boot/sys/boot/libstand/i386/Makefile +++ b/usr/src/boot/sys/boot/libstand/i386/Makefile @@ -27,12 +27,12 @@ ASFLAGS += -m32 CLEANFILES += x86 # _setjmp/_longjmp -SRCS += $(LIBSTAND_SRC)/i386/_setjmp.S +SRCS += $(SASRC)/i386/_setjmp.S OBJS += _setjmp.o $(LIBRARY): $(SRCS) $(OBJS) $(OBJS): machine x86 -%.o: $(LIBSTAND_SRC)/i386/%.S +%.o: $(SASRC)/i386/%.S $(COMPILE.S) $< diff --git a/usr/src/boot/sys/boot/zfs/Makefile b/usr/src/boot/sys/boot/zfs/Makefile deleted file mode 100644 index 660b8e3485..0000000000 --- a/usr/src/boot/sys/boot/zfs/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -# -# This file and its contents are supplied under the terms of the -# Common Development and Distribution License ("CDDL"), version 1.0. -# You may only use this file in accordance with the terms of version -# 1.0 of the CDDL. -# -# A full copy of the text of the CDDL should have accompanied this -# source. A copy of the CDDL is also available via the Internet at -# http://www.illumos.org/license/CDDL. -# - -# -# Copyright 2016 Toomas Soome <tsoome@me.com> -# - -include $(SRC)/Makefile.master - -SUBDIRS= $(MACH) $(MACH64) - -all:= TARGET= all -install:= TARGET= install -clean:= TARGET= clean -clobber:= TARGET= clobber - -.KEEP_STATE: - -all clean clobber: $(SUBDIRS) - -install: $(SUBDIRS) - -FRC: - -$(SUBDIRS): FRC - @cd $@; pwd; $(MAKE) $(TARGET) diff --git a/usr/src/boot/sys/boot/zfs/Makefile.com b/usr/src/boot/sys/boot/zfs/Makefile.com deleted file mode 100644 index a9bef1e23b..0000000000 --- a/usr/src/boot/sys/boot/zfs/Makefile.com +++ /dev/null @@ -1,73 +0,0 @@ -# -# This file and its contents are supplied under the terms of the -# Common Development and Distribution License ("CDDL"), version 1.0. -# You may only use this file in accordance with the terms of version -# 1.0 of the CDDL. -# -# A full copy of the text of the CDDL should have accompanied this -# source. A copy of the CDDL is also available via the Internet at -# http://www.illumos.org/license/CDDL. -# - -# -# Copyright 2016 Toomas Soome <tsoome@me.com> -# - -include $(SRC)/Makefile.master - -LIB= zfsboot - -clean: clobber - -clobber: - $(RM) machine x86 $(OBJS) libzfsboot.a - -CC= $(GNUC_ROOT)/bin/gcc - -CFLAGS= -Os -CFLAGS += -fPIC -ffreestanding -msoft-float -CFLAGS += -mno-mmx -mno-3dnow -mno-sse2 -mno-sse3 -mno-sse -CFLAGS += -mno-avx -mno-aes -std=gnu99 - -SRCS += $(SRC)/boot/sys/boot/zfs/zfs.c $(SRC)/boot/sys/boot/zfs/gzip.c -SRCS += $(SRC)/common/crypto/edonr/edonr.c -SRCS += $(SRC)/common/crypto/skein/skein.c -SRCS += $(SRC)/common/crypto/skein/skein_iv.c -SRCS += $(SRC)/common/crypto/skein/skein_block.c -OBJS += zfs.o gzip.o edonr.o skein.o skein_iv.o skein_block.o - -CPPFLAGS= -D_STANDALONE -nostdinc -I../../../../include -I../.. -CPPFLAGS += -I../../common -I../../.. -I.. -I. -CPPFLAGS += -I../../../../lib/libstand -CPPFLAGS += -I../../../../lib/libz -CPPFLAGS += -I../../../cddl/boot/zfs -CPPFLAGS += -I$(SRC)/uts/common - -# Do not unroll skein loops, reduce code size -CPPFLAGS += -DSKEIN_LOOP=111 - -#include ../../Makefile.inc - -CLEANFILES += machine - -machine: - $(RM) machine - $(SYMLINK) ../../../$(MACHINE)/include machine - -x86: - $(RM) x86 - $(SYMLINK) ../../../x86/include x86 - -libzfsboot.a: $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -%.o: $(SRC)/boot/sys/boot/zfs/%.c - $(COMPILE.c) -o $@ $< - -%.o: $(SRC)/common/crypto/edonr/%.c - $(COMPILE.c) -o $@ $< - -%.o: $(SRC)/common/crypto/skein/%.c - $(COMPILE.c) -o $@ $< - -zfs.o: $(SRC)/boot/sys/boot/zfs/zfsimpl.c diff --git a/usr/src/boot/sys/boot/zfs/amd64/Makefile b/usr/src/boot/sys/boot/zfs/amd64/Makefile deleted file mode 100644 index da13c92b13..0000000000 --- a/usr/src/boot/sys/boot/zfs/amd64/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# -# This file and its contents are supplied under the terms of the -# Common Development and Distribution License ("CDDL"), version 1.0. -# You may only use this file in accordance with the terms of version -# 1.0 of the CDDL. -# -# A full copy of the text of the CDDL should have accompanied this -# source. A copy of the CDDL is also available via the Internet at -# http://www.illumos.org/license/CDDL. -# - -# -# Copyright 2016 Toomas Soome <tsoome@me.com> -# Copyright 2016 RackTop Systems. -# - -MACHINE= $(MACH64) - -all install: libzfsboot.a - -include ../Makefile.com - -CLEANFILES += x86 -CFLAGS += -mno-red-zone -m64 - -$(OBJS): machine x86 diff --git a/usr/src/boot/sys/sys/mount.h b/usr/src/boot/sys/sys/mount.h deleted file mode 100644 index f11f8f5389..0000000000 --- a/usr/src/boot/sys/sys/mount.h +++ /dev/null @@ -1,949 +0,0 @@ -/*- - * Copyright (c) 1989, 1991, 1993 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)mount.h 8.21 (Berkeley) 5/20/95 - * $FreeBSD$ - */ - -#ifndef _SYS_MOUNT_H_ -#define _SYS_MOUNT_H_ - -#include <sys/ucred.h> -#include <sys/queue.h> -#ifdef _KERNEL -#include <sys/lock.h> -#include <sys/lockmgr.h> -#include <sys/_mutex.h> -#include <sys/_sx.h> -#endif - -/* - * NOTE: When changing statfs structure, mount structure, MNT_* flags or - * MNTK_* flags also update DDB show mount command in vfs_subr.c. - */ - -typedef struct fsid { int32_t val[2]; } fsid_t; /* filesystem id type */ - -/* - * File identifier. - * These are unique per filesystem on a single machine. - */ -#define MAXFIDSZ 16 - -struct fid { - u_short fid_len; /* length of data in bytes */ - u_short fid_data0; /* force longword alignment */ - char fid_data[MAXFIDSZ]; /* data (variable length) */ -}; - -/* - * filesystem statistics - */ -#define MFSNAMELEN 16 /* length of type name including null */ -#define MNAMELEN 88 /* size of on/from name bufs */ -#define STATFS_VERSION 0x20030518 /* current version number */ -struct statfs { - uint32_t f_version; /* structure version number */ - uint32_t f_type; /* type of filesystem */ - uint64_t f_flags; /* copy of mount exported flags */ - uint64_t f_bsize; /* filesystem fragment size */ - uint64_t f_iosize; /* optimal transfer block size */ - uint64_t f_blocks; /* total data blocks in filesystem */ - uint64_t f_bfree; /* free blocks in filesystem */ - int64_t f_bavail; /* free blocks avail to non-superuser */ - uint64_t f_files; /* total file nodes in filesystem */ - int64_t f_ffree; /* free nodes avail to non-superuser */ - uint64_t f_syncwrites; /* count of sync writes since mount */ - uint64_t f_asyncwrites; /* count of async writes since mount */ - uint64_t f_syncreads; /* count of sync reads since mount */ - uint64_t f_asyncreads; /* count of async reads since mount */ - uint64_t f_spare[10]; /* unused spare */ - uint32_t f_namemax; /* maximum filename length */ - uid_t f_owner; /* user that mounted the filesystem */ - fsid_t f_fsid; /* filesystem id */ - char f_charspare[80]; /* spare string space */ - char f_fstypename[MFSNAMELEN]; /* filesystem type name */ - char f_mntfromname[MNAMELEN]; /* mounted filesystem */ - char f_mntonname[MNAMELEN]; /* directory on which mounted */ -}; - -#ifdef _KERNEL -#define OMFSNAMELEN 16 /* length of fs type name, including null */ -#define OMNAMELEN (88 - 2 * sizeof(long)) /* size of on/from name bufs */ - -/* XXX getfsstat.2 is out of date with write and read counter changes here. */ -/* XXX statfs.2 is out of date with read counter changes here. */ -struct ostatfs { - long f_spare2; /* placeholder */ - long f_bsize; /* fundamental filesystem block size */ - long f_iosize; /* optimal transfer block size */ - long f_blocks; /* total data blocks in filesystem */ - long f_bfree; /* free blocks in fs */ - long f_bavail; /* free blocks avail to non-superuser */ - long f_files; /* total file nodes in filesystem */ - long f_ffree; /* free file nodes in fs */ - fsid_t f_fsid; /* filesystem id */ - uid_t f_owner; /* user that mounted the filesystem */ - int f_type; /* type of filesystem */ - int f_flags; /* copy of mount exported flags */ - long f_syncwrites; /* count of sync writes since mount */ - long f_asyncwrites; /* count of async writes since mount */ - char f_fstypename[OMFSNAMELEN]; /* fs type name */ - char f_mntonname[OMNAMELEN]; /* directory on which mounted */ - long f_syncreads; /* count of sync reads since mount */ - long f_asyncreads; /* count of async reads since mount */ - short f_spares1; /* unused spare */ - char f_mntfromname[OMNAMELEN];/* mounted filesystem */ - short f_spares2; /* unused spare */ - /* - * XXX on machines where longs are aligned to 8-byte boundaries, there - * is an unnamed int32_t here. This spare was after the apparent end - * of the struct until we bit off the read counters from f_mntonname. - */ - long f_spare[2]; /* unused spare */ -}; - -TAILQ_HEAD(vnodelst, vnode); - -/* Mount options list */ -TAILQ_HEAD(vfsoptlist, vfsopt); -struct vfsopt { - TAILQ_ENTRY(vfsopt) link; - char *name; - void *value; - int len; - int pos; - int seen; -}; - -/* - * Structure per mounted filesystem. Each mounted filesystem has an - * array of operations and an instance record. The filesystems are - * put on a doubly linked list. - * - * Lock reference: - * m - mountlist_mtx - * i - interlock - * v - vnode freelist mutex - * - * Unmarked fields are considered stable as long as a ref is held. - * - */ -struct mount { - struct mtx mnt_mtx; /* mount structure interlock */ - int mnt_gen; /* struct mount generation */ -#define mnt_startzero mnt_list - TAILQ_ENTRY(mount) mnt_list; /* (m) mount list */ - struct vfsops *mnt_op; /* operations on fs */ - struct vfsconf *mnt_vfc; /* configuration info */ - struct vnode *mnt_vnodecovered; /* vnode we mounted on */ - struct vnode *mnt_syncer; /* syncer vnode */ - int mnt_ref; /* (i) Reference count */ - struct vnodelst mnt_nvnodelist; /* (i) list of vnodes */ - int mnt_nvnodelistsize; /* (i) # of vnodes */ - struct vnodelst mnt_activevnodelist; /* (v) list of active vnodes */ - int mnt_activevnodelistsize;/* (v) # of active vnodes */ - int mnt_writeopcount; /* (i) write syscalls pending */ - int mnt_kern_flag; /* (i) kernel only flags */ - uint64_t mnt_flag; /* (i) flags shared with user */ - struct vfsoptlist *mnt_opt; /* current mount options */ - struct vfsoptlist *mnt_optnew; /* new options passed to fs */ - int mnt_maxsymlinklen; /* max size of short symlink */ - struct statfs mnt_stat; /* cache of filesystem stats */ - struct ucred *mnt_cred; /* credentials of mounter */ - void * mnt_data; /* private data */ - time_t mnt_time; /* last time written*/ - int mnt_iosize_max; /* max size for clusters, etc */ - struct netexport *mnt_export; /* export list */ - struct label *mnt_label; /* MAC label for the fs */ - u_int mnt_hashseed; /* Random seed for vfs_hash */ - int mnt_lockref; /* (i) Lock reference count */ - int mnt_secondary_writes; /* (i) # of secondary writes */ - int mnt_secondary_accwrites;/* (i) secondary wr. starts */ - struct thread *mnt_susp_owner; /* (i) thread owning suspension */ -#define mnt_endzero mnt_gjprovider - char *mnt_gjprovider; /* gjournal provider name */ - struct lock mnt_explock; /* vfs_export walkers lock */ - TAILQ_ENTRY(mount) mnt_upper_link; /* (m) we in the all uppers */ - TAILQ_HEAD(, mount) mnt_uppers; /* (m) upper mounts over us*/ -}; - -/* - * Definitions for MNT_VNODE_FOREACH_ALL. - */ -struct vnode *__mnt_vnode_next_all(struct vnode **mvp, struct mount *mp); -struct vnode *__mnt_vnode_first_all(struct vnode **mvp, struct mount *mp); -void __mnt_vnode_markerfree_all(struct vnode **mvp, struct mount *mp); - -#define MNT_VNODE_FOREACH_ALL(vp, mp, mvp) \ - for (vp = __mnt_vnode_first_all(&(mvp), (mp)); \ - (vp) != NULL; vp = __mnt_vnode_next_all(&(mvp), (mp))) - -#define MNT_VNODE_FOREACH_ALL_ABORT(mp, mvp) \ - do { \ - MNT_ILOCK(mp); \ - __mnt_vnode_markerfree_all(&(mvp), (mp)); \ - /* MNT_IUNLOCK(mp); -- done in above function */ \ - mtx_assert(MNT_MTX(mp), MA_NOTOWNED); \ - } while (0) - -/* - * Definitions for MNT_VNODE_FOREACH_ACTIVE. - */ -struct vnode *__mnt_vnode_next_active(struct vnode **mvp, struct mount *mp); -struct vnode *__mnt_vnode_first_active(struct vnode **mvp, struct mount *mp); -void __mnt_vnode_markerfree_active(struct vnode **mvp, struct mount *); - -#define MNT_VNODE_FOREACH_ACTIVE(vp, mp, mvp) \ - for (vp = __mnt_vnode_first_active(&(mvp), (mp)); \ - (vp) != NULL; vp = __mnt_vnode_next_active(&(mvp), (mp))) - -#define MNT_VNODE_FOREACH_ACTIVE_ABORT(mp, mvp) \ - __mnt_vnode_markerfree_active(&(mvp), (mp)) - -#define MNT_ILOCK(mp) mtx_lock(&(mp)->mnt_mtx) -#define MNT_ITRYLOCK(mp) mtx_trylock(&(mp)->mnt_mtx) -#define MNT_IUNLOCK(mp) mtx_unlock(&(mp)->mnt_mtx) -#define MNT_MTX(mp) (&(mp)->mnt_mtx) -#define MNT_REF(mp) (mp)->mnt_ref++ -#define MNT_REL(mp) do { \ - KASSERT((mp)->mnt_ref > 0, ("negative mnt_ref")); \ - (mp)->mnt_ref--; \ - if ((mp)->mnt_ref == 0) \ - wakeup((mp)); \ -} while (0) - -#endif /* _KERNEL */ - -/* - * User specifiable flags, stored in mnt_flag. - */ -#define MNT_RDONLY 0x0000000000000001ULL /* read only filesystem */ -#define MNT_SYNCHRONOUS 0x0000000000000002ULL /* fs written synchronously */ -#define MNT_NOEXEC 0x0000000000000004ULL /* can't exec from filesystem */ -#define MNT_NOSUID 0x0000000000000008ULL /* don't honor setuid fs bits */ -#define MNT_NFS4ACLS 0x0000000000000010ULL /* enable NFS version 4 ACLs */ -#define MNT_UNION 0x0000000000000020ULL /* union with underlying fs */ -#define MNT_ASYNC 0x0000000000000040ULL /* fs written asynchronously */ -#define MNT_SUIDDIR 0x0000000000100000ULL /* special SUID dir handling */ -#define MNT_SOFTDEP 0x0000000000200000ULL /* using soft updates */ -#define MNT_NOSYMFOLLOW 0x0000000000400000ULL /* do not follow symlinks */ -#define MNT_GJOURNAL 0x0000000002000000ULL /* GEOM journal support enabled */ -#define MNT_MULTILABEL 0x0000000004000000ULL /* MAC support for objects */ -#define MNT_ACLS 0x0000000008000000ULL /* ACL support enabled */ -#define MNT_NOATIME 0x0000000010000000ULL /* dont update file access time */ -#define MNT_NOCLUSTERR 0x0000000040000000ULL /* disable cluster read */ -#define MNT_NOCLUSTERW 0x0000000080000000ULL /* disable cluster write */ -#define MNT_SUJ 0x0000000100000000ULL /* using journaled soft updates */ -#define MNT_AUTOMOUNTED 0x0000000200000000ULL /* mounted by automountd(8) */ - -/* - * NFS export related mount flags. - */ -#define MNT_EXRDONLY 0x0000000000000080ULL /* exported read only */ -#define MNT_EXPORTED 0x0000000000000100ULL /* filesystem is exported */ -#define MNT_DEFEXPORTED 0x0000000000000200ULL /* exported to the world */ -#define MNT_EXPORTANON 0x0000000000000400ULL /* anon uid mapping for all */ -#define MNT_EXKERB 0x0000000000000800ULL /* exported with Kerberos */ -#define MNT_EXPUBLIC 0x0000000020000000ULL /* public export (WebNFS) */ - -/* - * Flags set by internal operations, - * but visible to the user. - * XXX some of these are not quite right.. (I've never seen the root flag set) - */ -#define MNT_LOCAL 0x0000000000001000ULL /* filesystem is stored locally */ -#define MNT_QUOTA 0x0000000000002000ULL /* quotas are enabled on fs */ -#define MNT_ROOTFS 0x0000000000004000ULL /* identifies the root fs */ -#define MNT_USER 0x0000000000008000ULL /* mounted by a user */ -#define MNT_IGNORE 0x0000000000800000ULL /* do not show entry in df */ - -/* - * Mask of flags that are visible to statfs(). - * XXX I think that this could now become (~(MNT_CMDFLAGS)) - * but the 'mount' program may need changing to handle this. - */ -#define MNT_VISFLAGMASK (MNT_RDONLY | MNT_SYNCHRONOUS | MNT_NOEXEC | \ - MNT_NOSUID | MNT_UNION | MNT_SUJ | \ - MNT_ASYNC | MNT_EXRDONLY | MNT_EXPORTED | \ - MNT_DEFEXPORTED | MNT_EXPORTANON| MNT_EXKERB | \ - MNT_LOCAL | MNT_USER | MNT_QUOTA | \ - MNT_ROOTFS | MNT_NOATIME | MNT_NOCLUSTERR| \ - MNT_NOCLUSTERW | MNT_SUIDDIR | MNT_SOFTDEP | \ - MNT_IGNORE | MNT_EXPUBLIC | MNT_NOSYMFOLLOW | \ - MNT_GJOURNAL | MNT_MULTILABEL | MNT_ACLS | \ - MNT_NFS4ACLS | MNT_AUTOMOUNTED) - -/* Mask of flags that can be updated. */ -#define MNT_UPDATEMASK (MNT_NOSUID | MNT_NOEXEC | \ - MNT_SYNCHRONOUS | MNT_UNION | MNT_ASYNC | \ - MNT_NOATIME | \ - MNT_NOSYMFOLLOW | MNT_IGNORE | \ - MNT_NOCLUSTERR | MNT_NOCLUSTERW | MNT_SUIDDIR | \ - MNT_ACLS | MNT_USER | MNT_NFS4ACLS | \ - MNT_AUTOMOUNTED) - -/* - * External filesystem command modifier flags. - * Unmount can use the MNT_FORCE flag. - * XXX: These are not STATES and really should be somewhere else. - * XXX: MNT_BYFSID collides with MNT_ACLS, but because MNT_ACLS is only used for - * mount(2) and MNT_BYFSID is only used for unmount(2) it's harmless. - */ -#define MNT_UPDATE 0x0000000000010000ULL /* not real mount, just update */ -#define MNT_DELEXPORT 0x0000000000020000ULL /* delete export host lists */ -#define MNT_RELOAD 0x0000000000040000ULL /* reload filesystem data */ -#define MNT_FORCE 0x0000000000080000ULL /* force unmount or readonly */ -#define MNT_SNAPSHOT 0x0000000001000000ULL /* snapshot the filesystem */ -#define MNT_BYFSID 0x0000000008000000ULL /* specify filesystem by ID. */ -#define MNT_CMDFLAGS (MNT_UPDATE | MNT_DELEXPORT | MNT_RELOAD | \ - MNT_FORCE | MNT_SNAPSHOT | MNT_BYFSID) -/* - * Internal filesystem control flags stored in mnt_kern_flag. - * - * MNTK_UNMOUNT locks the mount entry so that name lookup cannot proceed - * past the mount point. This keeps the subtree stable during mounts - * and unmounts. - * - * MNTK_UNMOUNTF permits filesystems to detect a forced unmount while - * dounmount() is still waiting to lock the mountpoint. This allows - * the filesystem to cancel operations that might otherwise deadlock - * with the unmount attempt (used by NFS). - * - * MNTK_NOINSMNTQ is strict subset of MNTK_UNMOUNT. They are separated - * to allow for failed unmount attempt to restore the syncer vnode for - * the mount. - */ -#define MNTK_UNMOUNTF 0x00000001 /* forced unmount in progress */ -#define MNTK_ASYNC 0x00000002 /* filtered async flag */ -#define MNTK_SOFTDEP 0x00000004 /* async disabled by softdep */ -#define MNTK_NOINSMNTQ 0x00000008 /* insmntque is not allowed */ -#define MNTK_DRAINING 0x00000010 /* lock draining is happening */ -#define MNTK_REFEXPIRE 0x00000020 /* refcount expiring is happening */ -#define MNTK_EXTENDED_SHARED 0x00000040 /* Allow shared locking for more ops */ -#define MNTK_SHARED_WRITES 0x00000080 /* Allow shared locking for writes */ -#define MNTK_NO_IOPF 0x00000100 /* Disallow page faults during reads - and writes. Filesystem shall properly - handle i/o state on EFAULT. */ -#define MNTK_VGONE_UPPER 0x00000200 -#define MNTK_VGONE_WAITER 0x00000400 -#define MNTK_LOOKUP_EXCL_DOTDOT 0x00000800 -#define MNTK_MARKER 0x00001000 -#define MNTK_UNMAPPED_BUFS 0x00002000 -#define MNTK_USES_BCACHE 0x00004000 /* FS uses the buffer cache. */ -#define MNTK_NOASYNC 0x00800000 /* disable async */ -#define MNTK_UNMOUNT 0x01000000 /* unmount in progress */ -#define MNTK_MWAIT 0x02000000 /* waiting for unmount to finish */ -#define MNTK_SUSPEND 0x08000000 /* request write suspension */ -#define MNTK_SUSPEND2 0x04000000 /* block secondary writes */ -#define MNTK_SUSPENDED 0x10000000 /* write operations are suspended */ -#define MNTK_UNUSED1 0x20000000 -#define MNTK_LOOKUP_SHARED 0x40000000 /* FS supports shared lock lookups */ -#define MNTK_NOKNOTE 0x80000000 /* Don't send KNOTEs from VOP hooks */ - -#ifdef _KERNEL -static inline int -MNT_SHARED_WRITES(struct mount *mp) -{ - - return (mp != NULL && (mp->mnt_kern_flag & MNTK_SHARED_WRITES) != 0); -} - -static inline int -MNT_EXTENDED_SHARED(struct mount *mp) -{ - - return (mp != NULL && (mp->mnt_kern_flag & MNTK_EXTENDED_SHARED) != 0); -} -#endif - -/* - * Sysctl CTL_VFS definitions. - * - * Second level identifier specifies which filesystem. Second level - * identifier VFS_VFSCONF returns information about all filesystems. - * Second level identifier VFS_GENERIC is non-terminal. - */ -#define VFS_VFSCONF 0 /* get configured filesystems */ -#define VFS_GENERIC 0 /* generic filesystem information */ -/* - * Third level identifiers for VFS_GENERIC are given below; third - * level identifiers for specific filesystems are given in their - * mount specific header files. - */ -#define VFS_MAXTYPENUM 1 /* int: highest defined filesystem type */ -#define VFS_CONF 2 /* struct: vfsconf for filesystem given - as next argument */ - -/* - * Flags for various system call interfaces. - * - * waitfor flags to vfs_sync() and getfsstat() - */ -#define MNT_WAIT 1 /* synchronously wait for I/O to complete */ -#define MNT_NOWAIT 2 /* start all I/O, but do not wait for it */ -#define MNT_LAZY 3 /* push data not written by filesystem syncer */ -#define MNT_SUSPEND 4 /* Suspend file system after sync */ - -/* - * Generic file handle - */ -struct fhandle { - fsid_t fh_fsid; /* Filesystem id of mount point */ - struct fid fh_fid; /* Filesys specific id */ -}; -typedef struct fhandle fhandle_t; - -/* - * Old export arguments without security flavor list - */ -struct oexport_args { - int ex_flags; /* export related flags */ - uid_t ex_root; /* mapping for root uid */ - struct xucred ex_anon; /* mapping for anonymous user */ - struct sockaddr *ex_addr; /* net address to which exported */ - u_char ex_addrlen; /* and the net address length */ - struct sockaddr *ex_mask; /* mask of valid bits in saddr */ - u_char ex_masklen; /* and the smask length */ - char *ex_indexfile; /* index file for WebNFS URLs */ -}; - -/* - * Export arguments for local filesystem mount calls. - */ -#define MAXSECFLAVORS 5 -struct export_args { - int ex_flags; /* export related flags */ - uid_t ex_root; /* mapping for root uid */ - struct xucred ex_anon; /* mapping for anonymous user */ - struct sockaddr *ex_addr; /* net address to which exported */ - u_char ex_addrlen; /* and the net address length */ - struct sockaddr *ex_mask; /* mask of valid bits in saddr */ - u_char ex_masklen; /* and the smask length */ - char *ex_indexfile; /* index file for WebNFS URLs */ - int ex_numsecflavors; /* security flavor count */ - int ex_secflavors[MAXSECFLAVORS]; /* list of security flavors */ -}; - -/* - * Structure holding information for a publicly exported filesystem - * (WebNFS). Currently the specs allow just for one such filesystem. - */ -struct nfs_public { - int np_valid; /* Do we hold valid information */ - fhandle_t np_handle; /* Filehandle for pub fs (internal) */ - struct mount *np_mount; /* Mountpoint of exported fs */ - char *np_index; /* Index file */ -}; - -/* - * Filesystem configuration information. One of these exists for each - * type of filesystem supported by the kernel. These are searched at - * mount time to identify the requested filesystem. - * - * XXX: Never change the first two arguments! - */ -struct vfsconf { - u_int vfc_version; /* ABI version number */ - char vfc_name[MFSNAMELEN]; /* filesystem type name */ - struct vfsops *vfc_vfsops; /* filesystem operations vector */ - int vfc_typenum; /* historic filesystem type number */ - int vfc_refcount; /* number mounted of this type */ - int vfc_flags; /* permanent flags */ - struct vfsoptdecl *vfc_opts; /* mount options */ - TAILQ_ENTRY(vfsconf) vfc_list; /* list of vfscons */ -}; - -/* Userland version of the struct vfsconf. */ -struct xvfsconf { - struct vfsops *vfc_vfsops; /* filesystem operations vector */ - char vfc_name[MFSNAMELEN]; /* filesystem type name */ - int vfc_typenum; /* historic filesystem type number */ - int vfc_refcount; /* number mounted of this type */ - int vfc_flags; /* permanent flags */ - struct vfsconf *vfc_next; /* next in list */ -}; - -#ifndef BURN_BRIDGES -struct ovfsconf { - void *vfc_vfsops; - char vfc_name[32]; - int vfc_index; - int vfc_refcount; - int vfc_flags; -}; -#endif - -/* - * NB: these flags refer to IMPLEMENTATION properties, not properties of - * any actual mounts; i.e., it does not make sense to change the flags. - */ -#define VFCF_STATIC 0x00010000 /* statically compiled into kernel */ -#define VFCF_NETWORK 0x00020000 /* may get data over the network */ -#define VFCF_READONLY 0x00040000 /* writes are not implemented */ -#define VFCF_SYNTHETIC 0x00080000 /* data does not represent real files */ -#define VFCF_LOOPBACK 0x00100000 /* aliases some other mounted FS */ -#define VFCF_UNICODE 0x00200000 /* stores file names as Unicode */ -#define VFCF_JAIL 0x00400000 /* can be mounted from within a jail */ -#define VFCF_DELEGADMIN 0x00800000 /* supports delegated administration */ -#define VFCF_SBDRY 0x01000000 /* defer stop requests */ - -typedef uint32_t fsctlop_t; - -struct vfsidctl { - int vc_vers; /* should be VFSIDCTL_VERS1 (below) */ - fsid_t vc_fsid; /* fsid to operate on */ - char vc_fstypename[MFSNAMELEN]; - /* type of fs 'nfs' or '*' */ - fsctlop_t vc_op; /* operation VFS_CTL_* (below) */ - void *vc_ptr; /* pointer to data structure */ - size_t vc_len; /* sizeof said structure */ - u_int32_t vc_spare[12]; /* spare (must be zero) */ -}; - -/* vfsidctl API version. */ -#define VFS_CTL_VERS1 0x01 - -/* - * New style VFS sysctls, do not reuse/conflict with the namespace for - * private sysctls. - * All "global" sysctl ops have the 33rd bit set: - * 0x...1.... - * Private sysctl ops should have the 33rd bit unset. - */ -#define VFS_CTL_QUERY 0x00010001 /* anything wrong? (vfsquery) */ -#define VFS_CTL_TIMEO 0x00010002 /* set timeout for vfs notification */ -#define VFS_CTL_NOLOCKS 0x00010003 /* disable file locking */ - -struct vfsquery { - u_int32_t vq_flags; - u_int32_t vq_spare[31]; -}; - -/* vfsquery flags */ -#define VQ_NOTRESP 0x0001 /* server down */ -#define VQ_NEEDAUTH 0x0002 /* server bad auth */ -#define VQ_LOWDISK 0x0004 /* we're low on space */ -#define VQ_MOUNT 0x0008 /* new filesystem arrived */ -#define VQ_UNMOUNT 0x0010 /* filesystem has left */ -#define VQ_DEAD 0x0020 /* filesystem is dead, needs force unmount */ -#define VQ_ASSIST 0x0040 /* filesystem needs assistance from external - program */ -#define VQ_NOTRESPLOCK 0x0080 /* server lockd down */ -#define VQ_FLAG0100 0x0100 /* placeholder */ -#define VQ_FLAG0200 0x0200 /* placeholder */ -#define VQ_FLAG0400 0x0400 /* placeholder */ -#define VQ_FLAG0800 0x0800 /* placeholder */ -#define VQ_FLAG1000 0x1000 /* placeholder */ -#define VQ_FLAG2000 0x2000 /* placeholder */ -#define VQ_FLAG4000 0x4000 /* placeholder */ -#define VQ_FLAG8000 0x8000 /* placeholder */ - -#ifdef _KERNEL -/* Point a sysctl request at a vfsidctl's data. */ -#define VCTLTOREQ(vc, req) \ - do { \ - (req)->newptr = (vc)->vc_ptr; \ - (req)->newlen = (vc)->vc_len; \ - (req)->newidx = 0; \ - } while (0) -#endif - -struct iovec; -struct uio; - -#ifdef _KERNEL - -/* - * vfs_busy specific flags and mask. - */ -#define MBF_NOWAIT 0x01 -#define MBF_MNTLSTLOCK 0x02 -#define MBF_MASK (MBF_NOWAIT | MBF_MNTLSTLOCK) - -#ifdef MALLOC_DECLARE -MALLOC_DECLARE(M_MOUNT); -#endif -extern int maxvfsconf; /* highest defined filesystem type */ - -TAILQ_HEAD(vfsconfhead, vfsconf); -extern struct vfsconfhead vfsconf; - -/* - * Operations supported on mounted filesystem. - */ -struct mount_args; -struct nameidata; -struct sysctl_req; -struct mntarg; - -typedef int vfs_cmount_t(struct mntarg *ma, void *data, uint64_t flags); -typedef int vfs_unmount_t(struct mount *mp, int mntflags); -typedef int vfs_root_t(struct mount *mp, int flags, struct vnode **vpp); -typedef int vfs_quotactl_t(struct mount *mp, int cmds, uid_t uid, void *arg); -typedef int vfs_statfs_t(struct mount *mp, struct statfs *sbp); -typedef int vfs_sync_t(struct mount *mp, int waitfor); -typedef int vfs_vget_t(struct mount *mp, ino_t ino, int flags, - struct vnode **vpp); -typedef int vfs_fhtovp_t(struct mount *mp, struct fid *fhp, - int flags, struct vnode **vpp); -typedef int vfs_checkexp_t(struct mount *mp, struct sockaddr *nam, - int *extflagsp, struct ucred **credanonp, - int *numsecflavors, int **secflavors); -typedef int vfs_init_t(struct vfsconf *); -typedef int vfs_uninit_t(struct vfsconf *); -typedef int vfs_extattrctl_t(struct mount *mp, int cmd, - struct vnode *filename_vp, int attrnamespace, - const char *attrname); -typedef int vfs_mount_t(struct mount *mp); -typedef int vfs_sysctl_t(struct mount *mp, fsctlop_t op, - struct sysctl_req *req); -typedef void vfs_susp_clean_t(struct mount *mp); -typedef void vfs_notify_lowervp_t(struct mount *mp, struct vnode *lowervp); -typedef void vfs_purge_t(struct mount *mp); - -struct vfsops { - vfs_mount_t *vfs_mount; - vfs_cmount_t *vfs_cmount; - vfs_unmount_t *vfs_unmount; - vfs_root_t *vfs_root; - vfs_quotactl_t *vfs_quotactl; - vfs_statfs_t *vfs_statfs; - vfs_sync_t *vfs_sync; - vfs_vget_t *vfs_vget; - vfs_fhtovp_t *vfs_fhtovp; - vfs_checkexp_t *vfs_checkexp; - vfs_init_t *vfs_init; - vfs_uninit_t *vfs_uninit; - vfs_extattrctl_t *vfs_extattrctl; - vfs_sysctl_t *vfs_sysctl; - vfs_susp_clean_t *vfs_susp_clean; - vfs_notify_lowervp_t *vfs_reclaim_lowervp; - vfs_notify_lowervp_t *vfs_unlink_lowervp; - vfs_purge_t *vfs_purge; - vfs_mount_t *vfs_spare[6]; /* spares for ABI compat */ -}; - -vfs_statfs_t __vfs_statfs; - -#define VFS_PROLOGUE(MP) do { \ - struct mount *mp__; \ - int _enable_stops; \ - \ - mp__ = (MP); \ - _enable_stops = (mp__ != NULL && \ - (mp__->mnt_vfc->vfc_flags & VFCF_SBDRY) && sigdeferstop()) - -#define VFS_EPILOGUE(MP) \ - if (_enable_stops) \ - sigallowstop(); \ -} while (0) - -#define VFS_MOUNT(MP) ({ \ - int _rc; \ - \ - VFS_PROLOGUE(MP); \ - _rc = (*(MP)->mnt_op->vfs_mount)(MP); \ - VFS_EPILOGUE(MP); \ - _rc; }) - -#define VFS_UNMOUNT(MP, FORCE) ({ \ - int _rc; \ - \ - VFS_PROLOGUE(MP); \ - _rc = (*(MP)->mnt_op->vfs_unmount)(MP, FORCE); \ - VFS_EPILOGUE(MP); \ - _rc; }) - -#define VFS_ROOT(MP, FLAGS, VPP) ({ \ - int _rc; \ - \ - VFS_PROLOGUE(MP); \ - _rc = (*(MP)->mnt_op->vfs_root)(MP, FLAGS, VPP); \ - VFS_EPILOGUE(MP); \ - _rc; }) - -#define VFS_QUOTACTL(MP, C, U, A) ({ \ - int _rc; \ - \ - VFS_PROLOGUE(MP); \ - _rc = (*(MP)->mnt_op->vfs_quotactl)(MP, C, U, A); \ - VFS_EPILOGUE(MP); \ - _rc; }) - -#define VFS_STATFS(MP, SBP) ({ \ - int _rc; \ - \ - VFS_PROLOGUE(MP); \ - _rc = __vfs_statfs((MP), (SBP)); \ - VFS_EPILOGUE(MP); \ - _rc; }) - -#define VFS_SYNC(MP, WAIT) ({ \ - int _rc; \ - \ - VFS_PROLOGUE(MP); \ - _rc = (*(MP)->mnt_op->vfs_sync)(MP, WAIT); \ - VFS_EPILOGUE(MP); \ - _rc; }) - -#define VFS_VGET(MP, INO, FLAGS, VPP) ({ \ - int _rc; \ - \ - VFS_PROLOGUE(MP); \ - _rc = (*(MP)->mnt_op->vfs_vget)(MP, INO, FLAGS, VPP); \ - VFS_EPILOGUE(MP); \ - _rc; }) - -#define VFS_FHTOVP(MP, FIDP, FLAGS, VPP) ({ \ - int _rc; \ - \ - VFS_PROLOGUE(MP); \ - _rc = (*(MP)->mnt_op->vfs_fhtovp)(MP, FIDP, FLAGS, VPP); \ - VFS_EPILOGUE(MP); \ - _rc; }) - -#define VFS_CHECKEXP(MP, NAM, EXFLG, CRED, NUMSEC, SEC) ({ \ - int _rc; \ - \ - VFS_PROLOGUE(MP); \ - _rc = (*(MP)->mnt_op->vfs_checkexp)(MP, NAM, EXFLG, CRED, NUMSEC,\ - SEC); \ - VFS_EPILOGUE(MP); \ - _rc; }) - -#define VFS_EXTATTRCTL(MP, C, FN, NS, N) ({ \ - int _rc; \ - \ - VFS_PROLOGUE(MP); \ - _rc = (*(MP)->mnt_op->vfs_extattrctl)(MP, C, FN, NS, N); \ - VFS_EPILOGUE(MP); \ - _rc; }) - -#define VFS_SYSCTL(MP, OP, REQ) ({ \ - int _rc; \ - \ - VFS_PROLOGUE(MP); \ - _rc = (*(MP)->mnt_op->vfs_sysctl)(MP, OP, REQ); \ - VFS_EPILOGUE(MP); \ - _rc; }) - -#define VFS_SUSP_CLEAN(MP) do { \ - if (*(MP)->mnt_op->vfs_susp_clean != NULL) { \ - VFS_PROLOGUE(MP); \ - (*(MP)->mnt_op->vfs_susp_clean)(MP); \ - VFS_EPILOGUE(MP); \ - } \ -} while (0) - -#define VFS_RECLAIM_LOWERVP(MP, VP) do { \ - if (*(MP)->mnt_op->vfs_reclaim_lowervp != NULL) { \ - VFS_PROLOGUE(MP); \ - (*(MP)->mnt_op->vfs_reclaim_lowervp)((MP), (VP)); \ - VFS_EPILOGUE(MP); \ - } \ -} while (0) - -#define VFS_UNLINK_LOWERVP(MP, VP) do { \ - if (*(MP)->mnt_op->vfs_unlink_lowervp != NULL) { \ - VFS_PROLOGUE(MP); \ - (*(MP)->mnt_op->vfs_unlink_lowervp)((MP), (VP)); \ - VFS_EPILOGUE(MP); \ - } \ -} while (0) - -#define VFS_PURGE(MP) do { \ - if (*(MP)->mnt_op->vfs_purge != NULL) { \ - VFS_PROLOGUE(MP); \ - (*(MP)->mnt_op->vfs_purge)(MP); \ - VFS_EPILOGUE(MP); \ - } \ -} while (0) - -#define VFS_KNOTE_LOCKED(vp, hint) do \ -{ \ - if (((vp)->v_vflag & VV_NOKNOTE) == 0) \ - VN_KNOTE((vp), (hint), KNF_LISTLOCKED); \ -} while (0) - -#define VFS_KNOTE_UNLOCKED(vp, hint) do \ -{ \ - if (((vp)->v_vflag & VV_NOKNOTE) == 0) \ - VN_KNOTE((vp), (hint), 0); \ -} while (0) - -#define VFS_NOTIFY_UPPER_RECLAIM 1 -#define VFS_NOTIFY_UPPER_UNLINK 2 - -#include <sys/module.h> - -/* - * Version numbers. - */ -#define VFS_VERSION_00 0x19660120 -#define VFS_VERSION_01 0x20121030 -#define VFS_VERSION VFS_VERSION_01 - -#define VFS_SET(vfsops, fsname, flags) \ - static struct vfsconf fsname ## _vfsconf = { \ - .vfc_version = VFS_VERSION, \ - .vfc_name = #fsname, \ - .vfc_vfsops = &vfsops, \ - .vfc_typenum = -1, \ - .vfc_flags = flags, \ - }; \ - static moduledata_t fsname ## _mod = { \ - #fsname, \ - vfs_modevent, \ - & fsname ## _vfsconf \ - }; \ - DECLARE_MODULE(fsname, fsname ## _mod, SI_SUB_VFS, SI_ORDER_MIDDLE) - -/* - * exported vnode operations - */ - -int dounmount(struct mount *, int, struct thread *); - -int kernel_mount(struct mntarg *ma, uint64_t flags); -int kernel_vmount(int flags, ...); -struct mntarg *mount_arg(struct mntarg *ma, const char *name, const void *val, int len); -struct mntarg *mount_argb(struct mntarg *ma, int flag, const char *name); -struct mntarg *mount_argf(struct mntarg *ma, const char *name, const char *fmt, ...); -struct mntarg *mount_argsu(struct mntarg *ma, const char *name, const void *val, int len); -void statfs_scale_blocks(struct statfs *sf, long max_size); -struct vfsconf *vfs_byname(const char *); -struct vfsconf *vfs_byname_kld(const char *, struct thread *td, int *); -void vfs_mount_destroy(struct mount *); -void vfs_event_signal(fsid_t *, u_int32_t, intptr_t); -void vfs_freeopts(struct vfsoptlist *opts); -void vfs_deleteopt(struct vfsoptlist *opts, const char *name); -int vfs_buildopts(struct uio *auio, struct vfsoptlist **options); -int vfs_flagopt(struct vfsoptlist *opts, const char *name, uint64_t *w, - uint64_t val); -int vfs_getopt(struct vfsoptlist *, const char *, void **, int *); -int vfs_getopt_pos(struct vfsoptlist *opts, const char *name); -int vfs_getopt_size(struct vfsoptlist *opts, const char *name, - off_t *value); -char *vfs_getopts(struct vfsoptlist *, const char *, int *error); -int vfs_copyopt(struct vfsoptlist *, const char *, void *, int); -int vfs_filteropt(struct vfsoptlist *, const char **legal); -void vfs_opterror(struct vfsoptlist *opts, const char *fmt, ...); -int vfs_scanopt(struct vfsoptlist *opts, const char *name, const char *fmt, ...); -int vfs_setopt(struct vfsoptlist *opts, const char *name, void *value, - int len); -int vfs_setopt_part(struct vfsoptlist *opts, const char *name, void *value, - int len); -int vfs_setopts(struct vfsoptlist *opts, const char *name, - const char *value); -int vfs_setpublicfs /* set publicly exported fs */ - (struct mount *, struct netexport *, struct export_args *); -void vfs_msync(struct mount *, int); -int vfs_busy(struct mount *, int); -int vfs_export /* process mount export info */ - (struct mount *, struct export_args *); -void vfs_allocate_syncvnode(struct mount *); -void vfs_deallocate_syncvnode(struct mount *); -int vfs_donmount(struct thread *td, uint64_t fsflags, - struct uio *fsoptions); -void vfs_getnewfsid(struct mount *); -struct cdev *vfs_getrootfsid(struct mount *); -struct mount *vfs_getvfs(fsid_t *); /* return vfs given fsid */ -struct mount *vfs_busyfs(fsid_t *); -int vfs_modevent(module_t, int, void *); -void vfs_mount_error(struct mount *, const char *, ...); -void vfs_mountroot(void); /* mount our root filesystem */ -void vfs_mountedfrom(struct mount *, const char *from); -void vfs_notify_upper(struct vnode *, int); -void vfs_oexport_conv(const struct oexport_args *oexp, - struct export_args *exp); -void vfs_ref(struct mount *); -void vfs_rel(struct mount *); -struct mount *vfs_mount_alloc(struct vnode *, struct vfsconf *, const char *, - struct ucred *); -int vfs_suser(struct mount *, struct thread *); -void vfs_unbusy(struct mount *); -void vfs_unmountall(void); -extern TAILQ_HEAD(mntlist, mount) mountlist; /* mounted filesystem list */ -extern struct mtx mountlist_mtx; -extern struct nfs_public nfs_pub; -extern struct sx vfsconf_sx; -#define vfsconf_lock() sx_xlock(&vfsconf_sx) -#define vfsconf_unlock() sx_xunlock(&vfsconf_sx) -#define vfsconf_slock() sx_slock(&vfsconf_sx) -#define vfsconf_sunlock() sx_sunlock(&vfsconf_sx) - -/* - * Declarations for these vfs default operations are located in - * kern/vfs_default.c. They will be automatically used to replace - * null entries in VFS ops tables when registering a new filesystem - * type in the global table. - */ -vfs_root_t vfs_stdroot; -vfs_quotactl_t vfs_stdquotactl; -vfs_statfs_t vfs_stdstatfs; -vfs_sync_t vfs_stdsync; -vfs_sync_t vfs_stdnosync; -vfs_vget_t vfs_stdvget; -vfs_fhtovp_t vfs_stdfhtovp; -vfs_checkexp_t vfs_stdcheckexp; -vfs_init_t vfs_stdinit; -vfs_uninit_t vfs_stduninit; -vfs_extattrctl_t vfs_stdextattrctl; -vfs_sysctl_t vfs_stdsysctl; - -void syncer_suspend(void); -void syncer_resume(void); - -#else /* !_KERNEL */ - -#include <sys/cdefs.h> - -struct stat; - -__BEGIN_DECLS -int fhopen(const struct fhandle *, int); -int fhstat(const struct fhandle *, struct stat *); -int fhstatfs(const struct fhandle *, struct statfs *); -int fstatfs(int, struct statfs *); -int getfh(const char *, fhandle_t *); -int getfsstat(struct statfs *, long, int); -int getmntinfo(struct statfs **, int); -int lgetfh(const char *, fhandle_t *); -int mount(const char *, const char *, int, void *); -int nmount(struct iovec *, unsigned int, int); -int statfs(const char *, struct statfs *); -int unmount(const char *, int); - -/* C library stuff */ -int getvfsbyname(const char *, struct xvfsconf *); -__END_DECLS - -#endif /* _KERNEL */ - -#endif /* !_SYS_MOUNT_H_ */ diff --git a/usr/src/boot/sys/sys/ucred.h b/usr/src/boot/sys/sys/ucred.h deleted file mode 100644 index 8dbf2fef74..0000000000 --- a/usr/src/boot/sys/sys/ucred.h +++ /dev/null @@ -1,119 +0,0 @@ -/*- - * Copyright (c) 1989, 1993 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)ucred.h 8.4 (Berkeley) 1/9/95 - * $FreeBSD$ - */ - -#ifndef _SYS_UCRED_H_ -#define _SYS_UCRED_H_ - -#include <bsm/audit.h> - -struct loginclass; - -#define XU_NGROUPS 16 - -/* - * Credentials. - * - * Please do not inspect cr_uid directly to determine superuserness. The - * priv(9) interface should be used to check for privilege. - */ -#if defined(_KERNEL) || defined(_WANT_UCRED) -struct ucred { - u_int cr_ref; /* reference count */ -#define cr_startcopy cr_uid - uid_t cr_uid; /* effective user id */ - uid_t cr_ruid; /* real user id */ - uid_t cr_svuid; /* saved user id */ - int cr_ngroups; /* number of groups */ - gid_t cr_rgid; /* real group id */ - gid_t cr_svgid; /* saved group id */ - struct uidinfo *cr_uidinfo; /* per euid resource consumption */ - struct uidinfo *cr_ruidinfo; /* per ruid resource consumption */ - struct prison *cr_prison; /* jail(2) */ - struct loginclass *cr_loginclass; /* login class */ - u_int cr_flags; /* credential flags */ - void *cr_pspare2[2]; /* general use 2 */ -#define cr_endcopy cr_label - struct label *cr_label; /* MAC label */ - struct auditinfo_addr cr_audit; /* Audit properties. */ - gid_t *cr_groups; /* groups */ - int cr_agroups; /* Available groups */ - gid_t cr_smallgroups[XU_NGROUPS]; /* storage for small groups */ -}; -#define NOCRED ((struct ucred *)0) /* no credential available */ -#define FSCRED ((struct ucred *)-1) /* filesystem credential */ -#endif /* _KERNEL || _WANT_UCRED */ - -/* - * Flags for cr_flags. - */ -#define CRED_FLAG_CAPMODE 0x00000001 /* In capability mode. */ - -/* - * This is the external representation of struct ucred. - */ -struct xucred { - u_int cr_version; /* structure layout version */ - uid_t cr_uid; /* effective user id */ - short cr_ngroups; /* number of groups */ - gid_t cr_groups[XU_NGROUPS]; /* groups */ - void *_cr_unused1; /* compatibility with old ucred */ -}; -#define XUCRED_VERSION 0 - -/* This can be used for both ucred and xucred structures. */ -#define cr_gid cr_groups[0] - -#ifdef _KERNEL -struct proc; -struct thread; - -void change_egid(struct ucred *newcred, gid_t egid); -void change_euid(struct ucred *newcred, struct uidinfo *euip); -void change_rgid(struct ucred *newcred, gid_t rgid); -void change_ruid(struct ucred *newcred, struct uidinfo *ruip); -void change_svgid(struct ucred *newcred, gid_t svgid); -void change_svuid(struct ucred *newcred, uid_t svuid); -void crcopy(struct ucred *dest, struct ucred *src); -struct ucred *crcopysafe(struct proc *p, struct ucred *cr); -struct ucred *crdup(struct ucred *cr); -void crextend(struct ucred *cr, int n); -void proc_set_cred_init(struct proc *p, struct ucred *cr); -struct ucred *proc_set_cred(struct proc *p, struct ucred *cr); -void crfree(struct ucred *cr); -struct ucred *crget(void); -struct ucred *crhold(struct ucred *cr); -void cru2x(struct ucred *cr, struct xucred *xcr); -void crsetgroups(struct ucred *cr, int n, gid_t *groups); -int groupmember(gid_t gid, struct ucred *cred); -#endif /* _KERNEL */ - -#endif /* !_SYS_UCRED_H_ */ diff --git a/usr/src/cmd/cmd-inet/lib/ipmgmtd/net-ipmgmt b/usr/src/cmd/cmd-inet/lib/ipmgmtd/net-ipmgmt index d5812793d4..6b39cde11f 100644 --- a/usr/src/cmd/cmd-inet/lib/ipmgmtd/net-ipmgmt +++ b/usr/src/cmd/cmd-inet/lib/ipmgmtd/net-ipmgmt @@ -30,7 +30,7 @@ . /lib/svc/share/smf_include.sh if [ -z "$SMF_FMRI" ]; then - echo "this script can only be invoked by smf(5)" + echo "this script can only be invoked by smf(5)" exit $SMF_EXIT_ERR_NOSMF fi diff --git a/usr/src/cmd/dlmgmtd/svc-dlmgmtd b/usr/src/cmd/dlmgmtd/svc-dlmgmtd index a75e71f9b3..af59ba7fa6 100644 --- a/usr/src/cmd/dlmgmtd/svc-dlmgmtd +++ b/usr/src/cmd/dlmgmtd/svc-dlmgmtd @@ -32,7 +32,9 @@ # an empty contract. if smf_is_nonglobalzone; then - exit $SMF_EXIT_NODAEMON + [ -n "$SMF_EXIT_NODAEMON" ] && exit $SMF_EXIT_NODAEMON + (while true ; do sleep 3600 ; done) & + exit $SMF_EXIT_OK fi # Start the dlmgmtd daemon. diff --git a/usr/src/cmd/fs.d/reparsed/reparsed.c b/usr/src/cmd/fs.d/reparsed/reparsed.c index 17027b0c78..0b1532dc40 100644 --- a/usr/src/cmd/fs.d/reparsed/reparsed.c +++ b/usr/src/cmd/fs.d/reparsed/reparsed.c @@ -24,6 +24,10 @@ */ /* + * Copyright (c) 2018, Joyent, Inc. + */ + +/* * Reparsed daemon */ @@ -191,10 +195,11 @@ reparsed_door_call_error(int error, int buflen) memset(&rpd_res, 0, sizeof (reparsed_door_res_t)); rpd_res.res_status = error; rpd_res.res_len = buflen; - door_return((char *)&rpd_res, sizeof (reparsed_door_res_t), NULL, 0); + (void) door_return((char *)&rpd_res, + sizeof (reparsed_door_res_t), NULL, 0); (void) door_return(NULL, 0, NULL, 0); - /* NOTREACHED */ + abort(); } /* diff --git a/usr/src/cmd/fs.d/smbclnt/chacl/chacl.c b/usr/src/cmd/fs.d/smbclnt/chacl/chacl.c index 4b5f8722df..413c8a62fa 100644 --- a/usr/src/cmd/fs.d/smbclnt/chacl/chacl.c +++ b/usr/src/cmd/fs.d/smbclnt/chacl/chacl.c @@ -25,6 +25,10 @@ */ /* + * Copyright (c) 2018, Joyent, Inc. + */ + +/* * This is the smbfs/chacl command. * (just for testing - not installed) * @@ -138,9 +142,8 @@ main(int argc, char **argv) /* * Which parts of the SD are being modified? */ - selector = 0; - if (acl) - selector |= DACL_SECURITY_INFORMATION; + selector = DACL_SECURITY_INFORMATION; + if (uid != (uid_t)-1) selector |= OWNER_SECURITY_INFORMATION; if (gid != (gid_t)-1) diff --git a/usr/src/cmd/fs.d/smbclnt/umount/umount.c b/usr/src/cmd/fs.d/smbclnt/umount/umount.c index 5bf6984e78..412557e567 100644 --- a/usr/src/cmd/fs.d/smbclnt/umount/umount.c +++ b/usr/src/cmd/fs.d/smbclnt/umount/umount.c @@ -24,6 +24,10 @@ */ /* + * Copyright (c) 2018, Joyent, Inc. + */ + +/* * smbfs umount */ @@ -179,6 +183,6 @@ mnttab_find(dirname) } } - fclose(fp); + (void) fclose(fp); return (res); } diff --git a/usr/src/cmd/fs.d/ufs/mkfs/mkfs.c b/usr/src/cmd/fs.d/ufs/mkfs/mkfs.c index 6b5439d47c..0098b56082 100644 --- a/usr/src/cmd/fs.d/ufs/mkfs/mkfs.c +++ b/usr/src/cmd/fs.d/ufs/mkfs/mkfs.c @@ -37,6 +37,10 @@ */ /* + * Copyright (c) 2018, Joyent, Inc. + */ + +/* * The maximum supported file system size (in sectors) is the * number of frags that can be represented in an int32_t field * (INT_MAX) times the maximum number of sectors per frag. Since @@ -235,6 +239,7 @@ #include <sys/int_const.h> #include <signal.h> #include <sys/efi_partition.h> +#include <fslib.h> #include "roll_log.h" #define bcopy(f, t, n) (void) memcpy(t, f, n) diff --git a/usr/src/cmd/nscd/svc-nscd b/usr/src/cmd/nscd/svc-nscd index 78b318bf87..c9f23f7088 100644 --- a/usr/src/cmd/nscd/svc-nscd +++ b/usr/src/cmd/nscd/svc-nscd @@ -34,34 +34,36 @@ if (smf_is_system_labeled); then if (smf_is_nonglobalzone); then if [ ! -f /var/tsol/doors/nscd_per_label ]; then - # If needed create a door to the global zone daemon. - if [ -r /var/run/name_service_door ]; then + # If needed create a door to the global zone daemon. + if [ -r /var/run/name_service_door ]; then rm /var/run/name_service_door - fi - ln -s /var/tsol/doors/name_service_door \ + fi + ln -s /var/tsol/doors/name_service_door \ /var/run || exit $SMF_EXIT_ERR_FATAL - # If current service duration is not "transient", - # create a dummy background process to preserve + # If current service duration is not "transient", + # create a dummy background process to preserve # contract lifetime. - duration="" - if /bin/svcprop -q -c -p startd/duration $SMF_FMRI + duration="" + if /bin/svcprop -q -c -p startd/duration $SMF_FMRI then - duration=`/bin/svcprop -c -p startd/duration \ + duration=`/bin/svcprop -c -p startd/duration \ $SMF_FMRI` - fi - if [ "$duration" != "transient" ]; then - exit $SMF_EXIT_NODAEMON - fi + fi + if [ "$duration" != "transient" ]; then + [ -n "$SMF_EXIT_NODAEMON" ] && \ + exit $SMF_EXIT_NODAEMON + (while true ; do sleep 3600 ; done) & + fi - # The real daemon is not started in non-global zones, + # The real daemon is not started in non-global zones, # so exit now. - exit $SMF_EXIT_OK + exit $SMF_EXIT_OK else - # remove the door to the global zone daemon - if [ -L /var/run/name_service_door ]; then - rm /var/run/name_service_door - fi + # remove the door to the global zone daemon + if [ -L /var/run/name_service_door ]; then + rm /var/run/name_service_door + fi fi fi fi diff --git a/usr/src/cmd/svc/shell/smf_include.sh b/usr/src/cmd/svc/shell/smf_include.sh index 429e3310f4..a5e3431d5b 100644 --- a/usr/src/cmd/svc/shell/smf_include.sh +++ b/usr/src/cmd/svc/shell/smf_include.sh @@ -24,6 +24,7 @@ # Use is subject to license terms. # Copyright 2012 Joyent, Inc. All rights reserved. # Copyright 2015 Nexenta Systems, Inc. All rights reserved. +# Copyright 2012 Joyent, Inc. All rights reserved. # smf_present () { @@ -155,7 +156,7 @@ smf_netstrategy () { # # Example, send SIGTERM to contract 200: # -# smf_kill_contract 200 TERM +# smf_kill_contract 200 TERM # # Since killing a contract with pkill(1) is not atomic, # smf_kill_contract will continue to send SIGNAL to CONTRACT @@ -202,7 +203,7 @@ smf_kill_contract() { # Return if WAIT is not set or is "0" [ -z "$3" ] && return 0 [ "$3" -eq 0 ] && return 0 - + # If contract does not empty, keep killing the contract to catch # any child processes missed because they were forking /usr/bin/pgrep -c $1 > /dev/null 2>&1 diff --git a/usr/src/cmd/svc/startd/method.c b/usr/src/cmd/svc/startd/method.c index 1d8ffaa2b6..915ad42da6 100644 --- a/usr/src/cmd/svc/startd/method.c +++ b/usr/src/cmd/svc/startd/method.c @@ -698,7 +698,7 @@ method_run(restarter_inst_t **instp, int type, int *exit_code) if (inst->ri_mi_deleted) return (ECANCELED); - *exit_code = 0; + *exit_code = SMF_EXIT_OK; assert(0 <= type && type <= 2); mname = method_names[type]; @@ -1034,7 +1034,8 @@ method_run(restarter_inst_t **instp, int type, int *exit_code) } *exit_code = WEXITSTATUS(ret_status); - if (*exit_code != 0 && *exit_code != SMF_EXIT_NODAEMON) { + if (*exit_code != SMF_EXIT_OK && + *exit_code != SMF_EXIT_NODAEMON) { log_error(LOG_WARNING, "%s: Method \"%s\" failed with exit status %d.\n", inst->ri_i.i_fmri, method, WEXITSTATUS(ret_status)); @@ -1044,7 +1045,7 @@ method_run(restarter_inst_t **instp, int type, int *exit_code) "%d.", mname, *exit_code); /* Note: we will take this path for SMF_EXIT_NODAEMON */ - if (*exit_code != 0) + if (*exit_code != SMF_EXIT_OK) goto contract_out; end_time = time(NULL); @@ -1095,7 +1096,7 @@ contract_out: * SMF_EXIT_NODAEMON & methods that fail. */ transient = method_is_transient(inst, type); - if ((transient || *exit_code != 0 || result != 0) && + if ((transient || *exit_code != SMF_EXIT_OK || result != 0) && (restarter_is_kill_method(method) < 0)) method_remove_contract(inst, !transient, B_TRUE); @@ -1191,7 +1192,8 @@ retry: r = method_run(&inst, info->sf_method_type, &exit_code); - if (r == 0 && (exit_code == 0 || exit_code == SMF_EXIT_NODAEMON)) { + if (r == 0 && + (exit_code == SMF_EXIT_OK || exit_code == SMF_EXIT_NODAEMON)) { /* Success! */ assert(inst->ri_i.i_next_state != RESTARTER_STATE_NONE); diff --git a/usr/src/lib/libscf/inc/libscf.h b/usr/src/lib/libscf/inc/libscf.h index f4502b7f14..adc7455622 100644 --- a/usr/src/lib/libscf/inc/libscf.h +++ b/usr/src/lib/libscf/inc/libscf.h @@ -23,6 +23,7 @@ * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2012, Joyent, Inc. All rights reserved. * Copyright 2016 RackTop Systems. + * Copyright (c) 2012, Joyent, Inc. All rights reserved. */ #ifndef _LIBSCF_H @@ -340,7 +341,7 @@ typedef struct { #define SCF_PROPERTY_GROUP "group" #define SCF_PROPERTY_GROUPING "grouping" #define SCF_PROPERTY_IGNORE "ignore_error" -#define SCF_PROPERTY_INTERNAL_SEPARATORS "internal_separators" +#define SCF_PROPERTY_INTERNAL_SEPARATORS "internal_separators" #define SCF_PROPERTY_LIMIT_PRIVILEGES "limit_privileges" #define SCF_PROPERTY_MAINT_OFF "maint_off" #define SCF_PROPERTY_MAINT_ON "maint_on" @@ -390,7 +391,7 @@ typedef struct { #define SCF_PROPERTY_TM_CHOICES_NAME "choices_name" #define SCF_PROPERTY_TM_CHOICES_RANGE "choices_range" #define SCF_PROPERTY_TM_CONSTRAINT_NAME "constraint_name" -#define SCF_PROPERTY_TM_CONSTRAINT_RANGE "constraint_range" +#define SCF_PROPERTY_TM_CONSTRAINT_RANGE "constraint_range" #define SCF_PROPERTY_TM_MANPATH "manpath" #define SCF_PROPERTY_TM_NAME "name" #define SCF_PROPERTY_TM_PG_PATTERN "pg_pattern" diff --git a/usr/src/uts/common/Makefile.files b/usr/src/uts/common/Makefile.files index 77479bcf24..0c734ff062 100644 --- a/usr/src/uts/common/Makefile.files +++ b/usr/src/uts/common/Makefile.files @@ -2263,3 +2263,24 @@ QEDE_GEN_OBJS += ecore_hw.o ecore_cxt.o ecore_selftest.o ecore_init_ops.o \ ecore_init_fw_funcs.o ecore_sp_commands.o ecore_dcbx.o \ ecore_dbg_fw_funcs.o ecore_mcp.o ecore_spq.o ecore_phy.o \ ecore_dev.o ecore_l2.o ecore_int.o + +BNX_OBJS += \ + bnxmod.o \ + bnxcfg.o \ + bnxdbg.o \ + bnxgldv3.o \ + bnxhwi.o \ + bnxint.o \ + bnxrcv.o \ + bnxsnd.o \ + bnxtmr.o \ + bnx_kstat.o \ + bnx_mm.o \ + bnx_hw_cpu.o \ + bnx_hw_misc.o \ + bnx_hw_nvram.o \ + bnx_hw_phy.o \ + bnx_hw_reset.o \ + bnx_lm_main.o \ + bnx_lm_recv.o \ + bnx_lm_send.o diff --git a/usr/src/uts/common/Makefile.rules b/usr/src/uts/common/Makefile.rules index 225a97295e..958e3bbf8c 100644 --- a/usr/src/uts/common/Makefile.rules +++ b/usr/src/uts/common/Makefile.rules @@ -664,6 +664,14 @@ $(OBJS_DIR)/%.o: $(UTSBASE)/common/io/blkdev/%.c $(COMPILE.c) -o $@ $< $(CTFCONVERT_O) +$(OBJS_DIR)/%.o: $(UTSBASE)/common/io/bnx/%.c + $(COMPILE.c) -o $@ $< + $(CTFCONVERT_O) + +$(OBJS_DIR)/%.o: $(UTSBASE)/common/io/bnx/570x/driver/common/lmdev/%.c + $(COMPILE.c) -o $@ $< + $(CTFCONVERT_O) + $(OBJS_DIR)/%.o: $(UTSBASE)/common/io/bnxe/%.c $(COMPILE.c) -o $@ $< $(CTFCONVERT_O) diff --git a/usr/src/uts/common/io/bnx/570x/common/include/54xx_reg.h b/usr/src/uts/common/io/bnx/570x/common/include/54xx_reg.h new file mode 100644 index 0000000000..d73fbfcb4c --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/54xx_reg.h @@ -0,0 +1,224 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _54xx_reg_h +#define _54xx_reg_h + +#include "bits.h" + + + +/* Control register. */ +#define PHY_CTRL_REG 0x00 +#define PHY_CTRL_SPEED_MASK (BIT_6 | BIT_13) +#define PHY_CTRL_SPEED_SELECT_10MBPS BIT_NONE +#define PHY_CTRL_SPEED_SELECT_100MBPS BIT_13 +#define PHY_CTRL_SPEED_SELECT_1000MBPS BIT_6 +#define PHY_CTRL_COLLISION_TEST_ENABLE BIT_7 +#define PHY_CTRL_FULL_DUPLEX_MODE BIT_8 +#define PHY_CTRL_RESTART_AUTO_NEG BIT_9 +#define PHY_CTRL_ISOLATE_PHY BIT_10 +#define PHY_CTRL_LOWER_POWER_MODE BIT_11 +#define PHY_CTRL_AUTO_NEG_ENABLE BIT_12 +#define PHY_CTRL_LOOPBACK_MODE BIT_14 +#define PHY_CTRL_PHY_RESET BIT_15 + + +/* Status register. */ +#define PHY_STATUS_REG 0x01 +#define PHY_STATUS_LINK_PASS BIT_2 +#define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5 + + +/* Phy Id registers. */ +#define PHY_ID1_REG 0x02 +#define PHY_ID2_REG 0x03 + +/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */ +#define PHY_BCM5400_PHY_ID 0x00206040 +#define PHY_BCM5401_PHY_ID 0x00206050 +#define PHY_BCM5411_PHY_ID 0x00206070 +#define PHY_BCM5701_PHY_ID 0x00206110 +#define PHY_BCM5703_PHY_ID 0x00206160 +#define PHY_BCM5706_PHY_ID 0x00206160 + +#define PHY_ID(id) ((id) & 0xfffffff0) +#define PHY_REV_ID(id) ((id) & 0xf) +#define PHY_BCM5401_B0_REV 0x1 +#define PHY_BCM5401_B2_REV 0x3 +#define PHY_BCM5401_C0_REV 0x6 + + +/* Auto-negotiation advertisement register. */ +#define PHY_AN_AD_REG 0x04 +#define PHY_AN_AD_10BASET_HALF BIT_5 +#define PHY_AN_AD_10BASET_FULL BIT_6 +#define PHY_AN_AD_100BASETX_HALF BIT_7 +#define PHY_AN_AD_100BASETX_FULL BIT_8 +#define PHY_AN_AD_PAUSE_CAPABLE BIT_10 +#define PHY_AN_AD_ASYM_PAUSE BIT_11 +#define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01 + + +/* Apply to 1000-X fiber mode only */ +#define PHY_AN_AD_1000X_FULL_DUPLEX BIT_5 +#define PHY_AN_AD_1000X_HALF_DUPLEX BIT_6 +#define PHY_AN_AD_1000X_PAUSE_CAPABLE BIT_7 +#define PHY_AN_AD_1000X_ASYM_PAUSE BIT_8 +#define PHY_AN_AD_1000X_REMOTE_FAULT_LINK_FAILURE BIT_12 +#define PHY_AN_AD_1000X_REMOTE_FAULT_OFFLINE BIT_13 +#define PHY_AN_AD_1000X_REMOTE_FAULT_AUTONEG_ERR (BIT_12 | BIT_13) + +/* Auto-negotiation Link Partner Ability register. */ +#define PHY_LINK_PARTNER_ABILITY_REG 0x05 +#define PHY_LINK_PARTNER_10BASET_HALF BIT_5 +#define PHY_LINK_PARTNER_10BASET_FULL BIT_6 +#define PHY_LINK_PARTNER_100BASETX_HALF BIT_7 +#define PHY_LINK_PARTNER_100BASETX_FULL BIT_8 +#define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10 +#define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11 + + +/* Auto-negotiation expansion register. */ +#define PHY_AN_EXPANSION_REG 0x06 +#define PHY_LINK_PARTNER_AUTONEG_ABILITY BIT_0 + + +/* 1000Base-T control/advertisement register. */ +#define PHY_1000BASET_CTRL_REG 0x09 +#define PHY_AN_AD_1000BASET_HALF BIT_8 +#define PHY_AN_AD_1000BASET_FULL BIT_9 +#define PHY_CONFIG_AS_MASTER BIT_11 +#define PHY_ENABLE_CONFIG_AS_MASTER BIT_12 + + +/* 1000Base-T status/link partner advertisement. */ +#define PHY_1000BASET_STATUS_REG 0x0a +#define PHY_LINK_PARTNER_1000BASET_HALF BIT_10 +#define PHY_LINK_PARTNER_1000BASET_FULL BIT_11 + + +/* Extended control register. */ +#define BCM540X_EXT_CTRL_REG 0x10 + +#define BCM540X_EXT_CTRL_LINK3_LED_MODE BIT_1 +#define BCM540X_EXT_CTRL_TBI BIT_15 + + +/* DSP Coefficient Read/Write Port. */ +#define BCM540X_DSP_RW_PORT 0x15 + + +/* DSP Coeficient Address Register. */ +#define BCM540X_DSP_ADDRESS_REG 0x17 + +#define BCM540X_DSP_TAP_NUMBER_MASK 0x00 +#define BCM540X_DSP_AGC_A 0x00 +#define BCM540X_DSP_AGC_B 0x01 +#define BCM540X_DSP_MSE_PAIR_STATUS 0x02 +#define BCM540X_DSP_SOFT_DECISION 0x03 +#define BCM540X_DSP_PHASE_REG 0x04 +#define BCM540X_DSP_SKEW 0x05 +#define BCM540X_DSP_POWER_SAVER_UPPER_BOUND 0x06 +#define BCM540X_DSP_POWER_SAVER_LOWER_BOUND 0x07 +#define BCM540X_DSP_LAST_ECHO 0x08 +#define BCM540X_DSP_FREQUENCY 0x09 +#define BCM540X_DSP_PLL_BANDWIDTH 0x0a +#define BCM540X_DSP_PLL_PHASE_OFFSET 0x0b + +#define BCM540X_DSP_FILTER_DCOFFSET (BIT_10 | BIT_11) +#define BCM540X_DSP_FILTER_FEXT3 (BIT_8 | BIT_9 | BIT_11) +#define BCM540X_DSP_FILTER_FEXT2 (BIT_9 | BIT_11) +#define BCM540X_DSP_FILTER_FEXT1 (BIT_8 | BIT_11) +#define BCM540X_DSP_FILTER_FEXT0 BIT_11 +#define BCM540X_DSP_FILTER_NEXT3 (BIT_8 | BIT_9 | BIT_10) +#define BCM540X_DSP_FILTER_NEXT2 (BIT_9 | BIT_10) +#define BCM540X_DSP_FILTER_NEXT1 (BIT_8 | BIT_10) +#define BCM540X_DSP_FILTER_NEXT0 BIT_10 +#define BCM540X_DSP_FILTER_ECHO (BIT_8 | BIT_9) +#define BCM540X_DSP_FILTER_DFE BIT_9 +#define BCM540X_DSP_FILTER_FFE BIT_8 + +#define BCM540X_DSP_CONTROL_ALL_FILTERS BIT_12 + +#define BCM540X_DSP_SEL_CH_0 BIT_NONE +#define BCM540X_DSP_SEL_CH_1 BIT_13 +#define BCM540X_DSP_SEL_CH_2 BIT_14 +#define BCM540X_DSP_SEL_CH_3 (BIT_13 | BIT_14) + +#define BCM540X_CONTROL_ALL_CHANNELS BIT_15 + + +/* Auxilliary Control Register (Shadow Register) */ +#define BCM5401_AUX_CTRL 0x18 + +#define BCM5401_SHADOW_SEL_MASK 0x7 +#define BCM5401_SHADOW_SEL_NORMAL 0x00 +#define BCM5401_SHADOW_SEL_10BASET 0x01 +#define BCM5401_SHADOW_SEL_POWER_CONTROL 0x02 +#define BCM5401_SHADOW_SEL_IP_PHONE 0x03 +#define BCM5401_SHADOW_SEL_MISC_TEST1 0x04 +#define BCM5401_SHADOW_SEL_MISC_TEST2 0x05 +#define BCM5401_SHADOW_SEL_IP_PHONE_SEED 0x06 + + +/* Shadow register selector == '000' */ +#define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3 +#define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4 +#define BCM5401_SHDW_NORMAL_DISABLE_LOW_PWR BIT_5 +#define BCM5401_SHDW_NORMAL_DISABLE_INV_PRF BIT_6 +#define BCM5401_SHDW_NORMAL_DISABLE_PRF BIT_7 +#define BCM5401_SHDW_NORMAL_RX_SLICING_NORMAL BIT_NONE +#define BCM5401_SHDW_NORMAL_RX_SLICING_4D BIT_8 +#define BCM5401_SHDW_NORMAL_RX_SLICING_3LVL_1D BIT_9 +#define BCM5401_SHDW_NORMAL_RX_SLICING_5LVL_1D (BIT_8 | BIT_9) +#define BCM5401_SHDW_NORMAL_TX_6DB_CODING BIT_10 +#define BCM5401_SHDW_NORMAL_ENABLE_SM_DSP_CLOCK BIT_11 +#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_4NS BIT_NONE +#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_5NS BIT_12 +#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_3NS BIT_13 +#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_0NS (BIT_12 | BIT_13) +#define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14 +#define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15 + + +/* Auxilliary status summary. */ +#define BCM540X_AUX_STATUS_REG 0x19 + +#define BCM540X_AUX_LINK_PASS BIT_2 +#define BCM540X_AUX_SPEED_MASK (BIT_8 | BIT_9 | BIT_10) +#define BCM540X_AUX_10BASET_HD BIT_8 +#define BCM540X_AUX_10BASET_FD BIT_9 +#define BCM540X_AUX_100BASETX_HD (BIT_8 | BIT_9) +#define BCM540X_AUX_100BASET4 BIT_10 +#define BCM540X_AUX_100BASETX_FD (BIT_8 | BIT_10) +#define BCM540X_AUX_1000BASET_HD (BIT_9 | BIT_10) +#define BCM540X_AUX_1000BASET_FD (BIT_8 | BIT_9 | BIT_10) + + +/* Interrupt status. */ +#define BCM540X_INT_STATUS_REG 0x1a + +#define BCM540X_INT_LINK_CHNG BIT_1 +#define BCM540X_INT_SPEED_CHNG BIT_2 +#define BCM540X_INT_DUPLEX_CHNG BIT_3 +#define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10 + + +/* Interrupt mask register. */ +#define BCM540X_INT_MASK_REG 0x1b + + + +#endif // _54xx_reg_h diff --git a/usr/src/uts/common/io/bnx/570x/common/include/5706_reg.h b/usr/src/uts/common/io/bnx/570x/common/include/5706_reg.h new file mode 100644 index 0000000000..22f17c804b --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/5706_reg.h @@ -0,0 +1,17893 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "bcmtype.h" + +#ifndef _5709_reg_h_ +#define _5709_reg_h_ + +// ???? #pragma pack(4) + +#ifndef STATUS_BLOCK_SPACING +#define STATUS_BLOCK_SPACING 64 +#endif + +#if !defined(LITTLE_ENDIAN) && !defined(BIG_ENDIAN) + #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." +#endif + + + +/* + * tx_bd_b definition + */ +typedef struct tx_bd_b +{ + u32_t tx_bd_haddr_hi; + u32_t tx_bd_haddr_lo; + u16_t tx_bd_reserved; + #define TX_BD_RESERVED_MSS (0x3fff<<0) + #define TX_BD_RESERVED_BIT14_15 (0x03<<14) + u16_t tx_bd_nbytes; + u16_t tx_bd_vlan_tag; + u16_t tx_bd_flags; + #define TX_BD_FLAGS_CONN_FAULT (1<<0) + #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) + #define TX_BD_FLAGS_IP_CKSUM (1<<2) + #define TX_BD_FLAGS_VLAN_TAG (1<<3) + #define TX_BD_FLAGS_COAL_NOW (1<<4) + #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) + #define TX_BD_FLAGS_END (1<<6) + #define TX_BD_FLAGS_START (1<<7) + #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) + #define TX_BD_FLAGS_SW_OPTION_MSB (1<<12) + #define TX_BD_FLAGS_SW_END (1<<12) + #define TX_BD_FLAGS_SW_FLAGS (1<<13) + #define TX_BD_FLAGS_SW_SNAP (1<<14) + #define TX_BD_FLAGS_SW_LSO (1<<15) + +} tx_bd_b_t; + + +/* + * tx_bd_l definition + */ +typedef struct tx_bd_l +{ + u32_t tx_bd_haddr_hi; + u32_t tx_bd_haddr_lo; + u16_t tx_bd_nbytes; + u16_t tx_bd_reserved; + #define TX_BD_RESERVED_MSS (0x3fff<<0) + #define TX_BD_RESERVED_BIT14_15 (0x03<<14) + u16_t tx_bd_flags; + #define TX_BD_FLAGS_CONN_FAULT (1<<0) + #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) + #define TX_BD_FLAGS_IP_CKSUM (1<<2) + #define TX_BD_FLAGS_VLAN_TAG (1<<3) + #define TX_BD_FLAGS_COAL_NOW (1<<4) + #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) + #define TX_BD_FLAGS_END (1<<6) + #define TX_BD_FLAGS_START (1<<7) + #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) + #define TX_BD_FLAGS_SW_OPTION_MSB (1<<12) + #define TX_BD_FLAGS_SW_END (1<<12) + #define TX_BD_FLAGS_SW_FLAGS (1<<13) + #define TX_BD_FLAGS_SW_SNAP (1<<14) + #define TX_BD_FLAGS_SW_LSO (1<<15) + + u16_t tx_bd_vlan_tag; +} tx_bd_l_t; + + +/* + * tx_bd select + */ +#if defined(LITTLE_ENDIAN) + typedef tx_bd_l_t tx_bd_t; +#elif defined(BIG_ENDIAN) + typedef tx_bd_b_t tx_bd_t; +#endif + + +/* + * tx_bd_next definition + */ +typedef struct tx_bd_next +{ + u32_t tx_bd_next_paddr_hi; + u32_t tx_bd_next_paddr_lo; + u8_t tx_bd_next_reserved[8]; +} tx_bd_next_t; + + +/* + * hqc_basic_b definition + */ +typedef struct hqc_basic_b +{ + u8_t hqc_type; + #define HQC_TYPE_N64W (0xf<<0) + #define HQC_TYPE_VALUE (0xf<<4) + #define HQC_TYPE_VALUE_BASIC (0<<4) + #define HQC_TYPE_VALUE_TOE (1<<4) + #define HQC_TYPE_VALUE_HOLE (2<<4) + #define HQC_TYPE_VALUE_LSO_CAPTURE (3<<4) + #define HQC_TYPE_VALUE_LSO_DUPLICATE (4<<4) + #define HQC_TYPE_VALUE_IWARP_STD (5<<4) + #define HQC_TYPE_VALUE_IWARP_EDGE (6<<4) + + u8_t hqc_knum; + u16_t hqc_hdr_nbytes; + u32_t unused_0; +} hqc_basic_b_t; + + +/* + * hqc_basic_l definition + */ +typedef struct hqc_basic_l +{ + u16_t hqc_hdr_nbytes; + u8_t hqc_knum; + u8_t hqc_type; + #define HQC_TYPE_N64W (0xf<<0) + #define HQC_TYPE_VALUE (0xf<<4) + #define HQC_TYPE_VALUE_BASIC (0<<4) + #define HQC_TYPE_VALUE_TOE (1<<4) + #define HQC_TYPE_VALUE_HOLE (2<<4) + #define HQC_TYPE_VALUE_LSO_CAPTURE (3<<4) + #define HQC_TYPE_VALUE_LSO_DUPLICATE (4<<4) + #define HQC_TYPE_VALUE_IWARP_STD (5<<4) + #define HQC_TYPE_VALUE_IWARP_EDGE (6<<4) + #define HQC_TYPE_VALUE_ISCSI (7<<4) + u32_t unused_0; +} hqc_basic_l_t; + + +/* + * hqc_basic select + */ +#if defined(LITTLE_ENDIAN) + typedef hqc_basic_l_t hqc_basic_t; +#elif defined(BIG_ENDIAN) + typedef hqc_basic_b_t hqc_basic_t; +#endif + + +/* + * hqc_toe_b definition + */ +typedef struct hqc_toe_b +{ + u8_t hqt_type; + u8_t hqt_knum; + u16_t hqt_hdr_nbytes; + #define HQT_HDR_NBYTES_VALUE (0x3fff<<0) + #define HQT_HDR_NBYTES_PLUS_TWO (1<<15) + + u16_t unused_0; + u16_t hqt_xsum_boff; +} hqc_toe_b_t; + + +/* + * hqc_toe_l definition + */ +typedef struct hqc_toe_l +{ + u16_t hqt_hdr_nbytes; + #define HQT_HDR_NBYTES_VALUE (0x3fff<<0) + #define HQT_HDR_NBYTES_PLUS_TWO (1<<15) + + u8_t hqt_knum; + u8_t hqt_type; + u16_t hqt_xsum_boff; + u16_t unused_0; +} hqc_toe_l_t; + + +/* + * hqc_toe select + */ +#if defined(LITTLE_ENDIAN) + typedef hqc_toe_l_t hqc_toe_t; +#elif defined(BIG_ENDIAN) + typedef hqc_toe_b_t hqc_toe_t; +#endif + + +/* + * hqc_hole_b definition + */ +typedef struct hqc_hole_b +{ + u8_t hqh_type; + u8_t hqh_knum; + u16_t hqh_hdr_nbytes; + #define HQH_HDR_NBYTES_VALUE (0x3fff<<0) + #define HQH_HDR_NBYTES_PLUS_TWO (1<<15) + + u16_t hqh_hole_bytes; + u16_t hqh_hole_pos; + u8_t hqh_value[4]; + u32_t unused_0; +} hqc_hole_b_t; + + +/* + * hqc_hole_l definition + */ +typedef struct hqc_hole_l +{ + u16_t hqh_hdr_nbytes; + #define HQH_HDR_NBYTES_VALUE (0x3fff<<0) + #define HQH_HDR_NBYTES_PLUS_TWO (1<<15) + + u8_t hqh_knum; + u8_t hqh_type; + u16_t hqh_hole_pos; + u16_t hqh_hole_bytes; + u8_t hqh_value[4]; + u32_t unused_0; +} hqc_hole_l_t; + + +/* + * hqc_hole select + */ +#if defined(LITTLE_ENDIAN) + typedef hqc_hole_l_t hqc_hole_t; +#elif defined(BIG_ENDIAN) + typedef hqc_hole_b_t hqc_hole_t; +#endif + + +/* + * hqc_lso_cap_b definition + */ +typedef struct hqc_lso_cap_b +{ + u8_t hqca_type; + u8_t hqca_knum; + u16_t hqca_hdr_nbytes; + #define HQCA_HDR_NBYTES_VALUE (0x3fff<<0) + #define HQCA_HDR_NBYTES_PLUS_TWO (1<<15) + + u16_t hqca_cap_hdr_nbytes; + u16_t hqca_l2hdr_nbytes; + u32_t hqca_vlan_tag; + u32_t hqca_ipv6_exthdr_len; + #define HQDU_FLAGS_IPV6_EXTHDR_LEN (0x7fffffffUL<<0) + #define HQDU_FLAGS_BSEQ_FLAGS_LAST_PKT (1UL<<31) +} hqc_lso_cap_b_t; + + +/* + * hqc_lso_cap_l definition + */ +typedef struct hqc_lso_cap_l +{ + u16_t hqca_hdr_nbytes; + #define HQCA_HDR_NBYTES_VALUE (0x3fff<<0) + #define HQCA_HDR_NBYTES_PLUS_TWO (1<<15) + + u8_t hqca_knum; + u8_t hqca_type; + u16_t hqca_l2hdr_nbytes; + u16_t hqca_cap_hdr_nbytes; + u32_t hqca_vlan_tag; + u32_t hqca_ipv6_exthdr_len; + #define HQDU_FLAGS_IPV6_EXTHDR_LEN (0x7fffffffUL<<0) + #define HQDU_FLAGS_BSEQ_FLAGS_LAST_PKT (1UL<<31) +} hqc_lso_cap_l_t; + + +/* + * hqc_lso_cap select + */ +#if defined(LITTLE_ENDIAN) + typedef hqc_lso_cap_l_t hqc_lso_cap_t; +#elif defined(BIG_ENDIAN) + typedef hqc_lso_cap_b_t hqc_lso_cap_t; +#endif + + +/* + * hqc_lso_dup_b definition + */ +typedef struct hqc_lso_dup_b +{ + u8_t hqdu_type; + u8_t hqdu_knum; + u16_t hqdu_hdr_nbytes; + #define HQDU_HDR_NBYTES_VALUE (0x3fff<<0) + #define HQDU_HDR_NBYTES_PLUS_TWO (1<<15) + + u32_t hqdu_flags_bseq; + #define HQDU_FLAGS_BSEQ_BSEQ_VALUE (0x7fffffffUL<<0) + #define HQDU_FLAGS_BSEQ_FLAGS_LAST_PKT (1UL<<31) + +} hqc_lso_dup_b_t; + + +/* + * hqc_lso_dup_l definition + */ +typedef struct hqc_lso_dup_l +{ + u16_t hqdu_hdr_nbytes; + #define HQDU_HDR_NBYTES_VALUE (0x3fff<<0) + #define HQDU_HDR_NBYTES_PLUS_TWO (1<<15) + + u8_t hqdu_knum; + u8_t hqdu_type; + u32_t hqdu_flags_bseq; + #define HQDU_FLAGS_BSEQ_BSEQ_VALUE (0x7fffffffUL<<0) + #define HQDU_FLAGS_BSEQ_FLAGS_LAST_PKT (1UL<<31) + +} hqc_lso_dup_l_t; + + +/* + * hqc_lso_dup select + */ +#if defined(LITTLE_ENDIAN) + typedef hqc_lso_dup_l_t hqc_lso_dup_t; +#elif defined(BIG_ENDIAN) + typedef hqc_lso_dup_b_t hqc_lso_dup_t; +#endif + + +/* + * hqc_iwarp_std_b definition + */ +typedef struct hqc_iwarp_std_b +{ + u8_t hqis_type; + u8_t hqis_knum; + u16_t hqis_hdr_nbytes; + #define HQIS_HDR_NBYTES_HDR_NBYTES_VALUE (0x3fff<<0) + + u16_t hqis_l5_hdr_nbytes; + u16_t hqis_xsum_boff; +} hqc_iwarp_std_b_t; + + +/* + * hqc_iwarp_std_l definition + */ +typedef struct hqc_iwarp_std_l +{ + u16_t hqis_hdr_nbytes; + #define HQIS_HDR_NBYTES_HDR_NBYTES_VALUE (0x3fff<<0) + + u8_t hqis_knum; + u8_t hqis_type; + u16_t hqis_xsum_boff; + u16_t hqis_l5_hdr_nbytes; +} hqc_iwarp_std_l_t; + + +/* + * hqc_iwarp_std select + */ +#if defined(LITTLE_ENDIAN) + typedef hqc_iwarp_std_l_t hqc_iwarp_std_t; +#elif defined(BIG_ENDIAN) + typedef hqc_iwarp_std_b_t hqc_iwarp_std_t; +#endif + + +/* + * hqc_iwarp_edge_b definition + */ +typedef struct hqc_iwarp_edge_b +{ + u8_t hqie_type; + u8_t hqie_knum; + u16_t hqie_hdr_nbytes; + #define HQIE_HDR_NBYTES_HDR_NBYTES_VALUE (0x3fff<<0) + + u16_t hqie_l5_hdr_nbytes; + u16_t hqie_xsum_boff; + u32_t hqie_marker_value; + u32_t unused_0; +} hqc_iwarp_edge_b_t; + + +/* + * hqc_iwarp_edge_l definition + */ +typedef struct hqc_iwarp_edge_l +{ + u16_t hqie_hdr_nbytes; + #define HQIE_HDR_NBYTES_HDR_NBYTES_VALUE (0x3fff<<0) + + u8_t hqie_knum; + u8_t hqie_type; + u16_t hqie_xsum_boff; + u16_t hqie_l5_hdr_nbytes; + u32_t hqie_marker_value; + u32_t unused_0; +} hqc_iwarp_edge_l_t; + + +/* + * hqc_iwarp_edge select + */ +#if defined(LITTLE_ENDIAN) + typedef hqc_iwarp_edge_l_t hqc_iwarp_edge_t; +#elif defined(BIG_ENDIAN) + typedef hqc_iwarp_edge_b_t hqc_iwarp_edge_t; +#endif + + +/* + * rx_bd_b definition + */ +typedef struct rx_bd_b +{ + u32_t rx_bd_haddr_hi; + u32_t rx_bd_haddr_lo; + u32_t rx_bd_len; + u16_t unused_0; + u16_t rx_bd_flags; + #define RX_BD_FLAGS_NOPUSH (1<<0) + #define RX_BD_FLAGS_DUMMY (1<<1) + #define RX_BD_FLAGS_END (1<<2) + #define RX_BD_FLAGS_START (1<<3) + #define RX_BD_FLAGS_INTRMDT (1<<4) // intermediate boundary for partial io buffer + #define RX_BD_FLAGS_HEADERSPLIT (1<<5) +} rx_bd_b_t; + + +/* + * rx_bd_l definition + */ +typedef struct rx_bd_l +{ + u32_t rx_bd_haddr_hi; + u32_t rx_bd_haddr_lo; + u32_t rx_bd_len; + u16_t rx_bd_flags; + #define RX_BD_FLAGS_NOPUSH (1<<0) + #define RX_BD_FLAGS_DUMMY (1<<1) + #define RX_BD_FLAGS_END (1<<2) + #define RX_BD_FLAGS_START (1<<3) + #define RX_BD_FLAGS_INTRMDT (1<<4) // intermediate boundary for partial io buffer + #define RX_BD_FLAGS_HEADERSPLIT (1<<5) + u16_t unused_0; +} rx_bd_l_t; + + +/* + * rx_bd select + */ +#if defined(LITTLE_ENDIAN) + typedef rx_bd_l_t rx_bd_t; +#elif defined(BIG_ENDIAN) + typedef rx_bd_b_t rx_bd_t; +#endif + + +/* + * rx_generic_bd_b definition + */ +typedef struct rx_generic_bd_b +{ + u16_t rx_generic_bd_tag; + u16_t rx_generic_bd_haddr_hi; + u32_t rx_generic_bd_haddr_lo; + #define RX_GENERIC_BD_HADDR_LO_SELECT (0x3UL<<0) + #define RX_GENERIC_BD_HADDR_LO_ADDR (0x3fffUL<<2) + + u32_t rx_generic_bd_len; + u16_t unused_0; + u16_t rx_generic_bd_flags; + #define RX_GENERIC_BD_FLAGS_END (1<<2) + #define RX_GENERIC_BD_FLAGS_START (1<<3) + +} rx_generic_bd_b_t; + + +/* + * rx_generic_bd_l definition + */ +typedef struct rx_generic_bd_l +{ + u16_t rx_generic_bd_haddr_hi; + u16_t rx_generic_bd_tag; + u32_t rx_generic_bd_haddr_lo; + #define RX_GENERIC_BD_HADDR_LO_SELECT (0x3UL<<0) + #define RX_GENERIC_BD_HADDR_LO_ADDR (0x3fffUL<<2) + + u32_t rx_generic_bd_len; + u16_t rx_generic_bd_flags; + #define RX_GENERIC_BD_FLAGS_END (1<<2) + #define RX_GENERIC_BD_FLAGS_START (1<<3) + + u16_t unused_0; +} rx_generic_bd_l_t; + + +/* + * rx_generic_bd select + */ +#if defined(LITTLE_ENDIAN) + typedef rx_generic_bd_l_t rx_generic_bd_t; +#elif defined(BIG_ENDIAN) + typedef rx_generic_bd_b_t rx_generic_bd_t; +#endif + + +/* + * attentions definition + */ +typedef struct attentions +{ + u32_t attentions_bits; + #define ATTENTIONS_BITS_LINK_STATE (1UL<<0) + #define ATTENTIONS_BITS_TX_SCHEDULER_ABORT (1UL<<1) + #define ATTENTIONS_BITS_TX_BD_READ_ABORT (1UL<<2) + #define ATTENTIONS_BITS_TX_BD_CACHE_ABORT (1UL<<3) + #define ATTENTIONS_BITS_TX_PROCESSOR_ABORT (1UL<<4) + #define ATTENTIONS_BITS_TX_DMA_ABORT (1UL<<5) + #define ATTENTIONS_BITS_TX_PATCHUP_ABORT (1UL<<6) + #define ATTENTIONS_BITS_TX_ASSEMBLER_ABORT (1UL<<7) + #define ATTENTIONS_BITS_RX_PARSER_MAC_ABORT (1UL<<8) + #define ATTENTIONS_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) + #define ATTENTIONS_BITS_RX_MBUF_ABORT (1UL<<10) + #define ATTENTIONS_BITS_RX_LOOKUP_ABORT (1UL<<11) + #define ATTENTIONS_BITS_RX_PROCESSOR_ABORT (1UL<<12) + #define ATTENTIONS_BITS_RX_V2P_ABORT (1UL<<13) + #define ATTENTIONS_BITS_RX_BD_CACHE_ABORT (1UL<<14) + #define ATTENTIONS_BITS_RX_DMA_ABORT (1UL<<15) + #define ATTENTIONS_BITS_COMPLETION_ABORT (1UL<<16) + #define ATTENTIONS_BITS_HOST_COALESCE_ABORT (1UL<<17) + #define ATTENTIONS_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) + #define ATTENTIONS_BITS_CONTEXT_ABORT (1UL<<19) + #define ATTENTIONS_BITS_CMD_SCHEDULER_ABORT (1UL<<20) + #define ATTENTIONS_BITS_CMD_PROCESSOR_ABORT (1UL<<21) + #define ATTENTIONS_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) + #define ATTENTIONS_BITS_MAC_ABORT (1UL<<23) + #define ATTENTIONS_BITS_TIMER_ABORT (1UL<<24) + #define ATTENTIONS_BITS_DMAE_ABORT (1UL<<25) + #define ATTENTIONS_BITS_FLSH_ABORT (1UL<<26) + #define ATTENTIONS_BITS_GRC_ABORT (1UL<<27) + #define ATTENTIONS_BITS_EPB_ERROR (1UL<<30) + #define ATTENTIONS_BITS_PARITY_ERROR (1UL<<31) + +} attentions_t; + + +/* + * status_block_b definition + */ +typedef struct status_block_b +{ + u32_t status_attn_bits; + #define STATUS_ATTN_BITS_LINK_STATE (1UL<<0) + #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1UL<<1) + #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1UL<<2) + #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1UL<<3) + #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1UL<<4) + #define STATUS_ATTN_BITS_TX_DMA_ABORT (1UL<<5) + #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1UL<<6) + #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1UL<<7) + #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1UL<<8) + #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) + #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1UL<<10) + #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1UL<<11) + #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1UL<<12) + #define STATUS_ATTN_BITS_RX_V2P_ABORT (1UL<<13) + #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1UL<<14) + #define STATUS_ATTN_BITS_RX_DMA_ABORT (1UL<<15) + #define STATUS_ATTN_BITS_COMPLETION_ABORT (1UL<<16) + #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1UL<<17) + #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) + #define STATUS_ATTN_BITS_CONTEXT_ABORT (1UL<<19) + #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1UL<<20) + #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1UL<<21) + #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) + #define STATUS_ATTN_BITS_MAC_ABORT (1UL<<23) + #define STATUS_ATTN_BITS_TIMER_ABORT (1UL<<24) + #define STATUS_ATTN_BITS_DMAE_ABORT (1UL<<25) + #define STATUS_ATTN_BITS_FLSH_ABORT (1UL<<26) + #define STATUS_ATTN_BITS_GRC_ABORT (1UL<<27) + #define STATUS_ATTN_BITS_EPB_ERROR (1UL<<30) + #define STATUS_ATTN_BITS_PARITY_ERROR (1UL<<31) + + u32_t status_attn_bits_ack; + u16_t status_tx_quick_consumer_index0; + u16_t status_tx_quick_consumer_index1; + u16_t status_tx_quick_consumer_index2; + u16_t status_tx_quick_consumer_index3; + u16_t status_rx_quick_consumer_index0; + u16_t status_rx_quick_consumer_index1; + u16_t status_rx_quick_consumer_index2; + u16_t status_rx_quick_consumer_index3; + u16_t status_rx_quick_consumer_index4; + u16_t status_rx_quick_consumer_index5; + u16_t status_rx_quick_consumer_index6; + u16_t status_rx_quick_consumer_index7; + u16_t status_rx_quick_consumer_index8; + u16_t status_rx_quick_consumer_index9; + u16_t status_rx_quick_consumer_index10; + u16_t status_rx_quick_consumer_index11; + u16_t status_rx_quick_consumer_index12; + u16_t status_rx_quick_consumer_index13; + u16_t status_rx_quick_consumer_index14; + u16_t status_rx_quick_consumer_index15; + u16_t status_completion_producer_index; + u16_t status_cmd_consumer_index; + u16_t status_idx; + u8_t unused_0; + u8_t status_blk_num; + u32_t unused_1[2]; + #if (STATUS_BLOCK_SPACING > 64) + u32_t unused_z[STATUS_BLOCK_SPACING/4-64/4]; + #endif + +} status_block_b_t; + + +/* + * status_block_l definition + */ +typedef struct status_block_l +{ + u32_t status_attn_bits; + #define STATUS_ATTN_BITS_LINK_STATE (1UL<<0) + #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1UL<<1) + #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1UL<<2) + #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1UL<<3) + #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1UL<<4) + #define STATUS_ATTN_BITS_TX_DMA_ABORT (1UL<<5) + #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1UL<<6) + #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1UL<<7) + #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1UL<<8) + #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) + #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1UL<<10) + #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1UL<<11) + #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1UL<<12) + #define STATUS_ATTN_BITS_RX_V2P_ABORT (1UL<<13) + #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1UL<<14) + #define STATUS_ATTN_BITS_RX_DMA_ABORT (1UL<<15) + #define STATUS_ATTN_BITS_COMPLETION_ABORT (1UL<<16) + #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1UL<<17) + #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) + #define STATUS_ATTN_BITS_CONTEXT_ABORT (1UL<<19) + #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1UL<<20) + #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1UL<<21) + #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) + #define STATUS_ATTN_BITS_MAC_ABORT (1UL<<23) + #define STATUS_ATTN_BITS_TIMER_ABORT (1UL<<24) + #define STATUS_ATTN_BITS_DMAE_ABORT (1UL<<25) + #define STATUS_ATTN_BITS_FLSH_ABORT (1UL<<26) + #define STATUS_ATTN_BITS_GRC_ABORT (1UL<<27) + #define STATUS_ATTN_BITS_EPB_ERROR (1UL<<30) + #define STATUS_ATTN_BITS_PARITY_ERROR (1UL<<31) + + u32_t status_attn_bits_ack; + u16_t status_tx_quick_consumer_index1; + u16_t status_tx_quick_consumer_index0; + u16_t status_tx_quick_consumer_index3; + u16_t status_tx_quick_consumer_index2; + u16_t status_rx_quick_consumer_index1; + u16_t status_rx_quick_consumer_index0; + u16_t status_rx_quick_consumer_index3; + u16_t status_rx_quick_consumer_index2; + u16_t status_rx_quick_consumer_index5; + u16_t status_rx_quick_consumer_index4; + u16_t status_rx_quick_consumer_index7; + u16_t status_rx_quick_consumer_index6; + u16_t status_rx_quick_consumer_index9; + u16_t status_rx_quick_consumer_index8; + u16_t status_rx_quick_consumer_index11; + u16_t status_rx_quick_consumer_index10; + u16_t status_rx_quick_consumer_index13; + u16_t status_rx_quick_consumer_index12; + u16_t status_rx_quick_consumer_index15; + u16_t status_rx_quick_consumer_index14; + u16_t status_cmd_consumer_index; + u16_t status_completion_producer_index; + u8_t status_blk_num; + u8_t unused_0; + u16_t status_idx; + u32_t unused_1[2]; + #if (STATUS_BLOCK_SPACING > 64) + u32_t unused_z[STATUS_BLOCK_SPACING/4-64/4]; + #endif + +} status_block_l_t; + + +/* + * status_block select + */ +#if defined(LITTLE_ENDIAN) + typedef status_block_l_t status_block_t; +#elif defined(BIG_ENDIAN) + typedef status_block_b_t status_block_t; +#endif + + +/* + * status_per_cpu_block_b definition + */ +typedef struct status_per_cpu_block_b +{ + u16_t status_pcpu_tx_quick_consumer_index; + u16_t status_pcpu_rx_quick_consumer_index; + u16_t status_pcpu_completion_producer_index; + u16_t status_pcpu_cmd_consumer_index; + u32_t unused_0; + u16_t status_pcpu_idx; + u8_t unused_1; + u8_t status_pcpu_blk_num; + u32_t unused_z[STATUS_BLOCK_SPACING/4-16/4]; + +} status_per_cpu_block_b_t; + + +/* + * status_per_cpu_block_l definition + */ +typedef struct status_per_cpu_block_l +{ + u16_t status_pcpu_rx_quick_consumer_index; + u16_t status_pcpu_tx_quick_consumer_index; + u16_t status_pcpu_cmd_consumer_index; + u16_t status_pcpu_completion_producer_index; + u32_t unused_0; + u8_t status_pcpu_blk_num; + u8_t unused_1; + u16_t status_pcpu_idx; + u32_t unused_z[STATUS_BLOCK_SPACING/4-16/4]; + +} status_per_cpu_block_l_t; + + +/* + * status_per_cpu_block select + */ +#if defined(LITTLE_ENDIAN) + typedef status_per_cpu_block_l_t status_per_cpu_block_t; +#elif defined(BIG_ENDIAN) + typedef status_per_cpu_block_b_t status_per_cpu_block_t; +#endif + + +/* + * status_blk_combined definition + */ +typedef struct status_blk_combined +{ + status_block_t deflt; + status_per_cpu_block_t proc[8]; +} status_blk_combined_t; + + +/* + * statistics_block definition + */ +typedef struct statistics_block +{ + u32_t stat_IfHCInOctets_hi; + u32_t stat_IfHCInOctets_lo; + u32_t stat_IfHCInBadOctets_hi; + u32_t stat_IfHCInBadOctets_lo; + u32_t stat_IfHCOutOctets_hi; + u32_t stat_IfHCOutOctets_lo; + u32_t stat_IfHCOutBadOctets_hi; + u32_t stat_IfHCOutBadOctets_lo; + u32_t stat_IfHCInUcastPkts_hi; + u32_t stat_IfHCInUcastPkts_lo; + u32_t stat_IfHCInMulticastPkts_hi; + u32_t stat_IfHCInMulticastPkts_lo; + u32_t stat_IfHCInBroadcastPkts_hi; + u32_t stat_IfHCInBroadcastPkts_lo; + u32_t stat_IfHCOutUcastPkts_hi; + u32_t stat_IfHCOutUcastPkts_lo; + u32_t stat_IfHCOutMulticastPkts_hi; + u32_t stat_IfHCOutMulticastPkts_lo; + u32_t stat_IfHCOutBroadcastPkts_hi; + u32_t stat_IfHCOutBroadcastPkts_lo; + u32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; + u32_t stat_Dot3StatsCarrierSenseErrors; + u32_t stat_Dot3StatsFCSErrors; + u32_t stat_Dot3StatsAlignmentErrors; + u32_t stat_Dot3StatsSingleCollisionFrames; + u32_t stat_Dot3StatsMultipleCollisionFrames; + u32_t stat_Dot3StatsDeferredTransmissions; + u32_t stat_Dot3StatsExcessiveCollisions; + u32_t stat_Dot3StatsLateCollisions; + u32_t stat_EtherStatsCollisions; + u32_t stat_EtherStatsFragments; + u32_t stat_EtherStatsJabbers; + u32_t stat_EtherStatsUndersizePkts; + u32_t stat_EtherStatsOverrsizePkts; + u32_t stat_EtherStatsPktsRx64Octets; + u32_t stat_EtherStatsPktsRx65Octetsto127Octets; + u32_t stat_EtherStatsPktsRx128Octetsto255Octets; + u32_t stat_EtherStatsPktsRx256Octetsto511Octets; + u32_t stat_EtherStatsPktsRx512Octetsto1023Octets; + u32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; + u32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; + u32_t stat_EtherStatsPktsTx64Octets; + u32_t stat_EtherStatsPktsTx65Octetsto127Octets; + u32_t stat_EtherStatsPktsTx128Octetsto255Octets; + u32_t stat_EtherStatsPktsTx256Octetsto511Octets; + u32_t stat_EtherStatsPktsTx512Octetsto1023Octets; + u32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; + u32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; + u32_t stat_XonPauseFramesReceived; + u32_t stat_XoffPauseFramesReceived; + u32_t stat_OutXonSent; + u32_t stat_OutXoffSent; + u32_t stat_FlowControlDone; + u32_t stat_MacControlFramesReceived; + u32_t stat_XoffStateEntered; + u32_t stat_IfInFramesL2FilterDiscards; + u32_t stat_IfInRuleCheckerDiscards; + u32_t stat_IfInFTQDiscards; + u32_t stat_IfInMBUFDiscards; + u32_t stat_IfInRuleCheckerP4Hit; + u32_t stat_CatchupInRuleCheckerDiscards; + u32_t stat_CatchupInFTQDiscards; + u32_t stat_CatchupInMBUFDiscards; + u32_t stat_CatchupInRuleCheckerP4Hit; + u32_t stat_GenStat00; + u32_t stat_GenStat01; + u32_t stat_GenStat02; + u32_t stat_GenStat03; + u32_t stat_GenStat04; + u32_t stat_GenStat05; + u32_t stat_GenStat06; + u32_t stat_GenStat07; + u32_t stat_GenStat08; + u32_t stat_GenStat09; + u32_t stat_GenStat10; + u32_t stat_GenStat11; + u32_t stat_GenStat12; + u32_t stat_GenStat13; + u32_t stat_GenStat14; + u32_t stat_GenStat15; +} statistics_block_t; + + +/* + * l2_fhdr_b definition + */ +typedef struct l2_fhdr_b +{ + u16_t l2_fhdr_errors; + #define L2_FHDR_ERRORS_ABORT_PKT (1<<0) + #define L2_FHDR_ERRORS_BAD_CRC (1<<1) + #define L2_FHDR_ERRORS_PHY_DECODE (1<<2) + #define L2_FHDR_ERRORS_ALIGNMENT (1<<3) + #define L2_FHDR_ERRORS_TOO_SHORT (1<<4) + #define L2_FHDR_ERRORS_GIANT_FRAME (1<<5) + #define L2_FHDR_ERRORS_IP_BAD_XSUM (1<<10) + #define L2_FHDR_ERRORS_TCP_BAD_XSUM (1<<12) + #define L2_FHDR_ERRORS_UDP_BAD_XSUM (1<<15) + + u16_t l2_fhdr_status; + #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) + #define L2_FHDR_STATUS_RULE_P2 (1<<3) + #define L2_FHDR_STATUS_RULE_P3 (1<<4) + #define L2_FHDR_STATUS_RULE_P4 (1<<5) + #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) + #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) + #define L2_FHDR_STATUS_RSS_HASH (1<<8) + #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) + #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) + #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) + + u32_t l2_fhdr_hash; + u16_t l2_fhdr_pkt_len; + u16_t l2_fhdr_vlan_tag; + u16_t l2_fhdr_ip_xsum; + u16_t l2_fhdr_tcp_udp_xsum; +} l2_fhdr_b_t; + + +/* + * l2_fhdr_l definition + */ +typedef struct l2_fhdr_l +{ + u16_t l2_fhdr_status; + #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) + #define L2_FHDR_STATUS_RULE_P2 (1<<3) + #define L2_FHDR_STATUS_RULE_P3 (1<<4) + #define L2_FHDR_STATUS_RULE_P4 (1<<5) + #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) + #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) + #define L2_FHDR_STATUS_RSS_HASH (1<<8) + #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) + #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) + #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) + + u16_t l2_fhdr_errors; + #define L2_FHDR_ERRORS_ABORT_PKT (1<<0) + #define L2_FHDR_ERRORS_BAD_CRC (1<<1) + #define L2_FHDR_ERRORS_PHY_DECODE (1<<2) + #define L2_FHDR_ERRORS_ALIGNMENT (1<<3) + #define L2_FHDR_ERRORS_TOO_SHORT (1<<4) + #define L2_FHDR_ERRORS_GIANT_FRAME (1<<5) + #define L2_FHDR_ERRORS_IP_BAD_XSUM (1<<10) + #define L2_FHDR_ERRORS_TCP_BAD_XSUM (1<<12) + #define L2_FHDR_ERRORS_UDP_BAD_XSUM (1<<15) + + u32_t l2_fhdr_hash; + u16_t l2_fhdr_vlan_tag; + u16_t l2_fhdr_pkt_len; + u16_t l2_fhdr_tcp_udp_xsum; + u16_t l2_fhdr_ip_xsum; +} l2_fhdr_l_t; + + +/* + * l2_fhdr select + */ +#if defined(LITTLE_ENDIAN) + typedef l2_fhdr_l_t l2_fhdr_t; +#elif defined(BIG_ENDIAN) + typedef l2_fhdr_b_t l2_fhdr_t; +#endif + +/* + * l2_fhdr_ooo_b definition + */ +typedef struct l2_fhdr_ooo_b +{ + u8_t l2_fhdr_block_idx; + u8_t l2_fhdr_opcode; + #define L2_FHDR_OPCODE_ADD_PEN (0) + #define L2_FHDR_OPCODE_ADD_NEW (1) + #define L2_FHDR_OPCODE_ADD_RIGHT (2) + #define L2_FHDR_OPCODE_ADD_LEFT (3) + #define L2_FHDR_OPCODE_JOIN (4) + #define L2_FHDR_OPCODE_NOOP (5) + #define L2_FHDR_OPCODE_CLEAN_UP (10) + u8_t l2_fhdr_drop_size; + u8_t l2_fhdr_drop_block_idx; + u32_t l2_fhdr_icid; + + u16_t l2_fhdr_pkt_len; + u16_t l2_fhdr_vlan_tag; + u16_t l2_fhdr_ip_xsum; + u16_t l2_fhdr_tcp_udp_xsum; +} l2_fhdr_ooo_b_t; + + +/* + * l2_fhdr_ooo_l definition + */ +typedef struct l2_fhdr_ooo_l +{ + u8_t l2_fhdr_drop_block_idx; + u8_t l2_fhdr_drop_size; + u8_t l2_fhdr_opcode; + u8_t l2_fhdr_block_idx; + u32_t l2_fhdr_icid; + + u16_t l2_fhdr_vlan_tag; + u16_t l2_fhdr_pkt_len; + u16_t l2_fhdr_tcp_udp_xsum; + u16_t l2_fhdr_ip_xsum; +} l2_fhdr_ooo_l_t; + +/* + * l2_fhdr_ooo select + */ +#if defined(LITTLE_ENDIAN) + typedef l2_fhdr_ooo_l_t l2_fhdr_ooo_t; +#elif defined(BIG_ENDIAN) + typedef l2_fhdr_ooo_b_t l2_fhdr_ooo_t; +#endif + +/* + * pci_config definition + * offset: 0000 + */ +typedef struct pci_config +{ + u16_t pcicfg_vendor_id; + u16_t pcicfg_device_id; + u16_t pcicfg_command; + #define PCICFG_COMMAND_IO_SPACE (1<<0) + #define PCICFG_COMMAND_MEM_SPACE (1<<1) + #define PCICFG_COMMAND_BUS_MASTER (1<<2) + #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) + #define PCICFG_COMMAND_MWI_CYCLES (1<<4) + #define PCICFG_COMMAND_VGA_SNOOP (1<<5) + #define PCICFG_COMMAND_PERR_ENA (1<<6) + #define PCICFG_COMMAND_STEPPING (1<<7) + #define PCICFG_COMMAND_SERR_ENA (1<<8) + #define PCICFG_COMMAND_FAST_B2B (1<<9) + #define PCICFG_COMMAND_INT_DISABLE (1<<10) + #define PCICFG_COMMAND_RESERVED (0x1f<<11) + + u16_t pcicfg_status; + #define PCICFG_STATUS_RESERVED1 (0x7<<0) + #define PCICFG_STATUS_INT_STATUS (1<<3) + #define PCICFG_STATUS_CAP_LIST (1<<4) + #define PCICFG_STATUS_66MHZ_CAP (1<<5) + #define PCICFG_STATUS_RESERVED2 (1<<6) + #define PCICFG_STATUS_FAST_B2B_CAP (1<<7) + #define PCICFG_STATUS_SIG_PERR_TE (1<<8) + #define PCICFG_STATUS_MSTR_PERR_XI (1<<8) + #define PCICFG_STATUS_DEVSEL_TIMING (0x3<<9) + #define PCICFG_STATUS_SIG_TGT_ABT (1<<11) + #define PCICFG_STATUS_RCV_TGT_ABT (1<<12) + #define PCICFG_STATUS_RCV_MSTR_ABT (1<<13) + #define PCICFG_STATUS_SIG_SERR (1<<14) + #define PCICFG_STATUS_PAR_ERR (1<<15) + + u32_t pcicfg_class_code; + #define PCICFG_CLASS_CODE_REV_ID (0xffUL<<0) + #define PCICFG_CLASS_CODE_VALUE (0xffffffUL<<8) + + u8_t pcicfg_cache_line_size; + u8_t pcicfg_latency_timer; + u8_t pcicfg_header_type; + u8_t pcicfg_bist; + u32_t pcicfg_bar_1; + #define PCICFG_BAR_1_MEM_SPACE (1UL<<0) + #define PCICFG_BAR_1_SPACE_TYPE (0x3UL<<1) + #define PCICFG_BAR_1_PREFETCH (1UL<<3) + #define PCICFG_BAR_1_ADDRESS (0xfffffffUL<<4) + + u32_t pcicfg_bar_2; + #define PCICFG_BAR_2_ADDR (0xffffffffUL<<0) + + u32_t pcicfg_bar_3; + #define PCICFG_BAR_3_MEM_SPACE (1UL<<0) + #define PCICFG_BAR_3_SPACE_TYPE (0x3UL<<1) + #define PCICFG_BAR_3_PREFETCH (1UL<<3) + #define PCICFG_BAR_3_ADDRESS (0xfffffffUL<<4) + + u32_t pcicfg_bar_4; + #define PCICFG_BAR_4_ADDR (0xffffffffUL<<0) + + u32_t pcicfg_bar_5; + u32_t pcicfg_bar_6; + u32_t pcicfg_cardbus_cis; + u16_t pcicfg_subsystem_vendor_id; + u16_t pcicfg_subsystem_id; + u32_t pcicfg_exp_rom_bar; + #define PCICFG_EXP_ROM_BAR_BAR_ENA (1UL<<0) + #define PCICFG_EXP_ROM_BAR_LOW_TE (0x1ffUL<<1) + #define PCICFG_EXP_ROM_BAR_SIZE_TE (0x3fffUL<<10) + #define PCICFG_EXP_ROM_BAR_LOW_XI (0x3ffUL<<1) + #define PCICFG_EXP_ROM_BAR_SIZE_XI (0x1fffUL<<11) + #define PCICFG_EXP_ROM_BAR_ADDRESS (0xffUL<<24) + + u8_t pcicfg_cap_pointer; + u8_t unused_0; + u16_t unused_1; + u32_t unused_2; + u8_t pcicfg_int_line; + u8_t pcicfg_int_pin; + u8_t pcicfg_min_grant; + u8_t pcicfg_maximum_latency; + u8_t pcicfg_pcix_cap_id; + u8_t pcicfg_pcix_next_cap_ptr; + u16_t pcicfg_pcix_command; + #define PCICFG_PCIX_COMMAND_DATA_PAR_ERR (1<<0) + #define PCICFG_PCIX_COMMAND_RELAX_ORDER (1<<1) + #define PCICFG_PCIX_COMMAND_MAX_MEM_READ (0x3<<2) + #define PCICFG_PCIX_COMMAND_MAX_MEM_READ_512 (0<<2) + #define PCICFG_PCIX_COMMAND_MAX_MEM_READ_1K (1<<2) + #define PCICFG_PCIX_COMMAND_MAX_MEM_READ_2K (2<<2) + #define PCICFG_PCIX_COMMAND_MAX_MEM_READ_4K (3<<2) + #define PCICFG_PCIX_COMMAND_MAX_SPLIT (0x7<<4) + #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_1 (0<<4) + #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_2 (1<<4) + #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_3 (2<<4) + #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_4 (3<<4) + #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_8 (4<<4) + #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_12 (5<<4) + #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_16 (6<<4) + #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_32 (7<<4) + #define PCICFG_PCIX_COMMAND_MAX_SPLIT_RESERVED (511<<4) + + u32_t pcicfg_pcix_status; + #define PCICFG_PCIX_STATUS_FUNC_NUM (0x7UL<<0) + #define PCICFG_PCIX_STATUS_DEV_NUM (0x1fUL<<3) + #define PCICFG_PCIX_STATUS_BUS_NUM (0xffUL<<8) + #define PCICFG_PCIX_STATUS_64_BIT (1UL<<16) + #define PCICFG_PCIX_STATUS_MAX_133_ADVERTIZE (1UL<<17) + #define PCICFG_PCIX_STATUS_SPLIT_DISCARD (1UL<<18) + #define PCICFG_PCIX_STATUS_UNEXPECTED_SPLIT (1UL<<19) + #define PCICFG_PCIX_STATUS_DEV_COMPLEX (1UL<<20) + #define PCICFG_PCIX_STATUS_MAX_MEM_READ (0x3UL<<21) + #define PCICFG_PCIX_STATUS_MAX_MEM_READ_512 (0UL<<21) + #define PCICFG_PCIX_STATUS_MAX_MEM_READ_1K (1UL<<21) + #define PCICFG_PCIX_STATUS_MAX_MEM_READ_2K (2UL<<21) + #define PCICFG_PCIX_STATUS_MAX_MEM_READ_4K (3UL<<21) + #define PCICFG_PCIX_STATUS_MAX_SPLIT (0x7UL<<23) + #define PCICFG_PCIX_STATUS_MAX_SPLIT_1 (0UL<<23) + #define PCICFG_PCIX_STATUS_MAX_SPLIT_2 (1UL<<23) + #define PCICFG_PCIX_STATUS_MAX_SPLIT_3 (2UL<<23) + #define PCICFG_PCIX_STATUS_MAX_SPLIT_4 (3UL<<23) + #define PCICFG_PCIX_STATUS_MAX_SPLIT_8 (4UL<<23) + #define PCICFG_PCIX_STATUS_MAX_SPLIT_12 (5UL<<23) + #define PCICFG_PCIX_STATUS_MAX_SPLIT_16 (6UL<<23) + #define PCICFG_PCIX_STATUS_MAX_SPLIT_32 (7UL<<23) + #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE (0x7UL<<26) + #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_1KB (0UL<<26) + #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_2KB (1UL<<26) + #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_4KB (2UL<<26) + #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_8KB (3UL<<26) + #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_16KB (4UL<<26) + #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_32KB (5UL<<26) + #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_64KB (6UL<<26) + #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_128KB (7UL<<26) + #define PCICFG_PCIX_STATUS_SPLIT_ERR (1UL<<29) + #define PCICFG_PCIX_STATUS_RESERVED (0x3UL<<30) + + u8_t pcicfg_pm_cap_id; + u8_t pcicfg_pm_next_cap_ptr; + u16_t pcicfg_pm_capability; + #define PCICFG_PM_CAPABILITY_VERSION (0x3<<0) + #define PCICFG_PM_CAPABILITY_CLOCK (1<<3) + #define PCICFG_PM_CAPABILITY_RESERVED (1<<4) + #define PCICFG_PM_CAPABILITY_DSI (1<<5) + #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<6) + #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<9) + #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<10) + #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<11) + #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<12) + #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<13) + #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<14) + #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<15) + + u16_t pcicfg_pm_csr; + #define PCICFG_PM_CSR_STATE (0x3<<0) + #define PCICFG_PM_CSR_STATE_D0 (0<<0) + #define PCICFG_PM_CSR_STATE_D1 (1<<0) + #define PCICFG_PM_CSR_STATE_D2 (2<<0) + #define PCICFG_PM_CSR_STATE_D3_HOT (3<<0) + #define PCICFG_PM_CSR_RESERVED_TE (0x3f<<2) + #define PCICFG_PM_CSR_RESERVED0_XI (1<<2) + #define PCICFG_PM_CSR_NO_SOFT_RESET_XI (1<<3) + #define PCICFG_PM_CSR_RESERVED1_XI (0xf<<4) + #define PCICFG_PM_CSR_PME_ENABLE (1<<8) + #define PCICFG_PM_CSR_DATA_SEL (0xf<<9) + #define PCICFG_PM_CSR_DATA_SEL_0 (0<<9) + #define PCICFG_PM_CSR_DATA_SEL_1 (1<<9) + #define PCICFG_PM_CSR_DATA_SEL_2 (2<<9) + #define PCICFG_PM_CSR_DATA_SEL_3 (3<<9) + #define PCICFG_PM_CSR_DATA_SEL_4 (4<<9) + #define PCICFG_PM_CSR_DATA_SEL_5 (5<<9) + #define PCICFG_PM_CSR_DATA_SEL_6 (6<<9) + #define PCICFG_PM_CSR_DATA_SEL_7 (7<<9) + #define PCICFG_PM_CSR_DATA_SCALE (0x3<<13) + #define PCICFG_PM_CSR_DATA_SCALE_0 (0<<13) + #define PCICFG_PM_CSR_DATA_SCALE_1 (1<<13) + #define PCICFG_PM_CSR_DATA_SCALE_2 (2<<13) + #define PCICFG_PM_CSR_DATA_SCALE_3 (3<<13) + #define PCICFG_PM_CSR_PME_STATUS (1<<15) + + u8_t pcicfg_pm_csr_bse; + u8_t pcicfg_pm_data; + u8_t pcicfg_vpd_cap_id; + u8_t pcicfg_vpd_next_cap_ptr; + u16_t pcicfg_vpd_flag_addr; + #define PCICFG_VPD_FLAG_ADDR_ADDRESS (0x1fff<<2) + #define PCICFG_VPD_FLAG_ADDR_FLAG (1<<15) + + u32_t pcicfg_vpd_data; + u8_t pcicfg_msi_cap_id; + u8_t pcicfg_msi_next_cap_ptr; + u16_t pcicfg_msi_control; + #define PCICFG_MSI_CONTROL_ENABLE (1<<0) + #define PCICFG_MSI_CONTROL_MCAP (0x7<<1) + #define PCICFG_MSI_CONTROL_MCAP_1 (0<<1) + #define PCICFG_MSI_CONTROL_MCAP_2 (1<<1) + #define PCICFG_MSI_CONTROL_MCAP_4 (2<<1) + #define PCICFG_MSI_CONTROL_MCAP_8 (3<<1) + #define PCICFG_MSI_CONTROL_MCAP_16 (4<<1) + #define PCICFG_MSI_CONTROL_MCAP_32 (5<<1) + #define PCICFG_MSI_CONTROL_MENA (0x7<<4) + #define PCICFG_MSI_CONTROL_MENA_1 (0<<4) + #define PCICFG_MSI_CONTROL_MENA_2 (1<<4) + #define PCICFG_MSI_CONTROL_MENA_4 (2<<4) + #define PCICFG_MSI_CONTROL_MENA_8 (3<<4) + #define PCICFG_MSI_CONTROL_MENA_16 (4<<4) + #define PCICFG_MSI_CONTROL_MENA_32 (5<<4) + #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (1<<7) + #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (1<<8) + + u32_t pcicfg_msi_addr_l; + #define PCICFG_MSI_ADDR_L_VAL (0x3fffffffUL<<2) + + u32_t pcicfg_msi_addr_h; + u16_t pcicfg_msi_data; + u16_t pcicfg_reserved; + u32_t pcicfg_misc_config; + #define PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1UL<<2) + #define PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1UL<<3) + #define PCICFG_MISC_CONFIG_RESERVED1 (1UL<<4) + #define PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1UL<<5) + #define PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1UL<<6) + #define PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1UL<<7) + #define PCICFG_MISC_CONFIG_CORE_RST_REQ (1UL<<8) + #define PCICFG_MISC_CONFIG_CORE_RST_BSY (1UL<<9) + #define PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN (1UL<<10) + #define PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN (1UL<<11) + #define PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN (1UL<<12) + #define PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffUL<<16) + #define PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfUL<<24) + #define PCICFG_MISC_CONFIG_ASIC_ID (0xfUL<<28) + + u32_t pcicfg_misc_status; + #define PCICFG_MISC_STATUS_INTA_VALUE (1UL<<0) + #define PCICFG_MISC_STATUS_32BIT_DET (1UL<<1) + #define PCICFG_MISC_STATUS_M66EN (1UL<<2) + #define PCICFG_MISC_STATUS_PCIX_DET (1UL<<3) + #define PCICFG_MISC_STATUS_PCIX_SPEED (0x3UL<<4) + #define PCICFG_MISC_STATUS_PCIX_SPEED_66 (0UL<<4) + #define PCICFG_MISC_STATUS_PCIX_SPEED_100 (1UL<<4) + #define PCICFG_MISC_STATUS_PCIX_SPEED_133 (2UL<<4) + #define PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3UL<<4) + #define PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE (1UL<<8) + + u32_t pcicfg_pci_clock_control_bits; + #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfUL<<0) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0UL<<0) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1UL<<0) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2UL<<0) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3UL<<0) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4UL<<0) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5UL<<0) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6UL<<0) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7UL<<0) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (15UL<<0) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1UL<<6) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1UL<<7) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7UL<<8) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0UL<<8) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1UL<<8) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2UL<<8) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4UL<<8) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER (1UL<<11) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfUL<<12) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0UL<<12) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1UL<<12) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2UL<<12) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4UL<<12) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8UL<<12) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1UL<<16) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17 (1UL<<17) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1UL<<18) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19 (1UL<<19) + #define PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffUL<<20) + + u32_t unused_3; + u32_t pcicfg_reg_window_address; + #define PCICFG_REG_WINDOW_ADDRESS_VAL (0xfffffUL<<2) + + u32_t unused_4; + u32_t pcicfg_reg_window; + u32_t pcicfg_int_ack_cmd; + #define PCICFG_INT_ACK_CMD_INDEX (0xffffUL<<0) + #define PCICFG_INT_ACK_CMD_INDEX_VALID (1UL<<16) + #define PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1UL<<17) + #define PCICFG_INT_ACK_CMD_MASK_INT (1UL<<18) + #define PCICFG_INT_ACK_CMD_INTERRUPT_NUM (0xfUL<<24) + + u32_t pcicfg_status_bit_set_cmd; + u32_t pcicfg_status_bit_clear_cmd; + u32_t pcicfg_mailbox_queue_addr; + u32_t pcicfg_mailbox_queue_data; + u32_t unused_5[2]; + u8_t pcicfg_msix_cap_id; + u8_t pcicfg_msix_next_cap_ptr; + u16_t pcicfg_msix_control; + #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<0) + #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<11) + #define PCICFG_MSIX_CONTROL_FUNC_MASK (1<<14) + #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (1<<15) + + u32_t pcicfg_msix_tbl_off_bir; + #define PCICFG_MSIX_TBL_OFF_BIR_TABLE_BIR (0x7UL<<0) + #define PCICFG_MSIX_TBL_OFF_BIR_TABLE_OFFSET (0x1fffffffUL<<3) + + u32_t pcicfg_msix_pba_off_bir; + #define PCICFG_MSIX_PBA_OFF_BIR_PBA_BIR (0x7UL<<0) + #define PCICFG_MSIX_PBA_OFF_BIR_PBA_OFFSET (0x1fffffffUL<<3) + + u8_t pcicfg_pcie_cap_id; + u8_t pcicfg_pcie_next_cap_ptr; + u16_t pcicfg_pcie_capability; + #define PCICFG_PCIE_CAPABILITY_VER (0xf<<0) + #define PCICFG_PCIE_CAPABILITY_TYPE (0xf<<4) + + u32_t pcicfg_device_capability; + #define PCICFG_DEVICE_CAPABILITY_MAX_PAYLOAD (0x7UL<<0) + #define PCICFG_DEVICE_CAPABILITY_PHANTOM_SUPPT (0x3UL<<3) + #define PCICFG_DEVICE_CAPABILITY_EXT_TAG_SUPPT (1UL<<5) + #define PCICFG_DEVICE_CAPABILITY_EP_L0S_ACCP_LAT (0x7UL<<6) + #define PCICFG_DEVICE_CAPABILITY_EP_L1_ACCP_LAT (0x7UL<<9) + + u16_t pcicfg_device_control; + #define PCICFG_DEVICE_CONTROL_CORR_ERR_REP_ENA (1<<0) + #define PCICFG_DEVICE_CONTROL_NON_FATAL_REP_ENA (1<<1) + #define PCICFG_DEVICE_CONTROL_FATAL_REP_ENA (1<<2) + #define PCICFG_DEVICE_CONTROL_UNSUP_REQ_ENA (1<<3) + #define PCICFG_DEVICE_CONTROL_RELAX_ENA (1<<4) + #define PCICFG_DEVICE_CONTROL_MAX_PAYLOAD (0x7<<5) + #define PCICFG_DEVICE_CONTROL_EXT_TAG_ENA (1<<8) + #define PCICFG_DEVICE_CONTROL_AUX_PWR_PM_ENA (1<<10) + #define PCICFG_DEVICE_CONTROL_ENA_NO_SNOOP (1<<11) + #define PCICFG_DEVICE_CONTROL_MAX_RD_REQ (0x7<<12) + + u16_t pcicfg_device_status; + #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) + #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) + #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) + #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) + #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) + #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) + + u32_t pcicfg_link_capability; + #define PCICFG_LINK_CAPABILITY_MAX_LINK_SPEED (0xfUL<<0) + #define PCICFG_LINK_CAPABILITY_MAX_LINK_SPEED_2_5 (1UL<<0) + #define PCICFG_LINK_CAPABILITY_MAX_LINK_SPEED_5 (2UL<<0) + #define PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH (0x3fUL<<4) + #define PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH_1 (1UL<<4) + #define PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH_2 (2UL<<4) + #define PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH_4 (4UL<<4) + #define PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH_8 (8UL<<4) + #define PCICFG_LINK_CAPABILITY_ASPM_SUPT (0x3UL<<10) + #define PCICFG_LINK_CAPABILITY_ASPM_SUPT_RES_0 (0UL<<10) + #define PCICFG_LINK_CAPABILITY_ASPM_SUPT_L0S (0UL<<10) + #define PCICFG_LINK_CAPABILITY_ASPM_SUPT_RES_2 (0UL<<10) + #define PCICFG_LINK_CAPABILITY_ASPM_SUPT_L0S_L1 (0UL<<10) + #define PCICFG_LINK_CAPABILITY_L0S_EXIT_LAT (0x7UL<<12) + #define PCICFG_LINK_CAPABILITY_L0S_EXIT_LAT_1_2 (5UL<<12) + #define PCICFG_LINK_CAPABILITY_L0S_EXIT_LAT_2_4 (6UL<<12) + #define PCICFG_LINK_CAPABILITY_L1_EXIT_LAT (0x7UL<<15) + #define PCICFG_LINK_CAPABILITY_L1_EXIT_LAT_1_2 (1UL<<15) + #define PCICFG_LINK_CAPABILITY_L1_EXIT_LAT_2_4 (2UL<<15) + #define PCICFG_LINK_CAPABILITY_CLK_PWR_MGMT (1UL<<18) + #define PCICFG_LINK_CAPABILITY_PORT_NUMBER (0xffUL<<24) + + u16_t pcicfg_link_control; + #define PCICFG_LINK_CONTROL_ASPM_CTRL (0x3<<0) + #define PCICFG_LINK_CONTROL_RD_COMP_BOUND (1<<3) + #define PCICFG_LINK_CONTROL_RD_COMP_BOUND_64 (0<<3) + #define PCICFG_LINK_CONTROL_RD_COMP_BOUND_128 (1<<3) + #define PCICFG_LINK_CONTROL_LINK_CR_COMMON_CLK (1<<6) + #define PCICFG_LINK_CONTROL_LINK_CR_EXT_SYNC (1<<7) + + u16_t pcicfg_link_status; + #define PCICFG_LINK_STATUS_SPEED (0xf<<0) + #define PCICFG_LINK_STATUS_NEG_LINK_WIDTH (0x3f<<4) + #define PCICFG_LINK_STATUS_TRAINING_ERR (1<<10) + #define PCICFG_LINK_STATUS_TRAINING (1<<11) + #define PCICFG_LINK_STATUS_SLOT_CLK (1<<12) + + u32_t pcicfg_slot_capability; + u16_t pcicfg_slot_control; + u16_t pcicfg_slot_status; + u16_t pcicfg_root_control; + u16_t pcicfg_root_cap; + u32_t pcicfg_root_status; + u32_t pcicfg_device_capability_2; + #define PCICFG_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP (0xfUL<<0) + #define PCICFG_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP_ABCD (15UL<<0) + #define PCICFG_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP (1UL<<4) + + u16_t pcicfg_device_control_2; + #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE (0xf<<0) + #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_50MS (0<<0) + #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_100US (1<<0) + #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_10MS (2<<0) + #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_55MS (3<<0) + #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_210MS (4<<0) + #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_900MS (5<<0) + #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_3_5S (6<<0) + #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_13S (7<<0) + #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_64S (8<<0) + #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_DISABLE (1<<4) + + u16_t pcicfg_device_status_2; + u32_t pcicfg_link_capability_2; + u16_t pcicfg_link_control_2; + #define PCICFG_LINK_CONTROL_2_TARGET_LINK_SPEED (0xf<<0) + #define PCICFG_LINK_CONTROL_2_TARGET_LINK_SPEED_2_5 (0<<0) + #define PCICFG_LINK_CONTROL_2_TARGET_LINK_SPEED_5_0 (1<<0) + #define PCICFG_LINK_CONTROL_2_ENTER_COMPLIANCE (1<<4) + #define PCICFG_LINK_CONTROL_2_HW_AUTO_SPEED_DISABLE (1<<5) + #define PCICFG_LINK_CONTROL_2_SEL_DEEMPHASIS (1<<6) + #define PCICFG_LINK_CONTROL_2_SEL_DEEMPHASIS_0 (0<<6) + #define PCICFG_LINK_CONTROL_2_SEL_DEEMPHASIS_1 (1<<6) + #define PCICFG_LINK_CONTROL_2_TX_MARGIN (0x7<<7) + #define PCICFG_LINK_CONTROL_2_TX_MARGIN_000 (0<<7) + #define PCICFG_LINK_CONTROL_2_TX_MARGIN_001 (1<<7) + #define PCICFG_LINK_CONTROL_2_TX_MARGIN_010 (2<<7) + #define PCICFG_LINK_CONTROL_2_TX_MARGIN_011 (3<<7) + #define PCICFG_LINK_CONTROL_2_TX_MARGIN_100 (4<<7) + #define PCICFG_LINK_CONTROL_2_TX_MARGIN_101 (5<<7) + #define PCICFG_LINK_CONTROL_2_TX_MARGIN_110 (6<<7) + #define PCICFG_LINK_CONTROL_2_TX_MARGIN_111 (7<<7) + + u16_t pcicfg_link_status_2; + u32_t unused_6[8]; + u16_t pcicfg_device_ser_num_cap_id; + u16_t pcicfg_device_ser_num_cap_off; + #define PCICFG_DEVICE_SER_NUM_CAP_OFF_VER (0xf<<0) + #define PCICFG_DEVICE_SER_NUM_CAP_OFF_NEXT (0xfff<<4) + + u32_t pcicfg_lower_ser_num; + u32_t pcicfg_upper_ser_num; + u32_t unused_7; + u16_t pcicfg_adv_err_cap_id; + u16_t pcicfg_adv_err_cap_off; + #define PCICFG_ADV_ERR_CAP_OFF_VER (0xf<<0) + #define PCICFG_ADV_ERR_CAP_OFF_NEXT (0xfff<<4) + + u32_t pcicfg_ucorr_err_status; + #define PCICFG_UCORR_ERR_STATUS_DLPES (1UL<<4) + #define PCICFG_UCORR_ERR_STATUS_PTLPS (1UL<<12) + #define PCICFG_UCORR_ERR_STATUS_FCPES (1UL<<13) + #define PCICFG_UCORR_ERR_STATUS_CTS (1UL<<14) + #define PCICFG_UCORR_ERR_STATUS_CAS (1UL<<15) + #define PCICFG_UCORR_ERR_STATUS_UCS (1UL<<16) + #define PCICFG_UCORR_ERR_STATUS_ROS (1UL<<17) + #define PCICFG_UCORR_ERR_STATUS_MTLPS (1UL<<18) + #define PCICFG_UCORR_ERR_STATUS_ECRCS (1UL<<19) + #define PCICFG_UCORR_ERR_STATUS_URES (1UL<<20) + + u32_t pcicfg_ucorr_err_mask; + #define PCICFG_UCORR_ERR_MASK_DLPEM (1UL<<4) + #define PCICFG_UCORR_ERR_MASK_SDEM (1UL<<5) + #define PCICFG_UCORR_ERR_MASK_PTLPM (1UL<<12) + #define PCICFG_UCORR_ERR_MASK_FCPEM (1UL<<13) + #define PCICFG_UCORR_ERR_MASK_CTM (1UL<<14) + #define PCICFG_UCORR_ERR_MASK_CAM (1UL<<15) + #define PCICFG_UCORR_ERR_MASK_UCM (1UL<<16) + #define PCICFG_UCORR_ERR_MASK_ROM (1UL<<17) + #define PCICFG_UCORR_ERR_MASK_MTLPM (1UL<<18) + #define PCICFG_UCORR_ERR_MASK_ECRCEM (1UL<<19) + #define PCICFG_UCORR_ERR_MASK_UREM (1UL<<20) + + u32_t pcicfg_ucorr_err_sevr; + #define PCICFG_UCORR_ERR_SEVR_DLPES (1UL<<4) + #define PCICFG_UCORR_ERR_SEVR_SDES (1UL<<5) + #define PCICFG_UCORR_ERR_SEVR_PTLPS (1UL<<12) + #define PCICFG_UCORR_ERR_SEVR_FCPES (1UL<<13) + #define PCICFG_UCORR_ERR_SEVR_CTS (1UL<<14) + #define PCICFG_UCORR_ERR_SEVR_CAS (1UL<<15) + #define PCICFG_UCORR_ERR_SEVR_UCS (1UL<<16) + #define PCICFG_UCORR_ERR_SEVR_ROS (1UL<<17) + #define PCICFG_UCORR_ERR_SEVR_MTLPS (1UL<<18) + #define PCICFG_UCORR_ERR_SEVR_ECRCES (1UL<<19) + #define PCICFG_UCORR_ERR_SEVR_URES (1UL<<20) + + u32_t pcicfg_corr_err_status; + #define PCICFG_CORR_ERR_STATUS_RES (1UL<<0) + #define PCICFG_CORR_ERR_STATUS_BDLLPS (1UL<<7) + #define PCICFG_CORR_ERR_STATUS_BTLPS (1UL<<7) + #define PCICFG_CORR_ERR_STATUS_RNRS (1UL<<8) + #define PCICFG_CORR_ERR_STATUS_RTTS (1UL<<12) + #define PCICFG_CORR_ERR_STATUS_ANFS (1UL<<13) + + u32_t pcicfg_corr_err_mask; + #define PCICFG_CORR_ERR_MASK_RES (1UL<<0) + #define PCICFG_CORR_ERR_MASK_BTLPS (1UL<<6) + #define PCICFG_CORR_ERR_MASK_BDLLPS (1UL<<7) + #define PCICFG_CORR_ERR_MASK_RNRS (1UL<<8) + #define PCICFG_CORR_ERR_MASK_RTTS (1UL<<12) + #define PCICFG_CORR_ERR_MASK_ANFM (1UL<<13) + + u32_t pcicfg_adv_err_cap_control; + #define PCICFG_ADV_ERR_CAP_CONTROL_FIRST_UERR_PTR (0x1fUL<<0) + #define PCICFG_ADV_ERR_CAP_CONTROL_ECRCGCAP (1UL<<5) + #define PCICFG_ADV_ERR_CAP_CONTROL_ECRCGEN (1UL<<6) + #define PCICFG_ADV_ERR_CAP_CONTROL_ECRCCAP (1UL<<7) + #define PCICFG_ADV_ERR_CAP_CONTROL_ECRCEN (1UL<<8) + + u32_t pcicfg_header_log1; + u32_t pcicfg_header_log2; + u32_t pcicfg_header_log3; + u32_t pcicfg_header_log4; + u32_t unused_8[5]; + u16_t pcicfg_pwr_bdgt_cap_id; + u16_t pcicfg_pwr_bdgt_cap_off; + #define PCICFG_PWR_BDGT_CAP_OFF_VER (0xf<<0) + #define PCICFG_PWR_BDGT_CAP_OFF_NEXT (0xfff<<4) + + u32_t pcicfg_pwr_bdgt_data_sel; + #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE (0xffUL<<0) + #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_0 (0UL<<0) + #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_1 (1UL<<0) + #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_2 (2UL<<0) + #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_3 (3UL<<0) + #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_4 (4UL<<0) + #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_5 (5UL<<0) + #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_6 (6UL<<0) + #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_7 (7UL<<0) + + u32_t pcicfg_pwr_bdgt_data; + #define PCICFG_PWR_BDGT_DATA_BASE_PWR (0xffUL<<0) + #define PCICFG_PWR_BDGT_DATA_DSCALE (0x3UL<<8) + #define PCICFG_PWR_BDGT_DATA_PM_STATE (0x3UL<<13) + #define PCICFG_PWR_BDGT_DATA_TYPE (0x7UL<<15) + #define PCICFG_PWR_BDGT_DATA_RAIL (0x7UL<<18) + + u32_t pcicfg_pwr_bdgt_capability; + #define PCICFG_PWR_BDGT_CAPABILITY_PCIE_CFG_PB_CAP_SYS_ALLOC (1UL<<0) + + u16_t pcicfg_vc_cap_id; + u16_t pcicfg_vc_cap_off; + #define PCICFG_VC_CAP_OFF_VER (0xf<<0) + #define PCICFG_VC_CAP_OFF_NEXT (0xfff<<4) + + u32_t pcicfg_port_vc_capability; + u32_t pcicfg_port_vc_capability2; + u16_t pcicfg_port_vc_control; + u16_t pcicfg_port_vc_status; + u32_t pcicfg_port_arb_table; + u32_t pcicfg_vc_rsrc_control; + #define PCICFG_VC_RSRC_CONTROL_TC_VC_MAP (0xffUL<<0) + #define PCICFG_VC_RSRC_CONTROL_VC_ENABLE (1UL<<31) + + u16_t pcicfg_rsvdp; + u16_t pcicfg_vc_rsrc_status; + u32_t unused_9[161]; +} pci_config_t; + + +/* + * pci_reg definition + * offset: 0x400 + */ +typedef struct pci_reg +{ + u32_t pci_grc_window_addr; + #define PCI_GRC_WINDOW_ADDR_VALUE (0x1ffUL<<13) + #define PCI_GRC_WINDOW_ADDR_SEP_WIN (1UL<<31) + + u32_t pci_config_1; + #define PCI_CONFIG_1_RESERVED0 (0xffUL<<0) + #define PCI_CONFIG_1_READ_BOUNDARY (0x7UL<<8) + #define PCI_CONFIG_1_READ_BOUNDARY_OFF (0UL<<8) + #define PCI_CONFIG_1_READ_BOUNDARY_16 (1UL<<8) + #define PCI_CONFIG_1_READ_BOUNDARY_32 (2UL<<8) + #define PCI_CONFIG_1_READ_BOUNDARY_64 (3UL<<8) + #define PCI_CONFIG_1_READ_BOUNDARY_128 (4UL<<8) + #define PCI_CONFIG_1_READ_BOUNDARY_256 (5UL<<8) + #define PCI_CONFIG_1_READ_BOUNDARY_512 (6UL<<8) + #define PCI_CONFIG_1_READ_BOUNDARY_1024 (7UL<<8) + #define PCI_CONFIG_1_WRITE_BOUNDARY (0x7UL<<11) + #define PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0UL<<11) + #define PCI_CONFIG_1_WRITE_BOUNDARY_16 (1UL<<11) + #define PCI_CONFIG_1_WRITE_BOUNDARY_32 (2UL<<11) + #define PCI_CONFIG_1_WRITE_BOUNDARY_64 (3UL<<11) + #define PCI_CONFIG_1_WRITE_BOUNDARY_128 (4UL<<11) + #define PCI_CONFIG_1_WRITE_BOUNDARY_256 (5UL<<11) + #define PCI_CONFIG_1_WRITE_BOUNDARY_512 (6UL<<11) + #define PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7UL<<11) + #define PCI_CONFIG_1_RESERVED1 (0x3ffffUL<<14) + + u32_t pci_config_2; + #define PCI_CONFIG_2_BAR1_SIZE (0xfUL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0UL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_64K (1UL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_128K (2UL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_256K (3UL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_512K (4UL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_1M (5UL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_2M (6UL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_4M (7UL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_8M (8UL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_16M (9UL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_32M (10UL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_64M (11UL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_128M (12UL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_256M (13UL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_512M (14UL<<0) + #define PCI_CONFIG_2_BAR1_SIZE_1G (15UL<<0) + #define PCI_CONFIG_2_BAR1_64ENA (1UL<<4) + #define PCI_CONFIG_2_EXP_ROM_RETRY (1UL<<5) + #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1UL<<6) + #define PCI_CONFIG_2_FIRST_CFG_DONE (1UL<<7) + #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffUL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_1K_TE (1UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_2K_TE (2UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_4K_TE (3UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_8K_TE (4UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_16K_TE (5UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_32K_TE (6UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_64K_TE (7UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_128K_TE (8UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_256K_TE (9UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_512K_TE (10UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_1M_TE (11UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_2M_TE (12UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_4M_TE (13UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_8M_TE (14UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_16M_TE (15UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_2K_XI (1UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_4K_XI (2UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_8K_XI (3UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_16K_XI (4UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_32K_XI (5UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_64K_XI (6UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_128K_XI (7UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_256K_XI (8UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_512K_XI (9UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_1M_XI (10UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_2M_XI (11UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_4M_XI (12UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_8M_XI (13UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_16M_XI (14UL<<8) + #define PCI_CONFIG_2_EXP_ROM_SIZE_32M_XI (15UL<<8) + #define PCI_CONFIG_2_MAX_SPLIT_LIMIT_TE (0x1fUL<<16) + #define PCI_CONFIG_2_MAX_READ_LIMIT_TE (0x3UL<<21) + #define PCI_CONFIG_2_MAX_READ_LIMIT_512_TE (0UL<<21) + #define PCI_CONFIG_2_MAX_READ_LIMIT_1K_TE (1UL<<21) + #define PCI_CONFIG_2_MAX_READ_LIMIT_2K_TE (2UL<<21) + #define PCI_CONFIG_2_MAX_READ_LIMIT_4K_TE (3UL<<21) + #define PCI_CONFIG_2_FORCE_32_BIT_MSTR_TE (1UL<<23) + #define PCI_CONFIG_2_FORCE_32_BIT_TGT_TE (1UL<<24) + #define PCI_CONFIG_2_KEEP_REQ_ASSERT_TE (1UL<<25) + #define PCI_CONFIG_2_RESERVED0_TE (0x3fUL<<26) + #define PCI_CONFIG_2_BAR_PREFETCH_XI (1UL<<16) + #define PCI_CONFIG_2_RESERVED0_XI (0x7fffUL<<17) + + u32_t pci_config_3; + #define PCI_CONFIG_3_STICKY_BYTE (0xffUL<<0) + #define PCI_CONFIG_3_REG_STICKY_BYTE (0xffUL<<8) + #define PCI_CONFIG_3_FORCE_PME (1UL<<24) + #define PCI_CONFIG_3_PME_STATUS (1UL<<25) + #define PCI_CONFIG_3_PME_ENABLE (1UL<<26) + #define PCI_CONFIG_3_PM_STATE (0x3UL<<27) + #define PCI_CONFIG_3_VAUX_PRESET (1UL<<30) + #define PCI_CONFIG_3_PCI_POWER (1UL<<31) + + u32_t pci_pm_data_a; + #define PCI_PM_DATA_A_PM_DATA_0_PRG (0xffUL<<0) + #define PCI_PM_DATA_A_PM_DATA_1_PRG (0xffUL<<8) + #define PCI_PM_DATA_A_PM_DATA_2_PRG (0xffUL<<16) + #define PCI_PM_DATA_A_PM_DATA_3_PRG (0xffUL<<24) + + u32_t pci_pm_data_b; + #define PCI_PM_DATA_B_PM_DATA_4_PRG (0xffUL<<0) + #define PCI_PM_DATA_B_PM_DATA_5_PRG (0xffUL<<8) + #define PCI_PM_DATA_B_PM_DATA_6_PRG (0xffUL<<16) + #define PCI_PM_DATA_B_PM_DATA_7_PRG (0xffUL<<24) + + u32_t pci_swap_diag0; + u32_t pci_swap_diag1; + u32_t pci_exp_rom_addr; + #define PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffUL<<2) + #define PCI_EXP_ROM_ADDR_REQ (1UL<<31) + + u32_t pci_exp_rom_data; + u32_t pci_vpd_intf; + #define PCI_VPD_INTF_INTF_REQ (1UL<<0) + + u16_t unused_0; + u16_t pci_vpd_addr_flag; + #define PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) + #define PCI_VPD_ADDR_FLAG_WR (1<<15) + + u32_t pci_vpd_data; + u32_t pci_id_val1; + #define PCI_ID_VAL1_DEVICE_ID (0xffffUL<<0) + #define PCI_ID_VAL1_VENDOR_ID (0xffffUL<<16) + + u32_t pci_id_val2; + #define PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffUL<<0) + #define PCI_ID_VAL2_SUBSYSTEM_ID (0xffffUL<<16) + + u32_t pci_id_val3; + #define PCI_ID_VAL3_CLASS_CODE (0xffffffUL<<0) + #define PCI_ID_VAL3_REVISION_ID (0xffUL<<24) + + u32_t pci_id_val4; + #define PCI_ID_VAL4_CAP_ENA (0xfUL<<0) + #define PCI_ID_VAL4_CAP_ENA_0 (0UL<<0) + #define PCI_ID_VAL4_CAP_ENA_1 (1UL<<0) + #define PCI_ID_VAL4_CAP_ENA_2 (2UL<<0) + #define PCI_ID_VAL4_CAP_ENA_3 (3UL<<0) + #define PCI_ID_VAL4_CAP_ENA_4 (4UL<<0) + #define PCI_ID_VAL4_CAP_ENA_5 (5UL<<0) + #define PCI_ID_VAL4_CAP_ENA_6 (6UL<<0) + #define PCI_ID_VAL4_CAP_ENA_7 (7UL<<0) + #define PCI_ID_VAL4_CAP_ENA_8 (8UL<<0) + #define PCI_ID_VAL4_CAP_ENA_9 (9UL<<0) + #define PCI_ID_VAL4_CAP_ENA_10 (10UL<<0) + #define PCI_ID_VAL4_CAP_ENA_11 (11UL<<0) + #define PCI_ID_VAL4_CAP_ENA_12 (12UL<<0) + #define PCI_ID_VAL4_CAP_ENA_13 (13UL<<0) + #define PCI_ID_VAL4_CAP_ENA_14 (14UL<<0) + #define PCI_ID_VAL4_CAP_ENA_15 (15UL<<0) + #define PCI_ID_VAL4_RESERVED0 (0x3UL<<4) + #define PCI_ID_VAL4_PM_SCALE_PRG (0x3UL<<6) + #define PCI_ID_VAL4_PM_SCALE_PRG_0 (0UL<<6) + #define PCI_ID_VAL4_PM_SCALE_PRG_1 (1UL<<6) + #define PCI_ID_VAL4_PM_SCALE_PRG_2 (2UL<<6) + #define PCI_ID_VAL4_PM_SCALE_PRG_3 (3UL<<6) + #define PCI_ID_VAL4_MSI_PV_MASK_CAP (1UL<<8) + #define PCI_ID_VAL4_MSI_LIMIT (0x7UL<<9) + #define PCI_ID_VAL4_MULTI_MSG_CAP (0x7UL<<12) + #define PCI_ID_VAL4_MSI_ENABLE (1UL<<15) + #define PCI_ID_VAL4_MAX_64_ADVERTIZE_TE (1UL<<16) + #define PCI_ID_VAL4_MAX_133_ADVERTIZE_TE (1UL<<17) + #define PCI_ID_VAL4_RESERVED2_TE (0x7UL<<18) + #define PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21_TE (0x3UL<<21) + #define PCI_ID_VAL4_MAX_SPLIT_SIZE_B21_TE (0x3UL<<23) + #define PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0_TE (1UL<<25) + #define PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10_TE (0x3UL<<26) + #define PCI_ID_VAL4_MAX_SPLIT_SIZE_B0_TE (1UL<<28) + #define PCI_ID_VAL4_RESERVED3_TE (0x7UL<<29) + #define PCI_ID_VAL4_RESERVED3_XI (0xffffUL<<16) + + u32_t pci_id_val5; + #define PCI_ID_VAL5_D1_SUPPORT (1UL<<0) + #define PCI_ID_VAL5_D2_SUPPORT (1UL<<1) + #define PCI_ID_VAL5_PME_IN_D0 (1UL<<2) + #define PCI_ID_VAL5_PME_IN_D1 (1UL<<3) + #define PCI_ID_VAL5_PME_IN_D2 (1UL<<4) + #define PCI_ID_VAL5_PME_IN_D3_HOT (1UL<<5) + #define PCI_ID_VAL5_RESERVED0_TE (0x3ffffffUL<<6) + #define PCI_ID_VAL5_PM_VERSION_XI (0x7UL<<6) + #define PCI_ID_VAL5_NO_SOFT_RESET_XI (1UL<<9) + #define PCI_ID_VAL5_RESERVED0_XI (0x3fffffUL<<10) + + u32_t pci_pcix_extended_status; + #define PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1UL<<8) + #define PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1UL<<9) + #define PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfUL<<16) + #define PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffUL<<24) + + u32_t pci_id_val6; + #define PCI_ID_VAL6_MAX_LAT (0xffUL<<0) + #define PCI_ID_VAL6_MIN_GNT (0xffUL<<8) + #define PCI_ID_VAL6_BIST (0xffUL<<16) + #define PCI_ID_VAL6_RESERVED0 (0xffUL<<24) + + u32_t pci_msi_data; + #define PCI_MSI_DATA_MSI_DATA (0xffffUL<<0) + + u32_t pci_msi_addr_h; + u32_t pci_msi_addr_l; + #define PCI_MSI_ADDR_L_VAL (0x3fffffffUL<<2) + + u32_t pci_cfg_access_cmd; + #define PCI_CFG_ACCESS_CMD_ADR (0x3fUL<<2) + #define PCI_CFG_ACCESS_CMD_RD_REQ (1UL<<27) + #define PCI_CFG_ACCESS_CMD_WR_REQ (0xfUL<<28) + + u32_t pci_cfg_access_data; + u32_t pci_msi_mask; + #define PCI_MSI_MASK_MSI_MASK (0xffffffffUL<<0) + + u32_t pci_msi_pend; + #define PCI_MSI_PEND_MSI_PEND (0xffffffffUL<<0) + + u32_t pci_pm_data_c; + #define PCI_PM_DATA_C_PM_DATA_8_PRG (0xffUL<<0) + #define PCI_PM_DATA_C_RESERVED0 (0xffffffUL<<8) + + u32_t unused_1[20]; + u32_t pci_msix_control; + #define PCI_MSIX_CONTROL_MSIX_TBL_SIZ (0x7ffUL<<0) + #define PCI_MSIX_CONTROL_RESERVED0 (0x1fffffUL<<11) + + u32_t pci_msix_tbl_off_bir; + #define PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR (0x7UL<<0) + #define PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF (0x1fffffffUL<<3) + + u32_t pci_msix_pba_off_bit; + #define PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR (0x7UL<<0) + #define PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF (0x1fffffffUL<<3) + + u32_t unused_2; + u32_t pci_pcie_capability; + #define PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM (0x1fUL<<0) + #define PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1 (1UL<<5) + + u32_t pci_device_capability; + #define PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED (0x7UL<<0) + #define PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT (1UL<<5) + #define PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY (0x7UL<<6) + #define PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY (0x7UL<<9) + #define PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT (1UL<<15) + + u32_t unused_3; + u32_t pci_link_capability; + #define PCI_LINK_CAPABILITY_MAX_LINK_SPEED (0xfUL<<0) + #define PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001 (1UL<<0) + #define PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010 (2UL<<0) + #define PCI_LINK_CAPABILITY_MAX_LINK_WIDTH (0x1fUL<<4) + #define PCI_LINK_CAPABILITY_CLK_POWER_MGMT (1UL<<9) + #define PCI_LINK_CAPABILITY_ASPM_SUPPORT (0x3UL<<10) + #define PCI_LINK_CAPABILITY_L0S_EXIT_LAT (0x7UL<<12) + #define PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101 (5UL<<12) + #define PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110 (6UL<<12) + #define PCI_LINK_CAPABILITY_L1_EXIT_LAT (0x7UL<<15) + #define PCI_LINK_CAPABILITY_L1_EXIT_LAT_001 (1UL<<15) + #define PCI_LINK_CAPABILITY_L1_EXIT_LAT_010 (2UL<<15) + #define PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT (0x7UL<<18) + #define PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101 (5UL<<18) + #define PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110 (6UL<<18) + #define PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT (0x7UL<<21) + #define PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001 (1UL<<21) + #define PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010 (2UL<<21) + #define PCI_LINK_CAPABILITY_PORT_NUM (0xffUL<<24) + + u32_t pci_bar2_config; + #define PCI_BAR2_CONFIG_BAR2_SIZE (0xfUL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_DISABLED (0UL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_64K (1UL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_128K (2UL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_256K (3UL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_512K (4UL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_1M (5UL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_2M (6UL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_4M (7UL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_8M (8UL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_16M (9UL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_32M (10UL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_64M (11UL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_128M (12UL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_256M (13UL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_512M (14UL<<0) + #define PCI_BAR2_CONFIG_BAR2_SIZE_1G (15UL<<0) + #define PCI_BAR2_CONFIG_BAR2_64ENA (1UL<<4) + #define PCI_BAR2_CONFIG_BAR2_PREFETCH (1UL<<5) + #define PCI_BAR2_CONFIG_RESERVED (0x3ffffffUL<<6) + + u32_t pci_pcie_device_capability_2; + #define PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP (0xfUL<<0) + #define PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP (1UL<<4) + #define PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED (0x7ffffffUL<<5) + + u32_t pci_pcie_link_capability_2; + #define PCI_PCIE_LINK_CAPABILITY_2_RESERVED (0xffffffffUL<<0) + + u32_t unused_4[5]; + u32_t pci_dev_ser_num_cap_id; + #define PCI_DEV_SER_NUM_CAP_ID_CAP_ID (0xffffUL<<0) + #define PCI_DEV_SER_NUM_CAP_ID_CAP_VER (0xfUL<<16) + #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA (0xfUL<<20) + #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_8 (8UL<<20) + #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_9 (9UL<<20) + #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_10 (10UL<<20) + #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_11 (11UL<<20) + #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_12 (12UL<<20) + #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_13 (13UL<<20) + #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_14 (14UL<<20) + #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_15 (15UL<<20) + + u32_t pci_lower_ser_num; + #define PCI_LOWER_SER_NUM_LOWER_SER_NUM (0xffffffffUL<<0) + + u32_t pci_upper_ser_num; + #define PCI_UPPER_SER_NUM_UPPER_SER_NUM (0xffffffffUL<<0) + + u32_t pci_adv_err_cap; + #define PCI_ADV_ERR_CAP_ECRC_CHK_CAP (1UL<<0) + #define PCI_ADV_ERR_CAP_ECRC_GEN_CAP (1UL<<1) + + u32_t pci_pwr_bdgt_data_0; + #define PCI_PWR_BDGT_DATA_0_PWR_BDGT_DATA_0 (0x1fffffUL<<0) + #define PCI_PWR_BDGT_DATA_0_RESERVED (0x7ffUL<<21) + + u32_t pci_pwr_bdgt_data_1; + #define PCI_PWR_BDGT_DATA_1_PWR_BDGT_DATA_1 (0x1fffffUL<<0) + #define PCI_PWR_BDGT_DATA_1_RW (0x7ffUL<<21) + + u32_t pci_pwr_bdgt_data_2; + #define PCI_PWR_BDGT_DATA_2_PWR_BDGT_DATA_2 (0x1fffffUL<<0) + #define PCI_PWR_BDGT_DATA_2_RW (0x7ffUL<<21) + + u32_t pci_pwd_bdgt_data_3; + #define PCI_PWD_BDGT_DATA_3_PWR_BDGT_DATA_3 (0x1fffffUL<<0) + #define PCI_PWD_BDGT_DATA_3_RW (0x7ffUL<<21) + + u32_t pci_pwr_bdgt_data_4; + #define PCI_PWR_BDGT_DATA_4_PWR_BDGT_DATA_4 (0x1fffffUL<<0) + #define PCI_PWR_BDGT_DATA_4_RW (0x7ffUL<<21) + + u32_t pci_pwr_bdgt_data_5; + #define PCI_PWR_BDGT_DATA_5_PWR_BDGT_DATA_5 (0x1fffffUL<<0) + #define PCI_PWR_BDGT_DATA_5_RW (0x7ffUL<<21) + + u32_t pci_pwr_bdgt_data_6; + #define PCI_PWR_BDGT_DATA_6_PWR_BDGT_DATA_6 (0x1fffffUL<<0) + #define PCI_PWR_BDGT_DATA_6_RW (0x7ffUL<<21) + + u32_t pci_pwr_bdgt_data_7; + #define PCI_PWR_BDGT_DATA_7_PWR_BDGT_DATA_7 (0x1fffffUL<<0) + #define PCI_PWR_BDGT_DATA_7_RW (0x7ffUL<<21) + + u32_t unused_5[8]; + u32_t pci_pwr_bdgt_capability_ctl; + #define PCI_PWR_BDGT_CAPABILITY_CTL_PWR_SYSTEM_ALLOC (1UL<<0) + #define PCI_PWR_BDGT_CAPABILITY_CTL_RESERVED (0x7fffffffUL<<1) + + u32_t unused_6[47]; + u32_t pci_grc_window1_addr; + #define PCI_GRC_WINDOW1_ADDR_VALUE (0x1ffUL<<13) + + u32_t pci_grc_window2_addr; + #define PCI_GRC_WINDOW2_ADDR_VALUE (0x1ffUL<<13) + + u32_t pci_grc_window3_addr; + #define PCI_GRC_WINDOW3_ADDR_VALUE (0x1ffUL<<13) + + u32_t unused_7[9]; + u32_t pci_exp_rom_adr; + #define PCI_EXP_ROM_ADR_ADDRESS (0x3fffffUL<<2) + #define PCI_EXP_ROM_ADR_ADDR_SIZE (0x3UL<<24) + #define PCI_EXP_ROM_ADR_REQ (1UL<<31) + + u32_t pci_exp_rom_data0; + u32_t pci_exp_rom_data1; + u32_t pci_exp_rom_data2; + u32_t pci_exp_rom_ctrl; + #define PCI_EXP_ROM_CTRL_ENA (1UL<<0) + #define PCI_EXP_ROM_CTRL_BFRD (1UL<<1) + #define PCI_EXP_ROM_CTRL_ARB_NUM (0x3UL<<4) + #define PCI_EXP_ROM_CTRL_STATE (0xfUL<<16) + #define PCI_EXP_ROM_CTRL_CACHE_VALID (1UL<<28) + #define PCI_EXP_ROM_CTRL_ARB_TIMEOUT (1UL<<29) + #define PCI_EXP_ROM_CTRL_READ_TIMEOUT (1UL<<30) + #define PCI_EXP_ROM_CTRL_ACTIVE (1UL<<31) + + u32_t pci_exp_rom_baddr; + #define PCI_EXP_ROM_BADDR_VALUE (0x3fffffUL<<2) + + u32_t pci_exp_rom_cfg; + #define PCI_EXP_ROM_CFG_ARB_TIMEOUT_SHFT (0xfUL<<0) + #define PCI_EXP_ROM_CFG_READ_TIMEOUT_SHFT (0xfUL<<4) + + u32_t unused_8[41]; + u32_t pci_debug_vect_peek; + #define PCI_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define PCI_DEBUG_VECT_PEEK_1_EN (1UL<<11) + #define PCI_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define PCI_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define PCI_DEBUG_VECT_PEEK_2_EN (1UL<<27) + #define PCI_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t unused_9[63]; +} pci_reg_t; + + +/* + * pcie_reg definition + * offset: 0x300000 + */ +typedef struct pcie_reg +{ + u16_t pci1_cfg_device_id; + u16_t pci1_cfg_vendor_id; + u16_t pci1_cfg_status; + #define PCI1_CFG_STATUS_RESERVED1 (0x7<<0) + #define PCI1_CFG_STATUS_INT_STATUS (1<<3) + #define PCI1_CFG_STATUS_CAP_LIST (1<<4) + #define PCI1_CFG_STATUS_66MHZ_CAP (1<<5) + #define PCI1_CFG_STATUS_RESERVED2 (1<<6) + #define PCI1_CFG_STATUS_FAST_B2B_CAP (1<<7) + #define PCI1_CFG_STATUS_MSTR_PERR (1<<8) + #define PCI1_CFG_STATUS_DEVSEL_TIMING (0x3<<9) + #define PCI1_CFG_STATUS_SIG_TGT_ABT (1<<11) + #define PCI1_CFG_STATUS_RCV_TGT_ABT (1<<12) + #define PCI1_CFG_STATUS_RCV_MSTR_ABT (1<<13) + #define PCI1_CFG_STATUS_SIG_SERR (1<<14) + #define PCI1_CFG_STATUS_PAR_ERR (1<<15) + + u16_t pci1_cfg_command; + #define PCI1_CFG_COMMAND_IO_SPACE (1<<0) + #define PCI1_CFG_COMMAND_MEM_SPACE (1<<1) + #define PCI1_CFG_COMMAND_BUS_MASTER (1<<2) + #define PCI1_CFG_COMMAND_SPECIAL_CYCLES (1<<3) + #define PCI1_CFG_COMMAND_MWI_CYCLES (1<<4) + #define PCI1_CFG_COMMAND_VGA_SNOOP (1<<5) + #define PCI1_CFG_COMMAND_PERR_ENA (1<<6) + #define PCI1_CFG_COMMAND_STEPPING (1<<7) + #define PCI1_CFG_COMMAND_SERR_ENA (1<<8) + #define PCI1_CFG_COMMAND_FAST_B2B (1<<9) + #define PCI1_CFG_COMMAND_INT_DISABLE (1<<10) + #define PCI1_CFG_COMMAND_RESERVED (0x1f<<11) + + u32_t pci1_cfg_class_code; + #define PCI1_CFG_CLASS_CODE_REV_ID (0xffUL<<0) + #define PCI1_CFG_CLASS_CODE_VALUE (0xffffffUL<<8) + + u8_t pci1_cfg_bist; + u8_t pci1_cfg_header_type; + u8_t pci1_cfg_latency_timer; + u8_t pci1_cfg_cache_line_size; + u32_t pci1_cfg_bar_1; + #define PCI1_CFG_BAR_1_MEM_SPACE (1UL<<0) + #define PCI1_CFG_BAR_1_SPACE_TYPE (0x3UL<<1) + #define PCI1_CFG_BAR_1_PREFETCH (1UL<<3) + #define PCI1_CFG_BAR_1_ADDRESS (0xfffffffUL<<4) + + u32_t pci1_cfg_bar_2; + #define PCI1_CFG_BAR_2_ADDR (0xffffffffUL<<0) + + u32_t pci1_cfg_bar_3; + #define PCI1_CFG_BAR_3_MEM_SPACE (1UL<<0) + #define PCI1_CFG_BAR_3_SPACE_TYPE (0x3UL<<1) + #define PCI1_CFG_BAR_3_PREFETCH (1UL<<3) + #define PCI1_CFG_BAR_3_ADDRESS (0xfffffffUL<<4) + + u32_t pci1_cfg_bar_4; + #define PCI1_CFG_BAR_4_ADDR (0xffffffffUL<<0) + + u32_t pci1_cfg_bar_5; + u32_t pci1_cfg_bar_6; + u32_t pci1_cfg_cardbus_cis; + u16_t pci1_cfg_subsystem_id; + u16_t pci1_cfg_subsystem_vendor_id; + u32_t pci1_cfg_exp_rom_bar; + #define PCI1_CFG_EXP_ROM_BAR_BAR_ENA (1UL<<0) + #define PCI1_CFG_EXP_ROM_BAR_LOW (0x3ffUL<<1) + #define PCI1_CFG_EXP_ROM_BAR_SIZE (0x1fffUL<<11) + #define PCI1_CFG_EXP_ROM_BAR_ADDRESS (0xffUL<<24) + + u16_t unused_0; + u8_t unused_1; + u8_t pci1_cfg_cap_pointer; + u32_t unused_2; + u8_t pci1_cfg_maximum_latency; + u8_t pci1_cfg_min_grant; + u8_t pci1_cfg_int_pin; + u8_t pci1_cfg_int_line; + u32_t unused_3[2]; + u16_t pci1_cfg_pm_capability; + #define PCI1_CFG_PM_CAPABILITY_VERSION (0x3<<0) + #define PCI1_CFG_PM_CAPABILITY_CLOCK (1<<3) + #define PCI1_CFG_PM_CAPABILITY_RESERVED (1<<4) + #define PCI1_CFG_PM_CAPABILITY_DSI (1<<5) + #define PCI1_CFG_PM_CAPABILITY_AUX_CURRENT (0x7<<6) + #define PCI1_CFG_PM_CAPABILITY_D1_SUPPORT (1<<9) + #define PCI1_CFG_PM_CAPABILITY_D2_SUPPORT (1<<10) + #define PCI1_CFG_PM_CAPABILITY_PME_IN_D0 (1<<11) + #define PCI1_CFG_PM_CAPABILITY_PME_IN_D1 (1<<12) + #define PCI1_CFG_PM_CAPABILITY_PME_IN_D2 (1<<13) + #define PCI1_CFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<14) + #define PCI1_CFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<15) + + u8_t pci1_cfg_pm_next_cap_ptr; + u8_t pci1_cfg_pm_cap_id; + u8_t pci1_cfg_pm_data; + u8_t pci1_cfg_pm_csr_bse; + u16_t pci1_cfg_pm_csr; + #define PCI1_CFG_PM_CSR_STATE (0x3<<0) + #define PCI1_CFG_PM_CSR_STATE_D0 (0<<0) + #define PCI1_CFG_PM_CSR_STATE_D1 (1<<0) + #define PCI1_CFG_PM_CSR_STATE_D2 (2<<0) + #define PCI1_CFG_PM_CSR_STATE_D3_HOT (3<<0) + #define PCI1_CFG_PM_CSR_RESERVED0 (1<<2) + #define PCI1_CFG_PM_CSR_NO_SOFT_RESET (1<<3) + #define PCI1_CFG_PM_CSR_RESERVED1 (0xf<<4) + #define PCI1_CFG_PM_CSR_PME_ENABLE (1<<8) + #define PCI1_CFG_PM_CSR_DATA_SEL (0xf<<9) + #define PCI1_CFG_PM_CSR_DATA_SEL_0 (0<<9) + #define PCI1_CFG_PM_CSR_DATA_SEL_1 (1<<9) + #define PCI1_CFG_PM_CSR_DATA_SEL_2 (2<<9) + #define PCI1_CFG_PM_CSR_DATA_SEL_3 (3<<9) + #define PCI1_CFG_PM_CSR_DATA_SEL_4 (4<<9) + #define PCI1_CFG_PM_CSR_DATA_SEL_5 (5<<9) + #define PCI1_CFG_PM_CSR_DATA_SEL_6 (6<<9) + #define PCI1_CFG_PM_CSR_DATA_SEL_7 (7<<9) + #define PCI1_CFG_PM_CSR_DATA_SCALE (0x3<<13) + #define PCI1_CFG_PM_CSR_DATA_SCALE_0 (0<<13) + #define PCI1_CFG_PM_CSR_DATA_SCALE_1 (1<<13) + #define PCI1_CFG_PM_CSR_DATA_SCALE_2 (2<<13) + #define PCI1_CFG_PM_CSR_DATA_SCALE_3 (3<<13) + #define PCI1_CFG_PM_CSR_PME_STATUS (1<<15) + + u16_t pci1_cfg_vpd_flag_addr; + #define PCI1_CFG_VPD_FLAG_ADDR_ADDRESS (0x1fff<<2) + #define PCI1_CFG_VPD_FLAG_ADDR_FLAG (1<<15) + + u8_t pci1_cfg_vpd_next_cap_ptr; + u8_t pci1_cfg_vpd_cap_id; + u32_t pci1_cfg_vpd_data; + u16_t pci1_cfg_msi_control; + #define PCI1_CFG_MSI_CONTROL_ENABLE (1<<0) + #define PCI1_CFG_MSI_CONTROL_MCAP (0x7<<1) + #define PCI1_CFG_MSI_CONTROL_MCAP_1 (0<<1) + #define PCI1_CFG_MSI_CONTROL_MCAP_2 (1<<1) + #define PCI1_CFG_MSI_CONTROL_MCAP_4 (2<<1) + #define PCI1_CFG_MSI_CONTROL_MCAP_8 (3<<1) + #define PCI1_CFG_MSI_CONTROL_MCAP_16 (4<<1) + #define PCI1_CFG_MSI_CONTROL_MCAP_32 (5<<1) + #define PCI1_CFG_MSI_CONTROL_MENA (0x7<<4) + #define PCI1_CFG_MSI_CONTROL_MENA_1 (0<<4) + #define PCI1_CFG_MSI_CONTROL_MENA_2 (1<<4) + #define PCI1_CFG_MSI_CONTROL_MENA_4 (2<<4) + #define PCI1_CFG_MSI_CONTROL_MENA_8 (3<<4) + #define PCI1_CFG_MSI_CONTROL_MENA_16 (4<<4) + #define PCI1_CFG_MSI_CONTROL_MENA_32 (5<<4) + #define PCI1_CFG_MSI_CONTROL_64_BIT_ADDR_CAP (1<<7) + #define PCI1_CFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (1<<8) + + u8_t pci1_cfg_msi_next_cap_ptr; + u8_t pci1_cfg_msi_cap_id; + u32_t pci1_cfg_msi_addr_l; + #define PCI1_CFG_MSI_ADDR_L_VAL (0x3fffffffUL<<2) + + u32_t pci1_cfg_msi_addr_h; + u16_t unused_4; + u16_t pci1_cfg_msi_data; + u32_t pci1_cfg_misc_config; + #define PCI1_CFG_MISC_CONFIG_TARGET_BYTE_SWAP (1UL<<2) + #define PCI1_CFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1UL<<3) + #define PCI1_CFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1UL<<6) + #define PCI1_CFG_MISC_CONFIG_REG_WINDOW_ENA (1UL<<7) + #define PCI1_CFG_MISC_CONFIG_GRC_WIN1_SWAP_EN (1UL<<10) + #define PCI1_CFG_MISC_CONFIG_GRC_WIN2_SWAP_EN (1UL<<11) + #define PCI1_CFG_MISC_CONFIG_GRC_WIN3_SWAP_EN (1UL<<12) + #define PCI1_CFG_MISC_CONFIG_ASIC_METAL_REV (0xffUL<<16) + #define PCI1_CFG_MISC_CONFIG_ASIC_BASE_REV (0xfUL<<24) + #define PCI1_CFG_MISC_CONFIG_ASIC_ID (0xfUL<<28) + + u32_t pci1_cfg_misc_status; + #define PCI1_CFG_MISC_STATUS_INTA_VALUE (1UL<<0) + #define PCI1_CFG_MISC_STATUS_BAD_MEM_WRITE_BE (1UL<<8) + + u32_t unused_5[2]; + u32_t pci1_cfg_reg_window_address; + u32_t unused_6; + u32_t pci1_cfg_reg_window; + u32_t pci1_cfg_int_ack_cmd; + #define PCI1_CFG_INT_ACK_CMD_INDEX (0xffffUL<<0) + #define PCI1_CFG_INT_ACK_CMD_INDEX_VALID (1UL<<16) + #define PCI1_CFG_INT_ACK_CMD_USE_INT_HC_PARAM (1UL<<17) + #define PCI1_CFG_INT_ACK_CMD_MASK_INT (1UL<<18) + #define PCI1_CFG_INT_ACK_CMD_INTERRUPT_NUM (0xfUL<<24) + + u32_t pci1_cfg_status_bit_set_cmd; + u32_t pci1_cfg_status_bit_clear_cmd; + u32_t pci1_cfg_mailbox_queue_addr; + u32_t pci1_cfg_mailbox_queue_data; + u32_t unused_7[2]; + u16_t pci1_cfg_msix_control; + #define PCI1_CFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<0) + #define PCI1_CFG_MSIX_CONTROL_RESERVED (0x7<<11) + #define PCI1_CFG_MSIX_CONTROL_FUNC_MASK (1<<14) + #define PCI1_CFG_MSIX_CONTROL_MSIX_ENABLE (1<<15) + + u8_t pci1_cfg_msix_next_cap_ptr; + u8_t pci1_cfg_msix_cap_id; + u32_t pci1_cfg_msix_tbl_off_bir; + #define PCI1_CFG_MSIX_TBL_OFF_BIR_TABLE_BIR (0x7UL<<0) + #define PCI1_CFG_MSIX_TBL_OFF_BIR_TABLE_OFFSET (0x1fffffffUL<<3) + + u32_t pci1_cfg_msix_pba_off_bir; + #define PCI1_CFG_MSIX_PBA_OFF_BIR_PBA_BIR (0x7UL<<0) + #define PCI1_CFG_MSIX_PBA_OFF_BIR_PBA_OFFSET (0x1fffffffUL<<3) + + u16_t pci1_cfg_pcie_capability; + #define PCI1_CFG_PCIE_CAPABILITY_VER (0xf<<0) + #define PCI1_CFG_PCIE_CAPABILITY_TYPE (0xf<<4) + + u8_t pci1_cfg_pcie_next_cap_ptr; + u8_t pci1_cfg_pcie_cap_id; + u32_t pci1_cfg_device_capability; + #define PCI1_CFG_DEVICE_CAPABILITY_MAX_PAYLOAD (0x7UL<<0) + #define PCI1_CFG_DEVICE_CAPABILITY_PHANTOM_SUPPT (0x3UL<<3) + #define PCI1_CFG_DEVICE_CAPABILITY_EXT_TAG_SUPPT (1UL<<5) + #define PCI1_CFG_DEVICE_CAPABILITY_EP_L0S_ACCP_LAT (0x7UL<<6) + #define PCI1_CFG_DEVICE_CAPABILITY_EP_L1_ACCP_LAT (0x7UL<<9) + + u16_t pci1_cfg_device_status; + #define PCI1_CFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) + #define PCI1_CFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) + #define PCI1_CFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) + #define PCI1_CFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) + #define PCI1_CFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) + #define PCI1_CFG_DEVICE_STATUS_NO_PEND (1<<5) + + u16_t pci1_cfg_device_control; + #define PCI1_CFG_DEVICE_CONTROL_CORR_ERR_REP_ENA (1<<0) + #define PCI1_CFG_DEVICE_CONTROL_NON_FATAL_REP_ENA (1<<1) + #define PCI1_CFG_DEVICE_CONTROL_FATAL_REP_ENA (1<<2) + #define PCI1_CFG_DEVICE_CONTROL_UNSUP_REQ_ENA (1<<3) + #define PCI1_CFG_DEVICE_CONTROL_RELAX_ENA (1<<4) + #define PCI1_CFG_DEVICE_CONTROL_MAX_PAYLOAD (0x7<<5) + #define PCI1_CFG_DEVICE_CONTROL_EXT_TAG_ENA (1<<8) + #define PCI1_CFG_DEVICE_CONTROL_AUX_PWR_PM_ENA (1<<10) + #define PCI1_CFG_DEVICE_CONTROL_ENA_NO_SNOOP (1<<11) + #define PCI1_CFG_DEVICE_CONTROL_MAX_RD_REQ (0x7<<12) + + u32_t pci1_cfg_link_capability; + #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_SPEED (0xfUL<<0) + #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_SPEED_2_5 (1UL<<0) + #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_SPEED_5 (2UL<<0) + #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_WIDTH (0x3fUL<<4) + #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_WIDTH_1 (1UL<<4) + #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_WIDTH_2 (2UL<<4) + #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_WIDTH_4 (4UL<<4) + #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_WIDTH_8 (8UL<<4) + #define PCI1_CFG_LINK_CAPABILITY_ASPM_SUPT (0x3UL<<10) + #define PCI1_CFG_LINK_CAPABILITY_ASPM_SUPT_RES_0 (0UL<<10) + #define PCI1_CFG_LINK_CAPABILITY_ASPM_SUPT_L0S (0UL<<10) + #define PCI1_CFG_LINK_CAPABILITY_ASPM_SUPT_RES_2 (0UL<<10) + #define PCI1_CFG_LINK_CAPABILITY_ASPM_SUPT_L0S_L1 (0UL<<10) + #define PCI1_CFG_LINK_CAPABILITY_L0S_EXIT_LAT (0x7UL<<12) + #define PCI1_CFG_LINK_CAPABILITY_L0S_EXIT_LAT_1_2 (5UL<<12) + #define PCI1_CFG_LINK_CAPABILITY_L0S_EXIT_LAT_2_4 (6UL<<12) + #define PCI1_CFG_LINK_CAPABILITY_L1_EXIT_LAT (0x7UL<<15) + #define PCI1_CFG_LINK_CAPABILITY_L1_EXIT_LAT_1_2 (1UL<<15) + #define PCI1_CFG_LINK_CAPABILITY_L1_EXIT_LAT_2_4 (2UL<<15) + #define PCI1_CFG_LINK_CAPABILITY_CLK_PWR_MGMT (1UL<<18) + #define PCI1_CFG_LINK_CAPABILITY_PORT_NUMBER (0xffUL<<24) + + u16_t pci1_cfg_link_status; + #define PCI1_CFG_LINK_STATUS_SPEED (0xf<<0) + #define PCI1_CFG_LINK_STATUS_NEG_LINK_WIDTH (0x3f<<4) + #define PCI1_CFG_LINK_STATUS_TRAINING_ERR (1<<10) + #define PCI1_CFG_LINK_STATUS_TRAINING (1<<11) + #define PCI1_CFG_LINK_STATUS_SLOT_CLK (1<<12) + + u16_t pci1_cfg_link_control; + #define PCI1_CFG_LINK_CONTROL_ASPM_CTRL (0x3<<0) + #define PCI1_CFG_LINK_CONTROL_RD_COMP_BOUND (1<<3) + #define PCI1_CFG_LINK_CONTROL_RD_COMP_BOUND_64 (0<<3) + #define PCI1_CFG_LINK_CONTROL_RD_COMP_BOUND_128 (1<<3) + #define PCI1_CFG_LINK_CONTROL_LINK_CR_COMMON_CLK (1<<6) + #define PCI1_CFG_LINK_CONTROL_LINK_CR_EXT_SYNC (1<<7) + + u32_t pci1_cfg_slot_capability; + u16_t pci1_cfg_slot_status; + u16_t pci1_cfg_slot_control; + u16_t pci1_cfg_root_cap; + u16_t pci1_cfg_root_control; + u32_t pci1_cfg_root_status; + u32_t pci1_cfg_device_capability_2; + #define PCI1_CFG_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP (0xfUL<<0) + #define PCI1_CFG_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP_ABCD (15UL<<0) + #define PCI1_CFG_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP (1UL<<4) + + u16_t pci1_cfg_device_status_2; + u16_t pci1_cfg_device_control_2; + #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE (0xf<<0) + #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_50MS (0<<0) + #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_100US (1<<0) + #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_10MS (2<<0) + #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_55MS (3<<0) + #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_210MS (4<<0) + #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_900MS (5<<0) + #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_3_5S (6<<0) + #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_13S (7<<0) + #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_64S (8<<0) + #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_DISABLE (1<<4) + + u32_t pci1_cfg_link_capability_2; + u16_t pci1_cfg_link_status_2; + u16_t pci1_cfg_link_control_2; + #define PCI1_CFG_LINK_CONTROL_2_TARGET_LINK_SPEED (0xf<<0) + #define PCI1_CFG_LINK_CONTROL_2_TARGET_LINK_SPEED_2_5 (0<<0) + #define PCI1_CFG_LINK_CONTROL_2_TARGET_LINK_SPEED_5_0 (1<<0) + #define PCI1_CFG_LINK_CONTROL_2_ENTER_COMPLIANCE (1<<4) + #define PCI1_CFG_LINK_CONTROL_2_HW_AUTO_SPEED_DISABLE (1<<5) + #define PCI1_CFG_LINK_CONTROL_2_SEL_DEEMPHASIS (1<<6) + #define PCI1_CFG_LINK_CONTROL_2_SEL_DEEMPHASIS_0 (0<<6) + #define PCI1_CFG_LINK_CONTROL_2_SEL_DEEMPHASIS_1 (1<<6) + #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN (0x7<<7) + #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_000 (0<<7) + #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_001 (1<<7) + #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_010 (2<<7) + #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_011 (3<<7) + #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_100 (4<<7) + #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_101 (5<<7) + #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_110 (6<<7) + #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_111 (7<<7) + + u32_t unused_8[8]; + u16_t pci1_cfg_device_ser_num_cap_off; + #define PCI1_CFG_DEVICE_SER_NUM_CAP_OFF_VER (0xf<<0) + #define PCI1_CFG_DEVICE_SER_NUM_CAP_OFF_NEXT (0xfff<<4) + + u16_t pci1_cfg_device_ser_num_cap_id; + u32_t pci1_cfg_lower_ser_num; + u32_t pci1_cfg_upper_ser_num; + u32_t unused_9; + u16_t pci1_cfg_adv_err_cap_off; + #define PCI1_CFG_ADV_ERR_CAP_OFF_VER (0xf<<0) + #define PCI1_CFG_ADV_ERR_CAP_OFF_NEXT (0xfff<<4) + + u16_t pci1_cfg_adv_err_cap_id; + u32_t pci1_cfg_ucorr_err_status; + #define PCI1_CFG_UCORR_ERR_STATUS_DLPES (1UL<<4) + #define PCI1_CFG_UCORR_ERR_STATUS_PTLPS (1UL<<12) + #define PCI1_CFG_UCORR_ERR_STATUS_FCPES (1UL<<13) + #define PCI1_CFG_UCORR_ERR_STATUS_CTS (1UL<<14) + #define PCI1_CFG_UCORR_ERR_STATUS_CAS (1UL<<15) + #define PCI1_CFG_UCORR_ERR_STATUS_UCS (1UL<<16) + #define PCI1_CFG_UCORR_ERR_STATUS_ROS (1UL<<17) + #define PCI1_CFG_UCORR_ERR_STATUS_MTLPS (1UL<<18) + #define PCI1_CFG_UCORR_ERR_STATUS_ECRCS (1UL<<19) + #define PCI1_CFG_UCORR_ERR_STATUS_URES (1UL<<20) + + u32_t pci1_cfg_ucorr_err_mask; + #define PCI1_CFG_UCORR_ERR_MASK_DLPEM (1UL<<4) + #define PCI1_CFG_UCORR_ERR_MASK_SDEM (1UL<<5) + #define PCI1_CFG_UCORR_ERR_MASK_PTLPM (1UL<<12) + #define PCI1_CFG_UCORR_ERR_MASK_FCPEM (1UL<<13) + #define PCI1_CFG_UCORR_ERR_MASK_CTM (1UL<<14) + #define PCI1_CFG_UCORR_ERR_MASK_CAM (1UL<<15) + #define PCI1_CFG_UCORR_ERR_MASK_UCM (1UL<<16) + #define PCI1_CFG_UCORR_ERR_MASK_ROM (1UL<<17) + #define PCI1_CFG_UCORR_ERR_MASK_MTLPM (1UL<<18) + #define PCI1_CFG_UCORR_ERR_MASK_ECRCEM (1UL<<19) + #define PCI1_CFG_UCORR_ERR_MASK_UREM (1UL<<20) + + u32_t pci1_cfg_ucorr_err_sevr; + #define PCI1_CFG_UCORR_ERR_SEVR_DLPES (1UL<<4) + #define PCI1_CFG_UCORR_ERR_SEVR_SDES (1UL<<5) + #define PCI1_CFG_UCORR_ERR_SEVR_PTLPS (1UL<<12) + #define PCI1_CFG_UCORR_ERR_SEVR_FCPES (1UL<<13) + #define PCI1_CFG_UCORR_ERR_SEVR_CTS (1UL<<14) + #define PCI1_CFG_UCORR_ERR_SEVR_CAS (1UL<<15) + #define PCI1_CFG_UCORR_ERR_SEVR_UCS (1UL<<16) + #define PCI1_CFG_UCORR_ERR_SEVR_ROS (1UL<<17) + #define PCI1_CFG_UCORR_ERR_SEVR_MTLPS (1UL<<18) + #define PCI1_CFG_UCORR_ERR_SEVR_ECRCES (1UL<<19) + #define PCI1_CFG_UCORR_ERR_SEVR_URES (1UL<<20) + + u32_t pci1_cfg_corr_err_status; + #define PCI1_CFG_CORR_ERR_STATUS_RES (1UL<<0) + #define PCI1_CFG_CORR_ERR_STATUS_BDLLPS (1UL<<7) + #define PCI1_CFG_CORR_ERR_STATUS_BTLPS (1UL<<7) + #define PCI1_CFG_CORR_ERR_STATUS_RNRS (1UL<<8) + #define PCI1_CFG_CORR_ERR_STATUS_RTTS (1UL<<12) + #define PCI1_CFG_CORR_ERR_STATUS_ANFS (1UL<<13) + + u32_t pci1_cfg_corr_err_mask; + #define PCI1_CFG_CORR_ERR_MASK_RES (1UL<<0) + #define PCI1_CFG_CORR_ERR_MASK_BTLPS (1UL<<6) + #define PCI1_CFG_CORR_ERR_MASK_BDLLPS (1UL<<7) + #define PCI1_CFG_CORR_ERR_MASK_RNRS (1UL<<8) + #define PCI1_CFG_CORR_ERR_MASK_RTTS (1UL<<12) + #define PCI1_CFG_CORR_ERR_MASK_ANFM (1UL<<13) + + u32_t pci1_cfg_adv_err_cap_control; + #define PCI1_CFG_ADV_ERR_CAP_CONTROL_FIRST_UERR_PTR (0x1fUL<<0) + #define PCI1_CFG_ADV_ERR_CAP_CONTROL_ECRCGCAP (1UL<<5) + #define PCI1_CFG_ADV_ERR_CAP_CONTROL_ECRCGEN (1UL<<6) + #define PCI1_CFG_ADV_ERR_CAP_CONTROL_ECRCCAP (1UL<<7) + #define PCI1_CFG_ADV_ERR_CAP_CONTROL_ECRCEN (1UL<<8) + + u32_t pci1_cfg_header_log1; + u32_t pci1_cfg_header_log2; + u32_t pci1_cfg_header_log3; + u32_t pci1_cfg_header_log4; + u32_t unused_10[5]; + u16_t pci1_cfg_pwr_bdgt_cap_off; + #define PCI1_CFG_PWR_BDGT_CAP_OFF_VER (0xf<<0) + #define PCI1_CFG_PWR_BDGT_CAP_OFF_NEXT (0xfff<<4) + + u16_t pci1_cfg_pwr_bdgt_cap_id; + u32_t pci1_cfg_pwr_bdgt_data_sel; + #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE (0xffUL<<0) + #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_0 (0UL<<0) + #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_1 (1UL<<0) + #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_2 (2UL<<0) + #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_3 (3UL<<0) + #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_4 (4UL<<0) + #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_5 (5UL<<0) + #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_6 (6UL<<0) + #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_7 (7UL<<0) + + u32_t pci1_cfg_pwr_bdgt_data; + #define PCI1_CFG_PWR_BDGT_DATA_BASE_PWR (0xffUL<<0) + #define PCI1_CFG_PWR_BDGT_DATA_DSCALE (0x3UL<<8) + #define PCI1_CFG_PWR_BDGT_DATA_PM_STATE (0x3UL<<13) + #define PCI1_CFG_PWR_BDGT_DATA_TYPE (0x7UL<<15) + #define PCI1_CFG_PWR_BDGT_DATA_RAIL (0x7UL<<18) + + u32_t pci1_cfg_pwr_bdgt_capability; + #define PCI1_CFG_PWR_BDGT_CAPABILITY_PCIE_CFG_PB_CAP_SYS_ALLOC (1UL<<0) + + u16_t pci1_cfg_vc_cap_off; + #define PCI1_CFG_VC_CAP_OFF_VER (0xf<<0) + #define PCI1_CFG_VC_CAP_OFF_NEXT (0xfff<<4) + + u16_t pci1_cfg_vc_cap_id; + u32_t pci1_cfg_port_vc_capability; + u32_t pci1_cfg_port_vc_capability2; + u16_t pci1_cfg_port_vc_status; + u16_t pci1_cfg_port_vc_control; + u32_t pci1_cfg_port_arb_table; + u32_t pci1_cfg_vc_rsrc_control; + #define PCI1_CFG_VC_RSRC_CONTROL_TC_VC_MAP (0xffUL<<0) + #define PCI1_CFG_VC_RSRC_CONTROL_VC_ENABLE (1UL<<31) + + u16_t pci1_cfg_vc_rsrc_status; + u16_t pci1_cfg_rsvdp; + u32_t unused_11[161]; + u32_t pci1_grc_window_addr; + #define PCI1_GRC_WINDOW_ADDR_VALUE (0x1ffUL<<13) + #define PCI1_GRC_WINDOW_ADDR_SEP_WIN (1UL<<31) + + u32_t unused_12; + u32_t pci1_config_2; + #define PCI1_CONFIG_2_BAR1_SIZE (0xfUL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_DISABLED (0UL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_64K (1UL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_128K (2UL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_256K (3UL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_512K (4UL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_1M (5UL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_2M (6UL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_4M (7UL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_8M (8UL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_16M (9UL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_32M (10UL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_64M (11UL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_128M (12UL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_256M (13UL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_512M (14UL<<0) + #define PCI1_CONFIG_2_BAR1_SIZE_1G (15UL<<0) + #define PCI1_CONFIG_2_BAR1_64ENA (1UL<<4) + #define PCI1_CONFIG_2_EXP_ROM_RETRY (1UL<<5) + #define PCI1_CONFIG_2_CFG_CYCLE_RETRY (1UL<<6) + #define PCI1_CONFIG_2_FIRST_CFG_DONE (1UL<<7) + #define PCI1_CONFIG_2_EXP_ROM_SIZE (0xffUL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_DISABLED (0UL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_2K (1UL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_4K (2UL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_8K (3UL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_16K (4UL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_32K (5UL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_64K (6UL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_128K (7UL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_256K (8UL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_512K (9UL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_1M (10UL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_2M (11UL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_4M (12UL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_8M (13UL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_16M (14UL<<8) + #define PCI1_CONFIG_2_EXP_ROM_SIZE_32M (15UL<<8) + #define PCI1_CONFIG_2_BAR_PREFETCH (1UL<<16) + #define PCI1_CONFIG_2_RESERVED0 (0x7fffUL<<17) + + u32_t pci1_config_3; + #define PCI1_CONFIG_3_STICKY_BYTE (0xffUL<<0) + #define PCI1_CONFIG_3_REG_STICKY_BYTE (0xffUL<<8) + #define PCI1_CONFIG_3_FORCE_PME (1UL<<24) + #define PCI1_CONFIG_3_PME_STATUS (1UL<<25) + #define PCI1_CONFIG_3_PME_ENABLE (1UL<<26) + #define PCI1_CONFIG_3_PM_STATE (0x3UL<<27) + #define PCI1_CONFIG_3_VAUX_PRESET (1UL<<30) + #define PCI1_CONFIG_3_PCI_POWER (1UL<<31) + + u32_t pci1_pm_data_a; + #define PCI1_PM_DATA_A_PM_DATA_0_PRG (0xffUL<<0) + #define PCI1_PM_DATA_A_PM_DATA_1_PRG (0xffUL<<8) + #define PCI1_PM_DATA_A_PM_DATA_2_PRG (0xffUL<<16) + #define PCI1_PM_DATA_A_PM_DATA_3_PRG (0xffUL<<24) + + u32_t pci1_pm_data_b; + #define PCI1_PM_DATA_B_PM_DATA_4_PRG (0xffUL<<0) + #define PCI1_PM_DATA_B_PM_DATA_5_PRG (0xffUL<<8) + #define PCI1_PM_DATA_B_PM_DATA_6_PRG (0xffUL<<16) + #define PCI1_PM_DATA_B_PM_DATA_7_PRG (0xffUL<<24) + + u32_t pci1_swap_diag0; + u32_t pci1_swap_diag1; + u32_t unused_13[2]; + u32_t pci1_vpd_intf; + #define PCI1_VPD_INTF_INTF_REQ (1UL<<0) + + u16_t unused_14; + u16_t pci1_vpd_addr_flag; + #define PCI1_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) + #define PCI1_VPD_ADDR_FLAG_WR (1<<15) + + u32_t pci1_vpd_data; + u32_t pci1_id_val1; + #define PCI1_ID_VAL1_DEVICE_ID (0xffffUL<<0) + #define PCI1_ID_VAL1_VENDOR_ID (0xffffUL<<16) + + u32_t pci1_id_val2; + #define PCI1_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffUL<<0) + #define PCI1_ID_VAL2_SUBSYSTEM_ID (0xffffUL<<16) + + u32_t pci1_id_val3; + #define PCI1_ID_VAL3_CLASS_CODE (0xffffffUL<<0) + #define PCI1_ID_VAL3_REVISION_ID (0xffUL<<24) + + u32_t pci1_id_val4; + #define PCI1_ID_VAL4_CAP_ENA (0xfUL<<0) + #define PCI1_ID_VAL4_CAP_ENA_0 (0UL<<0) + #define PCI1_ID_VAL4_CAP_ENA_1 (1UL<<0) + #define PCI1_ID_VAL4_CAP_ENA_2 (2UL<<0) + #define PCI1_ID_VAL4_CAP_ENA_3 (3UL<<0) + #define PCI1_ID_VAL4_CAP_ENA_4 (4UL<<0) + #define PCI1_ID_VAL4_CAP_ENA_5 (5UL<<0) + #define PCI1_ID_VAL4_CAP_ENA_6 (6UL<<0) + #define PCI1_ID_VAL4_CAP_ENA_7 (7UL<<0) + #define PCI1_ID_VAL4_CAP_ENA_8 (8UL<<0) + #define PCI1_ID_VAL4_CAP_ENA_9 (9UL<<0) + #define PCI1_ID_VAL4_CAP_ENA_10 (10UL<<0) + #define PCI1_ID_VAL4_CAP_ENA_11 (11UL<<0) + #define PCI1_ID_VAL4_CAP_ENA_12 (12UL<<0) + #define PCI1_ID_VAL4_CAP_ENA_13 (13UL<<0) + #define PCI1_ID_VAL4_CAP_ENA_14 (14UL<<0) + #define PCI1_ID_VAL4_CAP_ENA_15 (15UL<<0) + #define PCI1_ID_VAL4_PM_SCALE_PRG (0x3UL<<6) + #define PCI1_ID_VAL4_PM_SCALE_PRG_0 (0UL<<6) + #define PCI1_ID_VAL4_PM_SCALE_PRG_1 (1UL<<6) + #define PCI1_ID_VAL4_PM_SCALE_PRG_2 (2UL<<6) + #define PCI1_ID_VAL4_PM_SCALE_PRG_3 (3UL<<6) + #define PCI1_ID_VAL4_MSI_PV_MASK_CAP (1UL<<8) + #define PCI1_ID_VAL4_MSI_LIMIT (0x7UL<<9) + #define PCI1_ID_VAL4_MULTI_MSG_CAP (0x7UL<<12) + #define PCI1_ID_VAL4_MSI_ENABLE (1UL<<15) + #define PCI1_ID_VAL4_RESERVED3 (0xffffUL<<16) + + u32_t pci1_id_val5; + #define PCI1_ID_VAL5_D1_SUPPORT (1UL<<0) + #define PCI1_ID_VAL5_D2_SUPPORT (1UL<<1) + #define PCI1_ID_VAL5_PME_IN_D0 (1UL<<2) + #define PCI1_ID_VAL5_PME_IN_D1 (1UL<<3) + #define PCI1_ID_VAL5_PME_IN_D2 (1UL<<4) + #define PCI1_ID_VAL5_PME_IN_D3_HOT (1UL<<5) + #define PCI1_ID_VAL5_PM_VERSION (0x7UL<<6) + #define PCI1_ID_VAL5_NO_SOFT_RESET (1UL<<9) + #define PCI1_ID_VAL5_RESERVED0 (0x3fffffUL<<10) + + u32_t unused_15; + u32_t pci1_id_val6; + #define PCI1_ID_VAL6_BIST (0xffUL<<16) + + u32_t pci1_msi_data; + #define PCI1_MSI_DATA_MSI_DATA (0xffffUL<<0) + + u32_t pci1_msi_addr_h; + u32_t pci1_msi_addr_l; + #define PCI1_MSI_ADDR_L_VAL (0x3fffffffUL<<2) + + u32_t unused_16[2]; + u32_t pci1_msi_mask; + #define PCI1_MSI_MASK_MSI_MASK (0xffffffffUL<<0) + + u32_t pci1_msi_pend; + #define PCI1_MSI_PEND_MSI_PEND (0xffffffffUL<<0) + + u32_t pci1_pm_data_c; + #define PCI1_PM_DATA_C_PM_DATA_8_PRG (0xffUL<<0) + #define PCI1_PM_DATA_C_RESERVED0 (0xffffffUL<<8) + + u32_t unused_17[20]; + u32_t pci1_msix_control; + #define PCI1_MSIX_CONTROL_MSIX_TBL_SIZ (0x7ffUL<<0) + #define PCI1_MSIX_CONTROL_RESERVED0 (0x1fffffUL<<11) + + u32_t pci1_msix_tbl_off_bir; + #define PCI1_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR (0x7UL<<0) + #define PCI1_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF (0x1fffffffUL<<3) + + u32_t pci1_msix_pba_off_bit; + #define PCI1_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR (0x7UL<<0) + #define PCI1_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF (0x1fffffffUL<<3) + + u32_t unused_18; + u32_t pci1_pcie_capability; + #define PCI1_PCIE_CAPABILITY_INTERRUPT_MSG_NUM (0x1fUL<<0) + #define PCI1_PCIE_CAPABILITY_COMPLY_PCIE_1_1 (1UL<<5) + + u32_t pci1_device_capability; + #define PCI1_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED (0x7UL<<0) + #define PCI1_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT (1UL<<5) + #define PCI1_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY (0x7UL<<6) + #define PCI1_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY (0x7UL<<9) + #define PCI1_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT (1UL<<15) + + u32_t unused_19; + u32_t pci1_link_capability; + #define PCI1_LINK_CAPABILITY_MAX_LINK_SPEED (0xfUL<<0) + #define PCI1_LINK_CAPABILITY_MAX_LINK_SPEED_0001 (1UL<<0) + #define PCI1_LINK_CAPABILITY_MAX_LINK_SPEED_0010 (2UL<<0) + #define PCI1_LINK_CAPABILITY_MAX_LINK_WIDTH (0x1fUL<<4) + #define PCI1_LINK_CAPABILITY_CLK_POWER_MGMT (1UL<<9) + #define PCI1_LINK_CAPABILITY_ASPM_SUPPORT (0x3UL<<10) + #define PCI1_LINK_CAPABILITY_L0S_EXIT_LAT (0x7UL<<12) + #define PCI1_LINK_CAPABILITY_L0S_EXIT_LAT_101 (5UL<<12) + #define PCI1_LINK_CAPABILITY_L0S_EXIT_LAT_110 (6UL<<12) + #define PCI1_LINK_CAPABILITY_L1_EXIT_LAT (0x7UL<<15) + #define PCI1_LINK_CAPABILITY_L1_EXIT_LAT_001 (1UL<<15) + #define PCI1_LINK_CAPABILITY_L1_EXIT_LAT_010 (2UL<<15) + #define PCI1_LINK_CAPABILITY_L0S_EXIT_COMM_LAT (0x7UL<<18) + #define PCI1_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101 (5UL<<18) + #define PCI1_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110 (6UL<<18) + #define PCI1_LINK_CAPABILITY_L1_EXIT_COMM_LAT (0x7UL<<21) + #define PCI1_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001 (1UL<<21) + #define PCI1_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010 (2UL<<21) + #define PCI1_LINK_CAPABILITY_PORT_NUM (0xffUL<<24) + + u32_t pci1_bar2_config; + #define PCI1_BAR2_CONFIG_BAR2_SIZE (0xfUL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_DISABLED (0UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_64K (1UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_128K (2UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_256K (3UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_512K (4UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_1M (5UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_2M (6UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_4M (7UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_8M (8UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_16M (9UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_32M (10UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_64M (11UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_128M (12UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_256M (13UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_512M (14UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_SIZE_1G (15UL<<0) + #define PCI1_BAR2_CONFIG_BAR2_64ENA (1UL<<4) + #define PCI1_BAR2_CONFIG_BAR2_PREFETCH (1UL<<5) + #define PCI1_BAR2_CONFIG_RESERVED (0x3ffffffUL<<6) + + u32_t pci1_pcie_device_capability_2; + #define PCI1_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP (0xfUL<<0) + #define PCI1_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP (1UL<<4) + #define PCI1_PCIE_DEVICE_CAPABILITY_2_RESERVED (0x7ffffffUL<<5) + + u32_t pci1_pcie_link_capability_2; + #define PCI1_PCIE_LINK_CAPABILITY_2_RESERVED (0xffffffffUL<<0) + + u32_t unused_20[5]; + u32_t pci1_dev_ser_num_cap_id; + #define PCI1_DEV_SER_NUM_CAP_ID_CAP_ID (0xffffUL<<0) + #define PCI1_DEV_SER_NUM_CAP_ID_CAP_VER (0xfUL<<16) + #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA (0xfUL<<20) + #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_8 (8UL<<20) + #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_9 (9UL<<20) + #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_10 (10UL<<20) + #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_11 (11UL<<20) + #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_12 (12UL<<20) + #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_13 (13UL<<20) + #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_14 (14UL<<20) + #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_15 (15UL<<20) + + u32_t pci1_lower_ser_num; + #define PCI1_LOWER_SER_NUM_LOWER_SER_NUM (0xffffffffUL<<0) + + u32_t pci1_upper_ser_num; + #define PCI1_UPPER_SER_NUM_UPPER_SER_NUM (0xffffffffUL<<0) + + u32_t pci1_adv_err_cap; + #define PCI1_ADV_ERR_CAP_ECRC_CHK_CAP (1UL<<0) + #define PCI1_ADV_ERR_CAP_ECRC_GEN_CAP (1UL<<1) + + u32_t pci1_pwr_bdgt_data_0; + #define PCI1_PWR_BDGT_DATA_0_PWR_BDGT_DATA_0 (0x1fffffUL<<0) + #define PCI1_PWR_BDGT_DATA_0_RESERVED (0x7ffUL<<21) + + u32_t pci1_pwr_bdgt_data_1; + #define PCI1_PWR_BDGT_DATA_1_PWR_BDGT_DATA_1 (0x1fffffUL<<0) + #define PCI1_PWR_BDGT_DATA_1_RW (0x7ffUL<<21) + + u32_t pci1_pwr_bdgt_data_2; + #define PCI1_PWR_BDGT_DATA_2_PWR_BDGT_DATA_2 (0x1fffffUL<<0) + #define PCI1_PWR_BDGT_DATA_2_RW (0x7ffUL<<21) + + u32_t pci1_pwd_bdgt_data_3; + #define PCI1_PWD_BDGT_DATA_3_PWR_BDGT_DATA_3 (0x1fffffUL<<0) + #define PCI1_PWD_BDGT_DATA_3_RW (0x7ffUL<<21) + + u32_t pci1_pwr_bdgt_data_4; + #define PCI1_PWR_BDGT_DATA_4_PWR_BDGT_DATA_4 (0x1fffffUL<<0) + #define PCI1_PWR_BDGT_DATA_4_RW (0x7ffUL<<21) + + u32_t pci1_pwr_bdgt_data_5; + #define PCI1_PWR_BDGT_DATA_5_PWR_BDGT_DATA_5 (0x1fffffUL<<0) + #define PCI1_PWR_BDGT_DATA_5_RW (0x7ffUL<<21) + + u32_t pci1_pwr_bdgt_data_6; + #define PCI1_PWR_BDGT_DATA_6_PWR_BDGT_DATA_6 (0x1fffffUL<<0) + #define PCI1_PWR_BDGT_DATA_6_RW (0x7ffUL<<21) + + u32_t pci1_pwr_bdgt_data_7; + #define PCI1_PWR_BDGT_DATA_7_PWR_BDGT_DATA_7 (0x1fffffUL<<0) + #define PCI1_PWR_BDGT_DATA_7_RW (0x7ffUL<<21) + + u32_t unused_21[8]; + u32_t pci1_pwr_bdgt_capability_ctl; + #define PCI1_PWR_BDGT_CAPABILITY_CTL_PWR_SYSTEM_ALLOC (1UL<<0) + #define PCI1_PWR_BDGT_CAPABILITY_CTL_RESERVED (0x7fffffffUL<<1) + + u32_t unused_22[47]; + u32_t pci1_grc_window1_addr; + #define PCI1_GRC_WINDOW1_ADDR_VALUE (0x1ffUL<<13) + + u32_t pci1_grc_window2_addr; + #define PCI1_GRC_WINDOW2_ADDR_VALUE (0x1ffUL<<13) + + u32_t pci1_grc_window3_addr; + #define PCI1_GRC_WINDOW3_ADDR_VALUE (0x1ffUL<<13) + + u32_t unused_23[9]; + u32_t pci1_exp_rom_adr; + #define PCI1_EXP_ROM_ADR_ADDRESS (0x3fffffUL<<2) + #define PCI1_EXP_ROM_ADR_ADDR_SIZE (0x3UL<<24) + #define PCI1_EXP_ROM_ADR_REQ (1UL<<31) + + u32_t pci1_exp_rom_data0; + u32_t pci1_exp_rom_data1; + u32_t pci1_exp_rom_data2; + u32_t pci1_exp_rom_ctrl; + #define PCI1_EXP_ROM_CTRL_ENA (1UL<<0) + #define PCI1_EXP_ROM_CTRL_BFRD (1UL<<1) + #define PCI1_EXP_ROM_CTRL_ARB_NUM (0x3UL<<4) + #define PCI1_EXP_ROM_CTRL_STATE (0xfUL<<16) + #define PCI1_EXP_ROM_CTRL_CACHE_VALID (1UL<<28) + #define PCI1_EXP_ROM_CTRL_ARB_TIMEOUT (1UL<<29) + #define PCI1_EXP_ROM_CTRL_READ_TIMEOUT (1UL<<30) + #define PCI1_EXP_ROM_CTRL_ACTIVE (1UL<<31) + + u32_t pci1_exp_rom_baddr; + #define PCI1_EXP_ROM_BADDR_VALUE (0x3fffffUL<<2) + + u32_t pci1_exp_rom_cfg; + #define PCI1_EXP_ROM_CFG_ARB_TIMEOUT_SHFT (0xfUL<<0) + #define PCI1_EXP_ROM_CFG_READ_TIMEOUT_SHFT (0xfUL<<4) + + u32_t unused_24[41]; + u32_t pci1_debug_vect_peek; + #define PCI1_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define PCI1_DEBUG_VECT_PEEK_1_EN (1UL<<11) + #define PCI1_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define PCI1_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define PCI1_DEBUG_VECT_PEEK_2_EN (1UL<<27) + #define PCI1_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t unused_25[63]; + u32_t pci1_tl_control_0; + #define PCI1_TL_CONTROL_0_PM_TL_IGNORE_REQS (1UL<<0) + #define PCI1_TL_CONTROL_0_TIMEOUT (0x3fUL<<1) + #define PCI1_TL_CONTROL_0_FUNC0_HIDDEN (1UL<<16) + #define PCI1_TL_CONTROL_0_FUNC1_HIDDEN (1UL<<17) + #define PCI1_TL_CONTROL_0_BEACON_MULTI_LN_EN (1UL<<19) + #define PCI1_TL_CONTROL_0_BEACON_DIS (1UL<<20) + #define PCI1_TL_CONTROL_0_WAKE_L0_L1_EN (1UL<<21) + #define PCI1_TL_CONTROL_0_OOB_EN (1UL<<22) + #define PCI1_TL_CONTROL_0_RST_IGNORE_DLPDOWN (1UL<<23) + #define PCI1_TL_CONTROL_0_DISABL_L1_REENTRY (1UL<<24) + #define PCI1_TL_CONTROL_0_TX_MARGIN_SEL (1UL<<25) + #define PCI1_TL_CONTROL_0_TX_MARGIN_SEL_0 (0UL<<25) + #define PCI1_TL_CONTROL_0_TX_MARGIN_SEL_1 (1UL<<25) + + u32_t pci1_tl_control_1; + #define PCI1_TL_CONTROL_1_EN_4G_CHK (1UL<<0) + #define PCI1_TL_CONTROL_1_EN_4K_CHK (1UL<<1) + #define PCI1_TL_CONTROL_1_EN_BC_CHK (1UL<<2) + #define PCI1_TL_CONTROL_1_EN_BE_CHK (1UL<<3) + #define PCI1_TL_CONTROL_1_EN_EP_CHK (1UL<<4) + #define PCI1_TL_CONTROL_1_EN_MPS_CHECK (1UL<<5) + #define PCI1_TL_CONTROL_1_EN_RCB_CHK (1UL<<6) + #define PCI1_TL_CONTROL_1_EN_RTE_CHK (1UL<<7) + #define PCI1_TL_CONTROL_1_EN_TAC_CHK (1UL<<8) + #define PCI1_TL_CONTROL_1_EN_FC_CHK (1UL<<9) + #define PCI1_TL_CONTROL_1_EN_TO_CHK (1UL<<10) + #define PCI1_TL_CONTROL_1_RESERVED (0x1fffffUL<<11) + + u32_t pci1_tl_control_2; + #define PCI1_TL_CONTROL_2_PES0 (1UL<<0) + #define PCI1_TL_CONTROL_2_FCPES0 (1UL<<1) + #define PCI1_TL_CONTROL_2_CTS0 (1UL<<2) + #define PCI1_TL_CONTROL_2_CAS0 (1UL<<3) + #define PCI1_TL_CONTROL_2_UCS0 (1UL<<4) + #define PCI1_TL_CONTROL_2_ROS0 (1UL<<5) + #define PCI1_TL_CONTROL_2_MTLPS0 (1UL<<6) + #define PCI1_TL_CONTROL_2_ECRCS0 (1UL<<7) + #define PCI1_TL_CONTROL_2_URES0 (1UL<<8) + #define PCI1_TL_CONTROL_2_RXTABRT0 (1UL<<9) + #define PCI1_TL_CONTROL_2_PES1 (1UL<<10) + #define PCI1_TL_CONTROL_2_FCPES1 (1UL<<11) + #define PCI1_TL_CONTROL_2_CTS1 (1UL<<12) + #define PCI1_TL_CONTROL_2_CAS1 (1UL<<13) + #define PCI1_TL_CONTROL_2_UCS1 (1UL<<14) + #define PCI1_TL_CONTROL_2_ROS1 (1UL<<15) + #define PCI1_TL_CONTROL_2_MTLPS1 (1UL<<16) + #define PCI1_TL_CONTROL_2_ECRCS1 (1UL<<17) + #define PCI1_TL_CONTROL_2_URES1 (1UL<<18) + #define PCI1_TL_CONTROL_2_RXTABRT1 (1UL<<19) + #define PCI1_TL_CONTROL_2_DLPES (1UL<<20) + #define PCI1_TL_CONTROL_2_PHYES (1UL<<21) + + u32_t pci1_tl_control_3; + #define PCI1_TL_CONTROL_3_EN_CMPL_RETRY (1UL<<0) + #define PCI1_TL_CONTROL_3_EN_PSND_RETRY (1UL<<1) + #define PCI1_TL_CONTROL_3_EN_HOLD_PHCRDT (1UL<<2) + #define PCI1_TL_CONTROL_3_MAX_INTER_L1_GAP (0xffffUL<<16) + + u32_t pci1_tl_control_4; + #define PCI1_TL_CONTROL_4_RESERVED2 (0xffffUL<<0) + #define PCI1_TL_CONTROL_4_RESERVED1 (0xffffUL<<16) + + u32_t pci1_tl_control_5; + #define PCI1_TL_CONTROL_5_PES0 (1UL<<0) + #define PCI1_TL_CONTROL_5_FCPES0 (1UL<<1) + #define PCI1_TL_CONTROL_5_CTS0 (1UL<<2) + #define PCI1_TL_CONTROL_5_CAS0 (1UL<<3) + #define PCI1_TL_CONTROL_5_UCS0 (1UL<<4) + #define PCI1_TL_CONTROL_5_ROS0 (1UL<<5) + #define PCI1_TL_CONTROL_5_MTLPS0 (1UL<<6) + #define PCI1_TL_CONTROL_5_ECRCS0 (1UL<<7) + #define PCI1_TL_CONTROL_5_URES0 (1UL<<8) + #define PCI1_TL_CONTROL_5_RXTABRT0 (1UL<<9) + #define PCI1_TL_CONTROL_5_PES1 (1UL<<10) + #define PCI1_TL_CONTROL_5_FCPES1 (1UL<<11) + #define PCI1_TL_CONTROL_5_CTS1 (1UL<<12) + #define PCI1_TL_CONTROL_5_CAS1 (1UL<<13) + #define PCI1_TL_CONTROL_5_UCS1 (1UL<<14) + #define PCI1_TL_CONTROL_5_ROS1 (1UL<<15) + #define PCI1_TL_CONTROL_5_MTLPS1 (1UL<<16) + #define PCI1_TL_CONTROL_5_ECRCS1 (1UL<<17) + #define PCI1_TL_CONTROL_5_URES1 (1UL<<18) + #define PCI1_TL_CONTROL_5_RXTABRT1 (1UL<<19) + #define PCI1_TL_CONTROL_5_DLPES (1UL<<20) + #define PCI1_TL_CONTROL_5_PHYES (1UL<<21) + + u32_t unused_26[23]; + u32_t pci1_TL_CTLSTAT_0; + #define PCI1_TL_CTLSTAT_0_PCIE_FUNC_1_HIDDEN (1UL<<0) + #define PCI1_TL_CTLSTAT_0_RESERVED (0x7fffffffUL<<1) + + u32_t pci1_pm_status_0; + #define PCI1_PM_STATUS_0_PME_SENT_SM0 (0x1fUL<<0) + #define PCI1_PM_STATUS_0_PME_SENT_SM1 (0x1fUL<<8) + #define PCI1_PM_STATUS_0_PM_LINK_STATE_SM (0x7fUL<<25) + + u32_t pci1_pm_status_1; + #define PCI1_PM_STATUS_1_CFG_PME_ENABLE0B (1UL<<0) + #define PCI1_PM_STATUS_1_CFG_PME_STATUS0 (1UL<<1) + #define PCI1_PM_STATUS_1_CFG_AUX_PWR_PM_EN0 (1UL<<2) + #define PCI1_PM_STATUS_1_CFG_PME_ENABLE1 (1UL<<3) + #define PCI1_PM_STATUS_1_CFG_PME_STATUS1 (1UL<<4) + #define PCI1_PM_STATUS_1_CFG_AUX_PWR_PM_EN1 (1UL<<5) + + u32_t unused_27[32]; + u32_t pci1_tl_status_0; + #define PCI1_TL_STATUS_0_DEVICE_NO (0xfUL<<0) + #define PCI1_TL_STATUS_0_FUNC_NO (0x7UL<<4) + #define PCI1_TL_STATUS_0_TC (0x7UL<<7) + #define PCI1_TL_STATUS_0_ATTR (0x3UL<<10) + #define PCI1_TL_STATUS_0_BYTE_COUNT (0x1fffUL<<12) + #define PCI1_TL_STATUS_0_LWR_ADDR (0x7fUL<<25) + + u32_t pci1_tl_status_1; + u32_t pci1_tl_status_2; + u32_t pci1_tl_status_3; + u32_t pci1_tl_status_4; + u32_t pci1_tl_status_5; + u32_t pci1_tl_status_6; + u32_t pci1_tl_status_7; + u32_t pci1_tl_status_8; + u32_t pci1_tl_status_9; + u32_t pci1_tl_status_10; + u32_t pci1_tl_status_11; + u32_t pci1_tl_status_12; + u32_t pci1_tl_status_13; + u32_t pci1_tl_status_14; + u32_t pci1_tl_status_15; + u32_t pci1_tl_status_16; + u32_t pci1_tl_status_17; + u32_t pci1_tl_status_18; + u32_t pci1_tl_status_19; + u32_t pci1_tl_status_20; + u32_t pci1_tl_status_21; + u32_t pci1_tl_status_22; + u32_t pci1_tl_status_23; + u32_t pci1_tl_status_24; + u32_t pci1_tl_status_25; + u32_t pci1_tl_status_26; + u32_t pci1_tl_status_27; + u32_t pci1_tl_status_28; + u32_t pci1_tl_status_29; + u32_t pci1_tl_status_30; + u32_t pci1_tl_status_31; + u32_t pci1_tl_hdr_fc_st; + #define PCI1_TL_HDR_FC_ST_NPH_AVAIL (0xffUL<<0) + #define PCI1_TL_HDR_FC_ST_PH_AVAIL (0xffUL<<8) + #define PCI1_TL_HDR_FC_ST_CPLH_AVAIL (0xffUL<<16) + + u32_t pci1_tl_dat_fc_st; + #define PCI1_TL_DAT_FC_ST_PD_AVAIL (0xfffUL<<0) + #define PCI1_TL_DAT_FC_ST_CPLD_AVAIL (0xfffUL<<16) + + u32_t pci1_tl_hdr_fccon_st; + #define PCI1_TL_HDR_FCCON_ST_NPH_CC (0xffUL<<0) + #define PCI1_TL_HDR_FCCON_ST_PH_CC (0xffUL<<8) + #define PCI1_TL_HDR_FCCON_ST_CPLH_CC (0xffUL<<16) + + u32_t pci1_tl_dat_fccon_st; + #define PCI1_TL_DAT_FCCON_ST_PD_CC (0xfffUL<<0) + #define PCI1_TL_DAT_FCCON_ST_CPLD_CC (0xfffUL<<16) + + u32_t pci1_tl_tgt_crdt_st; + #define PCI1_TL_TGT_CRDT_ST_PH_CRDT_CNTR (0x7fUL<<0) + #define PCI1_TL_TGT_CRDT_ST_PD_CRDT_CNTR (0x7fUL<<8) + #define PCI1_TL_TGT_CRDT_ST_NP_CRDT_CNTR (1UL<<16) + + u32_t pci1_tl_crdt_alloc_st; + #define PCI1_TL_CRDT_ALLOC_ST_NPH_ALLOC (0xffUL<<0) + #define PCI1_TL_CRDT_ALLOC_ST_NPD_ALLOC (0xffUL<<8) + #define PCI1_TL_CRDT_ALLOC_ST_PH_ALLOC (0xffUL<<16) + #define PCI1_TL_CRDT_ALLOC_ST_PD_ALLOC (0xffUL<<24) + + u32_t pci1_tl_smlogic_st; + #define PCI1_TL_SMLOGIC_ST_NP_CURR_STATE (0xfUL<<0) + #define PCI1_TL_SMLOGIC_ST_PH_CURR_STATE (0xfUL<<4) + #define PCI1_TL_SMLOGIC_ST_CPL_CURR_STATE (0x3UL<<8) + #define PCI1_TL_SMLOGIC_ST_TX_SM (0x7UL<<16) + + u32_t unused_28[409]; + u32_t pci1_pdl_control_0; + #define PCI1_PDL_CONTROL_0_ENABLE_SCRAMB (1UL<<0) + #define PCI1_PDL_CONTROL_0_DISABLE_REVERSE (1UL<<1) + #define PCI1_PDL_CONTROL_0_DISABLE_REPLAY_TIMER (1UL<<2) + #define PCI1_PDL_CONTROL_0_DISABLE_FRAM_CHECK (1UL<<3) + #define PCI1_PDL_CONTROL_0_DISABLE_CRC_DLL (1UL<<4) + #define PCI1_PDL_CONTROL_0_DISABLE_CRC_DLP (1UL<<5) + #define PCI1_PDL_CONTROL_0_DISABLE_REPLAY_BUFF (1UL<<6) + #define PCI1_PDL_CONTROL_0_DISABLE_SKEW_RET (1UL<<7) + #define PCI1_PDL_CONTROL_0_ENABLE_COMPLIANCE (1UL<<8) + #define PCI1_PDL_CONTROL_0_DISABLE_8B10_BYPAS (1UL<<9) + #define PCI1_PDL_CONTROL_0_DISABLE_LOST_SYNCH (1UL<<10) + #define PCI1_PDL_CONTROL_0_DISABLE_AUTO_CRDUPD (1UL<<11) + #define PCI1_PDL_CONTROL_0_DISABLE_RETRAIN_REQ (1UL<<12) + #define PCI1_PDL_CONTROL_0_FORCE_L0TOL1 (1UL<<13) + #define PCI1_PDL_CONTROL_0_RESERVED (1UL<<14) + #define PCI1_PDL_CONTROL_0_DISABLE_REV_LANE (1UL<<15) + #define PCI1_PDL_CONTROL_0_ENABLE_TX_ERR_MUX (1UL<<16) + #define PCI1_PDL_CONTROL_0_ENABLE_RX_ERR_MUX (1UL<<17) + #define PCI1_PDL_CONTROL_0_ENABLE_ERR_FRAMING (1UL<<18) + #define PCI1_PDL_CONTROL_0_ENABLE_SINGLE_ERR (1UL<<19) + #define PCI1_PDL_CONTROL_0_ENCOMFORSIG (1UL<<20) + #define PCI1_PDL_CONTROL_0_DISABLE_TLPRDNXT (1UL<<21) + #define PCI1_PDL_CONTROL_0_DISABLE_GENE_TIMER (1UL<<22) + #define PCI1_PDL_CONTROL_0_DISABLETXDETECT (1UL<<23) + #define PCI1_PDL_CONTROL_0_LOOPBACK_CNTL_REG (0x7UL<<24) + #define PCI1_PDL_CONTROL_0_FORCE_L0TOL2 (1UL<<27) + #define PCI1_PDL_CONTROL_0_DISABLE_HOT_SERDES (1UL<<28) + #define PCI1_PDL_CONTROL_0_DISSKEWCHECK (1UL<<29) + #define PCI1_PDL_CONTROL_0_DISABLERXSKIP (1UL<<30) + #define PCI1_PDL_CONTROL_0_FORCE_RECTOCONF (1UL<<31) + + u32_t pci1_pdl_control_1; + #define PCI1_PDL_CONTROL_1_MAX_DLP_IDLE_CNT (0x7fUL<<0) + #define PCI1_PDL_CONTROL_1_DISABLE_CC_DESKEW (1UL<<8) + #define PCI1_PDL_CONTROL_1_DISABLE_DLPTX_BB (1UL<<10) + #define PCI1_PDL_CONTROL_1_FORCE_L0TOL0S (1UL<<11) + #define PCI1_PDL_CONTROL_1_MAX_REPLAY_NUM (0x3UL<<12) + #define PCI1_PDL_CONTROL_1_RETRAIN_REQ (1UL<<14) + #define PCI1_PDL_CONTROL_1_PHYRX_DETECT_ERROR_DIS (1UL<<15) + #define PCI1_PDL_CONTROL_1_MAX_DLP_L1_ENTRANCE (0x7fUL<<16) + #define PCI1_PDL_CONTROL_1_REPLAY_INTDEL_GEN2 (0x1ffUL<<23) + + u32_t pci1_pdl_control_2; + #define PCI1_PDL_CONTROL_2_MAX_SYMB_SKIP_OS (0x7UL<<0) + #define PCI1_PDL_CONTROL_2_ENABLE_ACK_LAT_TIMER (1UL<<3) + #define PCI1_PDL_CONTROL_2_SW_ACK_LAT_SEL (1UL<<4) + #define PCI1_PDL_CONTROL_2_SW_REPLAY_TIMER_SEL (1UL<<5) + #define PCI1_PDL_CONTROL_2_SELDETECT_DELAY (0x3UL<<6) + #define PCI1_PDL_CONTROL_2_MAX_WAIT_RX_L0S_ENTRY (0xfUL<<8) + #define PCI1_PDL_CONTROL_2_MAX_WAIT_TX_L0S_ENTRY (0xfUL<<12) + #define PCI1_PDL_CONTROL_2_ENABLE_CRD_LAT_P (1UL<<16) + #define PCI1_PDL_CONTROL_2_ENABLE_CRD_LAT_N (1UL<<17) + #define PCI1_PDL_CONTROL_2_CORR_ERR_REG_MAX (0x3ffUL<<18) + #define PCI1_PDL_CONTROL_2_DISABLE_DESKEW_ERR (1UL<<28) + #define PCI1_PDL_CONTROL_2_ENABLE_SKIP_RST_ERR (1UL<<29) + #define PCI1_PDL_CONTROL_2_DISABLE_FASTACQ (1UL<<30) + #define PCI1_PDL_CONTROL_2_DISABLE_RX_ELEC (1UL<<31) + + u32_t pci1_pdl_control_3; + #define PCI1_PDL_CONTROL_3_MAX_TX_FTS_LIMIT (0xffUL<<0) + #define PCI1_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_LONG (0xffUL<<8) + #define PCI1_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_GEN2 (0xffUL<<16) + #define PCI1_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_LONG_GEN2 (0xffUL<<24) + + u32_t pci1_pdl_control_4; + #define PCI1_PDL_CONTROL_4_NPD_FC_INIT (0xfffUL<<0) + #define PCI1_PDL_CONTROL_4_PD_FC_INIT (0xfffUL<<12) + #define PCI1_PDL_CONTROL_4_NPH_FC_INIT (0xffUL<<24) + + u32_t pci1_pdl_control_5; + #define PCI1_PDL_CONTROL_5_PH_FC_INIT (0xffUL<<0) + #define PCI1_PDL_CONTROL_5_LINK_UPSTREAM (1UL<<8) + #define PCI1_PDL_CONTROL_5_GLOOPBACK (1UL<<9) + #define PCI1_PDL_CONTROL_5_RESERVED (0x3fUL<<10) + #define PCI1_PDL_CONTROL_5_LOOPBACK_REG (0xffffUL<<16) + + u32_t pci1_pdl_control_6; + #define PCI1_PDL_CONTROL_6_LOOPBACK_REG (0xffffffffUL<<0) + + u32_t pci1_pdl_control_7; + #define PCI1_PDL_CONTROL_7_LOOPBACK_REG (0xffffffffUL<<0) + + u32_t pci1_pdl_control_8; + #define PCI1_PDL_CONTROL_8_LOOPBACK_REG (0xffffffffUL<<0) + + u32_t pci1_pdl_control_9; + #define PCI1_PDL_CONTROL_9_LOOPBACK_REG (0xffffffffUL<<0) + + u32_t pci1_pdl_control_10; + #define PCI1_PDL_CONTROL_10_DL_HI_WATERMARK (0x1fUL<<0) + #define PCI1_PDL_CONTROL_10_DL_CS_RXENABLE (1UL<<8) + #define PCI1_PDL_CONTROL_10_DL_CS_ENABLE (1UL<<9) + #define PCI1_PDL_CONTROL_10_DL_CS_WRITE_NULLIFY (1UL<<10) + #define PCI1_PDL_CONTROL_10_DL_CS_NULLIFY (1UL<<11) + + u32_t pci1_pdl_control_11; + #define PCI1_PDL_CONTROL_11_REPLAY_TIMER_LIMIT_GEN1 (0xfffUL<<0) + #define PCI1_PDL_CONTROL_11_REPLAY_TIMER_LIMIT_GEN2 (0xfffUL<<12) + #define PCI1_PDL_CONTROL_11_RESERVED (0xffUL<<24) + + u32_t pci1_pdl_control_12; + #define PCI1_PDL_CONTROL_12_UPDATE_FREQ_GEN1 (0xffUL<<0) + #define PCI1_PDL_CONTROL_12_UPDATE_FREQ_GEN2 (0xffUL<<8) + #define PCI1_PDL_CONTROL_12_RESERVED (0xffffUL<<16) + + u32_t pci1_pdl_control_13; + #define PCI1_PDL_CONTROL_13_ACK_LATENCY_TIMER_GEN1 (0x3ffUL<<0) + #define PCI1_PDL_CONTROL_13_ACK_LATENCY_TIMER_GEN2 (0x3ffUL<<10) + #define PCI1_PDL_CONTROL_13_ACK_INTDEL_GEN2 (0xffUL<<20) + #define PCI1_PDL_CONTROL_13_RESERVED (0xfUL<<28) + + u32_t pci1_pdl_control_14; + #define PCI1_PDL_CONTROL_14_DEBUG_EXT_SEL_0 (0x1fffUL<<0) + #define PCI1_PDL_CONTROL_14_DEBUG_EXT_SEL_1 (0x1fffUL<<13) + #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_0 (0x3UL<<27) + #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_0_00 (0UL<<27) + #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_0_01 (1UL<<27) + #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_0_10 (2UL<<27) + #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_0_11 (2UL<<27) + #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_1 (0x3UL<<29) + #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_1_00 (0UL<<29) + #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_1_01 (1UL<<29) + #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_1_10 (2UL<<29) + #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_1_11 (2UL<<29) + #define PCI1_PDL_CONTROL_14_DEBUG_GRC_ENA (1UL<<31) + + u32_t pci1_pdl_control_15; + #define PCI1_PDL_CONTROL_15_FORCE_UPDATE_GEN2 (0x7fffUL<<0) + #define PCI1_PDL_CONTROL_15_FORCE_UPDATE_EXTENDED_SYNC_GEN2 (0x7fffUL<<15) + + u32_t pci1_DL_ATTN_VECTOR; + #define PCI1_DL_ATTN_VECTOR_DL_CKSUM_ERR_AT (1UL<<0) + #define PCI1_DL_ATTN_VECTOR_DL_D2TBUF_OFLOW_ERR (1UL<<1) + #define PCI1_DL_ATTN_VECTOR_DLP2TLP_PARITY_ERROR (1UL<<2) + #define PCI1_DL_ATTN_VECTOR_REPLAY_ADDRESS_PARITY_ERROR (1UL<<3) + #define PCI1_DL_ATTN_VECTOR_REPLAY_WRAPPER_PARITY_ERROR (1UL<<4) + #define PCI1_DL_ATTN_VECTOR_DL_CORRECTABLE_ERROR (1UL<<5) + #define PCI1_DL_ATTN_VECTOR_DE_FRAMING_ERROR (1UL<<6) + #define PCI1_DL_ATTN_VECTOR_DLP_ERROR_STATUS (1UL<<7) + #define PCI1_DL_ATTN_VECTOR_DLP_INCORRECT (1UL<<8) + #define PCI1_DL_ATTN_VECTOR_TLPBUFRDERR (1UL<<9) + #define PCI1_DL_ATTN_VECTOR_REPLAY_SEQUENCE_OVERRUN (1UL<<10) + #define PCI1_DL_ATTN_VECTOR_DLL_ERROR_ACK (1UL<<11) + #define PCI1_DL_ATTN_VECTOR_REPLAY_BUFFER_OVERRUN (1UL<<12) + #define PCI1_DL_ATTN_VECTOR_REPLAY_NUMBER_ROLL_OVER (1UL<<13) + #define PCI1_DL_ATTN_VECTOR_REPLAY_TIMEOUT (1UL<<14) + #define PCI1_DL_ATTN_VECTOR_FCPE_ERROR_STATUS (1UL<<15) + #define PCI1_DL_ATTN_VECTOR_DLL_ERROR_STATUS (1UL<<16) + #define PCI1_DL_ATTN_VECTOR_DLL_PE_INIT_STATUS (1UL<<17) + #define PCI1_DL_ATTN_VECTOR_COL_FULL (1UL<<18) + #define PCI1_DL_ATTN_VECTOR_TLP_INCORRECT (1UL<<19) + #define PCI1_DL_ATTN_VECTOR_TLP_SYNC_ERROR (1UL<<20) + + u32_t pci1_DL_ATTN_MASK; + #define PCI1_DL_ATTN_MASK_MASK_FOR_DL_ATTENTIONS (0x1fffffUL<<0) + #define PCI1_DL_ATTN_MASK_RESERVED1 (0x7ffUL<<21) + + u32_t pci1_DL_STATUS; + #define PCI1_DL_STATUS_CORR_ERR_REG (0x3ffUL<<0) + #define PCI1_DL_STATUS_REPLAY_ALM_FULL (1UL<<10) + #define PCI1_DL_STATUS_PHYLINKUP (1UL<<13) + #define PCI1_DL_STATUS_DL_ACTIVE (1UL<<14) + #define PCI1_DL_STATUS_DL_INIT (1UL<<15) + #define PCI1_DL_STATUS_RESERVED (0xffffUL<<16) + + u32_t pci1_DL_TX_Checksum; + #define PCI1_DL_TX_CHECKSUM_EXPECTED_TX_CHECKSUM (0xffffUL<<0) + #define PCI1_DL_TX_CHECKSUM_ACTUAL_TX_CHECKSUM (0xffffUL<<16) + + u32_t pci1_dl_forced_update_gen1; + #define PCI1_DL_FORCED_UPDATE_GEN1_FORCE_UPDATE_GEN1 (0x7fffUL<<0) + #define PCI1_DL_FORCED_UPDATE_GEN1_FORCE_UPDATE_EXTENDED_SYNC_GEN1 (0x7fffUL<<15) + + u32_t unused_29[43]; + u32_t pci1_mdio_addr; + #define PCI1_MDIO_ADDR_ADR (0xffffUL<<0) + #define PCI1_MDIO_ADDR_PORT (0xfUL<<16) + #define PCI1_MDIO_ADDR_CMD (0xfffUL<<20) + + u32_t pci1_mdio_wr_data; + #define PCI1_MDIO_WR_DATA_DATA (0xffffUL<<0) + #define PCI1_MDIO_WR_DATA_CMD (1UL<<31) + + u32_t pci1_mdio_rd_data; + #define PCI1_MDIO_RD_DATA_DATA (0xffffUL<<0) + #define PCI1_MDIO_RD_DATA_CMD (1UL<<31) + + u32_t unused_30[189]; + u32_t pci1_dl_rx_pn_credit_limit; + #define PCI1_DL_RX_PN_CREDIT_LIMIT_DL_RX_PN_CREDIT_LIMIT (0xffffffffUL<<0) + + u32_t pci1_dl_rx_c_credit_limit; + #define PCI1_DL_RX_C_CREDIT_LIMIT_DL_RX_C_CREDIT_LIMIT (0xffffffffUL<<0) + + u32_t pci1_dl_rx_ack_nack; + #define PCI1_DL_RX_ACK_NACK_DL_RX_ACK_NACK (0xffffffffUL<<0) + + u32_t pci1_dl_coldat_lsb; + #define PCI1_DL_COLDAT_LSB_DL_COLDAT_LSB (0xffffffffUL<<0) + + u32_t pci1_dl_coldat_msb; + #define PCI1_DL_COLDAT_MSB_DL_COLDAT_MSB (0xffffffffUL<<0) + + u32_t pci1_dl_colcntl; + #define PCI1_DL_COLCNTL_DL_COLCNTL (0xffffffffUL<<0) + + u32_t pci1_dl_coldeb; + #define PCI1_DL_COLDEB_DL_COLDEB (0xffffffffUL<<0) + + u32_t pci1_dl_pwr_mgmt; + #define PCI1_DL_PWR_MGMT_DL_PWR_MGMT (0xffffffffUL<<0) + + u32_t pci1_dl_t2d_rxcksum; + #define PCI1_DL_T2D_RXCKSUM_DL_T2D_RXCKSUM (0xffffffffUL<<0) + + u32_t pci1_dl_resend0_dlptx0; + #define PCI1_DL_RESEND0_DLPTX0_DL_RESEND0_DLPTX0 (0xffffffffUL<<0) + + u32_t pci1_dl_resend1_dlptx1; + #define PCI1_DL_RESEND1_DLPTX1_DL_RESEND1_DLPTX1 (0xffffffffUL<<0) + + u32_t pci1_dl_resend2_dlptx2; + #define PCI1_DL_RESEND2_DLPTX2_DL_RESEND2_DLPTX2 (0xffffffffUL<<0) + + u32_t pci1_dl_resend2_dlptx3; + #define PCI1_DL_RESEND2_DLPTX3_DL_RESEND2_DLPTX3 (0xffffffffUL<<0) + + u32_t pci1_dl_phyrx0_d2trx0; + #define PCI1_DL_PHYRX0_D2TRX0_DL_PHYRX0_D2TRX0 (0xffffffffUL<<0) + + u32_t pci1_dl_phyrx1_d2trx1; + #define PCI1_DL_PHYRX1_D2TRX1_DL_PHYRX1_D2TRX1 (0xffffffffUL<<0) + + u32_t pci1_dl_phyrx2_d2trx1; + #define PCI1_DL_PHYRX2_D2TRX1_DL_PHYRX2_D2TRX1 (0xffffffffUL<<0) + + u32_t pci1_dl_coldeb_vec1; + #define PCI1_DL_COLDEB_VEC1_DL_COLDEB_VEC1 (0xffffffffUL<<0) + + u32_t pci1_dl_d2tbuf_0; + #define PCI1_DL_D2TBUF_0_DL_D2TBUF_0 (0xffffffffUL<<0) + + u32_t pci1_dl_d2trx1; + #define PCI1_DL_D2TRX1_DL_D2TRX1 (0xffffffffUL<<0) + + u32_t pci1_dl_tx_nullify; + #define PCI1_DL_TX_NULLIFY_DL_TX_NULLIFY (0xffffffffUL<<0) + + u32_t pci1_dl_datapathtx0; + #define PCI1_DL_DATAPATHTX0_DL_DATAPATHTX0 (0xffffffffUL<<0) + + u32_t pci1_dl_datapathtx1; + #define PCI1_DL_DATAPATHTX1_DL_DATAPATHTX1 (0xffffffffUL<<0) + + u32_t pci1_dl_datapathtx2; + #define PCI1_DL_DATAPATHTX2_DL_DATAPATHTX2 (0xffffffffUL<<0) + + u32_t pci1_dl_dllrx0; + #define PCI1_DL_DLLRX0_DL_DLLRX0 (0xffffffffUL<<0) + + u32_t pci1_dl_dllrx1; + #define PCI1_DL_DLLRX1_DL_DLLRX1 (0xffffffffUL<<0) + + u32_t pci1_dl_dllrx2; + #define PCI1_DL_DLLRX2_DL_DLLRX2 (0xffffffffUL<<0) + + u32_t pci1_dl_rx_tx; + #define PCI1_DL_RX_TX_DL_RX_TX (0xffffffffUL<<0) + + u32_t pci1_dbg_dl_ctrl_status0; + #define PCI1_DBG_DL_CTRL_STATUS0_MAX_FORCE_UPDATE (0x7fffUL<<0) + #define PCI1_DBG_DL_CTRL_STATUS0_EXTENDED_SYNC (1UL<<15) + #define PCI1_DBG_DL_CTRL_STATUS0_FORCE_UPD_VAL_FOR_GEN1 (0x7fffUL<<16) + #define PCI1_DBG_DL_CTRL_STATUS0_PCIE_PHY_RATE (1UL<<31) + + u32_t pci1_dbg_dl_ctrl_status1; + #define PCI1_DBG_DL_CTRL_STATUS1_MAX_FORCE_UPDATE (0x7fffUL<<0) + #define PCI1_DBG_DL_CTRL_STATUS1_MAX_UPDATE_FREQUENCY (0x1ffUL<<15) + #define PCI1_DBG_DL_CTRL_STATUS1_MAX_REPLAY_TIMER (0xffUL<<24) + + u32_t pci1_dbg_dl_ctrl_status2; + #define PCI1_DBG_DL_CTRL_STATUS2_DBG_MAX_REPLAY_TIMER (0x1fffUL<<0) + #define PCI1_DBG_DL_CTRL_STATUS2_RX_L0S_ADJUSTMENT_R (0x3ffUL<<13) + #define PCI1_DBG_DL_CTRL_STATUS2_DBG_MAX_REPLAY_TIMER_LIMIT (0x1ffUL<<23) + + u32_t pci1_dbg_dl_ctrl_status3; + #define PCI1_DBG_DL_CTRL_STATUS3_MAX_REPLAY_TIMER_LIMIT (0xfffUL<<0) + #define PCI1_DBG_DL_CTRL_STATUS3_REPLAYLIMIT_WO_INTDEL (0xfffUL<<12) + #define PCI1_DBG_DL_CTRL_STATUS3_REPLAY_INTDEL (0xffUL<<24) + + u32_t unused_31[225]; + u32_t pci1_phy_ctl_0; + #define PCI1_PHY_CTL_0_SPEED_CHANGE_REQ (1UL<<1) + #define PCI1_PHY_CTL_0_WIDTH_CHANGE_REQ (1UL<<1) + #define PCI1_PHY_CTL_0_DIS_X2_LINK_WIDTH (1UL<<2) + #define PCI1_PHY_CTL_0_LINK_LOOPBACK (1UL<<3) + #define PCI1_PHY_CTL_0_LINK_DISABLE (1UL<<4) + #define PCI1_PHY_CTL_0_IDL_TO_RLOCK_ENA (1UL<<5) + #define PCI1_PHY_CTL_0_UPCONFIG_ENA (1UL<<6) + #define PCI1_PHY_CTL_0_HI_AVAIL_COMPLI_EN (1UL<<7) + #define PCI1_PHY_CTL_0_RESERVED (0xffffffUL<<8) + + u32_t pci1_phy_ctl_1; + #define PCI1_PHY_CTL_1_FORCE_16BIT (1UL<<0) + #define PCI1_PHY_CTL_1_AUTO_TRAIN_ENA (1UL<<1) + #define PCI1_PHY_CTL_1_LANE_PWRDN_ENA (1UL<<2) + #define PCI1_PHY_CTL_1_P2_PWRDWN_ENA (1UL<<3) + #define PCI1_PHY_CTL_1_FAREND_LPBK_REQ (1UL<<4) + #define PCI1_PHY_CTL_1_DIS_SKIP_IN_SPEED (1UL<<5) + #define PCI1_PHY_CTL_1_RESERVED1 (1UL<<6) + #define PCI1_PHY_CTL_1_EIDL_DLY (0x1fUL<<7) + #define PCI1_PHY_CTL_1_RESERVED (0xfffffUL<<12) + + u32_t pci1_phy_ctl_2; + u32_t pci1_phy_ctl_3; + u32_t pci1_phy_ctl_4; + #define PCI1_PHY_CTL_4_PRESCALE (0x7ffUL<<0) + #define PCI1_PHY_CTL_4_RESERVED_B (0x1fUL<<11) + #define PCI1_PHY_CTL_4_EIDL_RX_MAX (0x7ffUL<<16) + #define PCI1_PHY_CTL_4_EIDL_RX_PRESCALE (1UL<<27) + #define PCI1_PHY_CTL_4_RESERVED (0xfUL<<28) + + u32_t pci1_phy_ctl_5; + #define PCI1_PHY_CTL_5_EIDL_TX_GOOD_MAX (0x7ffUL<<0) + #define PCI1_PHY_CTL_5_RESERVED_2 (0x1fUL<<11) + #define PCI1_PHY_CTL_5_EIDL_TX_BAD_MAX (0x7ffUL<<16) + #define PCI1_PHY_CTL_5_RESERVED (0x1fUL<<27) + + u32_t pci1_phy_ctl_6; + #define PCI1_PHY_CTL_6_EIDL_INF_COM_MAX (0x7ffUL<<0) + #define PCI1_PHY_CTL_6_EIDL_INF_COM_PRESCALE (1UL<<11) + #define PCI1_PHY_CTL_6_RESERVED (0x7UL<<12) + #define PCI1_PHY_CTL_6_EIDL_INF_EIES_PRESCALE (1UL<<15) + #define PCI1_PHY_CTL_6_EIDL_INF_EIES_MAX (0xffffUL<<16) + + u32_t pci1_phy_ctl_7; + #define PCI1_PHY_CTL_7_L1_MIN_WAIT_MAX (0x3fUL<<0) + #define PCI1_PHY_CTL_7_RESERVED1 (0x3ffUL<<6) + #define PCI1_PHY_CTL_7_DETECT_MIN_WAIT_MAX (0x3fffUL<<16) + #define PCI1_PHY_CTL_7_RESERVED (0x3UL<<30) + + u32_t pci1_phy_err_attn_vec; + #define PCI1_PHY_ERR_ATTN_VEC_ELASTIC_ERR (1UL<<0) + #define PCI1_PHY_ERR_ATTN_VEC_DISPARITY_ERR (1UL<<1) + #define PCI1_PHY_ERR_ATTN_VEC_DECODE_ERR (1UL<<2) + #define PCI1_PHY_ERR_ATTN_VEC_LINK_IS_SKEW (1UL<<3) + #define PCI1_PHY_ERR_ATTN_VEC_TRAIN_ERR (1UL<<4) + #define PCI1_PHY_ERR_ATTN_VEC_L0S_MAIN_ERR (1UL<<5) + #define PCI1_PHY_ERR_ATTN_VEC_RETRAIN_REQ (1UL<<6) + #define PCI1_PHY_ERR_ATTN_VEC_CC_ERR_STATUS (1UL<<7) + #define PCI1_PHY_ERR_ATTN_VEC_RESERVED (0xffffffUL<<8) + + u32_t pci1_phy_err_attn_mask; + #define PCI1_PHY_ERR_ATTN_MASK_MASK_ELASTIC_ERR (1UL<<0) + #define PCI1_PHY_ERR_ATTN_MASK_MASK_DISPARITY_ERR (1UL<<1) + #define PCI1_PHY_ERR_ATTN_MASK_MASK_DECODE_ERR (1UL<<2) + #define PCI1_PHY_ERR_ATTN_MASK_MASK_LINK_IS_SKEW (1UL<<3) + #define PCI1_PHY_ERR_ATTN_MASK_MASK_TRAIN_ERR (1UL<<4) + #define PCI1_PHY_ERR_ATTN_MASK_MASK_L0S_MAIN_ERR (1UL<<5) + #define PCI1_PHY_ERR_ATTN_MASK_MASK_RETRAIN_REQ (1UL<<6) + #define PCI1_PHY_ERR_ATTN_MASK_MASK_CC_ERR_STATUS (1UL<<7) + #define PCI1_PHY_ERR_ATTN_MASK_RESERVED (0xffffffUL<<8) + + u32_t unused_32[307]; + u32_t pci1_phy_ltssm_hist_0; + #define PCI1_PHY_LTSSM_HIST_0_LTSSM_HIST_0 (0xffffffffUL<<0) + + u32_t pci1_phy_ltssm_hist_1; + #define PCI1_PHY_LTSSM_HIST_1_LTSSM_HIST_1 (0xffffffffUL<<0) + + u32_t pci1_phy_ltssm_hist_2; + #define PCI1_PHY_LTSSM_HIST_2_LTSSM_HIST_2 (0xffffffffUL<<0) + + u32_t pci1_phy_dbg_0; + #define PCI1_PHY_DBG_0_PHY_DBG_0 (0xffffffffUL<<0) + + u32_t pci1_phy_dbg_1; + #define PCI1_PHY_DBG_1_PHY_DBG_1 (0xffffffffUL<<0) + + u32_t pci1_phy_dbg_2; + #define PCI1_PHY_DBG_2_PHY_DBG_2 (0xffffffffUL<<0) + + u32_t pci1_phy_dbg_3; + #define PCI1_PHY_DBG_3_PHY_DBG_3 (0xffffffffUL<<0) + + u32_t pci1_phy_dbg_4; + #define PCI1_PHY_DBG_4_PHY_DBG_4 (0xffffffffUL<<0) + + u32_t pci1_phy_dbg_5; + #define PCI1_PHY_DBG_5_PHY_DBG_5 (0xffffffffUL<<0) + + u32_t pci1_phy_dbg_6; + #define PCI1_PHY_DBG_6_PHY_DBG_6 (0xffffffffUL<<0) + + u32_t pci1_phy_dbg_7; + #define PCI1_PHY_DBG_7_PHY_DBG_7 (0xffffffffUL<<0) + + u32_t pci1_phy_dbg_8; + #define PCI1_PHY_DBG_8_PHY_DBG_8 (0xffffffffUL<<0) + + u32_t pci1_phy_dbg_9; + #define PCI1_PHY_DBG_9_PHY_DBG_9 (0xffffffffUL<<0) + + u32_t pci1_phy_dbg_10; + #define PCI1_PHY_DBG_10_PHY_DBG_10 (0xffffffffUL<<0) + + u32_t pci1_phy_dbg_11; + #define PCI1_PHY_DBG_11_PHY_DBG_11 (0xffffffffUL<<0) + + u32_t unused_33[180]; + u32_t pci1_function1[1536]; + u32_t unused_34[12800]; +} pcie_reg_t; + + +/* + * misc_reg definition + * offset: 0x800 + */ +typedef struct misc_reg +{ + u32_t misc_command; + #define MISC_COMMAND_ENABLE_ALL (1UL<<0) + #define MISC_COMMAND_DISABLE_ALL (1UL<<1) + #define MISC_COMMAND_SW_RESET (1UL<<4) + #define MISC_COMMAND_POR_RESET (1UL<<5) + #define MISC_COMMAND_HD_RESET (1UL<<6) + #define MISC_COMMAND_CMN_SW_RESET (1UL<<7) + #define MISC_COMMAND_PAR_ERROR (1UL<<8) + #define MISC_COMMAND_CS16_ERR (1UL<<9) + #define MISC_COMMAND_CS16_ERR_LOC (0xfUL<<12) + #define MISC_COMMAND_PAR_ERR_RAM (0x7fUL<<16) + #define MISC_COMMAND_POWERDOWN_EVENT (1UL<<23) + #define MISC_COMMAND_SW_SHUTDOWN (1UL<<24) + #define MISC_COMMAND_SHUTDOWN_EN (1UL<<25) + #define MISC_COMMAND_DINTEG_ATTN_EN (1UL<<26) + #define MISC_COMMAND_PCIE_LINK_IN_L23 (1UL<<27) + #define MISC_COMMAND_PCIE_DIS (1UL<<28) + + u32_t misc_cfg; + #define MISC_CFG_GRC_TMOUT (1UL<<0) + #define MISC_CFG_NVM_WR_EN (0x3UL<<1) + #define MISC_CFG_NVM_WR_EN_PROTECT (0UL<<1) + #define MISC_CFG_NVM_WR_EN_PCI (1UL<<1) + #define MISC_CFG_NVM_WR_EN_ALLOW (2UL<<1) + #define MISC_CFG_NVM_WR_EN_ALLOW2 (3UL<<1) + #define MISC_CFG_BIST_EN (1UL<<3) + #define MISC_CFG_CK25_OUT_ALT_SRC (1UL<<4) + #define MISC_CFG_RESERVED5_TE (1UL<<5) + #define MISC_CFG_RESERVED6_TE (1UL<<6) + #define MISC_CFG_CLK_CTL_OVERRIDE_TE (1UL<<7) + #define MISC_CFG_LEDMODE_TE (0x7UL<<8) + #define MISC_CFG_LEDMODE_MAC_TE (0UL<<8) + #define MISC_CFG_LEDMODE_PHY1_TE (1UL<<8) + #define MISC_CFG_LEDMODE_PHY2_TE (2UL<<8) + #define MISC_CFG_LEDMODE_PHY3_TE (3UL<<8) + #define MISC_CFG_LEDMODE_PHY4_TE (4UL<<8) + #define MISC_CFG_LEDMODE_PHY5_TE (5UL<<8) + #define MISC_CFG_LEDMODE_PHY6_TE (6UL<<8) + #define MISC_CFG_LEDMODE_PHY7_TE (7UL<<8) + #define MISC_CFG_MCP_GRC_TMOUT_TE (1UL<<11) + #define MISC_CFG_DBU_GRC_TMOUT_TE (1UL<<12) + #define MISC_CFG_LEDMODE_XI (0xfUL<<8) + #define MISC_CFG_LEDMODE_MAC_XI (0UL<<8) + #define MISC_CFG_LEDMODE_PHY1_XI (1UL<<8) + #define MISC_CFG_LEDMODE_PHY2_XI (2UL<<8) + #define MISC_CFG_LEDMODE_PHY3_XI (3UL<<8) + #define MISC_CFG_LEDMODE_MAC2_XI (4UL<<8) + #define MISC_CFG_LEDMODE_PHY4_XI (5UL<<8) + #define MISC_CFG_LEDMODE_PHY5_XI (6UL<<8) + #define MISC_CFG_LEDMODE_PHY6_XI (7UL<<8) + #define MISC_CFG_LEDMODE_MAC3_XI (8UL<<8) + #define MISC_CFG_LEDMODE_PHY7_XI (9UL<<8) + #define MISC_CFG_LEDMODE_PHY8_XI (10UL<<8) + #define MISC_CFG_LEDMODE_PHY9_XI (11UL<<8) + #define MISC_CFG_LEDMODE_MAC4_XI (12UL<<8) + #define MISC_CFG_LEDMODE_PHY10_XI (13UL<<8) + #define MISC_CFG_LEDMODE_PHY11_XI (14UL<<8) + #define MISC_CFG_LEDMODE_UNUSED_XI (15UL<<8) + #define MISC_CFG_PORT_SELECT_XI (1UL<<13) + #define MISC_CFG_PARITY_MODE_XI (1UL<<14) + + u32_t misc_id; + #define MISC_ID_BOND_ID (0xfUL<<0) + #define MISC_ID_BOND_ID_X (0UL<<0) + #define MISC_ID_BOND_ID_C (3UL<<0) + #define MISC_ID_BOND_ID_S (12UL<<0) + #define MISC_ID_CHIP_METAL (0xffUL<<4) + #define MISC_ID_CHIP_REV (0xfUL<<12) + #define MISC_ID_CHIP_NUM (0xffffUL<<16) + + u32_t misc_enable_status_bits; + #define MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1UL<<0) + #define MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1UL<<1) + #define MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1UL<<2) + #define MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1UL<<3) + #define MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1UL<<4) + #define MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1UL<<5) + #define MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1UL<<6) + #define MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1UL<<7) + #define MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1UL<<8) + #define MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1UL<<9) + #define MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1UL<<10) + #define MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1UL<<11) + #define MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1UL<<12) + #define MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1UL<<13) + #define MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1UL<<14) + #define MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1UL<<15) + #define MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1UL<<16) + #define MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1UL<<17) + #define MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1UL<<18) + #define MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1UL<<19) + #define MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1UL<<20) + #define MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1UL<<21) + #define MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1UL<<22) + #define MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1UL<<23) + #define MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1UL<<24) + #define MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1UL<<25) + #define MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1UL<<26) + #define MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1UL<<27) + #define MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE (1UL<<28) + #define MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE (0x7UL<<29) + + u32_t misc_enable_set_bits; + #define MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1UL<<0) + #define MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1UL<<1) + #define MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1UL<<2) + #define MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1UL<<3) + #define MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1UL<<4) + #define MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1UL<<5) + #define MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1UL<<6) + #define MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1UL<<7) + #define MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1UL<<8) + #define MISC_ENABLE_SET_BITS_EMAC_ENABLE (1UL<<9) + #define MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1UL<<10) + #define MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1UL<<11) + #define MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1UL<<12) + #define MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1UL<<13) + #define MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1UL<<14) + #define MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1UL<<15) + #define MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1UL<<16) + #define MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1UL<<17) + #define MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1UL<<18) + #define MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1UL<<19) + #define MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1UL<<20) + #define MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1UL<<21) + #define MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1UL<<22) + #define MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1UL<<23) + #define MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1UL<<24) + #define MISC_ENABLE_SET_BITS_TIMER_ENABLE (1UL<<25) + #define MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1UL<<26) + #define MISC_ENABLE_SET_BITS_UMP_ENABLE (1UL<<27) + #define MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE (1UL<<28) + #define MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE (0x7UL<<29) + + u32_t misc_enable_clr_bits; + #define MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1UL<<0) + #define MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1UL<<1) + #define MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1UL<<2) + #define MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1UL<<3) + #define MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1UL<<4) + #define MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1UL<<5) + #define MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1UL<<6) + #define MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1UL<<7) + #define MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1UL<<8) + #define MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1UL<<9) + #define MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1UL<<10) + #define MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1UL<<11) + #define MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1UL<<12) + #define MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1UL<<13) + #define MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1UL<<14) + #define MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1UL<<15) + #define MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1UL<<16) + #define MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1UL<<17) + #define MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1UL<<18) + #define MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1UL<<19) + #define MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1UL<<20) + #define MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1UL<<21) + #define MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1UL<<22) + #define MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1UL<<23) + #define MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1UL<<24) + #define MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1UL<<25) + #define MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1UL<<26) + #define MISC_ENABLE_CLR_BITS_UMP_ENABLE (1UL<<27) + #define MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE (1UL<<28) + #define MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE (0x7UL<<29) + + u32_t misc_clock_control_bits; + #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfUL<<0) + #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0UL<<0) + #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1UL<<0) + #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2UL<<0) + #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3UL<<0) + #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4UL<<0) + #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5UL<<0) + #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6UL<<0) + #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7UL<<0) + #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (15UL<<0) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1UL<<6) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1UL<<7) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_TE (0x7UL<<8) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF_TE (0UL<<8) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12_TE (1UL<<8) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6_TE (2UL<<8) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62_TE (4UL<<8) + #define MISC_CLOCK_CONTROL_BITS_RESERVED0_XI (0x7UL<<8) + #define MISC_CLOCK_CONTROL_BITS_MIN_POWER (1UL<<11) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_TE (0xfUL<<12) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100_TE (0UL<<12) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80_TE (1UL<<12) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50_TE (2UL<<12) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40_TE (4UL<<12) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25_TE (8UL<<12) + #define MISC_CLOCK_CONTROL_BITS_RESERVED1_XI (0xfUL<<12) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1UL<<16) + #define MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE (1UL<<17) + #define MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE (1UL<<18) + #define MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE (1UL<<19) + #define MISC_CLOCK_CONTROL_BITS_RESERVED_TE (0xfffUL<<20) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI (1UL<<17) + #define MISC_CLOCK_CONTROL_BITS_RESERVED2_XI (0x3fUL<<18) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI (0x7UL<<24) + #define MISC_CLOCK_CONTROL_BITS_RESERVED3_XI (1UL<<27) + #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI (0xfUL<<28) + + u32_t misc_spio; + #define MISC_SPIO_VALUE (0xffUL<<0) + #define MISC_SPIO_SET (0xffUL<<8) + #define MISC_SPIO_CLR (0xffUL<<16) + #define MISC_SPIO_FLOAT (0xffUL<<24) + + u32_t misc_spio_int; + #define MISC_SPIO_INT_INT_STATE_TE (0xfUL<<0) + #define MISC_SPIO_INT_OLD_VALUE_TE (0xfUL<<8) + #define MISC_SPIO_INT_OLD_SET_TE (0xfUL<<16) + #define MISC_SPIO_INT_OLD_CLR_TE (0xfUL<<24) + #define MISC_SPIO_INT_INT_STATE_XI (0xffUL<<0) + #define MISC_SPIO_INT_OLD_VALUE_XI (0xffUL<<8) + #define MISC_SPIO_INT_OLD_SET_XI (0xffUL<<16) + #define MISC_SPIO_INT_OLD_CLR_XI (0xffUL<<24) + + u32_t misc_config_lfsr; + #define MISC_CONFIG_LFSR_DIV (0xffffUL<<0) + + u32_t misc_lfsr_mask_bits; + #define MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1UL<<0) + #define MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1UL<<1) + #define MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1UL<<2) + #define MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1UL<<3) + #define MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1UL<<4) + #define MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1UL<<5) + #define MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1UL<<6) + #define MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1UL<<7) + #define MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1UL<<8) + #define MISC_LFSR_MASK_BITS_EMAC_ENABLE (1UL<<9) + #define MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1UL<<10) + #define MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1UL<<11) + #define MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1UL<<12) + #define MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1UL<<13) + #define MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1UL<<14) + #define MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1UL<<15) + #define MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1UL<<16) + #define MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1UL<<17) + #define MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1UL<<18) + #define MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1UL<<19) + #define MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1UL<<20) + #define MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1UL<<21) + #define MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1UL<<22) + #define MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1UL<<23) + #define MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1UL<<24) + #define MISC_LFSR_MASK_BITS_TIMER_ENABLE (1UL<<25) + #define MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1UL<<26) + #define MISC_LFSR_MASK_BITS_UMP_ENABLE (1UL<<27) + #define MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE (1UL<<28) + #define MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE (0x7UL<<29) + + u32_t misc_arb_req[5]; + u32_t misc_arb_free[5]; + u32_t misc_arb_req_status[5]; + u32_t misc_arb_gnt0; + #define MISC_ARB_GNT0_0 (0x7UL<<0) + #define MISC_ARB_GNT0_1 (0x7UL<<4) + #define MISC_ARB_GNT0_2 (0x7UL<<8) + #define MISC_ARB_GNT0_3 (0x7UL<<12) + #define MISC_ARB_GNT0_4 (0x7UL<<16) + #define MISC_ARB_GNT0_5 (0x7UL<<20) + #define MISC_ARB_GNT0_6 (0x7UL<<24) + #define MISC_ARB_GNT0_7 (0x7UL<<28) + + u32_t misc_arb_gnt1; + #define MISC_ARB_GNT1_8 (0x7UL<<0) + #define MISC_ARB_GNT1_9 (0x7UL<<4) + #define MISC_ARB_GNT1_10 (0x7UL<<8) + #define MISC_ARB_GNT1_11 (0x7UL<<12) + #define MISC_ARB_GNT1_12 (0x7UL<<16) + #define MISC_ARB_GNT1_13 (0x7UL<<20) + #define MISC_ARB_GNT1_14 (0x7UL<<24) + #define MISC_ARB_GNT1_15 (0x7UL<<28) + + u32_t misc_arb_gnt2; + #define MISC_ARB_GNT2_16 (0x7UL<<0) + #define MISC_ARB_GNT2_17 (0x7UL<<4) + #define MISC_ARB_GNT2_18 (0x7UL<<8) + #define MISC_ARB_GNT2_19 (0x7UL<<12) + #define MISC_ARB_GNT2_20 (0x7UL<<16) + #define MISC_ARB_GNT2_21 (0x7UL<<20) + #define MISC_ARB_GNT2_22 (0x7UL<<24) + #define MISC_ARB_GNT2_23 (0x7UL<<28) + + u32_t misc_arb_gnt3; + #define MISC_ARB_GNT3_24 (0x7UL<<0) + #define MISC_ARB_GNT3_25 (0x7UL<<4) + #define MISC_ARB_GNT3_26 (0x7UL<<8) + #define MISC_ARB_GNT3_27 (0x7UL<<12) + #define MISC_ARB_GNT3_28 (0x7UL<<16) + #define MISC_ARB_GNT3_29 (0x7UL<<20) + #define MISC_ARB_GNT3_30 (0x7UL<<24) + #define MISC_ARB_GNT3_31 (0x7UL<<28) + + u32_t misc_reserved1; + #define MISC_RESERVED1_MISC_RESERVED1_VALUE (0x3fUL<<0) + + u32_t misc_reserved2; + #define MISC_RESERVED2_PCIE_DIS (1UL<<0) + #define MISC_RESERVED2_LINK_IN_L23 (1UL<<1) + + u32_t misc_sm_asf_control; + #define MISC_SM_ASF_CONTROL_ASF_RST (1UL<<0) + #define MISC_SM_ASF_CONTROL_TSC_EN (1UL<<1) + #define MISC_SM_ASF_CONTROL_WG_TO (1UL<<2) + #define MISC_SM_ASF_CONTROL_HB_TO (1UL<<3) + #define MISC_SM_ASF_CONTROL_PA_TO (1UL<<4) + #define MISC_SM_ASF_CONTROL_PL_TO (1UL<<5) + #define MISC_SM_ASF_CONTROL_RT_TO (1UL<<6) + #define MISC_SM_ASF_CONTROL_SMB_EVENT (1UL<<7) + #define MISC_SM_ASF_CONTROL_STRETCH_EN (1UL<<8) + #define MISC_SM_ASF_CONTROL_STRETCH_PULSE (1UL<<9) + #define MISC_SM_ASF_CONTROL_RES (0x3UL<<10) + #define MISC_SM_ASF_CONTROL_SMB_EN (1UL<<12) + #define MISC_SM_ASF_CONTROL_SMB_BB_EN (1UL<<13) + #define MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1UL<<14) + #define MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1UL<<15) + #define MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fUL<<16) + #define MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fUL<<23) + #define MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1UL<<30) + #define MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1UL<<31) + + u32_t misc_smb_in; + #define MISC_SMB_IN_DAT_IN (0xffUL<<0) + #define MISC_SMB_IN_RDY (1UL<<8) + #define MISC_SMB_IN_DONE (1UL<<9) + #define MISC_SMB_IN_FIRSTBYTE (1UL<<10) + #define MISC_SMB_IN_STATUS (0x7UL<<11) + #define MISC_SMB_IN_STATUS_OK (0UL<<11) + #define MISC_SMB_IN_STATUS_PEC (1UL<<11) + #define MISC_SMB_IN_STATUS_OFLOW (2UL<<11) + #define MISC_SMB_IN_STATUS_STOP (3UL<<11) + #define MISC_SMB_IN_STATUS_TIMEOUT (4UL<<11) + + u32_t misc_smb_out; + #define MISC_SMB_OUT_DAT_OUT (0xffUL<<0) + #define MISC_SMB_OUT_RDY (1UL<<8) + #define MISC_SMB_OUT_START (1UL<<9) + #define MISC_SMB_OUT_LAST (1UL<<10) + #define MISC_SMB_OUT_ACC_TYPE (1UL<<11) + #define MISC_SMB_OUT_ENB_PEC (1UL<<12) + #define MISC_SMB_OUT_GET_RX_LEN (1UL<<13) + #define MISC_SMB_OUT_SMB_READ_LEN (0x3fUL<<14) + #define MISC_SMB_OUT_SMB_OUT_STATUS (0xfUL<<20) + #define MISC_SMB_OUT_SMB_OUT_STATUS_OK (0UL<<20) + #define MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1UL<<20) + #define MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2UL<<20) + #define MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3UL<<20) + #define MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4UL<<20) + #define MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5UL<<20) + #define MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (6UL<<20) + #define MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9UL<<20) + #define MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (13UL<<20) + #define MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1UL<<24) + #define MISC_SMB_OUT_SMB_OUT_DAT_EN (1UL<<25) + #define MISC_SMB_OUT_SMB_OUT_DAT_IN (1UL<<26) + #define MISC_SMB_OUT_SMB_OUT_CLK_EN (1UL<<27) + #define MISC_SMB_OUT_SMB_OUT_CLK_IN (1UL<<28) + + u32_t misc_smb_watchdog; + #define MISC_SMB_WATCHDOG_WATCHDOG (0xffffUL<<0) + + u32_t misc_smb_heartbeat; + #define MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffUL<<0) + + u32_t misc_smb_poll_asf; + #define MISC_SMB_POLL_ASF_POLL_ASF (0xffffUL<<0) + + u32_t misc_smb_poll_legacy; + #define MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffUL<<0) + + u32_t misc_smb_retran; + #define MISC_SMB_RETRAN_RETRAN (0xffUL<<0) + + u32_t misc_smb_timestamp; + #define MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffUL<<0) + + u32_t misc_perr_ena0; + #define MISC_PERR_ENA0_COM_MISC_CTXC_TE (1UL<<0) + #define MISC_PERR_ENA0_COM_MISC_REGF_TE (1UL<<1) + #define MISC_PERR_ENA0_COM_MISC_SCPAD_TE (1UL<<2) + #define MISC_PERR_ENA0_CP_MISC_CTXC_TE (1UL<<3) + #define MISC_PERR_ENA0_CP_MISC_REGF_TE (1UL<<4) + #define MISC_PERR_ENA0_CP_MISC_SCPAD_TE (1UL<<5) + #define MISC_PERR_ENA0_CS_MISC_TMEM_TE (1UL<<6) + #define MISC_PERR_ENA0_CTX_MISC_ACCM0_TE (1UL<<7) + #define MISC_PERR_ENA0_CTX_MISC_ACCM1_TE (1UL<<8) + #define MISC_PERR_ENA0_CTX_MISC_ACCM2_TE (1UL<<9) + #define MISC_PERR_ENA0_CTX_MISC_ACCM3_TE (1UL<<10) + #define MISC_PERR_ENA0_CTX_MISC_ACCM4_TE (1UL<<11) + #define MISC_PERR_ENA0_CTX_MISC_ACCM5_TE (1UL<<12) + #define MISC_PERR_ENA0_CTX_MISC_PGTBL_TE (1UL<<13) + #define MISC_PERR_ENA0_DMAE_MISC_DR0_TE (1UL<<14) + #define MISC_PERR_ENA0_DMAE_MISC_DR1_TE (1UL<<15) + #define MISC_PERR_ENA0_DMAE_MISC_DR2_TE (1UL<<16) + #define MISC_PERR_ENA0_DMAE_MISC_DR3_TE (1UL<<17) + #define MISC_PERR_ENA0_DMAE_MISC_DR4_TE (1UL<<18) + #define MISC_PERR_ENA0_DMAE_MISC_DW0_TE (1UL<<19) + #define MISC_PERR_ENA0_DMAE_MISC_DW1_TE (1UL<<20) + #define MISC_PERR_ENA0_DMAE_MISC_DW2_TE (1UL<<21) + #define MISC_PERR_ENA0_HC_MISC_DMA_TE (1UL<<22) + #define MISC_PERR_ENA0_MCP_MISC_REGF_TE (1UL<<23) + #define MISC_PERR_ENA0_MCP_MISC_SCPAD_TE (1UL<<24) + #define MISC_PERR_ENA0_MQ_MISC_CTX_TE (1UL<<25) + #define MISC_PERR_ENA0_RBDC_MISC_TE (1UL<<26) + #define MISC_PERR_ENA0_RBUF_MISC_MB_TE (1UL<<27) + #define MISC_PERR_ENA0_RBUF_MISC_PTR_TE (1UL<<28) + #define MISC_PERR_ENA0_RDE_MISC_RPC_TE (1UL<<29) + #define MISC_PERR_ENA0_RDE_MISC_RPM_TE (1UL<<30) + #define MISC_PERR_ENA0_RV2P_MISC_CB0REGS_TE (1UL<<31) + #define MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI (1UL<<0) + #define MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI (1UL<<1) + #define MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI (1UL<<2) + #define MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI (1UL<<3) + #define MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI (1UL<<4) + #define MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI (1UL<<5) + #define MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI (1UL<<6) + #define MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI (1UL<<7) + #define MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI (1UL<<8) + #define MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI (1UL<<9) + #define MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI (1UL<<10) + #define MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI (1UL<<11) + #define MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI (1UL<<12) + #define MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI (1UL<<13) + #define MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI (1UL<<14) + #define MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI (1UL<<15) + #define MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI (1UL<<16) + #define MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI (1UL<<17) + #define MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI (1UL<<18) + #define MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI (1UL<<19) + #define MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI (1UL<<20) + #define MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI (1UL<<21) + #define MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI (1UL<<22) + #define MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI (1UL<<23) + #define MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI (1UL<<24) + #define MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI (1UL<<25) + #define MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI (1UL<<26) + #define MISC_PERR_ENA0_TPBUF_PERR_EN_XI (1UL<<27) + #define MISC_PERR_ENA0_THBUF_PERR_EN_XI (1UL<<28) + #define MISC_PERR_ENA0_TDMA_PERR_EN_XI (1UL<<29) + #define MISC_PERR_ENA0_TBDC_PERR_EN_XI (1UL<<30) + #define MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI (1UL<<31) + + u32_t misc_perr_ena1; + #define MISC_PERR_ENA1_RV2P_MISC_CB1REGS_TE (1UL<<0) + #define MISC_PERR_ENA1_RV2P_MISC_P1IRAM_TE (1UL<<1) + #define MISC_PERR_ENA1_RV2P_MISC_P2IRAM_TE (1UL<<2) + #define MISC_PERR_ENA1_RXP_MISC_CTXC_TE (1UL<<3) + #define MISC_PERR_ENA1_RXP_MISC_REGF_TE (1UL<<4) + #define MISC_PERR_ENA1_RXP_MISC_SCPAD_TE (1UL<<5) + #define MISC_PERR_ENA1_RXP_MISC_RBUFC_TE (1UL<<6) + #define MISC_PERR_ENA1_TBDC_MISC_TE (1UL<<7) + #define MISC_PERR_ENA1_TDMA_MISC_TE (1UL<<8) + #define MISC_PERR_ENA1_THBUF_MISC_MB0_TE (1UL<<9) + #define MISC_PERR_ENA1_THBUF_MISC_MB1_TE (1UL<<10) + #define MISC_PERR_ENA1_TPAT_MISC_REGF_TE (1UL<<11) + #define MISC_PERR_ENA1_TPAT_MISC_SCPAD_TE (1UL<<12) + #define MISC_PERR_ENA1_TPBUF_MISC_MB_TE (1UL<<13) + #define MISC_PERR_ENA1_TSCH_MISC_LR_TE (1UL<<14) + #define MISC_PERR_ENA1_TXP_MISC_CTXC_TE (1UL<<15) + #define MISC_PERR_ENA1_TXP_MISC_REGF_TE (1UL<<16) + #define MISC_PERR_ENA1_TXP_MISC_SCPAD_TE (1UL<<17) + #define MISC_PERR_ENA1_UMP_MISC_FIORX_TE (1UL<<18) + #define MISC_PERR_ENA1_UMP_MISC_FIOTX_TE (1UL<<19) + #define MISC_PERR_ENA1_UMP_MISC_RX_TE (1UL<<20) + #define MISC_PERR_ENA1_UMP_MISC_TX_TE (1UL<<21) + #define MISC_PERR_ENA1_RDMAQ_MISC_TE (1UL<<22) + #define MISC_PERR_ENA1_CSQ_MISC_TE (1UL<<23) + #define MISC_PERR_ENA1_CPQ_MISC_TE (1UL<<24) + #define MISC_PERR_ENA1_MCPQ_MISC_TE (1UL<<25) + #define MISC_PERR_ENA1_RV2PMQ_MISC_TE (1UL<<26) + #define MISC_PERR_ENA1_RV2PPQ_MISC_TE (1UL<<27) + #define MISC_PERR_ENA1_RV2PTQ_MISC_TE (1UL<<28) + #define MISC_PERR_ENA1_RXPQ_MISC_TE (1UL<<29) + #define MISC_PERR_ENA1_RXPCQ_MISC_TE (1UL<<30) + #define MISC_PERR_ENA1_RLUPQ_MISC_TE (1UL<<31) + #define MISC_PERR_ENA1_RBDC_PERR_EN_XI (1UL<<0) + #define MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI (1UL<<2) + #define MISC_PERR_ENA1_HC_STATS_PERR_EN_XI (1UL<<3) + #define MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI (1UL<<4) + #define MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI (1UL<<5) + #define MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI (1UL<<6) + #define MISC_PERR_ENA1_TPATQ_PERR_EN_XI (1UL<<7) + #define MISC_PERR_ENA1_MCPQ_PERR_EN_XI (1UL<<8) + #define MISC_PERR_ENA1_TDMAQ_PERR_EN_XI (1UL<<9) + #define MISC_PERR_ENA1_TXPQ_PERR_EN_XI (1UL<<10) + #define MISC_PERR_ENA1_COMTQ_PERR_EN_XI (1UL<<11) + #define MISC_PERR_ENA1_COMQ_PERR_EN_XI (1UL<<12) + #define MISC_PERR_ENA1_RLUPQ_PERR_EN_XI (1UL<<13) + #define MISC_PERR_ENA1_RXPQ_PERR_EN_XI (1UL<<14) + #define MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI (1UL<<15) + #define MISC_PERR_ENA1_RDMAQ_PERR_EN_XI (1UL<<16) + #define MISC_PERR_ENA1_TASQ_PERR_EN_XI (1UL<<17) + #define MISC_PERR_ENA1_TBDRQ_PERR_EN_XI (1UL<<18) + #define MISC_PERR_ENA1_TSCHQ_PERR_EN_XI (1UL<<19) + #define MISC_PERR_ENA1_COMXQ_PERR_EN_XI (1UL<<20) + #define MISC_PERR_ENA1_RXPCQ_PERR_EN_XI (1UL<<21) + #define MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI (1UL<<22) + #define MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI (1UL<<23) + #define MISC_PERR_ENA1_CPQ_PERR_EN_XI (1UL<<24) + #define MISC_PERR_ENA1_CSQ_PERR_EN_XI (1UL<<25) + #define MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI (1UL<<26) + #define MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI (1UL<<27) + #define MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI (1UL<<28) + #define MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI (1UL<<29) + + u32_t misc_perr_ena2; + #define MISC_PERR_ENA2_COMQ_MISC_TE (1UL<<0) + #define MISC_PERR_ENA2_COMXQ_MISC_TE (1UL<<1) + #define MISC_PERR_ENA2_COMTQ_MISC_TE (1UL<<2) + #define MISC_PERR_ENA2_TSCHQ_MISC_TE (1UL<<3) + #define MISC_PERR_ENA2_TBDRQ_MISC_TE (1UL<<4) + #define MISC_PERR_ENA2_TXPQ_MISC_TE (1UL<<5) + #define MISC_PERR_ENA2_TDMAQ_MISC_TE (1UL<<6) + #define MISC_PERR_ENA2_TPATQ_MISC_TE (1UL<<7) + #define MISC_PERR_ENA2_TASQ_MISC_TE (1UL<<8) + #define MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI (1UL<<0) + #define MISC_PERR_ENA2_UMP_TX_PERR_EN_XI (1UL<<1) + #define MISC_PERR_ENA2_UMP_RX_PERR_EN_XI (1UL<<2) + #define MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI (1UL<<3) + #define MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI (1UL<<4) + #define MISC_PERR_ENA2_HB_MEM_PERR_EN_XI (1UL<<5) + #define MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI (1UL<<6) + + u32_t misc_debug_vector_sel; + #define MISC_DEBUG_VECTOR_SEL_0 (0xfffUL<<0) + #define MISC_DEBUG_VECTOR_SEL_1_TE (0xfffUL<<12) + #define MISC_DEBUG_VECTOR_SEL_1_XI (0xfffUL<<15) + + u32_t misc_vreg_control; + #define MISC_VREG_CONTROL_1_2_TE (0xfUL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_XI (0xfUL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0UL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI (1UL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI (2UL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI (3UL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI (4UL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI (5UL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI (6UL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_NOM_XI (7UL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI (8UL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI (9UL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI (10UL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI (11UL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI (12UL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI (13UL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI (14UL<<0) + #define MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI (15UL<<0) + #define MISC_VREG_CONTROL_2_5 (0xfUL<<4) + #define MISC_VREG_CONTROL_2_5_PLUS14 (0UL<<4) + #define MISC_VREG_CONTROL_2_5_PLUS12 (1UL<<4) + #define MISC_VREG_CONTROL_2_5_PLUS10 (2UL<<4) + #define MISC_VREG_CONTROL_2_5_PLUS8 (3UL<<4) + #define MISC_VREG_CONTROL_2_5_PLUS6 (4UL<<4) + #define MISC_VREG_CONTROL_2_5_PLUS4 (5UL<<4) + #define MISC_VREG_CONTROL_2_5_PLUS2 (6UL<<4) + #define MISC_VREG_CONTROL_2_5_NOM (7UL<<4) + #define MISC_VREG_CONTROL_2_5_MINUS2 (8UL<<4) + #define MISC_VREG_CONTROL_2_5_MINUS4 (9UL<<4) + #define MISC_VREG_CONTROL_2_5_MINUS6 (10UL<<4) + #define MISC_VREG_CONTROL_2_5_MINUS8 (11UL<<4) + #define MISC_VREG_CONTROL_2_5_MINUS10 (12UL<<4) + #define MISC_VREG_CONTROL_2_5_MINUS12 (13UL<<4) + #define MISC_VREG_CONTROL_2_5_MINUS14 (14UL<<4) + #define MISC_VREG_CONTROL_2_5_MINUS16 (15UL<<4) + #define MISC_VREG_CONTROL_1_0_MGMT (0xfUL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0UL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_PLUS12 (1UL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_PLUS10 (2UL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_PLUS8 (3UL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_PLUS6 (4UL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_PLUS4 (5UL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_PLUS2 (6UL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_NOM (7UL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_MINUS2 (8UL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_MINUS4 (9UL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_MINUS6 (10UL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_MINUS8 (11UL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_MINUS10 (12UL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_MINUS12 (13UL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_MINUS14 (14UL<<8) + #define MISC_VREG_CONTROL_1_0_MGMT_MINUS16 (15UL<<8) + + u32_t misc_final_clk_ctl_val; + #define MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffUL<<6) + + u32_t misc_gp_hw_ctl0; + #define MISC_GP_HW_CTL0_TX_DRIVE (1UL<<0) + #define MISC_GP_HW_CTL0_RMII_MODE (1UL<<1) + #define MISC_GP_HW_CTL0_RMII_CRSDV_SEL (1UL<<2) + #define MISC_GP_HW_CTL0_RVMII_MODE (1UL<<3) + #define MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE (1UL<<4) + #define MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE (1UL<<5) + #define MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE (1UL<<6) + #define MISC_GP_HW_CTL0_RESERVED1_XI (0x7UL<<4) + #define MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY (1UL<<7) + #define MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE (1UL<<8) + #define MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE (1UL<<9) + #define MISC_GP_HW_CTL0_LED_ACT_SEL_TE (1UL<<10) + #define MISC_GP_HW_CTL0_RESERVED2_XI (0x7UL<<8) + #define MISC_GP_HW_CTL0_UP1_DEF0 (1UL<<11) + #define MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF (1UL<<12) + #define MISC_GP_HW_CTL0_FORCE2500_DEF (1UL<<13) + #define MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF (1UL<<14) + #define MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF (1UL<<15) + #define MISC_GP_HW_CTL0_OSCCTRL_DAI (0xfUL<<16) + #define MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA (0UL<<16) + #define MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA (1UL<<16) + #define MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA (3UL<<16) + #define MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA (5UL<<16) + #define MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA (7UL<<16) + #define MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN (15UL<<16) + #define MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS (1UL<<20) + #define MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS (1UL<<21) + #define MISC_GP_HW_CTL0_OSCCTRL_CTAT (0x3UL<<22) + #define MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P (0UL<<22) + #define MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P (1UL<<22) + #define MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P (2UL<<22) + #define MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P (3UL<<22) + #define MISC_GP_HW_CTL0_OSCCTRL_PTAT (0x3UL<<24) + #define MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P (0UL<<24) + #define MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P (1UL<<24) + #define MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P (2UL<<24) + #define MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P (3UL<<24) + #define MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ (0x3UL<<26) + #define MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA (0UL<<26) + #define MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA (1UL<<26) + #define MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA (2UL<<26) + #define MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA (3UL<<26) + #define MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ (0x3UL<<28) + #define MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA (0UL<<28) + #define MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA (1UL<<28) + #define MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA (2UL<<28) + #define MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA (3UL<<28) + #define MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ (0x3UL<<30) + #define MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 (0UL<<30) + #define MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45 (1UL<<30) + #define MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62 (2UL<<30) + #define MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66 (3UL<<30) + + u32_t misc_gp_hw_ctl1; + #define MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE (1UL<<0) + #define MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE (1UL<<1) + #define MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE (1UL<<2) + #define MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE (1UL<<3) + #define MISC_GP_HW_CTL1_RESERVED_SOFT_XI (0xffffUL<<0) + #define MISC_GP_HW_CTL1_RESERVED_HARD_XI (0xffffUL<<16) + + u32_t misc_new_hw_ctl; + #define MISC_NEW_HW_CTL_MAIN_POR_BYPASS (1UL<<0) + #define MISC_NEW_HW_CTL_RINGOSC_ENABLE (1UL<<1) + #define MISC_NEW_HW_CTL_RINGOSC_SEL0 (1UL<<2) + #define MISC_NEW_HW_CTL_RINGOSC_SEL1 (1UL<<3) + #define MISC_NEW_HW_CTL_RINGOSC_TAP (0x7UL<<4) + #define MISC_NEW_HW_CTL_SMBUS_FILT_EN (1UL<<7) + #define MISC_NEW_HW_CTL_LED_PHY_SERDES_MODE_0 (1UL<<8) + #define MISC_NEW_HW_CTL_LED_PHY_SERDES_MODE_1 (1UL<<9) + #define MISC_NEW_HW_CTL_SWAP_LED (1UL<<10) + #define MISC_NEW_HW_CTL_SWAP_GPIO (1UL<<11) + #define MISC_NEW_HW_CTL_RESERVED_SHARED (0xfUL<<12) + #define MISC_NEW_HW_CTL_RESERVED_SPLIT (0xffffUL<<16) + + u32_t misc_new_core_ctl; + #define MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1UL<<0) + #define MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1UL<<1) + #define MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffUL<<2) + #define MISC_NEW_CORE_CTL_DMA_ENABLE (1UL<<16) + #define MISC_NEW_CORE_CTL_RESERVED_TC (0x7fffUL<<17) + + u32_t misc_eco_hw_ctl; + #define MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN (1UL<<0) + #define MISC_ECO_HW_CTL_RESERVED_SOFT (0x7fffUL<<1) + #define MISC_ECO_HW_CTL_RESERVED_HARD (0xffffUL<<16) + + u32_t misc_eco_core_ctl; + #define MISC_ECO_CORE_CTL_GLOBAL_REG_ATTN_0 (1UL<<0) + #define MISC_ECO_CORE_CTL_GLOBAL_REG_ATTN_1 (1UL<<1) + #define MISC_ECO_CORE_CTL_RESERVED_SOFT (0xffffUL<<0) + #define MISC_ECO_CORE_CTL_RESERVED_HARD (0xffffUL<<16) + + u32_t misc_ppio; + #define MISC_PPIO_VALUE (0xfUL<<0) + #define MISC_PPIO_SET (0xfUL<<8) + #define MISC_PPIO_CLR (0xfUL<<16) + #define MISC_PPIO_FLOAT (0xfUL<<24) + + u32_t misc_ppio_int; + #define MISC_PPIO_INT_INT_STATE (0xfUL<<0) + #define MISC_PPIO_INT_OLD_VALUE (0xfUL<<8) + #define MISC_PPIO_INT_OLD_SET (0xfUL<<16) + #define MISC_PPIO_INT_OLD_CLR (0xfUL<<24) + + u32_t misc_reset_nums; + #define MISC_RESET_NUMS_NUM_HARD_RESETS (0x7UL<<0) + #define MISC_RESET_NUMS_NUM_PCIE_RESETS (0x7UL<<4) + #define MISC_RESET_NUMS_NUM_PERSTB_RESETS (0x7UL<<8) + #define MISC_RESET_NUMS_NUM_CMN_RESETS (0x7UL<<12) + #define MISC_RESET_NUMS_NUM_PORT_RESETS (0x7UL<<16) + + u32_t misc_cs16_err; + #define MISC_CS16_ERR_ENA_PCI (1UL<<0) + #define MISC_CS16_ERR_ENA_RDMA (1UL<<1) + #define MISC_CS16_ERR_ENA_TDMA (1UL<<2) + #define MISC_CS16_ERR_ENA_EMAC (1UL<<3) + #define MISC_CS16_ERR_ENA_CTX (1UL<<4) + #define MISC_CS16_ERR_ENA_TBDR (1UL<<5) + #define MISC_CS16_ERR_ENA_RBDC (1UL<<6) + #define MISC_CS16_ERR_ENA_COM (1UL<<7) + #define MISC_CS16_ERR_ENA_CP (1UL<<8) + #define MISC_CS16_ERR_STA_PCI (1UL<<16) + #define MISC_CS16_ERR_STA_RDMA (1UL<<17) + #define MISC_CS16_ERR_STA_TDMA (1UL<<18) + #define MISC_CS16_ERR_STA_EMAC (1UL<<19) + #define MISC_CS16_ERR_STA_CTX (1UL<<20) + #define MISC_CS16_ERR_STA_TBDR (1UL<<21) + #define MISC_CS16_ERR_STA_RBDC (1UL<<22) + #define MISC_CS16_ERR_STA_COM (1UL<<23) + #define MISC_CS16_ERR_STA_CP (1UL<<24) + + u32_t misc_spio_event; + #define MISC_SPIO_EVENT_ENABLE (0xffUL<<0) + + u32_t misc_ppio_event; + #define MISC_PPIO_EVENT_ENABLE (0xfUL<<0) + + u32_t misc_dual_media_ctrl; + #define MISC_DUAL_MEDIA_CTRL_BOND_ID (0xffUL<<0) + #define MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0UL<<0) + #define MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3UL<<0) + #define MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12UL<<0) + #define MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP (0x7UL<<8) + #define MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN (1UL<<11) + #define MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET (1UL<<12) + #define MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET (1UL<<13) + #define MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET (1UL<<14) + #define MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET (1UL<<15) + #define MISC_DUAL_MEDIA_CTRL_LCPLL_RST (1UL<<16) + #define MISC_DUAL_MEDIA_CTRL_SERDES1_RST (1UL<<17) + #define MISC_DUAL_MEDIA_CTRL_SERDES0_RST (1UL<<18) + #define MISC_DUAL_MEDIA_CTRL_PHY1_RST (1UL<<19) + #define MISC_DUAL_MEDIA_CTRL_PHY0_RST (1UL<<20) + #define MISC_DUAL_MEDIA_CTRL_PHY_CTRL (0x7UL<<21) + #define MISC_DUAL_MEDIA_CTRL_PORT_SWAP (1UL<<24) + #define MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE (1UL<<25) + #define MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ (0xfUL<<26) + #define MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ (1UL<<26) + #define MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ (2UL<<26) + #define MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ (4UL<<26) + #define MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ (8UL<<26) + + u32_t misc_otp_cmd1; + #define MISC_OTP_CMD1_FMODE (0x7UL<<0) + #define MISC_OTP_CMD1_FMODE_IDLE (0UL<<0) + #define MISC_OTP_CMD1_FMODE_WRITE (1UL<<0) + #define MISC_OTP_CMD1_FMODE_INIT (2UL<<0) + #define MISC_OTP_CMD1_FMODE_SET (3UL<<0) + #define MISC_OTP_CMD1_FMODE_RST (4UL<<0) + #define MISC_OTP_CMD1_FMODE_VERIFY (5UL<<0) + #define MISC_OTP_CMD1_FMODE_RESERVED0 (6UL<<0) + #define MISC_OTP_CMD1_FMODE_RESERVED1 (7UL<<0) + #define MISC_OTP_CMD1_USEPINS (1UL<<8) + #define MISC_OTP_CMD1_PROGSEL (1UL<<9) + #define MISC_OTP_CMD1_PROGSTART (1UL<<10) + #define MISC_OTP_CMD1_PCOUNT (0x7UL<<16) + #define MISC_OTP_CMD1_PBYP (1UL<<19) + #define MISC_OTP_CMD1_VSEL (0xfUL<<20) + #define MISC_OTP_CMD1_TM (0x7UL<<27) + #define MISC_OTP_CMD1_SADBYP (1UL<<30) + #define MISC_OTP_CMD1_DEBUG (1UL<<31) + + u32_t misc_otp_cmd2; + #define MISC_OTP_CMD2_OTP_ROM_ADDR (0x3ffUL<<0) + #define MISC_OTP_CMD2_DOSEL (0x7fUL<<16) + #define MISC_OTP_CMD2_DOSEL_0 (0UL<<16) + #define MISC_OTP_CMD2_DOSEL_1 (1UL<<16) + #define MISC_OTP_CMD2_DOSEL_127 (127UL<<16) + + u32_t misc_otp_status; + #define MISC_OTP_STATUS_DATA (0xffUL<<0) + #define MISC_OTP_STATUS_VALID (1UL<<8) + #define MISC_OTP_STATUS_BUSY (1UL<<9) + #define MISC_OTP_STATUS_BUSYSM (1UL<<10) + #define MISC_OTP_STATUS_DONE (1UL<<11) + + u32_t misc_otp_shift1_cmd; + #define MISC_OTP_SHIFT1_CMD_RESET_MODE_N (1UL<<0) + #define MISC_OTP_SHIFT1_CMD_SHIFT_DONE (1UL<<1) + #define MISC_OTP_SHIFT1_CMD_SHIFT_START (1UL<<2) + #define MISC_OTP_SHIFT1_CMD_LOAD_DATA (1UL<<3) + #define MISC_OTP_SHIFT1_CMD_SHIFT_SELECT (0x1fUL<<8) + + u32_t misc_otp_shift1_data; + u32_t misc_otp_shift2_cmd; + #define MISC_OTP_SHIFT2_CMD_RESET_MODE_N (1UL<<0) + #define MISC_OTP_SHIFT2_CMD_SHIFT_DONE (1UL<<1) + #define MISC_OTP_SHIFT2_CMD_SHIFT_START (1UL<<2) + #define MISC_OTP_SHIFT2_CMD_LOAD_DATA (1UL<<3) + #define MISC_OTP_SHIFT2_CMD_SHIFT_SELECT (0x1fUL<<8) + + u32_t misc_otp_shift2_data; + u32_t misc_bist_cs0; + #define MISC_BIST_CS0_MBIST_EN (1UL<<0) + #define MISC_BIST_CS0_BIST_SETUP (0x3UL<<1) + #define MISC_BIST_CS0_MBIST_ASYNC_RESET (1UL<<3) + #define MISC_BIST_CS0_MBIST_DONE (1UL<<8) + #define MISC_BIST_CS0_MBIST_GO (1UL<<9) + #define MISC_BIST_CS0_BIST_OVERRIDE (1UL<<31) + + u32_t misc_bist_memstatus0; + u32_t misc_bist_cs1; + #define MISC_BIST_CS1_MBIST_EN (1UL<<0) + #define MISC_BIST_CS1_BIST_SETUP (0x3UL<<1) + #define MISC_BIST_CS1_MBIST_ASYNC_RESET (1UL<<3) + #define MISC_BIST_CS1_MBIST_DONE (1UL<<8) + #define MISC_BIST_CS1_MBIST_GO (1UL<<9) + + u32_t misc_bist_memstatus1; + u32_t misc_bist_cs2; + #define MISC_BIST_CS2_MBIST_EN (1UL<<0) + #define MISC_BIST_CS2_BIST_SETUP (0x3UL<<1) + #define MISC_BIST_CS2_MBIST_ASYNC_RESET (1UL<<3) + #define MISC_BIST_CS2_MBIST_DONE (1UL<<8) + #define MISC_BIST_CS2_MBIST_GO (1UL<<9) + + u32_t misc_bist_memstatus2; + u32_t misc_bist_cs3; + #define MISC_BIST_CS3_MBIST_EN (1UL<<0) + #define MISC_BIST_CS3_BIST_SETUP (0x3UL<<1) + #define MISC_BIST_CS3_MBIST_ASYNC_RESET (1UL<<3) + #define MISC_BIST_CS3_MBIST_DONE (1UL<<8) + #define MISC_BIST_CS3_MBIST_GO (1UL<<9) + + u32_t misc_bist_memstatus3; + u32_t misc_bist_cs4; + #define MISC_BIST_CS4_MBIST_EN (1UL<<0) + #define MISC_BIST_CS4_BIST_SETUP (0x3UL<<1) + #define MISC_BIST_CS4_MBIST_ASYNC_RESET (1UL<<3) + #define MISC_BIST_CS4_MBIST_DONE (1UL<<8) + #define MISC_BIST_CS4_MBIST_GO (1UL<<9) + + u32_t misc_bist_memstatus4; + u32_t misc_bist_cs5; + #define MISC_BIST_CS5_MBIST_EN (1UL<<0) + #define MISC_BIST_CS5_BIST_SETUP (0x3UL<<1) + #define MISC_BIST_CS5_MBIST_ASYNC_RESET (1UL<<3) + #define MISC_BIST_CS5_MBIST_DONE (1UL<<8) + #define MISC_BIST_CS5_MBIST_GO (1UL<<9) + + u32_t misc_bist_memstatus5; + u32_t misc_mem_tm0; + #define MISC_MEM_TM0_PCIE_REPLAY_TM (0xfUL<<0) + #define MISC_MEM_TM0_MCP_SCPAD (0xfUL<<8) + #define MISC_MEM_TM0_UMP_TM (0xffUL<<16) + #define MISC_MEM_TM0_HB_MEM_TM (0xfUL<<24) + + u32_t misc_uspll_ctrl; + #define MISC_USPLL_CTRL_PH_DET_DIS (1UL<<0) + #define MISC_USPLL_CTRL_FREQ_DET_DIS (1UL<<1) + #define MISC_USPLL_CTRL_LCPX (0x3fUL<<2) + #define MISC_USPLL_CTRL_RX (0x3UL<<8) + #define MISC_USPLL_CTRL_VC_EN (1UL<<10) + #define MISC_USPLL_CTRL_VCO_MG (0x3UL<<11) + #define MISC_USPLL_CTRL_KVCO_XF (0x7UL<<13) + #define MISC_USPLL_CTRL_KVCO_XS (0x7UL<<16) + #define MISC_USPLL_CTRL_TESTD_EN (1UL<<19) + #define MISC_USPLL_CTRL_TESTD_SEL (0x7UL<<20) + #define MISC_USPLL_CTRL_TESTA_EN (1UL<<23) + #define MISC_USPLL_CTRL_TESTA_SEL (0x3UL<<24) + #define MISC_USPLL_CTRL_ATTEN_FREF (1UL<<26) + #define MISC_USPLL_CTRL_DIGITAL_RST (1UL<<27) + #define MISC_USPLL_CTRL_ANALOG_RST (1UL<<28) + #define MISC_USPLL_CTRL_LOCK (1UL<<29) + + u32_t misc_perr_status0; + #define MISC_PERR_STATUS0_COM_DMAE_PERR (1UL<<0) + #define MISC_PERR_STATUS0_CP_DMAE_PERR (1UL<<1) + #define MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR (1UL<<2) + #define MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR (1UL<<3) + #define MISC_PERR_STATUS0_CTX_PGTBL_PERR (1UL<<4) + #define MISC_PERR_STATUS0_CTX_CACHE_PERR (1UL<<5) + #define MISC_PERR_STATUS0_CTX_MIRROR_PERR (1UL<<6) + #define MISC_PERR_STATUS0_COM_CTXC_PERR (1UL<<7) + #define MISC_PERR_STATUS0_COM_SCPAD_PERR (1UL<<8) + #define MISC_PERR_STATUS0_CP_CTXC_PERR (1UL<<9) + #define MISC_PERR_STATUS0_CP_SCPAD_PERR (1UL<<10) + #define MISC_PERR_STATUS0_RXP_RBUFC_PERR (1UL<<11) + #define MISC_PERR_STATUS0_RXP_CTXC_PERR (1UL<<12) + #define MISC_PERR_STATUS0_RXP_SCPAD_PERR (1UL<<13) + #define MISC_PERR_STATUS0_TPAT_SCPAD_PERR (1UL<<14) + #define MISC_PERR_STATUS0_TXP_CTXC_PERR (1UL<<15) + #define MISC_PERR_STATUS0_TXP_SCPAD_PERR (1UL<<16) + #define MISC_PERR_STATUS0_CS_TMEM_PERR (1UL<<17) + #define MISC_PERR_STATUS0_MQ_CTX_PERR (1UL<<18) + #define MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR (1UL<<19) + #define MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR (1UL<<20) + #define MISC_PERR_STATUS0_RBUF_PTRMEM_PERR (1UL<<21) + #define MISC_PERR_STATUS0_RBUF_DATAMEM_PERR (1UL<<22) + #define MISC_PERR_STATUS0_RV2P_P2IRAM_PERR (1UL<<23) + #define MISC_PERR_STATUS0_RV2P_P1IRAM_PERR (1UL<<24) + #define MISC_PERR_STATUS0_RV2P_CB1REGS_PERR (1UL<<25) + #define MISC_PERR_STATUS0_RV2P_CB0REGS_PERR (1UL<<26) + #define MISC_PERR_STATUS0_TPBUF_PERR (1UL<<27) + #define MISC_PERR_STATUS0_THBUF_PERR (1UL<<28) + #define MISC_PERR_STATUS0_TDMA_PERR (1UL<<29) + #define MISC_PERR_STATUS0_TBDC_PERR (1UL<<30) + #define MISC_PERR_STATUS0_TSCH_LR_PERR (1UL<<31) + + u32_t misc_perr_status1; + #define MISC_PERR_STATUS1_RBDC_PERR (1UL<<0) + #define MISC_PERR_STATUS1_RDMA_DFIFO_PERR (1UL<<2) + #define MISC_PERR_STATUS1_HC_STATS_PERR (1UL<<3) + #define MISC_PERR_STATUS1_HC_MSIX_PERR (1UL<<4) + #define MISC_PERR_STATUS1_HC_PRODUCSTB_PERR (1UL<<5) + #define MISC_PERR_STATUS1_HC_CONSUMSTB_PERR (1UL<<6) + #define MISC_PERR_STATUS1_TPATQ_PERR (1UL<<7) + #define MISC_PERR_STATUS1_MCPQ_PERR (1UL<<8) + #define MISC_PERR_STATUS1_TDMAQ_PERR (1UL<<9) + #define MISC_PERR_STATUS1_TXPQ_PERR (1UL<<10) + #define MISC_PERR_STATUS1_COMTQ_PERR (1UL<<11) + #define MISC_PERR_STATUS1_COMQ_PERR (1UL<<12) + #define MISC_PERR_STATUS1_RLUPQ_PERR (1UL<<13) + #define MISC_PERR_STATUS1_RXPQ_PERR (1UL<<14) + #define MISC_PERR_STATUS1_RV2PPQ_PERR (1UL<<15) + #define MISC_PERR_STATUS1_RDMAQ_PERR (1UL<<16) + #define MISC_PERR_STATUS1_TASQ_PERR (1UL<<17) + #define MISC_PERR_STATUS1_TBDRQ_PERR (1UL<<18) + #define MISC_PERR_STATUS1_TSCHQ_PERR (1UL<<19) + #define MISC_PERR_STATUS1_COMXQ_PERR (1UL<<20) + #define MISC_PERR_STATUS1_RXPCQ_PERR (1UL<<21) + #define MISC_PERR_STATUS1_RV2PTQ_PERR (1UL<<22) + #define MISC_PERR_STATUS1_RV2PMQ_PERR (1UL<<23) + #define MISC_PERR_STATUS1_CPQ_PERR (1UL<<24) + #define MISC_PERR_STATUS1_CSQ_PERR (1UL<<25) + #define MISC_PERR_STATUS1_RLUP_CID_PERR (1UL<<26) + #define MISC_PERR_STATUS1_RV2PCS_TMEM_PERR (1UL<<27) + #define MISC_PERR_STATUS1_RV2PCSQ_PERR (1UL<<28) + #define MISC_PERR_STATUS1_MQ_IDX_PERR (1UL<<29) + + u32_t misc_perr_status2; + #define MISC_PERR_STATUS2_TGT_FIFO_PERR (1UL<<0) + #define MISC_PERR_STATUS2_UMP_TX_PERR (1UL<<1) + #define MISC_PERR_STATUS2_UMP_RX_PERR (1UL<<2) + #define MISC_PERR_STATUS2_MCP_ROM_PERR (1UL<<3) + #define MISC_PERR_STATUS2_MCP_SCPAD_PERR (1UL<<4) + #define MISC_PERR_STATUS2_HB_MEM_PERR (1UL<<5) + #define MISC_PERR_STATUS2_PCIE_REPLAY_PERR (1UL<<6) + + u32_t misc_lcpll_ctrl0; + #define MISC_LCPLL_CTRL0_OAC (0x7UL<<0) + #define MISC_LCPLL_CTRL0_OAC_NEGTWENTY (0UL<<0) + #define MISC_LCPLL_CTRL0_OAC_ZERO (1UL<<0) + #define MISC_LCPLL_CTRL0_OAC_TWENTY (3UL<<0) + #define MISC_LCPLL_CTRL0_OAC_FORTY (7UL<<0) + #define MISC_LCPLL_CTRL0_ICP_CTRL (0x7UL<<3) + #define MISC_LCPLL_CTRL0_ICP_CTRL_360 (0UL<<3) + #define MISC_LCPLL_CTRL0_ICP_CTRL_480 (1UL<<3) + #define MISC_LCPLL_CTRL0_ICP_CTRL_600 (3UL<<3) + #define MISC_LCPLL_CTRL0_ICP_CTRL_720 (7UL<<3) + #define MISC_LCPLL_CTRL0_BIAS_CTRL (0x3UL<<6) + #define MISC_LCPLL_CTRL0_PLL_OBSERVE (0x7UL<<8) + #define MISC_LCPLL_CTRL0_VTH_CTRL (0x3UL<<11) + #define MISC_LCPLL_CTRL0_VTH_CTRL_0 (0UL<<11) + #define MISC_LCPLL_CTRL0_VTH_CTRL_1 (1UL<<11) + #define MISC_LCPLL_CTRL0_VTH_CTRL_2 (2UL<<11) + #define MISC_LCPLL_CTRL0_PLLSEQSTART (1UL<<13) + #define MISC_LCPLL_CTRL0_RESERVED (1UL<<14) + #define MISC_LCPLL_CTRL0_CAPRETRY_EN (1UL<<15) + #define MISC_LCPLL_CTRL0_FREQMONITOR_EN (1UL<<16) + #define MISC_LCPLL_CTRL0_FREQDETRESTART_EN (1UL<<17) + #define MISC_LCPLL_CTRL0_FREQDETRETRY_EN (1UL<<18) + #define MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN (1UL<<19) + #define MISC_LCPLL_CTRL0_PLLFORCEFDONE (1UL<<20) + #define MISC_LCPLL_CTRL0_PLLFORCEFPASS (1UL<<21) + #define MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN (1UL<<22) + #define MISC_LCPLL_CTRL0_PLLFORCECAPDONE (1UL<<23) + #define MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN (1UL<<24) + #define MISC_LCPLL_CTRL0_PLLFORCECAPPASS (1UL<<25) + #define MISC_LCPLL_CTRL0_CAPRESTART (1UL<<26) + #define MISC_LCPLL_CTRL0_CAPSELECTM_EN (1UL<<27) + + u32_t misc_lcpll_ctrl1; + #define MISC_LCPLL_CTRL1_CAPSELECTM (0x1fUL<<0) + #define MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN (1UL<<5) + #define MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN (1UL<<6) + #define MISC_LCPLL_CTRL1_SLOWDN_XOR (1UL<<7) + + u32_t misc_lcpll_status; + #define MISC_LCPLL_STATUS_FREQDONE_SM (1UL<<0) + #define MISC_LCPLL_STATUS_FREQPASS_SM (1UL<<1) + #define MISC_LCPLL_STATUS_PLLSEQDONE (1UL<<2) + #define MISC_LCPLL_STATUS_PLLSEQPASS (1UL<<3) + #define MISC_LCPLL_STATUS_PLLSTATE (0x7UL<<4) + #define MISC_LCPLL_STATUS_CAPSTATE (0x7UL<<7) + #define MISC_LCPLL_STATUS_CAPSELECT (0x1fUL<<10) + #define MISC_LCPLL_STATUS_SLOWDN_INDICATOR (1UL<<15) + #define MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 (0UL<<15) + #define MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1 (1UL<<15) + + u32_t misc_oscfunds_ctrl; + #define MISC_OSCFUNDS_CTRL_FREQ_MON (1UL<<5) + #define MISC_OSCFUNDS_CTRL_FREQ_MON_OFF (0UL<<5) + #define MISC_OSCFUNDS_CTRL_FREQ_MON_ON (1UL<<5) + #define MISC_OSCFUNDS_CTRL_XTAL_ADJCM (0x3UL<<6) + #define MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 (0UL<<6) + #define MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1 (1UL<<6) + #define MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2 (2UL<<6) + #define MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3 (3UL<<6) + #define MISC_OSCFUNDS_CTRL_ICBUF_ADJ (0x3UL<<8) + #define MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 (0UL<<8) + #define MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1 (1UL<<8) + #define MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2 (2UL<<8) + #define MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3 (3UL<<8) + #define MISC_OSCFUNDS_CTRL_IAMP_ADJ (0x3UL<<10) + #define MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 (0UL<<10) + #define MISC_OSCFUNDS_CTRL_IAMP_ADJ_1 (1UL<<10) + #define MISC_OSCFUNDS_CTRL_IAMP_ADJ_2 (2UL<<10) + #define MISC_OSCFUNDS_CTRL_IAMP_ADJ_3 (3UL<<10) + + u32_t misc_cpu_otp_ctrl1; + #define MISC_CPU_OTP_CTRL1_START (1UL<<0) + #define MISC_CPU_OTP_CTRL1_COMMAND (0xfUL<<1) + #define MISC_CPU_OTP_CTRL1_COMMAND_READ (0UL<<1) + #define MISC_CPU_OTP_CTRL1_COMMAND_PGM_BIT_INT (1UL<<1) + #define MISC_CPU_OTP_CTRL1_COMMAND_PGM_WORD_INT (2UL<<1) + #define MISC_CPU_OTP_CTRL1_COMMAND_VERIFY (3UL<<1) + #define MISC_CPU_OTP_CTRL1_COMMAND_INIT (4UL<<1) + #define MISC_CPU_OTP_CTRL1_COMMAND_SET (5UL<<1) + #define MISC_CPU_OTP_CTRL1_COMMAND_RST (6UL<<1) + #define MISC_CPU_OTP_CTRL1_COMMAND_OCST (7UL<<1) + #define MISC_CPU_OTP_CTRL1_COMMAND_ROW_LOCK (8UL<<1) + #define MISC_CPU_OTP_CTRL1_COMMAND_PRESCREEN_TEST (9UL<<1) + #define MISC_CPU_OTP_CTRL1_COMMAND_PGM_BIT_EXT (10UL<<1) + #define MISC_CPU_OTP_CTRL1_COMMAND_PGM_WORD_EXT (11UL<<1) + #define MISC_CPU_OTP_CTRL1_WRP_PROG_SEL (1UL<<5) + #define MISC_CPU_OTP_CTRL1_WRP_VSEL (0xfUL<<6) + #define MISC_CPU_OTP_CTRL1_WRP_PCOUNT (0x7UL<<10) + #define MISC_CPU_OTP_CTRL1_WRP_PBYP (1UL<<13) + #define MISC_CPU_OTP_CTRL1_WRP_SADBYP (1UL<<15) + #define MISC_CPU_OTP_CTRL1_WRP_TIME_MARGIN (0x7UL<<16) + #define MISC_CPU_OTP_CTRL1_WRP_CONTINUE_ON_FAIL (1UL<<19) + #define MISC_CPU_OTP_CTRL1_OTP_DEBUG_MODE (1UL<<20) + #define MISC_CPU_OTP_CTRL1_OTP_PROG_EN (1UL<<21) + #define MISC_CPU_OTP_CTRL1_ACCESS_MODE (0x3UL<<22) + #define MISC_CPU_OTP_CTRL1_ACCESS_MODE_RAW (0UL<<22) + #define MISC_CPU_OTP_CTRL1_ACCESS_MODE_MFG (1UL<<22) + #define MISC_CPU_OTP_CTRL1_ACCESS_MODE_CFG (2UL<<22) + #define MISC_CPU_OTP_CTRL1_ACCESS_MODE_REP (3UL<<22) + #define MISC_CPU_OTP_CTRL1_BURST_STAT_SEL (1UL<<24) + + u32_t misc_cpu_otp_ctrl2; + #define MISC_CPU_OTP_CTRL2_OTP_ROM_ADDR (0x3ffUL<<0) + #define MISC_CPU_OTP_CTRL2_DOSEL (0x7fUL<<16) + #define MISC_CPU_OTP_CTRL2_DOSEL_16 (16UL<<16) + #define MISC_CPU_OTP_CTRL2_DOSEL_17 (17UL<<16) + #define MISC_CPU_OTP_CTRL2_DOSEL_127 (127UL<<16) + #define MISC_CPU_OTP_CTRL2_JTAG_CPU_MODE (1UL<<31) + + u32_t misc_cpu_otp_status; + #define MISC_CPU_OTP_STATUS_COMMAND_DONE (1UL<<0) + #define MISC_CPU_OTP_STATUS_WRP_DATA_READY (1UL<<1) + #define MISC_CPU_OTP_STATUS_WRP_DOUT (1UL<<2) + #define MISC_CPU_OTP_STATUS_WRP_BUSY (1UL<<3) + #define MISC_CPU_OTP_STATUS_WRP_FAIL (1UL<<4) + #define MISC_CPU_OTP_STATUS_INVALID_PROG_REQ (1UL<<5) + #define MISC_CPU_OTP_STATUS_PROG_BLOCKED (1UL<<6) + #define MISC_CPU_OTP_STATUS_INIT_WAIT_DONE (1UL<<7) + #define MISC_CPU_OTP_STATUS_DATA (0xffUL<<8) + + u32_t misc_cpu_otp_write_data; + u32_t misc_cpu_otp_read_data; + u32_t misc_mem_65_tm0; + #define MISC_MEM_65_TM0_UMP_EGRESS_TM (0xffUL<<0) + #define MISC_MEM_65_TM0_MCP_SCPAD_TM (0xfUL<<8) + #define MISC_MEM_65_TM0_UMP_INGRESS_TM (0xffUL<<16) + #define MISC_MEM_65_TM0_HB_MEM_TM (0xfUL<<24) + + u32_t misc_mem_65_tm1; + #define MISC_MEM_65_TM1_MCP_ROM_TM (0x1fUL<<0) + #define MISC_MEM_65_TM1_PCIE_DLP2TLP_BUF_TMA (0x3UL<<8) + #define MISC_MEM_65_TM1_PCIE_DLP2TLP_BUF_TMB (0x3UL<<12) + #define MISC_MEM_65_TM1_PCIE_REPLAY_TM (0xfUL<<16) + #define MISC_MEM_65_TM1_PCIE_REPLAY_ADDR_TM (0x3UL<<24) + #define MISC_MEM_65_TM1_TGT_FIFO_TM (0x3UL<<28) + + u32_t misc_weak_wr_cmdstat; + #define MISC_WEAK_WR_CMDSTAT_WW_MODE (1UL<<0) + #define MISC_WEAK_WR_CMDSTAT_WW_START (1UL<<1) + #define MISC_WEAK_WR_CMDSTAT_WW_DONE (1UL<<2) + #define MISC_WEAK_WR_CMDSTAT_HB_MEM_FAIL_FLAG (1UL<<4) + #define MISC_WEAK_WR_CMDSTAT_PCIE_REPLAY_FAIL_FLAG (1UL<<5) + #define MISC_WEAK_WR_CMDSTAT_UMP_INGRESS_FAIL_FLAG (1UL<<6) + #define MISC_WEAK_WR_CMDSTAT_UMP_EGRESS_FAIL_FLAG (1UL<<7) + #define MISC_WEAK_WR_CMDSTAT_MCP_SCPAD_FAIL_FLAG (1UL<<8) + + u32_t misc_new_id; + #define MISC_NEW_ID_CHIP_METAL (0xffUL<<0) + #define MISC_NEW_ID_CHIP_REV (0xfUL<<8) + #define MISC_NEW_ID_CHIP_NUM (0xfffffUL<<12) + + u32_t misc_add_core_ctl; + #define MISC_ADD_CORE_CTL_RESERVED_SOFT (0xffffUL<<0) + #define MISC_ADD_CORE_CTL_RESERVED_HARD (0xffffUL<<16) + + u32_t misc_full_reset_nums0; + #define MISC_FULL_RESET_NUMS0_NUM_HARD_RESETS (0xffUL<<0) + #define MISC_FULL_RESET_NUMS0_NUM_PCIE_RESETS (0xffUL<<8) + #define MISC_FULL_RESET_NUMS0_NUM_PERSTB_RESETS (0xffUL<<16) + #define MISC_FULL_RESET_NUMS0_NUM_CMN_RESETS (0xffUL<<24) + + u32_t misc_full_reset_nums1; + #define MISC_FULL_RESET_NUMS1_NUM_PORT_RESETS (0xffUL<<0) + + u32_t misc_uspll65_ctrl0; + #define MISC_USPLL65_CTRL0_NUM_PORT_RESETS (0xffffffffUL<<0) + + u32_t misc_uspll65_ctrl1; + #define MISC_USPLL65_CTRL1_NUM_PORT_RESETS (0xffffffffUL<<0) + + u32_t misc_lcpll65_ctrl0; + #define MISC_LCPLL65_CTRL0_NUM_PORT_RESETS (0xffffffffUL<<0) + + u32_t misc_lcpll65_ctrl1; + #define MISC_LCPLL65_CTRL1_NUM_PORT_RESETS (0xffffffffUL<<0) + + u32_t misc_lcpll65_status; + #define MISC_LCPLL65_STATUS_NUM_PORT_RESETS (0xffffffffUL<<0) + + u32_t misc_lcpll65_ctrl2; + #define MISC_LCPLL65_CTRL2_NUM_PORT_RESETS (0xffffffffUL<<0) + + u32_t misc_lcpll65_ctrl3; + #define MISC_LCPLL65_CTRL3_NUM_PORT_RESETS (0xffffffffUL<<0) + + u32_t misc_oscfunds65_ctrl1; + #define MISC_OSCFUNDS65_CTRL1_NUM_PORT_RESETS (0xffffffffUL<<0) + + u32_t unused_1[148]; +} misc_reg_t; + + +/* + * p2r_reg definition + * offset: 0x240000 + */ +typedef struct p2r_reg +{ + u32_t p2r_epb_config[256]; + u32_t p2r_debug[256]; + u32_t p2r_mdio_addr; + #define P2R_MDIO_ADDR_ADR (0xffffUL<<0) + #define P2R_MDIO_ADDR_PORT (0xfUL<<16) + #define P2R_MDIO_ADDR_CMD (0xfffUL<<20) + + u32_t p2r_mdio_wr_data; + #define P2R_MDIO_WR_DATA_DATA (0xffffUL<<0) + #define P2R_MDIO_WR_DATA_CMD (1UL<<31) + + u32_t p2r_mdio_rd_data; + #define P2R_MDIO_RD_DATA_DATA (0xffffUL<<0) + #define P2R_MDIO_RD_DATA_CMD (1UL<<31) + + u32_t unused_0[3581]; + u32_t p2r_command; + #define P2R_COMMAND_P2R_CMD_GRC_TIMEOUT (1UL<<0) + + u32_t unused_1[64511]; +} p2r_reg_t; + + +/* + * nvm_reg definition + * offset: 0x6400 + */ +typedef struct nvm_reg +{ + u32_t nvm_command; + #define NVM_COMMAND_RST (1UL<<0) + #define NVM_COMMAND_DONE (1UL<<3) + #define NVM_COMMAND_DOIT (1UL<<4) + #define NVM_COMMAND_WR (1UL<<5) + #define NVM_COMMAND_ERASE (1UL<<6) + #define NVM_COMMAND_FIRST (1UL<<7) + #define NVM_COMMAND_LAST (1UL<<8) + #define NVM_COMMAND_WREN (1UL<<16) + #define NVM_COMMAND_WRDI (1UL<<17) + #define NVM_COMMAND_EWSR (1UL<<18) + #define NVM_COMMAND_WRSR (1UL<<19) + #define NVM_COMMAND_RD_ID (1UL<<20) + #define NVM_COMMAND_RD_STATUS (1UL<<21) + #define NVM_COMMAND_MODE_256 (1UL<<22) + + u32_t nvm_status; + #define NVM_STATUS_PI_FSM_STATE_TE (0xfUL<<0) + #define NVM_STATUS_EE_FSM_STATE_TE (0xfUL<<4) + #define NVM_STATUS_EQ_FSM_STATE_TE (0xfUL<<8) + #define NVM_STATUS_SPI_FSM_STATE_XI (0x1fUL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI (0UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI (1UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI (2UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI (3UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI (4UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI (5UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI (6UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI (7UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI (8UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI (9UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI (10UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI (11UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI (12UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI (13UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI (14UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI (15UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI (16UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI (17UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI (18UL<<0) + #define NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI (19UL<<0) + + u32_t nvm_write; + #define NVM_WRITE_NVM_WRITE_VALUE (0xffffffffUL<<0) + #define NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0UL<<0) + #define NVM_WRITE_NVM_WRITE_VALUE_EECLK_TE (1UL<<0) + #define NVM_WRITE_NVM_WRITE_VALUE_EEDATA_TE (2UL<<0) + #define NVM_WRITE_NVM_WRITE_VALUE_SCLK_TE (4UL<<0) + #define NVM_WRITE_NVM_WRITE_VALUE_CS_B_TE (8UL<<0) + #define NVM_WRITE_NVM_WRITE_VALUE_SO_TE (16UL<<0) + #define NVM_WRITE_NVM_WRITE_VALUE_SI_TE (32UL<<0) + #define NVM_WRITE_NVM_WRITE_VALUE_SI_XI (1UL<<0) + #define NVM_WRITE_NVM_WRITE_VALUE_SO_XI (2UL<<0) + #define NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI (4UL<<0) + #define NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI (8UL<<0) + + u32_t nvm_addr; + #define NVM_ADDR_NVM_ADDR_VALUE (0xffffffUL<<0) + #define NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0UL<<0) + #define NVM_ADDR_NVM_ADDR_VALUE_EECLK_TE (1UL<<0) + #define NVM_ADDR_NVM_ADDR_VALUE_EEDATA_TE (2UL<<0) + #define NVM_ADDR_NVM_ADDR_VALUE_SCLK_TE (4UL<<0) + #define NVM_ADDR_NVM_ADDR_VALUE_CS_B_TE (8UL<<0) + #define NVM_ADDR_NVM_ADDR_VALUE_SO_TE (16UL<<0) + #define NVM_ADDR_NVM_ADDR_VALUE_SI_TE (32UL<<0) + #define NVM_ADDR_NVM_ADDR_VALUE_SI_XI (1UL<<0) + #define NVM_ADDR_NVM_ADDR_VALUE_SO_XI (2UL<<0) + #define NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI (4UL<<0) + #define NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI (8UL<<0) + + u32_t nvm_read; + #define NVM_READ_NVM_READ_VALUE (0xffffffffUL<<0) + #define NVM_READ_NVM_READ_VALUE_BIT_BANG (0UL<<0) + #define NVM_READ_NVM_READ_VALUE_EECLK_TE (1UL<<0) + #define NVM_READ_NVM_READ_VALUE_EEDATA_TE (2UL<<0) + #define NVM_READ_NVM_READ_VALUE_SCLK_TE (4UL<<0) + #define NVM_READ_NVM_READ_VALUE_CS_B_TE (8UL<<0) + #define NVM_READ_NVM_READ_VALUE_SO_TE (16UL<<0) + #define NVM_READ_NVM_READ_VALUE_SI_TE (32UL<<0) + #define NVM_READ_NVM_READ_VALUE_SI_XI (1UL<<0) + #define NVM_READ_NVM_READ_VALUE_SO_XI (2UL<<0) + #define NVM_READ_NVM_READ_VALUE_CS_B_XI (4UL<<0) + #define NVM_READ_NVM_READ_VALUE_SCLK_XI (8UL<<0) + + u32_t nvm_cfg1; + #define NVM_CFG1_FLASH_MODE (1UL<<0) + #define NVM_CFG1_BUFFER_MODE (1UL<<1) + #define NVM_CFG1_PASS_MODE (1UL<<2) + #define NVM_CFG1_BITBANG_MODE (1UL<<3) + #define NVM_CFG1_STATUS_BIT (0x7UL<<4) + #define NVM_CFG1_STATUS_BIT_FLASH_RDY (0UL<<4) + #define NVM_CFG1_STATUS_BIT_BUFFER_RDY (7UL<<4) + #define NVM_CFG1_SPI_CLK_DIV (0xfUL<<7) + #define NVM_CFG1_SEE_CLK_DIV (0x7ffUL<<11) + #define NVM_CFG1_STRAP_CONTROL_0 (1UL<<23) + #define NVM_CFG1_PROTECT_MODE (1UL<<24) + #define NVM_CFG1_FLASH_SIZE (1UL<<25) + #define NVM_CFG1_FW_USTRAP_1 (1UL<<26) + #define NVM_CFG1_FW_USTRAP_0 (1UL<<27) + #define NVM_CFG1_FW_USTRAP_2 (1UL<<28) + #define NVM_CFG1_FW_USTRAP_3 (1UL<<29) + #define NVM_CFG1_FW_FLASH_TYPE_EN (1UL<<30) + #define NVM_CFG1_COMPAT_BYPASSS (1UL<<31) + + u32_t nvm_cfg2; + #define NVM_CFG2_ERASE_CMD (0xffUL<<0) + #define NVM_CFG2_DUMMY (0xffUL<<8) + #define NVM_CFG2_STATUS_CMD (0xffUL<<16) + #define NVM_CFG2_READ_ID (0xffUL<<24) + + u32_t nvm_cfg3; + #define NVM_CFG3_BUFFER_RD_CMD (0xffUL<<0) + #define NVM_CFG3_WRITE_CMD (0xffUL<<8) + #define NVM_CFG3_BUFFER_WRITE_CMD (0xffUL<<16) + #define NVM_CFG3_READ_CMD (0xffUL<<24) + + u32_t nvm_sw_arb; + #define NVM_SW_ARB_ARB_REQ_SET0 (1UL<<0) + #define NVM_SW_ARB_ARB_REQ_SET1 (1UL<<1) + #define NVM_SW_ARB_ARB_REQ_SET2 (1UL<<2) + #define NVM_SW_ARB_ARB_REQ_SET3 (1UL<<3) + #define NVM_SW_ARB_ARB_REQ_CLR0 (1UL<<4) + #define NVM_SW_ARB_ARB_REQ_CLR1 (1UL<<5) + #define NVM_SW_ARB_ARB_REQ_CLR2 (1UL<<6) + #define NVM_SW_ARB_ARB_REQ_CLR3 (1UL<<7) + #define NVM_SW_ARB_ARB_ARB0 (1UL<<8) + #define NVM_SW_ARB_ARB_ARB1 (1UL<<9) + #define NVM_SW_ARB_ARB_ARB2 (1UL<<10) + #define NVM_SW_ARB_ARB_ARB3 (1UL<<11) + #define NVM_SW_ARB_REQ0 (1UL<<12) + #define NVM_SW_ARB_REQ1 (1UL<<13) + #define NVM_SW_ARB_REQ2 (1UL<<14) + #define NVM_SW_ARB_REQ3 (1UL<<15) + + u32_t nvm_access_enable; + #define NVM_ACCESS_ENABLE_EN (1UL<<0) + #define NVM_ACCESS_ENABLE_WR_EN (1UL<<1) + + u32_t nvm_write1; + #define NVM_WRITE1_WREN_CMD (0xffUL<<0) + #define NVM_WRITE1_WRDI_CMD (0xffUL<<8) + #define NVM_WRITE1_SR_DATA (0xffUL<<16) + + u32_t nvm_cfg4; + #define NVM_CFG4_FLASH_SIZE (0x7UL<<0) + #define NVM_CFG4_FLASH_SIZE_1MBIT (0UL<<0) + #define NVM_CFG4_FLASH_SIZE_2MBIT (1UL<<0) + #define NVM_CFG4_FLASH_SIZE_4MBIT (2UL<<0) + #define NVM_CFG4_FLASH_SIZE_8MBIT (3UL<<0) + #define NVM_CFG4_FLASH_SIZE_16MBIT (4UL<<0) + #define NVM_CFG4_FLASH_SIZE_32MBIT (5UL<<0) + #define NVM_CFG4_FLASH_SIZE_64MBIT (6UL<<0) + #define NVM_CFG4_FLASH_SIZE_128MBIT (7UL<<0) + #define NVM_CFG4_FLASH_VENDOR (1UL<<3) + #define NVM_CFG4_FLASH_VENDOR_ST (0UL<<3) + #define NVM_CFG4_FLASH_VENDOR_ATMEL (1UL<<3) + #define NVM_CFG4_MODE_256_EMPTY_BIT_LOC (0x3UL<<4) + #define NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 (0UL<<4) + #define NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9 (1UL<<4) + #define NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10 (2UL<<4) + #define NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11 (3UL<<4) + #define NVM_CFG4_STATUS_BIT_POLARITY (1UL<<6) + #define NVM_CFG4_RESERVED (0x1ffffffUL<<7) + + u32_t nvm_reconfig; + #define NVM_RECONFIG_ORIG_STRAP_VALUE (0xfUL<<0) + #define NVM_RECONFIG_ORIG_STRAP_VALUE_ST (0UL<<0) + #define NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL (1UL<<0) + #define NVM_RECONFIG_RECONFIG_STRAP_VALUE (0xfUL<<4) + #define NVM_RECONFIG_RESERVED (0x7fffffUL<<8) + #define NVM_RECONFIG_RECONFIG_DONE (1UL<<31) + + u32_t unused_0[243]; +} nvm_reg_t; + + +/* + * dma_reg definition + * offset: 0xc00 + */ +typedef struct dma_reg +{ + u32_t dma_command; + #define DMA_COMMAND_ENABLE (1UL<<0) + + u32_t dma_status; + #define DMA_STATUS_PAR_ERROR_STATE_TE (1UL<<0) + #define DMA_STATUS_READ_TRANSFERS_STAT_TE (1UL<<16) + #define DMA_STATUS_READ_DELAY_PCI_CLKS_STAT_TE (1UL<<17) + #define DMA_STATUS_BIG_READ_TRANSFERS_STAT_TE (1UL<<18) + #define DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT_TE (1UL<<19) + #define DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT_TE (1UL<<20) + #define DMA_STATUS_WRITE_TRANSFERS_STAT_TE (1UL<<21) + #define DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT_TE (1UL<<22) + #define DMA_STATUS_BIG_WRITE_TRANSFERS_STAT_TE (1UL<<23) + #define DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT_TE (1UL<<24) + #define DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT_TE (1UL<<25) + #define DMA_STATUS_GLOBAL_ERR_XI (1UL<<0) + #define DMA_STATUS_BME_XI (1UL<<4) + + u32_t dma_config; + #define DMA_CONFIG_DATA_BYTE_SWAP_TE (1UL<<0) + #define DMA_CONFIG_DATA_WORD_SWAP_TE (1UL<<1) + #define DMA_CONFIG_CNTL_BYTE_SWAP_TE (1UL<<4) + #define DMA_CONFIG_CNTL_WORD_SWAP_TE (1UL<<5) + #define DMA_CONFIG_ONE_DMA_TE (1UL<<6) + #define DMA_CONFIG_CNTL_TWO_DMA_TE (1UL<<7) + #define DMA_CONFIG_CNTL_FPGA_MODE_TE (1UL<<8) + #define DMA_CONFIG_CNTL_PING_PONG_DMA_TE (1UL<<10) + #define DMA_CONFIG_CNTL_PCI_COMP_DLY_TE (1UL<<11) + #define DMA_CONFIG_NO_RCHANS_IN_USE_TE (0xfUL<<12) + #define DMA_CONFIG_NO_WCHANS_IN_USE_TE (0xfUL<<16) + #define DMA_CONFIG_PCI_CLK_CMP_BITS_TE (0x7UL<<20) + #define DMA_CONFIG_PCI_FAST_CLK_CMP_TE (1UL<<23) + #define DMA_CONFIG_BIG_SIZE_TE (0xfUL<<24) + #define DMA_CONFIG_BIG_SIZE_NONE_TE (0UL<<24) + #define DMA_CONFIG_BIG_SIZE_64_TE (1UL<<24) + #define DMA_CONFIG_BIG_SIZE_128_TE (2UL<<24) + #define DMA_CONFIG_BIG_SIZE_256_TE (4UL<<24) + #define DMA_CONFIG_BIG_SIZE_512_TE (8UL<<24) + #define DMA_CONFIG_DAT_WBSWAP_MODE_XI (0x3UL<<0) + #define DMA_CONFIG_CTL_WBSWAP_MODE_XI (0x3UL<<4) + #define DMA_CONFIG_MAX_PL_XI (0x7UL<<12) + #define DMA_CONFIG_MAX_PL_128B_XI (0UL<<12) + #define DMA_CONFIG_MAX_PL_256B_XI (1UL<<12) + #define DMA_CONFIG_MAX_PL_512B_XI (2UL<<12) + #define DMA_CONFIG_MAX_PL_EN_XI (1UL<<15) + #define DMA_CONFIG_MAX_RRS_XI (0x7UL<<16) + #define DMA_CONFIG_MAX_RRS_128B_XI (0UL<<16) + #define DMA_CONFIG_MAX_RRS_256B_XI (1UL<<16) + #define DMA_CONFIG_MAX_RRS_512B_XI (2UL<<16) + #define DMA_CONFIG_MAX_RRS_1024B_XI (3UL<<16) + #define DMA_CONFIG_MAX_RRS_2048B_XI (4UL<<16) + #define DMA_CONFIG_MAX_RRS_4096B_XI (5UL<<16) + #define DMA_CONFIG_MAX_RRS_EN_XI (1UL<<19) + #define DMA_CONFIG_NO_64SWAP_EN_XI (1UL<<31) + + u32_t dma_blackout; + #define DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffUL<<0) + #define DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffUL<<8) + #define DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffUL<<16) + + u32_t dma_read_master_setting_0; + #define DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP (1UL<<0) + #define DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER (1UL<<1) + #define DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY (1UL<<2) + #define DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS (0x7UL<<4) + #define DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN (1UL<<7) + #define DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP (1UL<<8) + #define DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER (1UL<<9) + #define DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY (1UL<<10) + #define DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS (0x7UL<<12) + #define DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN (1UL<<15) + #define DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP (1UL<<16) + #define DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER (1UL<<17) + #define DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY (1UL<<18) + #define DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS (0x7UL<<20) + #define DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN (1UL<<23) + #define DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP (1UL<<24) + #define DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER (1UL<<25) + #define DMA_READ_MASTER_SETTING_0_CTX_PRIORITY (1UL<<26) + #define DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS (0x7UL<<28) + #define DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN (1UL<<31) + + u32_t dma_read_master_setting_1; + #define DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP (1UL<<0) + #define DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER (1UL<<1) + #define DMA_READ_MASTER_SETTING_1_COM_PRIORITY (1UL<<2) + #define DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS (0x7UL<<4) + #define DMA_READ_MASTER_SETTING_1_COM_PARAM_EN (1UL<<7) + #define DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP (1UL<<8) + #define DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER (1UL<<9) + #define DMA_READ_MASTER_SETTING_1_CP_PRIORITY (1UL<<10) + #define DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS (0x7UL<<12) + #define DMA_READ_MASTER_SETTING_1_CP_PARAM_EN (1UL<<15) + + u32_t dma_write_master_setting_0; + #define DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP (1UL<<0) + #define DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER (1UL<<1) + #define DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY (1UL<<2) + #define DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD (1UL<<3) + #define DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS (0x7UL<<4) + #define DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN (1UL<<7) + #define DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP (1UL<<8) + #define DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER (1UL<<9) + #define DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY (1UL<<10) + #define DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD (1UL<<11) + #define DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS (0x7UL<<12) + #define DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN (1UL<<15) + #define DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP (1UL<<24) + #define DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER (1UL<<25) + #define DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY (1UL<<26) + #define DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD (1UL<<27) + #define DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS (0x7UL<<28) + #define DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN (1UL<<31) + + u32_t dma_write_master_setting_1; + #define DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP (1UL<<0) + #define DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER (1UL<<1) + #define DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY (1UL<<2) + #define DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD (1UL<<3) + #define DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS (0x7UL<<4) + #define DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN (1UL<<7) + #define DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP (1UL<<8) + #define DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER (1UL<<9) + #define DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY (1UL<<10) + #define DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD (1UL<<11) + #define DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS (0x7UL<<12) + #define DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN (1UL<<15) + + u32_t dma_arbiter; + #define DMA_ARBITER_NUM_READS (0x7UL<<0) + #define DMA_ARBITER_WR_ARB_MODE (1UL<<4) + #define DMA_ARBITER_WR_ARB_MODE_STRICT (0UL<<4) + #define DMA_ARBITER_WR_ARB_MODE_RND_RBN (1UL<<4) + #define DMA_ARBITER_RD_ARB_MODE (0x3UL<<5) + #define DMA_ARBITER_RD_ARB_MODE_STRICT (0UL<<5) + #define DMA_ARBITER_RD_ARB_MODE_RND_RBN (1UL<<5) + #define DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN (2UL<<5) + #define DMA_ARBITER_ALT_MODE_EN (1UL<<8) + #define DMA_ARBITER_RR_MODE (1UL<<9) + #define DMA_ARBITER_TIMER_MODE (1UL<<10) + #define DMA_ARBITER_OUSTD_READ_REQ (0xfUL<<12) + + u32_t dma_arb_timers; + #define DMA_ARB_TIMERS_RD_DRR_WAIT_TIME (0xffUL<<0) + #define DMA_ARB_TIMERS_TM_MIN_TIMEOUT (0xffUL<<12) + #define DMA_ARB_TIMERS_TM_MAX_TIMEOUT (0xfffUL<<20) + + u32_t unused_0; + u32_t dma_debug_vect_peek; + #define DMA_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define DMA_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) + #define DMA_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define DMA_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define DMA_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) + #define DMA_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t dma_tag_ram_00; + #define DMA_TAG_RAM_00_CHANNEL (0xfUL<<0) + #define DMA_TAG_RAM_00_MASTER (0x7UL<<4) + #define DMA_TAG_RAM_00_MASTER_CTX (0UL<<4) + #define DMA_TAG_RAM_00_MASTER_RBDC (1UL<<4) + #define DMA_TAG_RAM_00_MASTER_TBDC (2UL<<4) + #define DMA_TAG_RAM_00_MASTER_COM (3UL<<4) + #define DMA_TAG_RAM_00_MASTER_CP (4UL<<4) + #define DMA_TAG_RAM_00_MASTER_TDMA (5UL<<4) + #define DMA_TAG_RAM_00_SWAP (0x3UL<<7) + #define DMA_TAG_RAM_00_SWAP_CONFIG (0UL<<7) + #define DMA_TAG_RAM_00_SWAP_DATA (1UL<<7) + #define DMA_TAG_RAM_00_SWAP_CONTROL (2UL<<7) + #define DMA_TAG_RAM_00_FUNCTION (1UL<<9) + #define DMA_TAG_RAM_00_VALID (1UL<<10) + + u32_t dma_tag_ram_01; + #define DMA_TAG_RAM_01_CHANNEL (0xfUL<<0) + #define DMA_TAG_RAM_01_MASTER (0x7UL<<4) + #define DMA_TAG_RAM_01_MASTER_CTX (0UL<<4) + #define DMA_TAG_RAM_01_MASTER_RBDC (1UL<<4) + #define DMA_TAG_RAM_01_MASTER_TBDC (2UL<<4) + #define DMA_TAG_RAM_01_MASTER_COM (3UL<<4) + #define DMA_TAG_RAM_01_MASTER_CP (4UL<<4) + #define DMA_TAG_RAM_01_MASTER_TDMA (5UL<<4) + #define DMA_TAG_RAM_01_SWAP (0x3UL<<7) + #define DMA_TAG_RAM_01_SWAP_CONFIG (0UL<<7) + #define DMA_TAG_RAM_01_SWAP_DATA (1UL<<7) + #define DMA_TAG_RAM_01_SWAP_CONTROL (2UL<<7) + #define DMA_TAG_RAM_01_FUNCTION (1UL<<9) + #define DMA_TAG_RAM_01_VALID (1UL<<10) + + u32_t dma_tag_ram_02; + #define DMA_TAG_RAM_02_CHANNEL (0xfUL<<0) + #define DMA_TAG_RAM_02_MASTER (0x7UL<<4) + #define DMA_TAG_RAM_02_MASTER_CTX (0UL<<4) + #define DMA_TAG_RAM_02_MASTER_RBDC (1UL<<4) + #define DMA_TAG_RAM_02_MASTER_TBDC (2UL<<4) + #define DMA_TAG_RAM_02_MASTER_COM (3UL<<4) + #define DMA_TAG_RAM_02_MASTER_CP (4UL<<4) + #define DMA_TAG_RAM_02_MASTER_TDMA (5UL<<4) + #define DMA_TAG_RAM_02_SWAP (0x3UL<<7) + #define DMA_TAG_RAM_02_SWAP_CONFIG (0UL<<7) + #define DMA_TAG_RAM_02_SWAP_DATA (1UL<<7) + #define DMA_TAG_RAM_02_SWAP_CONTROL (2UL<<7) + #define DMA_TAG_RAM_02_FUNCTION (1UL<<9) + #define DMA_TAG_RAM_02_VALID (1UL<<10) + + u32_t dma_tag_ram_03; + #define DMA_TAG_RAM_03_CHANNEL (0xfUL<<0) + #define DMA_TAG_RAM_03_MASTER (0x7UL<<4) + #define DMA_TAG_RAM_03_MASTER_CTX (0UL<<4) + #define DMA_TAG_RAM_03_MASTER_RBDC (1UL<<4) + #define DMA_TAG_RAM_03_MASTER_TBDC (2UL<<4) + #define DMA_TAG_RAM_03_MASTER_COM (3UL<<4) + #define DMA_TAG_RAM_03_MASTER_CP (4UL<<4) + #define DMA_TAG_RAM_03_MASTER_TDMA (5UL<<4) + #define DMA_TAG_RAM_03_SWAP (0x3UL<<7) + #define DMA_TAG_RAM_03_SWAP_CONFIG (0UL<<7) + #define DMA_TAG_RAM_03_SWAP_DATA (1UL<<7) + #define DMA_TAG_RAM_03_SWAP_CONTROL (2UL<<7) + #define DMA_TAG_RAM_03_FUNCTION (1UL<<9) + #define DMA_TAG_RAM_03_VALID (1UL<<10) + + u32_t dma_tag_ram_04; + #define DMA_TAG_RAM_04_CHANNEL (0xfUL<<0) + #define DMA_TAG_RAM_04_MASTER (0x7UL<<4) + #define DMA_TAG_RAM_04_MASTER_CTX (0UL<<4) + #define DMA_TAG_RAM_04_MASTER_RBDC (1UL<<4) + #define DMA_TAG_RAM_04_MASTER_TBDC (2UL<<4) + #define DMA_TAG_RAM_04_MASTER_COM (3UL<<4) + #define DMA_TAG_RAM_04_MASTER_CP (4UL<<4) + #define DMA_TAG_RAM_04_MASTER_TDMA (5UL<<4) + #define DMA_TAG_RAM_04_SWAP (0x3UL<<7) + #define DMA_TAG_RAM_04_SWAP_CONFIG (0UL<<7) + #define DMA_TAG_RAM_04_SWAP_DATA (1UL<<7) + #define DMA_TAG_RAM_04_SWAP_CONTROL (2UL<<7) + #define DMA_TAG_RAM_04_FUNCTION (1UL<<9) + #define DMA_TAG_RAM_04_VALID (1UL<<10) + + u32_t dma_tag_ram_05; + #define DMA_TAG_RAM_05_CHANNEL (0xfUL<<0) + #define DMA_TAG_RAM_05_MASTER (0x7UL<<4) + #define DMA_TAG_RAM_05_MASTER_CTX (0UL<<4) + #define DMA_TAG_RAM_05_MASTER_RBDC (1UL<<4) + #define DMA_TAG_RAM_05_MASTER_TBDC (2UL<<4) + #define DMA_TAG_RAM_05_MASTER_COM (3UL<<4) + #define DMA_TAG_RAM_05_MASTER_CP (4UL<<4) + #define DMA_TAG_RAM_05_MASTER_TDMA (5UL<<4) + #define DMA_TAG_RAM_05_SWAP (0x3UL<<7) + #define DMA_TAG_RAM_05_SWAP_CONFIG (0UL<<7) + #define DMA_TAG_RAM_05_SWAP_DATA (1UL<<7) + #define DMA_TAG_RAM_05_SWAP_CONTROL (2UL<<7) + #define DMA_TAG_RAM_05_FUNCTION (1UL<<9) + #define DMA_TAG_RAM_05_VALID (1UL<<10) + + u32_t dma_tag_ram_06; + #define DMA_TAG_RAM_06_CHANNEL (0xfUL<<0) + #define DMA_TAG_RAM_06_MASTER (0x7UL<<4) + #define DMA_TAG_RAM_06_MASTER_CTX (0UL<<4) + #define DMA_TAG_RAM_06_MASTER_RBDC (1UL<<4) + #define DMA_TAG_RAM_06_MASTER_TBDC (2UL<<4) + #define DMA_TAG_RAM_06_MASTER_COM (3UL<<4) + #define DMA_TAG_RAM_06_MASTER_CP (4UL<<4) + #define DMA_TAG_RAM_06_MASTER_TDMA (5UL<<4) + #define DMA_TAG_RAM_06_SWAP (0x3UL<<7) + #define DMA_TAG_RAM_06_SWAP_CONFIG (0UL<<7) + #define DMA_TAG_RAM_06_SWAP_DATA (1UL<<7) + #define DMA_TAG_RAM_06_SWAP_CONTROL (2UL<<7) + #define DMA_TAG_RAM_06_FUNCTION (1UL<<9) + #define DMA_TAG_RAM_06_VALID (1UL<<10) + + u32_t dma_tag_ram_07; + #define DMA_TAG_RAM_07_CHANNEL (0xfUL<<0) + #define DMA_TAG_RAM_07_MASTER (0x7UL<<4) + #define DMA_TAG_RAM_07_MASTER_CTX (0UL<<4) + #define DMA_TAG_RAM_07_MASTER_RBDC (1UL<<4) + #define DMA_TAG_RAM_07_MASTER_TBDC (2UL<<4) + #define DMA_TAG_RAM_07_MASTER_COM (3UL<<4) + #define DMA_TAG_RAM_07_MASTER_CP (4UL<<4) + #define DMA_TAG_RAM_07_MASTER_TDMA (5UL<<4) + #define DMA_TAG_RAM_07_SWAP (0x3UL<<7) + #define DMA_TAG_RAM_07_SWAP_CONFIG (0UL<<7) + #define DMA_TAG_RAM_07_SWAP_DATA (1UL<<7) + #define DMA_TAG_RAM_07_SWAP_CONTROL (2UL<<7) + #define DMA_TAG_RAM_07_FUNCTION (1UL<<9) + #define DMA_TAG_RAM_07_VALID (1UL<<10) + + u32_t dma_tag_ram_08; + #define DMA_TAG_RAM_08_CHANNEL (0xfUL<<0) + #define DMA_TAG_RAM_08_MASTER (0x7UL<<4) + #define DMA_TAG_RAM_08_MASTER_CTX (0UL<<4) + #define DMA_TAG_RAM_08_MASTER_RBDC (1UL<<4) + #define DMA_TAG_RAM_08_MASTER_TBDC (2UL<<4) + #define DMA_TAG_RAM_08_MASTER_COM (3UL<<4) + #define DMA_TAG_RAM_08_MASTER_CP (4UL<<4) + #define DMA_TAG_RAM_08_MASTER_TDMA (5UL<<4) + #define DMA_TAG_RAM_08_SWAP (0x3UL<<7) + #define DMA_TAG_RAM_08_SWAP_CONFIG (0UL<<7) + #define DMA_TAG_RAM_08_SWAP_DATA (1UL<<7) + #define DMA_TAG_RAM_08_SWAP_CONTROL (2UL<<7) + #define DMA_TAG_RAM_08_FUNCTION (1UL<<9) + #define DMA_TAG_RAM_08_VALID (1UL<<10) + + u32_t dma_tag_ram_09; + #define DMA_TAG_RAM_09_CHANNEL (0xfUL<<0) + #define DMA_TAG_RAM_09_MASTER (0x7UL<<4) + #define DMA_TAG_RAM_09_MASTER_CTX (0UL<<4) + #define DMA_TAG_RAM_09_MASTER_RBDC (1UL<<4) + #define DMA_TAG_RAM_09_MASTER_TBDC (2UL<<4) + #define DMA_TAG_RAM_09_MASTER_COM (3UL<<4) + #define DMA_TAG_RAM_09_MASTER_CP (4UL<<4) + #define DMA_TAG_RAM_09_MASTER_TDMA (5UL<<4) + #define DMA_TAG_RAM_09_SWAP (0x3UL<<7) + #define DMA_TAG_RAM_09_SWAP_CONFIG (0UL<<7) + #define DMA_TAG_RAM_09_SWAP_DATA (1UL<<7) + #define DMA_TAG_RAM_09_SWAP_CONTROL (2UL<<7) + #define DMA_TAG_RAM_09_FUNCTION (1UL<<9) + #define DMA_TAG_RAM_09_VALID (1UL<<10) + + u32_t dma_tag_ram_10; + #define DMA_TAG_RAM_10_CHANNEL (0xfUL<<0) + #define DMA_TAG_RAM_10_MASTER (0x7UL<<4) + #define DMA_TAG_RAM_10_MASTER_CTX (0UL<<4) + #define DMA_TAG_RAM_10_MASTER_RBDC (1UL<<4) + #define DMA_TAG_RAM_10_MASTER_TBDC (2UL<<4) + #define DMA_TAG_RAM_10_MASTER_COM (3UL<<4) + #define DMA_TAG_RAM_10_MASTER_CP (4UL<<4) + #define DMA_TAG_RAM_10_MASTER_TDMA (5UL<<4) + #define DMA_TAG_RAM_10_SWAP (0x3UL<<7) + #define DMA_TAG_RAM_10_SWAP_CONFIG (0UL<<7) + #define DMA_TAG_RAM_10_SWAP_DATA (1UL<<7) + #define DMA_TAG_RAM_10_SWAP_CONTROL (2UL<<7) + #define DMA_TAG_RAM_10_FUNCTION (1UL<<9) + #define DMA_TAG_RAM_10_VALID (1UL<<10) + + u32_t dma_tag_ram_11; + #define DMA_TAG_RAM_11_CHANNEL (0xfUL<<0) + #define DMA_TAG_RAM_11_MASTER (0x7UL<<4) + #define DMA_TAG_RAM_11_MASTER_CTX (0UL<<4) + #define DMA_TAG_RAM_11_MASTER_RBDC (1UL<<4) + #define DMA_TAG_RAM_11_MASTER_TBDC (2UL<<4) + #define DMA_TAG_RAM_11_MASTER_COM (3UL<<4) + #define DMA_TAG_RAM_11_MASTER_CP (4UL<<4) + #define DMA_TAG_RAM_11_MASTER_TDMA (5UL<<4) + #define DMA_TAG_RAM_11_SWAP (0x3UL<<7) + #define DMA_TAG_RAM_11_SWAP_CONFIG (0UL<<7) + #define DMA_TAG_RAM_11_SWAP_DATA (1UL<<7) + #define DMA_TAG_RAM_11_SWAP_CONTROL (2UL<<7) + #define DMA_TAG_RAM_11_FUNCTION (1UL<<9) + #define DMA_TAG_RAM_11_VALID (1UL<<10) + + u32_t dma_rchan_stat_22; + u32_t dma_rchan_stat_30; + u32_t dma_rchan_stat_31; + u32_t dma_rchan_stat_32; + u32_t dma_rchan_stat_40; + u32_t dma_rchan_stat_41; + u32_t dma_rchan_stat_42; + u32_t dma_rchan_stat_50; + u32_t dma_rchan_stat_51; + u32_t dma_rchan_stat_52; + u32_t dma_rchan_stat_60; + u32_t dma_rchan_stat_61; + u32_t dma_rchan_stat_62; + u32_t dma_rchan_stat_70; + u32_t dma_rchan_stat_71; + u32_t dma_rchan_stat_72; + u32_t dma_wchan_stat_00; + #define DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffUL<<0) + + u32_t dma_wchan_stat_01; + #define DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffUL<<0) + + u32_t dma_wchan_stat_02; + #define DMA_WCHAN_STAT_02_LENGTH (0xffffUL<<0) + #define DMA_WCHAN_STAT_02_WORD_SWAP (1UL<<16) + #define DMA_WCHAN_STAT_02_BYTE_SWAP (1UL<<17) + #define DMA_WCHAN_STAT_02_PRIORITY_LVL (1UL<<18) + + u32_t dma_wchan_stat_10; + u32_t dma_wchan_stat_11; + u32_t dma_wchan_stat_12; + u32_t dma_wchan_stat_20; + u32_t dma_wchan_stat_21; + u32_t dma_wchan_stat_22; + u32_t dma_wchan_stat_30; + u32_t dma_wchan_stat_31; + u32_t dma_wchan_stat_32; + u32_t dma_wchan_stat_40; + u32_t dma_wchan_stat_41; + u32_t dma_wchan_stat_42; + u32_t dma_wchan_stat_50; + u32_t dma_wchan_stat_51; + u32_t dma_wchan_stat_52; + u32_t dma_wchan_stat_60; + u32_t dma_wchan_stat_61; + u32_t dma_wchan_stat_62; + u32_t dma_wchan_stat_70; + u32_t dma_wchan_stat_71; + u32_t dma_wchan_stat_72; + u32_t dma_arb_stat_00; + #define DMA_ARB_STAT_00_MASTER (0xffffUL<<0) + #define DMA_ARB_STAT_00_MASTER_ENC (0xffUL<<16) + #define DMA_ARB_STAT_00_CUR_BINMSTR (0xffUL<<24) + + u32_t dma_arb_stat_01; + #define DMA_ARB_STAT_01_LPR_RPTR (0xfUL<<0) + #define DMA_ARB_STAT_01_LPR_WPTR (0xfUL<<4) + #define DMA_ARB_STAT_01_LPB_RPTR (0xfUL<<8) + #define DMA_ARB_STAT_01_LPB_WPTR (0xfUL<<12) + #define DMA_ARB_STAT_01_HPR_RPTR (0xfUL<<16) + #define DMA_ARB_STAT_01_HPR_WPTR (0xfUL<<20) + #define DMA_ARB_STAT_01_HPB_RPTR (0xfUL<<24) + #define DMA_ARB_STAT_01_HPB_WPTR (0xfUL<<28) + + u32_t unused_1[126]; + u32_t dma_fuse_ctrl0_cmd; + #define DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1UL<<0) + #define DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1UL<<1) + #define DMA_FUSE_CTRL0_CMD_SHIFT (1UL<<2) + #define DMA_FUSE_CTRL0_CMD_LOAD (1UL<<3) + #define DMA_FUSE_CTRL0_CMD_SEL (0xfUL<<8) + + u32_t dma_fuse_ctrl0_data; + u32_t dma_fuse_ctrl1_cmd; + #define DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1UL<<0) + #define DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1UL<<1) + #define DMA_FUSE_CTRL1_CMD_SHIFT (1UL<<2) + #define DMA_FUSE_CTRL1_CMD_LOAD (1UL<<3) + #define DMA_FUSE_CTRL1_CMD_SEL (0xfUL<<8) + + u32_t dma_fuse_ctrl1_data; + u32_t dma_fuse_ctrl2_cmd; + #define DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1UL<<0) + #define DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1UL<<1) + #define DMA_FUSE_CTRL2_CMD_SHIFT (1UL<<2) + #define DMA_FUSE_CTRL2_CMD_LOAD (1UL<<3) + #define DMA_FUSE_CTRL2_CMD_SEL (0xfUL<<8) + + u32_t dma_fuse_ctrl2_data; + u32_t unused_2[58]; +} dma_reg_t; + + +/* + * context_reg definition + * offset: 0x1000 + */ +typedef struct context_reg +{ + u32_t ctx_command; + #define CTX_COMMAND_ENABLED (1UL<<0) + #define CTX_COMMAND_DISABLE_USAGE_CNT (1UL<<1) + #define CTX_COMMAND_DISABLE_PLRU (1UL<<2) + #define CTX_COMMAND_DISABLE_COMBINE_READ (1UL<<3) + #define CTX_COMMAND_FLUSH_AHEAD (0x1fUL<<8) + #define CTX_COMMAND_MEM_INIT (1UL<<13) + #define CTX_COMMAND_PAGE_SIZE (0xfUL<<16) + #define CTX_COMMAND_PAGE_SIZE_256 (0UL<<16) + #define CTX_COMMAND_PAGE_SIZE_512 (1UL<<16) + #define CTX_COMMAND_PAGE_SIZE_1K (2UL<<16) + #define CTX_COMMAND_PAGE_SIZE_2K (3UL<<16) + #define CTX_COMMAND_PAGE_SIZE_4K (4UL<<16) + #define CTX_COMMAND_PAGE_SIZE_8K (5UL<<16) + #define CTX_COMMAND_PAGE_SIZE_16K (6UL<<16) + #define CTX_COMMAND_PAGE_SIZE_32K (7UL<<16) + #define CTX_COMMAND_PAGE_SIZE_64K (8UL<<16) + #define CTX_COMMAND_PAGE_SIZE_128K (9UL<<16) + #define CTX_COMMAND_PAGE_SIZE_256K (10UL<<16) + #define CTX_COMMAND_PAGE_SIZE_512K (11UL<<16) + #define CTX_COMMAND_PAGE_SIZE_1M (12UL<<16) + + u32_t ctx_status; + #define CTX_STATUS_LOCK_WAIT (1UL<<0) + #define CTX_STATUS_READ_STAT (1UL<<16) + #define CTX_STATUS_WRITE_STAT (1UL<<17) + #define CTX_STATUS_ACC_STALL_STAT (1UL<<18) + #define CTX_STATUS_LOCK_STALL_STAT (1UL<<19) + #define CTX_STATUS_EXT_READ_STAT (1UL<<20) + #define CTX_STATUS_EXT_WRITE_STAT (1UL<<21) + #define CTX_STATUS_MISS_STAT (1UL<<22) + #define CTX_STATUS_HIT_STAT (1UL<<23) + #define CTX_STATUS_DEAD_LOCK (1UL<<24) + #define CTX_STATUS_USAGE_CNT_ERR (1UL<<25) + #define CTX_STATUS_INVALID_PAGE (1UL<<26) + + u32_t ctx_virt_addr; + #define CTX_VIRT_ADDR_VIRT_ADDR (0x7fffUL<<6) + + u32_t ctx_page_tbl; + #define CTX_PAGE_TBL_PAGE_TBL (0x3fffUL<<6) + + u32_t ctx_data_adr; + #define CTX_DATA_ADR_DATA_ADR (0x7ffffUL<<2) + + u32_t ctx_data; + u32_t ctx_lock; + #define CTX_LOCK_TYPE (0x7UL<<0) + #define CTX_LOCK_TYPE_LOCK_TYPE_VOID_TE (0UL<<0) + #define CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL_TE (1UL<<0) + #define CTX_LOCK_TYPE_LOCK_TYPE_TX_TE (2UL<<0) + #define CTX_LOCK_TYPE_LOCK_TYPE_TIMER_TE (4UL<<0) + #define CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE_TE (7UL<<0) + #define CTX_LOCK_TYPE_VOID_XI (0UL<<0) + #define CTX_LOCK_TYPE_PROTOCOL_XI (1UL<<0) + #define CTX_LOCK_TYPE_TX_XI (2UL<<0) + #define CTX_LOCK_TYPE_TIMER_XI (4UL<<0) + #define CTX_LOCK_TYPE_COMPLETE_XI (7UL<<0) + #define CTX_LOCK_CID_VALUE (0x3fffUL<<7) + #define CTX_LOCK_GRANTED (1UL<<26) + #define CTX_LOCK_MODE (0x7UL<<27) + #define CTX_LOCK_MODE_UNLOCK (0UL<<27) + #define CTX_LOCK_MODE_IMMEDIATE (1UL<<27) + #define CTX_LOCK_MODE_SURE (2UL<<27) + #define CTX_LOCK_STATUS (1UL<<30) + #define CTX_LOCK_REQ (1UL<<31) + + u32_t ctx_ctx_ctrl; + #define CTX_CTX_CTRL_CTX_ADDR (0x7ffffUL<<2) + #define CTX_CTX_CTRL_MOD_USAGE_CNT (0x3UL<<21) + #define CTX_CTX_CTRL_NO_RAM_ACC (1UL<<23) + #define CTX_CTX_CTRL_PREFETCH_SIZE (0x3UL<<24) + #define CTX_CTX_CTRL_ATTR (1UL<<26) + #define CTX_CTX_CTRL_WRITE_REQ (1UL<<30) + #define CTX_CTX_CTRL_READ_REQ (1UL<<31) + + u32_t ctx_ctx_data; + u32_t unused_0[7]; + u32_t ctx_access_status; + #define CTX_ACCESS_STATUS_MASTERENCODED_TE (0xfUL<<0) + #define CTX_ACCESS_STATUS_ACCESSMEMORYSM_TE (0x3UL<<10) + #define CTX_ACCESS_STATUS_PAGETABLEINITSM_TE (0x3UL<<12) + #define CTX_ACCESS_STATUS_ACCESSMEMORYINITSM_TE (0x3UL<<14) + #define CTX_ACCESS_STATUS_QUALIFIED_REQUEST_TE (0x7ffUL<<17) + #define CTX_ACCESS_STATUS_CAMMASTERENCODED_XI (0x1fUL<<0) + #define CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI (0x1fUL<<5) + #define CTX_ACCESS_STATUS_REQUEST_XI (0x3fffffUL<<10) + + u32_t ctx_dbg_lock_status; + #define CTX_DBG_LOCK_STATUS_SM (0x3ffUL<<0) + #define CTX_DBG_LOCK_STATUS_MATCH (0x3ffUL<<22) + + u32_t ctx_cache_ctrl_status; + #define CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW (1UL<<0) + #define CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP (1UL<<1) + #define CTX_CACHE_CTRL_STATUS_FLUSH_START (1UL<<6) + #define CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT (0x3fUL<<7) + #define CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED (0x3fUL<<13) + #define CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE (1UL<<19) + #define CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE (1UL<<20) + #define CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE (1UL<<21) + #define CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE (1UL<<22) + #define CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE (1UL<<23) + #define CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE (1UL<<24) + #define CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE (1UL<<25) + #define CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE (1UL<<26) + #define CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE (1UL<<27) + #define CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE (1UL<<28) + #define CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE (1UL<<29) + + u32_t ctx_cache_ctrl_sm_status; + #define CTX_CACHE_CTRL_SM_STATUS_CS_DWC (0x7UL<<0) + #define CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC (0x7UL<<3) + #define CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC (0x7UL<<6) + #define CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC (0x7UL<<9) + #define CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR (0x7fffUL<<16) + + u32_t ctx_cache_status; + #define CTX_CACHE_STATUS_HELD_ENTRIES (0x3ffUL<<0) + #define CTX_CACHE_STATUS_MAX_HELD_ENTRIES (0x3ffUL<<16) + + u32_t ctx_dma_status; + #define CTX_DMA_STATUS_RD_CHAN0_STATUS (0x3UL<<0) + #define CTX_DMA_STATUS_RD_CHAN1_STATUS (0x3UL<<2) + #define CTX_DMA_STATUS_RD_CHAN2_STATUS (0x3UL<<4) + #define CTX_DMA_STATUS_RD_CHAN3_STATUS (0x3UL<<6) + #define CTX_DMA_STATUS_RD_CHAN4_STATUS (0x3UL<<8) + #define CTX_DMA_STATUS_RD_CHAN5_STATUS (0x3UL<<10) + #define CTX_DMA_STATUS_RD_CHAN6_STATUS (0x3UL<<12) + #define CTX_DMA_STATUS_RD_CHAN7_STATUS (0x3UL<<14) + #define CTX_DMA_STATUS_RD_CHAN8_STATUS (0x3UL<<16) + #define CTX_DMA_STATUS_RD_CHAN9_STATUS (0x3UL<<18) + #define CTX_DMA_STATUS_RD_CHAN10_STATUS (0x3UL<<20) + + u32_t ctx_rep_status; + #define CTX_REP_STATUS_ERROR_ENTRY (0x3ffUL<<0) + #define CTX_REP_STATUS_ERROR_CLIENT_ID (0x1fUL<<10) + #define CTX_REP_STATUS_USAGE_CNT_MAX_ERR (1UL<<16) + #define CTX_REP_STATUS_USAGE_CNT_MIN_ERR (1UL<<17) + #define CTX_REP_STATUS_USAGE_CNT_MISS_ERR (1UL<<18) + + u32_t ctx_cksum_error_status; + #define CTX_CKSUM_ERROR_STATUS_CALCULATED (0xffffUL<<0) + #define CTX_CKSUM_ERROR_STATUS_EXPECTED (0xffffUL<<16) + + u32_t unused_1[8]; + u32_t ctx_chnl_lock_status_0; + #define CTX_CHNL_LOCK_STATUS_0_CID (0x3fffUL<<0) + #define CTX_CHNL_LOCK_STATUS_0_TYPE_TE (0x3UL<<14) + #define CTX_CHNL_LOCK_STATUS_0_MODE_TE (1UL<<16) + #define CTX_CHNL_LOCK_STATUS_0_MODE_XI (1UL<<14) + #define CTX_CHNL_LOCK_STATUS_0_TYPE_XI (0x7UL<<15) + + u32_t ctx_chnl_lock_status_1; + u32_t ctx_chnl_lock_status_2; + u32_t ctx_chnl_lock_status_3; + u32_t ctx_chnl_lock_status_4; + u32_t ctx_chnl_lock_status_5; + u32_t ctx_chnl_lock_status_6; + u32_t ctx_chnl_lock_status_7; + u32_t ctx_chnl_lock_status_8; + u32_t ctx_chnl_lock_status_9; + u32_t ctx_debug_sm; + u32_t unused_2[5]; + u32_t ctx_cache_ctrl; + #define CTX_CACHE_CTRL_CACHE_ADDR (0x3fffUL<<2) + #define CTX_CACHE_CTRL_WRITE_REQ (1UL<<30) + #define CTX_CACHE_CTRL_READ_REQ (1UL<<31) + + u32_t ctx_cache_data; + u32_t ctx_host_page_tbl_ctrl; + #define CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR (0x1ffUL<<0) + #define CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ (1UL<<30) + #define CTX_HOST_PAGE_TBL_CTRL_READ_REQ (1UL<<31) + + u32_t ctx_host_page_tbl_data0; + #define CTX_HOST_PAGE_TBL_DATA0_VALID (1UL<<0) + #define CTX_HOST_PAGE_TBL_DATA0_VALUE (0xffffffUL<<8) + + u32_t ctx_host_page_tbl_data1; + u32_t ctx_cam_ctrl; + #define CTX_CAM_CTRL_CAM_ADDR (0x3ffUL<<0) + #define CTX_CAM_CTRL_RESET (1UL<<27) + #define CTX_CAM_CTRL_INVALIDATE (1UL<<28) + #define CTX_CAM_CTRL_SEARCH (1UL<<29) + #define CTX_CAM_CTRL_WRITE_REQ (1UL<<30) + #define CTX_CAM_CTRL_READ_REQ (1UL<<31) + + u32_t ctx_cam_data; + #define CTX_CAM_DATA_CAM_DATA (0xffffUL<<0) + + u32_t ctx_mirror_ctrl; + #define CTX_MIRROR_CTRL_MIRROR_ADDR (0x3ffUL<<0) + #define CTX_MIRROR_CTRL_WRITE_REQ (1UL<<30) + #define CTX_MIRROR_CTRL_READ_REQ (1UL<<31) + + u32_t ctx_mirror_data; + #define CTX_MIRROR_DATA_MIRROR_DATA (0x7fffUL<<0) + + u32_t ctx_usage_cnt_ctrl; + #define CTX_USAGE_CNT_CTRL_USAGE_CNT_ADDR (0x3ffUL<<0) + #define CTX_USAGE_CNT_CTRL_WRITE_REQ (1UL<<30) + #define CTX_USAGE_CNT_CTRL_READ_REQ (1UL<<31) + + u32_t ctx_usage_cnt_data; + #define CTX_USAGE_CNT_DATA_USAGE_CNT_DATA (0x7fUL<<0) + #define CTX_USAGE_CNT_DATA_USAGE_CNT_ZERO (1UL<<7) + + u32_t unused_3[191]; + u32_t ctx_cam_bist_command; + #define CTX_CAM_BIST_COMMAND_BIST_RST_B (1UL<<0) + #define CTX_CAM_BIST_COMMAND_BIST_EN (1UL<<1) + #define CTX_CAM_BIST_COMMAND_BIST_DONE (1UL<<2) + #define CTX_CAM_BIST_COMMAND_BIST_PASSED (1UL<<3) + + u32_t ctx_cam_bist_status0; + #define CTX_CAM_BIST_STATUS0_MATCH_STATUS (1UL<<0) + #define CTX_CAM_BIST_STATUS0_ACTUAL_BITPOS (0xfUL<<1) + #define CTX_CAM_BIST_STATUS0_ACTUAL_ADDROUT (0x3ffUL<<5) + + u32_t ctx_cam_bist_status1; + #define CTX_CAM_BIST_STATUS1_MATCH_STATUS (1UL<<0) + #define CTX_CAM_BIST_STATUS1_ADDROUT_STATUS (1UL<<1) + #define CTX_CAM_BIST_STATUS1_ACTUAL_ADDROUT (0x3ffUL<<2) + #define CTX_CAM_BIST_STATUS1_EXPECTED_ADDROUT (0x3ffUL<<12) + + u32_t ctx_cam_bist_status2; + #define CTX_CAM_BIST_STATUS2_MATCH_STATUS (1UL<<0) + #define CTX_CAM_BIST_STATUS2_ACTUAL_BITPOS (0xfUL<<1) + #define CTX_CAM_BIST_STATUS2_ACTUAL_ADDROUT (0x3ffUL<<5) + + u32_t ctx_cam_bist_status3; + #define CTX_CAM_BIST_STATUS3_MATCH_STATUS (1UL<<0) + #define CTX_CAM_BIST_STATUS3_ADDROUT_STATUS (1UL<<1) + #define CTX_CAM_BIST_STATUS3_ACTUAL_ADDROUT (0x3ffUL<<2) + #define CTX_CAM_BIST_STATUS3_EXPECTED_ADDROUT (0x3ffUL<<12) + + u32_t ctx_cam_bist_status4; + #define CTX_CAM_BIST_STATUS4_MATCH_STATUS (1UL<<0) + #define CTX_CAM_BIST_STATUS4_ACTUAL_ADDROUT (0x3ffUL<<1) + +} context_reg_t; + + +/* + * emac_reg definition + * offset: 0x1400 + */ +typedef struct emac_reg +{ + u32_t emac_mode; + #define EMAC_MODE_RESET (1UL<<0) + #define EMAC_MODE_HALF_DUPLEX (1UL<<1) + #define EMAC_MODE_PORT (0x3UL<<2) + #define EMAC_MODE_PORT_NONE (0UL<<2) + #define EMAC_MODE_PORT_MII (1UL<<2) + #define EMAC_MODE_PORT_GMII (2UL<<2) + #define EMAC_MODE_PORT_MII_10M (3UL<<2) + #define EMAC_MODE_MAC_LOOP (1UL<<4) + #define EMAC_MODE_25G_MODE (1UL<<5) + #define EMAC_MODE_TAGGED_MAC_CTL (1UL<<7) + #define EMAC_MODE_TX_BURST (1UL<<8) + #define EMAC_MODE_MAX_DEFER_DROP_ENA (1UL<<9) + #define EMAC_MODE_EXT_LINK_POL (1UL<<10) + #define EMAC_MODE_FORCE_LINK (1UL<<11) + #define EMAC_MODE_SERDES_MODE (1UL<<12) + #define EMAC_MODE_BOND_OVRD (1UL<<13) + #define EMAC_MODE_MPKT (1UL<<18) + #define EMAC_MODE_MPKT_RCVD (1UL<<19) + #define EMAC_MODE_ACPI_RCVD (1UL<<20) + + u32_t emac_status; + #define EMAC_STATUS_LINK (1UL<<11) + #define EMAC_STATUS_LINK_CHANGE (1UL<<12) + #define EMAC_STATUS_SERDES_AUTONEG_COMPLETE (1UL<<13) + #define EMAC_STATUS_SERDES_AUTONEG_CHANGE (1UL<<14) + #define EMAC_STATUS_SERDES_NXT_PG_CHANGE (1UL<<16) + #define EMAC_STATUS_SERDES_RX_CONFIG_IS_0 (1UL<<17) + #define EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE (1UL<<18) + #define EMAC_STATUS_MI_COMPLETE (1UL<<22) + #define EMAC_STATUS_MI_INT (1UL<<23) + #define EMAC_STATUS_AP_ERROR (1UL<<24) + #define EMAC_STATUS_PARITY_ERROR_STATE (1UL<<31) + + u32_t emac_attention_ena; + #define EMAC_ATTENTION_ENA_LINK (1UL<<11) + #define EMAC_ATTENTION_ENA_AUTONEG_CHANGE (1UL<<14) + #define EMAC_ATTENTION_ENA_NXT_PG_CHANGE (1UL<<16) + #define EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE (1UL<<18) + #define EMAC_ATTENTION_ENA_MI_COMPLETE (1UL<<22) + #define EMAC_ATTENTION_ENA_MI_INT (1UL<<23) + #define EMAC_ATTENTION_ENA_AP_ERROR (1UL<<24) + + u32_t emac_led; + #define EMAC_LED_OVERRIDE (1UL<<0) + #define EMAC_LED_1000MB_OVERRIDE (1UL<<1) + #define EMAC_LED_100MB_OVERRIDE (1UL<<2) + #define EMAC_LED_10MB_OVERRIDE (1UL<<3) + #define EMAC_LED_TRAFFIC_OVERRIDE (1UL<<4) + #define EMAC_LED_BLNK_TRAFFIC (1UL<<5) + #define EMAC_LED_TRAFFIC (1UL<<6) + #define EMAC_LED_1000MB (1UL<<7) + #define EMAC_LED_100MB (1UL<<8) + #define EMAC_LED_10MB (1UL<<9) + #define EMAC_LED_TRAFFIC_STAT (1UL<<10) + #define EMAC_LED_2500MB (1UL<<11) + #define EMAC_LED_2500MB_OVERRIDE (1UL<<12) + #define EMAC_LED_ACTIVITY_SEL (0x3UL<<17) + #define EMAC_LED_ACTIVITY_SEL_0 (0UL<<17) + #define EMAC_LED_ACTIVITY_SEL_1 (1UL<<17) + #define EMAC_LED_ACTIVITY_SEL_2 (2UL<<17) + #define EMAC_LED_ACTIVITY_SEL_3 (3UL<<17) + #define EMAC_LED_BLNK_RATE (0xfffUL<<19) + #define EMAC_LED_BLNK_RATE_ENA (1UL<<31) + + u32_t emac_mac_match[32]; + u32_t unused_0[2]; + u32_t emac_backoff_seed; + #define EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffUL<<0) + + u32_t emac_rx_mtu_size; + #define EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffUL<<0) + #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1UL<<31) + + u32_t unused_1[3]; + u32_t emac_mdio_comm; + #define EMAC_MDIO_COMM_DATA (0xffffUL<<0) + #define EMAC_MDIO_COMM_REG_ADDR (0x1fUL<<16) + #define EMAC_MDIO_COMM_PHY_ADDR (0x1fUL<<21) + #define EMAC_MDIO_COMM_COMMAND (0x3UL<<26) + #define EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0UL<<26) + #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0UL<<26) + #define EMAC_MDIO_COMM_COMMAND_WRITE_TE (1UL<<26) + #define EMAC_MDIO_COMM_COMMAND_READ_TE (2UL<<26) + #define EMAC_MDIO_COMM_COMMAND_WRITE_22_XI (1UL<<26) + #define EMAC_MDIO_COMM_COMMAND_WRITE_45_XI (1UL<<26) + #define EMAC_MDIO_COMM_COMMAND_READ_22_XI (2UL<<26) + #define EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI (2UL<<26) + #define EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3UL<<26) + #define EMAC_MDIO_COMM_COMMAND_READ_45 (3UL<<26) + #define EMAC_MDIO_COMM_FAIL (1UL<<28) + #define EMAC_MDIO_COMM_START_BUSY (1UL<<29) + #define EMAC_MDIO_COMM_DISEXT (1UL<<30) + + u32_t emac_mdio_status; + #define EMAC_MDIO_STATUS_LINK (1UL<<0) + #define EMAC_MDIO_STATUS_10MB (1UL<<1) + + u32_t emac_mdio_mode; + #define EMAC_MDIO_MODE_SHORT_PREAMBLE (1UL<<1) + #define EMAC_MDIO_MODE_AUTO_POLL (1UL<<4) + #define EMAC_MDIO_MODE_BIT_BANG (1UL<<8) + #define EMAC_MDIO_MODE_MDIO (1UL<<9) + #define EMAC_MDIO_MODE_MDIO_OE (1UL<<10) + #define EMAC_MDIO_MODE_MDC (1UL<<11) + #define EMAC_MDIO_MODE_MDINT (1UL<<12) + #define EMAC_MDIO_MODE_EXT_MDINT (1UL<<13) + #define EMAC_MDIO_MODE_CLOCK_CNT_TE (0x1fUL<<16) + #define EMAC_MDIO_MODE_CLOCK_CNT_XI (0x3fUL<<16) + #define EMAC_MDIO_MODE_CLAUSE_45_XI (1UL<<31) + + u32_t emac_mdio_auto_status; + #define EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1UL<<0) + + u32_t emac_tx_mode; + #define EMAC_TX_MODE_RESET (1UL<<0) + #define EMAC_TX_MODE_CS16_TEST (1UL<<2) + #define EMAC_TX_MODE_EXT_PAUSE_EN (1UL<<3) + #define EMAC_TX_MODE_FLOW_EN (1UL<<4) + #define EMAC_TX_MODE_BIG_BACKOFF (1UL<<5) + #define EMAC_TX_MODE_LONG_PAUSE (1UL<<6) + #define EMAC_TX_MODE_LINK_AWARE (1UL<<7) + + u32_t emac_tx_status; + #define EMAC_TX_STATUS_XOFFED (1UL<<0) + #define EMAC_TX_STATUS_XOFF_SENT (1UL<<1) + #define EMAC_TX_STATUS_XON_SENT (1UL<<2) + #define EMAC_TX_STATUS_LINK_UP (1UL<<3) + #define EMAC_TX_STATUS_UNDERRUN (1UL<<4) + #define EMAC_TX_STATUS_CS16_ERROR (1UL<<5) + + u32_t emac_tx_lengths; + #define EMAC_TX_LENGTHS_SLOT (0xffUL<<0) + #define EMAC_TX_LENGTHS_IPG (0xfUL<<8) + #define EMAC_TX_LENGTHS_IPG_CRS (0x3UL<<12) + + u32_t emac_rx_mode; + #define EMAC_RX_MODE_RESET (1UL<<0) + #define EMAC_RX_MODE_FLOW_EN (1UL<<2) + #define EMAC_RX_MODE_KEEP_MAC_CONTROL (1UL<<3) + #define EMAC_RX_MODE_KEEP_PAUSE (1UL<<4) + #define EMAC_RX_MODE_ACCEPT_OVERSIZE (1UL<<5) + #define EMAC_RX_MODE_ACCEPT_RUNTS (1UL<<6) + #define EMAC_RX_MODE_LLC_CHK (1UL<<7) + #define EMAC_RX_MODE_PROMISCUOUS (1UL<<8) + #define EMAC_RX_MODE_NO_CRC_CHK (1UL<<9) + #define EMAC_RX_MODE_KEEP_VLAN_TAG (1UL<<10) + #define EMAC_RX_MODE_FILT_BROADCAST (1UL<<11) + #define EMAC_RX_MODE_SORT_MODE (1UL<<12) + + u32_t emac_rx_status; + #define EMAC_RX_STATUS_FFED (1UL<<0) + #define EMAC_RX_STATUS_FF_RECEIVED (1UL<<1) + #define EMAC_RX_STATUS_N_RECEIVED (1UL<<2) + + u32_t emac_multicast_hash[8]; + u32_t emac_cksum_error_status; + #define EMAC_CKSUM_ERROR_STATUS_CALCULATED (0xffffUL<<0) + #define EMAC_CKSUM_ERROR_STATUS_EXPECTED (0xffffUL<<16) + + u32_t unused_2[3]; + u32_t emac_rx_stat_ifhcinoctets; + u32_t emac_rx_stat_ifhcinbadoctets; + u32_t emac_rx_stat_etherstatsfragments; + u32_t emac_rx_stat_ifhcinucastpkts; + u32_t emac_rx_stat_ifhcinmulticastpkts; + u32_t emac_rx_stat_ifhcinbroadcastpkts; + u32_t emac_rx_stat_dot3statsfcserrors; + u32_t emac_rx_stat_dot3statsalignmenterrors; + u32_t emac_rx_stat_dot3statscarriersenseerrors; + u32_t emac_rx_stat_xonpauseframesreceived; + u32_t emac_rx_stat_xoffpauseframesreceived; + u32_t emac_rx_stat_maccontrolframesreceived; + u32_t emac_rx_stat_xoffstateentered; + u32_t emac_rx_stat_dot3statsframestoolong; + u32_t emac_rx_stat_etherstatsjabbers; + u32_t emac_rx_stat_etherstatsundersizepkts; + u32_t emac_rx_stat_etherstatspkts64octets; + u32_t emac_rx_stat_etherstatspkts65octetsto127octets; + u32_t emac_rx_stat_etherstatspkts128octetsto255octets; + u32_t emac_rx_stat_etherstatspkts256octetsto511octets; + u32_t emac_rx_stat_etherstatspkts512octetsto1023octets; + u32_t emac_rx_stat_etherstatspkts1024octetsto1522octets; + u32_t emac_rx_stat_etherstatspktsover1522octets; + u32_t emac_rxmac_debug0; + u32_t emac_rxmac_debug1; + #define EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1UL<<0) + #define EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1UL<<1) + #define EMAC_RXMAC_DEBUG1_BAD_CRC (1UL<<2) + #define EMAC_RXMAC_DEBUG1_RX_ERROR (1UL<<3) + #define EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1UL<<4) + #define EMAC_RXMAC_DEBUG1_LAST_DATA (1UL<<5) + #define EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1UL<<6) + #define EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffUL<<7) + #define EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffUL<<23) + + u32_t emac_rxmac_debug2; + #define EMAC_RXMAC_DEBUG2_SM_STATE (0x7UL<<0) + #define EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0UL<<0) + #define EMAC_RXMAC_DEBUG2_SM_STATE_SFD (1UL<<0) + #define EMAC_RXMAC_DEBUG2_SM_STATE_DATA (2UL<<0) + #define EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (3UL<<0) + #define EMAC_RXMAC_DEBUG2_SM_STATE_EXT (4UL<<0) + #define EMAC_RXMAC_DEBUG2_SM_STATE_DROP (5UL<<0) + #define EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (6UL<<0) + #define EMAC_RXMAC_DEBUG2_SM_STATE_FC (7UL<<0) + #define EMAC_RXMAC_DEBUG2_IDI_STATE (0xfUL<<3) + #define EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0UL<<3) + #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (1UL<<3) + #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (2UL<<3) + #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (3UL<<3) + #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (4UL<<3) + #define EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (5UL<<3) + #define EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (6UL<<3) + #define EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (7UL<<3) + #define EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (8UL<<3) + #define EMAC_RXMAC_DEBUG2_BYTE_IN (0xffUL<<7) + #define EMAC_RXMAC_DEBUG2_FALSEC (1UL<<15) + #define EMAC_RXMAC_DEBUG2_TAGGED (1UL<<16) + #define EMAC_RXMAC_DEBUG2_PAUSE_STATE (1UL<<18) + #define EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0UL<<18) + #define EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1UL<<18) + #define EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfUL<<19) + #define EMAC_RXMAC_DEBUG2_QUANTA (0x1fUL<<23) + + u32_t emac_rxmac_debug3; + #define EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffUL<<0) + #define EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffUL<<16) + + u32_t emac_rxmac_debug4; + #define EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffUL<<0) + #define EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fUL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (1UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (2UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (3UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (5UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (6UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (7UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (7UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (8UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (9UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (10UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (14UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (15UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (16UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_MC (17UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (18UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (19UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (20UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (21UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (22UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (23UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_BC (24UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (25UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (26UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (27UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (28UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (29UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_XON (30UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (31UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (32UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (33UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (34UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (35UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (36UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (37UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (38UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (39UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (40UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (41UL<<16) + #define EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (42UL<<16) + #define EMAC_RXMAC_DEBUG4_DROP_PKT (1UL<<22) + #define EMAC_RXMAC_DEBUG4_SLOT_FILLED (1UL<<23) + #define EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1UL<<24) + #define EMAC_RXMAC_DEBUG4_LAST_DATA (1UL<<25) + #define EMAC_RXMAC_DEBUG4_SFD_FOUND (1UL<<26) + #define EMAC_RXMAC_DEBUG4_ADVANCE (1UL<<27) + #define EMAC_RXMAC_DEBUG4_START (1UL<<28) + + u32_t emac_rxmac_debug5; + #define EMAC_RXMAC_DEBUG5_PS_IDISM (0x7UL<<0) + #define EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0UL<<0) + #define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1UL<<0) + #define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2UL<<0) + #define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3UL<<0) + #define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4UL<<0) + #define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5UL<<0) + #define EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6UL<<0) + #define EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7UL<<4) + #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0UL<<4) + #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (1UL<<4) + #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (2UL<<4) + #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (3UL<<4) + #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (4UL<<4) + #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (6UL<<4) + #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (7UL<<4) + #define EMAC_RXMAC_DEBUG5_EOF_DETECTED (1UL<<7) + #define EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7UL<<8) + #define EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1UL<<11) + #define EMAC_RXMAC_DEBUG5_LOAD_CCODE (1UL<<12) + #define EMAC_RXMAC_DEBUG5_LOAD_DATA (1UL<<13) + #define EMAC_RXMAC_DEBUG5_LOAD_STAT (1UL<<14) + #define EMAC_RXMAC_DEBUG5_CLR_STAT (1UL<<15) + #define EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3UL<<16) + #define EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1UL<<19) + #define EMAC_RXMAC_DEBUG5_FMLEN (0xfffUL<<20) + + u32_t emac_rx_stat_falsecarriererrors; + u32_t unused_3[2]; + u32_t emac_rx_stat_ac[23]; + u32_t emac_rxmac_suc_dbg_overrunvec; + u32_t unused_4[5]; + u32_t emac_rx_stat_ac_28; + u32_t unused_5[2]; + u32_t emac_tx_stat_ifhcoutoctets; + u32_t emac_tx_stat_ifhcoutbadoctets; + u32_t emac_tx_stat_etherstatscollisions; + u32_t emac_tx_stat_outxonsent; + u32_t emac_tx_stat_outxoffsent; + u32_t emac_tx_stat_flowcontroldone; + u32_t emac_tx_stat_dot3statssinglecollisionframes; + u32_t emac_tx_stat_dot3statsmultiplecollisionframes; + u32_t emac_tx_stat_dot3statsdeferredtransmissions; + u32_t emac_tx_stat_dot3statsexcessivecollisions; + u32_t emac_tx_stat_dot3statslatecollisions; + u32_t emac_tx_stat_ifhcoutucastpkts; + u32_t emac_tx_stat_ifhcoutmulticastpkts; + u32_t emac_tx_stat_ifhcoutbroadcastpkts; + u32_t emac_tx_stat_etherstatspkts64octets; + u32_t emac_tx_stat_etherstatspkts65octetsto127octets; + u32_t emac_tx_stat_etherstatspkts128octetsto255octets; + u32_t emac_tx_stat_etherstatspkts256octetsto511octets; + u32_t emac_tx_stat_etherstatspkts512octetsto1023octets; + u32_t emac_tx_stat_etherstatspkts1024octetsto1522octets; + u32_t emac_tx_stat_etherstatspktsover1522octets; + u32_t emac_tx_stat_dot3statsinternalmactransmiterrors; + u32_t emac_txmac_debug0; + u32_t emac_txmac_debug1; + #define EMAC_TXMAC_DEBUG1_ODI_STATE (0xfUL<<0) + #define EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0UL<<0) + #define EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (1UL<<0) + #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (4UL<<0) + #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (5UL<<0) + #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (6UL<<0) + #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (7UL<<0) + #define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (8UL<<0) + #define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (9UL<<0) + #define EMAC_TXMAC_DEBUG1_CRS_ENABLE (1UL<<4) + #define EMAC_TXMAC_DEBUG1_BAD_CRC (1UL<<5) + #define EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfUL<<6) + #define EMAC_TXMAC_DEBUG1_SEND_PAUSE (1UL<<10) + #define EMAC_TXMAC_DEBUG1_LATE_COLLISION (1UL<<11) + #define EMAC_TXMAC_DEBUG1_MAX_DEFER (1UL<<12) + #define EMAC_TXMAC_DEBUG1_DEFERRED (1UL<<13) + #define EMAC_TXMAC_DEBUG1_ONE_BYTE (1UL<<14) + #define EMAC_TXMAC_DEBUG1_IPG_TIME (0xfUL<<15) + #define EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffUL<<19) + + u32_t emac_txmac_debug2; + #define EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffUL<<0) + #define EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffUL<<10) + #define EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fUL<<26) + #define EMAC_TXMAC_DEBUG2_COL_BIT (1UL<<31) + + u32_t emac_txmac_debug3; + #define EMAC_TXMAC_DEBUG3_SM_STATE (0xfUL<<0) + #define EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0UL<<0) + #define EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (1UL<<0) + #define EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (2UL<<0) + #define EMAC_TXMAC_DEBUG3_SM_STATE_SFD (3UL<<0) + #define EMAC_TXMAC_DEBUG3_SM_STATE_DATA (4UL<<0) + #define EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (5UL<<0) + #define EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (6UL<<0) + #define EMAC_TXMAC_DEBUG3_SM_STATE_EXT (7UL<<0) + #define EMAC_TXMAC_DEBUG3_SM_STATE_STATB (8UL<<0) + #define EMAC_TXMAC_DEBUG3_SM_STATE_STATG (9UL<<0) + #define EMAC_TXMAC_DEBUG3_SM_STATE_JAM (10UL<<0) + #define EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (11UL<<0) + #define EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (12UL<<0) + #define EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (13UL<<0) + #define EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (14UL<<0) + #define EMAC_TXMAC_DEBUG3_FILT_STATE (0x7UL<<4) + #define EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0UL<<4) + #define EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (1UL<<4) + #define EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (2UL<<4) + #define EMAC_TXMAC_DEBUG3_FILT_STATE_MC (3UL<<4) + #define EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (4UL<<4) + #define EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (5UL<<4) + #define EMAC_TXMAC_DEBUG3_FILT_STATE_BC (6UL<<4) + #define EMAC_TXMAC_DEBUG3_CRS_DONE (1UL<<7) + #define EMAC_TXMAC_DEBUG3_XOFF (1UL<<8) + #define EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfUL<<9) + #define EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fUL<<13) + + u32_t emac_txmac_debug4; + #define EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffUL<<0) + #define EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfUL<<16) + #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0UL<<16) + #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (2UL<<16) + #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (3UL<<16) + #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (4UL<<16) + #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (5UL<<16) + #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (6UL<<16) + #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (7UL<<16) + #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (8UL<<16) + #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (9UL<<16) + #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (10UL<<16) + #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (12UL<<16) + #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (13UL<<16) + #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (14UL<<16) + #define EMAC_TXMAC_DEBUG4_STATS0_VALID (1UL<<20) + #define EMAC_TXMAC_DEBUG4_APPEND_CRC (1UL<<21) + #define EMAC_TXMAC_DEBUG4_SLOT_FILLED (1UL<<22) + #define EMAC_TXMAC_DEBUG4_MAX_DEFER (1UL<<23) + #define EMAC_TXMAC_DEBUG4_SEND_EXTEND (1UL<<24) + #define EMAC_TXMAC_DEBUG4_SEND_PADDING (1UL<<25) + #define EMAC_TXMAC_DEBUG4_EOF_LOC (1UL<<26) + #define EMAC_TXMAC_DEBUG4_COLLIDING (1UL<<27) + #define EMAC_TXMAC_DEBUG4_COL_IN (1UL<<28) + #define EMAC_TXMAC_DEBUG4_BURSTING (1UL<<29) + #define EMAC_TXMAC_DEBUG4_ADVANCE (1UL<<30) + #define EMAC_TXMAC_DEBUG4_GO (1UL<<31) + + u32_t unused_6[5]; + u32_t emac_tx_stat_ac[22]; + u32_t emac_txmac_suc_dbg_overrunvec; + u32_t unused_7[8]; + u32_t emac_tx_rate_limit_ctrl; + #define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC (0x7fUL<<0) + #define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM (0x7fUL<<16) + #define EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN (1UL<<31) + + u32_t unused_8[64]; +} emac_reg_t; + + +/* + * rpm_reg definition + * offset: 0x1800 + */ +typedef struct rpm_reg +{ + u32_t rpm_command; + #define RPM_COMMAND_ENABLED (1UL<<0) + #define RPM_COMMAND_OVERRUN_ABORT (1UL<<4) + + u32_t rpm_status; + #define RPM_STATUS_MBUF_WAIT (1UL<<0) + #define RPM_STATUS_FREE_WAIT (1UL<<1) + + u32_t rpm_config; + #define RPM_CONFIG_NO_PSD_HDR_CKSUM (1UL<<0) + #define RPM_CONFIG_ACPI_ENA (1UL<<1) + #define RPM_CONFIG_ACPI_KEEP (1UL<<2) + #define RPM_CONFIG_MP_KEEP (1UL<<3) + #define RPM_CONFIG_SORT_VECT_VAL (0xfUL<<4) + #define RPM_CONFIG_DISABLE_WOL_ASSERT (1UL<<30) + #define RPM_CONFIG_IGNORE_VLAN (1UL<<31) + + u32_t rpm_mgmt_pkt_ctrl; + #define RPM_MGMT_PKT_CTRL_MGMT_SORT (0xfUL<<0) + #define RPM_MGMT_PKT_CTRL_MGMT_RULE (0xfUL<<4) + #define RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN (1UL<<30) + #define RPM_MGMT_PKT_CTRL_MGMT_EN (1UL<<31) + + u32_t rpm_vlan_match0; + #define RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffUL<<0) + + u32_t rpm_vlan_match1; + #define RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffUL<<0) + + u32_t rpm_vlan_match2; + #define RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffUL<<0) + + u32_t rpm_vlan_match3; + #define RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffUL<<0) + + u32_t rpm_sort_user0; + #define RPM_SORT_USER0_PM_EN (0xffffUL<<0) + #define RPM_SORT_USER0_BC_EN (1UL<<16) + #define RPM_SORT_USER0_MC_EN (1UL<<17) + #define RPM_SORT_USER0_MC_HSH_EN (1UL<<18) + #define RPM_SORT_USER0_PROM_EN (1UL<<19) + #define RPM_SORT_USER0_VLAN_EN (0xfUL<<20) + #define RPM_SORT_USER0_PROM_VLAN (1UL<<24) + #define RPM_SORT_USER0_VLAN_NOTMATCH (1UL<<25) + #define RPM_SORT_USER0_ENA (1UL<<31) + + u32_t rpm_sort_user1; + #define RPM_SORT_USER1_PM_EN (0xffffUL<<0) + #define RPM_SORT_USER1_BC_EN (1UL<<16) + #define RPM_SORT_USER1_MC_EN (1UL<<17) + #define RPM_SORT_USER1_MC_HSH_EN (1UL<<18) + #define RPM_SORT_USER1_PROM_EN (1UL<<19) + #define RPM_SORT_USER1_VLAN_EN (0xfUL<<20) + #define RPM_SORT_USER1_PROM_VLAN (1UL<<24) + #define RPM_SORT_USER1_ENA (1UL<<31) + + u32_t rpm_sort_user2; + #define RPM_SORT_USER2_PM_EN (0xffffUL<<0) + #define RPM_SORT_USER2_BC_EN (1UL<<16) + #define RPM_SORT_USER2_MC_EN (1UL<<17) + #define RPM_SORT_USER2_MC_HSH_EN (1UL<<18) + #define RPM_SORT_USER2_PROM_EN (1UL<<19) + #define RPM_SORT_USER2_VLAN_EN (0xfUL<<20) + #define RPM_SORT_USER2_PROM_VLAN (1UL<<24) + #define RPM_SORT_USER2_ENA (1UL<<31) + + u32_t rpm_sort_user3; + #define RPM_SORT_USER3_PM_EN (0xffffUL<<0) + #define RPM_SORT_USER3_BC_EN (1UL<<16) + #define RPM_SORT_USER3_MC_EN (1UL<<17) + #define RPM_SORT_USER3_MC_HSH_EN (1UL<<18) + #define RPM_SORT_USER3_PROM_EN (1UL<<19) + #define RPM_SORT_USER3_VLAN_EN (0xfUL<<20) + #define RPM_SORT_USER3_PROM_VLAN (1UL<<24) + #define RPM_SORT_USER3_ENA (1UL<<31) + + u32_t unused_0[4]; + u32_t rpm_stat_l2_filter_discards; + u32_t rpm_stat_rule_checker_discards; + u32_t rpm_stat_ifinftqdiscards; + u32_t rpm_stat_ifinmbufdiscard; + u32_t rpm_stat_rule_checker_p4_hit; + u32_t rpm_ipv6_programmable_extension0; + #define RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN (0xffUL<<0) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER (0xffUL<<16) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN (1UL<<31) + + u32_t rpm_ipv6_programmable_extension1; + #define RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN (0xffUL<<0) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER (0xffUL<<16) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN (1UL<<31) + + u32_t rpm_ipv6_programmable_extension2; + #define RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN (0xffUL<<0) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER (0xffUL<<16) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN (1UL<<31) + + u32_t rpm_ipv6_programmable_extension3; + #define RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN (0xffUL<<0) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER (0xffUL<<16) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN (1UL<<31) + + u32_t rpm_ipv6_programmable_extension4; + #define RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN (0xffUL<<0) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER (0xffUL<<16) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN (1UL<<31) + + u32_t rpm_ipv6_programmable_extension5; + #define RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN (0xffUL<<0) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER (0xffUL<<16) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN (1UL<<31) + + u32_t rpm_ipv6_programmable_extension6; + #define RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN (0xffUL<<0) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER (0xffUL<<16) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN (1UL<<31) + + u32_t rpm_ipv6_programmable_extension7; + #define RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN (0xffUL<<0) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER (0xffUL<<16) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN (1UL<<31) + + u32_t unused_1[3]; + u32_t rpm_stat_ac[5]; + u32_t unused_2[19]; + u32_t rpm_rc_cntl_16; + #define RPM_RC_CNTL_16_OFFSET (0xffUL<<0) + #define RPM_RC_CNTL_16_CLASS (0x7UL<<8) + #define RPM_RC_CNTL_16_PRIORITY (1UL<<11) + #define RPM_RC_CNTL_16_P4 (1UL<<12) + #define RPM_RC_CNTL_16_HDR_TYPE (0x7UL<<13) + #define RPM_RC_CNTL_16_HDR_TYPE_START (0UL<<13) + #define RPM_RC_CNTL_16_HDR_TYPE_IP (1UL<<13) + #define RPM_RC_CNTL_16_HDR_TYPE_TCP (2UL<<13) + #define RPM_RC_CNTL_16_HDR_TYPE_UDP (3UL<<13) + #define RPM_RC_CNTL_16_HDR_TYPE_DATA (4UL<<13) + #define RPM_RC_CNTL_16_HDR_TYPE_TCP_UDP (5UL<<13) + #define RPM_RC_CNTL_16_HDR_TYPE_ICMPV6 (6UL<<13) + #define RPM_RC_CNTL_16_COMP (0x3UL<<16) + #define RPM_RC_CNTL_16_COMP_EQUAL (0UL<<16) + #define RPM_RC_CNTL_16_COMP_NEQUAL (1UL<<16) + #define RPM_RC_CNTL_16_COMP_GREATER (2UL<<16) + #define RPM_RC_CNTL_16_COMP_LESS (3UL<<16) + #define RPM_RC_CNTL_16_MAP (1UL<<18) + #define RPM_RC_CNTL_16_SBIT (1UL<<19) + #define RPM_RC_CNTL_16_CMDSEL (0x1fUL<<20) + #define RPM_RC_CNTL_16_DISCARD (1UL<<25) + #define RPM_RC_CNTL_16_MASK (1UL<<26) + #define RPM_RC_CNTL_16_P1 (1UL<<27) + #define RPM_RC_CNTL_16_P2 (1UL<<28) + #define RPM_RC_CNTL_16_P3 (1UL<<29) + #define RPM_RC_CNTL_16_NBIT (1UL<<30) + + u32_t rpm_rc_value_mask_16; + #define RPM_RC_VALUE_MASK_16_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_16_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_17; + #define RPM_RC_CNTL_17_OFFSET (0xffUL<<0) + #define RPM_RC_CNTL_17_CLASS (0x7UL<<8) + #define RPM_RC_CNTL_17_PRIORITY (1UL<<11) + #define RPM_RC_CNTL_17_P4 (1UL<<12) + #define RPM_RC_CNTL_17_HDR_TYPE (0x7UL<<13) + #define RPM_RC_CNTL_17_HDR_TYPE_START (0UL<<13) + #define RPM_RC_CNTL_17_HDR_TYPE_IP (1UL<<13) + #define RPM_RC_CNTL_17_HDR_TYPE_TCP (2UL<<13) + #define RPM_RC_CNTL_17_HDR_TYPE_UDP (3UL<<13) + #define RPM_RC_CNTL_17_HDR_TYPE_DATA (4UL<<13) + #define RPM_RC_CNTL_17_HDR_TYPE_TCP_UDP (5UL<<13) + #define RPM_RC_CNTL_17_HDR_TYPE_ICMPV6 (6UL<<13) + #define RPM_RC_CNTL_17_COMP (0x3UL<<16) + #define RPM_RC_CNTL_17_COMP_EQUAL (0UL<<16) + #define RPM_RC_CNTL_17_COMP_NEQUAL (1UL<<16) + #define RPM_RC_CNTL_17_COMP_GREATER (2UL<<16) + #define RPM_RC_CNTL_17_COMP_LESS (3UL<<16) + #define RPM_RC_CNTL_17_MAP (1UL<<18) + #define RPM_RC_CNTL_17_SBIT (1UL<<19) + #define RPM_RC_CNTL_17_CMDSEL (0x1fUL<<20) + #define RPM_RC_CNTL_17_DISCARD (1UL<<25) + #define RPM_RC_CNTL_17_MASK (1UL<<26) + #define RPM_RC_CNTL_17_P1 (1UL<<27) + #define RPM_RC_CNTL_17_P2 (1UL<<28) + #define RPM_RC_CNTL_17_P3 (1UL<<29) + #define RPM_RC_CNTL_17_NBIT (1UL<<30) + + u32_t rpm_rc_value_mask_17; + #define RPM_RC_VALUE_MASK_17_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_17_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_18; + #define RPM_RC_CNTL_18_OFFSET (0xffUL<<0) + #define RPM_RC_CNTL_18_CLASS (0x7UL<<8) + #define RPM_RC_CNTL_18_PRIORITY (1UL<<11) + #define RPM_RC_CNTL_18_P4 (1UL<<12) + #define RPM_RC_CNTL_18_HDR_TYPE (0x7UL<<13) + #define RPM_RC_CNTL_18_HDR_TYPE_START (0UL<<13) + #define RPM_RC_CNTL_18_HDR_TYPE_IP (1UL<<13) + #define RPM_RC_CNTL_18_HDR_TYPE_TCP (2UL<<13) + #define RPM_RC_CNTL_18_HDR_TYPE_UDP (3UL<<13) + #define RPM_RC_CNTL_18_HDR_TYPE_DATA (4UL<<13) + #define RPM_RC_CNTL_18_HDR_TYPE_TCP_UDP (5UL<<13) + #define RPM_RC_CNTL_18_HDR_TYPE_ICMPV6 (6UL<<13) + #define RPM_RC_CNTL_18_COMP (0x3UL<<16) + #define RPM_RC_CNTL_18_COMP_EQUAL (0UL<<16) + #define RPM_RC_CNTL_18_COMP_NEQUAL (1UL<<16) + #define RPM_RC_CNTL_18_COMP_GREATER (2UL<<16) + #define RPM_RC_CNTL_18_COMP_LESS (3UL<<16) + #define RPM_RC_CNTL_18_MAP (1UL<<18) + #define RPM_RC_CNTL_18_SBIT (1UL<<19) + #define RPM_RC_CNTL_18_CMDSEL (0x1fUL<<20) + #define RPM_RC_CNTL_18_DISCARD (1UL<<25) + #define RPM_RC_CNTL_18_MASK (1UL<<26) + #define RPM_RC_CNTL_18_P1 (1UL<<27) + #define RPM_RC_CNTL_18_P2 (1UL<<28) + #define RPM_RC_CNTL_18_P3 (1UL<<29) + #define RPM_RC_CNTL_18_NBIT (1UL<<30) + + u32_t rpm_rc_value_mask_18; + #define RPM_RC_VALUE_MASK_18_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_18_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_19; + #define RPM_RC_CNTL_19_OFFSET (0xffUL<<0) + #define RPM_RC_CNTL_19_CLASS (0x7UL<<8) + #define RPM_RC_CNTL_19_PRIORITY (1UL<<11) + #define RPM_RC_CNTL_19_P4 (1UL<<12) + #define RPM_RC_CNTL_19_HDR_TYPE (0x7UL<<13) + #define RPM_RC_CNTL_19_HDR_TYPE_START (0UL<<13) + #define RPM_RC_CNTL_19_HDR_TYPE_IP (1UL<<13) + #define RPM_RC_CNTL_19_HDR_TYPE_TCP (2UL<<13) + #define RPM_RC_CNTL_19_HDR_TYPE_UDP (3UL<<13) + #define RPM_RC_CNTL_19_HDR_TYPE_DATA (4UL<<13) + #define RPM_RC_CNTL_19_HDR_TYPE_TCP_UDP (5UL<<13) + #define RPM_RC_CNTL_19_HDR_TYPE_ICMPV6 (6UL<<13) + #define RPM_RC_CNTL_19_COMP (0x3UL<<16) + #define RPM_RC_CNTL_19_COMP_EQUAL (0UL<<16) + #define RPM_RC_CNTL_19_COMP_NEQUAL (1UL<<16) + #define RPM_RC_CNTL_19_COMP_GREATER (2UL<<16) + #define RPM_RC_CNTL_19_COMP_LESS (3UL<<16) + #define RPM_RC_CNTL_19_MAP (1UL<<18) + #define RPM_RC_CNTL_19_SBIT (1UL<<19) + #define RPM_RC_CNTL_19_CMDSEL (0x1fUL<<20) + #define RPM_RC_CNTL_19_DISCARD (1UL<<25) + #define RPM_RC_CNTL_19_MASK (1UL<<26) + #define RPM_RC_CNTL_19_P1 (1UL<<27) + #define RPM_RC_CNTL_19_P2 (1UL<<28) + #define RPM_RC_CNTL_19_P3 (1UL<<29) + #define RPM_RC_CNTL_19_NBIT (1UL<<30) + + u32_t rpm_rc_value_mask_19; + #define RPM_RC_VALUE_MASK_19_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_19_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_0; + #define RPM_RC_CNTL_0_OFFSET (0xffUL<<0) + #define RPM_RC_CNTL_0_CLASS (0x7UL<<8) + #define RPM_RC_CNTL_0_PRIORITY (1UL<<11) + #define RPM_RC_CNTL_0_P4 (1UL<<12) + #define RPM_RC_CNTL_0_HDR_TYPE (0x7UL<<13) + #define RPM_RC_CNTL_0_HDR_TYPE_START (0UL<<13) + #define RPM_RC_CNTL_0_HDR_TYPE_IP (1UL<<13) + #define RPM_RC_CNTL_0_HDR_TYPE_TCP (2UL<<13) + #define RPM_RC_CNTL_0_HDR_TYPE_UDP (3UL<<13) + #define RPM_RC_CNTL_0_HDR_TYPE_DATA (4UL<<13) + #define RPM_RC_CNTL_0_HDR_TYPE_TCP_UDP (5UL<<13) + #define RPM_RC_CNTL_0_HDR_TYPE_ICMPV6 (6UL<<13) + #define RPM_RC_CNTL_0_COMP (0x3UL<<16) + #define RPM_RC_CNTL_0_COMP_EQUAL (0UL<<16) + #define RPM_RC_CNTL_0_COMP_NEQUAL (1UL<<16) + #define RPM_RC_CNTL_0_COMP_GREATER (2UL<<16) + #define RPM_RC_CNTL_0_COMP_LESS (3UL<<16) + #define RPM_RC_CNTL_0_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_0_SBIT (1UL<<19) + #define RPM_RC_CNTL_0_CMDSEL_TE (0xfUL<<20) + #define RPM_RC_CNTL_0_MAP_TE (1UL<<24) + #define RPM_RC_CNTL_0_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_0_DISCARD (1UL<<25) + #define RPM_RC_CNTL_0_MASK (1UL<<26) + #define RPM_RC_CNTL_0_P1 (1UL<<27) + #define RPM_RC_CNTL_0_P2 (1UL<<28) + #define RPM_RC_CNTL_0_P3 (1UL<<29) + #define RPM_RC_CNTL_0_NBIT (1UL<<30) + + u32_t rpm_rc_value_mask_0; + #define RPM_RC_VALUE_MASK_0_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_0_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_1; + #define RPM_RC_CNTL_1_A_TE (0x3ffffUL<<0) + #define RPM_RC_CNTL_1_B_TE (0xfffUL<<19) + #define RPM_RC_CNTL_1_OFFSET_XI (0xffUL<<0) + #define RPM_RC_CNTL_1_CLASS_XI (0x7UL<<8) + #define RPM_RC_CNTL_1_PRIORITY_XI (1UL<<11) + #define RPM_RC_CNTL_1_P4_XI (1UL<<12) + #define RPM_RC_CNTL_1_HDR_TYPE_XI (0x7UL<<13) + #define RPM_RC_CNTL_1_HDR_TYPE_START_XI (0UL<<13) + #define RPM_RC_CNTL_1_HDR_TYPE_IP_XI (1UL<<13) + #define RPM_RC_CNTL_1_HDR_TYPE_TCP_XI (2UL<<13) + #define RPM_RC_CNTL_1_HDR_TYPE_UDP_XI (3UL<<13) + #define RPM_RC_CNTL_1_HDR_TYPE_DATA_XI (4UL<<13) + #define RPM_RC_CNTL_1_HDR_TYPE_TCP_UDP_XI (5UL<<13) + #define RPM_RC_CNTL_1_HDR_TYPE_ICMPV6_XI (6UL<<13) + #define RPM_RC_CNTL_1_COMP_XI (0x3UL<<16) + #define RPM_RC_CNTL_1_COMP_EQUAL_XI (0UL<<16) + #define RPM_RC_CNTL_1_COMP_NEQUAL_XI (1UL<<16) + #define RPM_RC_CNTL_1_COMP_GREATER_XI (2UL<<16) + #define RPM_RC_CNTL_1_COMP_LESS_XI (3UL<<16) + #define RPM_RC_CNTL_1_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_1_SBIT_XI (1UL<<19) + #define RPM_RC_CNTL_1_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_1_DISCARD_XI (1UL<<25) + #define RPM_RC_CNTL_1_MASK_XI (1UL<<26) + #define RPM_RC_CNTL_1_P1_XI (1UL<<27) + #define RPM_RC_CNTL_1_P2_XI (1UL<<28) + #define RPM_RC_CNTL_1_P3_XI (1UL<<29) + #define RPM_RC_CNTL_1_NBIT_XI (1UL<<30) + + u32_t rpm_rc_value_mask_1; + #define RPM_RC_VALUE_MASK_1_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_1_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_2; + #define RPM_RC_CNTL_2_A_TE (0x3ffffUL<<0) + #define RPM_RC_CNTL_2_B_TE (0xfffUL<<19) + #define RPM_RC_CNTL_2_OFFSET_XI (0xffUL<<0) + #define RPM_RC_CNTL_2_CLASS_XI (0x7UL<<8) + #define RPM_RC_CNTL_2_PRIORITY_XI (1UL<<11) + #define RPM_RC_CNTL_2_P4_XI (1UL<<12) + #define RPM_RC_CNTL_2_HDR_TYPE_XI (0x7UL<<13) + #define RPM_RC_CNTL_2_HDR_TYPE_START_XI (0UL<<13) + #define RPM_RC_CNTL_2_HDR_TYPE_IP_XI (1UL<<13) + #define RPM_RC_CNTL_2_HDR_TYPE_TCP_XI (2UL<<13) + #define RPM_RC_CNTL_2_HDR_TYPE_UDP_XI (3UL<<13) + #define RPM_RC_CNTL_2_HDR_TYPE_DATA_XI (4UL<<13) + #define RPM_RC_CNTL_2_HDR_TYPE_TCP_UDP_XI (5UL<<13) + #define RPM_RC_CNTL_2_HDR_TYPE_ICMPV6_XI (6UL<<13) + #define RPM_RC_CNTL_2_COMP_XI (0x3UL<<16) + #define RPM_RC_CNTL_2_COMP_EQUAL_XI (0UL<<16) + #define RPM_RC_CNTL_2_COMP_NEQUAL_XI (1UL<<16) + #define RPM_RC_CNTL_2_COMP_GREATER_XI (2UL<<16) + #define RPM_RC_CNTL_2_COMP_LESS_XI (3UL<<16) + #define RPM_RC_CNTL_2_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_2_SBIT_XI (1UL<<19) + #define RPM_RC_CNTL_2_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_2_DISCARD_XI (1UL<<25) + #define RPM_RC_CNTL_2_MASK_XI (1UL<<26) + #define RPM_RC_CNTL_2_P1_XI (1UL<<27) + #define RPM_RC_CNTL_2_P2_XI (1UL<<28) + #define RPM_RC_CNTL_2_P3_XI (1UL<<29) + #define RPM_RC_CNTL_2_NBIT_XI (1UL<<30) + + u32_t rpm_rc_value_mask_2; + #define RPM_RC_VALUE_MASK_2_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_2_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_3; + #define RPM_RC_CNTL_3_A_TE (0x3ffffUL<<0) + #define RPM_RC_CNTL_3_B_TE (0xfffUL<<19) + #define RPM_RC_CNTL_3_OFFSET_XI (0xffUL<<0) + #define RPM_RC_CNTL_3_CLASS_XI (0x7UL<<8) + #define RPM_RC_CNTL_3_PRIORITY_XI (1UL<<11) + #define RPM_RC_CNTL_3_P4_XI (1UL<<12) + #define RPM_RC_CNTL_3_HDR_TYPE_XI (0x7UL<<13) + #define RPM_RC_CNTL_3_HDR_TYPE_START_XI (0UL<<13) + #define RPM_RC_CNTL_3_HDR_TYPE_IP_XI (1UL<<13) + #define RPM_RC_CNTL_3_HDR_TYPE_TCP_XI (2UL<<13) + #define RPM_RC_CNTL_3_HDR_TYPE_UDP_XI (3UL<<13) + #define RPM_RC_CNTL_3_HDR_TYPE_DATA_XI (4UL<<13) + #define RPM_RC_CNTL_3_HDR_TYPE_TCP_UDP_XI (5UL<<13) + #define RPM_RC_CNTL_3_HDR_TYPE_ICMPV6_XI (6UL<<13) + #define RPM_RC_CNTL_3_COMP_XI (0x3UL<<16) + #define RPM_RC_CNTL_3_COMP_EQUAL_XI (0UL<<16) + #define RPM_RC_CNTL_3_COMP_NEQUAL_XI (1UL<<16) + #define RPM_RC_CNTL_3_COMP_GREATER_XI (2UL<<16) + #define RPM_RC_CNTL_3_COMP_LESS_XI (3UL<<16) + #define RPM_RC_CNTL_3_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_3_SBIT_XI (1UL<<19) + #define RPM_RC_CNTL_3_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_3_DISCARD_XI (1UL<<25) + #define RPM_RC_CNTL_3_MASK_XI (1UL<<26) + #define RPM_RC_CNTL_3_P1_XI (1UL<<27) + #define RPM_RC_CNTL_3_P2_XI (1UL<<28) + #define RPM_RC_CNTL_3_P3_XI (1UL<<29) + #define RPM_RC_CNTL_3_NBIT_XI (1UL<<30) + + u32_t rpm_rc_value_mask_3; + #define RPM_RC_VALUE_MASK_3_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_3_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_4; + #define RPM_RC_CNTL_4_A_TE (0x3ffffUL<<0) + #define RPM_RC_CNTL_4_B_TE (0xfffUL<<19) + #define RPM_RC_CNTL_4_OFFSET_XI (0xffUL<<0) + #define RPM_RC_CNTL_4_CLASS_XI (0x7UL<<8) + #define RPM_RC_CNTL_4_PRIORITY_XI (1UL<<11) + #define RPM_RC_CNTL_4_P4_XI (1UL<<12) + #define RPM_RC_CNTL_4_HDR_TYPE_XI (0x7UL<<13) + #define RPM_RC_CNTL_4_HDR_TYPE_START_XI (0UL<<13) + #define RPM_RC_CNTL_4_HDR_TYPE_IP_XI (1UL<<13) + #define RPM_RC_CNTL_4_HDR_TYPE_TCP_XI (2UL<<13) + #define RPM_RC_CNTL_4_HDR_TYPE_UDP_XI (3UL<<13) + #define RPM_RC_CNTL_4_HDR_TYPE_DATA_XI (4UL<<13) + #define RPM_RC_CNTL_4_HDR_TYPE_TCP_UDP_XI (5UL<<13) + #define RPM_RC_CNTL_4_HDR_TYPE_ICMPV6_XI (6UL<<13) + #define RPM_RC_CNTL_4_COMP_XI (0x3UL<<16) + #define RPM_RC_CNTL_4_COMP_EQUAL_XI (0UL<<16) + #define RPM_RC_CNTL_4_COMP_NEQUAL_XI (1UL<<16) + #define RPM_RC_CNTL_4_COMP_GREATER_XI (2UL<<16) + #define RPM_RC_CNTL_4_COMP_LESS_XI (3UL<<16) + #define RPM_RC_CNTL_4_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_4_SBIT_XI (1UL<<19) + #define RPM_RC_CNTL_4_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_4_DISCARD_XI (1UL<<25) + #define RPM_RC_CNTL_4_MASK_XI (1UL<<26) + #define RPM_RC_CNTL_4_P1_XI (1UL<<27) + #define RPM_RC_CNTL_4_P2_XI (1UL<<28) + #define RPM_RC_CNTL_4_P3_XI (1UL<<29) + #define RPM_RC_CNTL_4_NBIT_XI (1UL<<30) + + u32_t rpm_rc_value_mask_4; + #define RPM_RC_VALUE_MASK_4_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_4_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_5; + #define RPM_RC_CNTL_5_A_TE (0x3ffffUL<<0) + #define RPM_RC_CNTL_5_B_TE (0xfffUL<<19) + #define RPM_RC_CNTL_5_OFFSET_XI (0xffUL<<0) + #define RPM_RC_CNTL_5_CLASS_XI (0x7UL<<8) + #define RPM_RC_CNTL_5_PRIORITY_XI (1UL<<11) + #define RPM_RC_CNTL_5_P4_XI (1UL<<12) + #define RPM_RC_CNTL_5_HDR_TYPE_XI (0x7UL<<13) + #define RPM_RC_CNTL_5_HDR_TYPE_START_XI (0UL<<13) + #define RPM_RC_CNTL_5_HDR_TYPE_IP_XI (1UL<<13) + #define RPM_RC_CNTL_5_HDR_TYPE_TCP_XI (2UL<<13) + #define RPM_RC_CNTL_5_HDR_TYPE_UDP_XI (3UL<<13) + #define RPM_RC_CNTL_5_HDR_TYPE_DATA_XI (4UL<<13) + #define RPM_RC_CNTL_5_HDR_TYPE_TCP_UDP_XI (5UL<<13) + #define RPM_RC_CNTL_5_HDR_TYPE_ICMPV6_XI (6UL<<13) + #define RPM_RC_CNTL_5_COMP_XI (0x3UL<<16) + #define RPM_RC_CNTL_5_COMP_EQUAL_XI (0UL<<16) + #define RPM_RC_CNTL_5_COMP_NEQUAL_XI (1UL<<16) + #define RPM_RC_CNTL_5_COMP_GREATER_XI (2UL<<16) + #define RPM_RC_CNTL_5_COMP_LESS_XI (3UL<<16) + #define RPM_RC_CNTL_5_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_5_SBIT_XI (1UL<<19) + #define RPM_RC_CNTL_5_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_5_DISCARD_XI (1UL<<25) + #define RPM_RC_CNTL_5_MASK_XI (1UL<<26) + #define RPM_RC_CNTL_5_P1_XI (1UL<<27) + #define RPM_RC_CNTL_5_P2_XI (1UL<<28) + #define RPM_RC_CNTL_5_P3_XI (1UL<<29) + #define RPM_RC_CNTL_5_NBIT_XI (1UL<<30) + + u32_t rpm_rc_value_mask_5; + #define RPM_RC_VALUE_MASK_5_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_5_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_6; + #define RPM_RC_CNTL_6_A_TE (0x3ffffUL<<0) + #define RPM_RC_CNTL_6_B_TE (0xfffUL<<19) + #define RPM_RC_CNTL_6_OFFSET_XI (0xffUL<<0) + #define RPM_RC_CNTL_6_CLASS_XI (0x7UL<<8) + #define RPM_RC_CNTL_6_PRIORITY_XI (1UL<<11) + #define RPM_RC_CNTL_6_P4_XI (1UL<<12) + #define RPM_RC_CNTL_6_HDR_TYPE_XI (0x7UL<<13) + #define RPM_RC_CNTL_6_HDR_TYPE_START_XI (0UL<<13) + #define RPM_RC_CNTL_6_HDR_TYPE_IP_XI (1UL<<13) + #define RPM_RC_CNTL_6_HDR_TYPE_TCP_XI (2UL<<13) + #define RPM_RC_CNTL_6_HDR_TYPE_UDP_XI (3UL<<13) + #define RPM_RC_CNTL_6_HDR_TYPE_DATA_XI (4UL<<13) + #define RPM_RC_CNTL_6_HDR_TYPE_TCP_UDP_XI (5UL<<13) + #define RPM_RC_CNTL_6_HDR_TYPE_ICMPV6_XI (6UL<<13) + #define RPM_RC_CNTL_6_COMP_XI (0x3UL<<16) + #define RPM_RC_CNTL_6_COMP_EQUAL_XI (0UL<<16) + #define RPM_RC_CNTL_6_COMP_NEQUAL_XI (1UL<<16) + #define RPM_RC_CNTL_6_COMP_GREATER_XI (2UL<<16) + #define RPM_RC_CNTL_6_COMP_LESS_XI (3UL<<16) + #define RPM_RC_CNTL_6_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_6_SBIT_XI (1UL<<19) + #define RPM_RC_CNTL_6_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_6_DISCARD_XI (1UL<<25) + #define RPM_RC_CNTL_6_MASK_XI (1UL<<26) + #define RPM_RC_CNTL_6_P1_XI (1UL<<27) + #define RPM_RC_CNTL_6_P2_XI (1UL<<28) + #define RPM_RC_CNTL_6_P3_XI (1UL<<29) + #define RPM_RC_CNTL_6_NBIT_XI (1UL<<30) + + u32_t rpm_rc_value_mask_6; + #define RPM_RC_VALUE_MASK_6_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_6_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_7; + #define RPM_RC_CNTL_7_A_TE (0x3ffffUL<<0) + #define RPM_RC_CNTL_7_B_TE (0xfffUL<<19) + #define RPM_RC_CNTL_7_OFFSET_XI (0xffUL<<0) + #define RPM_RC_CNTL_7_CLASS_XI (0x7UL<<8) + #define RPM_RC_CNTL_7_PRIORITY_XI (1UL<<11) + #define RPM_RC_CNTL_7_P4_XI (1UL<<12) + #define RPM_RC_CNTL_7_HDR_TYPE_XI (0x7UL<<13) + #define RPM_RC_CNTL_7_HDR_TYPE_START_XI (0UL<<13) + #define RPM_RC_CNTL_7_HDR_TYPE_IP_XI (1UL<<13) + #define RPM_RC_CNTL_7_HDR_TYPE_TCP_XI (2UL<<13) + #define RPM_RC_CNTL_7_HDR_TYPE_UDP_XI (3UL<<13) + #define RPM_RC_CNTL_7_HDR_TYPE_DATA_XI (4UL<<13) + #define RPM_RC_CNTL_7_HDR_TYPE_TCP_UDP_XI (5UL<<13) + #define RPM_RC_CNTL_7_HDR_TYPE_ICMPV6_XI (6UL<<13) + #define RPM_RC_CNTL_7_COMP_XI (0x3UL<<16) + #define RPM_RC_CNTL_7_COMP_EQUAL_XI (0UL<<16) + #define RPM_RC_CNTL_7_COMP_NEQUAL_XI (1UL<<16) + #define RPM_RC_CNTL_7_COMP_GREATER_XI (2UL<<16) + #define RPM_RC_CNTL_7_COMP_LESS_XI (3UL<<16) + #define RPM_RC_CNTL_7_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_7_SBIT_XI (1UL<<19) + #define RPM_RC_CNTL_7_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_7_DISCARD_XI (1UL<<25) + #define RPM_RC_CNTL_7_MASK_XI (1UL<<26) + #define RPM_RC_CNTL_7_P1_XI (1UL<<27) + #define RPM_RC_CNTL_7_P2_XI (1UL<<28) + #define RPM_RC_CNTL_7_P3_XI (1UL<<29) + #define RPM_RC_CNTL_7_NBIT_XI (1UL<<30) + + u32_t rpm_rc_value_mask_7; + #define RPM_RC_VALUE_MASK_7_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_7_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_8; + #define RPM_RC_CNTL_8_A_TE (0x3ffffUL<<0) + #define RPM_RC_CNTL_8_B_TE (0xfffUL<<19) + #define RPM_RC_CNTL_8_OFFSET_XI (0xffUL<<0) + #define RPM_RC_CNTL_8_CLASS_XI (0x7UL<<8) + #define RPM_RC_CNTL_8_PRIORITY_XI (1UL<<11) + #define RPM_RC_CNTL_8_P4_XI (1UL<<12) + #define RPM_RC_CNTL_8_HDR_TYPE_XI (0x7UL<<13) + #define RPM_RC_CNTL_8_HDR_TYPE_START_XI (0UL<<13) + #define RPM_RC_CNTL_8_HDR_TYPE_IP_XI (1UL<<13) + #define RPM_RC_CNTL_8_HDR_TYPE_TCP_XI (2UL<<13) + #define RPM_RC_CNTL_8_HDR_TYPE_UDP_XI (3UL<<13) + #define RPM_RC_CNTL_8_HDR_TYPE_DATA_XI (4UL<<13) + #define RPM_RC_CNTL_8_HDR_TYPE_TCP_UDP_XI (5UL<<13) + #define RPM_RC_CNTL_8_HDR_TYPE_ICMPV6_XI (6UL<<13) + #define RPM_RC_CNTL_8_COMP_XI (0x3UL<<16) + #define RPM_RC_CNTL_8_COMP_EQUAL_XI (0UL<<16) + #define RPM_RC_CNTL_8_COMP_NEQUAL_XI (1UL<<16) + #define RPM_RC_CNTL_8_COMP_GREATER_XI (2UL<<16) + #define RPM_RC_CNTL_8_COMP_LESS_XI (3UL<<16) + #define RPM_RC_CNTL_8_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_8_SBIT_XI (1UL<<19) + #define RPM_RC_CNTL_8_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_8_DISCARD_XI (1UL<<25) + #define RPM_RC_CNTL_8_MASK_XI (1UL<<26) + #define RPM_RC_CNTL_8_P1_XI (1UL<<27) + #define RPM_RC_CNTL_8_P2_XI (1UL<<28) + #define RPM_RC_CNTL_8_P3_XI (1UL<<29) + #define RPM_RC_CNTL_8_NBIT_XI (1UL<<30) + + u32_t rpm_rc_value_mask_8; + #define RPM_RC_VALUE_MASK_8_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_8_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_9; + #define RPM_RC_CNTL_9_A_TE (0x3ffffUL<<0) + #define RPM_RC_CNTL_9_B_TE (0xfffUL<<19) + #define RPM_RC_CNTL_9_OFFSET_XI (0xffUL<<0) + #define RPM_RC_CNTL_9_CLASS_XI (0x7UL<<8) + #define RPM_RC_CNTL_9_PRIORITY_XI (1UL<<11) + #define RPM_RC_CNTL_9_P4_XI (1UL<<12) + #define RPM_RC_CNTL_9_HDR_TYPE_XI (0x7UL<<13) + #define RPM_RC_CNTL_9_HDR_TYPE_START_XI (0UL<<13) + #define RPM_RC_CNTL_9_HDR_TYPE_IP_XI (1UL<<13) + #define RPM_RC_CNTL_9_HDR_TYPE_TCP_XI (2UL<<13) + #define RPM_RC_CNTL_9_HDR_TYPE_UDP_XI (3UL<<13) + #define RPM_RC_CNTL_9_HDR_TYPE_DATA_XI (4UL<<13) + #define RPM_RC_CNTL_9_HDR_TYPE_TCP_UDP_XI (5UL<<13) + #define RPM_RC_CNTL_9_HDR_TYPE_ICMPV6_XI (6UL<<13) + #define RPM_RC_CNTL_9_COMP_XI (0x3UL<<16) + #define RPM_RC_CNTL_9_COMP_EQUAL_XI (0UL<<16) + #define RPM_RC_CNTL_9_COMP_NEQUAL_XI (1UL<<16) + #define RPM_RC_CNTL_9_COMP_GREATER_XI (2UL<<16) + #define RPM_RC_CNTL_9_COMP_LESS_XI (3UL<<16) + #define RPM_RC_CNTL_9_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_9_SBIT_XI (1UL<<19) + #define RPM_RC_CNTL_9_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_9_DISCARD_XI (1UL<<25) + #define RPM_RC_CNTL_9_MASK_XI (1UL<<26) + #define RPM_RC_CNTL_9_P1_XI (1UL<<27) + #define RPM_RC_CNTL_9_P2_XI (1UL<<28) + #define RPM_RC_CNTL_9_P3_XI (1UL<<29) + #define RPM_RC_CNTL_9_NBIT_XI (1UL<<30) + + u32_t rpm_rc_value_mask_9; + #define RPM_RC_VALUE_MASK_9_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_9_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_10; + #define RPM_RC_CNTL_10_A_TE (0x3ffffUL<<0) + #define RPM_RC_CNTL_10_B_TE (0xfffUL<<19) + #define RPM_RC_CNTL_10_OFFSET_XI (0xffUL<<0) + #define RPM_RC_CNTL_10_CLASS_XI (0x7UL<<8) + #define RPM_RC_CNTL_10_PRIORITY_XI (1UL<<11) + #define RPM_RC_CNTL_10_P4_XI (1UL<<12) + #define RPM_RC_CNTL_10_HDR_TYPE_XI (0x7UL<<13) + #define RPM_RC_CNTL_10_HDR_TYPE_START_XI (0UL<<13) + #define RPM_RC_CNTL_10_HDR_TYPE_IP_XI (1UL<<13) + #define RPM_RC_CNTL_10_HDR_TYPE_TCP_XI (2UL<<13) + #define RPM_RC_CNTL_10_HDR_TYPE_UDP_XI (3UL<<13) + #define RPM_RC_CNTL_10_HDR_TYPE_DATA_XI (4UL<<13) + #define RPM_RC_CNTL_10_HDR_TYPE_TCP_UDP_XI (5UL<<13) + #define RPM_RC_CNTL_10_HDR_TYPE_ICMPV6_XI (6UL<<13) + #define RPM_RC_CNTL_10_COMP_XI (0x3UL<<16) + #define RPM_RC_CNTL_10_COMP_EQUAL_XI (0UL<<16) + #define RPM_RC_CNTL_10_COMP_NEQUAL_XI (1UL<<16) + #define RPM_RC_CNTL_10_COMP_GREATER_XI (2UL<<16) + #define RPM_RC_CNTL_10_COMP_LESS_XI (3UL<<16) + #define RPM_RC_CNTL_10_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_10_SBIT_XI (1UL<<19) + #define RPM_RC_CNTL_10_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_10_DISCARD_XI (1UL<<25) + #define RPM_RC_CNTL_10_MASK_XI (1UL<<26) + #define RPM_RC_CNTL_10_P1_XI (1UL<<27) + #define RPM_RC_CNTL_10_P2_XI (1UL<<28) + #define RPM_RC_CNTL_10_P3_XI (1UL<<29) + #define RPM_RC_CNTL_10_NBIT_XI (1UL<<30) + + u32_t rpm_rc_value_mask_10; + #define RPM_RC_VALUE_MASK_10_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_10_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_11; + #define RPM_RC_CNTL_11_A_TE (0x3ffffUL<<0) + #define RPM_RC_CNTL_11_B_TE (0xfffUL<<19) + #define RPM_RC_CNTL_11_OFFSET_XI (0xffUL<<0) + #define RPM_RC_CNTL_11_CLASS_XI (0x7UL<<8) + #define RPM_RC_CNTL_11_PRIORITY_XI (1UL<<11) + #define RPM_RC_CNTL_11_P4_XI (1UL<<12) + #define RPM_RC_CNTL_11_HDR_TYPE_XI (0x7UL<<13) + #define RPM_RC_CNTL_11_HDR_TYPE_START_XI (0UL<<13) + #define RPM_RC_CNTL_11_HDR_TYPE_IP_XI (1UL<<13) + #define RPM_RC_CNTL_11_HDR_TYPE_TCP_XI (2UL<<13) + #define RPM_RC_CNTL_11_HDR_TYPE_UDP_XI (3UL<<13) + #define RPM_RC_CNTL_11_HDR_TYPE_DATA_XI (4UL<<13) + #define RPM_RC_CNTL_11_HDR_TYPE_TCP_UDP_XI (5UL<<13) + #define RPM_RC_CNTL_11_HDR_TYPE_ICMPV6_XI (6UL<<13) + #define RPM_RC_CNTL_11_COMP_XI (0x3UL<<16) + #define RPM_RC_CNTL_11_COMP_EQUAL_XI (0UL<<16) + #define RPM_RC_CNTL_11_COMP_NEQUAL_XI (1UL<<16) + #define RPM_RC_CNTL_11_COMP_GREATER_XI (2UL<<16) + #define RPM_RC_CNTL_11_COMP_LESS_XI (3UL<<16) + #define RPM_RC_CNTL_11_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_11_SBIT_XI (1UL<<19) + #define RPM_RC_CNTL_11_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_11_DISCARD_XI (1UL<<25) + #define RPM_RC_CNTL_11_MASK_XI (1UL<<26) + #define RPM_RC_CNTL_11_P1_XI (1UL<<27) + #define RPM_RC_CNTL_11_P2_XI (1UL<<28) + #define RPM_RC_CNTL_11_P3_XI (1UL<<29) + #define RPM_RC_CNTL_11_NBIT_XI (1UL<<30) + + u32_t rpm_rc_value_mask_11; + #define RPM_RC_VALUE_MASK_11_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_11_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_12; + #define RPM_RC_CNTL_12_A_TE (0x3ffffUL<<0) + #define RPM_RC_CNTL_12_B_TE (0xfffUL<<19) + #define RPM_RC_CNTL_12_OFFSET_XI (0xffUL<<0) + #define RPM_RC_CNTL_12_CLASS_XI (0x7UL<<8) + #define RPM_RC_CNTL_12_PRIORITY_XI (1UL<<11) + #define RPM_RC_CNTL_12_P4_XI (1UL<<12) + #define RPM_RC_CNTL_12_HDR_TYPE_XI (0x7UL<<13) + #define RPM_RC_CNTL_12_HDR_TYPE_START_XI (0UL<<13) + #define RPM_RC_CNTL_12_HDR_TYPE_IP_XI (1UL<<13) + #define RPM_RC_CNTL_12_HDR_TYPE_TCP_XI (2UL<<13) + #define RPM_RC_CNTL_12_HDR_TYPE_UDP_XI (3UL<<13) + #define RPM_RC_CNTL_12_HDR_TYPE_DATA_XI (4UL<<13) + #define RPM_RC_CNTL_12_HDR_TYPE_TCP_UDP_XI (5UL<<13) + #define RPM_RC_CNTL_12_HDR_TYPE_ICMPV6_XI (6UL<<13) + #define RPM_RC_CNTL_12_COMP_XI (0x3UL<<16) + #define RPM_RC_CNTL_12_COMP_EQUAL_XI (0UL<<16) + #define RPM_RC_CNTL_12_COMP_NEQUAL_XI (1UL<<16) + #define RPM_RC_CNTL_12_COMP_GREATER_XI (2UL<<16) + #define RPM_RC_CNTL_12_COMP_LESS_XI (3UL<<16) + #define RPM_RC_CNTL_12_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_12_SBIT_XI (1UL<<19) + #define RPM_RC_CNTL_12_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_12_DISCARD_XI (1UL<<25) + #define RPM_RC_CNTL_12_MASK_XI (1UL<<26) + #define RPM_RC_CNTL_12_P1_XI (1UL<<27) + #define RPM_RC_CNTL_12_P2_XI (1UL<<28) + #define RPM_RC_CNTL_12_P3_XI (1UL<<29) + #define RPM_RC_CNTL_12_NBIT_XI (1UL<<30) + + u32_t rpm_rc_value_mask_12; + #define RPM_RC_VALUE_MASK_12_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_12_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_13; + #define RPM_RC_CNTL_13_A_TE (0x3ffffUL<<0) + #define RPM_RC_CNTL_13_B_TE (0xfffUL<<19) + #define RPM_RC_CNTL_13_OFFSET_XI (0xffUL<<0) + #define RPM_RC_CNTL_13_CLASS_XI (0x7UL<<8) + #define RPM_RC_CNTL_13_PRIORITY_XI (1UL<<11) + #define RPM_RC_CNTL_13_P4_XI (1UL<<12) + #define RPM_RC_CNTL_13_HDR_TYPE_XI (0x7UL<<13) + #define RPM_RC_CNTL_13_HDR_TYPE_START_XI (0UL<<13) + #define RPM_RC_CNTL_13_HDR_TYPE_IP_XI (1UL<<13) + #define RPM_RC_CNTL_13_HDR_TYPE_TCP_XI (2UL<<13) + #define RPM_RC_CNTL_13_HDR_TYPE_UDP_XI (3UL<<13) + #define RPM_RC_CNTL_13_HDR_TYPE_DATA_XI (4UL<<13) + #define RPM_RC_CNTL_13_HDR_TYPE_TCP_UDP_XI (5UL<<13) + #define RPM_RC_CNTL_13_HDR_TYPE_ICMPV6_XI (6UL<<13) + #define RPM_RC_CNTL_13_COMP_XI (0x3UL<<16) + #define RPM_RC_CNTL_13_COMP_EQUAL_XI (0UL<<16) + #define RPM_RC_CNTL_13_COMP_NEQUAL_XI (1UL<<16) + #define RPM_RC_CNTL_13_COMP_GREATER_XI (2UL<<16) + #define RPM_RC_CNTL_13_COMP_LESS_XI (3UL<<16) + #define RPM_RC_CNTL_13_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_13_SBIT_XI (1UL<<19) + #define RPM_RC_CNTL_13_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_13_DISCARD_XI (1UL<<25) + #define RPM_RC_CNTL_13_MASK_XI (1UL<<26) + #define RPM_RC_CNTL_13_P1_XI (1UL<<27) + #define RPM_RC_CNTL_13_P2_XI (1UL<<28) + #define RPM_RC_CNTL_13_P3_XI (1UL<<29) + #define RPM_RC_CNTL_13_NBIT_XI (1UL<<30) + + u32_t rpm_rc_value_mask_13; + #define RPM_RC_VALUE_MASK_13_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_13_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_14; + #define RPM_RC_CNTL_14_A_TE (0x3ffffUL<<0) + #define RPM_RC_CNTL_14_B_TE (0xfffUL<<19) + #define RPM_RC_CNTL_14_OFFSET_XI (0xffUL<<0) + #define RPM_RC_CNTL_14_CLASS_XI (0x7UL<<8) + #define RPM_RC_CNTL_14_PRIORITY_XI (1UL<<11) + #define RPM_RC_CNTL_14_P4_XI (1UL<<12) + #define RPM_RC_CNTL_14_HDR_TYPE_XI (0x7UL<<13) + #define RPM_RC_CNTL_14_HDR_TYPE_START_XI (0UL<<13) + #define RPM_RC_CNTL_14_HDR_TYPE_IP_XI (1UL<<13) + #define RPM_RC_CNTL_14_HDR_TYPE_TCP_XI (2UL<<13) + #define RPM_RC_CNTL_14_HDR_TYPE_UDP_XI (3UL<<13) + #define RPM_RC_CNTL_14_HDR_TYPE_DATA_XI (4UL<<13) + #define RPM_RC_CNTL_14_HDR_TYPE_TCP_UDP_XI (5UL<<13) + #define RPM_RC_CNTL_14_HDR_TYPE_ICMPV6_XI (6UL<<13) + #define RPM_RC_CNTL_14_COMP_XI (0x3UL<<16) + #define RPM_RC_CNTL_14_COMP_EQUAL_XI (0UL<<16) + #define RPM_RC_CNTL_14_COMP_NEQUAL_XI (1UL<<16) + #define RPM_RC_CNTL_14_COMP_GREATER_XI (2UL<<16) + #define RPM_RC_CNTL_14_COMP_LESS_XI (3UL<<16) + #define RPM_RC_CNTL_14_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_14_SBIT_XI (1UL<<19) + #define RPM_RC_CNTL_14_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_14_DISCARD_XI (1UL<<25) + #define RPM_RC_CNTL_14_MASK_XI (1UL<<26) + #define RPM_RC_CNTL_14_P1_XI (1UL<<27) + #define RPM_RC_CNTL_14_P2_XI (1UL<<28) + #define RPM_RC_CNTL_14_P3_XI (1UL<<29) + #define RPM_RC_CNTL_14_NBIT_XI (1UL<<30) + + u32_t rpm_rc_value_mask_14; + #define RPM_RC_VALUE_MASK_14_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_14_MASK (0xffffUL<<16) + + u32_t rpm_rc_cntl_15; + #define RPM_RC_CNTL_15_A_TE (0x3ffffUL<<0) + #define RPM_RC_CNTL_15_B_TE (0xfffUL<<19) + #define RPM_RC_CNTL_15_OFFSET_XI (0xffUL<<0) + #define RPM_RC_CNTL_15_CLASS_XI (0x7UL<<8) + #define RPM_RC_CNTL_15_PRIORITY_XI (1UL<<11) + #define RPM_RC_CNTL_15_P4_XI (1UL<<12) + #define RPM_RC_CNTL_15_HDR_TYPE_XI (0x7UL<<13) + #define RPM_RC_CNTL_15_HDR_TYPE_START_XI (0UL<<13) + #define RPM_RC_CNTL_15_HDR_TYPE_IP_XI (1UL<<13) + #define RPM_RC_CNTL_15_HDR_TYPE_TCP_XI (2UL<<13) + #define RPM_RC_CNTL_15_HDR_TYPE_UDP_XI (3UL<<13) + #define RPM_RC_CNTL_15_HDR_TYPE_DATA_XI (4UL<<13) + #define RPM_RC_CNTL_15_HDR_TYPE_TCP_UDP_XI (5UL<<13) + #define RPM_RC_CNTL_15_HDR_TYPE_ICMPV6_XI (6UL<<13) + #define RPM_RC_CNTL_15_COMP_XI (0x3UL<<16) + #define RPM_RC_CNTL_15_COMP_EQUAL_XI (0UL<<16) + #define RPM_RC_CNTL_15_COMP_NEQUAL_XI (1UL<<16) + #define RPM_RC_CNTL_15_COMP_GREATER_XI (2UL<<16) + #define RPM_RC_CNTL_15_COMP_LESS_XI (3UL<<16) + #define RPM_RC_CNTL_15_MAP_XI (1UL<<18) + #define RPM_RC_CNTL_15_SBIT_XI (1UL<<19) + #define RPM_RC_CNTL_15_CMDSEL_XI (0x1fUL<<20) + #define RPM_RC_CNTL_15_DISCARD_XI (1UL<<25) + #define RPM_RC_CNTL_15_MASK_XI (1UL<<26) + #define RPM_RC_CNTL_15_P1_XI (1UL<<27) + #define RPM_RC_CNTL_15_P2_XI (1UL<<28) + #define RPM_RC_CNTL_15_P3_XI (1UL<<29) + #define RPM_RC_CNTL_15_NBIT_XI (1UL<<30) + + u32_t rpm_rc_value_mask_15; + #define RPM_RC_VALUE_MASK_15_VALUE (0xffffUL<<0) + #define RPM_RC_VALUE_MASK_15_MASK (0xffffUL<<16) + + u32_t rpm_rc_config; + #define RPM_RC_CONFIG_RULE_ENABLE_TE (0xffffUL<<0) + #define RPM_RC_CONFIG_RULE_ENABLE_XI (0xfffffUL<<0) + #define RPM_RC_CONFIG_DEF_CLASS (0x7UL<<24) + #define RPM_RC_CONFIG_KNUM_OVERWRITE (1UL<<31) + + u32_t rpm_debug0; + #define RPM_DEBUG0_FM_BCNT (0xffffUL<<0) + #define RPM_DEBUG0_T_DATA_OFST_VLD (1UL<<16) + #define RPM_DEBUG0_T_UDP_OFST_VLD (1UL<<17) + #define RPM_DEBUG0_T_TCP_OFST_VLD (1UL<<18) + #define RPM_DEBUG0_T_IP_OFST_VLD (1UL<<19) + #define RPM_DEBUG0_IP_MORE_FRGMT (1UL<<20) + #define RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1UL<<21) + #define RPM_DEBUG0_LLC_SNAP (1UL<<22) + #define RPM_DEBUG0_FM_STARTED (1UL<<23) + #define RPM_DEBUG0_DONE (1UL<<24) + #define RPM_DEBUG0_WAIT_4_DONE (1UL<<25) + #define RPM_DEBUG0_USE_TPBUF_CKSUM (1UL<<26) + #define RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1UL<<27) + #define RPM_DEBUG0_IGNORE_VLAN (1UL<<28) + #define RPM_DEBUG0_RP_ENA_ACTIVE (1UL<<31) + + u32_t rpm_debug1; + #define RPM_DEBUG1_FSM_CUR_ST (0xffffUL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_IDLE (0UL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1UL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2UL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4UL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8UL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_IP_START (16UL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_IP (32UL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_TCP (64UL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_UDP (128UL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_AH (256UL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_ESP (512UL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024UL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_DATA (2048UL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (8192UL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (16384UL<<0) + #define RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (32768UL<<0) + #define RPM_DEBUG1_HDR_BCNT (0x7ffUL<<16) + #define RPM_DEBUG1_UNKNOWN_ETYPE_D (1UL<<28) + #define RPM_DEBUG1_VLAN_REMOVED_D2 (1UL<<29) + #define RPM_DEBUG1_VLAN_REMOVED_D1 (1UL<<30) + #define RPM_DEBUG1_EOF_0XTRA_WD (1UL<<31) + + u32_t rpm_debug2; + #define RPM_DEBUG2_CMD_HIT_VEC (0xffffUL<<0) + #define RPM_DEBUG2_IP_BCNT (0xffUL<<16) + #define RPM_DEBUG2_THIS_CMD_M4 (1UL<<24) + #define RPM_DEBUG2_THIS_CMD_M3 (1UL<<25) + #define RPM_DEBUG2_THIS_CMD_M2 (1UL<<26) + #define RPM_DEBUG2_THIS_CMD_M1 (1UL<<27) + #define RPM_DEBUG2_IPIPE_EMPTY (1UL<<28) + #define RPM_DEBUG2_FM_DISCARD (1UL<<29) + #define RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1UL<<30) + #define RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1UL<<31) + + u32_t rpm_debug3; + #define RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffUL<<0) + #define RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1UL<<9) + #define RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1UL<<10) + #define RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1UL<<11) + #define RPM_DEBUG3_RDE_RBUF_FREE_REQ (1UL<<12) + #define RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1UL<<13) + #define RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1UL<<14) + #define RPM_DEBUG3_RBUF_RDE_SOF_DROP (1UL<<15) + #define RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfUL<<16) + #define RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1UL<<21) + #define RPM_DEBUG3_DROP_NXT_VLD (1UL<<22) + #define RPM_DEBUG3_DROP_NXT (1UL<<23) + #define RPM_DEBUG3_FTQ_FSM (0x3UL<<24) + #define RPM_DEBUG3_FTQ_FSM_IDLE (0UL<<24) + #define RPM_DEBUG3_FTQ_FSM_WAIT_ACK (1UL<<24) + #define RPM_DEBUG3_FTQ_FSM_WAIT_FREE (2UL<<24) + #define RPM_DEBUG3_MBWRITE_FSM (0x3UL<<26) + #define RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0UL<<26) + #define RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (1UL<<26) + #define RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (2UL<<26) + #define RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (3UL<<26) + #define RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (4UL<<26) + #define RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (5UL<<26) + #define RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (6UL<<26) + #define RPM_DEBUG3_MBWRITE_FSM_DONE (7UL<<26) + #define RPM_DEBUG3_MBFREE_FSM (1UL<<29) + #define RPM_DEBUG3_MBFREE_FSM_IDLE (0UL<<29) + #define RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1UL<<29) + #define RPM_DEBUG3_MBALLOC_FSM (1UL<<30) + #define RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0UL<<30) + #define RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (1UL<<30) + #define RPM_DEBUG3_CCODE_EOF_ERROR (1UL<<31) + + u32_t rpm_debug4; + #define RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffUL<<0) + #define RPM_DEBUG4_DFIFO_CUR_CCODE (0x7UL<<25) + #define RPM_DEBUG4_MBWRITE_FSM (0x7UL<<28) + #define RPM_DEBUG4_DFIFO_EMPTY (1UL<<31) + + u32_t rpm_debug5; + #define RPM_DEBUG5_RDROP_WPTR (0x1fUL<<0) + #define RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fUL<<5) + #define RPM_DEBUG5_RDROP_MC_RPTR (0x1fUL<<10) + #define RPM_DEBUG5_RDROP_RC_RPTR (0x1fUL<<15) + #define RPM_DEBUG5_RDROP_ACPI_EMPTY (1UL<<20) + #define RPM_DEBUG5_RDROP_MC_EMPTY (1UL<<21) + #define RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1UL<<22) + #define RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1UL<<23) + #define RPM_DEBUG5_HOLDREG_DISCARD (1UL<<24) + #define RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1UL<<25) + #define RPM_DEBUG5_HOLDREG_MC_EMPTY (1UL<<26) + #define RPM_DEBUG5_HOLDREG_RC_EMPTY (1UL<<27) + #define RPM_DEBUG5_HOLDREG_FC_EMPTY (1UL<<28) + #define RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1UL<<29) + #define RPM_DEBUG5_HOLDREG_FULL_T (1UL<<30) + #define RPM_DEBUG5_HOLDREG_RD (1UL<<31) + + u32_t rpm_debug6; + #define RPM_DEBUG6_ACPI_VEC (0xffffUL<<0) + #define RPM_DEBUG6_VEC (0xffffUL<<16) + + u32_t rpm_debug7; + #define RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffUL<<0) + + u32_t rpm_debug8; + #define RPM_DEBUG8_PS_ACPI_FSM (0xfUL<<0) + #define RPM_DEBUG8_PS_ACPI_FSM_IDLE (0UL<<0) + #define RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1UL<<0) + #define RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2UL<<0) + #define RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3UL<<0) + #define RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4UL<<0) + #define RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5UL<<0) + #define RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6UL<<0) + #define RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7UL<<0) + #define RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8UL<<0) + #define RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9UL<<0) + #define RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10UL<<0) + #define RPM_DEBUG8_COMPARE_AT_W0 (1UL<<4) + #define RPM_DEBUG8_COMPARE_AT_W3_DATA (1UL<<5) + #define RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1UL<<6) + #define RPM_DEBUG8_COMPARE_AT_SOF_W3 (1UL<<7) + #define RPM_DEBUG8_COMPARE_AT_SOF_W2 (1UL<<8) + #define RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1UL<<9) + #define RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1UL<<10) + #define RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1UL<<11) + #define RPM_DEBUG8_EOF_DET (1UL<<12) + #define RPM_DEBUG8_SOF_DET (1UL<<13) + #define RPM_DEBUG8_WAIT_4_SOF (1UL<<14) + #define RPM_DEBUG8_ALL_DONE (1UL<<15) + #define RPM_DEBUG8_THBUF_ADDR (0x7fUL<<16) + #define RPM_DEBUG8_BYTE_CTR (0xffUL<<24) + + u32_t rpm_debug9; + #define RPM_DEBUG9_OUTFIFO_COUNT_TE (0x7UL<<0) + #define RPM_DEBUG9_RDE_ACPI_RDY_TE (1UL<<3) + #define RPM_DEBUG9_VLD_RD_ENTRY_CT_TE (0x7UL<<4) + #define RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED_TE (1UL<<28) + #define RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED_TE (1UL<<29) + #define RPM_DEBUG9_ACPI_MATCH_INT_TE (1UL<<30) + #define RPM_DEBUG9_ACPI_ENABLE_SYN_TE (1UL<<31) + #define RPM_DEBUG9_BEMEM_R_XI (0x1fUL<<0) + #define RPM_DEBUG9_EO_XI (1UL<<5) + #define RPM_DEBUG9_AEOF_DE_XI (1UL<<6) + #define RPM_DEBUG9_SO_XI (1UL<<7) + #define RPM_DEBUG9_WD64_CT_XI (0x1fUL<<8) + #define RPM_DEBUG9_EOF_VLDBYTE_XI (0x7UL<<13) + #define RPM_DEBUG9_ACPI_RDE_PAT_ID_XI (0xfUL<<16) + #define RPM_DEBUG9_CALCRC_RESULT_XI (0x3ffUL<<20) + #define RPM_DEBUG9_DATA_IN_VL_XI (1UL<<30) + #define RPM_DEBUG9_CALCRC_BUFFER_VLD_XI (1UL<<31) + + u32_t unused_3[5]; + u32_t rpm_acpi_dbg_buf_w0[4]; + u32_t rpm_acpi_dbg_buf_w1[4]; + u32_t rpm_acpi_dbg_buf_w2[4]; + u32_t rpm_acpi_dbg_buf_w3[4]; + u32_t rpm_acpi_byte_enable_ctrl; + #define RPM_ACPI_BYTE_ENABLE_CTRL_BYTE_ADDRESS (0xffffUL<<0) + #define RPM_ACPI_BYTE_ENABLE_CTRL_DEBUGRD (1UL<<28) + #define RPM_ACPI_BYTE_ENABLE_CTRL_MODE (1UL<<29) + #define RPM_ACPI_BYTE_ENABLE_CTRL_INIT (1UL<<30) + #define RPM_ACPI_BYTE_ENABLE_CTRL_WR (1UL<<31) + + u32_t rpm_acpi_pattern_ctrl; + #define RPM_ACPI_PATTERN_CTRL_PATTERN_ID (0xfUL<<0) + #define RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR (1UL<<30) + #define RPM_ACPI_PATTERN_CTRL_WR (1UL<<31) + + u32_t rpm_acpi_data; + #define RPM_ACPI_DATA_PATTERN_BE (0xffffffffUL<<0) + + u32_t rpm_acpi_pattern_len0; + #define RPM_ACPI_PATTERN_LEN0_PATTERN_LEN3 (0xffUL<<0) + #define RPM_ACPI_PATTERN_LEN0_PATTERN_LEN2 (0xffUL<<8) + #define RPM_ACPI_PATTERN_LEN0_PATTERN_LEN1 (0xffUL<<16) + #define RPM_ACPI_PATTERN_LEN0_PATTERN_LEN0 (0xffUL<<24) + + u32_t rpm_acpi_pattern_len1; + #define RPM_ACPI_PATTERN_LEN1_PATTERN_LEN7 (0xffUL<<0) + #define RPM_ACPI_PATTERN_LEN1_PATTERN_LEN6 (0xffUL<<8) + #define RPM_ACPI_PATTERN_LEN1_PATTERN_LEN5 (0xffUL<<16) + #define RPM_ACPI_PATTERN_LEN1_PATTERN_LEN4 (0xffUL<<24) + + u32_t unused_4; + u32_t rpm_acpi_pattern_crc0; + #define RPM_ACPI_PATTERN_CRC0_PATTERN_CRC0 (0xffffffffUL<<0) + + u32_t rpm_acpi_pattern_crc1; + #define RPM_ACPI_PATTERN_CRC1_PATTERN_CRC1 (0xffffffffUL<<0) + + u32_t rpm_acpi_pattern_crc2; + #define RPM_ACPI_PATTERN_CRC2_PATTERN_CRC2 (0xffffffffUL<<0) + + u32_t rpm_acpi_pattern_crc3; + #define RPM_ACPI_PATTERN_CRC3_PATTERN_CRC3 (0xffffffffUL<<0) + + u32_t rpm_acpi_pattern_crc4; + #define RPM_ACPI_PATTERN_CRC4_PATTERN_CRC4 (0xffffffffUL<<0) + + u32_t rpm_acpi_pattern_crc5; + #define RPM_ACPI_PATTERN_CRC5_PATTERN_CRC5 (0xffffffffUL<<0) + + u32_t rpm_acpi_pattern_crc6; + #define RPM_ACPI_PATTERN_CRC6_PATTERN_CRC6 (0xffffffffUL<<0) + + u32_t rpm_acpi_pattern_crc7; + #define RPM_ACPI_PATTERN_CRC7_PATTERN_CRC7 (0xffffffffUL<<0) + + u32_t unused_5[114]; +} rpm_reg_t; + +typedef rpm_reg_t rx_parser_reg_t; + +/* + * rpc_reg definition + * offset: 0x1c00 + */ +typedef struct rpc_reg +{ + u32_t rpc_command; + #define RPC_COMMAND_ENABLED (1UL<<0) + #define RPC_COMMAND_OVERRUN_ABORT (1UL<<4) + + u32_t rpc_status; + #define RPC_STATUS_MBUF_WAIT (1UL<<0) + #define RPC_STATUS_FREE_WAIT (1UL<<1) + + u32_t rpc_config; + #define RPC_CONFIG_NO_PSD_HDR_CKSUM (1UL<<0) + #define RPC_CONFIG_SORT_VECT_VAL (0xfUL<<4) + #define RPC_CONFIG_IGNORE_VLAN (1UL<<31) + + u32_t unused_0[13]; + u32_t rpc_stat_l2_filter_discards; + u32_t rpc_stat_rule_checker_discards; + u32_t rpc_stat_ifinftqdiscards; + u32_t rpc_stat_ifinmbufdiscard; + u32_t rpc_stat_rule_checker_p4_hit; + u32_t rpc_ipv6_programmable_extension0; + #define RPC_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN (0xffUL<<0) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER (0xffUL<<16) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN (1UL<<31) + + u32_t rpc_ipv6_programmable_extension1; + #define RPC_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN (0xffUL<<0) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER (0xffUL<<16) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN (1UL<<31) + + u32_t rpc_ipv6_programmable_extension2; + #define RPC_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN (0xffUL<<0) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER (0xffUL<<16) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN (1UL<<31) + + u32_t rpc_ipv6_programmable_extension3; + #define RPC_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN (0xffUL<<0) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER (0xffUL<<16) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN (1UL<<31) + + u32_t rpc_ipv6_programmable_extension4; + #define RPC_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN (0xffUL<<0) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER (0xffUL<<16) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN (1UL<<31) + + u32_t rpc_ipv6_programmable_extension5; + #define RPC_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN (0xffUL<<0) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER (0xffUL<<16) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN (1UL<<31) + + u32_t rpc_ipv6_programmable_extension6; + #define RPC_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN (0xffUL<<0) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER (0xffUL<<16) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN (1UL<<31) + + u32_t rpc_ipv6_programmable_extension7; + #define RPC_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN (0xffUL<<0) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER (0xffUL<<16) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define RPC_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN (1UL<<31) + + u32_t unused_1[3]; + u32_t rpc_stat_ac[5]; + u32_t unused_2[27]; + u32_t rpc_rc_cntl_0; + #define RPC_RC_CNTL_0_OFFSET (0xffUL<<0) + #define RPC_RC_CNTL_0_CLASS (0x7UL<<8) + #define RPC_RC_CNTL_0_PRIORITY (1UL<<11) + #define RPC_RC_CNTL_0_P4 (1UL<<12) + #define RPC_RC_CNTL_0_HDR_TYPE (0x7UL<<13) + #define RPC_RC_CNTL_0_HDR_TYPE_START (0UL<<13) + #define RPC_RC_CNTL_0_HDR_TYPE_IP (1UL<<13) + #define RPC_RC_CNTL_0_HDR_TYPE_TCP (2UL<<13) + #define RPC_RC_CNTL_0_HDR_TYPE_UDP (3UL<<13) + #define RPC_RC_CNTL_0_HDR_TYPE_DATA (4UL<<13) + #define RPC_RC_CNTL_0_COMP (0x3UL<<16) + #define RPC_RC_CNTL_0_COMP_EQUAL (0UL<<16) + #define RPC_RC_CNTL_0_COMP_NEQUAL (1UL<<16) + #define RPC_RC_CNTL_0_COMP_GREATER (2UL<<16) + #define RPC_RC_CNTL_0_COMP_LESS (3UL<<16) + #define RPC_RC_CNTL_0_MAP_XI (1UL<<18) + #define RPC_RC_CNTL_0_SBIT (1UL<<19) + #define RPC_RC_CNTL_0_CMDSEL_TE (0xfUL<<20) + #define RPC_RC_CNTL_0_MAP_TE (1UL<<24) + #define RPC_RC_CNTL_0_CMDSEL_XI (0x1fUL<<20) + #define RPC_RC_CNTL_0_DISCARD (1UL<<25) + #define RPC_RC_CNTL_0_MASK (1UL<<26) + #define RPC_RC_CNTL_0_P1 (1UL<<27) + #define RPC_RC_CNTL_0_P2 (1UL<<28) + #define RPC_RC_CNTL_0_P3 (1UL<<29) + #define RPC_RC_CNTL_0_NBIT (1UL<<30) + + u32_t rpc_rc_value_mask_0; + #define RPC_RC_VALUE_MASK_0_VALUE (0xffffUL<<0) + #define RPC_RC_VALUE_MASK_0_MASK (0xffffUL<<16) + + u32_t rpc_rc_cntl_1; + #define RPC_RC_CNTL_1_A_TE (0x3ffffUL<<0) + #define RPC_RC_CNTL_1_B_TE (0xfffUL<<19) + #define RPC_RC_CNTL_1_OFFSET_XI (0xffUL<<0) + #define RPC_RC_CNTL_1_CLASS_XI (0x7UL<<8) + #define RPC_RC_CNTL_1_PRIORITY_XI (1UL<<11) + #define RPC_RC_CNTL_1_P4_XI (1UL<<12) + #define RPC_RC_CNTL_1_HDR_TYPE_XI (0x7UL<<13) + #define RPC_RC_CNTL_1_HDR_TYPE_START_XI (0UL<<13) + #define RPC_RC_CNTL_1_HDR_TYPE_IP_XI (1UL<<13) + #define RPC_RC_CNTL_1_HDR_TYPE_TCP_XI (2UL<<13) + #define RPC_RC_CNTL_1_HDR_TYPE_UDP_XI (3UL<<13) + #define RPC_RC_CNTL_1_HDR_TYPE_DATA_XI (4UL<<13) + #define RPC_RC_CNTL_1_COMP_XI (0x3UL<<16) + #define RPC_RC_CNTL_1_COMP_EQUAL_XI (0UL<<16) + #define RPC_RC_CNTL_1_COMP_NEQUAL_XI (1UL<<16) + #define RPC_RC_CNTL_1_COMP_GREATER_XI (2UL<<16) + #define RPC_RC_CNTL_1_COMP_LESS_XI (3UL<<16) + #define RPC_RC_CNTL_1_MAP_XI (1UL<<18) + #define RPC_RC_CNTL_1_SBIT_XI (1UL<<19) + #define RPC_RC_CNTL_1_CMDSEL_XI (0x1fUL<<20) + #define RPC_RC_CNTL_1_DISCARD_XI (1UL<<25) + #define RPC_RC_CNTL_1_MASK_XI (1UL<<26) + #define RPC_RC_CNTL_1_P1_XI (1UL<<27) + #define RPC_RC_CNTL_1_P2_XI (1UL<<28) + #define RPC_RC_CNTL_1_P3_XI (1UL<<29) + #define RPC_RC_CNTL_1_NBIT_XI (1UL<<30) + + u32_t rpc_rc_value_mask_1; + #define RPC_RC_VALUE_MASK_1_VALUE (0xffffUL<<0) + #define RPC_RC_VALUE_MASK_1_MASK (0xffffUL<<16) + + u32_t rpc_rc_cntl_2; + #define RPC_RC_CNTL_2_A_TE (0x3ffffUL<<0) + #define RPC_RC_CNTL_2_B_TE (0xfffUL<<19) + #define RPC_RC_CNTL_2_OFFSET_XI (0xffUL<<0) + #define RPC_RC_CNTL_2_CLASS_XI (0x7UL<<8) + #define RPC_RC_CNTL_2_PRIORITY_XI (1UL<<11) + #define RPC_RC_CNTL_2_P4_XI (1UL<<12) + #define RPC_RC_CNTL_2_HDR_TYPE_XI (0x7UL<<13) + #define RPC_RC_CNTL_2_HDR_TYPE_START_XI (0UL<<13) + #define RPC_RC_CNTL_2_HDR_TYPE_IP_XI (1UL<<13) + #define RPC_RC_CNTL_2_HDR_TYPE_TCP_XI (2UL<<13) + #define RPC_RC_CNTL_2_HDR_TYPE_UDP_XI (3UL<<13) + #define RPC_RC_CNTL_2_HDR_TYPE_DATA_XI (4UL<<13) + #define RPC_RC_CNTL_2_COMP_XI (0x3UL<<16) + #define RPC_RC_CNTL_2_COMP_EQUAL_XI (0UL<<16) + #define RPC_RC_CNTL_2_COMP_NEQUAL_XI (1UL<<16) + #define RPC_RC_CNTL_2_COMP_GREATER_XI (2UL<<16) + #define RPC_RC_CNTL_2_COMP_LESS_XI (3UL<<16) + #define RPC_RC_CNTL_2_MAP_XI (1UL<<18) + #define RPC_RC_CNTL_2_SBIT_XI (1UL<<19) + #define RPC_RC_CNTL_2_CMDSEL_XI (0x1fUL<<20) + #define RPC_RC_CNTL_2_DISCARD_XI (1UL<<25) + #define RPC_RC_CNTL_2_MASK_XI (1UL<<26) + #define RPC_RC_CNTL_2_P1_XI (1UL<<27) + #define RPC_RC_CNTL_2_P2_XI (1UL<<28) + #define RPC_RC_CNTL_2_P3_XI (1UL<<29) + #define RPC_RC_CNTL_2_NBIT_XI (1UL<<30) + + u32_t rpc_rc_value_mask_2; + #define RPC_RC_VALUE_MASK_2_VALUE (0xffffUL<<0) + #define RPC_RC_VALUE_MASK_2_MASK (0xffffUL<<16) + + u32_t rpc_rc_cntl_3; + #define RPC_RC_CNTL_3_A_TE (0x3ffffUL<<0) + #define RPC_RC_CNTL_3_B_TE (0xfffUL<<19) + #define RPC_RC_CNTL_3_OFFSET_XI (0xffUL<<0) + #define RPC_RC_CNTL_3_CLASS_XI (0x7UL<<8) + #define RPC_RC_CNTL_3_PRIORITY_XI (1UL<<11) + #define RPC_RC_CNTL_3_P4_XI (1UL<<12) + #define RPC_RC_CNTL_3_HDR_TYPE_XI (0x7UL<<13) + #define RPC_RC_CNTL_3_HDR_TYPE_START_XI (0UL<<13) + #define RPC_RC_CNTL_3_HDR_TYPE_IP_XI (1UL<<13) + #define RPC_RC_CNTL_3_HDR_TYPE_TCP_XI (2UL<<13) + #define RPC_RC_CNTL_3_HDR_TYPE_UDP_XI (3UL<<13) + #define RPC_RC_CNTL_3_HDR_TYPE_DATA_XI (4UL<<13) + #define RPC_RC_CNTL_3_COMP_XI (0x3UL<<16) + #define RPC_RC_CNTL_3_COMP_EQUAL_XI (0UL<<16) + #define RPC_RC_CNTL_3_COMP_NEQUAL_XI (1UL<<16) + #define RPC_RC_CNTL_3_COMP_GREATER_XI (2UL<<16) + #define RPC_RC_CNTL_3_COMP_LESS_XI (3UL<<16) + #define RPC_RC_CNTL_3_MAP_XI (1UL<<18) + #define RPC_RC_CNTL_3_SBIT_XI (1UL<<19) + #define RPC_RC_CNTL_3_CMDSEL_XI (0x1fUL<<20) + #define RPC_RC_CNTL_3_DISCARD_XI (1UL<<25) + #define RPC_RC_CNTL_3_MASK_XI (1UL<<26) + #define RPC_RC_CNTL_3_P1_XI (1UL<<27) + #define RPC_RC_CNTL_3_P2_XI (1UL<<28) + #define RPC_RC_CNTL_3_P3_XI (1UL<<29) + #define RPC_RC_CNTL_3_NBIT_XI (1UL<<30) + + u32_t rpc_rc_value_mask_3; + #define RPC_RC_VALUE_MASK_3_VALUE (0xffffUL<<0) + #define RPC_RC_VALUE_MASK_3_MASK (0xffffUL<<16) + + u32_t rpc_rc_cntl_4; + #define RPC_RC_CNTL_4_A (0x3ffffUL<<0) + #define RPC_RC_CNTL_4_B (0xfffUL<<19) + + u32_t rpc_rc_value_mask_4; + u32_t rpc_rc_cntl_5; + #define RPC_RC_CNTL_5_A (0x3ffffUL<<0) + #define RPC_RC_CNTL_5_B (0xfffUL<<19) + + u32_t rpc_rc_value_mask_5; + u32_t rpc_rc_cntl_6; + #define RPC_RC_CNTL_6_A (0x3ffffUL<<0) + #define RPC_RC_CNTL_6_B (0xfffUL<<19) + + u32_t rpc_rc_value_mask_6; + u32_t rpc_rc_cntl_7; + #define RPC_RC_CNTL_7_A (0x3ffffUL<<0) + #define RPC_RC_CNTL_7_B (0xfffUL<<19) + + u32_t rpc_rc_value_mask_7; + u32_t rpc_rc_cntl_8; + #define RPC_RC_CNTL_8_A (0x3ffffUL<<0) + #define RPC_RC_CNTL_8_B (0xfffUL<<19) + + u32_t rpc_rc_value_mask_8; + u32_t rpc_rc_cntl_9; + #define RPC_RC_CNTL_9_A (0x3ffffUL<<0) + #define RPC_RC_CNTL_9_B (0xfffUL<<19) + + u32_t rpc_rc_value_mask_9; + u32_t rpc_rc_cntl_10; + #define RPC_RC_CNTL_10_A (0x3ffffUL<<0) + #define RPC_RC_CNTL_10_B (0xfffUL<<19) + + u32_t rpc_rc_value_mask_10; + u32_t rpc_rc_cntl_11; + #define RPC_RC_CNTL_11_A (0x3ffffUL<<0) + #define RPC_RC_CNTL_11_B (0xfffUL<<19) + + u32_t rpc_rc_value_mask_11; + u32_t rpc_rc_cntl_12; + #define RPC_RC_CNTL_12_A (0x3ffffUL<<0) + #define RPC_RC_CNTL_12_B (0xfffUL<<19) + + u32_t rpc_rc_value_mask_12; + u32_t rpc_rc_cntl_13; + #define RPC_RC_CNTL_13_A (0x3ffffUL<<0) + #define RPC_RC_CNTL_13_B (0xfffUL<<19) + + u32_t rpc_rc_value_mask_13; + u32_t rpc_rc_cntl_14; + #define RPC_RC_CNTL_14_A (0x3ffffUL<<0) + #define RPC_RC_CNTL_14_B (0xfffUL<<19) + + u32_t rpc_rc_value_mask_14; + u32_t rpc_rc_cntl_15; + #define RPC_RC_CNTL_15_A (0x3ffffUL<<0) + #define RPC_RC_CNTL_15_B (0xfffUL<<19) + + u32_t rpc_rc_value_mask_15; + u32_t rpc_rc_config; + #define RPC_RC_CONFIG_RULE_ENABLE_TE (0xffffUL<<0) + #define RPC_RC_CONFIG_RULE_ENABLE_XI (0xfUL<<0) + #define RPC_RC_CONFIG_DEF_CLASS (0x7UL<<24) + + u32_t rpc_debug0; + #define RPC_DEBUG0_FM_BCNT (0xffffUL<<0) + #define RPC_DEBUG0_T_DATA_OFST_VLD (1UL<<16) + #define RPC_DEBUG0_T_UDP_OFST_VLD (1UL<<17) + #define RPC_DEBUG0_T_TCP_OFST_VLD (1UL<<18) + #define RPC_DEBUG0_T_IP_OFST_VLD (1UL<<19) + #define RPC_DEBUG0_IP_MORE_FRGMT (1UL<<20) + #define RPC_DEBUG0_T_IP_NO_TCP_UDP_HDR (1UL<<21) + #define RPC_DEBUG0_LLC_SNAP (1UL<<22) + #define RPC_DEBUG0_FM_STARTED (1UL<<23) + #define RPC_DEBUG0_DONE (1UL<<24) + #define RPC_DEBUG0_WAIT_4_DONE (1UL<<25) + #define RPC_DEBUG0_USE_TPBUF_CKSUM (1UL<<26) + #define RPC_DEBUG0_RX_NO_PSD_HDR_CKSUM (1UL<<27) + #define RPC_DEBUG0_IGNORE_VLAN (1UL<<28) + #define RPC_DEBUG0_RP_ENA_ACTIVE (1UL<<31) + + u32_t rpc_debug1; + #define RPC_DEBUG1_FSM_CUR_ST (0xffffUL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_IDLE (0UL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1UL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2UL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4UL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8UL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_IP_START (16UL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_IP (32UL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_TCP (64UL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_UDP (128UL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_AH (256UL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_ESP (512UL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024UL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_DATA (2048UL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_ADD_CARRY (8192UL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (16384UL<<0) + #define RPC_DEBUG1_FSM_CUR_ST_LATCH_RESULT (32768UL<<0) + #define RPC_DEBUG1_HDR_BCNT (0x7ffUL<<16) + #define RPC_DEBUG1_UNKNOWN_ETYPE_D (1UL<<28) + #define RPC_DEBUG1_VLAN_REMOVED_D2 (1UL<<29) + #define RPC_DEBUG1_VLAN_REMOVED_D1 (1UL<<30) + #define RPC_DEBUG1_EOF_0XTRA_WD (1UL<<31) + + u32_t rpc_debug2; + #define RPC_DEBUG2_CMD_HIT_VEC (0xffffUL<<0) + #define RPC_DEBUG2_IP_BCNT (0xffUL<<16) + #define RPC_DEBUG2_THIS_CMD_M4 (1UL<<24) + #define RPC_DEBUG2_THIS_CMD_M3 (1UL<<25) + #define RPC_DEBUG2_THIS_CMD_M2 (1UL<<26) + #define RPC_DEBUG2_THIS_CMD_M1 (1UL<<27) + #define RPC_DEBUG2_IPIPE_EMPTY (1UL<<28) + #define RPC_DEBUG2_FM_DISCARD (1UL<<29) + #define RPC_DEBUG2_LAST_RULE_IN_FM_D2 (1UL<<30) + #define RPC_DEBUG2_LAST_RULE_IN_FM_D1 (1UL<<31) + + u32_t rpc_debug3; + #define RPC_DEBUG3_AVAIL_MBUF_PTR (0x1ffUL<<0) + #define RPC_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1UL<<9) + #define RPC_DEBUG3_RDE_RBUF_WR_LAST_INT (1UL<<10) + #define RPC_DEBUG3_RDE_RBUF_WR_REQ_INT (1UL<<11) + #define RPC_DEBUG3_RDE_RBUF_FREE_REQ (1UL<<12) + #define RPC_DEBUG3_RDE_RBUF_ALLOC_REQ (1UL<<13) + #define RPC_DEBUG3_DFSM_MBUF_NOTAVAIL (1UL<<14) + #define RPC_DEBUG3_RBUF_RDE_SOF_DROP (1UL<<15) + #define RPC_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfUL<<16) + #define RPC_DEBUG3_RDE_SRC_FIFO_ALMFULL (1UL<<21) + #define RPC_DEBUG3_DROP_NXT_VLD (1UL<<22) + #define RPC_DEBUG3_DROP_NXT (1UL<<23) + #define RPC_DEBUG3_FTQ_FSM (0x3UL<<24) + #define RPC_DEBUG3_FTQ_FSM_IDLE (0UL<<24) + #define RPC_DEBUG3_FTQ_FSM_WAIT_ACK (1UL<<24) + #define RPC_DEBUG3_FTQ_FSM_WAIT_FREE (2UL<<24) + #define RPC_DEBUG3_MBWRITE_FSM (0x3UL<<26) + #define RPC_DEBUG3_MBWRITE_FSM_WAIT_SOF (0UL<<26) + #define RPC_DEBUG3_MBWRITE_FSM_GET_MBUF (1UL<<26) + #define RPC_DEBUG3_MBWRITE_FSM_DMA_DATA (2UL<<26) + #define RPC_DEBUG3_MBWRITE_FSM_WAIT_DATA (3UL<<26) + #define RPC_DEBUG3_MBWRITE_FSM_WAIT_EOF (4UL<<26) + #define RPC_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (5UL<<26) + #define RPC_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (6UL<<26) + #define RPC_DEBUG3_MBWRITE_FSM_DONE (7UL<<26) + #define RPC_DEBUG3_MBFREE_FSM (1UL<<29) + #define RPC_DEBUG3_MBFREE_FSM_IDLE (0UL<<29) + #define RPC_DEBUG3_MBFREE_FSM_WAIT_ACK (1UL<<29) + #define RPC_DEBUG3_MBALLOC_FSM (1UL<<30) + #define RPC_DEBUG3_MBALLOC_FSM_ET_MBUF (0UL<<30) + #define RPC_DEBUG3_MBALLOC_FSM_IVE_MBUF (1UL<<30) + #define RPC_DEBUG3_CCODE_EOF_ERROR (1UL<<31) + + u32_t rpc_debug4; + #define RPC_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffUL<<0) + #define RPC_DEBUG4_DFIFO_CUR_CCODE (0x7UL<<25) + #define RPC_DEBUG4_MBWRITE_FSM (0x7UL<<28) + #define RPC_DEBUG4_DFIFO_EMPTY (1UL<<31) + + u32_t rpc_debug5; + #define RPC_DEBUG5_RDROP_WPTR (0x1fUL<<0) + #define RPC_DEBUG5_RDROP_ACPI_RPTR (0x1fUL<<5) + #define RPC_DEBUG5_RDROP_MC_RPTR (0x1fUL<<10) + #define RPC_DEBUG5_RDROP_RC_RPTR (0x1fUL<<15) + #define RPC_DEBUG5_RDROP_ACPI_EMPTY (1UL<<20) + #define RPC_DEBUG5_RDROP_MC_EMPTY (1UL<<21) + #define RPC_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1UL<<22) + #define RPC_DEBUG5_HOLDREG_WOL_DROP_INT (1UL<<23) + #define RPC_DEBUG5_HOLDREG_DISCARD (1UL<<24) + #define RPC_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1UL<<25) + #define RPC_DEBUG5_HOLDREG_MC_EMPTY (1UL<<26) + #define RPC_DEBUG5_HOLDREG_RC_EMPTY (1UL<<27) + #define RPC_DEBUG5_HOLDREG_FC_EMPTY (1UL<<28) + #define RPC_DEBUG5_HOLDREG_ACPI_EMPTY (1UL<<29) + #define RPC_DEBUG5_HOLDREG_FULL_T (1UL<<30) + #define RPC_DEBUG5_HOLDREG_RD (1UL<<31) + + u32_t rpc_debug6; + #define RPC_DEBUG6_ACPI_VEC (0xffffUL<<0) + #define RPC_DEBUG6_VEC (0xffffUL<<16) + + u32_t rpc_debug7; + #define RPC_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffUL<<0) + + u32_t rpc_debug8; + #define RPC_DEBUG8_PS_ACPI_FSM (0xfUL<<0) + #define RPC_DEBUG8_PS_ACPI_FSM_IDLE (0UL<<0) + #define RPC_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1UL<<0) + #define RPC_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2UL<<0) + #define RPC_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3UL<<0) + #define RPC_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4UL<<0) + #define RPC_DEBUG8_PS_ACPI_FSM_W3_DATA (5UL<<0) + #define RPC_DEBUG8_PS_ACPI_FSM_W0_ADDR (6UL<<0) + #define RPC_DEBUG8_PS_ACPI_FSM_W1_ADDR (7UL<<0) + #define RPC_DEBUG8_PS_ACPI_FSM_W2_ADDR (8UL<<0) + #define RPC_DEBUG8_PS_ACPI_FSM_W3_ADDR (9UL<<0) + #define RPC_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10UL<<0) + #define RPC_DEBUG8_COMPARE_AT_W0 (1UL<<4) + #define RPC_DEBUG8_COMPARE_AT_W3_DATA (1UL<<5) + #define RPC_DEBUG8_COMPARE_AT_SOF_WAIT (1UL<<6) + #define RPC_DEBUG8_COMPARE_AT_SOF_W3 (1UL<<7) + #define RPC_DEBUG8_COMPARE_AT_SOF_W2 (1UL<<8) + #define RPC_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1UL<<9) + #define RPC_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1UL<<10) + #define RPC_DEBUG8_NXT_EOF_W_12_VLDBYTES (1UL<<11) + #define RPC_DEBUG8_EOF_DET (1UL<<12) + #define RPC_DEBUG8_SOF_DET (1UL<<13) + #define RPC_DEBUG8_WAIT_4_SOF (1UL<<14) + #define RPC_DEBUG8_ALL_DONE (1UL<<15) + #define RPC_DEBUG8_THBUF_ADDR (0x7fUL<<16) + #define RPC_DEBUG8_BYTE_CTR (0xffUL<<24) + + u32_t rpc_debug9; + #define RPC_DEBUG9_OUTFIFO_COUNT (0x7UL<<0) + #define RPC_DEBUG9_RDE_ACPI_RDY (1UL<<3) + #define RPC_DEBUG9_VLD_RD_ENTRY_CT (0x7UL<<4) + #define RPC_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1UL<<28) + #define RPC_DEBUG9_INFIFO_OVERRUN_OCCURRED (1UL<<29) + #define RPC_DEBUG9_ACPI_MATCH_INT (1UL<<30) + #define RPC_DEBUG9_ACPI_ENABLE_SYN (1UL<<31) + + u32_t unused_3[149]; +} rpc_reg_t; + +typedef rpc_reg_t rx_cu_parser_reg_t; + +/* + * rlupq definition + * offset: 0000 + */ +typedef struct rlupq +{ + u32_t rlupq_ip_destadd0; + u32_t rlupq_ip_destadd1; + u32_t rlupq_ip_destadd2; + u32_t rlupq_ip_destadd3; + u32_t rlupq_wd4; + #define RLUPQ_TCP_SRCPORT (0xffff<<16) + #define RLUPQ_TCP_DSTPORT (0xffff<<0) + + u32_t rlupq_wd5; + #define RLUPQ_CS16 (0xffff<<16) + + u32_t rlupq_wd6; + #define RLUPQ_EXT_STATUS_TCP_SYNC_PRESENT (1<<16) + #define RLUPQ_EXT_STATUS_RLUP_HIT2 (1<<17) + #define RLUPQ_EXT_STATUS_TCP_UDP_XSUM_IS_0 (1<<18) + #define RLUPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT (0x3<<19) + #define RLUPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_00 (0<<19) + #define RLUPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_01 (1<<19) + #define RLUPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_10 (2<<19) + #define RLUPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_11 (3<<19) + #define RLUPQ_EXT_STATUS_ACPI_MATCH (1<<21) + + u32_t unused_0[9]; + u32_t rlupq_bits_errors; + #define RLUPQ_BITS_ERRORS_L2_BAD_CRC (1UL<<1) + #define RLUPQ_BITS_ERRORS_L2_PHY_DECODE (1UL<<2) + #define RLUPQ_BITS_ERRORS_L2_ALIGNMENT (1UL<<3) + #define RLUPQ_BITS_ERRORS_L2_TOO_SHORT (1UL<<4) + #define RLUPQ_BITS_ERRORS_L2_GIANT_FRAME (1UL<<5) + #define RLUPQ_BITS_ERRORS_IP_BAD_LEN (1UL<<6) + #define RLUPQ_BITS_ERRORS_IP_TOO_SHORT (1UL<<7) + #define RLUPQ_BITS_ERRORS_IP_BAD_VERSION (1UL<<8) + #define RLUPQ_BITS_ERRORS_IP_BAD_HLEN (1UL<<9) + #define RLUPQ_BITS_ERRORS_IP_BAD_XSUM (1UL<<10) + #define RLUPQ_BITS_ERRORS_TCP_TOO_SHORT (1UL<<11) + #define RLUPQ_BITS_ERRORS_TCP_BAD_XSUM (1UL<<12) + #define RLUPQ_BITS_ERRORS_TCP_BAD_OFFSET (1UL<<13) + #define RLUPQ_BITS_ERRORS_UDP_BAD_XSUM (1UL<<15) + #define RLUPQ_BITS_ERRORS_IP_BAD_ORDER (1UL<<16) + #define RLUPQ_BITS_ERRORS_IP_HDR_MISMATCH (1UL<<18) + + u32_t rlupq_bits_status; + #define RLUPQ_BITS_STATUS_RULE_CLASS (0x7UL<<0) + #define RLUPQ_BITS_STATUS_RULE_P2 (1UL<<3) + #define RLUPQ_BITS_STATUS_RULE_P3 (1UL<<4) + #define RLUPQ_BITS_STATUS_RULE_P4 (1UL<<5) + #define RLUPQ_BITS_STATUS_L2_VLAN_TAG (1UL<<6) + #define RLUPQ_BITS_STATUS_L2_LLC_SNAP (1UL<<7) + #define RLUPQ_BITS_STATUS_RSS_HASH (1UL<<8) + #define RLUPQ_BITS_STATUS_SORT_VECT (0xfUL<<9) + #define RLUPQ_BITS_STATUS_IP_DATAGRAM (1UL<<13) + #define RLUPQ_BITS_STATUS_TCP_SEGMENT (1UL<<14) + #define RLUPQ_BITS_STATUS_UDP_DATAGRAM (1UL<<15) + #define RLUPQ_BITS_STATUS_CU_FRAME (1UL<<16) + #define RLUPQ_BITS_STATUS_IP_PROG_EXT (1UL<<17) + #define RLUPQ_BITS_STATUS_IP_TYPE (1UL<<18) + #define RLUPQ_BITS_STATUS_RULE_P1 (1UL<<19) + #define RLUPQ_BITS_STATUS_RLUP_HIT4 (1UL<<20) + #define RLUPQ_BITS_STATUS_IP_FRAGMENT (1UL<<21) + #define RLUPQ_BITS_STATUS_IP_OPTIONS_PRESENT (1UL<<22) + #define RLUPQ_BITS_STATUS_TCP_OPTIONS_PRESENT (1UL<<23) + #define RLUPQ_BITS_STATUS_L2_PM_IDX (0xfUL<<24) + #define RLUPQ_BITS_STATUS_L2_PM_HIT (1UL<<28) + #define RLUPQ_BITS_STATUS_L2_MC_HASH_HIT (1UL<<29) + #define RLUPQ_BITS_STATUS_RDMAC_CRC_PASS (1UL<<30) + #define RLUPQ_BITS_STATUS_MP_HIT (1UL<<31) + + u32_t rlupq_wd18; + #define RLUPQ_BITS_MULTICAST_HASH_IDX (0xff<<24) + #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT (0xf<<16) + #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_0 (0<<16) + #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_1 (1<<16) + #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_2 (2<<16) + #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_3 (3<<16) + #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_4 (4<<16) + #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_5 (5<<16) + #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_6 (6<<16) + #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_NONE (7<<16) + #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_8 (8<<16) + #define RLUPQ_KNUM (0xff<<8) + + u32_t rlupq_wd19; + #define RLUPQ_RULE_TAG (0xffff<<16) + #define RLUPQ_PKT_LEN_VALUE (0x3fff<<0) + + u32_t rlupq_wd20; + #define RLUPQ_VLAN_TAG (0xffff<<16) + #define RLUPQ_IP_HDR_OFFSET (0xff<<8) + + u32_t rlupq_wd21; + #define RLUPQ_IP_XSUM (0xffff<<16) + #define RLUPQ_TCP_UDP_HDR_OFFSET (0xffff<<0) + + u32_t rlupq_wd22; + #define RLUPQ_TCP_UDP_XSUM (0xffff<<16) + #define RLUPQ_TCP_PAYLOAD_LEN (0xffff<<0) + + u32_t rlupq_wd23; + #define RLUPQ_PSEUD_XSUM (0xffff<<16) + #define RLUPQ_L2_PAYLOAD_RAW_XSUM (0xffff<<0) + + u32_t rlupq_wd24; + #define RLUPQ_DATA_OFFSET (0xffff<<16) + #define RLUPQ_L3_PAYLOAD_RAW_XSUM (0xffff<<0) + + u32_t rlupq_mbuf_cluster; + #define RLUPQ_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) + + u32_t rlupq_ip_srcadd0; + u32_t rlupq_ip_srcadd1; + u32_t rlupq_ip_srcadd2; + u32_t rlupq_ip_srcadd3; +} rlupq_t; + + +/* + * rlup_reg definition + * offset: 0x2000 + */ +typedef struct rlup_reg +{ + u32_t rlup_command; + #define RLUP_COMMAND_ENABLED (1UL<<0) + #define RLUP_COMMAND_ADD (1UL<<1) + #define RLUP_COMMAND_INVALIDATE (1UL<<2) + #define RLUP_COMMAND_LOOKUP (1UL<<3) + #define RLUP_COMMAND_READ_TE (1UL<<4) + #define RLUP_COMMAND_WRITE_TE (1UL<<5) + #define RLUP_COMMAND_READ_CAM_XI (1UL<<4) + #define RLUP_COMMAND_WRITE_CAM_XI (1UL<<5) + #define RLUP_COMMAND_CAM_RESET (1UL<<6) + #define RLUP_COMMAND_READ_RAM (1UL<<7) + #define RLUP_COMMAND_WRITE_RAM (1UL<<8) + #define RLUP_COMMAND_ENTRY_TYPE (0x3UL<<9) + #define RLUP_COMMAND_ENTRY_TYPE_IPV4 (0UL<<9) + #define RLUP_COMMAND_ENTRY_TYPE_IPV6_4_TUPLE (1UL<<9) + #define RLUP_COMMAND_ENTRY_TYPE_IPV6_2_TUPLE (2UL<<9) + #define RLUP_COMMAND_ENTRY_TYPE_RES (3UL<<9) + #define RLUP_COMMAND_2ND_TUPLE_LOOKUP_EN (1UL<<11) + #define RLUP_COMMAND_MAINTENANCE_MODE (1UL<<12) + + u32_t rlup_status; + #define RLUP_STATUS_FTQ (1UL<<0) + #define RLUP_STATUS_SUCCESS (1UL<<1) + #define RLUP_STATUS_WORD_MATCH_TE (1UL<<2) + #define RLUP_STATUS_LOOKUP_MATCH_STAT_TE (1UL<<3) + #define RLUP_STATUS_LOOKUP_SM_TE (0x7UL<<16) + #define RLUP_STATUS_LOOKUP_SM_IDLE_TE (0UL<<16) + #define RLUP_STATUS_LOOKUP_SM_INPUT_TE (1UL<<16) + #define RLUP_STATUS_LOOKUP_SM_CAM_GRC_TE (2UL<<16) + #define RLUP_STATUS_LOOKUP_SM_CAM_STROBE_TE (3UL<<16) + #define RLUP_STATUS_LOOKUP_SM_CAM_WAIT_TE (4UL<<16) + #define RLUP_STATUS_LOOKUP_SM_RSS_WAIT_TE (5UL<<16) + #define RLUP_STATUS_LOOKUP_SM_FTQ_WR_TE (6UL<<16) + #define RLUP_STATUS_LOOKUP_SM_FTQ_POP_TE (7UL<<16) + #define RLUP_STATUS_REGCAM_SM_TE (0x3UL<<20) + #define RLUP_STATUS_REGCAM_SM_IDLE_TE (0UL<<20) + #define RLUP_STATUS_REGCAM_SM_STROBE_TE (1UL<<20) + #define RLUP_STATUS_REGCAM_SM_WAIT_TE (2UL<<20) + #define RLUP_STATUS_ACK_SM_TE (0x3UL<<24) + #define RLUP_STATUS_ACK_SM_IDLE_TE (0UL<<24) + #define RLUP_STATUS_ACK_SM_WAIT_TE (1UL<<24) + #define RLUP_STATUS_ACK_SM_STROBE_TE (2UL<<24) + #define RLUP_STATUS_LOOKUP_MATCH_STAT_XI (1UL<<2) + #define RLUP_STATUS_2TUPLE_LOOKUP_MATCH_STAT_XI (1UL<<3) + #define RLUP_STATUS_CAM_FULL_XI (1UL<<4) + #define RLUP_STATUS_DUPLICATE_ENTRY_XI (1UL<<5) + #define RLUP_STATUS_ZERO_CNT_ERR_XI (1UL<<6) + + u32_t rlup_ipsrc; + u32_t rlup_ipdest; + u32_t rlup_tcpport; + #define RLUP_TCPPORT_DESTPORT (0xffffUL<<0) + #define RLUP_TCPPORT_SRCPORT (0xffffUL<<16) + + u32_t rlup_cid; + #define RLUP_CID_VALUE (0x3fffUL<<7) + #define RLUP_CID_VALID (1UL<<31) + + u32_t rlup_idx; + #define RLUP_IDX_IDX_VALUE (0x3ffUL<<0) + + u32_t rlup_rss_config; + #define RLUP_RSS_CONFIG_RSS_TE (0x3UL<<0) + #define RLUP_RSS_CONFIG_RSS_OFF_TE (0UL<<0) + #define RLUP_RSS_CONFIG_RSS_ALL_TE (1UL<<0) + #define RLUP_RSS_CONFIG_RSS_IP_ONLY_TE (2UL<<0) + #define RLUP_RSS_CONFIG_RSS_RES_TE (3UL<<0) + #define RLUP_RSS_CONFIG_IPV4_RSS_TYPE_XI (0x3UL<<0) + #define RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI (0UL<<0) + #define RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI (1UL<<0) + #define RLUP_RSS_CONFIG_IPV4_RSS_TYPE_IP_ONLY_XI (2UL<<0) + #define RLUP_RSS_CONFIG_IPV4_RSS_TYPE_RES_XI (3UL<<0) + #define RLUP_RSS_CONFIG_IPV6_RSS_TYPE_XI (0x3UL<<2) + #define RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI (0UL<<2) + #define RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI (1UL<<2) + #define RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI (2UL<<2) + #define RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI (3UL<<2) + + u32_t rlup_rss_key1; + u32_t rlup_rss_key2; + u32_t rlup_rss_key3; + u32_t rlup_rss_key4; + u32_t rlup_ipv6_rss_key5; + u32_t rlup_ipv6_rss_key6; + u32_t rlup_ipv6_rss_key7; + u32_t rlup_ipv6_rss_key8; + u32_t rlup_ipv6_rss_key9; + u32_t rlup_ipv6_rss_key10; + u32_t rlup_rss_command; + #define RLUP_RSS_COMMAND_RSS_IND_TABLE_ADDR (0xfUL<<0) + #define RLUP_RSS_COMMAND_RSS_WRITE_MASK (0xffUL<<4) + #define RLUP_RSS_COMMAND_WRITE (1UL<<12) + #define RLUP_RSS_COMMAND_READ (1UL<<13) + #define RLUP_RSS_COMMAND_HASH_MASK (0x7UL<<14) + + u32_t rlup_rss_data; + #define RLUP_RSS_DATA_RSS_D0 (0xfUL<<0) + #define RLUP_RSS_DATA_RSS_D1 (0xfUL<<4) + #define RLUP_RSS_DATA_RSS_D2 (0xfUL<<8) + #define RLUP_RSS_DATA_RSS_D3 (0xfUL<<12) + #define RLUP_RSS_DATA_RSS_D4 (0xfUL<<16) + #define RLUP_RSS_DATA_RSS_D5 (0xfUL<<20) + #define RLUP_RSS_DATA_RSS_D6 (0xfUL<<24) + #define RLUP_RSS_DATA_RSS_D7 (0xfUL<<28) + + u32_t unused_0[9]; + u32_t rlup_free_count; + #define RLUP_FREE_COUNT_FREE_COUNT (0x7ffUL<<0) + + u32_t rlup_ipv6_src1; + u32_t rlup_ipv6_src2; + u32_t rlup_ipv6_src3; + u32_t rlup_ipv6_src4; + u32_t rlup_ipv6_dest1; + u32_t rlup_ipv6_dest2; + u32_t rlup_ipv6_dest3; + u32_t rlup_ipv6_dest4; + u32_t unused_1[154]; + u32_t rlup_cam_bist_command; + #define RLUP_CAM_BIST_COMMAND_BIST_RST_B (1UL<<0) + #define RLUP_CAM_BIST_COMMAND_BIST_EN (1UL<<1) + #define RLUP_CAM_BIST_COMMAND_BIST_DONE (1UL<<2) + #define RLUP_CAM_BIST_COMMAND_BIST_PASSED (1UL<<3) + + u32_t rlup_cam_bist_status0; + #define RLUP_CAM_BIST_STATUS0_MATCH_STATUS (1UL<<0) + #define RLUP_CAM_BIST_STATUS0_ACTUAL_BITPOS (0x7fUL<<1) + #define RLUP_CAM_BIST_STATUS0_ACTUAL_ADDROUT (0x3ffUL<<8) + + u32_t rlup_cam_bist_status1; + #define RLUP_CAM_BIST_STATUS1_MATCH_STATUS (1UL<<0) + #define RLUP_CAM_BIST_STATUS1_ADDROUT_STATUS (1UL<<1) + #define RLUP_CAM_BIST_STATUS1_ACTUAL_ADDROUT (0x3ffUL<<2) + #define RLUP_CAM_BIST_STATUS1_EXPECTED_ADDROUT (0x3ffUL<<12) + + u32_t rlup_cam_bist_status2; + #define RLUP_CAM_BIST_STATUS2_MATCH_STATUS (1UL<<0) + #define RLUP_CAM_BIST_STATUS2_ACTUAL_BITPOS (0x7fUL<<1) + #define RLUP_CAM_BIST_STATUS2_ACTUAL_ADDROUT (0x3ffUL<<8) + + u32_t rlup_cam_bist_status3; + #define RLUP_CAM_BIST_STATUS3_MATCH_STATUS (1UL<<0) + #define RLUP_CAM_BIST_STATUS3_ADDROUT_STATUS (1UL<<1) + #define RLUP_CAM_BIST_STATUS3_ACTUAL_ADDROUT (0x3ffUL<<2) + #define RLUP_CAM_BIST_STATUS3_EXPECTED_ADDROUT (0x3ffUL<<12) + + u32_t rlup_cam_bist_status4; + #define RLUP_CAM_BIST_STATUS4_MATCH_STATUS (1UL<<0) + #define RLUP_CAM_BIST_STATUS4_ACTUAL_ADDROUT (0x3ffUL<<1) + + u32_t unused_2[10]; + u32_t rlup_debug_vect_peek; + #define RLUP_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define RLUP_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) + #define RLUP_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define RLUP_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define RLUP_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) + #define RLUP_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t unused_3[15]; + rlupq_t rlup_rlupq; + u32_t rlup_ftq_cmd; + #define RLUP_FTQ_CMD_OFFSET (0x3ffUL<<0) + #define RLUP_FTQ_CMD_WR_TOP (1UL<<10) + #define RLUP_FTQ_CMD_WR_TOP_0 (0UL<<10) + #define RLUP_FTQ_CMD_WR_TOP_1 (1UL<<10) + #define RLUP_FTQ_CMD_SFT_RESET (1UL<<25) + #define RLUP_FTQ_CMD_RD_DATA (1UL<<26) + #define RLUP_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define RLUP_FTQ_CMD_ADD_DATA (1UL<<28) + #define RLUP_FTQ_CMD_INTERVENE_CLR (1UL<<29) + #define RLUP_FTQ_CMD_POP (1UL<<30) + #define RLUP_FTQ_CMD_BUSY (1UL<<31) + + u32_t rlup_ftq_ctl; + #define RLUP_FTQ_CTL_INTERVENE (1UL<<0) + #define RLUP_FTQ_CTL_OVERFLOW (1UL<<1) + #define RLUP_FTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define RLUP_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define RLUP_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + +} rlup_reg_t; + +typedef rlup_reg_t rx_lookup_reg_t; + +/* + * rx_v2p_mailbox_enqueue definition + * offset: 0000 + */ +typedef struct rx_v2p_mailbox_enqueue +{ + u32_t rx_v2p_mailbox_enqueue_cid; + #define RX_V2P_MAILBOX_ENQUEUE_CID_VALUE (0x3fffUL<<7) + +} rx_v2p_mailbox_enqueue_t; + + +/* + * rx_v2p_timeout_enqueue definition + * offset: 0000 + */ +typedef struct rx_v2p_timeout_enqueue +{ + u32_t rx_v2p_timeout_enqueue_cid; + #define RX_V2P_TIMEOUT_ENQUEUE_CID_VALUE (0x3fffUL<<7) + +} rx_v2p_timeout_enqueue_t; + + +/* + * rx_v2p_enqueue definition + * offset: 0000 + */ +typedef struct rx_v2p_enqueue +{ + u32_t rx_v2p_enqueue_cid; + #define RX_V2P_ENQUEUE_CID_VALUE (0x3fffUL<<7) + + u32_t rx_v2p_enqueue_mbuf_cluster; + #define RX_V2P_ENQUEUE_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) + + u32_t rx_v2p_enqueue_wd2; + #define RX_V2P_ENQUEUE_OPERAND_FLAGS (0xffff<<16) + #define RX_V2P_ENQUEUE_KNUM (0xff<<8) + #define RX_V2P_ENQUEUE_OPCODE (0xff<<0) + + u32_t rx_v2p_enqueue_wd3; + #define RX_V2P_ENQUEUE_OPERAND16_0 (0xffff<<16) + #define RX_V2P_ENQUEUE_OPERAND16_1 (0xffff<<0) + + u32_t rx_v2p_enqueue_wd4; + #define RX_V2P_ENQUEUE_OPERAND16_2 (0xffff<<16) + #define RX_V2P_ENQUEUE_OPERAND16_3 (0xffff<<0) + + u32_t rx_v2p_enqueue_wd5; + #define RX_V2P_ENQUEUE_OPERAND16_4 (0xffff<<16) + #define RX_V2P_ENQUEUE_OPERAND16_5 (0xffff<<0) + + u32_t rx_v2p_enqueue_wd6; + #define RX_V2P_ENQUEUE_OPERAND16_6 (0xffff<<16) + #define RX_V2P_ENQUEUE_OPERAND16_7 (0xffff<<0) + + u32_t rx_v2p_enqueue_operand32_0; + u32_t rx_v2p_enqueue_operand32_1; + u32_t rx_v2p_enqueue_operand32_2; + u32_t rx_v2p_enqueue_operand32_3; + u32_t rx_v2p_enqueue_operand32_4; + u32_t rx_v2p_enqueue_wd12; + #define RX_V2P_ENQUEUE_RDMA_ACTION_CS16_VLD (1<<30) + #define RX_V2P_ENQUEUE_RDMA_ACTION_NO_SNOOP (1<<31) + #define RX_V2P_ENQUEUE_CS16_PKT_LEN_VALUE (0x7f<<16) + #define RX_V2P_ENQUEUE_CS16 (0xffff<<0) + +} rx_v2p_enqueue_t; + + +/* + * rv2p_reg definition + * offset: 0x2800 + */ +typedef struct rv2p_reg +{ + u32_t rv2p_command; + #define RV2P_COMMAND_ENABLED (1UL<<0) + #define RV2P_COMMAND_PROC1_INTRPT (1UL<<1) + #define RV2P_COMMAND_PROC2_INTRPT (1UL<<2) + #define RV2P_COMMAND_ABORT0 (1UL<<4) + #define RV2P_COMMAND_ABORT1 (1UL<<5) + #define RV2P_COMMAND_ABORT2 (1UL<<6) + #define RV2P_COMMAND_ABORT3 (1UL<<7) + #define RV2P_COMMAND_ABORT4 (1UL<<8) + #define RV2P_COMMAND_ABORT5 (1UL<<9) + #define RV2P_COMMAND_PROC1_RESET (1UL<<16) + #define RV2P_COMMAND_PROC2_RESET (1UL<<17) + #define RV2P_COMMAND_CTXIF_RESET (1UL<<18) + + u32_t rv2p_status; + #define RV2P_STATUS_ALWAYS_0 (1UL<<0) + #define RV2P_STATUS_RV2P_GEN_STAT0_CNT (1UL<<8) + #define RV2P_STATUS_RV2P_GEN_STAT1_CNT (1UL<<9) + #define RV2P_STATUS_RV2P_GEN_STAT2_CNT (1UL<<10) + #define RV2P_STATUS_RV2P_GEN_STAT3_CNT (1UL<<11) + #define RV2P_STATUS_RV2P_GEN_STAT4_CNT (1UL<<12) + #define RV2P_STATUS_RV2P_GEN_STAT5_CNT (1UL<<13) + + u32_t rv2p_config; + #define RV2P_CONFIG_STALL_PROC1 (1UL<<0) + #define RV2P_CONFIG_STALL_PROC2 (1UL<<1) + #define RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1UL<<8) + #define RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1UL<<9) + #define RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1UL<<10) + #define RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1UL<<11) + #define RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1UL<<12) + #define RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1UL<<13) + #define RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1UL<<16) + #define RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1UL<<17) + #define RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1UL<<18) + #define RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1UL<<19) + #define RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1UL<<20) + #define RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1UL<<21) + #define RV2P_CONFIG_PAGE_SIZE (0xfUL<<24) + #define RV2P_CONFIG_PAGE_SIZE_256 (0UL<<24) + #define RV2P_CONFIG_PAGE_SIZE_512 (1UL<<24) + #define RV2P_CONFIG_PAGE_SIZE_1K (2UL<<24) + #define RV2P_CONFIG_PAGE_SIZE_2K (3UL<<24) + #define RV2P_CONFIG_PAGE_SIZE_4K (4UL<<24) + #define RV2P_CONFIG_PAGE_SIZE_8K (5UL<<24) + #define RV2P_CONFIG_PAGE_SIZE_16K (6UL<<24) + #define RV2P_CONFIG_PAGE_SIZE_32K (7UL<<24) + #define RV2P_CONFIG_PAGE_SIZE_64K (8UL<<24) + #define RV2P_CONFIG_PAGE_SIZE_128K (9UL<<24) + #define RV2P_CONFIG_PAGE_SIZE_256K (10UL<<24) + #define RV2P_CONFIG_PAGE_SIZE_512K (11UL<<24) + #define RV2P_CONFIG_PAGE_SIZE_1M (12UL<<24) + + u32_t unused_0; + u32_t rv2p_gen_bfr_addr_0; + #define RV2P_GEN_BFR_ADDR_0_VALUE (0xffffUL<<16) + + u32_t rv2p_gen_bfr_addr_1; + #define RV2P_GEN_BFR_ADDR_1_VALUE (0xffffUL<<16) + + u32_t rv2p_gen_bfr_addr_2; + #define RV2P_GEN_BFR_ADDR_2_VALUE (0xffffUL<<16) + + u32_t rv2p_gen_bfr_addr_3; + #define RV2P_GEN_BFR_ADDR_3_VALUE (0xffffUL<<16) + + u32_t unused_1[4]; + u32_t rv2p_instr_high; + #define RV2P_INSTR_HIGH_HIGH (0x1fUL<<0) + + u32_t rv2p_instr_low; + #define RV2P_INSTR_LOW_LOW (0xffffffffUL<<0) + + u32_t rv2p_proc1_addr_cmd; + #define RV2P_PROC1_ADDR_CMD_ADD (0x3ffUL<<0) + #define RV2P_PROC1_ADDR_CMD_RDWR (1UL<<31) + + u32_t rv2p_proc2_addr_cmd; + #define RV2P_PROC2_ADDR_CMD_ADD (0x3ffUL<<0) + #define RV2P_PROC2_ADDR_CMD_RDWR (1UL<<31) + + u32_t rv2p_proc1_grc_debug; + u32_t rv2p_proc2_grc_debug; + u32_t rv2p_grc_proc_debug; + u32_t rv2p_debug_vect_peek; + #define RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) + #define RV2P_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) + #define RV2P_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t unused_2[171]; + u32_t rv2p_mpfe_pfe_ctl; + #define RV2P_MPFE_PFE_CTL_INC_USAGE_CNT (1UL<<0) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE (0xfUL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_0 (0UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_1 (1UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_2 (2UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_3 (3UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_4 (4UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_5 (5UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_6 (6UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_7 (7UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_8 (8UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_9 (9UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_10 (10UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_11 (11UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_12 (12UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_13 (13UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_14 (14UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_SIZE_15 (15UL<<4) + #define RV2P_MPFE_PFE_CTL_PFE_COUNT (0xfUL<<12) + #define RV2P_MPFE_PFE_CTL_OFFSET (0x1ffUL<<16) + + u32_t unused_3[16]; + rx_v2p_enqueue_t rv2p_rv2ppq; + u32_t unused_4; + u32_t rv2p_pftq_cmd; + #define RV2P_PFTQ_CMD_OFFSET (0x3ffUL<<0) + #define RV2P_PFTQ_CMD_WR_TOP (1UL<<10) + #define RV2P_PFTQ_CMD_WR_TOP_0 (0UL<<10) + #define RV2P_PFTQ_CMD_WR_TOP_1 (1UL<<10) + #define RV2P_PFTQ_CMD_SFT_RESET (1UL<<25) + #define RV2P_PFTQ_CMD_RD_DATA (1UL<<26) + #define RV2P_PFTQ_CMD_ADD_INTERVEN (1UL<<27) + #define RV2P_PFTQ_CMD_ADD_DATA (1UL<<28) + #define RV2P_PFTQ_CMD_INTERVENE_CLR (1UL<<29) + #define RV2P_PFTQ_CMD_POP (1UL<<30) + #define RV2P_PFTQ_CMD_BUSY (1UL<<31) + + u32_t rv2p_pftq_ctl; + #define RV2P_PFTQ_CTL_INTERVENE (1UL<<0) + #define RV2P_PFTQ_CTL_OVERFLOW (1UL<<1) + #define RV2P_PFTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + + rx_v2p_timeout_enqueue_t rv2p_rv2ptq; + u32_t unused_5[13]; + u32_t rv2p_tftq_cmd; + #define RV2P_TFTQ_CMD_OFFSET (0x3ffUL<<0) + #define RV2P_TFTQ_CMD_WR_TOP (1UL<<10) + #define RV2P_TFTQ_CMD_WR_TOP_0 (0UL<<10) + #define RV2P_TFTQ_CMD_WR_TOP_1 (1UL<<10) + #define RV2P_TFTQ_CMD_SFT_RESET (1UL<<25) + #define RV2P_TFTQ_CMD_RD_DATA (1UL<<26) + #define RV2P_TFTQ_CMD_ADD_INTERVEN (1UL<<27) + #define RV2P_TFTQ_CMD_ADD_DATA (1UL<<28) + #define RV2P_TFTQ_CMD_INTERVENE_CLR (1UL<<29) + #define RV2P_TFTQ_CMD_POP (1UL<<30) + #define RV2P_TFTQ_CMD_BUSY (1UL<<31) + + u32_t rv2p_tftq_ctl; + #define RV2P_TFTQ_CTL_INTERVENE (1UL<<0) + #define RV2P_TFTQ_CTL_OVERFLOW (1UL<<1) + #define RV2P_TFTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + + rx_v2p_mailbox_enqueue_t rv2p_rv2pmq; + u32_t unused_6[13]; + u32_t rv2p_mftq_cmd; + #define RV2P_MFTQ_CMD_OFFSET (0x3ffUL<<0) + #define RV2P_MFTQ_CMD_WR_TOP (1UL<<10) + #define RV2P_MFTQ_CMD_WR_TOP_0 (0UL<<10) + #define RV2P_MFTQ_CMD_WR_TOP_1 (1UL<<10) + #define RV2P_MFTQ_CMD_SFT_RESET (1UL<<25) + #define RV2P_MFTQ_CMD_RD_DATA (1UL<<26) + #define RV2P_MFTQ_CMD_ADD_INTERVEN (1UL<<27) + #define RV2P_MFTQ_CMD_ADD_DATA (1UL<<28) + #define RV2P_MFTQ_CMD_INTERVENE_CLR (1UL<<29) + #define RV2P_MFTQ_CMD_POP (1UL<<30) + #define RV2P_MFTQ_CMD_BUSY (1UL<<31) + + u32_t rv2p_mftq_ctl; + #define RV2P_MFTQ_CTL_INTERVENE (1UL<<0) + #define RV2P_MFTQ_CTL_OVERFLOW (1UL<<1) + #define RV2P_MFTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + +} rv2p_reg_t; + +typedef rv2p_reg_t rx_v2p_reg_t; + +/* + * rx_dma_enqueue definition + * offset: 0000 + */ +typedef struct rx_dma_enqueue +{ + u32_t rx_dma_enqueue_cid; + #define RX_DMA_ENQUEUE_CID_VALUE (0x3fffUL<<7) + + u32_t rx_dma_enqueue_mbuf_cluster; + #define RX_DMA_ENQUEUE_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) + + u32_t rx_dma_enqueue_wd2; + #define RX_DMA_ENQUEUE_OPERAND_FLAGS (0xffff<<16) + #define RX_DMA_ENQUEUE_KNUM (0xff<<8) + #define RX_DMA_ENQUEUE_OPCODE (0xff<<0) + + u32_t rx_dma_enqueue_wd3; + #define RX_DMA_ENQUEUE_OPERAND16_0 (0xffff<<16) + #define RX_DMA_ENQUEUE_OPERAND16_1 (0xffff<<0) + + u32_t rx_dma_enqueue_wd4; + #define RX_DMA_ENQUEUE_OPERAND16_2 (0xffff<<16) + #define RX_DMA_ENQUEUE_OPERAND16_3 (0xffff<<0) + + u32_t rx_dma_enqueue_wd5; + #define RX_DMA_ENQUEUE_OPERAND16_4 (0xffff<<16) + #define RX_DMA_ENQUEUE_OPERAND16_5 (0xffff<<0) + + u32_t rx_dma_enqueue_wd6; + #define RX_DMA_ENQUEUE_OPERAND16_6 (0xffff<<16) + #define RX_DMA_ENQUEUE_OPERAND16_7 (0xffff<<0) + + u32_t rx_dma_enqueue_operand32_0; + u32_t rx_dma_enqueue_operand32_1; + u32_t rx_dma_enqueue_operand32_2; + u32_t rx_dma_enqueue_operand32_3; + u32_t rx_dma_enqueue_operand32_4; + u32_t rx_dma_enqueue_wd12; + #define RX_DMA_ENQUEUE_RDMA_ACTION_DO_DMA (1<<24) + #define RX_DMA_ENQUEUE_RDMA_ACTION_PREPEND_L2_FRAME_HDR (1<<25) + #define RX_DMA_ENQUEUE_RDMA_ACTION_CRC_ENABLE (1<<26) + #define RX_DMA_ENQUEUE_RDMA_ACTION_CRC_USE_CTX_SEED (1<<27) + #define RX_DMA_ENQUEUE_RDMA_ACTION_CS16_FIRST (1<<28) + #define RX_DMA_ENQUEUE_RDMA_ACTION_CS16_LAST (1<<29) + #define RX_DMA_ENQUEUE_RDMA_ACTION_CS16_VLD (1<<30) + #define RX_DMA_ENQUEUE_RDMA_ACTION_NO_SNOOP (1<<31) + #define RX_DMA_ENQUEUE_CS16_PKT_LEN_VALUE (0x7f<<16) + #define RX_DMA_ENQUEUE_CS16 (0xffff<<0) + +} rx_dma_enqueue_t; + + +/* + * rdma_reg definition + * offset: 0x2c00 + */ +typedef struct rdma_reg +{ + u32_t rdma_command; + #define RDMA_COMMAND_ENABLED (1UL<<0) + #define RDMA_COMMAND_MASTER_ABORT (1UL<<4) + + u32_t rdma_status; + #define RDMA_STATUS_DMA_WAIT (1UL<<0) + #define RDMA_STATUS_MBUF_WAIT (1UL<<1) + #define RDMA_STATUS_CMP_FTQ_WAIT (1UL<<2) + #define RDMA_STATUS_DMA_CNT_STAT (1UL<<16) + #define RDMA_STATUS_BURST_CNT_STAT (1UL<<17) + #define RDMA_STATUS_ERR (0xffUL<<20) + #define RDMA_STATUS_CS16_ERR (1UL<<31) + + u32_t rdma_config; + #define RDMA_CONFIG_MAX_DMAS (0x3UL<<0) + #define RDMA_CONFIG_ONE_RECORD (1UL<<2) + #define RDMA_CONFIG_CACHE_ALIGN_EN (1UL<<3) + #define RDMA_CONFIG_LIMIT_SZ (0x7UL<<4) + #define RDMA_CONFIG_LIMIT_SZ_8 (0UL<<4) + #define RDMA_CONFIG_LIMIT_SZ_16 (1UL<<4) + #define RDMA_CONFIG_LIMIT_SZ_32 (2UL<<4) + #define RDMA_CONFIG_LIMIT_SZ_64 (3UL<<4) + #define RDMA_CONFIG_LIMIT_SZ_128 (4UL<<4) + #define RDMA_CONFIG_LIMIT_SZ_256 (5UL<<4) + #define RDMA_CONFIG_LIMIT_SZ_512 (6UL<<4) + #define RDMA_CONFIG_LINE_SZ (0x7UL<<8) + #define RDMA_CONFIG_LINE_SZ_8 (0UL<<8) + #define RDMA_CONFIG_LINE_SZ_16 (1UL<<8) + #define RDMA_CONFIG_LINE_SZ_32 (2UL<<8) + #define RDMA_CONFIG_LINE_SZ_64 (3UL<<8) + #define RDMA_CONFIG_LINE_SZ_128 (4UL<<8) + #define RDMA_CONFIG_LINE_SZ_256 (5UL<<8) + #define RDMA_CONFIG_LINE_SZ_512 (6UL<<8) + #define RDMA_CONFIG_DI_DISABLE (1UL<<12) + #define RDMA_CONFIG_CTXCACHE_DISABLE (1UL<<16) + #define RDMA_CONFIG_CRC_OFFSET (0x3ffUL<<18) + #define RDMA_CONFIG_DMA_BREAKUP (0x3UL<<28) + #define RDMA_CONFIG_DMA_BREAKUP_00 (0UL<<28) + #define RDMA_CONFIG_DMA_BREAKUP_01 (1UL<<28) + #define RDMA_CONFIG_DMA_BREAKUP_10 (2UL<<28) + #define RDMA_CONFIG_DMA_BREAKUP_11 (3UL<<28) + #define RDMA_CONFIG_DMA_BREAK_OVERRIDE (1UL<<31) + + u32_t rdma_debug_vect_peek; + #define RDMA_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define RDMA_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) + #define RDMA_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define RDMA_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define RDMA_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) + #define RDMA_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t rdma_cksum_error_status; + #define RDMA_CKSUM_ERROR_STATUS_CALCULATED (0xffffUL<<0) + #define RDMA_CKSUM_ERROR_STATUS_EXPECTED (0xffffUL<<16) + + u32_t unused_0[235]; + rx_dma_enqueue_t rdma_rdmaq; + u32_t unused_1; + u32_t rdma_ftq_cmd; + #define RDMA_FTQ_CMD_OFFSET (0x3ffUL<<0) + #define RDMA_FTQ_CMD_WR_TOP (1UL<<10) + #define RDMA_FTQ_CMD_WR_TOP_0 (0UL<<10) + #define RDMA_FTQ_CMD_WR_TOP_1 (1UL<<10) + #define RDMA_FTQ_CMD_SFT_RESET (1UL<<25) + #define RDMA_FTQ_CMD_RD_DATA (1UL<<26) + #define RDMA_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define RDMA_FTQ_CMD_ADD_DATA (1UL<<28) + #define RDMA_FTQ_CMD_INTERVENE_CLR (1UL<<29) + #define RDMA_FTQ_CMD_POP (1UL<<30) + #define RDMA_FTQ_CMD_BUSY (1UL<<31) + + u32_t rdma_ftq_ctl; + #define RDMA_FTQ_CTL_INTERVENE (1UL<<0) + #define RDMA_FTQ_CTL_OVERFLOW (1UL<<1) + #define RDMA_FTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define RDMA_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define RDMA_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + +} rdma_reg_t; + +typedef rdma_reg_t rx_dma_reg_t; + +/* + * rbdc_reg definition + * offset: 0x3000 + */ +typedef struct rbdc_reg +{ + u32_t rbdc_command; + #define RBDC_COMMAND_ENABLED (1UL<<0) + #define RBDC_COMMAND_FLUSH (1UL<<1) + #define RBDC_COMMAND_SOFT_RST (1UL<<2) + #define RBDC_COMMAND_REG_ARB (1UL<<3) + #define RBDC_COMMAND_MASTER_ABORT (1UL<<4) + + u32_t rbdc_status; + #define RBDC_STATUS_LOCKED_CNT (0xffUL<<0) + #define RBDC_STATUS_DMA_WAIT_COMP (1UL<<8) + #define RBDC_STATUS_DMA_WAIT_ALLOC (1UL<<9) + #define RBDC_STATUS_DMA_WAIT_FREE (1UL<<10) + #define RBDC_STATUS_ZLD1 (1UL<<11) + #define RBDC_STATUS_ZLD2 (1UL<<12) + #define RBDC_STATUS_BURST_CNT (1UL<<20) + #define RBDC_STATUS_PROC1_MISS_CNT (1UL<<21) + #define RBDC_STATUS_PROC2_MISS_CNT (1UL<<22) + + u32_t rbdc_control; + #define RBDC_CONTROL_SWAP_MODE (1UL<<0) + #define RBDC_CONTROL_PRIORITY (1UL<<1) + // This bit forces RBDC to run in a single channel mode, in other words + // it will only have outstanding DMA read request. This bit is + // available starting from Xinan 65nm. + #define RBDC_CONTROL_ONE_CHNL (1UL<<4) + // The bit forces RBDC to limit the DMA requests to 64bytes at a time. + // This bit is available starting from Xinan 65nm. + #define REQ64_MODE (1UL<<5) + u32_t rbdc_bd_haddr_hi; + u32_t rbdc_bd_haddr_lo; + u32_t rbdc_bd_len; + #define RBDC_BD_UNUSED_UNUSED (0xffffUL<<0) + + u32_t unused_0; + u32_t rbdc_bd_flags; + #define RBDC_BD_FLAGS_FLAGS (0xffffUL<<0) + + u32_t rbdc_add; + #define RBDC_ADD_ADD (0x1ffUL<<0) + + u32_t rbdc_bdidx; + #define RBDC_BDIDX_BDIDX (0xffffUL<<0) + + u32_t rbdc_cid; + #define RBDC_CID_CID (0x3fffUL<<7) + + u32_t rbdc_flength; + #define RBDC_FLENGTH_FLENGTH (0x1fUL<<0) + + u32_t rbdc_opcode; + #define RBDC_OPCODE_OPCODE (0xfUL<<0) + #define RBDC_OPCODE_BDPT_B (1UL<<4) + + u32_t rbdc_haddr_hi; + u32_t rbdc_haddr_lo; + u32_t rbdc_fillhi; + #define RBDC_FILLHI_FILLHI (0xfUL<<0) + + u32_t rbdc_filllo; + #define RBDC_FILLLO_FILLLO (0xfUL<<0) + + u32_t rbdc_validhi; + #define RBDC_VALIDHI_VALIDHI (0xfUL<<0) + + u32_t rbdc_validlo; + #define RBDC_VALIDLO_VALIDLO (0xfUL<<0) + + u32_t rbdc_lockcount; + #define RBDC_LOCKCOUNT_LOCKCOUNT (0x3UL<<0) + + u32_t rbdc_valid; + #define RBDC_VALID_VALID (1UL<<0) + + u32_t rbdc_debug_vect_peek; + #define RBDC_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define RBDC_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) + #define RBDC_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define RBDC_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define RBDC_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) + #define RBDC_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t rbdc_cksum_error_status; + #define RBDC_CKSUM_ERROR_STATUS_CALCULATED (0xffffUL<<0) + #define RBDC_CKSUM_ERROR_STATUS_EXPECTED (0xffffUL<<16) + + u32_t unused_1[233]; +} rbdc_reg_t; + +typedef rbdc_reg_t rx_bd_cache_reg_t; + +/* + * rbuf_reg definition + * offset: 0x200000 + */ +typedef struct rbuf_reg +{ + u32_t rbuf_command; + #define RBUF_COMMAND_ENABLED (1UL<<0) + #define RBUF_COMMAND_FREE_INIT (1UL<<1) + #define RBUF_COMMAND_RAM_INIT (1UL<<2) + #define RBUF_COMMAND_PKT_OFFSET_OVFL (1UL<<3) + #define RBUF_COMMAND_OVER_FREE (1UL<<4) + #define RBUF_COMMAND_ALLOC_REQ_TE (1UL<<5) + #define RBUF_COMMAND_EN_PRI_CHNGE_TE (1UL<<6) + #define RBUF_COMMAND_CU_ISOLATE_XI (1UL<<5) + #define RBUF_COMMAND_EN_PRI_CHANGE_XI (1UL<<6) + #define RBUF_COMMAND_GRC_ENDIAN_CONV_DIS_XI (1UL<<7) + + u32_t rbuf_status1; + #define RBUF_STATUS1_FREE_COUNT (0x3ffUL<<0) + + u32_t rbuf_status2; + #define RBUF_STATUS2_FREE_TAIL (0x1ffUL<<0) + #define RBUF_STATUS2_FREE_HEAD (0x1ffUL<<16) + + u32_t rbuf_config; + #define RBUF_CONFIG_XOFF_TRIP (0x3ffUL<<0) + #define RBUF_CONFIG_XON_TRIP (0x3ffUL<<16) + + u32_t rbuf_fw_buf_alloc; + #define RBUF_FW_BUF_ALLOC_VALUE (0x1ffUL<<7) + #define RBUF_FW_BUF_ALLOC_TYPE (1UL<<16) + #define RBUF_FW_BUF_ALLOC_ALLOC_REQ (1UL<<31) + + u32_t rbuf_fw_buf_free; + #define RBUF_FW_BUF_FREE_COUNT (0x7fUL<<0) + #define RBUF_FW_BUF_FREE_TAIL (0x1ffUL<<7) + #define RBUF_FW_BUF_FREE_HEAD (0x1ffUL<<16) + #define RBUF_FW_BUF_FREE_TYPE (1UL<<25) + #define RBUF_FW_BUF_FREE_FREE_REQ (1UL<<31) + + u32_t rbuf_fw_buf_sel; + #define RBUF_FW_BUF_SEL_COUNT (0x7fUL<<0) + #define RBUF_FW_BUF_SEL_TAIL (0x1ffUL<<7) + #define RBUF_FW_BUF_SEL_HEAD (0x1ffUL<<16) + #define RBUF_FW_BUF_SEL_SEL_REQ (1UL<<31) + + u32_t rbuf_config2; + #define RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffUL<<0) + #define RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffUL<<16) + + u32_t rbuf_config3; + #define RBUF_CONFIG3_CU_DROP_TRIP (0x3ffUL<<0) + #define RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffUL<<16) + + u32_t rbuf_mbuf_count; + #define RBUF_MBUF_COUNT_OCCUPIED_COUNT (0x3ffUL<<0) + #define RBUF_MBUF_COUNT_MAX_COUNT (0x3ffUL<<16) + #define RBUF_MBUF_COUNT_CLR (1UL<<31) + + u32_t rbuf_cu_mbuf_count; + #define RBUF_CU_MBUF_COUNT_OCCUPIED_COUNT (0x3ffUL<<0) + #define RBUF_CU_MBUF_COUNT_MAX_COUNT (0x3ffUL<<16) + #define RBUF_CU_MBUF_COUNT_CLR (1UL<<31) + + u32_t rbuf_cu_buffer_size; + #define RBUF_CU_BUFFER_SIZE_CU_BUFFER_SIZE (0x3ffUL<<0) + + u32_t rbuf_cu_free_count; + #define RBUF_CU_FREE_COUNT_CU_FREE_COUNT (0x3ffUL<<0) + + u32_t unused_0[243]; + u32_t rbuf_bist_cs0; + #define RBUF_BIST_CS0_MBIST_EN (1UL<<0) + #define RBUF_BIST_CS0_BIST_SETUP (0x3UL<<1) + #define RBUF_BIST_CS0_MBIST_ASYNC_RESET (1UL<<3) + #define RBUF_BIST_CS0_MBIST_DONE (1UL<<8) + #define RBUF_BIST_CS0_MBIST_GO (1UL<<9) + + u32_t rbuf_bist_memstatus0; + u32_t rbuf_bist_cs1; + #define RBUF_BIST_CS1_MBIST_EN (1UL<<0) + #define RBUF_BIST_CS1_BIST_SETUP (0x3UL<<1) + #define RBUF_BIST_CS1_MBIST_ASYNC_RESET (1UL<<3) + #define RBUF_BIST_CS1_MBIST_DONE (1UL<<8) + #define RBUF_BIST_CS1_MBIST_GO (1UL<<9) + + u32_t rbuf_bist_memstatus1; + u32_t rbuf_bist_cs2; + #define RBUF_BIST_CS2_MBIST_EN (1UL<<0) + #define RBUF_BIST_CS2_BIST_SETUP (0x3UL<<1) + #define RBUF_BIST_CS2_MBIST_ASYNC_RESET (1UL<<3) + #define RBUF_BIST_CS2_MBIST_DONE (1UL<<8) + #define RBUF_BIST_CS2_MBIST_GO (1UL<<9) + + u32_t rbuf_bist_memstatus2; + u32_t rbuf_bist_cs3; + #define RBUF_BIST_CS3_MBIST_EN (1UL<<0) + #define RBUF_BIST_CS3_BIST_SETUP (0x3UL<<1) + #define RBUF_BIST_CS3_MBIST_ASYNC_RESET (1UL<<3) + #define RBUF_BIST_CS3_MBIST_DONE (1UL<<8) + #define RBUF_BIST_CS3_MBIST_GO (1UL<<9) + + u32_t rbuf_bist_memstatus3; + u32_t rbuf_bist_cs4; + #define RBUF_BIST_CS4_MBIST_EN (1UL<<0) + #define RBUF_BIST_CS4_BIST_SETUP (0x3UL<<1) + #define RBUF_BIST_CS4_MBIST_ASYNC_RESET (1UL<<3) + #define RBUF_BIST_CS4_MBIST_DONE (1UL<<8) + #define RBUF_BIST_CS4_MBIST_GO (1UL<<9) + + u32_t rbuf_bist_memstatus4; + u32_t rbuf_bist_cs5; + #define RBUF_BIST_CS5_MBIST_EN (1UL<<0) + #define RBUF_BIST_CS5_BIST_SETUP (0x3UL<<1) + #define RBUF_BIST_CS5_MBIST_ASYNC_RESET (1UL<<3) + #define RBUF_BIST_CS5_MBIST_DONE (1UL<<8) + #define RBUF_BIST_CS5_MBIST_GO (1UL<<9) + + u32_t rbuf_bist_memstatus5; + u32_t rbuf_bist_cs6; + #define RBUF_BIST_CS6_MBIST_EN (1UL<<0) + #define RBUF_BIST_CS6_BIST_SETUP (0x3UL<<1) + #define RBUF_BIST_CS6_MBIST_ASYNC_RESET (1UL<<3) + #define RBUF_BIST_CS6_MBIST_DONE (1UL<<8) + #define RBUF_BIST_CS6_MBIST_GO (1UL<<9) + + u32_t rbuf_bist_memstatus6; + u32_t rbuf_bist_cs7; + #define RBUF_BIST_CS7_MBIST_EN (1UL<<0) + #define RBUF_BIST_CS7_BIST_SETUP (0x3UL<<1) + #define RBUF_BIST_CS7_MBIST_ASYNC_RESET (1UL<<3) + #define RBUF_BIST_CS7_MBIST_DONE (1UL<<8) + #define RBUF_BIST_CS7_MBIST_GO (1UL<<9) + + u32_t rbuf_bist_memstatus7; + u32_t rbuf_mem_tm0; + #define RBUF_MEM_TM0_CTX_USAGE_CNT_TMB (0x3UL<<0) + #define RBUF_MEM_TM0_CTX_USAGE_CNT_TMA (0x3UL<<2) + #define RBUF_MEM_TM0_CTX_PAGE_TABLE_TM (0xfUL<<4) + #define RBUF_MEM_TM0_CTX_CACHE_TM (0xfUL<<8) + #define RBUF_MEM_TM0_CTX_CAM_TM (0x7ffUL<<12) + + u32_t rbuf_mem_tm1; + #define RBUF_MEM_TM1_CTX_CAM_MIRROR_TM (0xfUL<<0) + #define RBUF_MEM_TM1_RXPQ_TM (0xffUL<<8) + #define RBUF_MEM_TM1_THBUF_DATAMEM_TM (0xffUL<<16) + #define RBUF_MEM_TM1_TSCH_CONN_LIST_TM (0xfUL<<24) + #define RBUF_MEM_TM1_MQ_IDX_STOR_TM (0xfUL<<28) + + u32_t rbuf_mem_tm2; + #define RBUF_MEM_TM2_RV2P_PROC2_TM (0xfUL<<0) + #define RBUF_MEM_TM2_CS_TMEM_TM (0xfUL<<4) + #define RBUF_MEM_TM2_RV2PCS_TMEM_TM (0xfUL<<8) + #define RBUF_MEM_TM2_CP_SCPAD_TM (0xfUL<<12) + #define RBUF_MEM_TM2_RLUP_CAM_TM (0x7ffUL<<16) + + u32_t rbuf_mem_tm3; + #define RBUF_MEM_TM3_RX_BDCACHE_TM (0xffUL<<0) + #define RBUF_MEM_TM3_TX_BDCACHE_TM (0xffUL<<8) + #define RBUF_MEM_TM3_RLUP_CID_TM (0xfUL<<16) + #define RBUF_MEM_TM3_RV2P_PROC1_TM (0xfUL<<24) + + u32_t rbuf_mem_tm4; + #define RBUF_MEM_TM4_COM_CP_CACHE_TM (0xfUL<<0) + #define RBUF_MEM_TM4_TPAT_SCPAD_TM (0xfUL<<8) + #define RBUF_MEM_TM4_TXP_SCPAD_TM (0xfUL<<16) + #define RBUF_MEM_TM4_RXP_SCPAD_TM (0xfUL<<24) + + u32_t rbuf_mem_tm5; + #define RBUF_MEM_TM5_TPBUF_DATAMEM_TM (0xffUL<<0) + #define RBUF_MEM_TM5_RBUF_DATAMEM_TM (0xffUL<<8) + #define RBUF_MEM_TM5_RBUF_PTRMEM_TMA (0x3UL<<16) + #define RBUF_MEM_TM5_RBUF_PTRMEM_TMB (0x3UL<<24) + + u32_t rbuf_mem_65_tm0; + #define RBUF_MEM_65_TM0_CTX_USAGE_CNT_TMB (0xfUL<<0) + #define RBUF_MEM_65_TM0_CTX_PAGE_TABLE_TM (0xfUL<<4) + #define RBUF_MEM_65_TM0_CTX_CACHE_TM (0xfUL<<8) + #define RBUF_MEM_65_TM0_CTX_CAM_TM (0x7ffUL<<12) + #define RBUF_MEM_65_TM0_CTX_USAGE_CNT_TMA (0xfUL<<28) + + u32_t rbuf_mem_65_tm1; + #define RBUF_MEM_65_TM1_CTX_CAM_MIRROR_TM (0xfUL<<0) + #define RBUF_MEM_65_TM1_RXPQ_TM (0xffUL<<8) + #define RBUF_MEM_65_TM1_THBUF_DATAMEM_TM (0xffUL<<16) + #define RBUF_MEM_65_TM1_TSCH_CONN_LIST_TM (0xfUL<<24) + #define RBUF_MEM_65_TM1_MQ_IDX_STOR_TM (0xfUL<<28) + + u32_t rbuf_mem_65_tm2; + #define RBUF_MEM_65_TM2_RV2P_PROC2_TM (0xfUL<<0) + #define RBUF_MEM_65_TM2_CS_TMEM_TM (0xfUL<<4) + #define RBUF_MEM_65_TM2_RV2PCS_TMEM_TM (0xfUL<<8) + #define RBUF_MEM_65_TM2_CP_SCPAD_TM (0xfUL<<12) + #define RBUF_MEM_65_TM2_RLUB_CAM_TM (0x7ffUL<<16) + #define RBUF_MEM_65_TM2_TDMA_IFIFO_TMB (0x3UL<<28) + #define RBUF_MEM_65_TM2_TDMA_IFIFO_TMA (0x3UL<<30) + + u32_t rbuf_mem_65_tm3; + #define RBUF_MEM_65_TM3_RX_BDCACHE_TM (0xffUL<<0) + #define RBUF_MEM_65_TM3_TX_BDCACHE_TM (0xffUL<<8) + #define RBUF_MEM_65_TM3_RLUP_CID_TM (0xfUL<<16) + #define RBUF_MEM_65_TM3_RV2P_PROC1_TM (0xfUL<<24) + #define RBUF_MEM_65_TM3_RDMA_DFIFO_TM (0x3UL<<28) + #define RBUF_MEM_65_TM3_MQ_FIFO_TM (0x3UL<<30) + + u32_t rbuf_mem_65_tm4; + #define RBUF_MEM_65_TM4_TPAT_SCPAD_TM (0xfUL<<8) + #define RBUF_MEM_65_TM4_COM_SCPAD_TM (0xfUL<<8) + #define RBUF_MEM_65_TM4_CTX_CP_BURST_BUFS_TM (0x3UL<<14) + #define RBUF_MEM_65_TM4_TXP_SCPAD_TM (0xfUL<<16) + #define RBUF_MEM_65_TM4_CTX_TXP_BURST_BUFS_TM (0x3UL<<22) + #define RBUF_MEM_65_TM4_RXP_SCPAD_TM (0xfUL<<24) + #define RBUF_MEM_65_TM4_CTX_RXP_BURST_BUFS_TM (0x3UL<<30) + + u32_t rbuf_mem_65_tm5; + #define RBUF_MEM_65_TM5_TPBUF_DATAMEM_TM (0xffUL<<0) + #define RBUF_MEM_65_TM5_RBUF_DATAMEM_TM (0xffUL<<8) + #define RBUF_MEM_65_TM5_RBUF_PTRMEM_TMA (0xfUL<<16) + #define RBUF_MEM_65_TM5_DMAE_COM_CACHE_TM (0x3UL<<22) + #define RBUF_MEM_65_TM5_RBUF_PTRMEM_TMB (0xfUL<<24) + #define RBUF_MEM_65_TM5_DMAE_CP_CACHE_TM (0x3UL<<30) + + u32_t rbuf_weak_wr_cmdstat; + #define RBUF_WEAK_WR_CMDSTAT_WW_MODE (1UL<<0) + #define RBUF_WEAK_WR_CMDSTAT_WW_START (1UL<<1) + #define RBUF_WEAK_WR_CMDSTAT_WW_DONE (1UL<<2) + #define RBUF_WEAK_WR_CMDSTAT_RBUF_DATAMEM_FAIL_FLAG (1UL<<4) + #define RBUF_WEAK_WR_CMDSTAT_TPBUF_DATAMEM_FAIL_FLAG (1UL<<5) + #define RBUF_WEAK_WR_CMDSTAT_RBUF_PTMEM_FAIL_FLAG (1UL<<6) + #define RBUF_WEAK_WR_CMDSTAT_RXP_SCPAD_FAIL_FLAG (1UL<<7) + #define RBUF_WEAK_WR_CMDSTAT_TPAT_SCPAD_FAIL_FLAG (1UL<<8) + #define RBUF_WEAK_WR_CMDSTAT_CTX_USAGE_CNT_FAIL_FLAG (1UL<<9) + #define RBUF_WEAK_WR_CMDSTAT_CTX_PAGE_TABLE_FAIL_FLAG (1UL<<10) + #define RBUF_WEAK_WR_CMDSTAT_CTX_CACHE_FAIL_FLAG (1UL<<11) + #define RBUF_WEAK_WR_CMDSTAT_CS_TMEM_1_FAIL_FLAG (1UL<<12) + #define RBUF_WEAK_WR_CMDSTAT_RLUP_CID_RAM_FAIL_FLAG (1UL<<13) + #define RBUF_WEAK_WR_CMDSTAT_RV2P_PROC2_FAIL_FLAG (1UL<<14) + #define RBUF_WEAK_WR_CMDSTAT_RV2P_PROC1_FAIL_FLAG (1UL<<15) + #define RBUF_WEAK_WR_CMDSTAT_TSCH_CONN_LIST_FAIL_FLAG (1UL<<16) + #define RBUF_WEAK_WR_CMDSTAT_RX_BDCACHE_FAIL_FLAG (1UL<<17) + #define RBUF_WEAK_WR_CMDSTAT_THBUF_DATAMEM_FAIL_FLAG (1UL<<18) + #define RBUF_WEAK_WR_CMDSTAT_CS_TMEM_2_FAIL_FLAG (1UL<<19) + #define RBUF_WEAK_WR_CMDSTAT_MQ_INDEX_STORAGE_FAIL_FLAG (1UL<<20) + #define RBUF_WEAK_WR_CMDSTAT_RXPQ_1_FAIL_FLAG (1UL<<21) + #define RBUF_WEAK_WR_CMDSTAT_RXPQ_2_FAIL_FLAG (1UL<<22) + #define RBUF_WEAK_WR_CMDSTAT_TX_BDCACHE_FAIL_FLAG (1UL<<23) + #define RBUF_WEAK_WR_CMDSTAT_COM_SCPAD_FAIL_FLAG (1UL<<24) + #define RBUF_WEAK_WR_CMDSTAT_CP_SCPAD_FAIL_FLAG (1UL<<25) + #define RBUF_WEAK_WR_CMDSTAT_CTX_CAM_MIRROR_FAIL_FLAG (1UL<<26) + #define RBUF_WEAK_WR_CMDSTAT_TXP_SCPAD_FAIL_FLAG (1UL<<27) + + u32_t unused_1[7907]; + u32_t rbuf_pkt_data[2250]; + u32_t unused_2[5942]; + u32_t rbuf_clist_data[512]; + u32_t unused_3[15872]; + u32_t rbuf_buf_data[16384]; + u32_t unused_4[16384]; +} rbuf_reg_t; + +typedef rbuf_reg_t rx_mbuf_reg_t; + +/* + * idb_state_val definition + * offset: 0000 + */ +typedef struct idb_state_val +{ + u32_t idb_state_val_val; + #define IDB_STATE_VAL_VAL_STATE (0x7UL<<0) + #define IDB_STATE_VAL_VAL_STATE_IDLE (0UL<<0) + #define IDB_STATE_VAL_VAL_STATE_FILLING (1UL<<0) + #define IDB_STATE_VAL_VAL_STATE_TRIGGERED (2UL<<0) + #define IDB_STATE_VAL_VAL_STATE_FULL (3UL<<0) + #define IDB_STATE_VAL_VAL_STATE_OUTWAIT (4UL<<0) + #define IDB_STATE_VAL_VAL_CID (0x3fffUL<<7) + +} idb_state_val_t; + + +/* + * mq_reg definition + * offset: 0x3c00 + */ +typedef struct mq_reg +{ + u32_t mq_command; + #define MQ_COMMAND_ENABLED (1UL<<0) + #define MQ_COMMAND_INIT (1UL<<1) + #define MQ_COMMAND_OVERFLOW (1UL<<4) + #define MQ_COMMAND_WR_ERROR (1UL<<5) + #define MQ_COMMAND_RD_ERROR (1UL<<6) + #define MQ_COMMAND_IDB_CFG_ERROR (1UL<<7) + #define MQ_COMMAND_IDB_OVERFLOW (1UL<<10) + #define MQ_COMMAND_NO_BIN_ERROR (1UL<<11) + #define MQ_COMMAND_NO_MAP_ERROR (1UL<<12) + + u32_t mq_status; + #define MQ_STATUS_CTX_ACCESS_STAT (1UL<<16) + #define MQ_STATUS_CTX_ACCESS64_STAT (1UL<<17) + #define MQ_STATUS_PCI_STALL_STAT (1UL<<18) + #define MQ_STATUS_IDB_OFLOW_STAT (1UL<<19) + + u32_t mq_config; + #define MQ_CONFIG_TX_HIGH_PRI (1UL<<0) + #define MQ_CONFIG_HALT_DIS (1UL<<1) + #define MQ_CONFIG_BIN_MQ_MODE (1UL<<2) + #define MQ_CONFIG_DIS_IDB_DROP (1UL<<3) + #define MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7UL<<4) + #define MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0UL<<4) + #define MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1UL<<4) + #define MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2UL<<4) + #define MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3UL<<4) + #define MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4UL<<4) + #define MQ_CONFIG_MAX_DEPTH (0x7fUL<<8) + #define MQ_CONFIG_CUR_DEPTH (0x7fUL<<20) + + u32_t mq_enqueue1; + #define MQ_ENQUEUE1_OFFSET (0x3fUL<<2) + #define MQ_ENQUEUE1_CID (0x3fffUL<<8) + #define MQ_ENQUEUE1_BYTE_MASK (0xfUL<<24) + #define MQ_ENQUEUE1_KNL_MODE (1UL<<28) + + u32_t mq_enqueue2; + u32_t mq_bad_wr_addr; + u32_t mq_bad_rd_addr; + u32_t mq_knl_byp_wind_start; + #define MQ_KNL_BYP_WIND_START_VALUE (0xfffffUL<<12) + + u32_t mq_knl_wind_end; + #define MQ_KNL_WIND_END_VALUE (0xffffffUL<<8) + + u32_t mq_knl_write_mask1; + u32_t mq_knl_tx_mask1; + u32_t mq_knl_cmd_mask1; + u32_t mq_knl_cond_enqueue_mask1; + u32_t mq_knl_rx_v2p_mask1; + u32_t mq_knl_write_mask2; + u32_t mq_knl_tx_mask2; + u32_t mq_knl_cmd_mask2; + u32_t mq_knl_cond_enqueue_mask2; + u32_t mq_knl_rx_v2p_mask2; + u32_t mq_knl_byp_write_mask1; + u32_t mq_knl_byp_tx_mask1; + u32_t mq_knl_byp_cmd_mask1; + u32_t mq_knl_byp_cond_enqueue_mask1; + u32_t mq_knl_byp_rx_v2p_mask1; + u32_t mq_knl_byp_write_mask2; + u32_t mq_knl_byp_tx_mask2; + u32_t mq_knl_byp_cmd_mask2; + u32_t mq_knl_byp_cond_enqueue_mask2; + u32_t mq_knl_byp_rx_v2p_mask2; + u32_t mq_mem_wr_addr; + #define MQ_MEM_WR_ADDR_VALUE (0x3fUL<<0) + + u32_t mq_mem_wr_data0; + #define MQ_MEM_WR_DATA0_VALUE (0xffffffffUL<<0) + + u32_t mq_mem_wr_data1; + #define MQ_MEM_WR_DATA1_VALUE (0xffffffffUL<<0) + + u32_t mq_mem_wr_data2; + #define MQ_MEM_WR_DATA2_VALUE_TE (0x3fffffffUL<<0) + #define MQ_MEM_WR_DATA2_VALUE_XI (0x7fffffffUL<<0) + + u32_t mq_mem_rd_addr; + #define MQ_MEM_RD_ADDR_VALUE (0x3fUL<<0) + + u32_t mq_mem_rd_data0; + #define MQ_MEM_RD_DATA0_VALUE (0xffffffffUL<<0) + + u32_t mq_mem_rd_data1; + #define MQ_MEM_RD_DATA1_VALUE (0xffffffffUL<<0) + + u32_t mq_mem_rd_data2; + #define MQ_MEM_RD_DATA2_VALUE_TE (0x3fffffffUL<<0) + #define MQ_MEM_RD_DATA2_VALUE_XI (0x7fffffffUL<<0) + + u32_t mq_debug_vect_peek; + #define MQ_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define MQ_DEBUG_VECT_PEEK_1_EN (1UL<<11) + #define MQ_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define MQ_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define MQ_DEBUG_VECT_PEEK_2_EN (1UL<<27) + #define MQ_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t unused_0[2]; + u32_t mq_idb_cfg; + #define MQ_IDB_CFG_MB_START (0x3UL<<0) + #define MQ_IDB_CFG_MB_START_256 (0UL<<0) + #define MQ_IDB_CFG_MB_START_512 (1UL<<0) + #define MQ_IDB_CFG_MB_START_1K (2UL<<0) + #define MQ_IDB_CFG_MB_START_2K (3UL<<0) + #define MQ_IDB_CFG_MB_SIZE (0x3UL<<4) + #define MQ_IDB_CFG_MB_SIZE_256 (0UL<<4) + #define MQ_IDB_CFG_MB_SIZE_512 (1UL<<4) + #define MQ_IDB_CFG_MB_SIZE_1K (2UL<<4) + #define MQ_IDB_CFG_MB_SIZE_2K (3UL<<4) + #define MQ_IDB_CFG_ADD_BYTE_SWAP (1UL<<6) + #define MQ_IDB_CFG_ADD_WORD_SWAP (1UL<<7) + #define MQ_IDB_CFG_WQE_SIZE (0x3UL<<8) + #define MQ_IDB_CFG_WQE_SIZE_NONE (0UL<<8) + #define MQ_IDB_CFG_WQE_SIZE_64B (1UL<<8) + #define MQ_IDB_CFG_WQE_SIZE_128B (2UL<<8) + #define MQ_IDB_CFG_CTX_LOC (0x7ffUL<<10) + #define MQ_IDB_CFG_TRIG_LOC (0x3fUL<<24) + #define MQ_IDB_CFG_ENA (1UL<<31) + + u32_t mq_idb_free; + #define MQ_IDB_FREE_CID (0x3fffUL<<7) + + u32_t unused_1[2]; + u32_t mq_idb_state0_val; + #define MQ_IDB_STATE0_VAL_STATE (0x7UL<<0) + #define MQ_IDB_STATE0_VAL_STATE_IDLE (0UL<<0) + #define MQ_IDB_STATE0_VAL_STATE_FILLING (1UL<<0) + #define MQ_IDB_STATE0_VAL_STATE_TRIGGERED (2UL<<0) + #define MQ_IDB_STATE0_VAL_STATE_FULL (3UL<<0) + #define MQ_IDB_STATE0_VAL_STATE_OUTWAIT (4UL<<0) + #define MQ_IDB_STATE0_VAL_CID (0x3fffUL<<7) + + idb_state_val_t mq_idb_state1; + idb_state_val_t mq_idb_state2; + idb_state_val_t mq_idb_state3; + u32_t unused_2[16]; + u32_t mq_config2; + #define MQ_CONFIG2_CONT_SZ (0x7UL<<4) + #define MQ_CONFIG2_CONT_SZ_4PER (2UL<<4) + #define MQ_CONFIG2_CONT_SZ_6PER (3UL<<4) + #define MQ_CONFIG2_CONT_SZ_8PER (4UL<<4) + #define MQ_CONFIG2_CONT_SZ_10PER (5UL<<4) + #define MQ_CONFIG2_CONT_SZ_12PER (6UL<<4) + #define MQ_CONFIG2_CONT_SZ_14PER (7UL<<4) + #define MQ_CONFIG2_FIRST_L4L5 (0x1fUL<<8) + #define MQ_CONFIG2_IDB_DROP_AUTO_RECOV (1UL<<16) + #define MQ_CONFIG2_IDB_AUTO_ON (0x3UL<<17) + #define MQ_CONFIG2_IDB_AUTO_ON_32 (0UL<<17) + #define MQ_CONFIG2_IDB_AUTO_ON_16 (1UL<<17) + #define MQ_CONFIG2_IDB_AUTO_ON_8 (2UL<<17) + #define MQ_CONFIG2_IDB_AUTO_ON_4 (3UL<<17) + #define MQ_CONFIG2_SCNR_CTHRU_DIS (1UL<<20) + + u32_t mq_idx_cmd; + #define MQ_IDX_CMD_RD_CMD (1UL<<0) + #define MQ_IDX_CMD_WR_CMD (0x3UL<<1) + #define MQ_IDX_CMD_WR_CMD_NOTHING (0UL<<1) + #define MQ_IDX_CMD_WR_CMD_LOW (1UL<<1) + #define MQ_IDX_CMD_WR_CMD_HIGH (2UL<<1) + #define MQ_IDX_CMD_WR_CMD_BOTH (3UL<<1) + #define MQ_IDX_CMD_SP (0x3UL<<4) + #define MQ_IDX_CMD_BIN_OFFSET (0x3UL<<12) + #define MQ_IDX_CMD_BIN (0xfffUL<<16) + + u32_t mq_idx_data; + u32_t mq_scnr_cmd; + #define MQ_SCNR_CMD_RD_CMD (1UL<<0) + #define MQ_SCNR_CMD_WR_CMD (1UL<<1) + #define MQ_SCNR_CMD_BIN (0xfffUL<<16) + + u32_t mq_scnr_data; + u32_t unused_3[3]; + u32_t mq_map_l2_0; + #define MQ_MAP_L2_0_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L2_0_SZ (0x3UL<<8) + #define MQ_MAP_L2_0_SZ_8B (1UL<<8) + #define MQ_MAP_L2_0_SZ_16B (2UL<<8) + #define MQ_MAP_L2_0_SZ_32B (3UL<<8) + #define MQ_MAP_L2_0_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L2_0_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L2_0_BIN_OFFSET_0 (0UL<<23) + #define MQ_MAP_L2_0_BIN_OFFSET_1 (1UL<<23) + #define MQ_MAP_L2_0_BIN_OFFSET_2 (2UL<<23) + #define MQ_MAP_L2_0_BIN_OFFSET_4 (4UL<<23) + #define MQ_MAP_L2_0_BIN_OFFSET_5 (5UL<<23) + #define MQ_MAP_L2_0_BIN_OFFSET_6 (6UL<<23) + #define MQ_MAP_L2_0_ARM (0x3UL<<26) + #define MQ_MAP_L2_0_ARM_NONE (0UL<<26) + #define MQ_MAP_L2_0_ARM_TSCH (1UL<<26) + #define MQ_MAP_L2_0_ARM_CS (2UL<<26) + #define MQ_MAP_L2_0_ARM_RV2PCS (3UL<<26) + #define MQ_MAP_L2_0_ENA (1UL<<31) + + u32_t mq_map_l2_1; + #define MQ_MAP_L2_1_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L2_1_SZ (0x3UL<<8) + #define MQ_MAP_L2_1_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L2_1_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L2_1_ARM (0x3UL<<26) + #define MQ_MAP_L2_1_ENA (1UL<<31) + + u32_t mq_map_l2_2; + #define MQ_MAP_L2_2_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L2_2_SZ (0x3UL<<8) + #define MQ_MAP_L2_2_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L2_2_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L2_2_ARM (0x3UL<<26) + #define MQ_MAP_L2_2_ENA (1UL<<31) + + u32_t mq_map_l2_3; + #define MQ_MAP_L2_3_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L2_3_SZ (0x3UL<<8) + #define MQ_MAP_L2_3_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L2_3_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L2_3_ARM (0x3UL<<26) + #define MQ_MAP_L2_3_ENA (1UL<<31) + + u32_t mq_map_l2_4; + #define MQ_MAP_L2_4_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L2_4_SZ (0x3UL<<8) + #define MQ_MAP_L2_4_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L2_4_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L2_4_ARM (0x3UL<<26) + #define MQ_MAP_L2_4_ENA (1UL<<31) + + u32_t mq_map_l2_5; + #define MQ_MAP_L2_5_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L2_5_SZ (0x3UL<<8) + #define MQ_MAP_L2_5_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L2_5_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L2_5_ARM (0x3UL<<26) + #define MQ_MAP_L2_5_ENA (1UL<<31) + + u32_t unused_4[2]; + u32_t mq_map_l4_0; + #define MQ_MAP_L4_0_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L4_0_SZ (0x3UL<<8) + #define MQ_MAP_L4_0_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L4_0_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L4_0_ARM (0x3UL<<26) + #define MQ_MAP_L4_0_ENA (1UL<<31) + + u32_t mq_map_l4_1; + #define MQ_MAP_L4_1_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L4_1_SZ (0x3UL<<8) + #define MQ_MAP_L4_1_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L4_1_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L4_1_ARM (0x3UL<<26) + #define MQ_MAP_L4_1_ENA (1UL<<31) + + u32_t mq_map_l4_2; + #define MQ_MAP_L4_2_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L4_2_SZ (0x3UL<<8) + #define MQ_MAP_L4_2_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L4_2_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L4_2_ARM (0x3UL<<26) + #define MQ_MAP_L4_2_ENA (1UL<<31) + + u32_t mq_map_l4_3; + #define MQ_MAP_L4_3_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L4_3_SZ (0x3UL<<8) + #define MQ_MAP_L4_3_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L4_3_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L4_3_ARM (0x3UL<<26) + #define MQ_MAP_L4_3_ENA (1UL<<31) + + u32_t mq_map_l4_4; + #define MQ_MAP_L4_4_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L4_4_SZ (0x3UL<<8) + #define MQ_MAP_L4_4_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L4_4_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L4_4_ARM (0x3UL<<26) + #define MQ_MAP_L4_4_ENA (1UL<<31) + + u32_t mq_map_l4_5; + #define MQ_MAP_L4_5_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L4_5_SZ (0x3UL<<8) + #define MQ_MAP_L4_5_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L4_5_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L4_5_ARM (0x3UL<<26) + #define MQ_MAP_L4_5_ENA (1UL<<31) + + u32_t unused_5[2]; + u32_t mq_map_l5_0; + #define MQ_MAP_L5_0_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L5_0_SZ (0x3UL<<8) + #define MQ_MAP_L5_0_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L5_0_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L5_0_ARM (0x3UL<<26) + #define MQ_MAP_L5_0_ENA (1UL<<31) + + u32_t mq_map_l5_1; + #define MQ_MAP_L5_1_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L5_1_SZ (0x3UL<<8) + #define MQ_MAP_L5_1_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L5_1_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L5_1_ARM (0x3UL<<26) + #define MQ_MAP_L5_1_ENA (1UL<<31) + + u32_t mq_map_l5_2; + #define MQ_MAP_L5_2_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L5_2_SZ (0x3UL<<8) + #define MQ_MAP_L5_2_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L5_2_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L5_2_ARM (0x3UL<<26) + #define MQ_MAP_L5_2_ENA (1UL<<31) + + u32_t mq_map_l5_3; + #define MQ_MAP_L5_3_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L5_3_SZ (0x3UL<<8) + #define MQ_MAP_L5_3_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L5_3_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L5_3_ARM (0x3UL<<26) + #define MQ_MAP_L5_3_ENA (1UL<<31) + + u32_t mq_map_l5_4; + #define MQ_MAP_L5_4_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L5_4_SZ (0x3UL<<8) + #define MQ_MAP_L5_4_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L5_4_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L5_4_ARM (0x3UL<<26) + #define MQ_MAP_L5_4_ENA (1UL<<31) + + u32_t mq_map_l5_5; + #define MQ_MAP_L5_5_MQ_OFFSET (0xffUL<<0) + #define MQ_MAP_L5_5_SZ (0x3UL<<8) + #define MQ_MAP_L5_5_CTX_OFFSET (0x3ffUL<<10) + #define MQ_MAP_L5_5_BIN_OFFSET (0x7UL<<23) + #define MQ_MAP_L5_5_ARM (0x3UL<<26) + #define MQ_MAP_L5_5_ENA (1UL<<31) + + u32_t unused_6[162]; +} mq_reg_t; + +typedef mq_reg_t mailbox_queue_reg_t; + +/* + * cmd_scheduler_enqueue definition + * offset: 0000 + */ +typedef struct cmd_scheduler_enqueue +{ + u32_t cmd_scheduler_enqueue_cid; + #define CMD_SCHEDULER_ENQUEUE_CID_VALUE (0x3fffUL<<7) + + u32_t cmd_scheduler_enqueue_wd1; + #define CMD_SCHEDULER_ENQUEUE_FLAGS_NORMAL (1<<25) + #define CMD_SCHEDULER_ENQUEUE_FLAGS_DELIST (1<<24) + +} cmd_scheduler_enqueue_t; + + +/* + * csch_reg definition + * offset: 0x4000 + */ +typedef struct csch_reg +{ + u32_t csch_ch_command; + #define CSCH_CH_COMMAND_ENABLE (1UL<<0) + + u32_t csch_ch_status; + #define CSCH_CH_STATUS_CMD_CNT_STAT (1UL<<16) + #define CSCH_CH_STATUS_SLOT_CNT_STAT (1UL<<17) + + u32_t csch_ch_list_ram_addr; + #define CSCH_CH_LIST_RAM_ADDR_CSCH_LIST_RAM_ADDR_VALUE (0x1ffUL<<4) + + u32_t csch_ch_list_ram_data; + u32_t csch_ch_hard_cid; + #define CSCH_CH_HARD_CID_VALUE (0x3fffUL<<7) + + u32_t unused_0[7]; + u32_t csch_ch_valid_array0; + u32_t csch_ch_valid_array1; + u32_t csch_ch_valid_array2; + u32_t csch_ch_valid_array3; + u32_t csch_ch_valid_array4; + u32_t csch_ch_valid_array5; + u32_t csch_ch_valid_array6; + u32_t csch_ch_valid_array7; + u32_t csch_ch_valid_array8; + u32_t csch_ch_valid_array9; + u32_t csch_ch_valid_array10; + u32_t csch_ch_valid_array11; + u32_t csch_ch_valid_array12; + u32_t csch_ch_valid_array13; + u32_t csch_ch_valid_array14; + u32_t csch_ch_valid_array15; + u32_t csch_hc_sch_stat; + #define CSCH_HC_SCH_STAT_PS_CSARB (0xfUL<<0) + #define CSCH_HC_SCH_STAT_PS_CPQIF (1UL<<8) + #define CSCH_HC_SCH_STAT_CUR_ACT_CID (0x3fffUL<<16) + + u32_t csch_ch_csqif_stat; + #define CSCH_CH_CSQIF_STAT_CSQIF_STAT_PS_CSQSM (0x3UL<<0) + + u32_t csch_ch_tmem_fsm; + #define CSCH_CH_TMEM_FSM_MEMARB (0x3UL<<0) + #define CSCH_CH_TMEM_FSM_TMEMCLR (0x3UL<<8) + #define CSCH_CH_TMEM_FSM_ARBLK_1 (1UL<<16) + #define CSCH_CH_TMEM_FSM_ARBLK_0 (1UL<<17) + #define CSCH_CH_TMEM_FSM_CSQLK (1UL<<18) + + u32_t csch_ch_tmem_stat; + #define CSCH_CH_TMEM_STAT_ARB_1 (0x3ffUL<<0) + #define CSCH_CH_TMEM_STAT_ARB_0 (0x3ffUL<<10) + #define CSCH_CH_TMEM_STAT_CSQ (0x3ffUL<<20) + + u32_t unused_1[208]; + cmd_scheduler_enqueue_t csch_csq; + u32_t unused_2[12]; + u32_t csch_ch_ftq_cmd; + #define CSCH_CH_FTQ_CMD_OFFSET (0x3ffUL<<0) + #define CSCH_CH_FTQ_CMD_WR_TOP (1UL<<10) + #define CSCH_CH_FTQ_CMD_WR_TOP_0 (0UL<<10) + #define CSCH_CH_FTQ_CMD_WR_TOP_1 (1UL<<10) + #define CSCH_CH_FTQ_CMD_SFT_RESET (1UL<<25) + #define CSCH_CH_FTQ_CMD_RD_DATA (1UL<<26) + #define CSCH_CH_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define CSCH_CH_FTQ_CMD_ADD_DATA (1UL<<28) + #define CSCH_CH_FTQ_CMD_INTERVENE_CLR (1UL<<29) + #define CSCH_CH_FTQ_CMD_POP (1UL<<30) + #define CSCH_CH_FTQ_CMD_BUSY (1UL<<31) + + u32_t csch_ch_ftq_ctl; + #define CSCH_CH_FTQ_CTL_INTERVENE (1UL<<0) + #define CSCH_CH_FTQ_CTL_OVERFLOW (1UL<<1) + #define CSCH_CH_FTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define CSCH_CH_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define CSCH_CH_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + +} csch_reg_t; + +typedef csch_reg_t cmd_scheduler_reg_t; + + +/* + * timer_reg definition + * offset: 0x4400 + */ +typedef struct timer_reg +{ + u32_t timer_command; + #define TIMER_COMMAND_ENABLED (1UL<<0) + + u32_t timer_status; + #define TIMER_STATUS_CMP_FTQ_WAIT (1UL<<0) + #define TIMER_STATUS_POLL_PASS_CNT (1UL<<8) + #define TIMER_STATUS_TMR1_CNT (1UL<<9) + #define TIMER_STATUS_TMR2_CNT (1UL<<10) + #define TIMER_STATUS_TMR3_CNT (1UL<<11) + #define TIMER_STATUS_TMR4_CNT (1UL<<12) + #define TIMER_STATUS_TMR5_CNT (1UL<<13) + + u32_t timer_config; + #define TIMER_CONFIG_SCAN_WD_CNT_TE (0xffUL<<0) + #define TIMER_CONFIG_SCAN_WD_CNT_XI (0x7ffUL<<0) + #define TIMER_CONFIG_TMR1_BASE (0x7UL<<16) + #define TIMER_CONFIG_TMR1_BASE_CORE (0UL<<16) + #define TIMER_CONFIG_TMR1_BASE_1US (1UL<<16) + #define TIMER_CONFIG_TMR1_BASE_10US (2UL<<16) + #define TIMER_CONFIG_TMR1_BASE_100US (3UL<<16) + #define TIMER_CONFIG_TMR1_BASE_1MS (4UL<<16) + #define TIMER_CONFIG_TMR1_BASE_10MS (5UL<<16) + #define TIMER_CONFIG_TMR1_BASE_100MS (6UL<<16) + #define TIMER_CONFIG_TMR1_BASE_1S (7UL<<16) + #define TIMER_CONFIG_TMR2_BASE (0x7UL<<19) + #define TIMER_CONFIG_TMR2_BASE_CORE (0UL<<19) + #define TIMER_CONFIG_TMR2_BASE_1US (1UL<<19) + #define TIMER_CONFIG_TMR2_BASE_10US (2UL<<19) + #define TIMER_CONFIG_TMR2_BASE_100US (3UL<<19) + #define TIMER_CONFIG_TMR2_BASE_1MS (4UL<<19) + #define TIMER_CONFIG_TMR2_BASE_10MS (5UL<<19) + #define TIMER_CONFIG_TMR2_BASE_100MS (6UL<<19) + #define TIMER_CONFIG_TMR2_BASE_1S (7UL<<19) + #define TIMER_CONFIG_TMR3_BASE (0x7UL<<22) + #define TIMER_CONFIG_TMR3_BASE_CORE (0UL<<22) + #define TIMER_CONFIG_TMR3_BASE_1US (1UL<<22) + #define TIMER_CONFIG_TMR3_BASE_10US (2UL<<22) + #define TIMER_CONFIG_TMR3_BASE_100US (3UL<<22) + #define TIMER_CONFIG_TMR3_BASE_1MS (4UL<<22) + #define TIMER_CONFIG_TMR3_BASE_10MS (5UL<<22) + #define TIMER_CONFIG_TMR3_BASE_100MS (6UL<<22) + #define TIMER_CONFIG_TMR3_BASE_1S (7UL<<22) + #define TIMER_CONFIG_TMR4_BASE (0x7UL<<25) + #define TIMER_CONFIG_TMR4_BASE_CORE (0UL<<25) + #define TIMER_CONFIG_TMR4_BASE_1US (1UL<<25) + #define TIMER_CONFIG_TMR4_BASE_10US (2UL<<25) + #define TIMER_CONFIG_TMR4_BASE_100US (3UL<<25) + #define TIMER_CONFIG_TMR4_BASE_1MS (4UL<<25) + #define TIMER_CONFIG_TMR4_BASE_10MS (5UL<<25) + #define TIMER_CONFIG_TMR4_BASE_100MS (6UL<<25) + #define TIMER_CONFIG_TMR4_BASE_1S (7UL<<25) + #define TIMER_CONFIG_TMR5_BASE (0x7UL<<28) + #define TIMER_CONFIG_TMR5_BASE_CORE (0UL<<28) + #define TIMER_CONFIG_TMR5_BASE_1US (1UL<<28) + #define TIMER_CONFIG_TMR5_BASE_10US (2UL<<28) + #define TIMER_CONFIG_TMR5_BASE_100US (3UL<<28) + #define TIMER_CONFIG_TMR5_BASE_1MS (4UL<<28) + #define TIMER_CONFIG_TMR5_BASE_10MS (5UL<<28) + #define TIMER_CONFIG_TMR5_BASE_100MS (6UL<<28) + #define TIMER_CONFIG_TMR5_BASE_1S (7UL<<28) + + u32_t timer_value1; + u16_t unused_0; + u16_t timer_value2; + u16_t unused_1; + u16_t timer_value3; + u16_t unused_2; + u16_t timer_value4; + u16_t unused_3; + u16_t timer_value5; + u32_t timer_ctx_scan_start_addr; + #define TIMER_CTX_SCAN_START_ADDR_VALUE (0x3ffffUL<<3) + #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE (0x7UL<<21) + #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_CORE (0UL<<21) + #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_1US (1UL<<21) + #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_10US (2UL<<21) + #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_100US (3UL<<21) + #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_1MS (4UL<<21) + #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_10MS (5UL<<21) + #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_100MS (6UL<<21) + #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_1S (7UL<<21) + #define TIMER_CTX_SCAN_START_ADDR_RESTART_RELOAD (0xffUL<<24) + + u32_t timer_sw_tmr_cfg1; + #define TIMER_SW_TMR_CFG1_ENA (1UL<<0) + #define TIMER_SW_TMR_CFG1_RELOAD (1UL<<1) + #define TIMER_SW_TMR_CFG1_ATTN (1UL<<2) + #define TIMER_SW_TMR_CFG1_COM (1UL<<3) + #define TIMER_SW_TMR_CFG1_BASE (0x7UL<<4) + #define TIMER_SW_TMR_CFG1_BASE_CORE (0UL<<4) + #define TIMER_SW_TMR_CFG1_BASE_1US (1UL<<4) + #define TIMER_SW_TMR_CFG1_BASE_10US (2UL<<4) + #define TIMER_SW_TMR_CFG1_BASE_100US (3UL<<4) + #define TIMER_SW_TMR_CFG1_BASE_1MS (4UL<<4) + #define TIMER_SW_TMR_CFG1_BASE_10MS (5UL<<4) + #define TIMER_SW_TMR_CFG1_BASE_100MS (6UL<<4) + #define TIMER_SW_TMR_CFG1_BASE_1S (7UL<<4) + + u32_t timer_sw_tmr_value1; + u32_t timer_sw_tmr_reload_value1; + u32_t timer_sw_tmr_value2; + u32_t timer_sw_tmr_reload_value2; + u32_t timer_sw_tmr_value3; + u32_t timer_sw_tmr_reload_value3; + u32_t timer_sw_tmr_value4; + u32_t timer_sw_tmr_reload_value4; + u32_t timer_25mhz_free_run; + u32_t timer_sw_tmr_cfg2; + #define TIMER_SW_TMR_CFG2_ENA (1UL<<0) + #define TIMER_SW_TMR_CFG2_RELOAD (1UL<<1) + #define TIMER_SW_TMR_CFG2_ATTN (1UL<<2) + #define TIMER_SW_TMR_CFG2_COM (1UL<<3) + #define TIMER_SW_TMR_CFG2_BASE (0x7UL<<4) + #define TIMER_SW_TMR_CFG2_BASE_CORE (0UL<<4) + #define TIMER_SW_TMR_CFG2_BASE_1US (1UL<<4) + #define TIMER_SW_TMR_CFG2_BASE_10US (2UL<<4) + #define TIMER_SW_TMR_CFG2_BASE_100US (3UL<<4) + #define TIMER_SW_TMR_CFG2_BASE_1MS (4UL<<4) + #define TIMER_SW_TMR_CFG2_BASE_10MS (5UL<<4) + #define TIMER_SW_TMR_CFG2_BASE_100MS (6UL<<4) + #define TIMER_SW_TMR_CFG2_BASE_1S (7UL<<4) + + u32_t timer_sw_tmr_cfg3; + #define TIMER_SW_TMR_CFG3_ENA (1UL<<0) + #define TIMER_SW_TMR_CFG3_RELOAD (1UL<<1) + #define TIMER_SW_TMR_CFG3_ATTN (1UL<<2) + #define TIMER_SW_TMR_CFG3_COM (1UL<<3) + #define TIMER_SW_TMR_CFG3_BASE (0x7UL<<4) + #define TIMER_SW_TMR_CFG3_BASE_CORE (0UL<<4) + #define TIMER_SW_TMR_CFG3_BASE_1US (1UL<<4) + #define TIMER_SW_TMR_CFG3_BASE_10US (2UL<<4) + #define TIMER_SW_TMR_CFG3_BASE_100US (3UL<<4) + #define TIMER_SW_TMR_CFG3_BASE_1MS (4UL<<4) + #define TIMER_SW_TMR_CFG3_BASE_10MS (5UL<<4) + #define TIMER_SW_TMR_CFG3_BASE_100MS (6UL<<4) + #define TIMER_SW_TMR_CFG3_BASE_1S (7UL<<4) + + u32_t timer_sw_tmr_cfg4; + #define TIMER_SW_TMR_CFG4_ENA (1UL<<0) + #define TIMER_SW_TMR_CFG4_RELOAD (1UL<<1) + #define TIMER_SW_TMR_CFG4_ATTN (1UL<<2) + #define TIMER_SW_TMR_CFG4_COM (1UL<<3) + #define TIMER_SW_TMR_CFG4_BASE (0x7UL<<4) + #define TIMER_SW_TMR_CFG4_BASE_CORE (0UL<<4) + #define TIMER_SW_TMR_CFG4_BASE_1US (1UL<<4) + #define TIMER_SW_TMR_CFG4_BASE_10US (2UL<<4) + #define TIMER_SW_TMR_CFG4_BASE_100US (3UL<<4) + #define TIMER_SW_TMR_CFG4_BASE_1MS (4UL<<4) + #define TIMER_SW_TMR_CFG4_BASE_10MS (5UL<<4) + #define TIMER_SW_TMR_CFG4_BASE_100MS (6UL<<4) + #define TIMER_SW_TMR_CFG4_BASE_1S (7UL<<4) + + u32_t timer_sw_tmr_event_clr; + #define TIMER_SW_TMR_EVENT_CLR_TMR1_EVENT_CLR (1UL<<0) + #define TIMER_SW_TMR_EVENT_CLR_TMR2_EVENT_CLR (1UL<<1) + #define TIMER_SW_TMR_EVENT_CLR_TMR3_EVENT_CLR (1UL<<2) + #define TIMER_SW_TMR_EVENT_CLR_TMR4_EVENT_CLR (1UL<<3) + + u32_t unused_4[2]; + u32_t timer_fsm_tmr; + #define TIMER_FSM_TMR_TMR_CTX_IF (0x7ffUL<<0) + #define TIMER_FSM_TMR_TMR_CTX_IF_IDLE (0UL<<0) + #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_SCAN_REQ (2UL<<0) + #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_SCAN_ACK (4UL<<0) + #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_SCAN_VLD (8UL<<0) + #define TIMER_FSM_TMR_TMR_CTX_IF_BITFLD_EVAL (16UL<<0) + #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_TM_REQ0 (32UL<<0) + #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_TM_REQ1 (64UL<<0) + #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_TM_VLD (128UL<<0) + #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_TM_EVAL (256UL<<0) + #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_LAST_ACK (512UL<<0) + #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_TM_WAIT (1024UL<<0) + #define TIMER_FSM_TMR_COMTQ_IF (0x3UL<<16) + #define TIMER_FSM_TMR_COMTQ_IF_IDLE (0UL<<16) + #define TIMER_FSM_TMR_COMTQ_IF_LOAD (1UL<<16) + #define TIMER_FSM_TMR_COMTQ_IF_REQ (2UL<<16) + + u32_t timer_stat_tmr; + #define TIMER_STAT_TMR_SCAN_WC (0xffffUL<<0) + #define TIMER_STAT_TMR_CTX_OFF (0xffffUL<<16) + + u32_t unused_5[229]; +} timer_reg_t; + + +/* + * tx_scheduler_enqueue definition + * offset: 0000 + */ +typedef struct tx_scheduler_enqueue +{ + u32_t tx_scheduler_enqueue_cid; + #define TX_SCHEDULER_ENQUEUE_CID_VALUE (0x3fffUL<<7) + + u32_t tx_scheduler_enqueue_wd1; + #define TX_SCHEDULER_ENQUEUE_FLAGS_DELIST (1<<24) + #define TX_SCHEDULER_ENQUEUE_FLAGS_NORMAL (1<<25) + #define TX_SCHEDULER_ENQUEUE_FLAGS_HIGH (1<<26) + #define TX_SCHEDULER_ENQUEUE_RSVD_FUTURE_VALUE (0x3<<16) + +} tx_scheduler_enqueue_t; + + +/* + * tsch_reg definition + * offset: 0x4c00 + */ +typedef struct tsch_reg +{ + u32_t tsch_command; + #define TSCH_COMMAND_ENABLE (1UL<<0) + + u32_t tsch_status; + #define TSCH_STATUS_LS_INIT (1UL<<0) + #define TSCH_STATUS_LOCK_WT (1UL<<1) + #define TSCH_STATUS_INT_LOC (1UL<<2) + #define TSCH_STATUS_INTERNAL_TBDR_WT (1UL<<3) + #define TSCH_STATUS_CMD_CNT_STAT (1UL<<4) + #define TSCH_STATUS_SLOT_CNT_STAT (1UL<<5) + + u32_t tsch_mix; + #define TSCH_MIX_0 (0x3UL<<0) + #define TSCH_MIX_0_NORMAL (0UL<<0) + #define TSCH_MIX_0_HIGH (1UL<<0) + #define TSCH_MIX_0_QUICK (2UL<<0) + #define TSCH_MIX_0_UNDEF (3UL<<0) + #define TSCH_MIX_1 (0x3UL<<2) + #define TSCH_MIX_2 (0x3UL<<4) + #define TSCH_MIX_3 (0x3UL<<6) + #define TSCH_MIX_4 (0x3UL<<8) + #define TSCH_MIX_5 (0x3UL<<10) + #define TSCH_MIX_6 (0x3UL<<12) + #define TSCH_MIX_7 (0x3UL<<14) + #define TSCH_MIX_8 (0x3UL<<16) + #define TSCH_MIX_9 (0x3UL<<18) + #define TSCH_MIX_10 (0x3UL<<20) + #define TSCH_MIX_11 (0x3UL<<22) + #define TSCH_MIX_12 (0x3UL<<24) + #define TSCH_MIX_13 (0x3UL<<26) + #define TSCH_MIX_14 (0x3UL<<28) + #define TSCH_MIX_15 (0x3UL<<30) + + u32_t tsch_quick_slot_size; + #define TSCH_QUICK_SLOT_SIZE_VALUE (0x1ffUL<<10) + #define TSCH_QUICK_SLOT_SIZE_CTX_L2_SLOT_SIZE_EN (1UL<<19) + #define TSCH_QUICK_SLOT_SIZE_PESS_DIV (0xfUL<<24) + + u32_t tsch_list_ram_addr; + #define TSCH_LIST_RAM_ADDR_VALUE (0x1ffUL<<5) + #define TSCH_LIST_RAM_ADDR_LIST_WD_SEL (1UL<<31) + + u32_t tsch_list_ram_data; + u32_t tsch_ctx_access_cfg; + #define TSCH_CTX_ACCESS_CFG_TCMD_CELL_OFFSET (0x3fUL<<0) + #define TSCH_CTX_ACCESS_CFG_L5_TCMD_PREFETCH_SIZE (0x7UL<<8) + #define TSCH_CTX_ACCESS_CFG_CMN_CELL_OFFSET (0x7UL<<16) + #define TSCH_CTX_ACCESS_CFG_ADD_PREFETCH_SIZE (0x3UL<<24) + #define TSCH_CTX_ACCESS_CFG_ADD_PREFETCH_EN (1UL<<26) + + u32_t tsch_tss_cfg; + #define TSCH_TSS_CFG_TSS_START_CID (0x7ffUL<<10) + #define TSCH_TSS_CFG_NUM_OF_TSS_CON (0xfUL<<24) + + u32_t unused_0[8]; + u32_t tsch_debug_1; + #define TSCH_DEBUG_1_SLOT_PT (0xfUL<<0) + #define TSCH_DEBUG_1_SERV_PT (0xfUL<<4) + #define TSCH_DEBUG_1_SLOT_SM (0x7UL<<8) + #define TSCH_DEBUG_1_SLOT_SM_IDLE (0UL<<8) + #define TSCH_DEBUG_1_SLOT_SM_TRAV (1UL<<8) + #define TSCH_DEBUG_1_SLOT_SM_ACK (2UL<<8) + #define TSCH_DEBUG_1_SLOT_SM_WAIT (3UL<<8) + #define TSCH_DEBUG_1_SLOT_SM_NOTIFY (4UL<<8) + #define TSCH_DEBUG_1_LP_REQ_SM (0x3UL<<12) + #define TSCH_DEBUG_1_LP_REQ_SM_IDLE (0UL<<12) + #define TSCH_DEBUG_1_LP_REQ_SM_REQ_SEL (1UL<<12) + #define TSCH_DEBUG_1_LP_REQ_SM_REQ_CON (2UL<<12) + #define TSCH_DEBUG_1_HP_REQ_SM (0x3UL<<14) + #define TSCH_DEBUG_1_HP_REQ_SM_IDLE (0UL<<14) + #define TSCH_DEBUG_1_HP_REQ_SM_REQ_SEL (1UL<<14) + #define TSCH_DEBUG_1_HP_REQ_SM_REQ_CON (2UL<<14) + #define TSCH_DEBUG_1_LIST_SM (0x7UL<<16) + #define TSCH_DEBUG_1_LIST_SM_IDLE (0UL<<16) + #define TSCH_DEBUG_1_LIST_SM_READ (1UL<<16) + #define TSCH_DEBUG_1_LIST_SM_STORE (2UL<<16) + #define TSCH_DEBUG_1_LIST_SM_FIND_CON (3UL<<16) + #define TSCH_DEBUG_1_LIST_SM_FIND_WORD (4UL<<16) + #define TSCH_DEBUG_1_LIST_SM_WAIT (5UL<<16) + #define TSCH_DEBUG_1_LIST_SM_SEL (6UL<<16) + #define TSCH_DEBUG_1_DO_HLIST (1UL<<19) + #define TSCH_DEBUG_1_LIST_EMPTY (1UL<<20) + #define TSCH_DEBUG_1_HLIST_EMPTY (1UL<<21) + #define TSCH_DEBUG_1_L2_SM (0x3UL<<22) + #define TSCH_DEBUG_1_L2_SM_IDLE (0UL<<22) + #define TSCH_DEBUG_1_L2_SM_FOUND (1UL<<22) + #define TSCH_DEBUG_1_L2_SM_SEL (2UL<<22) + #define TSCH_DEBUG_1_ACT_L2_LIST (0xfUL<<24) + #define TSCH_DEBUG_1_GENQ_SM (0x7UL<<28) + #define TSCH_DEBUG_1_GENQ_SM_IDLE (0UL<<28) + #define TSCH_DEBUG_1_GENQ_SM_READ_INPUT (1UL<<28) + #define TSCH_DEBUG_1_GENQ_SM_READ_OFFLOAD (2UL<<28) + #define TSCH_DEBUG_1_GENQ_SM_READ_STORE (3UL<<28) + #define TSCH_DEBUG_1_GENQ_SM_READ_UPDATE (4UL<<28) + #define TSCH_DEBUG_1_GENQ_SM_READ_WRITE (5UL<<28) + #define TSCH_DEBUG_1_GENQ_SM_READ_POP (6UL<<28) + + u32_t tsch_debug_2; + #define TSCH_DEBUG_2_LO_PRI_CID (0x1fffUL<<0) + #define TSCH_DEBUG_2_LO_PRI_REQ (1UL<<15) + #define TSCH_DEBUG_2_HI_PRI_CID (0x1fffUL<<16) + #define TSCH_DEBUG_2_HI_PRI_REQ (1UL<<31) + + u32_t tsch_debug_3; + #define TSCH_DEBUG_3_CNTX_AD (0x1fffUL<<0) + #define TSCH_DEBUG_3_CNTX_GO (1UL<<15) + #define TSCH_DEBUG_3_CON_TYP (0x3UL<<24) + #define TSCH_DEBUG_3_L2_PT (0x3UL<<28) + #define TSCH_DEBUG_3_L2_REQ (1UL<<31) + + u32_t tsch_debug_4; + #define TSCH_DEBUG_4_ACK_SM (0x3UL<<4) + #define TSCH_DEBUG_4_ACK_SM_IDLE (0UL<<4) + #define TSCH_DEBUG_4_ACK_SM_READ (1UL<<4) + #define TSCH_DEBUG_4_ACK_SM_WRITE (2UL<<4) + #define TSCH_DEBUG_4_ACK_SM_ACK (3UL<<4) + #define TSCH_DEBUG_4_DO_NXT_L5 (1UL<<8) + #define TSCH_DEBUG_4_CNTX_BUSY (1UL<<9) + #define TSCH_DEBUG_4_TBDR_SM (1UL<<11) + #define TSCH_DEBUG_4_LIST_RM_SM (0x3UL<<12) + #define TSCH_DEBUG_4_LIST_RM_SM_IDLE (0UL<<12) + #define TSCH_DEBUG_4_LIST_RM_SM_REM_L2 (1UL<<12) + #define TSCH_DEBUG_4_LIST_RM_SM_REM_L4 (2UL<<12) + #define TSCH_DEBUG_4_CNTX_WR_SM (0x3UL<<16) + #define TSCH_DEBUG_4_CNTX_WR_SM_IDLE (0UL<<16) + #define TSCH_DEBUG_4_CNTX_WR_SM_CTX_WR (1UL<<16) + #define TSCH_DEBUG_4_CNTX_WR_SM_CTX_WR_DONE (2UL<<16) + #define TSCH_DEBUG_4_PROC_SM (0xfUL<<20) + #define TSCH_DEBUG_4_PROC_SM_IDLE (0UL<<20) + #define TSCH_DEBUG_4_PROC_SM_1ST_STAGE (1UL<<20) + #define TSCH_DEBUG_4_PROC_SM_L2_1ST_STAGE (2UL<<20) + #define TSCH_DEBUG_4_PROC_SM_L2_2ND_STAGE (3UL<<20) + #define TSCH_DEBUG_4_PROC_SM_L4_1ST_STAGE (4UL<<20) + #define TSCH_DEBUG_4_PROC_SM_L4_2ND_STAGE (5UL<<20) + #define TSCH_DEBUG_4_PROC_SM_L5_STAGE (6UL<<20) + #define TSCH_DEBUG_4_PROC_SM_L5_WAIT (7UL<<20) + #define TSCH_DEBUG_4_PROC_SM_L5_HALT (8UL<<20) + #define TSCH_DEBUG_4_CNTX_RD_SM (0x7UL<<24) + #define TSCH_DEBUG_4_CNTX_RD_SM_IDLE (0UL<<24) + #define TSCH_DEBUG_4_CNTX_RD_SM_L2_1ST_READ (1UL<<24) + #define TSCH_DEBUG_4_CNTX_RD_SM_L2_LAST_READ (2UL<<24) + #define TSCH_DEBUG_4_CNTX_RD_SM_L4_1ST_READ (3UL<<24) + #define TSCH_DEBUG_4_CNTX_RD_SM_L4_LAST_READ (4UL<<24) + #define TSCH_DEBUG_4_CNTX_RD_SM_L5_1ST_READ (5UL<<24) + #define TSCH_DEBUG_4_CNTX_RD_SM_L5_LAST_READ (6UL<<24) + #define TSCH_DEBUG_4_LOCK_SM (0x7UL<<28) + #define TSCH_DEBUG_4_LOCK_SM_IDLE (0UL<<28) + #define TSCH_DEBUG_4_LOCK_SM_REQ (1UL<<28) + #define TSCH_DEBUG_4_LOCK_SM_WAIT (2UL<<28) + #define TSCH_DEBUG_4_LOCK_SM_UNLOCK (3UL<<28) + #define TSCH_DEBUG_4_LOCK_SM_TBDR (4UL<<28) + #define TSCH_DEBUG_4_LOCK_SM_UPDATE (5UL<<28) + #define TSCH_DEBUG_4_LOCK_SM_ENABLE (6UL<<28) + + u32_t tsch_debug_5; + #define TSCH_DEBUG_5_TSCH_DBG5_NU_SLT_SZ (0xffffffffUL<<0) + + u32_t unused_1[11]; + u32_t tsch_debug_vect_peek; + #define TSCH_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define TSCH_DEBUG_VECT_PEEK_1_EN (1UL<<11) + #define TSCH_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define TSCH_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define TSCH_DEBUG_VECT_PEEK_2_EN (1UL<<27) + #define TSCH_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t unused_2[207]; + tx_scheduler_enqueue_t tsch_tschq; + u32_t unused_3[12]; + u32_t tsch_ftq_cmd; + #define TSCH_FTQ_CMD_OFFSET (0x3ffUL<<0) + #define TSCH_FTQ_CMD_WR_TOP (1UL<<10) + #define TSCH_FTQ_CMD_WR_TOP_0 (0UL<<10) + #define TSCH_FTQ_CMD_WR_TOP_1 (1UL<<10) + #define TSCH_FTQ_CMD_SFT_RESET (1UL<<25) + #define TSCH_FTQ_CMD_RD_DATA (1UL<<26) + #define TSCH_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define TSCH_FTQ_CMD_ADD_DATA (1UL<<28) + #define TSCH_FTQ_CMD_INTERVENE_CLR (1UL<<29) + #define TSCH_FTQ_CMD_POP (1UL<<30) + #define TSCH_FTQ_CMD_BUSY (1UL<<31) + + u32_t tsch_ftq_ctl; + #define TSCH_FTQ_CTL_INTERVENE (1UL<<0) + #define TSCH_FTQ_CTL_OVERFLOW (1UL<<1) + #define TSCH_FTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define TSCH_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define TSCH_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + +} tsch_reg_t; + +typedef tsch_reg_t tx_scheduler_reg_t; + +/* + * tx_bd_read_enqueue definition + * offset: 0000 + */ +typedef struct tx_bd_read_enqueue +{ + u32_t tx_bd_read_enqueue_cid; + #define TX_BD_READ_ENQUEUE_CID_VALUE (0x3fffUL<<7) + + u32_t tx_bd_read_enqueue_bseq; + u32_t tx_bd_read_enqueue_wd2; + #define TX_BD_READ_ENQUEUE_FLAGS_FLAGS_QUICK_CID_ENA (1<<24) + #define TX_BD_READ_ENQUEUE_FLAGS_FLAGS_QUICK_CID_TE (0x3<<25) + #define TX_BD_READ_ENQUEUE_FLAGS_FLAGS_QUICK_CATCHUP_TE (1<<27) + #define TX_BD_READ_ENQUEUE_FLAGS_FLAGS_RSVD_XI (1<<25) + #define TX_BD_READ_ENQUEUE_FLAGS_FLAGS_BORROWED_XI (1<<26) + #define TX_BD_READ_ENQUEUE_FLAGS_FLAGS_BSEQ_INVLD_XI (1<<27) + #define TX_BD_READ_ENQUEUE_FLAGS_FLAGS_S_RETRAN (1<<28) + + u32_t tx_bd_read_enqueue_tcp_rcv_nxt; + u32_t tx_bd_read_enqueue_wd4; + #define TX_BD_READ_ENQUEUE_TCMD_FNUM_VALUE (0x3f<<24) + +} tx_bd_read_enqueue_t; + + +/* + * tbdr_reg definition + * offset: 0x5000 + */ +typedef struct tbdr_reg +{ + u32_t tbdr_command; + #define TBDR_COMMAND_ENABLE (1UL<<0) + #define TBDR_COMMAND_SOFT_RST (1UL<<1) + #define TBDR_COMMAND_MSTR_ABORT (1UL<<4) + + u32_t tbdr_status; + #define TBDR_STATUS_DMA_WAIT (1UL<<0) + #define TBDR_STATUS_FTQ_WAIT (1UL<<1) + #define TBDR_STATUS_FIFO_OVERFLOW (1UL<<2) + #define TBDR_STATUS_FIFO_UNDERFLOW (1UL<<3) + #define TBDR_STATUS_SEARCHMISS_ERROR (1UL<<4) + #define TBDR_STATUS_FTQ_ENTRY_CNT (1UL<<5) + #define TBDR_STATUS_BURST_CNT (1UL<<6) + + u32_t tbdr_config; + #define TBDR_CONFIG_MAX_BDS (0xffUL<<0) + #define TBDR_CONFIG_SWAP_MODE (1UL<<8) + #define TBDR_CONFIG_PRIORITY (1UL<<9) + #define TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1UL<<10) + #define TBDR_CONFIG_PAGE_SIZE (0xfUL<<24) + #define TBDR_CONFIG_PAGE_SIZE_256 (0UL<<24) + #define TBDR_CONFIG_PAGE_SIZE_512 (1UL<<24) + #define TBDR_CONFIG_PAGE_SIZE_1K (2UL<<24) + #define TBDR_CONFIG_PAGE_SIZE_2K (3UL<<24) + #define TBDR_CONFIG_PAGE_SIZE_4K (4UL<<24) + #define TBDR_CONFIG_PAGE_SIZE_8K (5UL<<24) + #define TBDR_CONFIG_PAGE_SIZE_16K (6UL<<24) + #define TBDR_CONFIG_PAGE_SIZE_32K (7UL<<24) + #define TBDR_CONFIG_PAGE_SIZE_64K (8UL<<24) + #define TBDR_CONFIG_PAGE_SIZE_128K (9UL<<24) + #define TBDR_CONFIG_PAGE_SIZE_256K (10UL<<24) + #define TBDR_CONFIG_PAGE_SIZE_512K (11UL<<24) + #define TBDR_CONFIG_PAGE_SIZE_1M (12UL<<24) + + u32_t tbdr_debug_vect_peek; + #define TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) + #define TBDR_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) + #define TBDR_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t tbdr_cksum_error_status; + #define TBDR_CKSUM_ERROR_STATUS_CALCULATED (0xffffUL<<0) + #define TBDR_CKSUM_ERROR_STATUS_EXPECTED (0xffffUL<<16) + + u32_t unused_0[235]; + tx_bd_read_enqueue_t tbdr_tbdrq; + u32_t unused_1[9]; + u32_t tbdr_ftq_cmd; + #define TBDR_FTQ_CMD_OFFSET (0x3ffUL<<0) + #define TBDR_FTQ_CMD_WR_TOP (1UL<<10) + #define TBDR_FTQ_CMD_WR_TOP_0 (0UL<<10) + #define TBDR_FTQ_CMD_WR_TOP_1 (1UL<<10) + #define TBDR_FTQ_CMD_SFT_RESET (1UL<<25) + #define TBDR_FTQ_CMD_RD_DATA (1UL<<26) + #define TBDR_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define TBDR_FTQ_CMD_ADD_DATA (1UL<<28) + #define TBDR_FTQ_CMD_INTERVENE_CLR (1UL<<29) + #define TBDR_FTQ_CMD_POP (1UL<<30) + #define TBDR_FTQ_CMD_BUSY (1UL<<31) + + u32_t tbdr_ftq_ctl; + #define TBDR_FTQ_CTL_INTERVENE (1UL<<0) + #define TBDR_FTQ_CTL_OVERFLOW (1UL<<1) + #define TBDR_FTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define TBDR_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define TBDR_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + +} tbdr_reg_t; + +typedef tbdr_reg_t tx_bd_read_reg_t; + +/* + * tbdc_reg definition + * offset: 0x5400 + */ +typedef struct tbdc_reg +{ + u32_t tbdc_command; + #define TBDC_COMMAND_CMD_ENABLED (1UL<<0) + #define TBDC_COMMAND_CMD_FLUSH (1UL<<1) + #define TBDC_COMMAND_CMD_SOFT_RST (1UL<<2) + #define TBDC_COMMAND_CMD_REG_ARB (1UL<<3) + #define TBDC_COMMAND_WRCHK_RANGE_ERROR (1UL<<4) + #define TBDC_COMMAND_WRCHK_ALL_ONES_ERROR (1UL<<5) + #define TBDC_COMMAND_WRCHK_ALL_ZEROS_ERROR (1UL<<6) + #define TBDC_COMMAND_WRCHK_ANY_ONES_ERROR (1UL<<7) + #define TBDC_COMMAND_WRCHK_ANY_ZEROS_ERROR (1UL<<8) + + u32_t tbdc_status; + #define TBDC_STATUS_FREE_CNT (0x3fUL<<0) + + u32_t tbdc_control; + #define TBDC_CONTROL_RANGE (1UL<<0) + #define TBDC_CONTROL_ALL_ONES (1UL<<1) + #define TBDC_CONTROL_ALL_ZEROS (1UL<<2) + #define TBDC_CONTROL_ANY_ONES (1UL<<3) + #define TBDC_CONTROL_ANY_ZEROS (1UL<<4) + + u32_t tbdc_bd_haddr_hi; + u32_t tbdc_bd_haddr_lo; + u32_t tbdc_bd_nbytes; + #define TBDC_BD_NBYTES_NBYTES (0xffffUL<<0) + + u32_t tbdc_bd_flags; + #define TBDC_BD_FLAGS_FLAGS (0xffffUL<<0) + + u32_t tbdc_bd_reserved; + #define TBDC_BD_RESERVED_VALUE (0xffffUL<<0) + + u32_t tbdc_bd_vlan_tag; + #define TBDC_BD_VLAN_TAG_VLAN_TAG (0xffffUL<<0) + + u32_t tbdc_bd_addr; + #define TBDC_BD_ADDR_ADDRESS (0xffUL<<0) + #define TBDC_BD_ADDR_HIT (1UL<<8) + + u32_t tbdc_bd_hiaddr; + #define TBDC_BD_HIADDR_HIADDR (0xffUL<<0) + + u32_t tbdc_bdidx; + #define TBDC_BDIDX_BDIDX (0xffffUL<<0) + #define TBDC_BDIDX_CMD (0xffUL<<24) + + u32_t tbdc_cid; + #define TBDC_CID_CID (0x3fffUL<<7) + + u32_t tbdc_cam_opcode; + #define TBDC_CAM_OPCODE_OPCODE (0x7UL<<0) + #define TBDC_CAM_OPCODE_OPCODE_SEARCH (0UL<<0) + #define TBDC_CAM_OPCODE_OPCODE_CACHE_WRITE (1UL<<0) + #define TBDC_CAM_OPCODE_OPCODE_INVALIDATE (2UL<<0) + #define TBDC_CAM_OPCODE_OPCODE_CAM_WRITE (4UL<<0) + #define TBDC_CAM_OPCODE_OPCODE_CAM_READ (5UL<<0) + #define TBDC_CAM_OPCODE_OPCODE_RAM_WRITE (6UL<<0) + #define TBDC_CAM_OPCODE_OPCODE_RAM_READ (7UL<<0) + #define TBDC_CAM_OPCODE_SMASK_BDIDX (1UL<<4) + #define TBDC_CAM_OPCODE_SMASK_CID (1UL<<5) + #define TBDC_CAM_OPCODE_SMASK_CMD (1UL<<6) + #define TBDC_CAM_OPCODE_WMT_FAILED (1UL<<7) + #define TBDC_CAM_OPCODE_CAM_VALIDS (0xffUL<<8) + + u32_t tbdc_haddr_hi; + u32_t tbdc_haddr_lo; + u32_t tbdc_debug_vect_peek; + #define TBDC_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define TBDC_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) + #define TBDC_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define TBDC_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define TBDC_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) + #define TBDC_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t unused_0[239]; +} tbdc_reg_t; + +typedef tbdc_reg_t tx_bd_cache_reg_t; + +/* + * tx_dma_enqueue definition + * offset: 0000 + */ +typedef struct tx_dma_enqueue +{ + u32_t tx_dma_enqueue_cid; + #define TX_DMA_ENQUEUE_CID_VALUE (0x3fffUL<<7) + + u32_t tx_dma_enqueue_wd1; + #define TX_DMA_ENQUEUE_TDMA_BIDX (0xffff<<16) + #define TX_DMA_ENQUEUE_TDMA_BOFF (0xffff<<0) + + u32_t tx_dma_enqueue_tdma_bseq; + u32_t tx_dma_enqueue_tdma_snd_next; + u32_t tx_dma_enqueue_wd4; + #define TX_DMA_ENQUEUE_TDMA_CMD (0xff<<24) + #define TX_DMA_ENQUEUE_XNUM (0xff<<16) + #define TX_DMA_ENQUEUE_KNUM (0xff<<8) + + u32_t tx_dma_enqueue_flags_flags; + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_PLUS_TWO (1UL<<0) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_TCP_UDP_CKSUM (1UL<<1) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_IP_CKSUM (1UL<<2) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_INCR_CMD (1UL<<3) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_COAL_NOW (1UL<<4) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_DONT_GEN_CRC (1UL<<5) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_LAST_PKT (1UL<<6) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_PKT_FRAG (1UL<<7) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_QUICK_CID_ENA (1UL<<9) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_QUICK_CID_TE (0x3UL<<10) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_RSVD_FUTURE_XI (0x3UL<<10) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_L5_PAGE_MODE (1UL<<12) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_COMPLETE (1UL<<13) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_RETRAN (1UL<<14) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_END_PADDING (0xfUL<<16) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_USAGE_CNT (1UL<<20) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_USAGE_CNT_AUTODECREMENT (0UL<<20) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_USAGE_CNT_DONOTDECREMENT (1UL<<20) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_BSEQ_INVLD (1UL<<21) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_WORK_AROUND (0x3UL<<22) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE_SZ (0x3UL<<25) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_4 (0UL<<25) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_8 (1UL<<25) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_12 (2UL<<25) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_16 (3UL<<25) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE0 (1UL<<28) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE1 (1UL<<29) + #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE2 (1UL<<30) + + u32_t tx_dma_enqueue_wd6; + #define TX_DMA_ENQUEUE_NBYTES_VALUE (0x3fff<<16) + #define TX_DMA_ENQUEUE_HOLE0_BOFF_VALUE (0x3fff<<0) + + u32_t tx_dma_enqueue_wd7; + #define TX_DMA_ENQUEUE_HOLE1_BOFF_VALUE (0x3fff<<16) + #define TX_DMA_ENQUEUE_HOLE2_BOFF_VALUE (0x3fff<<0) + + u32_t tx_dma_enqueue_hole0_fill; + u32_t tx_dma_enqueue_hole1_fill; + u32_t tx_dma_enqueue_hole2_fill; + u32_t tx_dma_enqueue_wd11; + #define TX_DMA_ENQUEUE_TCMD_FNUM_VALUE (0x3f<<24) + #define TX_DMA_ENQUEUE_TXP_ACT_CMD (0xff<<16) + +} tx_dma_enqueue_t; + + +/* + * tdma_reg definition + * offset: 0x5c00 + */ +typedef struct tdma_reg +{ + u32_t tdma_command; + #define TDMA_COMMAND_ENABLED (1UL<<0) + #define TDMA_COMMAND_MASTER_ABORT (1UL<<4) + #define TDMA_COMMAND_CS16_ERR (1UL<<5) + #define TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1UL<<7) + #define TDMA_COMMAND_MASK_CS1 (1UL<<20) + #define TDMA_COMMAND_MASK_CS2 (1UL<<21) + #define TDMA_COMMAND_MASK_CS3 (1UL<<22) + #define TDMA_COMMAND_MASK_CS4 (1UL<<23) + #define TDMA_COMMAND_FORCE_ILOCK_CKERR (1UL<<24) + #define TDMA_COMMAND_OFIFO_CLR (1UL<<30) + #define TDMA_COMMAND_IFIFO_CLR (1UL<<31) + + u32_t tdma_status; + #define TDMA_STATUS_DMA_WAIT (1UL<<0) + #define TDMA_STATUS_PAYLOAD_WAIT (1UL<<1) + #define TDMA_STATUS_PATCH_FTQ_WAIT (1UL<<2) + #define TDMA_STATUS_LOCK_WAIT (1UL<<3) + #define TDMA_STATUS_FTQ_ENTRY_CNT (1UL<<16) + #define TDMA_STATUS_BURST_CNT (1UL<<17) + #define TDMA_STATUS_MAX_IFIFO_DEPTH (0x3fUL<<20) + #define TDMA_STATUS_OFIFO_OVERFLOW (1UL<<30) + #define TDMA_STATUS_IFIFO_OVERFLOW (1UL<<31) + + u32_t tdma_config; + #define TDMA_CONFIG_ONE_DMA (1UL<<0) + #define TDMA_CONFIG_ONE_RECORD (1UL<<1) + #define TDMA_CONFIG_NUM_DMA_CHAN (0x3UL<<2) + #define TDMA_CONFIG_NUM_DMA_CHAN_0 (0UL<<2) + #define TDMA_CONFIG_NUM_DMA_CHAN_1 (1UL<<2) + #define TDMA_CONFIG_NUM_DMA_CHAN_2 (2UL<<2) + #define TDMA_CONFIG_NUM_DMA_CHAN_3 (3UL<<2) + #define TDMA_CONFIG_LIMIT_SZ (0xfUL<<4) + #define TDMA_CONFIG_LIMIT_SZ_64 (0UL<<4) + #define TDMA_CONFIG_LIMIT_SZ_128 (4UL<<4) + #define TDMA_CONFIG_LIMIT_SZ_256 (6UL<<4) + #define TDMA_CONFIG_LIMIT_SZ_512 (8UL<<4) + #define TDMA_CONFIG_LINE_SZ (0xfUL<<8) + #define TDMA_CONFIG_LINE_SZ_64 (0UL<<8) + #define TDMA_CONFIG_LINE_SZ_128 (4UL<<8) + #define TDMA_CONFIG_LINE_SZ_256 (6UL<<8) + #define TDMA_CONFIG_LINE_SZ_512 (8UL<<8) + #define TDMA_CONFIG_ALIGN_ENA (1UL<<15) + #define TDMA_CONFIG_CHK_L2_BD (1UL<<16) + #define TDMA_CONFIG_CMPL_ENTRY (1UL<<17) + #define TDMA_CONFIG_OFIFO_CMP (1UL<<19) + #define TDMA_CONFIG_OFIFO_CMP_3 (0UL<<19) + #define TDMA_CONFIG_OFIFO_CMP_2 (1UL<<19) + #define TDMA_CONFIG_FIFO_CMP_TE (0xfUL<<20) + #define TDMA_CONFIG_IFIFO_DEPTH_XI (0x7UL<<20) + #define TDMA_CONFIG_IFIFO_DEPTH_0_XI (0UL<<20) + #define TDMA_CONFIG_IFIFO_DEPTH_4_XI (1UL<<20) + #define TDMA_CONFIG_IFIFO_DEPTH_8_XI (2UL<<20) + #define TDMA_CONFIG_IFIFO_DEPTH_16_XI (3UL<<20) + #define TDMA_CONFIG_IFIFO_DEPTH_32_XI (4UL<<20) + #define TDMA_CONFIG_IFIFO_DEPTH_64_XI (5UL<<20) + #define TDMA_CONFIG_FIFO_CMP_EN_XI (1UL<<23) + #define TDMA_CONFIG_BYTES_OST_XI (0x7UL<<24) + #define TDMA_CONFIG_BYTES_OST_512_XI (0UL<<24) + #define TDMA_CONFIG_BYTES_OST_1024_XI (1UL<<24) + #define TDMA_CONFIG_BYTES_OST_2048_XI (2UL<<24) + #define TDMA_CONFIG_BYTES_OST_4096_XI (3UL<<24) + #define TDMA_CONFIG_BYTES_OST_8192_XI (4UL<<24) + #define TDMA_CONFIG_BYTES_OST_16384_XI (5UL<<24) + #define TDMA_CONFIG_HC_BYPASS_XI (1UL<<27) + #define TDMA_CONFIG_LCL_MRRS_XI (0x7UL<<28) + #define TDMA_CONFIG_LCL_MRRS_128_XI (0UL<<28) + #define TDMA_CONFIG_LCL_MRRS_256_XI (1UL<<28) + #define TDMA_CONFIG_LCL_MRRS_512_XI (2UL<<28) + #define TDMA_CONFIG_LCL_MRRS_1024_XI (3UL<<28) + #define TDMA_CONFIG_LCL_MRRS_2048_XI (4UL<<28) + #define TDMA_CONFIG_LCL_MRRS_4096_XI (5UL<<28) + #define TDMA_CONFIG_LCL_MRRS_EN_XI (1UL<<31) + + u32_t tdma_payload_prod; + #define TDMA_PAYLOAD_PROD_VALUE (0x1fffUL<<3) + + u32_t tdma_dbg_watchdog; + u32_t tdma_dbg_trigger; + u32_t unused_0[26]; + u32_t tdma_dmad_fsm; + #define TDMA_DMAD_FSM_BD_INVLD (1UL<<0) + #define TDMA_DMAD_FSM_PUSH (0xfUL<<4) + #define TDMA_DMAD_FSM_ARB_TBDC (0x3UL<<8) + #define TDMA_DMAD_FSM_ARB_CTX (1UL<<12) + #define TDMA_DMAD_FSM_DR_INTF (1UL<<16) + #define TDMA_DMAD_FSM_DMAD (0x7UL<<20) + #define TDMA_DMAD_FSM_BD (0xfUL<<24) + + u32_t tdma_dmad_status; + #define TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3UL<<0) + #define TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3UL<<4) + #define TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3UL<<8) + #define TDMA_DMAD_STATUS_IFTQ_ENUM (0xfUL<<12) + + u32_t tdma_dr_intf_fsm; + #define TDMA_DR_INTF_FSM_L2_COMP (0x3UL<<0) + #define TDMA_DR_INTF_FSM_TPATQ (0x7UL<<4) + #define TDMA_DR_INTF_FSM_TPBUF (0x3UL<<8) + #define TDMA_DR_INTF_FSM_DR_BUF (0x7UL<<12) + #define TDMA_DR_INTF_FSM_DMAD (0x7UL<<16) + + u32_t tdma_dr_intf_status; + #define TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7UL<<0) + #define TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3UL<<4) + #define TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7UL<<8) + #define TDMA_DR_INTF_STATUS_NXT_PNTR (0xfUL<<12) + #define TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7UL<<16) + + u32_t tdma_push_fsm; + u32_t tdma_bd_if_debug; + u32_t tdma_dmad_if_debug; + u32_t tdma_ctx_if_debug; + u32_t tdma_tpbuf_if_debug; + u32_t tdma_dr_if_debug; + u32_t tdma_tpatq_if_debug; + u32_t tdma_tdma_ilock_cksum; + #define TDMA_TDMA_ILOCK_CKSUM_CALCULATED (0xffffUL<<0) + #define TDMA_TDMA_ILOCK_CKSUM_EXPECTED (0xffffUL<<16) + + u32_t tdma_tdma_pcie_cksum; + #define TDMA_TDMA_PCIE_CKSUM_CALCULATED (0xffffUL<<0) + #define TDMA_TDMA_PCIE_CKSUM_EXPECTED (0xffffUL<<16) + + u32_t unused_1[195]; + tx_dma_enqueue_t tdma_tdmaq; + u32_t unused_2[2]; + u32_t tdma_ftq_cmd; + #define TDMA_FTQ_CMD_OFFSET (0x3ffUL<<0) + #define TDMA_FTQ_CMD_WR_TOP (1UL<<10) + #define TDMA_FTQ_CMD_WR_TOP_0 (0UL<<10) + #define TDMA_FTQ_CMD_WR_TOP_1 (1UL<<10) + #define TDMA_FTQ_CMD_SFT_RESET (1UL<<25) + #define TDMA_FTQ_CMD_RD_DATA (1UL<<26) + #define TDMA_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define TDMA_FTQ_CMD_ADD_DATA (1UL<<28) + #define TDMA_FTQ_CMD_INTERVENE_CLR (1UL<<29) + #define TDMA_FTQ_CMD_POP (1UL<<30) + #define TDMA_FTQ_CMD_BUSY (1UL<<31) + + u32_t tdma_ftq_ctl; + #define TDMA_FTQ_CTL_INTERVENE (1UL<<0) + #define TDMA_FTQ_CTL_OVERFLOW (1UL<<1) + #define TDMA_FTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define TDMA_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define TDMA_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + +} tdma_reg_t; + +typedef tdma_reg_t tx_dma_reg_t; + +/* + * dbu_reg definition + * offset: 0x6000 + */ +typedef struct dbu_reg +{ + u32_t dbu_cmd; + #define DBU_CMD_ENABLE (1UL<<0) + #define DBU_CMD_RX_ERROR (1UL<<1) + #define DBU_CMD_RX_OVERFLOW (1UL<<2) + + u32_t dbu_status; + #define DBU_STATUS_RXDATA_VALID (1UL<<0) + #define DBU_STATUS_TXDATA_OCCUPIED (1UL<<1) + + u32_t dbu_config; + #define DBU_CONFIG_TIMING_OVERRIDE (1UL<<0) + #define DBU_CONFIG_DEBUGSM_ENABLE (1UL<<1) + #define DBU_CONFIG_CRLF_ENABLE (1UL<<2) + + u32_t dbu_timing; + #define DBU_TIMING_FB_SMPL_OFFSET (0xffffUL<<0) + #define DBU_TIMING_BIT_INTERVAL (0xffffUL<<16) + + u32_t dbu_rxdata; + #define DBU_RXDATA_VALUE (0xffUL<<0) + #define DBU_RXDATA_ERROR (1UL<<8) + + u32_t dbu_txdata; + #define DBU_TXDATA_VALUE (0xffUL<<0) + + u32_t unused_0[250]; +} dbu_reg_t; + + +/* + * debug_reg definition + * offset: 0x7000 + */ +typedef struct debug_reg +{ + u32_t debug_command; + u32_t unused_0[511]; +} debug_reg_t; + + +/* + * tx_assembler_enqueue definition + * offset: 0000 + */ +typedef struct tx_assembler_enqueue +{ + u32_t tx_assembler_enqueue_wd0; + #define TX_ASSEMBLER_ENQUEUE_HDR_SKIP_VALUE (0xff<<16) + #define TX_ASSEMBLER_ENQUEUE_HDR_POST_SKIP_VALUE (0xff<<0) + + u32_t tx_assembler_enqueue_wd1; + #define TX_ASSEMBLER_ENQUEUE_HDR_SIZE_VALUE_TE (0xff<<16) + #define TX_ASSEMBLER_ENQUEUE_HDR_SIZE_VALUE_XI (0x1fff<<16) + #define TX_ASSEMBLER_ENQUEUE_PAYLOAD_SKIP_VALUE (0x3fff<<0) + + u32_t tx_assembler_enqueue_wd2; + #define TX_ASSEMBLER_ENQUEUE_PAYLOAD_SIZE_VALUE (0x3fff<<16) + #define TX_ASSEMBLER_ENQUEUE_FLAGS_PKT_END (1<<0) + #define TX_ASSEMBLER_ENQUEUE_FLAGS_MGMT_PACKET (1<<1) + #define TX_ASSEMBLER_ENQUEUE_FLAGS_CATCHUP_PACKET (1<<2) + #define TX_ASSEMBLER_ENQUEUE_FLAGS_DONT_GEN_CRC (1<<3) + #define TX_ASSEMBLER_ENQUEUE_FLAGS_DROP (1<<4) + #define TX_ASSEMBLER_ENQUEUE_FLAGS_RESERVED (0x3<<5) + #define TX_ASSEMBLER_ENQUEUE_FLAGS_MGMT_PKT_TAG_TE (0xf<<8) + #define TX_ASSEMBLER_ENQUEUE_FLAGS_MGMT_PKT_TAG_XI (0x1f<<8) + #define TX_ASSEMBLER_ENQUEUE_FLAGS_CS16_VLD_XI (1<<15) + + u32_t tx_assembler_enqueue_wd3; + #define TX_ASSEMBLER_ENQUEUE_CS16_VALUE (0xffff<<16) + +} tx_assembler_enqueue_t; + + +/* + * tas_reg definition + * offset: 0x1c0000 + */ +typedef struct tas_reg +{ + u32_t tas_command; + #define TAS_COMMAND_TAS_ENABLE (1UL<<0) + #define TAS_COMMAND_TPBUF_ENABLE (1UL<<1) + #define TAS_COMMAND_THBUF_ENABLE (1UL<<2) + #define TAS_COMMAND_PKT_END_TOSHORT_ABORT (1UL<<5) + #define TAS_COMMAND_THBUF_INIT (1UL<<6) + #define TAS_COMMAND_TPBUF_INIT (1UL<<7) + #define TAS_COMMAND_RESET_STATE (1UL<<31) + + u32_t tas_status; + #define TAS_STATUS_ACPI_MODE (1UL<<0) + #define TAS_STATUS_KNUM_TAG (0xfUL<<4) + #define TAS_STATUS_MGMT_TAG_TE (0xfUL<<8) + #define TAS_STATUS_MGMT_TAG_XI (0x1fUL<<8) + #define TAS_STATUS_MAC_PKTS_STAT (1UL<<16) + #define TAS_STATUS_CU_PKTS_STAT (1UL<<17) + + u32_t tas_config; + #define TAS_CONFIG_PAYLOAD_MAX_LOW (0x3ffUL<<0) + #define TAS_CONFIG_PAYLOAD_MAX (0x1fUL<<10) + + u32_t tas_payload_cons; + #define TAS_PAYLOAD_CONS_VALUE (0x1fffUL<<3) + + u32_t tas_header_cons; + #define TAS_HEADER_CONS_VALUE (0x7ffUL<<3) + + u32_t tas_debug_vect_peek; + u32_t unused_0[234]; + tx_assembler_enqueue_t tas_tasq; + u32_t unused_1[10]; + u32_t tas_ftq_cmd; + #define TAS_FTQ_CMD_OFFSET (0x3ffUL<<0) + #define TAS_FTQ_CMD_WR_TOP (1UL<<10) + #define TAS_FTQ_CMD_WR_TOP_0 (0UL<<10) + #define TAS_FTQ_CMD_WR_TOP_1 (1UL<<10) + #define TAS_FTQ_CMD_SFT_RESET (1UL<<25) + #define TAS_FTQ_CMD_RD_DATA (1UL<<26) + #define TAS_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define TAS_FTQ_CMD_ADD_DATA (1UL<<28) + #define TAS_FTQ_CMD_INTERVENE_CLR (1UL<<29) + #define TAS_FTQ_CMD_POP (1UL<<30) + #define TAS_FTQ_CMD_BUSY (1UL<<31) + + u32_t tas_ftq_ctl; + #define TAS_FTQ_CTL_INTERVENE (1UL<<0) + #define TAS_FTQ_CTL_OVERFLOW (1UL<<1) + #define TAS_FTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define TAS_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define TAS_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + + u32_t unused_2[32512]; + u32_t tas_thbuf[2048]; + u32_t unused_3[14336]; + u32_t tas_tpbuf[6144]; + u32_t unused_4[10240]; +} tas_reg_t; + +typedef tas_reg_t tx_assembler_reg_t; + +/* + * hc_reg definition + * offset: 0x6800 + */ +typedef struct hc_reg +{ + u32_t hc_command; + #define HC_COMMAND_ENABLE (1UL<<0) + #define HC_COMMAND_SKIP_ABORT (1UL<<4) + #define HC_COMMAND_COAL_NOW (1UL<<16) + #define HC_COMMAND_COAL_NOW_WO_INT (1UL<<17) + #define HC_COMMAND_STATS_NOW (1UL<<18) + #define HC_COMMAND_FORCE_INT (0x3UL<<19) + #define HC_COMMAND_FORCE_INT_NULL (0UL<<19) + #define HC_COMMAND_FORCE_INT_HIGH (1UL<<19) + #define HC_COMMAND_FORCE_INT_LOW (2UL<<19) + #define HC_COMMAND_FORCE_INT_FREE (3UL<<19) + #define HC_COMMAND_CLR_STAT_NOW (1UL<<21) + #define HC_COMMAND_MAIN_PWR_INT (1UL<<22) + #define HC_COMMAND_COAL_ON_NEXT_EVENT (1UL<<27) + + u32_t hc_status; + #define HC_STATUS_MASTER_ABORT (1UL<<0) + #define HC_STATUS_PARITY_ERROR_STATE (1UL<<1) + #define HC_STATUS_PCI_CLK_CNT_STAT (1UL<<16) + #define HC_STATUS_CORE_CLK_CNT_STAT (1UL<<17) + #define HC_STATUS_NUM_STATUS_BLOCKS_STAT (1UL<<18) + #define HC_STATUS_NUM_INT_GEN_STAT (1UL<<19) + #define HC_STATUS_NUM_INT_MBOX_WR_STAT (1UL<<20) + #define HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1UL<<23) + #define HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1UL<<24) + #define HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1UL<<25) + + u32_t hc_config; + #define HC_CONFIG_COLLECT_STATS (1UL<<0) + #define HC_CONFIG_RX_TMR_MODE (1UL<<1) + #define HC_CONFIG_TX_TMR_MODE (1UL<<2) + #define HC_CONFIG_COM_TMR_MODE (1UL<<3) + #define HC_CONFIG_CMD_TMR_MODE (1UL<<4) + #define HC_CONFIG_STATISTIC_PRIORITY (1UL<<5) + #define HC_CONFIG_STATUS_PRIORITY (1UL<<6) + #define HC_CONFIG_STAT_MEM_ADDR (0xffUL<<8) + #define HC_CONFIG_PER_MODE (1UL<<16) + #define HC_CONFIG_ONE_SHOT (1UL<<17) + #define HC_CONFIG_USE_INT_PARAM (1UL<<18) + #define HC_CONFIG_SET_MASK_AT_RD (1UL<<19) + #define HC_CONFIG_PER_COLLECT_LIMIT (0xfUL<<20) + #define HC_CONFIG_SB_ADDR_INC (0x7UL<<24) + #define HC_CONFIG_SB_ADDR_INC_64B (0UL<<24) + #define HC_CONFIG_SB_ADDR_INC_128B (1UL<<24) + #define HC_CONFIG_SB_ADDR_INC_256B (2UL<<24) + #define HC_CONFIG_SB_ADDR_INC_512B (3UL<<24) + #define HC_CONFIG_SB_ADDR_INC_1024B (4UL<<24) + #define HC_CONFIG_SB_ADDR_INC_2048B (5UL<<24) + #define HC_CONFIG_SB_ADDR_INC_4096B (6UL<<24) + #define HC_CONFIG_SB_ADDR_INC_8192B (7UL<<24) + #define HC_CONFIG_GEN_STAT_AVG_INTR (1UL<<29) + #define HC_CONFIG_UNMASK_ALL (1UL<<30) + #define HC_CONFIG_TX_SEL (1UL<<31) + + u32_t hc_attn_bits_enable; + u32_t hc_status_addr_l; + u32_t hc_status_addr_h; + u32_t hc_statistics_addr_l; + u32_t hc_statistics_addr_h; + u32_t hc_tx_quick_cons_trip; + #define HC_TX_QUICK_CONS_TRIP_VALUE (0xffUL<<0) + #define HC_TX_QUICK_CONS_TRIP_INT (0xffUL<<16) + + u32_t hc_comp_prod_trip; + #define HC_COMP_PROD_TRIP_VALUE (0xffUL<<0) + #define HC_COMP_PROD_TRIP_INT (0xffUL<<16) + + u32_t hc_rx_quick_cons_trip; + #define HC_RX_QUICK_CONS_TRIP_VALUE (0xffUL<<0) + #define HC_RX_QUICK_CONS_TRIP_INT (0xffUL<<16) + + u32_t hc_rx_ticks; + #define HC_RX_TICKS_VALUE (0x3ffUL<<0) + #define HC_RX_TICKS_INT (0x3ffUL<<16) + + u32_t hc_tx_ticks; + #define HC_TX_TICKS_VALUE (0x3ffUL<<0) + #define HC_TX_TICKS_INT (0x3ffUL<<16) + + u32_t hc_com_ticks; + #define HC_COM_TICKS_VALUE (0x3ffUL<<0) + #define HC_COM_TICKS_INT (0x3ffUL<<16) + + u32_t hc_cmd_ticks; + #define HC_CMD_TICKS_VALUE (0x3ffUL<<0) + #define HC_CMD_TICKS_INT (0x3ffUL<<16) + + u32_t hc_periodic_ticks; + #define HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc_stat_collect_ticks; + #define HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffUL<<4) + + u32_t hc_stats_ticks; + #define HC_STATS_TICKS_HC_STAT_TICKS (0xffffUL<<8) + + u32_t hc_stats_interrupt_status; + #define HC_STATS_INTERRUPT_STATUS_SB_STATUS (0x1ffUL<<0) + #define HC_STATS_INTERRUPT_STATUS_INT_STATUS (0x1ffUL<<16) + + u32_t hc_stat_mem_data; + u32_t hc_stat_gen_sel_0; + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TE (0x7fUL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0_TE (0UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1_TE (1UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2_TE (2UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3_TE (3UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4_TE (4UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5_TE (5UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6_TE (6UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7_TE (7UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8_TE (8UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9_TE (9UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10_TE (10UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11_TE (11UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0_TE (12UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1_TE (13UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2_TE (14UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3_TE (15UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4_TE (16UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5_TE (17UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6_TE (18UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7_TE (19UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0_TE (20UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1_TE (21UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2_TE (22UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3_TE (23UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4_TE (24UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5_TE (25UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6_TE (26UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7_TE (27UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8_TE (28UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9_TE (29UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10_TE (30UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11_TE (31UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0_TE (32UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1_TE (33UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2_TE (34UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3_TE (35UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0_TE (36UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1_TE (37UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2_TE (38UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3_TE (39UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4_TE (40UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5_TE (41UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6_TE (42UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7_TE (43UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0_TE (44UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1_TE (45UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2_TE (46UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3_TE (47UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4_TE (48UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5_TE (49UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6_TE (50UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7_TE (51UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT_TE (52UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT_TE (53UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_TE (54UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_TE (55UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_TE (56UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_TE (59UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_TE (60UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_TE (61UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT_TE (62UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT_TE (63UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT_TE (64UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT_TE (65UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT_TE (66UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT_TE (67UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT_TE (68UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT_TE (69UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT_TE (70UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT_TE (71UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT_TE (72UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT_TE (73UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT_TE (74UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT_TE (75UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT_TE (76UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT_TE (77UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT_TE (78UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT_TE (79UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT_TE (80UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT_TE (81UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT_TE (82UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT_TE (83UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT_TE (84UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT_TE (85UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT_TE (86UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT_TE (87UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT_TE (88UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT_TE (89UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT_TE (90UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT_TE (91UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT_TE (92UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT_TE (93UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT_TE (94UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64_TE (95UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64_TE (96UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS_TE (97UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS_TE (98UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT_TE (99UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT_TE (100UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT_TE (101UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT_TE (102UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT_TE (103UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT_TE (104UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT_TE (105UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT_TE (106UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT_TE (107UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT_TE (108UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT_TE (109UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT_TE (110UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT_TE (111UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT_TE (112UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT_TE (113UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT_TE (114UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0_TE (115UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1_TE (116UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2_TE (117UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3_TE (118UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4_TE (119UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5_TE (120UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS_TE (121UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS_TE (122UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT_TE (127UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_1_TE (0x7fUL<<8) + #define HC_STAT_GEN_SEL_0_GEN_SEL_2_TE (0x7fUL<<16) + #define HC_STAT_GEN_SEL_0_GEN_SEL_3_TE (0x7fUL<<24) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_XI (0xffUL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0_XI (0UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1_XI (1UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2_XI (2UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3_XI (3UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4_XI (4UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5_XI (5UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6_XI (6UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7_XI (7UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8_XI (8UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9_XI (9UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10_XI (10UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11_XI (11UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0_XI (12UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1_XI (13UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2_XI (14UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3_XI (15UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4_XI (16UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5_XI (17UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6_XI (18UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7_XI (19UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0_XI (20UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1_XI (21UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2_XI (22UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3_XI (23UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4_XI (24UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5_XI (25UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6_XI (26UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7_XI (27UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8_XI (28UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9_XI (29UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10_XI (30UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11_XI (31UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0_XI (32UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1_XI (33UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2_XI (34UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3_XI (35UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0_XI (36UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1_XI (37UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2_XI (38UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3_XI (39UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4_XI (40UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5_XI (41UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6_XI (42UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7_XI (43UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0_XI (44UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1_XI (45UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2_XI (46UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3_XI (47UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4_XI (48UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5_XI (49UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6_XI (50UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7_XI (51UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI (52UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT_XI (53UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_XI (54UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_XI (55UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_XI (56UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI (57UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI (58UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_XI (59UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_XI (60UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_XI (61UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT_XI (62UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT_XI (63UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT_XI (64UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT_XI (65UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT_XI (66UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT_XI (67UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT_XI (68UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT_XI (69UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT_XI (70UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT_XI (71UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT_XI (72UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT_XI (73UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT_XI (74UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT_XI (75UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT_XI (76UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT_XI (77UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT_XI (78UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT_XI (79UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT_XI (80UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT_XI (81UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT_XI (82UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT_XI (83UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT_XI (84UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI (85UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI (86UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI (87UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI (88UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI (89UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI (90UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI (91UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI (92UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI (93UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI (94UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64_XI (95UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64_XI (96UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS_XI (97UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS_XI (98UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT_XI (99UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT_XI (100UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT_XI (101UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT_XI (102UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT_XI (103UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT_XI (104UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT_XI (105UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT_XI (106UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT_XI (107UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT_XI (108UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT_XI (109UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT_XI (110UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT_XI (111UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT_XI (112UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT_XI (113UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT_XI (114UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0_XI (115UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1_XI (116UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2_XI (117UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3_XI (118UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4_XI (119UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5_XI (120UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS_XI (121UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS_XI (122UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI (123UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI (124UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI (125UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI (126UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT_XI (127UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI (128UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI (129UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI (130UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI (131UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI (132UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI (133UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI (134UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI (135UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI (136UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI (137UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI (138UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI (139UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI (140UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI (141UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI (142UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI (143UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI (144UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI (145UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI (146UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI (147UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI (148UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI (149UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI (150UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI (151UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI (152UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI (153UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI (154UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI (155UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI (156UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI (157UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI (158UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI (159UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI (160UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI (161UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI (162UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI (163UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI (164UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI (165UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI (166UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI (167UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI (168UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI (169UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI (170UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI (171UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI (172UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI (173UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI (174UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI (175UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI (176UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI (177UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI (178UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S15_XI (179UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S16_XI (180UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S17_XI (181UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S18_XI (182UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S19_XI (183UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S20_XI (184UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S21_XI (185UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S22_XI (186UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S23_XI (187UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S24_XI (188UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S25_XI (189UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S26_XI (190UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S27_XI (191UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S28_XI (192UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S29_XI (193UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S30_XI (194UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S31_XI (195UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S32_XI (196UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S33_XI (197UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S34_XI (198UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S35_XI (199UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S36_XI (200UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S37_XI (201UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S38_XI (202UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S39_XI (203UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S40_XI (204UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S41_XI (205UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S42_XI (206UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S43_XI (207UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S44_XI (208UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S45_XI (209UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S46_XI (210UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S47_XI (211UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S48_XI (212UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S49_XI (213UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S50_XI (214UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S51_XI (215UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S52_XI (216UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S53_XI (217UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S54_XI (218UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S55_XI (219UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S56_XI (220UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S57_XI (221UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S58_XI (222UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S59_XI (223UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S60_XI (224UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S61_XI (225UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S62_XI (226UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S63_XI (227UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S64_XI (228UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S65_XI (229UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S66_XI (230UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S67_XI (231UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S68_XI (232UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S69_XI (233UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S70_XI (234UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S71_XI (235UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S72_XI (236UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S73_XI (237UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S74_XI (238UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S75_XI (239UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S76_XI (240UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S77_XI (241UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S78_XI (242UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S79_XI (243UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S80_XI (244UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S81_XI (245UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S82_XI (246UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S83_XI (247UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S84_XI (248UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S85_XI (249UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S86_XI (250UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S87_XI (251UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S88_XI (252UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S89_XI (253UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S90_XI (254UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S91_XI (255UL<<0) + #define HC_STAT_GEN_SEL_0_GEN_SEL_1_XI (0xffUL<<8) + #define HC_STAT_GEN_SEL_0_GEN_SEL_2_XI (0xffUL<<16) + #define HC_STAT_GEN_SEL_0_GEN_SEL_3_XI (0xffUL<<24) + + u32_t hc_stat_gen_sel_1; + #define HC_STAT_GEN_SEL_1_GEN_SEL_4_TE (0x7fUL<<0) + #define HC_STAT_GEN_SEL_1_GEN_SEL_5_TE (0x7fUL<<8) + #define HC_STAT_GEN_SEL_1_GEN_SEL_6_TE (0x7fUL<<16) + #define HC_STAT_GEN_SEL_1_GEN_SEL_7_TE (0x7fUL<<24) + #define HC_STAT_GEN_SEL_1_GEN_SEL_4_XI (0xffUL<<0) + #define HC_STAT_GEN_SEL_1_GEN_SEL_5_XI (0xffUL<<8) + #define HC_STAT_GEN_SEL_1_GEN_SEL_6_XI (0xffUL<<16) + #define HC_STAT_GEN_SEL_1_GEN_SEL_7_XI (0xffUL<<24) + + u32_t hc_stat_gen_sel_2; + #define HC_STAT_GEN_SEL_2_GEN_SEL_8_TE (0x7fUL<<0) + #define HC_STAT_GEN_SEL_2_GEN_SEL_9_TE (0x7fUL<<8) + #define HC_STAT_GEN_SEL_2_GEN_SEL_10_TE (0x7fUL<<16) + #define HC_STAT_GEN_SEL_2_GEN_SEL_11_TE (0x7fUL<<24) + #define HC_STAT_GEN_SEL_2_GEN_SEL_8_XI (0xffUL<<0) + #define HC_STAT_GEN_SEL_2_GEN_SEL_9_XI (0xffUL<<8) + #define HC_STAT_GEN_SEL_2_GEN_SEL_10_XI (0xffUL<<16) + #define HC_STAT_GEN_SEL_2_GEN_SEL_11_XI (0xffUL<<24) + + u32_t hc_stat_gen_sel_3; + #define HC_STAT_GEN_SEL_3_GEN_SEL_12_TE (0x7fUL<<0) + #define HC_STAT_GEN_SEL_3_GEN_SEL_13_TE (0x7fUL<<8) + #define HC_STAT_GEN_SEL_3_GEN_SEL_14_TE (0x7fUL<<16) + #define HC_STAT_GEN_SEL_3_GEN_SEL_15_TE (0x7fUL<<24) + #define HC_STAT_GEN_SEL_3_GEN_SEL_12_XI (0xffUL<<0) + #define HC_STAT_GEN_SEL_3_GEN_SEL_13_XI (0xffUL<<8) + #define HC_STAT_GEN_SEL_3_GEN_SEL_14_XI (0xffUL<<16) + #define HC_STAT_GEN_SEL_3_GEN_SEL_15_XI (0xffUL<<24) + + u32_t unused_0[10]; + u32_t hc_stat_gen_stat[16]; + u32_t hc_stat_gen_stat_ac[16]; + u32_t hc_vis; + #define HC_VIS_STAT_BUILD_STATE (0xfUL<<0) + #define HC_VIS_STAT_BUILD_STATE_IDLE (0UL<<0) + #define HC_VIS_STAT_BUILD_STATE_START (1UL<<0) + #define HC_VIS_STAT_BUILD_STATE_REQUEST (2UL<<0) + #define HC_VIS_STAT_BUILD_STATE_UPDATE64 (3UL<<0) + #define HC_VIS_STAT_BUILD_STATE_UPDATE32 (4UL<<0) + #define HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5UL<<0) + #define HC_VIS_STAT_BUILD_STATE_DMA (6UL<<0) + #define HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7UL<<0) + #define HC_VIS_STAT_BUILD_STATE_MSI_LOW (8UL<<0) + #define HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9UL<<0) + #define HC_VIS_STAT_BUILD_STATE_MSI_DATA (10UL<<0) + #define HC_VIS_DMA_STAT_STATE (0xfUL<<8) + #define HC_VIS_DMA_STAT_STATE_IDLE (0UL<<8) + #define HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1UL<<8) + #define HC_VIS_DMA_STAT_STATE_STATUS_DMA (2UL<<8) + #define HC_VIS_DMA_STAT_STATE_WRITE_COMP (3UL<<8) + #define HC_VIS_DMA_STAT_STATE_COMP (4UL<<8) + #define HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5UL<<8) + #define HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6UL<<8) + #define HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7UL<<8) + #define HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8UL<<8) + #define HC_VIS_DMA_STAT_STATE_WAIT (9UL<<8) + #define HC_VIS_DMA_STAT_STATE_ABORT (15UL<<8) + #define HC_VIS_DMA_MSI_STATE (0x7UL<<12) + #define HC_VIS_STATISTIC_DMA_EN_STATE (0x3UL<<15) + #define HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0UL<<15) + #define HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1UL<<15) + #define HC_VIS_STATISTIC_DMA_EN_STATE_START (2UL<<15) + + u32_t hc_vis_1; + #define HC_VIS_1_HW_INTACK_STATE (1UL<<4) + #define HC_VIS_1_HW_INTACK_STATE_IDLE (0UL<<4) + #define HC_VIS_1_HW_INTACK_STATE_COUNT (1UL<<4) + #define HC_VIS_1_SW_INTACK_STATE (1UL<<5) + #define HC_VIS_1_SW_INTACK_STATE_IDLE (0UL<<5) + #define HC_VIS_1_SW_INTACK_STATE_COUNT (1UL<<5) + #define HC_VIS_1_DURING_SW_INTACK_STATE (1UL<<6) + #define HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0UL<<6) + #define HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1UL<<6) + #define HC_VIS_1_MAILBOX_COUNT_STATE (1UL<<7) + #define HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0UL<<7) + #define HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1UL<<7) + #define HC_VIS_1_RAM_RD_ARB_STATE (0xfUL<<17) + #define HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0UL<<17) + #define HC_VIS_1_RAM_RD_ARB_STATE_DMA (1UL<<17) + #define HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2UL<<17) + #define HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3UL<<17) + #define HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4UL<<17) + #define HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5UL<<17) + #define HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6UL<<17) + #define HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7UL<<17) + #define HC_VIS_1_RAM_WR_ARB_STATE (0x3UL<<21) + #define HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0UL<<21) + #define HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1UL<<21) + #define HC_VIS_1_INT_GEN_STATE (1UL<<23) + #define HC_VIS_1_INT_GEN_STATE_DLE (0UL<<23) + #define HC_VIS_1_INT_GEN_STATE_NTERRUPT (1UL<<23) + #define HC_VIS_1_STAT_CHAN_ID (0x7UL<<24) + #define HC_VIS_1_INT_B (1UL<<27) + + u32_t hc_debug_vect_peek; + #define HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define HC_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) + #define HC_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define HC_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) + #define HC_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t hc_coalesce_now; + #define HC_COALESCE_NOW_COAL_NOW (0x1ffUL<<1) + #define HC_COALESCE_NOW_COAL_NOW_WO_INT (0x1ffUL<<11) + #define HC_COALESCE_NOW_COAL_ON_NXT_EVENT (0x1ffUL<<21) + + u32_t hc_msix_bit_vector; + #define HC_MSIX_BIT_VECTOR_VAL (0x1ffUL<<0) + + u32_t unused_1[57]; + u32_t hc_sb_config_1; + #define HC_SB_CONFIG_1_RX_TMR_MODE (1UL<<1) + #define HC_SB_CONFIG_1_TX_TMR_MODE (1UL<<2) + #define HC_SB_CONFIG_1_COM_TMR_MODE (1UL<<3) + #define HC_SB_CONFIG_1_CMD_TMR_MODE (1UL<<4) + #define HC_SB_CONFIG_1_PER_MODE (1UL<<16) + #define HC_SB_CONFIG_1_ONE_SHOT (1UL<<17) + #define HC_SB_CONFIG_1_USE_INT_PARAM (1UL<<18) + #define HC_SB_CONFIG_1_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc_tx_quick_cons_trip_1; + #define HC_TX_QUICK_CONS_TRIP_1_VALUE (0xffUL<<0) + #define HC_TX_QUICK_CONS_TRIP_1_INT (0xffUL<<16) + + u32_t hc_comp_prod_trip_1; + #define HC_COMP_PROD_TRIP_1_VALUE (0xffUL<<0) + #define HC_COMP_PROD_TRIP_1_INT (0xffUL<<16) + + u32_t hc_rx_quick_cons_trip_1; + #define HC_RX_QUICK_CONS_TRIP_1_VALUE (0xffUL<<0) + #define HC_RX_QUICK_CONS_TRIP_1_INT (0xffUL<<16) + + u32_t hc_rx_ticks_1; + #define HC_RX_TICKS_1_VALUE (0x3ffUL<<0) + #define HC_RX_TICKS_1_INT (0x3ffUL<<16) + + u32_t hc_tx_ticks_1; + #define HC_TX_TICKS_1_VALUE (0x3ffUL<<0) + #define HC_TX_TICKS_1_INT (0x3ffUL<<16) + + u32_t hc_com_ticks_1; + #define HC_COM_TICKS_1_VALUE (0x3ffUL<<0) + #define HC_COM_TICKS_1_INT (0x3ffUL<<16) + + u32_t hc_cmd_ticks_1; + #define HC_CMD_TICKS_1_VALUE (0x3ffUL<<0) + #define HC_CMD_TICKS_1_INT (0x3ffUL<<16) + + u32_t hc_periodic_ticks_1; + #define HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc_sb_config_2; + #define HC_SB_CONFIG_2_RX_TMR_MODE (1UL<<1) + #define HC_SB_CONFIG_2_TX_TMR_MODE (1UL<<2) + #define HC_SB_CONFIG_2_COM_TMR_MODE (1UL<<3) + #define HC_SB_CONFIG_2_CMD_TMR_MODE (1UL<<4) + #define HC_SB_CONFIG_2_PER_MODE (1UL<<16) + #define HC_SB_CONFIG_2_ONE_SHOT (1UL<<17) + #define HC_SB_CONFIG_2_USE_INT_PARAM (1UL<<18) + #define HC_SB_CONFIG_2_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc_tx_quick_cons_trip_2; + #define HC_TX_QUICK_CONS_TRIP_2_VALUE (0xffUL<<0) + #define HC_TX_QUICK_CONS_TRIP_2_INT (0xffUL<<16) + + u32_t hc_comp_prod_trip_2; + #define HC_COMP_PROD_TRIP_2_VALUE (0xffUL<<0) + #define HC_COMP_PROD_TRIP_2_INT (0xffUL<<16) + + u32_t hc_rx_quick_cons_trip_2; + #define HC_RX_QUICK_CONS_TRIP_2_VALUE (0xffUL<<0) + #define HC_RX_QUICK_CONS_TRIP_2_INT (0xffUL<<16) + + u32_t hc_rx_ticks_2; + #define HC_RX_TICKS_2_VALUE (0x3ffUL<<0) + #define HC_RX_TICKS_2_INT (0x3ffUL<<16) + + u32_t hc_tx_ticks_2; + #define HC_TX_TICKS_2_VALUE (0x3ffUL<<0) + #define HC_TX_TICKS_2_INT (0x3ffUL<<16) + + u32_t hc_com_ticks_2; + #define HC_COM_TICKS_2_VALUE (0x3ffUL<<0) + #define HC_COM_TICKS_2_INT (0x3ffUL<<16) + + u32_t hc_cmd_ticks_2; + #define HC_CMD_TICKS_2_VALUE (0x3ffUL<<0) + #define HC_CMD_TICKS_2_INT (0x3ffUL<<16) + + u32_t hc_periodic_ticks_2; + #define HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc_sb_config_3; + #define HC_SB_CONFIG_3_RX_TMR_MODE (1UL<<1) + #define HC_SB_CONFIG_3_TX_TMR_MODE (1UL<<2) + #define HC_SB_CONFIG_3_COM_TMR_MODE (1UL<<3) + #define HC_SB_CONFIG_3_CMD_TMR_MODE (1UL<<4) + #define HC_SB_CONFIG_3_PER_MODE (1UL<<16) + #define HC_SB_CONFIG_3_ONE_SHOT (1UL<<17) + #define HC_SB_CONFIG_3_USE_INT_PARAM (1UL<<18) + #define HC_SB_CONFIG_3_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc_tx_quick_cons_trip_3; + #define HC_TX_QUICK_CONS_TRIP_3_VALUE (0xffUL<<0) + #define HC_TX_QUICK_CONS_TRIP_3_INT (0xffUL<<16) + + u32_t hc_comp_prod_trip_3; + #define HC_COMP_PROD_TRIP_3_VALUE (0xffUL<<0) + #define HC_COMP_PROD_TRIP_3_INT (0xffUL<<16) + + u32_t hc_rx_quick_cons_trip_3; + #define HC_RX_QUICK_CONS_TRIP_3_VALUE (0xffUL<<0) + #define HC_RX_QUICK_CONS_TRIP_3_INT (0xffUL<<16) + + u32_t hc_rx_ticks_3; + #define HC_RX_TICKS_3_VALUE (0x3ffUL<<0) + #define HC_RX_TICKS_3_INT (0x3ffUL<<16) + + u32_t hc_tx_ticks_3; + #define HC_TX_TICKS_3_VALUE (0x3ffUL<<0) + #define HC_TX_TICKS_3_INT (0x3ffUL<<16) + + u32_t hc_com_ticks_3; + #define HC_COM_TICKS_3_VALUE (0x3ffUL<<0) + #define HC_COM_TICKS_3_INT (0x3ffUL<<16) + + u32_t hc_cmd_ticks_3; + #define HC_CMD_TICKS_3_VALUE (0x3ffUL<<0) + #define HC_CMD_TICKS_3_INT (0x3ffUL<<16) + + u32_t hc_periodic_ticks_3; + #define HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc_sb_config_4; + #define HC_SB_CONFIG_4_RX_TMR_MODE (1UL<<1) + #define HC_SB_CONFIG_4_TX_TMR_MODE (1UL<<2) + #define HC_SB_CONFIG_4_COM_TMR_MODE (1UL<<3) + #define HC_SB_CONFIG_4_CMD_TMR_MODE (1UL<<4) + #define HC_SB_CONFIG_4_PER_MODE (1UL<<16) + #define HC_SB_CONFIG_4_ONE_SHOT (1UL<<17) + #define HC_SB_CONFIG_4_USE_INT_PARAM (1UL<<18) + #define HC_SB_CONFIG_4_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc_tx_quick_cons_trip_4; + #define HC_TX_QUICK_CONS_TRIP_4_VALUE (0xffUL<<0) + #define HC_TX_QUICK_CONS_TRIP_4_INT (0xffUL<<16) + + u32_t hc_comp_prod_trip_4; + #define HC_COMP_PROD_TRIP_4_VALUE (0xffUL<<0) + #define HC_COMP_PROD_TRIP_4_INT (0xffUL<<16) + + u32_t hc_rx_quick_cons_trip_4; + #define HC_RX_QUICK_CONS_TRIP_4_VALUE (0xffUL<<0) + #define HC_RX_QUICK_CONS_TRIP_4_INT (0xffUL<<16) + + u32_t hc_rx_ticks_4; + #define HC_RX_TICKS_4_VALUE (0x3ffUL<<0) + #define HC_RX_TICKS_4_INT (0x3ffUL<<16) + + u32_t hc_tx_ticks_4; + #define HC_TX_TICKS_4_VALUE (0x3ffUL<<0) + #define HC_TX_TICKS_4_INT (0x3ffUL<<16) + + u32_t hc_com_ticks_4; + #define HC_COM_TICKS_4_VALUE (0x3ffUL<<0) + #define HC_COM_TICKS_4_INT (0x3ffUL<<16) + + u32_t hc_cmd_ticks_4; + #define HC_CMD_TICKS_4_VALUE (0x3ffUL<<0) + #define HC_CMD_TICKS_4_INT (0x3ffUL<<16) + + u32_t hc_periodic_ticks_4; + #define HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc_sb_config_5; + #define HC_SB_CONFIG_5_RX_TMR_MODE (1UL<<1) + #define HC_SB_CONFIG_5_TX_TMR_MODE (1UL<<2) + #define HC_SB_CONFIG_5_COM_TMR_MODE (1UL<<3) + #define HC_SB_CONFIG_5_CMD_TMR_MODE (1UL<<4) + #define HC_SB_CONFIG_5_PER_MODE (1UL<<16) + #define HC_SB_CONFIG_5_ONE_SHOT (1UL<<17) + #define HC_SB_CONFIG_5_USE_INT_PARAM (1UL<<18) + #define HC_SB_CONFIG_5_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc_tx_quick_cons_trip_5; + #define HC_TX_QUICK_CONS_TRIP_5_VALUE (0xffUL<<0) + #define HC_TX_QUICK_CONS_TRIP_5_INT (0xffUL<<16) + + u32_t hc_comp_prod_trip_5; + #define HC_COMP_PROD_TRIP_5_VALUE (0xffUL<<0) + #define HC_COMP_PROD_TRIP_5_INT (0xffUL<<16) + + u32_t hc_rx_quick_cons_trip_5; + #define HC_RX_QUICK_CONS_TRIP_5_VALUE (0xffUL<<0) + #define HC_RX_QUICK_CONS_TRIP_5_INT (0xffUL<<16) + + u32_t hc_rx_ticks_5; + #define HC_RX_TICKS_5_VALUE (0x3ffUL<<0) + #define HC_RX_TICKS_5_INT (0x3ffUL<<16) + + u32_t hc_tx_ticks_5; + #define HC_TX_TICKS_5_VALUE (0x3ffUL<<0) + #define HC_TX_TICKS_5_INT (0x3ffUL<<16) + + u32_t hc_com_ticks_5; + #define HC_COM_TICKS_5_VALUE (0x3ffUL<<0) + #define HC_COM_TICKS_5_INT (0x3ffUL<<16) + + u32_t hc_cmd_ticks_5; + #define HC_CMD_TICKS_5_VALUE (0x3ffUL<<0) + #define HC_CMD_TICKS_5_INT (0x3ffUL<<16) + + u32_t hc_periodic_ticks_5; + #define HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc_sb_config_6; + #define HC_SB_CONFIG_6_RX_TMR_MODE (1UL<<1) + #define HC_SB_CONFIG_6_TX_TMR_MODE (1UL<<2) + #define HC_SB_CONFIG_6_COM_TMR_MODE (1UL<<3) + #define HC_SB_CONFIG_6_CMD_TMR_MODE (1UL<<4) + #define HC_SB_CONFIG_6_PER_MODE (1UL<<16) + #define HC_SB_CONFIG_6_ONE_SHOT (1UL<<17) + #define HC_SB_CONFIG_6_USE_INT_PARAM (1UL<<18) + #define HC_SB_CONFIG_6_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc_tx_quick_cons_trip_6; + #define HC_TX_QUICK_CONS_TRIP_6_VALUE (0xffUL<<0) + #define HC_TX_QUICK_CONS_TRIP_6_INT (0xffUL<<16) + + u32_t hc_comp_prod_trip_6; + #define HC_COMP_PROD_TRIP_6_VALUE (0xffUL<<0) + #define HC_COMP_PROD_TRIP_6_INT (0xffUL<<16) + + u32_t hc_rx_quick_cons_trip_6; + #define HC_RX_QUICK_CONS_TRIP_6_VALUE (0xffUL<<0) + #define HC_RX_QUICK_CONS_TRIP_6_INT (0xffUL<<16) + + u32_t hc_rx_ticks_6; + #define HC_RX_TICKS_6_VALUE (0x3ffUL<<0) + #define HC_RX_TICKS_6_INT (0x3ffUL<<16) + + u32_t hc_tx_ticks_6; + #define HC_TX_TICKS_6_VALUE (0x3ffUL<<0) + #define HC_TX_TICKS_6_INT (0x3ffUL<<16) + + u32_t hc_com_ticks_6; + #define HC_COM_TICKS_6_VALUE (0x3ffUL<<0) + #define HC_COM_TICKS_6_INT (0x3ffUL<<16) + + u32_t hc_cmd_ticks_6; + #define HC_CMD_TICKS_6_VALUE (0x3ffUL<<0) + #define HC_CMD_TICKS_6_INT (0x3ffUL<<16) + + u32_t hc_periodic_ticks_6; + #define HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc_sb_config_7; + #define HC_SB_CONFIG_7_RX_TMR_MODE (1UL<<1) + #define HC_SB_CONFIG_7_TX_TMR_MODE (1UL<<2) + #define HC_SB_CONFIG_7_COM_TMR_MODE (1UL<<3) + #define HC_SB_CONFIG_7_CMD_TMR_MODE (1UL<<4) + #define HC_SB_CONFIG_7_PER_MODE (1UL<<16) + #define HC_SB_CONFIG_7_ONE_SHOT (1UL<<17) + #define HC_SB_CONFIG_7_USE_INT_PARAM (1UL<<18) + #define HC_SB_CONFIG_7_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc_tx_quick_cons_trip_7; + #define HC_TX_QUICK_CONS_TRIP_7_VALUE (0xffUL<<0) + #define HC_TX_QUICK_CONS_TRIP_7_INT (0xffUL<<16) + + u32_t hc_comp_prod_trip_7; + #define HC_COMP_PROD_TRIP_7_VALUE (0xffUL<<0) + #define HC_COMP_PROD_TRIP_7_INT (0xffUL<<16) + + u32_t hc_rx_quick_cons_trip_7; + #define HC_RX_QUICK_CONS_TRIP_7_VALUE (0xffUL<<0) + #define HC_RX_QUICK_CONS_TRIP_7_INT (0xffUL<<16) + + u32_t hc_rx_ticks_7; + #define HC_RX_TICKS_7_VALUE (0x3ffUL<<0) + #define HC_RX_TICKS_7_INT (0x3ffUL<<16) + + u32_t hc_tx_ticks_7; + #define HC_TX_TICKS_7_VALUE (0x3ffUL<<0) + #define HC_TX_TICKS_7_INT (0x3ffUL<<16) + + u32_t hc_com_ticks_7; + #define HC_COM_TICKS_7_VALUE (0x3ffUL<<0) + #define HC_COM_TICKS_7_INT (0x3ffUL<<16) + + u32_t hc_cmd_ticks_7; + #define HC_CMD_TICKS_7_VALUE (0x3ffUL<<0) + #define HC_CMD_TICKS_7_INT (0x3ffUL<<16) + + u32_t hc_periodic_ticks_7; + #define HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc_sb_config_8; + #define HC_SB_CONFIG_8_RX_TMR_MODE (1UL<<1) + #define HC_SB_CONFIG_8_TX_TMR_MODE (1UL<<2) + #define HC_SB_CONFIG_8_COM_TMR_MODE (1UL<<3) + #define HC_SB_CONFIG_8_CMD_TMR_MODE (1UL<<4) + #define HC_SB_CONFIG_8_PER_MODE (1UL<<16) + #define HC_SB_CONFIG_8_ONE_SHOT (1UL<<17) + #define HC_SB_CONFIG_8_USE_INT_PARAM (1UL<<18) + #define HC_SB_CONFIG_8_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc_tx_quick_cons_trip_8; + #define HC_TX_QUICK_CONS_TRIP_8_VALUE (0xffUL<<0) + #define HC_TX_QUICK_CONS_TRIP_8_INT (0xffUL<<16) + + u32_t hc_comp_prod_trip_8; + #define HC_COMP_PROD_TRIP_8_VALUE (0xffUL<<0) + #define HC_COMP_PROD_TRIP_8_INT (0xffUL<<16) + + u32_t hc_rx_quick_cons_trip_8; + #define HC_RX_QUICK_CONS_TRIP_8_VALUE (0xffUL<<0) + #define HC_RX_QUICK_CONS_TRIP_8_INT (0xffUL<<16) + + u32_t hc_rx_ticks_8; + #define HC_RX_TICKS_8_VALUE (0x3ffUL<<0) + #define HC_RX_TICKS_8_INT (0x3ffUL<<16) + + u32_t hc_tx_ticks_8; + #define HC_TX_TICKS_8_VALUE (0x3ffUL<<0) + #define HC_TX_TICKS_8_INT (0x3ffUL<<16) + + u32_t hc_com_ticks_8; + #define HC_COM_TICKS_8_VALUE (0x3ffUL<<0) + #define HC_COM_TICKS_8_INT (0x3ffUL<<16) + + u32_t hc_cmd_ticks_8; + #define HC_CMD_TICKS_8_VALUE (0x3ffUL<<0) + #define HC_CMD_TICKS_8_INT (0x3ffUL<<16) + + u32_t hc_periodic_ticks_8; + #define HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t unused_2[56]; +} hc_reg_t; + +typedef hc_reg_t host_coalesce_reg_t; + +/* + * hc1_reg definition + * offset: 0x310000 + */ +typedef struct hc1_reg +{ + u32_t hc1_command; + #define HC1_COMMAND_ENABLE (1UL<<0) + #define HC1_COMMAND_COAL_NOW (1UL<<16) + #define HC1_COMMAND_COAL_NOW_WO_INT (1UL<<17) + #define HC1_COMMAND_STATS_NOW (1UL<<18) + #define HC1_COMMAND_FORCE_INT (0x3UL<<19) + #define HC1_COMMAND_FORCE_INT_NULL (0UL<<19) + #define HC1_COMMAND_FORCE_INT_HIGH (1UL<<19) + #define HC1_COMMAND_FORCE_INT_LOW (2UL<<19) + #define HC1_COMMAND_FORCE_INT_FREE (3UL<<19) + #define HC1_COMMAND_CLR_STAT_NOW (1UL<<21) + #define HC1_COMMAND_MAIN_PWR_INT (1UL<<22) + #define HC1_COMMAND_COAL_ON_NEXT_EVENT (1UL<<27) + + u32_t hc1_status; + #define HC1_STATUS_PARITY_ERROR_STATE (1UL<<1) + #define HC1_STATUS_CORE_CLK_CNT_STAT (1UL<<17) + #define HC1_STATUS_NUM_STATUS_BLOCKS_STAT (1UL<<18) + #define HC1_STATUS_NUM_INT_GEN_STAT (1UL<<19) + #define HC1_STATUS_NUM_INT_MBOX_WR_STAT (1UL<<20) + #define HC1_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1UL<<23) + #define HC1_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1UL<<24) + #define HC1_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1UL<<25) + + u32_t hc1_config; + #define HC1_CONFIG_COLLECT_STATS (1UL<<0) + #define HC1_CONFIG_RX_TMR_MODE (1UL<<1) + #define HC1_CONFIG_TX_TMR_MODE (1UL<<2) + #define HC1_CONFIG_COM_TMR_MODE (1UL<<3) + #define HC1_CONFIG_CMD_TMR_MODE (1UL<<4) + #define HC1_CONFIG_STATISTIC_PRIORITY (1UL<<5) + #define HC1_CONFIG_STATUS_PRIORITY (1UL<<6) + #define HC1_CONFIG_STAT_MEM_ADDR (0xffUL<<8) + #define HC1_CONFIG_PER_MODE (1UL<<16) + #define HC1_CONFIG_ONE_SHOT (1UL<<17) + #define HC1_CONFIG_USE_INT_PARAM (1UL<<18) + #define HC1_CONFIG_SET_MASK_AT_RD (1UL<<19) + #define HC1_CONFIG_PER_COLLECT_LIMIT (0xfUL<<20) + #define HC1_CONFIG_SB_ADDR_INC (0x7UL<<24) + #define HC1_CONFIG_SB_ADDR_INC_64B (0UL<<24) + #define HC1_CONFIG_SB_ADDR_INC_128B (1UL<<24) + #define HC1_CONFIG_SB_ADDR_INC_256B (2UL<<24) + #define HC1_CONFIG_SB_ADDR_INC_512B (3UL<<24) + #define HC1_CONFIG_SB_ADDR_INC_1024B (4UL<<24) + #define HC1_CONFIG_SB_ADDR_INC_2048B (5UL<<24) + #define HC1_CONFIG_SB_ADDR_INC_4096B (6UL<<24) + #define HC1_CONFIG_SB_ADDR_INC_8192B (7UL<<24) + #define HC1_CONFIG_GEN_STAT_AVG_INTR (1UL<<29) + #define HC1_CONFIG_UNMASK_ALL (1UL<<30) + #define HC1_CONFIG_TX_SEL (1UL<<31) + + u32_t hc1_attn_bits_enable; + u32_t hc1_status_addr_l; + u32_t hc1_status_addr_h; + u32_t hc1_statistics_addr_l; + u32_t hc1_statistics_addr_h; + u32_t hc1_tx_quick_cons_trip; + #define HC1_TX_QUICK_CONS_TRIP_VALUE (0xffUL<<0) + #define HC1_TX_QUICK_CONS_TRIP_INT (0xffUL<<16) + + u32_t hc1_comp_prod_trip; + #define HC1_COMP_PROD_TRIP_VALUE (0xffUL<<0) + #define HC1_COMP_PROD_TRIP_INT (0xffUL<<16) + + u32_t hc1_rx_quick_cons_trip; + #define HC1_RX_QUICK_CONS_TRIP_VALUE (0xffUL<<0) + #define HC1_RX_QUICK_CONS_TRIP_INT (0xffUL<<16) + + u32_t hc1_rx_ticks; + #define HC1_RX_TICKS_VALUE (0x3ffUL<<0) + #define HC1_RX_TICKS_INT (0x3ffUL<<16) + + u32_t hc1_tx_ticks; + #define HC1_TX_TICKS_VALUE (0x3ffUL<<0) + #define HC1_TX_TICKS_INT (0x3ffUL<<16) + + u32_t hc1_com_ticks; + #define HC1_COM_TICKS_VALUE (0x3ffUL<<0) + #define HC1_COM_TICKS_INT (0x3ffUL<<16) + + u32_t hc1_cmd_ticks; + #define HC1_CMD_TICKS_VALUE (0x3ffUL<<0) + #define HC1_CMD_TICKS_INT (0x3ffUL<<16) + + u32_t hc1_periodic_ticks; + #define HC1_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC1_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc1_stat_collect_ticks; + #define HC1_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffUL<<4) + + u32_t hc1_stats_ticks; + #define HC1_STATS_TICKS_HC_STAT_TICKS (0xffffUL<<8) + + u32_t hc1_stats_interrupt_status; + #define HC1_STATS_INTERRUPT_STATUS_SB_STATUS (0x1ffUL<<0) + #define HC1_STATS_INTERRUPT_STATUS_INT_STATUS (0x1ffUL<<16) + + u32_t hc1_stat_mem_data; + u32_t hc1_stat_gen_sel_0; + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0 (0xffUL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP (52UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0 (57UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1 (58UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2 (85UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3 (86UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4 (87UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5 (88UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6 (89UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7 (90UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8 (91UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9 (92UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10 (93UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW (94UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT (123UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT (124UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS (125UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES (126UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1 (128UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1 (129UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1 (130UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1 (131UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1 (132UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1 (133UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2 (134UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2 (135UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2 (136UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2 (137UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2 (138UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2 (139UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3 (140UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3 (141UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3 (142UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3 (143UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3 (144UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3 (145UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4 (146UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4 (147UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4 (148UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4 (149UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4 (150UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4 (151UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5 (152UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5 (153UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5 (154UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5 (155UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5 (156UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5 (157UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6 (158UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6 (159UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6 (160UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6 (161UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6 (162UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6 (163UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7 (164UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7 (165UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7 (166UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7 (167UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7 (168UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7 (169UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8 (170UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8 (171UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8 (172UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8 (173UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8 (174UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8 (175UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT (176UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT (177UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT (178UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S15 (179UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S16 (180UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S17 (181UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S18 (182UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S19 (183UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S20 (184UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S21 (185UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S22 (186UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S23 (187UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S24 (188UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S25 (189UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S26 (190UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S27 (191UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S28 (192UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S29 (193UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S30 (194UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S31 (195UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S32 (196UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S33 (197UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S34 (198UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S35 (199UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S36 (200UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S37 (201UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S38 (202UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S39 (203UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S40 (204UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S41 (205UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S42 (206UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S43 (207UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S44 (208UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S45 (209UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S46 (210UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S47 (211UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S48 (212UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S49 (213UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S50 (214UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S51 (215UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S52 (216UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S53 (217UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S54 (218UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S55 (219UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S56 (220UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S57 (221UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S58 (222UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S59 (223UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S60 (224UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S61 (225UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S62 (226UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S63 (227UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S64 (228UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S65 (229UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S66 (230UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S67 (231UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S68 (232UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S69 (233UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S70 (234UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S71 (235UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S72 (236UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S73 (237UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S74 (238UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S75 (239UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S76 (240UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S77 (241UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S78 (242UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S79 (243UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S80 (244UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S81 (245UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S82 (246UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S83 (247UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S84 (248UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S85 (249UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S86 (250UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S87 (251UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S88 (252UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S89 (253UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S90 (254UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S91 (255UL<<0) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_1 (0xffUL<<8) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_2 (0xffUL<<16) + #define HC1_STAT_GEN_SEL_0_GEN_SEL_3 (0xffUL<<24) + + u32_t hc1_stat_gen_sel_1; + #define HC1_STAT_GEN_SEL_1_GEN_SEL_4 (0xffUL<<0) + #define HC1_STAT_GEN_SEL_1_GEN_SEL_5 (0xffUL<<8) + #define HC1_STAT_GEN_SEL_1_GEN_SEL_6 (0xffUL<<16) + #define HC1_STAT_GEN_SEL_1_GEN_SEL_7 (0xffUL<<24) + + u32_t hc1_stat_gen_sel_2; + #define HC1_STAT_GEN_SEL_2_GEN_SEL_8 (0xffUL<<0) + #define HC1_STAT_GEN_SEL_2_GEN_SEL_9 (0xffUL<<8) + #define HC1_STAT_GEN_SEL_2_GEN_SEL_10 (0xffUL<<16) + #define HC1_STAT_GEN_SEL_2_GEN_SEL_11 (0xffUL<<24) + + u32_t hc1_stat_gen_sel_3; + #define HC1_STAT_GEN_SEL_3_GEN_SEL_12 (0xffUL<<0) + #define HC1_STAT_GEN_SEL_3_GEN_SEL_13 (0xffUL<<8) + #define HC1_STAT_GEN_SEL_3_GEN_SEL_14 (0xffUL<<16) + #define HC1_STAT_GEN_SEL_3_GEN_SEL_15 (0xffUL<<24) + + u32_t unused_0[10]; + u32_t hc1_stat_gen_stat[16]; + u32_t hc1_stat_gen_stat_ac[16]; + u32_t hc1_vis; + u32_t hc1_vis_1; + u32_t hc1_debug_vect_peek; + #define HC1_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define HC1_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) + #define HC1_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define HC1_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define HC1_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) + #define HC1_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t hc1_coalesce_now; + #define HC1_COALESCE_NOW_COAL_NOW (0x1ffUL<<1) + #define HC1_COALESCE_NOW_COAL_NOW_WO_INT (0x1ffUL<<11) + #define HC1_COALESCE_NOW_COAL_ON_NXT_EVENT (0x1ffUL<<21) + + u32_t hc1_msix_bit_vector; + #define HC1_MSIX_BIT_VECTOR_VAL (0x1ffUL<<0) + + u32_t unused_1[57]; + u32_t hc1_sb_config_1; + #define HC1_SB_CONFIG_1_RX_TMR_MODE (1UL<<1) + #define HC1_SB_CONFIG_1_TX_TMR_MODE (1UL<<2) + #define HC1_SB_CONFIG_1_COM_TMR_MODE (1UL<<3) + #define HC1_SB_CONFIG_1_CMD_TMR_MODE (1UL<<4) + #define HC1_SB_CONFIG_1_PER_MODE (1UL<<16) + #define HC1_SB_CONFIG_1_ONE_SHOT (1UL<<17) + #define HC1_SB_CONFIG_1_USE_INT_PARAM (1UL<<18) + #define HC1_SB_CONFIG_1_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc1_tx_quick_cons_trip_1; + #define HC1_TX_QUICK_CONS_TRIP_1_VALUE (0xffUL<<0) + #define HC1_TX_QUICK_CONS_TRIP_1_INT (0xffUL<<16) + + u32_t hc1_comp_prod_trip_1; + #define HC1_COMP_PROD_TRIP_1_VALUE (0xffUL<<0) + #define HC1_COMP_PROD_TRIP_1_INT (0xffUL<<16) + + u32_t hc1_rx_quick_cons_trip_1; + #define HC1_RX_QUICK_CONS_TRIP_1_VALUE (0xffUL<<0) + #define HC1_RX_QUICK_CONS_TRIP_1_INT (0xffUL<<16) + + u32_t hc1_rx_ticks_1; + #define HC1_RX_TICKS_1_VALUE (0x3ffUL<<0) + #define HC1_RX_TICKS_1_INT (0x3ffUL<<16) + + u32_t hc1_tx_ticks_1; + #define HC1_TX_TICKS_1_VALUE (0x3ffUL<<0) + #define HC1_TX_TICKS_1_INT (0x3ffUL<<16) + + u32_t hc1_com_ticks_1; + #define HC1_COM_TICKS_1_VALUE (0x3ffUL<<0) + #define HC1_COM_TICKS_1_INT (0x3ffUL<<16) + + u32_t hc1_cmd_ticks_1; + #define HC1_CMD_TICKS_1_VALUE (0x3ffUL<<0) + #define HC1_CMD_TICKS_1_INT (0x3ffUL<<16) + + u32_t hc1_periodic_ticks_1; + #define HC1_PERIODIC_TICKS_1_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC1_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc1_sb_config_2; + #define HC1_SB_CONFIG_2_RX_TMR_MODE (1UL<<1) + #define HC1_SB_CONFIG_2_TX_TMR_MODE (1UL<<2) + #define HC1_SB_CONFIG_2_COM_TMR_MODE (1UL<<3) + #define HC1_SB_CONFIG_2_CMD_TMR_MODE (1UL<<4) + #define HC1_SB_CONFIG_2_PER_MODE (1UL<<16) + #define HC1_SB_CONFIG_2_ONE_SHOT (1UL<<17) + #define HC1_SB_CONFIG_2_USE_INT_PARAM (1UL<<18) + #define HC1_SB_CONFIG_2_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc1_tx_quick_cons_trip_2; + #define HC1_TX_QUICK_CONS_TRIP_2_VALUE (0xffUL<<0) + #define HC1_TX_QUICK_CONS_TRIP_2_INT (0xffUL<<16) + + u32_t hc1_comp_prod_trip_2; + #define HC1_COMP_PROD_TRIP_2_VALUE (0xffUL<<0) + #define HC1_COMP_PROD_TRIP_2_INT (0xffUL<<16) + + u32_t hc1_rx_quick_cons_trip_2; + #define HC1_RX_QUICK_CONS_TRIP_2_VALUE (0xffUL<<0) + #define HC1_RX_QUICK_CONS_TRIP_2_INT (0xffUL<<16) + + u32_t hc1_rx_ticks_2; + #define HC1_RX_TICKS_2_VALUE (0x3ffUL<<0) + #define HC1_RX_TICKS_2_INT (0x3ffUL<<16) + + u32_t hc1_tx_ticks_2; + #define HC1_TX_TICKS_2_VALUE (0x3ffUL<<0) + #define HC1_TX_TICKS_2_INT (0x3ffUL<<16) + + u32_t hc1_com_ticks_2; + #define HC1_COM_TICKS_2_VALUE (0x3ffUL<<0) + #define HC1_COM_TICKS_2_INT (0x3ffUL<<16) + + u32_t hc1_cmd_ticks_2; + #define HC1_CMD_TICKS_2_VALUE (0x3ffUL<<0) + #define HC1_CMD_TICKS_2_INT (0x3ffUL<<16) + + u32_t hc1_periodic_ticks_2; + #define HC1_PERIODIC_TICKS_2_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC1_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc1_sb_config_3; + #define HC1_SB_CONFIG_3_RX_TMR_MODE (1UL<<1) + #define HC1_SB_CONFIG_3_TX_TMR_MODE (1UL<<2) + #define HC1_SB_CONFIG_3_COM_TMR_MODE (1UL<<3) + #define HC1_SB_CONFIG_3_CMD_TMR_MODE (1UL<<4) + #define HC1_SB_CONFIG_3_PER_MODE (1UL<<16) + #define HC1_SB_CONFIG_3_ONE_SHOT (1UL<<17) + #define HC1_SB_CONFIG_3_USE_INT_PARAM (1UL<<18) + #define HC1_SB_CONFIG_3_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc1_tx_quick_cons_trip_3; + #define HC1_TX_QUICK_CONS_TRIP_3_VALUE (0xffUL<<0) + #define HC1_TX_QUICK_CONS_TRIP_3_INT (0xffUL<<16) + + u32_t hc1_comp_prod_trip_3; + #define HC1_COMP_PROD_TRIP_3_VALUE (0xffUL<<0) + #define HC1_COMP_PROD_TRIP_3_INT (0xffUL<<16) + + u32_t hc1_rx_quick_cons_trip_3; + #define HC1_RX_QUICK_CONS_TRIP_3_VALUE (0xffUL<<0) + #define HC1_RX_QUICK_CONS_TRIP_3_INT (0xffUL<<16) + + u32_t hc1_rx_ticks_3; + #define HC1_RX_TICKS_3_VALUE (0x3ffUL<<0) + #define HC1_RX_TICKS_3_INT (0x3ffUL<<16) + + u32_t hc1_tx_ticks_3; + #define HC1_TX_TICKS_3_VALUE (0x3ffUL<<0) + #define HC1_TX_TICKS_3_INT (0x3ffUL<<16) + + u32_t hc1_com_ticks_3; + #define HC1_COM_TICKS_3_VALUE (0x3ffUL<<0) + #define HC1_COM_TICKS_3_INT (0x3ffUL<<16) + + u32_t hc1_cmd_ticks_3; + #define HC1_CMD_TICKS_3_VALUE (0x3ffUL<<0) + #define HC1_CMD_TICKS_3_INT (0x3ffUL<<16) + + u32_t hc1_periodic_ticks_3; + #define HC1_PERIODIC_TICKS_3_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC1_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc1_sb_config_4; + #define HC1_SB_CONFIG_4_RX_TMR_MODE (1UL<<1) + #define HC1_SB_CONFIG_4_TX_TMR_MODE (1UL<<2) + #define HC1_SB_CONFIG_4_COM_TMR_MODE (1UL<<3) + #define HC1_SB_CONFIG_4_CMD_TMR_MODE (1UL<<4) + #define HC1_SB_CONFIG_4_PER_MODE (1UL<<16) + #define HC1_SB_CONFIG_4_ONE_SHOT (1UL<<17) + #define HC1_SB_CONFIG_4_USE_INT_PARAM (1UL<<18) + #define HC1_SB_CONFIG_4_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc1_tx_quick_cons_trip_4; + #define HC1_TX_QUICK_CONS_TRIP_4_VALUE (0xffUL<<0) + #define HC1_TX_QUICK_CONS_TRIP_4_INT (0xffUL<<16) + + u32_t hc1_comp_prod_trip_4; + #define HC1_COMP_PROD_TRIP_4_VALUE (0xffUL<<0) + #define HC1_COMP_PROD_TRIP_4_INT (0xffUL<<16) + + u32_t hc1_rx_quick_cons_trip_4; + #define HC1_RX_QUICK_CONS_TRIP_4_VALUE (0xffUL<<0) + #define HC1_RX_QUICK_CONS_TRIP_4_INT (0xffUL<<16) + + u32_t hc1_rx_ticks_4; + #define HC1_RX_TICKS_4_VALUE (0x3ffUL<<0) + #define HC1_RX_TICKS_4_INT (0x3ffUL<<16) + + u32_t hc1_tx_ticks_4; + #define HC1_TX_TICKS_4_VALUE (0x3ffUL<<0) + #define HC1_TX_TICKS_4_INT (0x3ffUL<<16) + + u32_t hc1_com_ticks_4; + #define HC1_COM_TICKS_4_VALUE (0x3ffUL<<0) + #define HC1_COM_TICKS_4_INT (0x3ffUL<<16) + + u32_t hc1_cmd_ticks_4; + #define HC1_CMD_TICKS_4_VALUE (0x3ffUL<<0) + #define HC1_CMD_TICKS_4_INT (0x3ffUL<<16) + + u32_t hc1_periodic_ticks_4; + #define HC1_PERIODIC_TICKS_4_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC1_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc1_sb_config_5; + #define HC1_SB_CONFIG_5_RX_TMR_MODE (1UL<<1) + #define HC1_SB_CONFIG_5_TX_TMR_MODE (1UL<<2) + #define HC1_SB_CONFIG_5_COM_TMR_MODE (1UL<<3) + #define HC1_SB_CONFIG_5_CMD_TMR_MODE (1UL<<4) + #define HC1_SB_CONFIG_5_PER_MODE (1UL<<16) + #define HC1_SB_CONFIG_5_ONE_SHOT (1UL<<17) + #define HC1_SB_CONFIG_5_USE_INT_PARAM (1UL<<18) + #define HC1_SB_CONFIG_5_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc1_tx_quick_cons_trip_5; + #define HC1_TX_QUICK_CONS_TRIP_5_VALUE (0xffUL<<0) + #define HC1_TX_QUICK_CONS_TRIP_5_INT (0xffUL<<16) + + u32_t hc1_comp_prod_trip_5; + #define HC1_COMP_PROD_TRIP_5_VALUE (0xffUL<<0) + #define HC1_COMP_PROD_TRIP_5_INT (0xffUL<<16) + + u32_t hc1_rx_quick_cons_trip_5; + #define HC1_RX_QUICK_CONS_TRIP_5_VALUE (0xffUL<<0) + #define HC1_RX_QUICK_CONS_TRIP_5_INT (0xffUL<<16) + + u32_t hc1_rx_ticks_5; + #define HC1_RX_TICKS_5_VALUE (0x3ffUL<<0) + #define HC1_RX_TICKS_5_INT (0x3ffUL<<16) + + u32_t hc1_tx_ticks_5; + #define HC1_TX_TICKS_5_VALUE (0x3ffUL<<0) + #define HC1_TX_TICKS_5_INT (0x3ffUL<<16) + + u32_t hc1_com_ticks_5; + #define HC1_COM_TICKS_5_VALUE (0x3ffUL<<0) + #define HC1_COM_TICKS_5_INT (0x3ffUL<<16) + + u32_t hc1_cmd_ticks_5; + #define HC1_CMD_TICKS_5_VALUE (0x3ffUL<<0) + #define HC1_CMD_TICKS_5_INT (0x3ffUL<<16) + + u32_t hc1_periodic_ticks_5; + #define HC1_PERIODIC_TICKS_5_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC1_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc1_sb_config_6; + #define HC1_SB_CONFIG_6_RX_TMR_MODE (1UL<<1) + #define HC1_SB_CONFIG_6_TX_TMR_MODE (1UL<<2) + #define HC1_SB_CONFIG_6_COM_TMR_MODE (1UL<<3) + #define HC1_SB_CONFIG_6_CMD_TMR_MODE (1UL<<4) + #define HC1_SB_CONFIG_6_PER_MODE (1UL<<16) + #define HC1_SB_CONFIG_6_ONE_SHOT (1UL<<17) + #define HC1_SB_CONFIG_6_USE_INT_PARAM (1UL<<18) + #define HC1_SB_CONFIG_6_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc1_tx_quick_cons_trip_6; + #define HC1_TX_QUICK_CONS_TRIP_6_VALUE (0xffUL<<0) + #define HC1_TX_QUICK_CONS_TRIP_6_INT (0xffUL<<16) + + u32_t hc1_comp_prod_trip_6; + #define HC1_COMP_PROD_TRIP_6_VALUE (0xffUL<<0) + #define HC1_COMP_PROD_TRIP_6_INT (0xffUL<<16) + + u32_t hc1_rx_quick_cons_trip_6; + #define HC1_RX_QUICK_CONS_TRIP_6_VALUE (0xffUL<<0) + #define HC1_RX_QUICK_CONS_TRIP_6_INT (0xffUL<<16) + + u32_t hc1_rx_ticks_6; + #define HC1_RX_TICKS_6_VALUE (0x3ffUL<<0) + #define HC1_RX_TICKS_6_INT (0x3ffUL<<16) + + u32_t hc1_tx_ticks_6; + #define HC1_TX_TICKS_6_VALUE (0x3ffUL<<0) + #define HC1_TX_TICKS_6_INT (0x3ffUL<<16) + + u32_t hc1_com_ticks_6; + #define HC1_COM_TICKS_6_VALUE (0x3ffUL<<0) + #define HC1_COM_TICKS_6_INT (0x3ffUL<<16) + + u32_t hc1_cmd_ticks_6; + #define HC1_CMD_TICKS_6_VALUE (0x3ffUL<<0) + #define HC1_CMD_TICKS_6_INT (0x3ffUL<<16) + + u32_t hc1_periodic_ticks_6; + #define HC1_PERIODIC_TICKS_6_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC1_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc1_sb_config_7; + #define HC1_SB_CONFIG_7_RX_TMR_MODE (1UL<<1) + #define HC1_SB_CONFIG_7_TX_TMR_MODE (1UL<<2) + #define HC1_SB_CONFIG_7_COM_TMR_MODE (1UL<<3) + #define HC1_SB_CONFIG_7_CMD_TMR_MODE (1UL<<4) + #define HC1_SB_CONFIG_7_PER_MODE (1UL<<16) + #define HC1_SB_CONFIG_7_ONE_SHOT (1UL<<17) + #define HC1_SB_CONFIG_7_USE_INT_PARAM (1UL<<18) + #define HC1_SB_CONFIG_7_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc1_tx_quick_cons_trip_7; + #define HC1_TX_QUICK_CONS_TRIP_7_VALUE (0xffUL<<0) + #define HC1_TX_QUICK_CONS_TRIP_7_INT (0xffUL<<16) + + u32_t hc1_comp_prod_trip_7; + #define HC1_COMP_PROD_TRIP_7_VALUE (0xffUL<<0) + #define HC1_COMP_PROD_TRIP_7_INT (0xffUL<<16) + + u32_t hc1_rx_quick_cons_trip_7; + #define HC1_RX_QUICK_CONS_TRIP_7_VALUE (0xffUL<<0) + #define HC1_RX_QUICK_CONS_TRIP_7_INT (0xffUL<<16) + + u32_t hc1_rx_ticks_7; + #define HC1_RX_TICKS_7_VALUE (0x3ffUL<<0) + #define HC1_RX_TICKS_7_INT (0x3ffUL<<16) + + u32_t hc1_tx_ticks_7; + #define HC1_TX_TICKS_7_VALUE (0x3ffUL<<0) + #define HC1_TX_TICKS_7_INT (0x3ffUL<<16) + + u32_t hc1_com_ticks_7; + #define HC1_COM_TICKS_7_VALUE (0x3ffUL<<0) + #define HC1_COM_TICKS_7_INT (0x3ffUL<<16) + + u32_t hc1_cmd_ticks_7; + #define HC1_CMD_TICKS_7_VALUE (0x3ffUL<<0) + #define HC1_CMD_TICKS_7_INT (0x3ffUL<<16) + + u32_t hc1_periodic_ticks_7; + #define HC1_PERIODIC_TICKS_7_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC1_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t hc1_sb_config_8; + #define HC1_SB_CONFIG_8_RX_TMR_MODE (1UL<<1) + #define HC1_SB_CONFIG_8_TX_TMR_MODE (1UL<<2) + #define HC1_SB_CONFIG_8_COM_TMR_MODE (1UL<<3) + #define HC1_SB_CONFIG_8_CMD_TMR_MODE (1UL<<4) + #define HC1_SB_CONFIG_8_PER_MODE (1UL<<16) + #define HC1_SB_CONFIG_8_ONE_SHOT (1UL<<17) + #define HC1_SB_CONFIG_8_USE_INT_PARAM (1UL<<18) + #define HC1_SB_CONFIG_8_PER_COLLECT_LIMIT (0xfUL<<20) + + u32_t hc1_tx_quick_cons_trip_8; + #define HC1_TX_QUICK_CONS_TRIP_8_VALUE (0xffUL<<0) + #define HC1_TX_QUICK_CONS_TRIP_8_INT (0xffUL<<16) + + u32_t hc1_comp_prod_trip_8; + #define HC1_COMP_PROD_TRIP_8_VALUE (0xffUL<<0) + #define HC1_COMP_PROD_TRIP_8_INT (0xffUL<<16) + + u32_t hc1_rx_quick_cons_trip_8; + #define HC1_RX_QUICK_CONS_TRIP_8_VALUE (0xffUL<<0) + #define HC1_RX_QUICK_CONS_TRIP_8_INT (0xffUL<<16) + + u32_t hc1_rx_ticks_8; + #define HC1_RX_TICKS_8_VALUE (0x3ffUL<<0) + #define HC1_RX_TICKS_8_INT (0x3ffUL<<16) + + u32_t hc1_tx_ticks_8; + #define HC1_TX_TICKS_8_VALUE (0x3ffUL<<0) + #define HC1_TX_TICKS_8_INT (0x3ffUL<<16) + + u32_t hc1_com_ticks_8; + #define HC1_COM_TICKS_8_VALUE (0x3ffUL<<0) + #define HC1_COM_TICKS_8_INT (0x3ffUL<<16) + + u32_t hc1_cmd_ticks_8; + #define HC1_CMD_TICKS_8_VALUE (0x3ffUL<<0) + #define HC1_CMD_TICKS_8_INT (0x3ffUL<<16) + + u32_t hc1_periodic_ticks_8; + #define HC1_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffUL<<0) + #define HC1_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffUL<<16) + + u32_t unused_2[7992]; + u32_t hc1_msix_vector0_addr_l; + #define HC1_MSIX_VECTOR0_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) + + u32_t hc1_msix_vector0_addr_h; + #define HC1_MSIX_VECTOR0_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) + + u32_t hc1_msix_vector0_data; + #define HC1_MSIX_VECTOR0_DATA_MSG_DATA (0xffffffffUL<<0) + + u32_t hc1_msix_vector0_mask; + #define HC1_MSIX_VECTOR0_MASK_MSG_MASK (1UL<<0) + + u32_t hc1_msix_vector1_addr_l; + #define HC1_MSIX_VECTOR1_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) + + u32_t hc1_msix_vector1_addr_h; + #define HC1_MSIX_VECTOR1_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) + + u32_t hc1_msix_vector1_data; + #define HC1_MSIX_VECTOR1_DATA_MSG_DATA (0xffffffffUL<<0) + + u32_t hc1_msix_vector1_mask; + #define HC1_MSIX_VECTOR1_MASK_MSG_MASK (1UL<<0) + + u32_t hc1_msix_vector2_addr_l; + #define HC1_MSIX_VECTOR2_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) + + u32_t hc1_msix_vector2_addr_h; + #define HC1_MSIX_VECTOR2_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) + + u32_t hc1_msix_vector2_data; + #define HC1_MSIX_VECTOR2_DATA_MSG_DATA (0xffffffffUL<<0) + + u32_t hc1_msix_vector2_mask; + #define HC1_MSIX_VECTOR2_MASK_MSG_MASK (1UL<<0) + + u32_t hc1_msix_vector3_addr_l; + #define HC1_MSIX_VECTOR3_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) + + u32_t hc1_msix_vector3_addr_h; + #define HC1_MSIX_VECTOR3_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) + + u32_t hc1_msix_vector3_data; + #define HC1_MSIX_VECTOR3_DATA_MSG_DATA (0xffffffffUL<<0) + + u32_t hc1_msix_vector3_mask; + #define HC1_MSIX_VECTOR3_MASK_MSG_MASK (1UL<<0) + + u32_t hc1_msix_vector4_addr_l; + #define HC1_MSIX_VECTOR4_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) + + u32_t hc1_msix_vector4_addr_h; + #define HC1_MSIX_VECTOR4_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) + + u32_t hc1_msix_vector4_data; + #define HC1_MSIX_VECTOR4_DATA_MSG_DATA (0xffffffffUL<<0) + + u32_t hc1_msix_vector4_mask; + #define HC1_MSIX_VECTOR4_MASK_MSG_MASK (1UL<<0) + + u32_t hc1_msix_vector5_addr_l; + #define HC1_MSIX_VECTOR5_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) + + u32_t hc1_msix_vector5_addr_h; + #define HC1_MSIX_VECTOR5_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) + + u32_t hc1_msix_vector5_data; + #define HC1_MSIX_VECTOR5_DATA_MSG_DATA (0xffffffffUL<<0) + + u32_t hc1_msix_vector5_mask; + #define HC1_MSIX_VECTOR5_MASK_MSG_MASK (1UL<<0) + + u32_t hc1_msix_vector6_addr_l; + #define HC1_MSIX_VECTOR6_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) + + u32_t hc1_msix_vector6_addr_h; + #define HC1_MSIX_VECTOR6_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) + + u32_t hc1_msix_vector6_data; + #define HC1_MSIX_VECTOR6_DATA_MSG_DATA (0xffffffffUL<<0) + + u32_t hc1_msix_vector6_mask; + #define HC1_MSIX_VECTOR6_MASK_MSG_MASK (1UL<<0) + + u32_t hc1_msix_vector7_addr_l; + #define HC1_MSIX_VECTOR7_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) + + u32_t hc1_msix_vector7_addr_h; + #define HC1_MSIX_VECTOR7_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) + + u32_t hc1_msix_vector7_data; + #define HC1_MSIX_VECTOR7_DATA_MSG_DATA (0xffffffffUL<<0) + + u32_t hc1_msix_vector7_mask; + #define HC1_MSIX_VECTOR7_MASK_MSG_MASK (1UL<<0) + + u32_t hc1_msix_vector8_addr_l; + #define HC1_MSIX_VECTOR8_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) + + u32_t hc1_msix_vector8_addr_h; + #define HC1_MSIX_VECTOR8_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) + + u32_t hc1_msix_vector8_data; + #define HC1_MSIX_VECTOR8_DATA_MSG_DATA (0xffffffffUL<<0) + + u32_t hc1_msix_vector8_mask; + #define HC1_MSIX_VECTOR8_MASK_MSG_MASK (1UL<<0) + + u32_t unused_3[4060]; + u32_t hc1_msix_pending_bits; + #define HC1_MSIX_PENDING_BITS_PENDING_BITS (0x1ffUL<<0) + + u32_t unused_4[4095]; +} hc1_reg_t; + +typedef hc1_reg_t host_coalesce_full_reg_t; + +/* + * tx_processor_enqueue definition + * offset: 0000 + */ +typedef struct tx_processor_enqueue +{ + u32_t tx_processor_enqueue_cid; + #define TX_PROCESSOR_ENQUEUE_CID_VALUE (0x3fffUL<<7) + + u32_t tx_processor_enqueue_bseq; + u32_t tx_processor_enqueue_wd2; + #define TX_PROCESSOR_ENQUEUE_FLAGS_FLAGS_QUICK_CID_ENA (1<<24) + #define TX_PROCESSOR_ENQUEUE_FLAGS_FLAGS_QUICK_CID_TE (0x3<<25) + #define TX_PROCESSOR_ENQUEUE_FLAGS_FLAGS_QUICK_CATCHUP_TE (1<<27) + #define TX_PROCESSOR_ENQUEUE_FLAGS_FLAGS_RSVD_XI (1<<25) + #define TX_PROCESSOR_ENQUEUE_FLAGS_FLAGS_BORROWED_XI (1<<26) + #define TX_PROCESSOR_ENQUEUE_FLAGS_FLAGS_BSEQ_INVLD_XI (1<<27) + #define TX_PROCESSOR_ENQUEUE_FLAGS_FLAGS_S_RETRAN (1<<28) + + u32_t tx_processor_enqueue_tcp_rcv_nxt; + #define TX_PROCESSOR_ENQUEUE_TCP_RCV_NXT_VALUE (0xffffffffUL<<0) + + u32_t tx_processor_enqueue_wd4; + #define TX_PROCESSOR_ENQUEUE_TCMD_FNUM_VALUE (0x3f<<24) + +} tx_processor_enqueue_t; + + +/* + * txp_reg definition + * offset: 0x40000 + */ +typedef struct txp_reg +{ + u32_t unused_0[5120]; + u32_t txp_cpu_mode; + #define TXP_CPU_MODE_LOCAL_RST (1UL<<0) + #define TXP_CPU_MODE_STEP_ENA (1UL<<1) + #define TXP_CPU_MODE_PAGE_0_DATA_ENA (1UL<<2) + #define TXP_CPU_MODE_PAGE_0_INST_ENA (1UL<<3) + #define TXP_CPU_MODE_MSG_BIT1 (1UL<<6) + #define TXP_CPU_MODE_INTERRUPT_ENA (1UL<<7) + #define TXP_CPU_MODE_SOFT_HALT (1UL<<10) + #define TXP_CPU_MODE_BAD_DATA_HALT_ENA (1UL<<11) + #define TXP_CPU_MODE_BAD_INST_HALT_ENA (1UL<<12) + #define TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1UL<<13) + #define TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1UL<<15) + + u32_t txp_cpu_state; + #define TXP_CPU_STATE_BREAKPOINT (1UL<<0) + #define TXP_CPU_STATE_BAD_INST_HALTED (1UL<<2) + #define TXP_CPU_STATE_PAGE_0_DATA_HALTED (1UL<<3) + #define TXP_CPU_STATE_PAGE_0_INST_HALTED (1UL<<4) + #define TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1UL<<5) + #define TXP_CPU_STATE_BAD_PC_HALTED (1UL<<6) + #define TXP_CPU_STATE_ALIGN_HALTED (1UL<<7) + #define TXP_CPU_STATE_FIO_ABORT_HALTED (1UL<<8) + #define TXP_CPU_STATE_SOFT_HALTED (1UL<<10) + #define TXP_CPU_STATE_SPAD_UNDERFLOW (1UL<<11) + #define TXP_CPU_STATE_INTERRRUPT (1UL<<12) + #define TXP_CPU_STATE_DATA_ACCESS_STALL (1UL<<14) + #define TXP_CPU_STATE_INST_FETCH_STALL (1UL<<15) + #define TXP_CPU_STATE_BLOCKED_READ (1UL<<31) + + u32_t txp_cpu_event_mask; + #define TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1UL<<0) + #define TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1UL<<2) + #define TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1UL<<3) + #define TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1UL<<4) + #define TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1UL<<5) + #define TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1UL<<6) + #define TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1UL<<7) + #define TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1UL<<8) + #define TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1UL<<10) + #define TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1UL<<11) + #define TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1UL<<12) + + u32_t unused_1[4]; + u32_t txp_cpu_program_counter; + u32_t txp_cpu_instruction; + u32_t txp_cpu_data_access; + u32_t txp_cpu_interrupt_enable; + u32_t txp_cpu_interrupt_vector; + u32_t txp_cpu_interrupt_saved_PC; + u32_t txp_cpu_hw_breakpoint; + #define TXP_CPU_HW_BREAKPOINT_DISABLE (1UL<<0) + #define TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffUL<<2) + + u32_t txp_cpu_debug_vect_peek; + #define TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) + #define TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) + #define TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t unused_2[3]; + u32_t txp_cpu_last_branch_addr; + #define TXP_CPU_LAST_BRANCH_ADDR_TYPE (1UL<<1) + #define TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0UL<<1) + #define TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1UL<<1) + #define TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffUL<<2) + + u32_t unused_3[109]; + u32_t txp_cpu_reg_file[32]; + u32_t unused_4[80]; + tx_processor_enqueue_t txp_txpq; + u32_t unused_5[9]; + u32_t txp_ftq_cmd; + #define TXP_FTQ_CMD_OFFSET (0x3ffUL<<0) + #define TXP_FTQ_CMD_WR_TOP (1UL<<10) + #define TXP_FTQ_CMD_WR_TOP_0 (0UL<<10) + #define TXP_FTQ_CMD_WR_TOP_1 (1UL<<10) + #define TXP_FTQ_CMD_SFT_RESET (1UL<<25) + #define TXP_FTQ_CMD_RD_DATA (1UL<<26) + #define TXP_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define TXP_FTQ_CMD_ADD_DATA (1UL<<28) + #define TXP_FTQ_CMD_INTERVENE_CLR (1UL<<29) + #define TXP_FTQ_CMD_POP (1UL<<30) + #define TXP_FTQ_CMD_BUSY (1UL<<31) + + u32_t txp_ftq_ctl; + #define TXP_FTQ_CTL_INTERVENE (1UL<<0) + #define TXP_FTQ_CTL_OVERFLOW (1UL<<1) + #define TXP_FTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define TXP_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define TXP_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + + u32_t unused_6[27392]; + u32_t txp_scratch[8192]; + u32_t unused_7[24576]; +} txp_reg_t; + +typedef txp_reg_t tx_processor_reg_t; + +/* + * tx_patchup_enqueue definition + * offset: 0000 + */ +typedef struct tx_patchup_enqueue +{ + u32_t tx_patchup_enqueue_cid; + #define TX_PATCHUP_ENQUEUE_CID_VALUE (0x3fffUL<<7) + + u32_t tx_patchup_enqueue_wd1; + #define TX_PATCHUP_ENQUEUE_NBYTES_VALUE (0x3fff<<16) + #define TX_PATCHUP_ENQUEUE_XNUM (0xff<<8) + #define TX_PATCHUP_ENQUEUE_KNUM (0xff<<0) + + u32_t tx_patchup_enqueue_flags_flags; + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_PLUS_TWO (1UL<<0) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_TCP_UDP_CKSUM (1UL<<1) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_IP_CKSUM (1UL<<2) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_INCR_CMD (1UL<<3) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_COAL_NOW (1UL<<4) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_DONT_GEN_CRC (1UL<<5) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_LAST_PKT (1UL<<6) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_PKT_FRAG (1UL<<7) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_QUICK_CID_ENA (1UL<<9) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_QUICK_CID_TE (0x3UL<<10) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_RSVD_FUTURE_XI (0x3UL<<10) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_L5_PAGE_MODE (1UL<<12) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_COMPLETE (1UL<<13) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_RETRAN (1UL<<14) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_END_PADDING (0xfUL<<16) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_USAGE_CNT (1UL<<20) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_USAGE_CNT_AUTODECREMENT (0UL<<20) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_USAGE_CNT_DONOTDECREMENT (1UL<<20) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_BSEQ_INVLD (1UL<<21) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_WORK_AROUND (0x3UL<<22) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE_SZ (0x3UL<<25) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_4 (0UL<<25) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_8 (1UL<<25) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_12 (2UL<<25) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_16 (3UL<<25) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE0 (1UL<<28) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE1 (1UL<<29) + #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE2 (1UL<<30) + + u32_t tx_patchup_enqueue_wd3; + #define TX_PATCHUP_ENQUEUE_RAW_CHKSUM (0xffff<<16) + #define TX_PATCHUP_ENQUEUE_TPAT_BIDX (0xffff<<0) + + u32_t tx_patchup_enqueue_wd4; + #define TX_PATCHUP_ENQUEUE_STATUS_CS16_ERR (1<<24) + +} tx_patchup_enqueue_t; + + +/* + * tpat_reg definition + * offset: 0x80000 + */ +typedef struct tpat_reg +{ + u32_t unused_0[5120]; + u32_t tpat_cpu_mode; + #define TPAT_CPU_MODE_LOCAL_RST (1UL<<0) + #define TPAT_CPU_MODE_STEP_ENA (1UL<<1) + #define TPAT_CPU_MODE_PAGE_0_DATA_ENA (1UL<<2) + #define TPAT_CPU_MODE_PAGE_0_INST_ENA (1UL<<3) + #define TPAT_CPU_MODE_MSG_BIT1 (1UL<<6) + #define TPAT_CPU_MODE_INTERRUPT_ENA (1UL<<7) + #define TPAT_CPU_MODE_SOFT_HALT (1UL<<10) + #define TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1UL<<11) + #define TPAT_CPU_MODE_BAD_INST_HALT_ENA (1UL<<12) + #define TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1UL<<13) + #define TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1UL<<15) + + u32_t tpat_cpu_state; + #define TPAT_CPU_STATE_BREAKPOINT (1UL<<0) + #define TPAT_CPU_STATE_BAD_INST_HALTED (1UL<<2) + #define TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1UL<<3) + #define TPAT_CPU_STATE_PAGE_0_INST_HALTED (1UL<<4) + #define TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1UL<<5) + #define TPAT_CPU_STATE_BAD_PC_HALTED (1UL<<6) + #define TPAT_CPU_STATE_ALIGN_HALTED (1UL<<7) + #define TPAT_CPU_STATE_FIO_ABORT_HALTED (1UL<<8) + #define TPAT_CPU_STATE_SOFT_HALTED (1UL<<10) + #define TPAT_CPU_STATE_SPAD_UNDERFLOW (1UL<<11) + #define TPAT_CPU_STATE_INTERRRUPT (1UL<<12) + #define TPAT_CPU_STATE_DATA_ACCESS_STALL (1UL<<14) + #define TPAT_CPU_STATE_INST_FETCH_STALL (1UL<<15) + #define TPAT_CPU_STATE_BLOCKED_READ (1UL<<31) + + u32_t tpat_cpu_event_mask; + #define TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1UL<<0) + #define TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1UL<<2) + #define TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1UL<<3) + #define TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1UL<<4) + #define TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1UL<<5) + #define TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1UL<<6) + #define TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1UL<<7) + #define TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1UL<<8) + #define TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1UL<<10) + #define TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1UL<<11) + #define TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1UL<<12) + + u32_t unused_1[4]; + u32_t tpat_cpu_program_counter; + u32_t tpat_cpu_instruction; + u32_t tpat_cpu_data_access; + u32_t tpat_cpu_interrupt_enable; + u32_t tpat_cpu_interrupt_vector; + u32_t tpat_cpu_interrupt_saved_PC; + u32_t tpat_cpu_hw_breakpoint; + #define TPAT_CPU_HW_BREAKPOINT_DISABLE (1UL<<0) + #define TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffUL<<2) + + u32_t tpat_cpu_debug_vect_peek; + #define TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) + #define TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) + #define TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t unused_2[3]; + u32_t tpat_cpu_last_branch_addr; + #define TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1UL<<1) + #define TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0UL<<1) + #define TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1UL<<1) + #define TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffUL<<2) + + u32_t unused_3[109]; + u32_t tpat_cpu_reg_file[32]; + u32_t unused_4[80]; + tx_patchup_enqueue_t tpat_tpatq; + u32_t unused_5[9]; + u32_t tpat_ftq_cmd; + #define TPAT_FTQ_CMD_OFFSET (0x3ffUL<<0) + #define TPAT_FTQ_CMD_WR_TOP (1UL<<10) + #define TPAT_FTQ_CMD_WR_TOP_0 (0UL<<10) + #define TPAT_FTQ_CMD_WR_TOP_1 (1UL<<10) + #define TPAT_FTQ_CMD_SFT_RESET (1UL<<25) + #define TPAT_FTQ_CMD_RD_DATA (1UL<<26) + #define TPAT_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define TPAT_FTQ_CMD_ADD_DATA (1UL<<28) + #define TPAT_FTQ_CMD_INTERVENE_CLR (1UL<<29) + #define TPAT_FTQ_CMD_POP (1UL<<30) + #define TPAT_FTQ_CMD_BUSY (1UL<<31) + + u32_t tpat_ftq_ctl; + #define TPAT_FTQ_CTL_INTERVENE (1UL<<0) + #define TPAT_FTQ_CTL_OVERFLOW (1UL<<1) + #define TPAT_FTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define TPAT_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define TPAT_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + + u32_t unused_6[27392]; + u32_t tpat_scratch[3072]; + u32_t unused_7[29696]; +} tpat_reg_t; + +typedef tpat_reg_t tx_patchup_reg_t; + +/* + * rx_processor_cmd_enqueue definition + * offset: 0000 + */ +typedef struct rx_processor_cmd_enqueue +{ + u32_t rx_processor_cmd_enqueue_cid; + #define RX_PROCESSOR_CMD_ENQUEUE_CID_VALUE (0x3fffUL<<7) + + u32_t rx_processor_cmd_enqueue_wd1; + #define RX_PROCESSOR_CMD_ENQUEUE_WORK_ID (0xffff<<16) + #define RX_PROCESSOR_CMD_ENQUEUE_CMD_TYPE (0xffff<<0) + + u32_t rx_processor_cmd_enqueue_wd2; + #define RX_PROCESSOR_CMD_ENQUEUE_CMD_STATUS_VALUE (0xfff<<16) + #define RX_PROCESSOR_CMD_ENQUEUE_CMD_STATUS_DRIVER_ID (0xf<<28) + #define RX_PROCESSOR_CMD_ENQUEUE_OPAQUE (0xffff<<0) + + u32_t rx_processor_cmd_enqueue_wd3; + #define RX_PROCESSOR_CMD_ENQUEUE_RSVD_FUTURE_VALUE (0x3<<24) + +} rx_processor_cmd_enqueue_t; + + +/* + * rx_processor_enqueue definition + * offset: 0000 + */ +typedef struct rx_processor_enqueue +{ + u32_t rx_processor_enqueue_bits_errors; + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_L2_BAD_CRC (1UL<<1) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_L2_PHY_DECODE (1UL<<2) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_L2_ALIGNMENT (1UL<<3) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_L2_TOO_SHORT (1UL<<4) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_L2_GIANT_FRAME (1UL<<5) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_IP_BAD_LEN (1UL<<6) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_IP_TOO_SHORT (1UL<<7) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_IP_BAD_VERSION (1UL<<8) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_IP_BAD_HLEN (1UL<<9) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_IP_BAD_XSUM (1UL<<10) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_TCP_TOO_SHORT (1UL<<11) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_TCP_BAD_XSUM (1UL<<12) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_TCP_BAD_OFFSET (1UL<<13) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_TCP_SYNC_PRESENT (1UL<<14) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_UDP_BAD_XSUM (1UL<<15) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_IP_BAD_ORDER (1UL<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_IP_HDR_MISMATCH (1UL<<18) + + u32_t rx_processor_enqueue_bits_status; + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RULE_CLASS (0x7UL<<0) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RULE_P2 (1UL<<3) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RULE_P3 (1UL<<4) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RULE_P4 (1UL<<5) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_L2_VLAN_TAG (1UL<<6) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_L2_LLC_SNAP (1UL<<7) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RSS_HASH (1UL<<8) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_SORT_VECT (0xfUL<<9) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_IP_DATAGRAM (1UL<<13) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_TCP_SEGMENT (1UL<<14) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_UDP_DATAGRAM (1UL<<15) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_CU_FRAME (1UL<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_IP_PROG_EXT (1UL<<17) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_IP_TYPE (1UL<<18) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RULE_P1 (1UL<<19) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_VALID_TE (1UL<<20) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RLUP_HIT4_XI (1UL<<20) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_IP_FRAGMENT (1UL<<21) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_IP_OPTIONS_PRESENT (1UL<<22) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_TCP_OPTIONS_PRESENT (1UL<<23) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_L2_PM_IDX (0xfUL<<24) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_L2_PM_HIT (1UL<<28) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_L2_MC_HASH_HIT (1UL<<29) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RDMAC_CRC_PASS (1UL<<30) + #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_MP_HIT (1UL<<31) + + u32_t rx_processor_enqueue_wd2; + #define RX_PROCESSOR_ENQUEUE_BITS_MULTICAST_HASH_IDX (0xff<<24) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_TE (0x7<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_0_TE (0<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_1_TE (1<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_2_TE (2<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_3_TE (3<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_4_TE (4<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_5_TE (5<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_6_TE (6<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_NONE_TE (7<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_XI (0xf<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_0_XI (0<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_1_XI (1<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_2_XI (2<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_3_XI (3<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_4_XI (4<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_5_XI (5<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_6_XI (6<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_NONE_XI (7<<16) + #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_8_XI (8<<16) + #define RX_PROCESSOR_ENQUEUE_KNUM (0xff<<8) + + u32_t rx_processor_enqueue_wd3; + #define RX_PROCESSOR_ENQUEUE_RULE_TAG (0xffff<<16) + #define RX_PROCESSOR_ENQUEUE_PKT_LEN_VALUE (0x3fff<<0) + + u32_t rx_processor_enqueue_wd4; + #define RX_PROCESSOR_ENQUEUE_VLAN_TAG (0xffff<<16) + #define RX_PROCESSOR_ENQUEUE_IP_HDR_OFFSET (0xff<<8) + #define RX_PROCESSOR_ENQUEUE_RX_QID_VALUE (0xf<<0) + + u32_t rx_processor_enqueue_wd5; + #define RX_PROCESSOR_ENQUEUE_IP_XSUM (0xffff<<16) + #define RX_PROCESSOR_ENQUEUE_TCP_UDP_HDR_OFFSET (0xffff<<0) + + u32_t rx_processor_enqueue_wd6; + #define RX_PROCESSOR_ENQUEUE_TCP_UDP_XSUM (0xffff<<16) + #define RX_PROCESSOR_ENQUEUE_TCP_PAYLOAD_LEN (0xffff<<0) + + u32_t rx_processor_enqueue_wd7; + #define RX_PROCESSOR_ENQUEUE_PSEUD_XSUM (0xffff<<16) + #define RX_PROCESSOR_ENQUEUE_L2_PAYLOAD_RAW_XSUM (0xffff<<0) + + u32_t rx_processor_enqueue_wd8; + #define RX_PROCESSOR_ENQUEUE_DATA_OFFSET (0xffff<<16) + #define RX_PROCESSOR_ENQUEUE_L3_PAYLOAD_RAW_XSUM (0xffff<<0) + + u32_t rx_processor_enqueue_mbuf_cluster; + #define RX_PROCESSOR_ENQUEUE_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) + + u32_t rx_processor_enqueue_cid; + #define RX_PROCESSOR_ENQUEUE_CID_VALUE (0x3fffUL<<7) + + u32_t rx_processor_enqueue_wd11; + #define RX_PROCESSOR_ENQUEUE_CS16_VALUE (0xffff<<16) + + u32_t rx_processor_enqueue_wd12; + #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_TCP_SYNC_PRESENT (1<<16) + #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_RLUP_HIT2 (1<<17) + #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_TCP_UDP_XSUM_IS_0 (1<<18) + #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT (0x3<<19) + #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_00 (0<<19) + #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_01 (1<<19) + #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_10 (2<<19) + #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_11 (3<<19) + #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_ACPI_MATCH (1<<21) + +} rx_processor_enqueue_t; + + +/* + * rxp_reg definition + * offset: 0xc0000 + */ +typedef struct rxp_reg +{ + u32_t unused_0[5120]; + u32_t rxp_cpu_mode; + #define RXP_CPU_MODE_LOCAL_RST (1UL<<0) + #define RXP_CPU_MODE_STEP_ENA (1UL<<1) + #define RXP_CPU_MODE_PAGE_0_DATA_ENA (1UL<<2) + #define RXP_CPU_MODE_PAGE_0_INST_ENA (1UL<<3) + #define RXP_CPU_MODE_MSG_BIT1 (1UL<<6) + #define RXP_CPU_MODE_INTERRUPT_ENA (1UL<<7) + #define RXP_CPU_MODE_SOFT_HALT (1UL<<10) + #define RXP_CPU_MODE_BAD_DATA_HALT_ENA (1UL<<11) + #define RXP_CPU_MODE_BAD_INST_HALT_ENA (1UL<<12) + #define RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1UL<<13) + #define RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1UL<<15) + + u32_t rxp_cpu_state; + #define RXP_CPU_STATE_BREAKPOINT (1UL<<0) + #define RXP_CPU_STATE_BAD_INST_HALTED (1UL<<2) + #define RXP_CPU_STATE_PAGE_0_DATA_HALTED (1UL<<3) + #define RXP_CPU_STATE_PAGE_0_INST_HALTED (1UL<<4) + #define RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1UL<<5) + #define RXP_CPU_STATE_BAD_PC_HALTED (1UL<<6) + #define RXP_CPU_STATE_ALIGN_HALTED (1UL<<7) + #define RXP_CPU_STATE_FIO_ABORT_HALTED (1UL<<8) + #define RXP_CPU_STATE_SOFT_HALTED (1UL<<10) + #define RXP_CPU_STATE_SPAD_UNDERFLOW (1UL<<11) + #define RXP_CPU_STATE_INTERRRUPT (1UL<<12) + #define RXP_CPU_STATE_DATA_ACCESS_STALL (1UL<<14) + #define RXP_CPU_STATE_INST_FETCH_STALL (1UL<<15) + #define RXP_CPU_STATE_BLOCKED_READ (1UL<<31) + + u32_t rxp_cpu_event_mask; + #define RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1UL<<0) + #define RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1UL<<2) + #define RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1UL<<3) + #define RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1UL<<4) + #define RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1UL<<5) + #define RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1UL<<6) + #define RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1UL<<7) + #define RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1UL<<8) + #define RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1UL<<10) + #define RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1UL<<11) + #define RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1UL<<12) + + u32_t unused_1[4]; + u32_t rxp_cpu_program_counter; + u32_t rxp_cpu_instruction; + u32_t rxp_cpu_data_access; + u32_t rxp_cpu_interrupt_enable; + u32_t rxp_cpu_interrupt_vector; + u32_t rxp_cpu_interrupt_saved_PC; + u32_t rxp_cpu_hw_breakpoint; + #define RXP_CPU_HW_BREAKPOINT_DISABLE (1UL<<0) + #define RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffUL<<2) + + u32_t rxp_cpu_debug_vect_peek; + #define RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) + #define RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) + #define RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t unused_2[3]; + u32_t rxp_cpu_last_branch_addr; + #define RXP_CPU_LAST_BRANCH_ADDR_TYPE (1UL<<1) + #define RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0UL<<1) + #define RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1UL<<1) + #define RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffUL<<2) + + u32_t unused_3[109]; + u32_t rxp_cpu_reg_file[32]; + u32_t unused_4[63]; + u32_t rxp_pfe_pfe_ctl; + #define RXP_PFE_PFE_CTL_INC_USAGE_CNT (1UL<<0) + #define RXP_PFE_PFE_CTL_PFE_SIZE (0xfUL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_0 (0UL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_1 (1UL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_2 (2UL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_3 (3UL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_4 (4UL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_5 (5UL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_6 (6UL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_7 (7UL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_8 (8UL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_9 (9UL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_10 (10UL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_11 (11UL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_12 (12UL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_13 (13UL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_14 (14UL<<4) + #define RXP_PFE_PFE_CTL_PFE_SIZE_15 (15UL<<4) + #define RXP_PFE_PFE_CTL_PFE_COUNT (0xfUL<<12) + #define RXP_PFE_PFE_CTL_OFFSET (0x1ffUL<<16) + + rx_processor_cmd_enqueue_t rxp_rxpcq; + u32_t unused_5[10]; + u32_t rxp_cftq_cmd; + #define RXP_CFTQ_CMD_OFFSET (0x3ffUL<<0) + #define RXP_CFTQ_CMD_WR_TOP (1UL<<10) + #define RXP_CFTQ_CMD_WR_TOP_0 (0UL<<10) + #define RXP_CFTQ_CMD_WR_TOP_1 (1UL<<10) + #define RXP_CFTQ_CMD_SFT_RESET (1UL<<25) + #define RXP_CFTQ_CMD_RD_DATA (1UL<<26) + #define RXP_CFTQ_CMD_ADD_INTERVEN (1UL<<27) + #define RXP_CFTQ_CMD_ADD_DATA (1UL<<28) + #define RXP_CFTQ_CMD_INTERVENE_CLR (1UL<<29) + #define RXP_CFTQ_CMD_POP (1UL<<30) + #define RXP_CFTQ_CMD_BUSY (1UL<<31) + + u32_t rxp_cftq_ctl; + #define RXP_CFTQ_CTL_INTERVENE (1UL<<0) + #define RXP_CFTQ_CTL_OVERFLOW (1UL<<1) + #define RXP_CFTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define RXP_CFTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define RXP_CFTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + + rx_processor_enqueue_t rxp_rxpq; + u32_t unused_6; + u32_t rxp_ftq_cmd; + #define RXP_FTQ_CMD_OFFSET (0x3ffUL<<0) + #define RXP_FTQ_CMD_WR_TOP (1UL<<10) + #define RXP_FTQ_CMD_WR_TOP_0 (0UL<<10) + #define RXP_FTQ_CMD_WR_TOP_1 (1UL<<10) + #define RXP_FTQ_CMD_SFT_RESET (1UL<<25) + #define RXP_FTQ_CMD_RD_DATA (1UL<<26) + #define RXP_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define RXP_FTQ_CMD_ADD_DATA (1UL<<28) + #define RXP_FTQ_CMD_INTERVENE_CLR (1UL<<29) + #define RXP_FTQ_CMD_POP (1UL<<30) + #define RXP_FTQ_CMD_BUSY (1UL<<31) + + u32_t rxp_ftq_ctl; + #define RXP_FTQ_CTL_INTERVENE (1UL<<0) + #define RXP_FTQ_CTL_OVERFLOW (1UL<<1) + #define RXP_FTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define RXP_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define RXP_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + + u32_t unused_7[27392]; + u32_t rxp_scratch[10240]; + u32_t unused_8[22528]; +} rxp_reg_t; + +typedef rxp_reg_t rx_processor_reg_t; + +/* + * completion_tx_enqueue definition + * offset: 0000 + */ +typedef struct completion_tx_enqueue +{ + u32_t completion_tx_enqueue_cid; + #define COMPLETION_TX_ENQUEUE_CID_VALUE (0x3fffUL<<7) + + u32_t completion_tx_enqueue_wd1; + #define COMPLETION_TX_ENQUEUE_FLAGS_CMD (0xff<<16) + #define COMPLETION_TX_ENQUEUE_FLAGS_COMPLETE (1<<24) + #define COMPLETION_TX_ENQUEUE_FLAGS_RETRAN (1<<25) + + u32_t completion_tx_enqueue_snd_next; + u32_t completion_tx_enqueue_wd3; + #define COMPLETION_TX_ENQUEUE_NEW_FLAGS_USAGE_CNT (1<<24) + #define COMPLETION_TX_ENQUEUE_NEW_FLAGS_USAGE_CNT_AUTODECREMENT (0<<24) + #define COMPLETION_TX_ENQUEUE_NEW_FLAGS_USAGE_CNT_DONOTDECREMENT (1<<24) + #define COMPLETION_TX_ENQUEUE_NEW_FLAGS_BSEQ_INVLD (1<<25) + #define COMPLETION_TX_ENQUEUE_NEW_FLAGS_WORK_AROUND (0x3<<26) + +} completion_tx_enqueue_t; + + +/* + * completion_timeout_enqueue definition + * offset: 0000 + */ +typedef struct completion_timeout_enqueue +{ + u32_t completion_timeout_enqueue_cid; + #define COMPLETION_TIMEOUT_ENQUEUE_CID_VALUE (0x3fffUL<<7) + + u32_t completion_timeout_enqueue_tmr_val; + u32_t completion_timeout_enqueue_wd2; + #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_TYPE (0x7<<24) + #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_TYPE_SW (0<<24) + #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_TYPE_RETRAN (1<<24) + #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_TYPE_PUSH (2<<24) + #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_TYPE_DELAY_ACK (3<<24) + #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_TYPE_KEEP_ALIVE (4<<24) + #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_TYPE_NAGLE (5<<24) + #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_EVENT_UNUSED (1<<28) + #define COMPLETION_TIMEOUT_ENQUEUE_RSVD_FUTURE_VALUE (0x3<<16) + +} completion_timeout_enqueue_t; + + +/* + * completion_enqueue definition + * offset: 0000 + */ +typedef struct completion_enqueue +{ + u32_t completion_enqueue_cid; + #define COMPLETION_ENQUEUE_CID_VALUE (0x3fffUL<<7) + + u32_t completion_enqueue_mbuf_cluster; + #define COMPLETION_ENQUEUE_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) + + u32_t completion_enqueue_wd2; + #define COMPLETION_ENQUEUE_OPERAND_FLAGS (0xffff<<16) + #define COMPLETION_ENQUEUE_KNUM (0xff<<8) + #define COMPLETION_ENQUEUE_OPCODE (0xff<<0) + + u32_t completion_enqueue_wd3; + #define COMPLETION_ENQUEUE_OPERAND16_2 (0xffff<<16) + #define COMPLETION_ENQUEUE_OPERAND16_3 (0xffff<<0) + + u32_t completion_enqueue_wd4; + #define COMPLETION_ENQUEUE_OPERAND16_4 (0xffff<<16) + #define COMPLETION_ENQUEUE_OPERAND16_5 (0xffff<<0) + + u32_t completion_enqueue_wd5; + #define COMPLETION_ENQUEUE_OPERAND16_6 (0xffff<<16) + #define COMPLETION_ENQUEUE_OPERAND16_7 (0xffff<<0) + + u32_t completion_enqueue_operand32_2; + u32_t completion_enqueue_operand32_3; + u32_t completion_enqueue_operand32_4; + u32_t completion_enqueue_wd9; + #define COMPLETION_ENQUEUE_RDMA_ACTION_DO_DMA (1<<24) + #define COMPLETION_ENQUEUE_RDMA_ACTION_PREPEND_L2_FRAME_HDR (1<<25) + #define COMPLETION_ENQUEUE_RDMA_ACTION_CRC_ENABLE (1<<26) + #define COMPLETION_ENQUEUE_RDMA_ACTION_CRC_USE_CTX_SEED (1<<27) + #define COMPLETION_ENQUEUE_RDMA_ACTION_CS16_FIRST (1<<28) + #define COMPLETION_ENQUEUE_RDMA_ACTION_CS16_LAST (1<<29) + #define COMPLETION_ENQUEUE_RDMA_ACTION_CS16_VLD (1<<30) + #define COMPLETION_ENQUEUE_RDMA_ACTION_CS16_ERR (1<<31) + #define COMPLETION_ENQUEUE_CS16_PKT_LEN_VALUE (0x7f<<16) + #define COMPLETION_ENQUEUE_CS16 (0xffff<<0) + +} completion_enqueue_t; + + +/* + * com_reg definition + * offset: 0x100000 + */ +typedef struct com_reg +{ + u32_t com_cksum_error_status; + #define COM_CKSUM_ERROR_STATUS_CALCULATED (0xffffUL<<0) + #define COM_CKSUM_ERROR_STATUS_EXPECTED (0xffffUL<<16) + + u32_t unused_0[5119]; + u32_t com_cpu_mode; + #define COM_CPU_MODE_LOCAL_RST (1UL<<0) + #define COM_CPU_MODE_STEP_ENA (1UL<<1) + #define COM_CPU_MODE_PAGE_0_DATA_ENA (1UL<<2) + #define COM_CPU_MODE_PAGE_0_INST_ENA (1UL<<3) + #define COM_CPU_MODE_MSG_BIT1 (1UL<<6) + #define COM_CPU_MODE_INTERRUPT_ENA (1UL<<7) + #define COM_CPU_MODE_SOFT_HALT (1UL<<10) + #define COM_CPU_MODE_BAD_DATA_HALT_ENA (1UL<<11) + #define COM_CPU_MODE_BAD_INST_HALT_ENA (1UL<<12) + #define COM_CPU_MODE_FIO_ABORT_HALT_ENA (1UL<<13) + #define COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1UL<<15) + + u32_t com_cpu_state; + #define COM_CPU_STATE_BREAKPOINT (1UL<<0) + #define COM_CPU_STATE_BAD_INST_HALTED (1UL<<2) + #define COM_CPU_STATE_PAGE_0_DATA_HALTED (1UL<<3) + #define COM_CPU_STATE_PAGE_0_INST_HALTED (1UL<<4) + #define COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1UL<<5) + #define COM_CPU_STATE_BAD_PC_HALTED (1UL<<6) + #define COM_CPU_STATE_ALIGN_HALTED (1UL<<7) + #define COM_CPU_STATE_FIO_ABORT_HALTED (1UL<<8) + #define COM_CPU_STATE_SOFT_HALTED (1UL<<10) + #define COM_CPU_STATE_SPAD_UNDERFLOW (1UL<<11) + #define COM_CPU_STATE_INTERRRUPT (1UL<<12) + #define COM_CPU_STATE_DATA_ACCESS_STALL (1UL<<14) + #define COM_CPU_STATE_INST_FETCH_STALL (1UL<<15) + #define COM_CPU_STATE_BLOCKED_READ (1UL<<31) + + u32_t com_cpu_event_mask; + #define COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1UL<<0) + #define COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1UL<<2) + #define COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1UL<<3) + #define COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1UL<<4) + #define COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1UL<<5) + #define COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1UL<<6) + #define COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1UL<<7) + #define COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1UL<<8) + #define COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1UL<<10) + #define COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1UL<<11) + #define COM_CPU_EVENT_MASK_INTERRUPT_MASK (1UL<<12) + + u32_t unused_1[4]; + u32_t com_cpu_program_counter; + u32_t com_cpu_instruction; + u32_t com_cpu_data_access; + u32_t com_cpu_interrupt_enable; + u32_t com_cpu_interrupt_vector; + u32_t com_cpu_interrupt_saved_PC; + u32_t com_cpu_hw_breakpoint; + #define COM_CPU_HW_BREAKPOINT_DISABLE (1UL<<0) + #define COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffUL<<2) + + u32_t com_cpu_debug_vect_peek; + #define COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) + #define COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) + #define COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t unused_2[3]; + u32_t com_cpu_last_branch_addr; + #define COM_CPU_LAST_BRANCH_ADDR_TYPE (1UL<<1) + #define COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0UL<<1) + #define COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1UL<<1) + #define COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffUL<<2) + + u32_t unused_3[109]; + u32_t com_cpu_reg_file[32]; + u32_t unused_4[15]; + u32_t com_comtq_pfe_pfe_ctl; + #define COM_COMTQ_PFE_PFE_CTL_INC_USAGE_CNT (1UL<<0) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE (0xfUL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_0 (0UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_1 (1UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_2 (2UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_3 (3UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_4 (4UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_5 (5UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_6 (6UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_7 (7UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_8 (8UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_9 (9UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_10 (10UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_11 (11UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_12 (12UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_13 (13UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_14 (14UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_15 (15UL<<4) + #define COM_COMTQ_PFE_PFE_CTL_PFE_COUNT (0xfUL<<12) + #define COM_COMTQ_PFE_PFE_CTL_OFFSET (0x1ffUL<<16) + + u32_t unused_5[32]; + completion_tx_enqueue_t com_comxq; + u32_t unused_6[10]; + u32_t com_comxq_ftq_cmd; + #define COM_COMXQ_FTQ_CMD_OFFSET (0x3ffUL<<0) + #define COM_COMXQ_FTQ_CMD_WR_TOP (1UL<<10) + #define COM_COMXQ_FTQ_CMD_WR_TOP_0 (0UL<<10) + #define COM_COMXQ_FTQ_CMD_WR_TOP_1 (1UL<<10) + #define COM_COMXQ_FTQ_CMD_SFT_RESET (1UL<<25) + #define COM_COMXQ_FTQ_CMD_RD_DATA (1UL<<26) + #define COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define COM_COMXQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1UL<<29) + #define COM_COMXQ_FTQ_CMD_POP (1UL<<30) + #define COM_COMXQ_FTQ_CMD_BUSY (1UL<<31) + + u32_t com_comxq_ftq_ctl; + #define COM_COMXQ_FTQ_CTL_INTERVENE (1UL<<0) + #define COM_COMXQ_FTQ_CTL_OVERFLOW (1UL<<1) + #define COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + + completion_timeout_enqueue_t com_comtq; + u32_t unused_7[11]; + u32_t com_comtq_ftq_cmd; + #define COM_COMTQ_FTQ_CMD_OFFSET (0x3ffUL<<0) + #define COM_COMTQ_FTQ_CMD_WR_TOP (1UL<<10) + #define COM_COMTQ_FTQ_CMD_WR_TOP_0 (0UL<<10) + #define COM_COMTQ_FTQ_CMD_WR_TOP_1 (1UL<<10) + #define COM_COMTQ_FTQ_CMD_SFT_RESET (1UL<<25) + #define COM_COMTQ_FTQ_CMD_RD_DATA (1UL<<26) + #define COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define COM_COMTQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1UL<<29) + #define COM_COMTQ_FTQ_CMD_POP (1UL<<30) + #define COM_COMTQ_FTQ_CMD_BUSY (1UL<<31) + + u32_t com_comtq_ftq_ctl; + #define COM_COMTQ_FTQ_CTL_INTERVENE (1UL<<0) + #define COM_COMTQ_FTQ_CTL_OVERFLOW (1UL<<1) + #define COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + + completion_enqueue_t com_comq; + u32_t unused_8[4]; + u32_t com_comq_ftq_cmd; + #define COM_COMQ_FTQ_CMD_OFFSET (0x3ffUL<<0) + #define COM_COMQ_FTQ_CMD_WR_TOP (1UL<<10) + #define COM_COMQ_FTQ_CMD_WR_TOP_0 (0UL<<10) + #define COM_COMQ_FTQ_CMD_WR_TOP_1 (1UL<<10) + #define COM_COMQ_FTQ_CMD_SFT_RESET (1UL<<25) + #define COM_COMQ_FTQ_CMD_RD_DATA (1UL<<26) + #define COM_COMQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define COM_COMQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define COM_COMQ_FTQ_CMD_INTERVENE_CLR (1UL<<29) + #define COM_COMQ_FTQ_CMD_POP (1UL<<30) + #define COM_COMQ_FTQ_CMD_BUSY (1UL<<31) + + u32_t com_comq_ftq_ctl; + #define COM_COMQ_FTQ_CTL_INTERVENE (1UL<<0) + #define COM_COMQ_FTQ_CTL_OVERFLOW (1UL<<1) + #define COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + + u32_t unused_9[27392]; + u32_t com_scratch[10240]; + u32_t unused_10[22528]; +} com_reg_t; + +typedef com_reg_t completion_reg_t; + +/* + * cmd_processor_enqueue definition + * offset: 0000 + */ +typedef struct cmd_processor_enqueue +{ + u32_t cmd_processor_enqueue_cid; + #define CMD_PROCESSOR_ENQUEUE_CID_VALUE (0x3fffUL<<7) + +} cmd_processor_enqueue_t; + + +/* + * cp_reg definition + * offset: 0x180000 + */ +typedef struct cp_reg +{ + u32_t cp_cksum_error_status; + #define CP_CKSUM_ERROR_STATUS_CALCULATED (0xffffUL<<0) + #define CP_CKSUM_ERROR_STATUS_EXPECTED (0xffffUL<<16) + + u32_t unused_0[5119]; + u32_t cp_cpu_mode; + #define CP_CPU_MODE_LOCAL_RST (1UL<<0) + #define CP_CPU_MODE_STEP_ENA (1UL<<1) + #define CP_CPU_MODE_PAGE_0_DATA_ENA (1UL<<2) + #define CP_CPU_MODE_PAGE_0_INST_ENA (1UL<<3) + #define CP_CPU_MODE_MSG_BIT1 (1UL<<6) + #define CP_CPU_MODE_INTERRUPT_ENA (1UL<<7) + #define CP_CPU_MODE_SOFT_HALT (1UL<<10) + #define CP_CPU_MODE_BAD_DATA_HALT_ENA (1UL<<11) + #define CP_CPU_MODE_BAD_INST_HALT_ENA (1UL<<12) + #define CP_CPU_MODE_FIO_ABORT_HALT_ENA (1UL<<13) + #define CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1UL<<15) + + u32_t cp_cpu_state; + #define CP_CPU_STATE_BREAKPOINT (1UL<<0) + #define CP_CPU_STATE_BAD_INST_HALTED (1UL<<2) + #define CP_CPU_STATE_PAGE_0_DATA_HALTED (1UL<<3) + #define CP_CPU_STATE_PAGE_0_INST_HALTED (1UL<<4) + #define CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1UL<<5) + #define CP_CPU_STATE_BAD_PC_HALTED (1UL<<6) + #define CP_CPU_STATE_ALIGN_HALTED (1UL<<7) + #define CP_CPU_STATE_FIO_ABORT_HALTED (1UL<<8) + #define CP_CPU_STATE_SOFT_HALTED (1UL<<10) + #define CP_CPU_STATE_SPAD_UNDERFLOW (1UL<<11) + #define CP_CPU_STATE_INTERRRUPT (1UL<<12) + #define CP_CPU_STATE_DATA_ACCESS_STALL (1UL<<14) + #define CP_CPU_STATE_INST_FETCH_STALL (1UL<<15) + #define CP_CPU_STATE_BLOCKED_READ (1UL<<31) + + u32_t cp_cpu_event_mask; + #define CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1UL<<0) + #define CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1UL<<2) + #define CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1UL<<3) + #define CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1UL<<4) + #define CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1UL<<5) + #define CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1UL<<6) + #define CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1UL<<7) + #define CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1UL<<8) + #define CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1UL<<10) + #define CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1UL<<11) + #define CP_CPU_EVENT_MASK_INTERRUPT_MASK (1UL<<12) + + u32_t unused_1[4]; + u32_t cp_cpu_program_counter; + u32_t cp_cpu_instruction; + u32_t cp_cpu_data_access; + u32_t cp_cpu_interrupt_enable; + u32_t cp_cpu_interrupt_vector; + u32_t cp_cpu_interrupt_saved_PC; + u32_t cp_cpu_hw_breakpoint; + #define CP_CPU_HW_BREAKPOINT_DISABLE (1UL<<0) + #define CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffUL<<2) + + u32_t cp_cpu_debug_vect_peek; + #define CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) + #define CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) + #define CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t unused_2[3]; + u32_t cp_cpu_last_branch_addr; + #define CP_CPU_LAST_BRANCH_ADDR_TYPE (1UL<<1) + #define CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0UL<<1) + #define CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1UL<<1) + #define CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffUL<<2) + + u32_t unused_3[109]; + u32_t cp_cpu_reg_file[32]; + u32_t unused_4[79]; + u32_t cp_cpq_pfe_pfe_ctl; + #define CP_CPQ_PFE_PFE_CTL_INC_USAGE_CNT (1UL<<0) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE (0xfUL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_0 (0UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_1 (1UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_2 (2UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_3 (3UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_4 (4UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_5 (5UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_6 (6UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_7 (7UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_8 (8UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_9 (9UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_10 (10UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_11 (11UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_12 (12UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_13 (13UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_14 (14UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_15 (15UL<<4) + #define CP_CPQ_PFE_PFE_CTL_PFE_COUNT (0xfUL<<12) + #define CP_CPQ_PFE_PFE_CTL_OFFSET (0x1ffUL<<16) + + cmd_processor_enqueue_t cp_cpq; + u32_t unused_5[13]; + u32_t cp_cpq_ftq_cmd; + #define CP_CPQ_FTQ_CMD_OFFSET (0x3ffUL<<0) + #define CP_CPQ_FTQ_CMD_WR_TOP (1UL<<10) + #define CP_CPQ_FTQ_CMD_WR_TOP_0 (0UL<<10) + #define CP_CPQ_FTQ_CMD_WR_TOP_1 (1UL<<10) + #define CP_CPQ_FTQ_CMD_SFT_RESET (1UL<<25) + #define CP_CPQ_FTQ_CMD_RD_DATA (1UL<<26) + #define CP_CPQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define CP_CPQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define CP_CPQ_FTQ_CMD_INTERVENE_CLR (1UL<<29) + #define CP_CPQ_FTQ_CMD_POP (1UL<<30) + #define CP_CPQ_FTQ_CMD_BUSY (1UL<<31) + + u32_t cp_cpq_ftq_ctl; + #define CP_CPQ_FTQ_CTL_INTERVENE (1UL<<0) + #define CP_CPQ_FTQ_CTL_OVERFLOW (1UL<<1) + #define CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + + u32_t unused_6[27392]; + u32_t cp_scratch[10240]; + u32_t unused_7[22528]; +} cp_reg_t; + +typedef cp_reg_t cmd_processor_reg_t; + +/* + * management_enqueue definition + * offset: 0000 + */ +typedef struct management_enqueue +{ + u32_t management_enqueue_bits_status; + #define MANAGEMENT_ENQUEUE_BITS_STATUS_RULE_CLASS (0x7UL<<0) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_RULE_P2 (1UL<<3) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_RULE_P3 (1UL<<4) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_RULE_P4 (1UL<<5) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_L2_VLAN_TAG (1UL<<6) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_L2_LLC_SNAP (1UL<<7) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_RSS_HASH (1UL<<8) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_SORT_VECT (0xfUL<<9) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_IP_DATAGRAM (1UL<<13) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_TCP_SEGMENT (1UL<<14) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_UDP_DATAGRAM (1UL<<15) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_CU_FRAME (1UL<<16) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_IP_PROG_EXT (1UL<<17) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_IP_TYPE (1UL<<18) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_RULE_P1 (1UL<<19) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_RLUP_HIT4 (1UL<<20) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_IP_FRAGMENT (1UL<<21) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_IP_OPTIONS_PRESENT (1UL<<22) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_TCP_OPTIONS_PRESENT (1UL<<23) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_L2_PM_IDX (0xfUL<<24) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_L2_PM_HIT (1UL<<28) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_L2_MC_HASH_HIT (1UL<<29) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_RDMAC_CRC_PASS (1UL<<30) + #define MANAGEMENT_ENQUEUE_BITS_STATUS_MP_HIT (1UL<<31) + + u32_t management_enqueue_wd1; + #define MANAGEMENT_ENQUEUE_PKT_LEN_VALUE (0x3fff<<16) + #define MANAGEMENT_ENQUEUE_VLAN_TAG (0xffff<<0) + + u32_t management_enqueue_mbuf_cluster; + #define MANAGEMENT_ENQUEUE_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) + + u32_t management_enqueue_frm_errors; + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_L2_BAD_CRC (1UL<<1) + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_L2_PHY_DECODE (1UL<<2) + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_L2_ALIGNMENT (1UL<<3) + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_L2_TOO_SHORT (1UL<<4) + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_L2_GIANT_FRAME (1UL<<5) + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_IP_BAD_LEN (1UL<<6) + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_IP_TOO_SHORT (1UL<<7) + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_IP_BAD_VERSION (1UL<<8) + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_IP_BAD_HLEN (1UL<<9) + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_IP_BAD_XSUM (1UL<<10) + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_TCP_TOO_SHORT (1UL<<11) + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_TCP_BAD_XSUM (1UL<<12) + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_TCP_BAD_OFFSET (1UL<<13) + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_UDP_BAD_XSUM (1UL<<15) + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_IP_BAD_ORDER (1UL<<16) + #define MANAGEMENT_ENQUEUE_FRM_ERRORS_IP_HDR_MISMATCH (1UL<<18) + + u32_t management_enqueue_wd4; + #define MANAGEMENT_ENQUEUE_EXT_STATUS_TCP_SYNC_PRESENT (1<<16) + #define MANAGEMENT_ENQUEUE_EXT_STATUS_RLUP_HIT2 (1<<17) + #define MANAGEMENT_ENQUEUE_EXT_STATUS_TCP_UDP_XSUM_IS_0 (1<<18) + #define MANAGEMENT_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT (0x3<<19) + #define MANAGEMENT_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_00 (0<<19) + #define MANAGEMENT_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_01 (1<<19) + #define MANAGEMENT_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_10 (2<<19) + #define MANAGEMENT_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_11 (3<<19) + #define MANAGEMENT_ENQUEUE_EXT_STATUS_ACPI_MATCH (1<<21) + #define MANAGEMENT_ENQUEUE_RESERVED (0xffff<<0) + +} management_enqueue_t; + + +/* + * mcp_reg definition + * offset: 0x140000 + */ +typedef struct mcp_reg +{ + u32_t unused_0[32]; + u32_t mcp_mcp_control; + #define MCP_MCP_CONTROL_SMBUS_SEL (1UL<<30) + #define MCP_MCP_CONTROL_MCP_ISOLATE (1UL<<31) + + u32_t mcp_mcp_attention_status; + #define MCP_MCP_ATTENTION_STATUS_DRV_DOORBELL (1UL<<29) + #define MCP_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT (1UL<<30) + #define MCP_MCP_ATTENTION_STATUS_CPU_EVENT (1UL<<31) + + u32_t mcp_mcp_heartbeat_control; + #define MCP_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE (1UL<<31) + + u32_t mcp_mcp_heartbeat_status; + #define MCP_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD (0x7ffUL<<0) + #define MCP_MCP_HEARTBEAT_STATUS_VALID (1UL<<31) + + u32_t mcp_mcp_heartbeat; + #define MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT (0x3fffffffUL<<0) + #define MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_INC (1UL<<30) + #define MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET (1UL<<31) + + u32_t mcp_watchdog_reset; + #define MCP_WATCHDOG_RESET_WATCHDOG_RESET (1UL<<31) + + u32_t mcp_watchdog_control; + #define MCP_WATCHDOG_CONTROL_WATCHDOG_TIMEOUT (0xfffffffUL<<0) + #define MCP_WATCHDOG_CONTROL_WATCHDOG_ATTN (1UL<<29) + #define MCP_WATCHDOG_CONTROL_MCP_RST_ENABLE (1UL<<30) + #define MCP_WATCHDOG_CONTROL_WATCHDOG_ENABLE (1UL<<31) + + u32_t mcp_access_lock; + #define MCP_ACCESS_LOCK_LOCK (1UL<<31) + + u32_t mcp_toe_id; + #define MCP_TOE_ID_FUNCTION_ID (1UL<<31) + + u32_t mcp_mailbox_cfg; + #define MCP_MAILBOX_CFG_MAILBOX_OFFSET (0x3fffUL<<0) + #define MCP_MAILBOX_CFG_MAILBOX_SIZE (0xfffUL<<20) + + u32_t mcp_mailbox_cfg_other_func; + #define MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET (0x3fffUL<<0) + #define MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE (0xfffUL<<20) + + u32_t mcp_mcp_doorbell; + #define MCP_MCP_DOORBELL_MCP_DOORBELL (1UL<<31) + + u32_t mcp_driver_doorbell; + #define MCP_DRIVER_DOORBELL_DRIVER_DOORBELL (1UL<<31) + + u32_t mcp_driver_doorbell_other_func; + #define MCP_DRIVER_DOORBELL_OTHER_FUNC_DRIVER_DOORBELL (1UL<<31) + + u32_t unused_1[5074]; + u32_t mcp_cpu_mode; + #define MCP_CPU_MODE_LOCAL_RST (1UL<<0) + #define MCP_CPU_MODE_STEP_ENA (1UL<<1) + #define MCP_CPU_MODE_PAGE_0_DATA_ENA (1UL<<2) + #define MCP_CPU_MODE_PAGE_0_INST_ENA (1UL<<3) + #define MCP_CPU_MODE_MSG_BIT1 (1UL<<6) + #define MCP_CPU_MODE_INTERRUPT_ENA (1UL<<7) + #define MCP_CPU_MODE_SOFT_HALT (1UL<<10) + #define MCP_CPU_MODE_BAD_DATA_HALT_ENA (1UL<<11) + #define MCP_CPU_MODE_BAD_INST_HALT_ENA (1UL<<12) + #define MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1UL<<13) + #define MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1UL<<15) + + u32_t mcp_cpu_state; + #define MCP_CPU_STATE_BREAKPOINT (1UL<<0) + #define MCP_CPU_STATE_BAD_INST_HALTED (1UL<<2) + #define MCP_CPU_STATE_PAGE_0_DATA_HALTED (1UL<<3) + #define MCP_CPU_STATE_PAGE_0_INST_HALTED (1UL<<4) + #define MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1UL<<5) + #define MCP_CPU_STATE_BAD_PC_HALTED (1UL<<6) + #define MCP_CPU_STATE_ALIGN_HALTED (1UL<<7) + #define MCP_CPU_STATE_FIO_ABORT_HALTED (1UL<<8) + #define MCP_CPU_STATE_SOFT_HALTED (1UL<<10) + #define MCP_CPU_STATE_SPAD_UNDERFLOW (1UL<<11) + #define MCP_CPU_STATE_INTERRRUPT (1UL<<12) + #define MCP_CPU_STATE_DATA_ACCESS_STALL (1UL<<14) + #define MCP_CPU_STATE_INST_FETCH_STALL (1UL<<15) + #define MCP_CPU_STATE_BLOCKED_READ (1UL<<31) + + u32_t mcp_cpu_event_mask; + #define MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1UL<<0) + #define MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1UL<<2) + #define MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1UL<<3) + #define MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1UL<<4) + #define MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1UL<<5) + #define MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1UL<<6) + #define MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1UL<<7) + #define MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1UL<<8) + #define MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1UL<<10) + #define MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1UL<<11) + #define MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1UL<<12) + + u32_t unused_2[4]; + u32_t mcp_cpu_program_counter; + u32_t mcp_cpu_instruction; + u32_t mcp_cpu_data_access; + u32_t mcp_cpu_interrupt_enable; + u32_t mcp_cpu_interrupt_vector; + u32_t mcp_cpu_interrupt_saved_PC; + u32_t mcp_cpu_hw_breakpoint; + #define MCP_CPU_HW_BREAKPOINT_DISABLE (1UL<<0) + #define MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffUL<<2) + + u32_t mcp_cpu_debug_vect_peek; + #define MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) + #define MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) + #define MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) + #define MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) + #define MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) + #define MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) + + u32_t unused_3[3]; + u32_t mcp_cpu_last_branch_addr; + #define MCP_CPU_LAST_BRANCH_ADDR_TYPE (1UL<<1) + #define MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0UL<<1) + #define MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1UL<<1) + #define MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffUL<<2) + + u32_t unused_4[109]; + u32_t mcp_cpu_reg_file[32]; + u32_t unused_5[80]; + management_enqueue_t mcp_mcpq; + u32_t unused_6[9]; + u32_t mcp_mcpq_ftq_cmd; + #define MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffUL<<0) + #define MCP_MCPQ_FTQ_CMD_WR_TOP (1UL<<10) + #define MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0UL<<10) + #define MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1UL<<10) + #define MCP_MCPQ_FTQ_CMD_SFT_RESET (1UL<<25) + #define MCP_MCPQ_FTQ_CMD_RD_DATA (1UL<<26) + #define MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define MCP_MCPQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1UL<<29) + #define MCP_MCPQ_FTQ_CMD_POP (1UL<<30) + #define MCP_MCPQ_FTQ_CMD_BUSY (1UL<<31) + + u32_t mcp_mcpq_ftq_ctl; + #define MCP_MCPQ_FTQ_CTL_INTERVENE (1UL<<0) + #define MCP_MCPQ_FTQ_CTL_OVERFLOW (1UL<<1) + #define MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1UL<<2) + #define MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) + #define MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) + + u32_t unused_7[1024]; + u32_t mcp_nvm_command; + #define MCP_NVM_COMMAND_RST (1UL<<0) + #define MCP_NVM_COMMAND_DONE (1UL<<3) + #define MCP_NVM_COMMAND_DOIT (1UL<<4) + #define MCP_NVM_COMMAND_WR (1UL<<5) + #define MCP_NVM_COMMAND_ERASE (1UL<<6) + #define MCP_NVM_COMMAND_FIRST (1UL<<7) + #define MCP_NVM_COMMAND_LAST (1UL<<8) + #define MCP_NVM_COMMAND_WREN (1UL<<16) + #define MCP_NVM_COMMAND_WRDI (1UL<<17) + #define MCP_NVM_COMMAND_RD_ID (1UL<<20) + #define MCP_NVM_COMMAND_RD_STATUS (1UL<<21) + #define MCP_NVM_COMMAND_MODE_256 (1UL<<22) + + u32_t mcp_nvm_status; + #define MCP_NVM_STATUS_SPI_FSM_STATE (0x1fUL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE (0UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0 (1UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1 (2UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0 (3UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1 (4UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0 (5UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0 (6UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1 (7UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2 (8UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0 (9UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1 (10UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2 (11UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0 (12UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1 (13UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2 (14UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3 (15UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4 (16UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0 (17UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN (18UL<<0) + #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT (19UL<<0) + + u32_t mcp_nvm_write; + #define MCP_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffUL<<0) + #define MCP_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0UL<<0) + #define MCP_NVM_WRITE_NVM_WRITE_VALUE_SI (1UL<<0) + #define MCP_NVM_WRITE_NVM_WRITE_VALUE_SO (2UL<<0) + #define MCP_NVM_WRITE_NVM_WRITE_VALUE_CS_B (4UL<<0) + #define MCP_NVM_WRITE_NVM_WRITE_VALUE_SCLK (8UL<<0) + + u32_t mcp_nvm_addr; + #define MCP_NVM_ADDR_NVM_ADDR_VALUE (0xffffffUL<<0) + #define MCP_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0UL<<0) + #define MCP_NVM_ADDR_NVM_ADDR_VALUE_SI (1UL<<0) + #define MCP_NVM_ADDR_NVM_ADDR_VALUE_SO (2UL<<0) + #define MCP_NVM_ADDR_NVM_ADDR_VALUE_CS_B (4UL<<0) + #define MCP_NVM_ADDR_NVM_ADDR_VALUE_SCLK (8UL<<0) + + u32_t mcp_nvm_read; + #define MCP_NVM_READ_NVM_READ_VALUE (0xffffffffUL<<0) + #define MCP_NVM_READ_NVM_READ_VALUE_BIT_BANG (0UL<<0) + #define MCP_NVM_READ_NVM_READ_VALUE_SI (1UL<<0) + #define MCP_NVM_READ_NVM_READ_VALUE_SO (2UL<<0) + #define MCP_NVM_READ_NVM_READ_VALUE_CS_B (4UL<<0) + #define MCP_NVM_READ_NVM_READ_VALUE_SCLK (8UL<<0) + + u32_t mcp_nvm_cfg1; + #define MCP_NVM_CFG1_FLASH_MODE (1UL<<0) + #define MCP_NVM_CFG1_BUFFER_MODE (1UL<<1) + #define MCP_NVM_CFG1_PASS_MODE (1UL<<2) + #define MCP_NVM_CFG1_BITBANG_MODE (1UL<<3) + #define MCP_NVM_CFG1_STATUS_BIT (0x7UL<<4) + #define MCP_NVM_CFG1_SPI_CLK_DIV (0xfUL<<7) + #define MCP_NVM_CFG1_SEE_CLK_DIV (0x7ffUL<<11) + #define MCP_NVM_CFG1_STRAP_CONTROL_0 (1UL<<23) + #define MCP_NVM_CFG1_PROTECT_MODE (1UL<<24) + #define MCP_NVM_CFG1_FLASH_SIZE (1UL<<25) + #define MCP_NVM_CFG1_FW_USTRAP_1 (1UL<<26) + #define MCP_NVM_CFG1_FW_USTRAP_0 (1UL<<27) + #define MCP_NVM_CFG1_FW_USTRAP_2 (1UL<<28) + #define MCP_NVM_CFG1_FW_USTRAP_3 (1UL<<29) + #define MCP_NVM_CFG1_FW_FLASH_TYPE_EN (1UL<<30) + #define MCP_NVM_CFG1_COMPAT_BYPASSS (1UL<<31) + + u32_t mcp_nvm_cfg2; + #define MCP_NVM_CFG2_ERASE_CMD (0xffUL<<0) + #define MCP_NVM_CFG2_STATUS_CMD (0xffUL<<16) + #define MCP_NVM_CFG2_READ_ID (0xffUL<<24) + + u32_t mcp_nvm_cfg3; + #define MCP_NVM_CFG3_BUFFER_RD_CMD (0xffUL<<0) + #define MCP_NVM_CFG3_WRITE_CMD (0xffUL<<8) + #define MCP_NVM_CFG3_READ_CMD (0xffUL<<24) + + u32_t mcp_nvm_sw_arb; + #define MCP_NVM_SW_ARB_ARB_REQ_SET0 (1UL<<0) + #define MCP_NVM_SW_ARB_ARB_REQ_SET1 (1UL<<1) + #define MCP_NVM_SW_ARB_ARB_REQ_SET2 (1UL<<2) + #define MCP_NVM_SW_ARB_ARB_REQ_SET3 (1UL<<3) + #define MCP_NVM_SW_ARB_ARB_REQ_CLR0 (1UL<<4) + #define MCP_NVM_SW_ARB_ARB_REQ_CLR1 (1UL<<5) + #define MCP_NVM_SW_ARB_ARB_REQ_CLR2 (1UL<<6) + #define MCP_NVM_SW_ARB_ARB_REQ_CLR3 (1UL<<7) + #define MCP_NVM_SW_ARB_ARB_ARB0 (1UL<<8) + #define MCP_NVM_SW_ARB_ARB_ARB1 (1UL<<9) + #define MCP_NVM_SW_ARB_ARB_ARB2 (1UL<<10) + #define MCP_NVM_SW_ARB_ARB_ARB3 (1UL<<11) + #define MCP_NVM_SW_ARB_REQ0 (1UL<<12) + #define MCP_NVM_SW_ARB_REQ1 (1UL<<13) + #define MCP_NVM_SW_ARB_REQ2 (1UL<<14) + #define MCP_NVM_SW_ARB_REQ3 (1UL<<15) + + u32_t mcp_nvm_access_enable; + #define MCP_NVM_ACCESS_ENABLE_EN (1UL<<0) + #define MCP_NVM_ACCESS_ENABLE_WR_EN (1UL<<1) + + u32_t mcp_nvm_write1; + #define MCP_NVM_WRITE1_WREN_CMD (0xffUL<<0) + #define MCP_NVM_WRITE1_WRDI_CMD (0xffUL<<8) + + u32_t mcp_nvm_cfg4; + #define MCP_NVM_CFG4_FLASH_SIZE (0x7UL<<0) + #define MCP_NVM_CFG4_FLASH_SIZE_1MBIT (0UL<<0) + #define MCP_NVM_CFG4_FLASH_SIZE_2MBIT (1UL<<0) + #define MCP_NVM_CFG4_FLASH_SIZE_4MBIT (2UL<<0) + #define MCP_NVM_CFG4_FLASH_SIZE_8MBIT (3UL<<0) + #define MCP_NVM_CFG4_FLASH_SIZE_16MBIT (4UL<<0) + #define MCP_NVM_CFG4_FLASH_SIZE_32MBIT (5UL<<0) + #define MCP_NVM_CFG4_FLASH_SIZE_64MBIT (6UL<<0) + #define MCP_NVM_CFG4_FLASH_SIZE_128MBIT (7UL<<0) + #define MCP_NVM_CFG4_FLASH_VENDOR (1UL<<3) + #define MCP_NVM_CFG4_FLASH_VENDOR_ST (0UL<<3) + #define MCP_NVM_CFG4_FLASH_VENDOR_ATMEL (1UL<<3) + #define MCP_NVM_CFG4_MODE_256_EMPTY_BIT_LOC (0x3UL<<4) + #define MCP_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 (0UL<<4) + #define MCP_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9 (1UL<<4) + #define MCP_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10 (2UL<<4) + #define MCP_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11 (3UL<<4) + #define MCP_NVM_CFG4_STATUS_BIT_POLARITY (1UL<<6) + #define MCP_NVM_CFG4_RESERVED (0x1ffffffUL<<7) + + u32_t mcp_nvm_reconfig; + #define MCP_NVM_RECONFIG_ORIG_STRAP_VALUE (0xfUL<<0) + #define MCP_NVM_RECONFIG_ORIG_STRAP_VALUE_ST (0UL<<0) + #define MCP_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL (1UL<<0) + #define MCP_NVM_RECONFIG_RECONFIG_STRAP_VALUE (0xfUL<<4) + #define MCP_NVM_RECONFIG_RESERVED (0x7fffffUL<<8) + #define MCP_NVM_RECONFIG_RECONFIG_DONE (1UL<<31) + + u32_t unused_8[1779]; + u32_t mcp_smbus_config; + #define MCP_SMBUS_CONFIG_HW_ARP_ASSIGN_ADDR (1UL<<7) + #define MCP_SMBUS_CONFIG_ARP_EN0 (1UL<<8) + #define MCP_SMBUS_CONFIG_ARP_EN1 (1UL<<9) + #define MCP_SMBUS_CONFIG_MASTER_RTRY_CNT (0xfUL<<16) + #define MCP_SMBUS_CONFIG_TIMESTAMP_CNT_EN (1UL<<26) + #define MCP_SMBUS_CONFIG_PROMISCOUS_MODE (1UL<<27) + #define MCP_SMBUS_CONFIG_EN_NIC_SMB_ADDR_0 (1UL<<28) + #define MCP_SMBUS_CONFIG_BIT_BANG_EN (1UL<<29) + #define MCP_SMBUS_CONFIG_SMB_EN (1UL<<30) + #define MCP_SMBUS_CONFIG_RESET (1UL<<31) + + u32_t mcp_smbus_timing_config; + #define MCP_SMBUS_TIMING_CONFIG_SMBUS_IDLE_TIME (0xffUL<<8) + #define MCP_SMBUS_TIMING_CONFIG_PERIODIC_SLAVE_STRETCH (0xffUL<<16) + #define MCP_SMBUS_TIMING_CONFIG_RANDOM_SLAVE_STRETCH (0x7fUL<<24) + #define MCP_SMBUS_TIMING_CONFIG_MODE_400 (1UL<<31) + + u32_t mcp_smbus_address; + #define MCP_SMBUS_ADDRESS_NIC_SMB_ADDR0 (0x7fUL<<0) + #define MCP_SMBUS_ADDRESS_EN_NIC_SMB_ADDR0 (1UL<<7) + #define MCP_SMBUS_ADDRESS_NIC_SMB_ADDR1 (0x7fUL<<8) + #define MCP_SMBUS_ADDRESS_EN_NIC_SMB_ADDR1 (1UL<<15) + #define MCP_SMBUS_ADDRESS_NIC_SMB_ADDR2 (0x7fUL<<16) + #define MCP_SMBUS_ADDRESS_EN_NIC_SMB_ADDR2 (1UL<<23) + #define MCP_SMBUS_ADDRESS_NIC_SMB_ADDR3 (0x7fUL<<24) + #define MCP_SMBUS_ADDRESS_EN_NIC_SMB_ADDR3 (1UL<<31) + + u32_t mcp_smbus_master_fifo_control; + #define MCP_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_THRESHOLD (0x7fUL<<8) + #define MCP_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_PKT_COUNT (0x7fUL<<16) + #define MCP_SMBUS_MASTER_FIFO_CONTROL_MASTER_TX_FIFO_FLUSH (1UL<<30) + #define MCP_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_FLUSH (1UL<<31) + + u32_t mcp_smbus_slave_fifo_control; + #define MCP_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_THRESHOLD (0x7fUL<<8) + #define MCP_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_PKT_COUNT (0x7fUL<<16) + #define MCP_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_TX_FIFO_FLUSH (1UL<<30) + #define MCP_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_FLUSH (1UL<<31) + + u32_t mcp_smbus_bit_bang_control; + #define MCP_SMBUS_BIT_BANG_CONTROL_SMBDAT_OUT_EN (1UL<<28) + #define MCP_SMBUS_BIT_BANG_CONTROL_SMBDAT_IN (1UL<<29) + #define MCP_SMBUS_BIT_BANG_CONTROL_SMBCLK_OUT_EN (1UL<<30) + #define MCP_SMBUS_BIT_BANG_CONTROL_SMBCLK_IN (1UL<<31) + + u32_t mcp_smbus_watchdog; + #define MCP_SMBUS_WATCHDOG_WATCHDOG (0xffffUL<<0) + + u32_t mcp_smbus_heartbeat; + #define MCP_SMBUS_HEARTBEAT_HEARTBEAT (0xffffUL<<0) + + u32_t mcp_smbus_poll_asf; + #define MCP_SMBUS_POLL_ASF_POLL_ASF (0xffffUL<<0) + + u32_t mcp_smbus_poll_legacy; + #define MCP_SMBUS_POLL_LEGACY_POLL_LEGACY (0xffffUL<<0) + + u32_t mcp_smbus_retran; + #define MCP_SMBUS_RETRAN_RETRAN (0xffUL<<0) + + u32_t mcp_smbus_timestamp; + #define MCP_SMBUS_TIMESTAMP_TIMESTAMP (0xffffffffUL<<0) + + u32_t mcp_smbus_master_command; + #define MCP_SMBUS_MASTER_COMMAND_RD_BYTE_COUNT (0xffUL<<0) + #define MCP_SMBUS_MASTER_COMMAND_PEC (1UL<<8) + #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL (0xfUL<<9) + #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0000 (0UL<<9) + #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0001 (1UL<<9) + #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0010 (2UL<<9) + #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0011 (3UL<<9) + #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0100 (4UL<<9) + #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0101 (5UL<<9) + #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0110 (6UL<<9) + #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0111 (7UL<<9) + #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1000 (8UL<<9) + #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1001 (9UL<<9) + #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1010 (10UL<<9) + #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1011 (11UL<<9) + #define MCP_SMBUS_MASTER_COMMAND_STATUS (0x7UL<<25) + #define MCP_SMBUS_MASTER_COMMAND_STATUS_000 (0UL<<25) + #define MCP_SMBUS_MASTER_COMMAND_STATUS_001 (1UL<<25) + #define MCP_SMBUS_MASTER_COMMAND_STATUS_010 (2UL<<25) + #define MCP_SMBUS_MASTER_COMMAND_STATUS_011 (3UL<<25) + #define MCP_SMBUS_MASTER_COMMAND_STATUS_100 (4UL<<25) + #define MCP_SMBUS_MASTER_COMMAND_STATUS_101 (5UL<<25) + #define MCP_SMBUS_MASTER_COMMAND_STATUS_110 (6UL<<25) + #define MCP_SMBUS_MASTER_COMMAND_STATUS_111 (7UL<<25) + #define MCP_SMBUS_MASTER_COMMAND_ABORT (1UL<<30) + #define MCP_SMBUS_MASTER_COMMAND_START_BUSY (1UL<<31) + + u32_t mcp_smbus_slave_command; + #define MCP_SMBUS_SLAVE_COMMAND_PEC (1UL<<8) + #define MCP_SMBUS_SLAVE_COMMAND_STATUS (0x7UL<<23) + #define MCP_SMBUS_SLAVE_COMMAND_STATUS_000 (0UL<<23) + #define MCP_SMBUS_SLAVE_COMMAND_STATUS_101 (5UL<<23) + #define MCP_SMBUS_SLAVE_COMMAND_STATUS_111 (7UL<<23) + #define MCP_SMBUS_SLAVE_COMMAND_ABORT (1UL<<30) + #define MCP_SMBUS_SLAVE_COMMAND_START (1UL<<31) + + u32_t mcp_smbus_event_enable; + #define MCP_SMBUS_EVENT_ENABLE_WATCHDOG_TO_EN (1UL<<0) + #define MCP_SMBUS_EVENT_ENABLE_HEARTBEAT_TO_EN (1UL<<1) + #define MCP_SMBUS_EVENT_ENABLE_POLL_ASF_TO_EN (1UL<<2) + #define MCP_SMBUS_EVENT_ENABLE_POLL_LEGACY_TO_EN (1UL<<3) + #define MCP_SMBUS_EVENT_ENABLE_RETRANSMIT_TO_EN (1UL<<4) + #define MCP_SMBUS_EVENT_ENABLE_SLAVE_ARP_EVENT_EN (1UL<<20) + #define MCP_SMBUS_EVENT_ENABLE_SLAVE_RD_EVENT_EN (1UL<<21) + #define MCP_SMBUS_EVENT_ENABLE_SLAVE_TX_UNDERRUN_EN (1UL<<22) + #define MCP_SMBUS_EVENT_ENABLE_SLAVE_START_BUSY_EN (1UL<<23) + #define MCP_SMBUS_EVENT_ENABLE_SLAVE_RX_EVENT_EN (1UL<<24) + #define MCP_SMBUS_EVENT_ENABLE_SLAVE_RX_THRESHOLD_HIT_EN (1UL<<25) + #define MCP_SMBUS_EVENT_ENABLE_SLAVE_RX_FIFO_FULL_EN (1UL<<26) + #define MCP_SMBUS_EVENT_ENABLE_MASTER_TX_UNDERRUN_EN (1UL<<27) + #define MCP_SMBUS_EVENT_ENABLE_MASTER_START_BUSY_EN (1UL<<28) + #define MCP_SMBUS_EVENT_ENABLE_MASTER_RX_EVENT_EN (1UL<<29) + #define MCP_SMBUS_EVENT_ENABLE_MASTER_RX_THRESHOLD_HIT_EN (1UL<<30) + #define MCP_SMBUS_EVENT_ENABLE_MASTER_RX_FIFO_FULL_EN (1UL<<31) + + u32_t mcp_smbus_event_status; + #define MCP_SMBUS_EVENT_STATUS_WATCHDOG_TO (1UL<<0) + #define MCP_SMBUS_EVENT_STATUS_HEARTBEAT_TO (1UL<<1) + #define MCP_SMBUS_EVENT_STATUS_POLL_ASF_TO (1UL<<2) + #define MCP_SMBUS_EVENT_STATUS_POLL_LEGACY_TO (1UL<<3) + #define MCP_SMBUS_EVENT_STATUS_RETRANSMIT_TO (1UL<<4) + #define MCP_SMBUS_EVENT_STATUS_SLAVE_ARP_EVENT (1UL<<20) + #define MCP_SMBUS_EVENT_STATUS_SLAVE_RD_EVENT (1UL<<21) + #define MCP_SMBUS_EVENT_STATUS_SLAVE_TX_UNDERRUN (1UL<<22) + #define MCP_SMBUS_EVENT_STATUS_SLAVE_START_BUSY (1UL<<23) + #define MCP_SMBUS_EVENT_STATUS_SLAVE_RX_EVENT (1UL<<24) + #define MCP_SMBUS_EVENT_STATUS_SLAVE_RX_THRESHOLD_HIT (1UL<<25) + #define MCP_SMBUS_EVENT_STATUS_SLAVE_RX_FIFO_FULL (1UL<<26) + #define MCP_SMBUS_EVENT_STATUS_MASTER_TX_UNDERRUN (1UL<<27) + #define MCP_SMBUS_EVENT_STATUS_MASTER_START_BUSY (1UL<<28) + #define MCP_SMBUS_EVENT_STATUS_MASTER_RX_EVENT (1UL<<29) + #define MCP_SMBUS_EVENT_STATUS_MASTER_RX_THRESHOLD_HIT (1UL<<30) + #define MCP_SMBUS_EVENT_STATUS_MASTER_RX_FIFO_FULL (1UL<<31) + + u32_t mcp_smbus_master_data_write; + #define MCP_SMBUS_MASTER_DATA_WRITE_MASTER_SMBUS_WR_DATA (0xffUL<<0) + #define MCP_SMBUS_MASTER_DATA_WRITE_WR_STATUS (1UL<<31) + + u32_t mcp_smbus_master_data_read; + #define MCP_SMBUS_MASTER_DATA_READ_MASTER_SMBUS_RD_DATA (0xffUL<<0) + #define MCP_SMBUS_MASTER_DATA_READ_PEC_ERR (1UL<<29) + #define MCP_SMBUS_MASTER_DATA_READ_RD_STATUS (0x3UL<<30) + #define MCP_SMBUS_MASTER_DATA_READ_RD_STATUS_00 (0UL<<30) + #define MCP_SMBUS_MASTER_DATA_READ_RD_STATUS_01 (1UL<<30) + #define MCP_SMBUS_MASTER_DATA_READ_RD_STATUS_10 (2UL<<30) + #define MCP_SMBUS_MASTER_DATA_READ_RD_STATUS_11 (3UL<<30) + + u32_t mcp_smbus_slave_data_write; + #define MCP_SMBUS_SLAVE_DATA_WRITE_SLAVE_SMBUS_WR_DATA (0xffUL<<0) + #define MCP_SMBUS_SLAVE_DATA_WRITE_WR_STATUS (1UL<<31) + #define MCP_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_0 (0UL<<31) + #define MCP_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_1 (1UL<<31) + + u32_t mcp_smbus_slave_data_read; + #define MCP_SMBUS_SLAVE_DATA_READ_SLAVE_SMBUS_RD_DATA (0xffUL<<0) + #define MCP_SMBUS_SLAVE_DATA_READ_ERR_STATUS (0x3UL<<28) + #define MCP_SMBUS_SLAVE_DATA_READ_ERR_STATUS_00 (0UL<<28) + #define MCP_SMBUS_SLAVE_DATA_READ_ERR_STATUS_01 (1UL<<28) + #define MCP_SMBUS_SLAVE_DATA_READ_ERR_STATUS_10 (2UL<<28) + #define MCP_SMBUS_SLAVE_DATA_READ_ERR_STATUS_11 (3UL<<28) + #define MCP_SMBUS_SLAVE_DATA_READ_RD_STATUS (0x3UL<<30) + #define MCP_SMBUS_SLAVE_DATA_READ_RD_STATUS_00 (0UL<<30) + #define MCP_SMBUS_SLAVE_DATA_READ_RD_STATUS_01 (1UL<<30) + #define MCP_SMBUS_SLAVE_DATA_READ_RD_STATUS_10 (2UL<<30) + #define MCP_SMBUS_SLAVE_DATA_READ_RD_STATUS_11 (3UL<<30) + + u32_t unused_9[12]; + u32_t mcp_smbus_arp_state; + #define MCP_SMBUS_ARP_STATE_AV_FLAG0 (1UL<<0) + #define MCP_SMBUS_ARP_STATE_AR_FLAG0 (1UL<<1) + #define MCP_SMBUS_ARP_STATE_AV_FLAG1 (1UL<<4) + #define MCP_SMBUS_ARP_STATE_AR_FLAG1 (1UL<<5) + + u32_t unused_10[3]; + u32_t mcp_smbus_udid0_3; + #define MCP_SMBUS_UDID0_3_BYTE_12 (0xffUL<<0) + #define MCP_SMBUS_UDID0_3_BYTE_13 (0xffUL<<8) + #define MCP_SMBUS_UDID0_3_BYTE_14 (0xffUL<<16) + #define MCP_SMBUS_UDID0_3_BYTE_15 (0xffUL<<24) + + u32_t mcp_smbus_udid0_2; + #define MCP_SMBUS_UDID0_2_BYTE_8 (0xffUL<<0) + #define MCP_SMBUS_UDID0_2_BYTE_9 (0xffUL<<8) + #define MCP_SMBUS_UDID0_2_BYTE_10 (0xffUL<<16) + #define MCP_SMBUS_UDID0_2_BYTE_11 (0xffUL<<24) + + u32_t mcp_smbus_udid0_1; + #define MCP_SMBUS_UDID0_1_BYTE_4 (0xffUL<<0) + #define MCP_SMBUS_UDID0_1_BYTE_5 (0xffUL<<8) + #define MCP_SMBUS_UDID0_1_BYTE_6 (0xffUL<<16) + #define MCP_SMBUS_UDID0_1_BYTE_7 (0xffUL<<24) + + u32_t mcp_smbus_udid0_0; + #define MCP_SMBUS_UDID0_0_BYTE_0 (0xffUL<<0) + #define MCP_SMBUS_UDID0_0_BYTE_1 (0xffUL<<8) + #define MCP_SMBUS_UDID0_0_BYTE_2 (0xffUL<<16) + #define MCP_SMBUS_UDID0_0_BYTE_3 (0xffUL<<24) + + u32_t mcp_smbus_udid1_3; + #define MCP_SMBUS_UDID1_3_BYTE_12 (0xffUL<<0) + #define MCP_SMBUS_UDID1_3_BYTE_13 (0xffUL<<8) + #define MCP_SMBUS_UDID1_3_BYTE_14 (0xffUL<<16) + #define MCP_SMBUS_UDID1_3_BYTE_15 (0xffUL<<24) + + u32_t mcp_smbus_udid1_2; + #define MCP_SMBUS_UDID1_2_BYTE_8 (0xffUL<<0) + #define MCP_SMBUS_UDID1_2_BYTE_9 (0xffUL<<8) + #define MCP_SMBUS_UDID1_2_BYTE_10 (0xffUL<<16) + #define MCP_SMBUS_UDID1_2_BYTE_11 (0xffUL<<24) + + u32_t mcp_smbus_udid1_1; + #define MCP_SMBUS_UDID1_1_BYTE_4 (0xffUL<<0) + #define MCP_SMBUS_UDID1_1_BYTE_5 (0xffUL<<8) + #define MCP_SMBUS_UDID1_1_BYTE_6 (0xffUL<<16) + #define MCP_SMBUS_UDID1_1_BYTE_7 (0xffUL<<24) + + u32_t mcp_smbus_udid1_0; + #define MCP_SMBUS_UDID1_0_BYTE_0 (0xffUL<<0) + #define MCP_SMBUS_UDID1_0_BYTE_1 (0xffUL<<8) + #define MCP_SMBUS_UDID1_0_BYTE_2 (0xffUL<<16) + #define MCP_SMBUS_UDID1_0_BYTE_3 (0xffUL<<24) + + u32_t unused_11[468]; + u32_t mcp_legacy_smb_asf_control; + #define MCP_LEGACY_SMB_ASF_CONTROL_ASF_RST (1UL<<0) + #define MCP_LEGACY_SMB_ASF_CONTROL_TSC_EN (1UL<<1) + #define MCP_LEGACY_SMB_ASF_CONTROL_WG_TO (1UL<<2) + #define MCP_LEGACY_SMB_ASF_CONTROL_HB_TO (1UL<<3) + #define MCP_LEGACY_SMB_ASF_CONTROL_PA_TO (1UL<<4) + #define MCP_LEGACY_SMB_ASF_CONTROL_PL_TO (1UL<<5) + #define MCP_LEGACY_SMB_ASF_CONTROL_RT_TO (1UL<<6) + #define MCP_LEGACY_SMB_ASF_CONTROL_SMB_EVENT (1UL<<7) + #define MCP_LEGACY_SMB_ASF_CONTROL_STRETCH_EN (1UL<<8) + #define MCP_LEGACY_SMB_ASF_CONTROL_STRETCH_PULSE (1UL<<9) + #define MCP_LEGACY_SMB_ASF_CONTROL_RES (0x3UL<<10) + #define MCP_LEGACY_SMB_ASF_CONTROL_SMB_EN (1UL<<12) + #define MCP_LEGACY_SMB_ASF_CONTROL_SMB_BB_EN (1UL<<13) + #define MCP_LEGACY_SMB_ASF_CONTROL_SMB_NO_ADDR_FILT (1UL<<14) + #define MCP_LEGACY_SMB_ASF_CONTROL_SMB_AUTOREAD (1UL<<15) + #define MCP_LEGACY_SMB_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fUL<<16) + #define MCP_LEGACY_SMB_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fUL<<23) + #define MCP_LEGACY_SMB_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1UL<<30) + #define MCP_LEGACY_SMB_ASF_CONTROL_SMB_EARLY_ATTN (1UL<<31) + + u32_t mcp_legacy_smb_in; + #define MCP_LEGACY_SMB_IN_DAT_IN (0xffUL<<0) + #define MCP_LEGACY_SMB_IN_RDY (1UL<<8) + #define MCP_LEGACY_SMB_IN_DONE (1UL<<9) + #define MCP_LEGACY_SMB_IN_FIRSTBYTE (1UL<<10) + #define MCP_LEGACY_SMB_IN_STATUS (0x7UL<<11) + #define MCP_LEGACY_SMB_IN_STATUS_OK (0UL<<11) + #define MCP_LEGACY_SMB_IN_STATUS_PEC (1UL<<11) + #define MCP_LEGACY_SMB_IN_STATUS_OFLOW (2UL<<11) + #define MCP_LEGACY_SMB_IN_STATUS_STOP (3UL<<11) + #define MCP_LEGACY_SMB_IN_STATUS_TIMEOUT (4UL<<11) + + u32_t mcp_legacy_smb_out; + #define MCP_LEGACY_SMB_OUT_DAT_OUT (0xffUL<<0) + #define MCP_LEGACY_SMB_OUT_RDY (1UL<<8) + #define MCP_LEGACY_SMB_OUT_START (1UL<<9) + #define MCP_LEGACY_SMB_OUT_LAST (1UL<<10) + #define MCP_LEGACY_SMB_OUT_ACC_TYPE (1UL<<11) + #define MCP_LEGACY_SMB_OUT_ENB_PEC (1UL<<12) + #define MCP_LEGACY_SMB_OUT_GET_RX_LEN (1UL<<13) + #define MCP_LEGACY_SMB_OUT_SMB_READ_LEN (0x3fUL<<14) + #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS (0xfUL<<20) + #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_OK (0UL<<20) + #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1UL<<20) + #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_UFLOW (2UL<<20) + #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_STOP (3UL<<20) + #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4UL<<20) + #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5UL<<20) + #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_BADACK (6UL<<20) + #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9UL<<20) + #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (13UL<<20) + #define MCP_LEGACY_SMB_OUT_SMB_OUT_SLAVEMODE (1UL<<24) + #define MCP_LEGACY_SMB_OUT_SMB_OUT_DAT_EN (1UL<<25) + #define MCP_LEGACY_SMB_OUT_SMB_OUT_DAT_IN (1UL<<26) + #define MCP_LEGACY_SMB_OUT_SMB_OUT_CLK_EN (1UL<<27) + #define MCP_LEGACY_SMB_OUT_SMB_OUT_CLK_IN (1UL<<28) + + u32_t mcp_legacy_smb_watchdog; + #define MCP_LEGACY_SMB_WATCHDOG_WATCHDOG (0xffffUL<<0) + + u32_t mcp_legacy_smb_heartbeat; + #define MCP_LEGACY_SMB_HEARTBEAT_HEARTBEAT (0xffffUL<<0) + + u32_t mcp_legacy_smb_poll_asf; + #define MCP_LEGACY_SMB_POLL_ASF_POLL_ASF (0xffffUL<<0) + + u32_t mcp_legacy_smb_poll_legacy; + #define MCP_LEGACY_SMB_POLL_LEGACY_POLL_LEGACY (0xffffUL<<0) + + u32_t mcp_legacy_smb_retran; + #define MCP_LEGACY_SMB_RETRAN_RETRAN (0xffUL<<0) + + u32_t mcp_legacy_smb_timestamp; + #define MCP_LEGACY_SMB_TIMESTAMP_TIMESTAMP (0xffffffffUL<<0) + + u32_t unused_12[7671]; + u32_t mcp_rom[320]; + u32_t unused_13[7872]; + u32_t mcp_ump_ump_cmd; + #define MCP_UMP_UMP_CMD_EGRESS_FIFO_ENABLED (1UL<<0) + #define MCP_UMP_UMP_CMD_INGRESS_FIFO_ENABLED (1UL<<1) + #define MCP_UMP_UMP_CMD_FC_EN (1UL<<2) + #define MCP_UMP_UMP_CMD_MAC_LOOPBACK (1UL<<3) + #define MCP_UMP_UMP_CMD_EGRESS_MAC_DISABLE (1UL<<5) + #define MCP_UMP_UMP_CMD_INGRESS_MAC_DISABLE (1UL<<6) + #define MCP_UMP_UMP_CMD_INGRESS_DRIVE (1UL<<8) + #define MCP_UMP_UMP_CMD_SW_PAUSE (1UL<<9) + #define MCP_UMP_UMP_CMD_AUTO_DRIVE (1UL<<13) + #define MCP_UMP_UMP_CMD_INGRESS_RESET (1UL<<14) + #define MCP_UMP_UMP_CMD_NO_PLUS_TWO (1UL<<15) + #define MCP_UMP_UMP_CMD_EGRESS_PKT_FLUSH (1UL<<16) + #define MCP_UMP_UMP_CMD_CMD_IPG (0x1fUL<<17) + #define MCP_UMP_UMP_CMD_EGRESS_FIO_RESET (1UL<<28) + #define MCP_UMP_UMP_CMD_INGRESS_FIO_RESET (1UL<<29) + #define MCP_UMP_UMP_CMD_EGRESS_MAC_RESET (1UL<<30) + #define MCP_UMP_UMP_CMD_INGRESS_MAC_RESET (1UL<<31) + + u32_t mcp_ump_ump_config; + #define MCP_UMP_UMP_CONFIG_RMII_MODE (1UL<<4) + #define MCP_UMP_UMP_CONFIG_RVMII_MODE (1UL<<6) + #define MCP_UMP_UMP_CONFIG_INGRESS_MODE (1UL<<7) + #define MCP_UMP_UMP_CONFIG_INGRESS_WORD_ACCM (0xffUL<<8) + + u32_t mcp_ump_ump_fc_trip; + #define MCP_UMP_UMP_FC_TRIP_XON_TRIP (0x1ffUL<<0) + #define MCP_UMP_UMP_FC_TRIP_XOFF_TRIP (0x1ffUL<<16) + + u32_t unused_14[33]; + u32_t mcp_ump_ump_egress_frm_rd_status; + #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_NEW_FRM (1UL<<0) + #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_FRM_IN_PRO (1UL<<1) + #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_FIFO_EMPTY (1UL<<2) + #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_BCNT (0x7ffUL<<3) + #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE (0x1fUL<<27) + #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_IDLE (0UL<<27) + #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_READY (1UL<<27) + #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_BUSY (2UL<<27) + #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_EXTRA_RD (3UL<<27) + #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_LATCH_IP_HDR (4UL<<27) + + u32_t mcp_ump_ump_egress_frm_rd_data; + u32_t mcp_ump_ump_ingress_frm_wr_ctl; + #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_NEW_FRM (1UL<<0) + #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_FIFO_RDY (1UL<<1) + #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_BCNT_RDY (1UL<<2) + #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_BCNT (0x7ffUL<<3) + #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE (0x3UL<<30) + #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_IDLE (0UL<<30) + #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_WAIT (1UL<<30) + #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_BUSY (2UL<<30) + #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_EXTRA_WR (3UL<<30) + + u32_t mcp_ump_ump_ingress_frm_wr_data; + u32_t mcp_ump_ump_egress_frame_type; + u32_t mcp_ump_ump_fifo_remaining_words; + #define MCP_UMP_UMP_FIFO_REMAINING_WORDS_EGRESS_FIFO_DEPTH (0x7ffUL<<0) + #define MCP_UMP_UMP_FIFO_REMAINING_WORDS_INGRESS_FIFO_DEPTH (0x3ffUL<<16) + + u32_t mcp_ump_ump_egress_fifo_ptrs; + #define MCP_UMP_UMP_EGRESS_FIFO_PTRS_EGRESS_FIFO_RD_PTR (0xfffUL<<0) + #define MCP_UMP_UMP_EGRESS_FIFO_PTRS_UPDATE_RDPTR (1UL<<15) + #define MCP_UMP_UMP_EGRESS_FIFO_PTRS_EGRESS_FIFO_WR_PTR (0xfffUL<<16) + #define MCP_UMP_UMP_EGRESS_FIFO_PTRS_UPDATE_WRPTR (1UL<<31) + + u32_t mcp_ump_ump_ingress_fifo_ptrs; + #define MCP_UMP_UMP_INGRESS_FIFO_PTRS_INGRESS_FIFO_RD_PTR (0x7ffUL<<0) + #define MCP_UMP_UMP_INGRESS_FIFO_PTRS_UPDATE_RDPTR (1UL<<15) + #define MCP_UMP_UMP_INGRESS_FIFO_PTRS_INGRESS_FIFO_WR_PTR (0x7ffUL<<16) + #define MCP_UMP_UMP_INGRESS_FIFO_PTRS_UPDATE_WRPTR (1UL<<31) + + u32_t unused_15; + u32_t mcp_ump_ump_egress_packet_sa_0; + #define MCP_UMP_UMP_EGRESS_PACKET_SA_0_EGRESS_SA (0xffffUL<<0) + + u32_t mcp_ump_ump_egress_packet_sa_1; + #define MCP_UMP_UMP_EGRESS_PACKET_SA_1_EGRESS_SA (0xffffffffUL<<0) + + u32_t mcp_ump_ump_ingress_burst_command; + #define MCP_UMP_UMP_INGRESS_BURST_COMMAND_INGRESS_DMA_START (1UL<<0) + #define MCP_UMP_UMP_INGRESS_BURST_COMMAND_INGRESS_PORT (1UL<<1) + #define MCP_UMP_UMP_INGRESS_BURST_COMMAND_DMA_LENGTH (0x7ffUL<<2) + #define MCP_UMP_UMP_INGRESS_BURST_COMMAND_RBUF_OFFSET (0x3fffUL<<16) + + u32_t mcp_ump_ump_ingress_rbuf_cluster; + #define MCP_UMP_UMP_INGRESS_RBUF_CLUSTER_RBUF_CLUSTER (0x1ffffffUL<<0) + + u32_t mcp_ump_ump_ingress_vlan; + #define MCP_UMP_UMP_INGRESS_VLAN_INGRESS_VLAN_TAG (0xffffUL<<0) + #define MCP_UMP_UMP_INGRESS_VLAN_VLAN_INS (1UL<<16) + #define MCP_UMP_UMP_INGRESS_VLAN_VLAN_DEL (1UL<<17) + + u32_t mcp_ump_ump_ingress_burst_status; + #define MCP_UMP_UMP_INGRESS_BURST_STATUS_RESULT (0x3UL<<0) + #define MCP_UMP_UMP_INGRESS_BURST_STATUS_RESULT_BUSY (0UL<<0) + #define MCP_UMP_UMP_INGRESS_BURST_STATUS_RESULT_DONE (1UL<<0) + #define MCP_UMP_UMP_INGRESS_BURST_STATUS_RESULT_ERR (2UL<<0) + #define MCP_UMP_UMP_INGRESS_BURST_STATUS_RESULT_ERR1 (3UL<<0) + + u32_t mcp_ump_ump_egress_burst_command; + #define MCP_UMP_UMP_EGRESS_BURST_COMMAND_EGRESS_DMA_START (1UL<<0) + #define MCP_UMP_UMP_EGRESS_BURST_COMMAND_EGRESS_PORT (1UL<<1) + #define MCP_UMP_UMP_EGRESS_BURST_COMMAND_DMA_LENGTH (0x7ffUL<<2) + #define MCP_UMP_UMP_EGRESS_BURST_COMMAND_TPBUF_OFFSET (0x1fffUL<<16) + + u32_t mcp_ump_ump_egress_vlan; + #define MCP_UMP_UMP_EGRESS_VLAN_EGRESS_VLAN_TAG (0xffffUL<<0) + #define MCP_UMP_UMP_EGRESS_VLAN_VLAN_INS (1UL<<16) + #define MCP_UMP_UMP_EGRESS_VLAN_VLAN_DEL (1UL<<17) + + u32_t mcp_ump_ump_egress_burst_status; + #define MCP_UMP_UMP_EGRESS_BURST_STATUS_RESULT (0x3UL<<0) + #define MCP_UMP_UMP_EGRESS_BURST_STATUS_RESULT_BUSY (0UL<<0) + #define MCP_UMP_UMP_EGRESS_BURST_STATUS_RESULT_DONE (1UL<<0) + #define MCP_UMP_UMP_EGRESS_BURST_STATUS_RESULT_ERR0 (2UL<<0) + #define MCP_UMP_UMP_EGRESS_BURST_STATUS_RESULT_RSVD (3UL<<0) + + u32_t mcp_ump_ump_egress_statistic; + #define MCP_UMP_UMP_EGRESS_STATISTIC_EGRESS_GOOD_CNT (0xffffUL<<0) + #define MCP_UMP_UMP_EGRESS_STATISTIC_EGRESS_ERROR_CNT (0xffUL<<16) + #define MCP_UMP_UMP_EGRESS_STATISTIC_EGRESS_DROP_CNT (0xffUL<<24) + + u32_t mcp_ump_ump_ingress_statistic; + #define MCP_UMP_UMP_INGRESS_STATISTIC_INGRESS_PKT_CNT (0xffffUL<<0) + + u32_t mcp_ump_ump_arb_cmd; + #define MCP_UMP_UMP_ARB_CMD_UMP_ID (0x7UL<<0) + #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_DISABLE (1UL<<4) + #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_START (1UL<<5) + #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_BYPASS (1UL<<6) + #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_AUTOBYPASS (1UL<<7) + #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_TOKEN_IPG (0x1fUL<<8) + #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_TOKEN_VALID (1UL<<13) + #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_FC_DISABLE (1UL<<15) + #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_TIMEOUT (0xffffUL<<16) + + u32_t unused_16[3]; + u32_t mcp_ump_ump_egress_statistic_ac; + #define MCP_UMP_UMP_EGRESS_STATISTIC_AC_EGRESS_GOOD_CNT (0xffffUL<<0) + #define MCP_UMP_UMP_EGRESS_STATISTIC_AC_EGRESS_ERROR_CNT (0xffUL<<16) + #define MCP_UMP_UMP_EGRESS_STATISTIC_AC_EGRESS_DROP_CNT (0xffUL<<24) + + u32_t mcp_ump_ump_ingress_statistic_ac; + #define MCP_UMP_UMP_INGRESS_STATISTIC_AC_INGRESS_PKT_CNT (0xffffUL<<0) + + u32_t mcp_ump_ump_event; + #define MCP_UMP_UMP_EVENT_INGRESS_RDY_EVENT (1UL<<0) + #define MCP_UMP_UMP_EVENT_EGRESS_RDY_EVENT (1UL<<1) + #define MCP_UMP_UMP_EVENT_INGRESSBURST_DONE_EVENT (1UL<<2) + #define MCP_UMP_UMP_EVENT_EGRESSBURST_DONE_EVENT (1UL<<3) + #define MCP_UMP_UMP_EVENT_EGRESS_FRAME_DROP_EVENT (1UL<<4) + #define MCP_UMP_UMP_EVENT_INGRESS_RDY_EVENT_EN (1UL<<16) + #define MCP_UMP_UMP_EVENT_EGRESS_RDY_EVENT_EN (1UL<<17) + #define MCP_UMP_UMP_EVENT_INGRESSBURST_DONE_EVENT_EN (1UL<<18) + #define MCP_UMP_UMP_EVENT_EGRESSBURST_DONE_EVENT_EN (1UL<<19) + #define MCP_UMP_UMP_EVENT_EGRESS_FRAME_DROP_EVENT_EN (1UL<<20) + + u32_t unused_17[4033]; + u32_t mcp_ump_ump_egress_fifo_flat_space[1920]; + u32_t unused_18[128]; + u32_t mcp_ump_ump_ingress_fifo_flat_space[768]; + u32_t unused_19[1280]; + u32_t mcp_scratch[16384]; + u32_t unused_20[16384]; +} mcp_reg_t; + +typedef mcp_reg_t management_reg_t; + +/* + * hb_reg definition + * offset: 0x240000 + */ +typedef struct hb_reg +{ + u32_t hb_command; + #define HB_COMMAND_ARM (1UL<<0) + #define HB_COMMAND_TRIG_NOW (1UL<<1) + #define HB_COMMAND_TRIG_MATCH (1UL<<2) + #define HB_COMMAND_TRIG_POS (0x7UL<<5) + #define HB_COMMAND_TRIG_POS_START (0UL<<5) + #define HB_COMMAND_TRIG_POS_25P (1UL<<5) + #define HB_COMMAND_TRIG_POS_50P (2UL<<5) + #define HB_COMMAND_TRIG_POS_75P (3UL<<5) + #define HB_COMMAND_TRIG_POS_END (4UL<<5) + #define HB_COMMAND_PC_MATCH (0x1ffffUL<<12) + + u32_t hb_status; + #define HB_STATUS_ARMED (1UL<<0) + #define HB_STATUS_TRIGGERED (1UL<<1) + #define HB_STATUS_ARM_CNT (0x3ffUL<<8) + #define HB_STATUS_CAP_ADDR (0x1ffUL<<20) + + u32_t hb_config; + #define HB_CONFIG_PROC_SEL (0xfUL<<0) + #define HB_CONFIG_PROC_SEL_TXP0 (0UL<<0) + #define HB_CONFIG_PROC_SEL_TXP1 (1UL<<0) + #define HB_CONFIG_PROC_SEL_TPAT0 (2UL<<0) + #define HB_CONFIG_PROC_SEL_TPAT1 (3UL<<0) + #define HB_CONFIG_PROC_SEL_RXP0 (4UL<<0) + #define HB_CONFIG_PROC_SEL_RXP1 (5UL<<0) + #define HB_CONFIG_PROC_SEL_COM0 (6UL<<0) + #define HB_CONFIG_PROC_SEL_COM1 (7UL<<0) + #define HB_CONFIG_PROC_SEL_CP0 (8UL<<0) + #define HB_CONFIG_PROC_SEL_CP1 (9UL<<0) + #define HB_CONFIG_PROC_SEL_MCP (10UL<<0) + + u32_t unused_0[1021]; + u32_t hb_hb_buf_data[1024]; +} hb_reg_t; + + +/* + * reg_space definition + */ +typedef struct reg_space +{ + pci_config_t pci_config; + pci_reg_t pci; + misc_reg_t misc; + dma_reg_t dma; + context_reg_t context; + emac_reg_t emac; + rx_parser_reg_t rpm; + rx_cu_parser_reg_t rpc; + rx_lookup_reg_t rlup; + cmd_scheduler_reg_t rv2pcs; + rx_v2p_reg_t rv2p; + rx_dma_reg_t rdma; + rx_bd_cache_reg_t rbdc; + u32_t unused_0[512]; + mailbox_queue_reg_t mq; + cmd_scheduler_reg_t csch; + timer_reg_t timer; + u32_t unused_1[256]; + tx_scheduler_reg_t tsch; + tx_bd_read_reg_t tbdr; + tx_bd_cache_reg_t tbdc; + u32_t unused_2[256]; + tx_dma_reg_t tdma; + dbu_reg_t dbu; + nvm_reg_t nvm; + host_coalesce_reg_t hc; + u32_t unused_3[256]; + debug_reg_t debug; + u32_t unused_4[57856]; + tx_processor_reg_t txp; + tx_patchup_reg_t tpat; + rx_processor_reg_t rxp; + completion_reg_t com; + management_reg_t mcp; + cmd_processor_reg_t cp; + tx_assembler_reg_t tas; + rx_mbuf_reg_t rbuf; + u32_t unused_5[196608]; + pcie_reg_t pci1; + host_coalesce_full_reg_t hc1; + hb_reg_t hb; +} reg_space_t; + + +/* + * txp_fio definition + * offset: 0x80000000 + */ +typedef struct txp_fio +{ + u32_t txpf_events_bits; + #define TXPF_EVENTS_BITS_GPIO0 (1UL<<15) + #define TXPF_EVENTS_BITS_GPIO1 (1UL<<16) + #define TXPF_EVENTS_BITS_GPIO2 (1UL<<17) + #define TXPF_EVENTS_BITS_GPIO3 (1UL<<18) + + u32_t txpf_attentions_bits; + #define TXPF_ATTENTIONS_BITS_EPB_ERROR (1UL<<30) + + u32_t txpf_event_enable; + u32_t txpf_attention_enable; + u32_t txpf_fio_status; + u32_t unused_0[3]; + + u32_t txpf_ctx_window_cid1; + + u32_t txpf_ctx_window_cid2; + + u32_t txpf_ctx_window_cid3; + #define TXPF_CTX_WINDOW_CID3_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) + + u32_t txpf_ctx_window_cid4; + #define TXPF_CTX_WINDOW_CID4_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) + u32_t unused_1[4]; + + u32_t txpf_txp_hc_inc_stat[8]; + u32_t unused_2[4]; + u32_t txpf_free_counter_value; + u32_t txpf_timer_retran_value; + u16_t txpf_timer_rxpush_value; + u16_t txpf_timer_delayack_value; + u16_t txpf_timer_keepalive_value; + u16_t txpf_timer_nagle_value; + u32_t txpf_bdcache_window_cid; + + u32_t txpf_bdcache_window_idx; + u16_t unused_3; + + u16_t txpf_tas_txp_thbuf_cons; + u32_t unused_4[29]; + + u32_t txpf_txpq_cid; + u32_t txpf_txpq_bseq; + u8_t txpf_txpq_flags_flags; + #define TXPF_TXPQ_FLAGS_FLAGS_QUICK_CID (0x3<<1) + #define TXPF_TXPQ_FLAGS_FLAGS_QUICK_CATCHUP (1<<3) + + u8_t txpf_txpq_cmd; + u8_t txpf_txpq_xnum; + u8_t txpf_txpq_protocol_flags; + u32_t unused_5[11]; + u32_t txpf_txpq_ftq_cmd; + u32_t unused_6; + + u32_t txpf_tdmaq_cid; + u16_t txpf_tdmaq_bidx; + u16_t txpf_tdmaq_boff; + u32_t txpf_tdmaq_bseq; + u32_t txpf_tdmaq_snd_next; + u8_t txpf_tdmaq_cmd; + u8_t txpf_tdmaq_xnum; + u8_t txpf_tdmaq_knum; + u8_t unused_7; + u32_t txpf_tdmaq_flags_flags; + #define TXPF_TDMAQ_FLAGS_FLAGS_QUICK_CID (0x3UL<<10) + + u16_t txpf_tdmaq_nbytes; + u16_t txpf_tdmaq_hole0_boff; + u16_t txpf_tdmaq_hole1_boff; + u16_t txpf_tdmaq_hole2_boff; + u32_t txpf_tdmaq_hole0_fill; + u32_t txpf_tdmaq_hole1_fill; + u32_t txpf_tdmaq_hole2_fill; + u32_t unused_8[3]; + u32_t txpf_tdmaq_ftq_cmd; + u32_t unused_9[417]; + + u32_t txpf_burst_base0; + + u32_t txpf_burst_base1; + + u32_t txpf_burst_base2; + + u32_t txpf_burst_base3; + + u32_t txpf_burst_cmd0; + + u32_t txpf_burst_cmd1; + + u32_t txpf_burst_cmd2; + + u32_t txpf_burst_cmd3; + u32_t unused_10[56]; + + u32_t txpf_burst_data0[16]; + u32_t txpf_burst_data1[16]; + u32_t txpf_burst_data2[16]; + u32_t txpf_burst_data3[16]; + u32_t unused_11[128]; + u32_t txpf_bd_cache_window[6]; + u32_t unused_12[122]; + u32_t txpf_bd_scan_cmd; + + u32_t txpf_bd_scan_len; + + u16_t txpf_bd_scan_flags; + u16_t txpf_bd_scan_vlan_tag; + u16_t txpf_bd_scan_reserved; + u16_t unused_13; + u16_t txpf_bd_scan_bidx_current; + u16_t txpf_bd_scan_boff_current; + u16_t txpf_bd_scan_bidx_prev; + u16_t txpf_bd_scan_boff_prev; + u32_t txpf_bd_scan_bseq_current; + u32_t txpf_bd_scan_bseq_prev; + u32_t unused_14[3192]; + u32_t txpf_thbuf[4096]; + u32_t unused_15[122880]; + u32_t txpf_ctx_window1[32768]; + u32_t txpf_ctx_window2[32768]; + u32_t txpf_ctx_window3[32768]; + u32_t txpf_ctx_window4[32768]; +} txp_fio_t; + + +/* + * txp_fio definition + * offset: 0x80000000 + */ +typedef struct txp_fio_xi +{ + u32_t txpf_events_bits; + #define TXPF_EVENTS_BITS_FTQ0_VALID (1UL<<0) + #define TXPF_EVENTS_BITS_FTQ1_VALID (1UL<<1) + #define TXPF_EVENTS_BITS_FTQ2_VALID (1UL<<2) + #define TXPF_EVENTS_BITS_SCANNER_DONE (1UL<<3) + #define TXPF_EVENTS_BITS_DMA_WR_DONE (1UL<<4) + #define TXPF_EVENTS_BITS_DMA_RD_DONE (1UL<<5) + #define TXPF_EVENTS_BITS_CRACKER_DONE (1UL<<6) + #define TXPF_EVENTS_BITS_MULTIPLY_DONE (1UL<<7) + #define TXPF_EVENTS_BITS_EXP_ROM (1UL<<8) + #define TXPF_EVENTS_BITS_VPD (1UL<<9) + #define TXPF_EVENTS_BITS_FLASH (1UL<<10) + #define TXPF_EVENTS_BITS_SMB0 (1UL<<11) + #define TXPF_EVENTS_BITS_RESERVED0 (1UL<<12) + #define TXPF_EVENTS_BITS_RESERVED1 (1UL<<13) + #define TXPF_EVENTS_BITS_RESERVED2 (1UL<<14) + #define TXPF_EVENTS_BITS_GPIO (1UL<<15) + #define TXPF_EVENTS_BITS_SW_TMR_1 (1UL<<19) + #define TXPF_EVENTS_BITS_SW_TMR_2 (1UL<<20) + #define TXPF_EVENTS_BITS_SW_TMR_3 (1UL<<21) + #define TXPF_EVENTS_BITS_SW_TMR_4 (1UL<<22) + #define TXPF_EVENTS_BITS_LINK_CHANGED (1UL<<23) + #define TXPF_EVENTS_BITS_MI_INT (1UL<<25) + #define TXPF_EVENTS_BITS_MI_COMPLETE (1UL<<26) + #define TXPF_EVENTS_BITS_MAIN_PWR_INT (1UL<<27) + #define TXPF_EVENTS_BITS_NOT_ENABLED (1UL<<30) + #define TXPF_EVENTS_BITS_ATTENTIONS_VALID (1UL<<31) + + u32_t txpf_attentions_bits; + #define TXPF_ATTENTIONS_BITS_LINK_STATE (1UL<<0) + #define TXPF_ATTENTIONS_BITS_TX_SCHEDULER_ABORT (1UL<<1) + #define TXPF_ATTENTIONS_BITS_TX_BD_READ_ABORT (1UL<<2) + #define TXPF_ATTENTIONS_BITS_TX_BD_CACHE_ABORT (1UL<<3) + #define TXPF_ATTENTIONS_BITS_TX_PROCESSOR_ABORT (1UL<<4) + #define TXPF_ATTENTIONS_BITS_TX_DMA_ABORT (1UL<<5) + #define TXPF_ATTENTIONS_BITS_TX_PATCHUP_ABORT (1UL<<6) + #define TXPF_ATTENTIONS_BITS_TX_ASSEMBLER_ABORT (1UL<<7) + #define TXPF_ATTENTIONS_BITS_RX_PARSER_MAC_ABORT (1UL<<8) + #define TXPF_ATTENTIONS_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) + #define TXPF_ATTENTIONS_BITS_RX_MBUF_ABORT (1UL<<10) + #define TXPF_ATTENTIONS_BITS_RX_LOOKUP_ABORT (1UL<<11) + #define TXPF_ATTENTIONS_BITS_RX_PROCESSOR_ABORT (1UL<<12) + #define TXPF_ATTENTIONS_BITS_RX_V2P_ABORT (1UL<<13) + #define TXPF_ATTENTIONS_BITS_RX_BD_CACHE_ABORT (1UL<<14) + #define TXPF_ATTENTIONS_BITS_RX_DMA_ABORT (1UL<<15) + #define TXPF_ATTENTIONS_BITS_COMPLETION_ABORT (1UL<<16) + #define TXPF_ATTENTIONS_BITS_HOST_COALESCE_ABORT (1UL<<17) + #define TXPF_ATTENTIONS_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) + #define TXPF_ATTENTIONS_BITS_CONTEXT_ABORT (1UL<<19) + #define TXPF_ATTENTIONS_BITS_CMD_SCHEDULER_ABORT (1UL<<20) + #define TXPF_ATTENTIONS_BITS_CMD_PROCESSOR_ABORT (1UL<<21) + #define TXPF_ATTENTIONS_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) + #define TXPF_ATTENTIONS_BITS_MAC_ABORT (1UL<<23) + #define TXPF_ATTENTIONS_BITS_TIMER_ABORT (1UL<<24) + #define TXPF_ATTENTIONS_BITS_DMAE_ABORT (1UL<<25) + #define TXPF_ATTENTIONS_BITS_FLSH_ABORT (1UL<<26) + #define TXPF_ATTENTIONS_BITS_GRC_ABORT (1UL<<27) + #define TXPF_ATTENTIONS_BITS_PARITY_ERROR (1UL<<31) + + u32_t txpf_event_enable; + u32_t txpf_attention_enable; + u32_t txpf_fio_status; + #define TXPF_FIO_STATUS_ENABLED (1UL<<0) + #define TXPF_FIO_STATUS_FORCE_ENA (1UL<<1) + + u32_t txpf_l2_compatibility; + #define TXPF_L2_COMPATIBILITY_CTX_OFFSET (0x1ffUL<<3) + #define TXPF_L2_COMPATIBILITY_COMP_ENABLE (1UL<<31) + u32_t unused_0[2]; + + u32_t txpf_ctx_window_cid1; + #define TXPF_CTX_WINDOW_CID1_LOCK_TYPE (0x7UL<<0) + #define TXPF_CTX_WINDOW_CID1_LOCK_TYPE_VOID (0UL<<0) + #define TXPF_CTX_WINDOW_CID1_LOCK_TYPE_PROTOCOL (1UL<<0) + #define TXPF_CTX_WINDOW_CID1_LOCK_TYPE_TX (2UL<<0) + #define TXPF_CTX_WINDOW_CID1_LOCK_TYPE_TIMER (4UL<<0) + #define TXPF_CTX_WINDOW_CID1_LOCK_TYPE_COMPLETE (7UL<<0) + #define TXPF_CTX_WINDOW_CID1_VALUE (0x3fffUL<<7) + #define TXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT (0x3UL<<24) + #define TXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_00 (0UL<<24) + #define TXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_01 (1UL<<24) + #define TXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_10 (2UL<<24) + #define TXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_11 (3UL<<24) + #define TXPF_CTX_WINDOW_CID1_LOCK_GRANTED (1UL<<26) + #define TXPF_CTX_WINDOW_CID1_LOCK_MODE (0x3UL<<27) + #define TXPF_CTX_WINDOW_CID1_LOCK_MODE_UNLOCK (0UL<<27) + #define TXPF_CTX_WINDOW_CID1_LOCK_MODE_IMMEDIATE (1UL<<27) + #define TXPF_CTX_WINDOW_CID1_LOCK_MODE_SURE (2UL<<27) + #define TXPF_CTX_WINDOW_CID1_NO_EXT_ACC (1UL<<29) + #define TXPF_CTX_WINDOW_CID1_LOCK_STATUS (1UL<<30) + #define TXPF_CTX_WINDOW_CID1_LOCK_REQ (1UL<<31) + + u32_t txpf_ctx_window_cid2; + #define TXPF_CTX_WINDOW_CID2_LOCK_TYPE (0x7UL<<0) + #define TXPF_CTX_WINDOW_CID2_LOCK_TYPE_VOID (0UL<<0) + #define TXPF_CTX_WINDOW_CID2_LOCK_TYPE_PROTOCOL (1UL<<0) + #define TXPF_CTX_WINDOW_CID2_LOCK_TYPE_TX (2UL<<0) + #define TXPF_CTX_WINDOW_CID2_LOCK_TYPE_TIMER (4UL<<0) + #define TXPF_CTX_WINDOW_CID2_LOCK_TYPE_COMPLETE (7UL<<0) + #define TXPF_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) + #define TXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT (0x3UL<<24) + #define TXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_00 (0UL<<24) + #define TXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_01 (1UL<<24) + #define TXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_10 (2UL<<24) + #define TXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_11 (3UL<<24) + #define TXPF_CTX_WINDOW_CID2_LOCK_GRANTED (1UL<<26) + #define TXPF_CTX_WINDOW_CID2_LOCK_MODE (0x3UL<<27) + #define TXPF_CTX_WINDOW_CID2_LOCK_MODE_UNLOCK (0UL<<27) + #define TXPF_CTX_WINDOW_CID2_LOCK_MODE_IMMEDIATE (1UL<<27) + #define TXPF_CTX_WINDOW_CID2_LOCK_MODE_SURE (2UL<<27) + #define TXPF_CTX_WINDOW_CID2_NO_EXT_ACC (1UL<<29) + #define TXPF_CTX_WINDOW_CID2_LOCK_STATUS (1UL<<30) + #define TXPF_CTX_WINDOW_CID2_LOCK_REQ (1UL<<31) + + u32_t txpf_ctx_window_cid3; + #define TXPF_CTX_WINDOW_CID3_LOCK_TYPE (0x7UL<<0) + #define TXPF_CTX_WINDOW_CID3_LOCK_TYPE_VOID (0UL<<0) + #define TXPF_CTX_WINDOW_CID3_LOCK_TYPE_PROTOCOL (1UL<<0) + #define TXPF_CTX_WINDOW_CID3_LOCK_TYPE_TX (2UL<<0) + #define TXPF_CTX_WINDOW_CID3_LOCK_TYPE_TIMER (4UL<<0) + #define TXPF_CTX_WINDOW_CID3_LOCK_TYPE_COMPLETE (7UL<<0) + #define TXPF_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) + #define TXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT (0x3UL<<24) + #define TXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_00 (0UL<<24) + #define TXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_01 (1UL<<24) + #define TXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_10 (2UL<<24) + #define TXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_11 (3UL<<24) + #define TXPF_CTX_WINDOW_CID3_LOCK_GRANTED (1UL<<26) + #define TXPF_CTX_WINDOW_CID3_LOCK_MODE (0x3UL<<27) + #define TXPF_CTX_WINDOW_CID3_LOCK_MODE_UNLOCK (0UL<<27) + #define TXPF_CTX_WINDOW_CID3_LOCK_MODE_IMMEDIATE (1UL<<27) + #define TXPF_CTX_WINDOW_CID3_LOCK_MODE_SURE (2UL<<27) + #define TXPF_CTX_WINDOW_CID3_NO_EXT_ACC (1UL<<29) + #define TXPF_CTX_WINDOW_CID3_LOCK_STATUS (1UL<<30) + #define TXPF_CTX_WINDOW_CID3_LOCK_REQ (1UL<<31) + + u32_t txpf_ctx_window_cid4; + #define TXPF_CTX_WINDOW_CID4_LOCK_TYPE (0x7UL<<0) + #define TXPF_CTX_WINDOW_CID4_LOCK_TYPE_VOID (0UL<<0) + #define TXPF_CTX_WINDOW_CID4_LOCK_TYPE_PROTOCOL (1UL<<0) + #define TXPF_CTX_WINDOW_CID4_LOCK_TYPE_TX (2UL<<0) + #define TXPF_CTX_WINDOW_CID4_LOCK_TYPE_TIMER (4UL<<0) + #define TXPF_CTX_WINDOW_CID4_LOCK_TYPE_COMPLETE (7UL<<0) + #define TXPF_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) + #define TXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT (0x3UL<<24) + #define TXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_00 (0UL<<24) + #define TXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_01 (1UL<<24) + #define TXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_10 (2UL<<24) + #define TXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_11 (3UL<<24) + #define TXPF_CTX_WINDOW_CID4_LOCK_GRANTED (1UL<<26) + #define TXPF_CTX_WINDOW_CID4_LOCK_MODE (0x3UL<<27) + #define TXPF_CTX_WINDOW_CID4_LOCK_MODE_UNLOCK (0UL<<27) + #define TXPF_CTX_WINDOW_CID4_LOCK_MODE_IMMEDIATE (1UL<<27) + #define TXPF_CTX_WINDOW_CID4_LOCK_MODE_SURE (2UL<<27) + #define TXPF_CTX_WINDOW_CID4_NO_EXT_ACC (1UL<<29) + #define TXPF_CTX_WINDOW_CID4_LOCK_STATUS (1UL<<30) + #define TXPF_CTX_WINDOW_CID4_LOCK_REQ (1UL<<31) + u32_t unused_1[4]; + + u32_t txpf_txp_hc_inc_stat[8]; + u32_t unused_2[4]; + u32_t txpf_free_counter_value; + u32_t txpf_timer_retran_value; + u16_t txpf_timer_rxpush_value; + u16_t txpf_timer_delayack_value; + u16_t txpf_timer_keepalive_value; + u16_t txpf_timer_nagle_value; + u32_t txpf_bdcache_window_cid; + #define TXPF_BDCACHE_WINDOW_CID_HIT (1UL<<0) + #define TXPF_BDCACHE_WINDOW_CID_RDY (1UL<<1) + #define TXPF_BDCACHE_WINDOW_CID_CID_VALUE (0x3fffUL<<7) + #define TXPF_BDCACHE_WINDOW_CID_CMD_VALUE (0xffUL<<24) + + u32_t txpf_bdcache_window_idx; + #define TXPF_BDCACHE_WINDOW_IDX_BDCACHE_WINDOW_IDX_VALUE (0xffffUL<<0) + u16_t unused_3; + + u16_t txpf_tas_txp_thbuf_cons; + #define TXPF_TAS_TXP_THBUF_CONS_VALUE (0xfff<<3) + u32_t unused_4; + + u32_t txpf_ctx_window_cid5; + #define TXPF_CTX_WINDOW_CID5_LOCK_TYPE (0x7UL<<0) + #define TXPF_CTX_WINDOW_CID5_LOCK_TYPE_VOID (0UL<<0) + #define TXPF_CTX_WINDOW_CID5_LOCK_TYPE_PROTOCOL (1UL<<0) + #define TXPF_CTX_WINDOW_CID5_LOCK_TYPE_TX (2UL<<0) + #define TXPF_CTX_WINDOW_CID5_LOCK_TYPE_TIMER (4UL<<0) + #define TXPF_CTX_WINDOW_CID5_LOCK_TYPE_COMPLETE (7UL<<0) + #define TXPF_CTX_WINDOW_CID5_VALUE (0x3fffUL<<7) + #define TXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT (0x3UL<<24) + #define TXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_00 (0UL<<24) + #define TXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_01 (1UL<<24) + #define TXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_10 (2UL<<24) + #define TXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_11 (3UL<<24) + #define TXPF_CTX_WINDOW_CID5_LOCK_GRANTED (1UL<<26) + #define TXPF_CTX_WINDOW_CID5_LOCK_MODE (0x3UL<<27) + #define TXPF_CTX_WINDOW_CID5_LOCK_MODE_UNLOCK (0UL<<27) + #define TXPF_CTX_WINDOW_CID5_LOCK_MODE_IMMEDIATE (1UL<<27) + #define TXPF_CTX_WINDOW_CID5_LOCK_MODE_SURE (2UL<<27) + #define TXPF_CTX_WINDOW_CID5_NO_EXT_ACC (1UL<<29) + #define TXPF_CTX_WINDOW_CID5_LOCK_STATUS (1UL<<30) + #define TXPF_CTX_WINDOW_CID5_LOCK_REQ (1UL<<31) + + u32_t txpf_ctx_window_cid6; + #define TXPF_CTX_WINDOW_CID6_LOCK_TYPE (0x7UL<<0) + #define TXPF_CTX_WINDOW_CID6_LOCK_TYPE_VOID (0UL<<0) + #define TXPF_CTX_WINDOW_CID6_LOCK_TYPE_PROTOCOL (1UL<<0) + #define TXPF_CTX_WINDOW_CID6_LOCK_TYPE_TX (2UL<<0) + #define TXPF_CTX_WINDOW_CID6_LOCK_TYPE_TIMER (4UL<<0) + #define TXPF_CTX_WINDOW_CID6_LOCK_TYPE_COMPLETE (7UL<<0) + #define TXPF_CTX_WINDOW_CID6_VALUE (0x3fffUL<<7) + #define TXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT (0x3UL<<24) + #define TXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_00 (0UL<<24) + #define TXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_01 (1UL<<24) + #define TXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_10 (2UL<<24) + #define TXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_11 (3UL<<24) + #define TXPF_CTX_WINDOW_CID6_LOCK_GRANTED (1UL<<26) + #define TXPF_CTX_WINDOW_CID6_LOCK_MODE (0x3UL<<27) + #define TXPF_CTX_WINDOW_CID6_LOCK_MODE_UNLOCK (0UL<<27) + #define TXPF_CTX_WINDOW_CID6_LOCK_MODE_IMMEDIATE (1UL<<27) + #define TXPF_CTX_WINDOW_CID6_LOCK_MODE_SURE (2UL<<27) + #define TXPF_CTX_WINDOW_CID6_NO_EXT_ACC (1UL<<29) + #define TXPF_CTX_WINDOW_CID6_LOCK_STATUS (1UL<<30) + #define TXPF_CTX_WINDOW_CID6_LOCK_REQ (1UL<<31) + u32_t unused_5[26]; + + u32_t txpf_txpq_cid; + u32_t txpf_txpq_bseq; + u8_t txpf_txpq_flags_flags; + #define TXPF_TXPQ_FLAGS_FLAGS_QUICK_CID_ENA (1<<0) + #define TXPF_TXPQ_FLAGS_FLAGS_RSVD (1<<1) + #define TXPF_TXPQ_FLAGS_FLAGS_BORROWED (1<<2) + #define TXPF_TXPQ_FLAGS_FLAGS_BSEQ_INVLD (1<<3) + #define TXPF_TXPQ_FLAGS_FLAGS_S_RETRAN (1<<4) + #define TXPF_TXPQ_FLAGS_FLAGS_WORKAROUND (0x3<<5) + + u8_t txpf_txpq_cmd; + u8_t txpf_txpq_xnum; + u8_t txpf_txpq_protocol_flags; + u32_t txpf_txpq_tcp_rcv_nxt; + #define TXPF_TXPQ_TCP_RCV_NXT_VALUE (0xffffffffUL<<0) + + u8_t txpf_tcmd_fnum; + #define TXPF_TCMD_FNUM_VALUE (0x3f<<0) + u8_t unused_6; + u16_t unused_7; + u32_t unused_8[9]; + + u32_t txpf_txpq_ftq_cmd; + #define TXPF_TXPQ_FTQ_CMD_TXPQ_FTQ_CMD_POP (1UL<<30) + u32_t unused_9; + + u32_t txpf_tdmaq_cid; + u16_t txpf_tdmaq_bidx; + u16_t txpf_tdmaq_boff; + u32_t txpf_tdmaq_bseq; + u32_t txpf_tdmaq_snd_next; + u8_t txpf_tdmaq_cmd; + u8_t txpf_tdmaq_xnum; + u8_t txpf_tdmaq_knum; + u8_t unused_10; + u32_t txpf_tdmaq_flags_flags; + #define TXPF_TDMAQ_FLAGS_FLAGS_PLUS_TWO (1UL<<0) + #define TXPF_TDMAQ_FLAGS_FLAGS_TCP_UDP_CKSUM (1UL<<1) + #define TXPF_TDMAQ_FLAGS_FLAGS_IP_CKSUM (1UL<<2) + #define TXPF_TDMAQ_FLAGS_FLAGS_INCR_CMD (1UL<<3) + #define TXPF_TDMAQ_FLAGS_FLAGS_COAL_NOW (1UL<<4) + #define TXPF_TDMAQ_FLAGS_FLAGS_DONT_GEN_CRC (1UL<<5) + #define TXPF_TDMAQ_FLAGS_FLAGS_LAST_PKT (1UL<<6) + #define TXPF_TDMAQ_FLAGS_FLAGS_PKT_FRAG (1UL<<7) + #define TXPF_TDMAQ_FLAGS_FLAGS_QUICK_CID_ENA (1UL<<9) + #define TXPF_TDMAQ_FLAGS_FLAGS_RSVD_FUTURE (0x3UL<<10) + #define TXPF_TDMAQ_FLAGS_FLAGS_L5_PAGE_MODE (1UL<<12) + #define TXPF_TDMAQ_FLAGS_FLAGS_COMPLETE (1UL<<13) + #define TXPF_TDMAQ_FLAGS_FLAGS_RETRAN (1UL<<14) + #define TXPF_TDMAQ_FLAGS_FLAGS_END_PADDING (0xfUL<<16) + #define TXPF_TDMAQ_FLAGS_FLAGS_USAGE_CNT (1UL<<20) + #define TXPF_TDMAQ_FLAGS_FLAGS_USAGE_CNT_AUTODECREMENT (0UL<<20) + #define TXPF_TDMAQ_FLAGS_FLAGS_USAGE_CNT_DONOTDECREMENT (1UL<<20) + #define TXPF_TDMAQ_FLAGS_FLAGS_BSEQ_INVLD (1UL<<21) + #define TXPF_TDMAQ_FLAGS_FLAGS_WORK_AROUND (0x3UL<<22) + #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE_SZ (0x3UL<<25) + #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE_SZ_4 (0UL<<25) + #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE_SZ_8 (1UL<<25) + #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE_SZ_12 (2UL<<25) + #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE_SZ_16 (3UL<<25) + #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE0 (1UL<<28) + #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE1 (1UL<<29) + #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE2 (1UL<<30) + + u16_t txpf_tdmaq_nbytes; + u16_t txpf_tdmaq_hole0_boff; + u16_t txpf_tdmaq_hole1_boff; + u16_t txpf_tdmaq_hole2_boff; + u32_t txpf_tdmaq_hole0_fill; + u32_t txpf_tdmaq_hole1_fill; + u32_t txpf_tdmaq_hole2_fill; + u8_t txpf_tdmaq_tcmd_fnum; + #define TXPF_TDMAQ_TCMD_FNUM_VALUE (0x3f<<0) + + u8_t txpf_tdmaq_txp_act_cmd; + u16_t unused_11; + u32_t unused_12[2]; + u32_t txpf_tdmaq_ftq_cmd; + #define TXPF_TDMAQ_FTQ_CMD_CPY_DATA (1UL<<11) + #define TXPF_TDMAQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define TXPF_TDMAQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define TXPF_TDMAQ_FTQ_CMD_BUSY (1UL<<31) + u32_t unused_13[417]; + + u32_t txpf_burst_base0; + #define TXPF_BURST_BASE0_BASE_VAL0 (0x3fffUL<<7) + + u32_t txpf_burst_base1; + #define TXPF_BURST_BASE1_BASE_VAL1 (0x3fffUL<<7) + + u32_t txpf_burst_base2; + #define TXPF_BURST_BASE2_BASE_VAL2 (0x3fffUL<<7) + + u32_t txpf_burst_base3; + #define TXPF_BURST_BASE3_BASE_VAL3 (0x3fffUL<<7) + + u32_t txpf_burst_cmd0; + #define TXPF_BURST_CMD0_FTQ_SEL (0x3UL<<0) + #define TXPF_BURST_CMD0_FTQ_SEL_0 (0UL<<0) + #define TXPF_BURST_CMD0_FTQ_SEL_1 (1UL<<0) + #define TXPF_BURST_CMD0_FTQ_SEL_2 (2UL<<0) + #define TXPF_BURST_CMD0_FTQ_SEL_3 (3UL<<0) + #define TXPF_BURST_CMD0_BUSY (1UL<<2) + #define TXPF_BURST_CMD0_OFFSET (0x1ffUL<<3) + #define TXPF_BURST_CMD0_BASE_REG_SEL (1UL<<23) + #define TXPF_BURST_CMD0_MOD_USAGE_CNT (0x3UL<<24) + #define TXPF_BURST_CMD0_MOD_USAGE_CNT_00 (0UL<<24) + #define TXPF_BURST_CMD0_MOD_USAGE_CNT_01 (1UL<<24) + #define TXPF_BURST_CMD0_MOD_USAGE_CNT_10 (2UL<<24) + #define TXPF_BURST_CMD0_MOD_USAGE_CNT_11 (3UL<<24) + #define TXPF_BURST_CMD0_PREFETCH_SIZE (0x3UL<<26) + #define TXPF_BURST_CMD0_NO_RAM_ACCESS (1UL<<28) + #define TXPF_BURST_CMD0_NO_CACHE (1UL<<29) + #define TXPF_BURST_CMD0_CROSS_BOUNDARY (1UL<<30) + + u32_t txpf_burst_cmd1; + #define TXPF_BURST_CMD1_FTQ_SEL (0x3UL<<0) + #define TXPF_BURST_CMD1_FTQ_SEL_0 (0UL<<0) + #define TXPF_BURST_CMD1_FTQ_SEL_1 (1UL<<0) + #define TXPF_BURST_CMD1_FTQ_SEL_2 (2UL<<0) + #define TXPF_BURST_CMD1_FTQ_SEL_3 (3UL<<0) + #define TXPF_BURST_CMD1_BUSY (1UL<<2) + #define TXPF_BURST_CMD1_OFFSET (0x1ffUL<<3) + #define TXPF_BURST_CMD1_BASE_REG_SEL (1UL<<23) + #define TXPF_BURST_CMD1_MOD_USAGE_CNT (0x3UL<<24) + #define TXPF_BURST_CMD1_MOD_USAGE_CNT_00 (0UL<<24) + #define TXPF_BURST_CMD1_MOD_USAGE_CNT_01 (1UL<<24) + #define TXPF_BURST_CMD1_MOD_USAGE_CNT_10 (2UL<<24) + #define TXPF_BURST_CMD1_MOD_USAGE_CNT_11 (3UL<<24) + #define TXPF_BURST_CMD1_PREFETCH_SIZE (0x3UL<<26) + #define TXPF_BURST_CMD1_NO_RAM_ACCESS (1UL<<28) + #define TXPF_BURST_CMD1_NO_CACHE (1UL<<29) + #define TXPF_BURST_CMD1_CROSS_BOUNDARY (1UL<<30) + + u32_t txpf_burst_cmd2; + #define TXPF_BURST_CMD2_FTQ_SEL (0x3UL<<0) + #define TXPF_BURST_CMD2_FTQ_SEL_0 (0UL<<0) + #define TXPF_BURST_CMD2_FTQ_SEL_1 (1UL<<0) + #define TXPF_BURST_CMD2_FTQ_SEL_2 (2UL<<0) + #define TXPF_BURST_CMD2_FTQ_SEL_3 (3UL<<0) + #define TXPF_BURST_CMD2_BUSY (1UL<<2) + #define TXPF_BURST_CMD2_OFFSET (0x1ffUL<<3) + #define TXPF_BURST_CMD2_BASE_REG_SEL (1UL<<23) + #define TXPF_BURST_CMD2_MOD_USAGE_CNT (0x3UL<<24) + #define TXPF_BURST_CMD2_MOD_USAGE_CNT_00 (0UL<<24) + #define TXPF_BURST_CMD2_MOD_USAGE_CNT_01 (1UL<<24) + #define TXPF_BURST_CMD2_MOD_USAGE_CNT_10 (2UL<<24) + #define TXPF_BURST_CMD2_MOD_USAGE_CNT_11 (3UL<<24) + #define TXPF_BURST_CMD2_PREFETCH_SIZE (0x3UL<<26) + #define TXPF_BURST_CMD2_NO_RAM_ACCESS (1UL<<28) + #define TXPF_BURST_CMD2_NO_CACHE (1UL<<29) + #define TXPF_BURST_CMD2_CROSS_BOUNDARY (1UL<<30) + + u32_t txpf_burst_cmd3; + #define TXPF_BURST_CMD3_FTQ_SEL (0x3UL<<0) + #define TXPF_BURST_CMD3_FTQ_SEL_0 (0UL<<0) + #define TXPF_BURST_CMD3_FTQ_SEL_1 (1UL<<0) + #define TXPF_BURST_CMD3_FTQ_SEL_2 (2UL<<0) + #define TXPF_BURST_CMD3_FTQ_SEL_3 (3UL<<0) + #define TXPF_BURST_CMD3_BUSY (1UL<<2) + #define TXPF_BURST_CMD3_OFFSET (0x1ffUL<<3) + #define TXPF_BURST_CMD3_BASE_REG_SEL (1UL<<23) + #define TXPF_BURST_CMD3_MOD_USAGE_CNT (0x3UL<<24) + #define TXPF_BURST_CMD3_MOD_USAGE_CNT_00 (0UL<<24) + #define TXPF_BURST_CMD3_MOD_USAGE_CNT_01 (1UL<<24) + #define TXPF_BURST_CMD3_MOD_USAGE_CNT_10 (2UL<<24) + #define TXPF_BURST_CMD3_MOD_USAGE_CNT_11 (3UL<<24) + #define TXPF_BURST_CMD3_PREFETCH_SIZE (0x3UL<<26) + #define TXPF_BURST_CMD3_NO_RAM_ACCESS (1UL<<28) + #define TXPF_BURST_CMD3_NO_CACHE (1UL<<29) + #define TXPF_BURST_CMD3_CROSS_BOUNDARY (1UL<<30) + + u32_t txpf_burst_cmd4; + #define TXPF_BURST_CMD4_FTQ_SEL (0x3UL<<0) + #define TXPF_BURST_CMD4_FTQ_SEL_0 (0UL<<0) + #define TXPF_BURST_CMD4_FTQ_SEL_1 (1UL<<0) + #define TXPF_BURST_CMD4_FTQ_SEL_2 (2UL<<0) + #define TXPF_BURST_CMD4_FTQ_SEL_3 (3UL<<0) + #define TXPF_BURST_CMD4_BUSY (1UL<<2) + #define TXPF_BURST_CMD4_OFFSET (0x1ffUL<<3) + #define TXPF_BURST_CMD4_BASE_REG_SEL (1UL<<23) + #define TXPF_BURST_CMD4_MOD_USAGE_CNT (0x3UL<<24) + #define TXPF_BURST_CMD4_MOD_USAGE_CNT_00 (0UL<<24) + #define TXPF_BURST_CMD4_MOD_USAGE_CNT_01 (1UL<<24) + #define TXPF_BURST_CMD4_MOD_USAGE_CNT_10 (2UL<<24) + #define TXPF_BURST_CMD4_MOD_USAGE_CNT_11 (3UL<<24) + #define TXPF_BURST_CMD4_PREFETCH_SIZE (0x3UL<<26) + #define TXPF_BURST_CMD4_NO_RAM_ACCESS (1UL<<28) + #define TXPF_BURST_CMD4_NO_CACHE (1UL<<29) + #define TXPF_BURST_CMD4_CROSS_BOUNDARY (1UL<<30) + + u32_t txpf_burst_cmd5; + #define TXPF_BURST_CMD5_FTQ_SEL (0x3UL<<0) + #define TXPF_BURST_CMD5_FTQ_SEL_0 (0UL<<0) + #define TXPF_BURST_CMD5_FTQ_SEL_1 (1UL<<0) + #define TXPF_BURST_CMD5_FTQ_SEL_2 (2UL<<0) + #define TXPF_BURST_CMD5_FTQ_SEL_3 (3UL<<0) + #define TXPF_BURST_CMD5_BUSY (1UL<<2) + #define TXPF_BURST_CMD5_OFFSET (0x1ffUL<<3) + #define TXPF_BURST_CMD5_BASE_REG_SEL (1UL<<23) + #define TXPF_BURST_CMD5_MOD_USAGE_CNT (0x3UL<<24) + #define TXPF_BURST_CMD5_MOD_USAGE_CNT_00 (0UL<<24) + #define TXPF_BURST_CMD5_MOD_USAGE_CNT_01 (1UL<<24) + #define TXPF_BURST_CMD5_MOD_USAGE_CNT_10 (2UL<<24) + #define TXPF_BURST_CMD5_MOD_USAGE_CNT_11 (3UL<<24) + #define TXPF_BURST_CMD5_PREFETCH_SIZE (0x3UL<<26) + #define TXPF_BURST_CMD5_NO_RAM_ACCESS (1UL<<28) + #define TXPF_BURST_CMD5_NO_CACHE (1UL<<29) + #define TXPF_BURST_CMD5_CROSS_BOUNDARY (1UL<<30) + + u32_t txpf_burst_cmd6; + #define TXPF_BURST_CMD6_FTQ_SEL (0x3UL<<0) + #define TXPF_BURST_CMD6_FTQ_SEL_0 (0UL<<0) + #define TXPF_BURST_CMD6_FTQ_SEL_1 (1UL<<0) + #define TXPF_BURST_CMD6_FTQ_SEL_2 (2UL<<0) + #define TXPF_BURST_CMD6_FTQ_SEL_3 (3UL<<0) + #define TXPF_BURST_CMD6_BUSY (1UL<<2) + #define TXPF_BURST_CMD6_OFFSET (0x1ffUL<<3) + #define TXPF_BURST_CMD6_BASE_REG_SEL (1UL<<23) + #define TXPF_BURST_CMD6_MOD_USAGE_CNT (0x3UL<<24) + #define TXPF_BURST_CMD6_MOD_USAGE_CNT_00 (0UL<<24) + #define TXPF_BURST_CMD6_MOD_USAGE_CNT_01 (1UL<<24) + #define TXPF_BURST_CMD6_MOD_USAGE_CNT_10 (2UL<<24) + #define TXPF_BURST_CMD6_MOD_USAGE_CNT_11 (3UL<<24) + #define TXPF_BURST_CMD6_PREFETCH_SIZE (0x3UL<<26) + #define TXPF_BURST_CMD6_NO_RAM_ACCESS (1UL<<28) + #define TXPF_BURST_CMD6_NO_CACHE (1UL<<29) + #define TXPF_BURST_CMD6_CROSS_BOUNDARY (1UL<<30) + + u32_t txpf_burst_cmd7; + #define TXPF_BURST_CMD7_FTQ_SEL (0x3UL<<0) + #define TXPF_BURST_CMD7_FTQ_SEL_0 (0UL<<0) + #define TXPF_BURST_CMD7_FTQ_SEL_1 (1UL<<0) + #define TXPF_BURST_CMD7_FTQ_SEL_2 (2UL<<0) + #define TXPF_BURST_CMD7_FTQ_SEL_3 (3UL<<0) + #define TXPF_BURST_CMD7_BUSY (1UL<<2) + #define TXPF_BURST_CMD7_OFFSET (0x1ffUL<<3) + #define TXPF_BURST_CMD7_BASE_REG_SEL (1UL<<23) + #define TXPF_BURST_CMD7_MOD_USAGE_CNT (0x3UL<<24) + #define TXPF_BURST_CMD7_MOD_USAGE_CNT_00 (0UL<<24) + #define TXPF_BURST_CMD7_MOD_USAGE_CNT_01 (1UL<<24) + #define TXPF_BURST_CMD7_MOD_USAGE_CNT_10 (2UL<<24) + #define TXPF_BURST_CMD7_MOD_USAGE_CNT_11 (3UL<<24) + #define TXPF_BURST_CMD7_PREFETCH_SIZE (0x3UL<<26) + #define TXPF_BURST_CMD7_NO_RAM_ACCESS (1UL<<28) + #define TXPF_BURST_CMD7_NO_CACHE (1UL<<29) + #define TXPF_BURST_CMD7_CROSS_BOUNDARY (1UL<<30) + + u32_t txpf_ctx_cmd; + #define TXPF_CTX_CMD_NUM_BLOCKS (0x3UL<<0) + #define TXPF_CTX_CMD_OFFSET (0x1ffUL<<3) + #define TXPF_CTX_CMD_CID_VALUE (0x3fffUL<<12) + #define TXPF_CTX_CMD_PREFETCH_SIZE (0x3UL<<26) + #define TXPF_CTX_CMD_MOD_USAGE_CNT (0x3UL<<28) + #define TXPF_CTX_CMD_MOD_USAGE_CNT_00 (0UL<<28) + #define TXPF_CTX_CMD_MOD_USAGE_CNT_01 (1UL<<28) + #define TXPF_CTX_CMD_MOD_USAGE_CNT_10 (2UL<<28) + #define TXPF_CTX_CMD_MOD_USAGE_CNT_11 (3UL<<28) + u32_t unused_14[51]; + + u32_t txpf_burst_data0[16]; + u32_t txpf_burst_data1[16]; + u32_t txpf_burst_data2[16]; + u32_t txpf_burst_data3[16]; + u32_t txpf_burst_data4[16]; + u32_t txpf_burst_data5[16]; + u32_t txpf_burst_data6[16]; + u32_t txpf_burst_data7[16]; + u32_t unused_15[64]; + u32_t txpf_bd_cache_window[6]; + u32_t unused_16[122]; + u32_t txpf_bd_scan_cmd; + #define TXPF_BD_SCAN_CMD_CMD (0xffffffUL<<0) + #define TXPF_BD_SCAN_CMD_CMD_SCAN (0UL<<0) + #define TXPF_BD_SCAN_CMD_CMD_RELOAD (16777213UL<<0) + #define TXPF_BD_SCAN_CMD_PAGE_SIZE (0xfUL<<24) + #define TXPF_BD_SCAN_CMD_CLR_OVERRUN (1UL<<29) + #define TXPF_BD_SCAN_CMD_ACCUM (1UL<<30) + #define TXPF_BD_SCAN_CMD_NO_STOP (1UL<<31) + + u32_t txpf_bd_scan_len; + #define TXPF_BD_SCAN_LEN_BD_SCAN_LEN_OVERRUN (1UL<<31) + + u16_t txpf_bd_scan_flags; + u16_t txpf_bd_scan_vlan_tag; + u16_t txpf_bd_scan_reserved; + u16_t unused_17; + u16_t txpf_bd_scan_bidx_current; + u16_t txpf_bd_scan_boff_current; + u16_t txpf_bd_scan_bidx_prev; + u16_t txpf_bd_scan_boff_prev; + u32_t txpf_bd_scan_bseq_current; + u32_t txpf_bd_scan_bseq_prev; + u32_t unused_18[3192]; + u32_t txpf_thbuf[4096]; + u32_t unused_19[57344]; + u32_t txpf_ctx_window5[32768]; + u32_t txpf_ctx_window6[32768]; + u32_t txpf_ctx_window1[32768]; + u32_t txpf_ctx_window2[32768]; + u32_t txpf_ctx_window3[32768]; + u32_t txpf_ctx_window4[32768]; +} txp_fio_xi_t; + + +/* + * tpat_fio definition + * offset: 0x80000000 + */ +typedef struct tpat_fio +{ + u32_t tpatf_events_bits; + #define TPATF_EVENTS_BITS_GPIO0 (1UL<<15) + #define TPATF_EVENTS_BITS_GPIO1 (1UL<<16) + #define TPATF_EVENTS_BITS_GPIO2 (1UL<<17) + #define TPATF_EVENTS_BITS_GPIO3 (1UL<<18) + + u32_t tpatf_attentions_bits; + #define TPATF_ATTENTIONS_BITS_EPB_ERROR (1UL<<30) + + u32_t tpatf_event_enable; + u32_t tpatf_attention_enable; + u32_t tpatf_fio_status; + u32_t unused_0[3]; + + u32_t tpatf_ctx_window_cid1; + #define TPATF_CTX_WINDOW_CID1_1_LOCK_TYPE (0x7UL<<0) + #define TPATF_CTX_WINDOW_CID1_1_LOCK_TYPE_VOID (0UL<<0) + #define TPATF_CTX_WINDOW_CID1_1_LOCK_TYPE_PROTOCOL (1UL<<0) + #define TPATF_CTX_WINDOW_CID1_1_LOCK_TYPE_TX (2UL<<0) + #define TPATF_CTX_WINDOW_CID1_1_LOCK_TYPE_TIMER (4UL<<0) + #define TPATF_CTX_WINDOW_CID1_1_LOCK_TYPE_COMPLETE (7UL<<0) + #define TPATF_CTX_WINDOW_CID1_1_VALUE (0x3fffUL<<7) + #define TPATF_CTX_WINDOW_CID1_1_LOCK_GRANTED (1UL<<26) + #define TPATF_CTX_WINDOW_CID1_1_LOCK_MODE (0x3UL<<27) + #define TPATF_CTX_WINDOW_CID1_1_LOCK_MODE_UNLOCK (0UL<<27) + #define TPATF_CTX_WINDOW_CID1_1_LOCK_MODE_IMMEDIATE (1UL<<27) + #define TPATF_CTX_WINDOW_CID1_1_LOCK_MODE_SURE (2UL<<27) + #define TPATF_CTX_WINDOW_CID1_1_LOCK_STATUS (1UL<<30) + #define TPATF_CTX_WINDOW_CID1_0_LOCK_REQ (1UL<<31) + + u32_t tpatf_ctx_window_cid2; + #define TPATF_CTX_WINDOW_CID2_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) + + u32_t tpatf_ctx_window_cid3; + #define TPATF_CTX_WINDOW_CID3_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) + + u32_t tpatf_ctx_window_cid4; + #define TPATF_CTX_WINDOW_CID4_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) + u32_t unused_1[4]; + + u32_t tpatf_tpat_hc_inc_stat[4]; + u32_t unused_2[8]; + u32_t tpatf_free_counter_value; + u32_t unused_3[3]; + u32_t tpatf_tpat_pq_cons; + + u32_t tpatf_tpat_hq_cons; + u32_t unused_4[30]; + + u32_t tpatf_tpatq_cid; + u16_t tpatf_tpatq_nbytes; + u8_t tpatf_tpatq_xnum; + u8_t tpatf_tpatq_knum; + u32_t tpatf_tpatq_flags_flags; + #define TPATF_TPATQ_FLAGS_FLAGS_QUICK_CID (0x3UL<<10) + + u16_t tpatf_tpatq_raw_chksum; + u16_t unused_5; + u32_t unused_6[10]; + u32_t tpatf_tpatq_ftq_cmd; + u32_t unused_7; + + u16_t tpatf_tasq_hdr_skip; + u16_t tpatf_tasq_hdr_post_skip; + u16_t tpatf_tasq_hdr_size; + u16_t tpatf_tasq_payload_skip; + u16_t tpatf_tasq_payload_size; + u16_t tpatf_tasq_flags; + #define TPATF_TASQ_FLAGS_PKT_END (1<<0) + #define TPATF_TASQ_FLAGS_SA_REPLACE (1<<4) + #define TPATF_TASQ_FLAGS_SA_SELECT (0x3<<5) + #define TPATF_TASQ_FLAGS_MGMT_PKT_TAG_TE (0xf<<8) + u32_t unused_8[11]; + + u32_t tpatf_tasq_ftq_cmd; + u32_t unused_9[929]; + + u32_t tpatf_tpat_crack_cmd; + + u16_t tpatf_tpat_crack_ip_offset; + u16_t tpatf_tpat_crack_ip_len; + u16_t tpatf_tpat_crack_tcp_offset; + u16_t tpatf_tpat_crack_tcp_len; + u16_t tpatf_tpat_crack_l5_offset; + u16_t tpatf_tpat_crack_l5_len; + u16_t tpatf_tpat_crack_ip_chksum; + u16_t tpatf_tpat_crack_ip_pseudo_chksum; + u16_t tpatf_tpat_crack_tcp_chksum; + u16_t tpatf_tpat_crack_crc32_1_start; + u32_t tpatf_tpat_crack_crc32_1_seed; + u32_t tpatf_tpat_crack_crc32_1_result; + u32_t tpatf_tpat_crack_crc32_2_result; + u32_t unused_10[3063]; + u32_t tpatf_tx_header_queue[4096]; + u32_t tpatf_tx_payload_queue[16384]; + u32_t unused_11[106496]; + u32_t tpatf_ctx_window1[32768]; + u32_t tpatf_ctx_window2[32768]; + u32_t tpatf_ctx_window3[32768]; + u32_t tpatf_ctx_window4[32768]; +} tpat_fio_t; + + +/* + * tpat_fio definition + * offset: 0x80000000 + */ +typedef struct tpat_fio_xi +{ + u32_t tpatf_events_bits; + #define TPATF_EVENTS_BITS_FTQ0_VALID (1UL<<0) + #define TPATF_EVENTS_BITS_FTQ1_VALID (1UL<<1) + #define TPATF_EVENTS_BITS_FTQ2_VALID (1UL<<2) + #define TPATF_EVENTS_BITS_SCANNER_DONE (1UL<<3) + #define TPATF_EVENTS_BITS_DMA_WR_DONE (1UL<<4) + #define TPATF_EVENTS_BITS_DMA_RD_DONE (1UL<<5) + #define TPATF_EVENTS_BITS_CRACKER_DONE (1UL<<6) + #define TPATF_EVENTS_BITS_MULTIPLY_DONE (1UL<<7) + #define TPATF_EVENTS_BITS_EXP_ROM (1UL<<8) + #define TPATF_EVENTS_BITS_VPD (1UL<<9) + #define TPATF_EVENTS_BITS_FLASH (1UL<<10) + #define TPATF_EVENTS_BITS_SMB0 (1UL<<11) + #define TPATF_EVENTS_BITS_RESERVED0 (1UL<<12) + #define TPATF_EVENTS_BITS_RESERVED1 (1UL<<13) + #define TPATF_EVENTS_BITS_RESERVED2 (1UL<<14) + #define TPATF_EVENTS_BITS_GPIO (1UL<<15) + #define TPATF_EVENTS_BITS_SW_TMR_1 (1UL<<19) + #define TPATF_EVENTS_BITS_SW_TMR_2 (1UL<<20) + #define TPATF_EVENTS_BITS_SW_TMR_3 (1UL<<21) + #define TPATF_EVENTS_BITS_SW_TMR_4 (1UL<<22) + #define TPATF_EVENTS_BITS_LINK_CHANGED (1UL<<23) + #define TPATF_EVENTS_BITS_MI_INT (1UL<<25) + #define TPATF_EVENTS_BITS_MI_COMPLETE (1UL<<26) + #define TPATF_EVENTS_BITS_MAIN_PWR_INT (1UL<<27) + #define TPATF_EVENTS_BITS_NOT_ENABLED (1UL<<30) + #define TPATF_EVENTS_BITS_ATTENTIONS_VALID (1UL<<31) + + u32_t tpatf_attentions_bits; + #define TPATF_ATTENTIONS_BITS_LINK_STATE (1UL<<0) + #define TPATF_ATTENTIONS_BITS_TX_SCHEDULER_ABORT (1UL<<1) + #define TPATF_ATTENTIONS_BITS_TX_BD_READ_ABORT (1UL<<2) + #define TPATF_ATTENTIONS_BITS_TX_BD_CACHE_ABORT (1UL<<3) + #define TPATF_ATTENTIONS_BITS_TX_PROCESSOR_ABORT (1UL<<4) + #define TPATF_ATTENTIONS_BITS_TX_DMA_ABORT (1UL<<5) + #define TPATF_ATTENTIONS_BITS_TX_PATCHUP_ABORT (1UL<<6) + #define TPATF_ATTENTIONS_BITS_TX_ASSEMBLER_ABORT (1UL<<7) + #define TPATF_ATTENTIONS_BITS_RX_PARSER_MAC_ABORT (1UL<<8) + #define TPATF_ATTENTIONS_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) + #define TPATF_ATTENTIONS_BITS_RX_MBUF_ABORT (1UL<<10) + #define TPATF_ATTENTIONS_BITS_RX_LOOKUP_ABORT (1UL<<11) + #define TPATF_ATTENTIONS_BITS_RX_PROCESSOR_ABORT (1UL<<12) + #define TPATF_ATTENTIONS_BITS_RX_V2P_ABORT (1UL<<13) + #define TPATF_ATTENTIONS_BITS_RX_BD_CACHE_ABORT (1UL<<14) + #define TPATF_ATTENTIONS_BITS_RX_DMA_ABORT (1UL<<15) + #define TPATF_ATTENTIONS_BITS_COMPLETION_ABORT (1UL<<16) + #define TPATF_ATTENTIONS_BITS_HOST_COALESCE_ABORT (1UL<<17) + #define TPATF_ATTENTIONS_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) + #define TPATF_ATTENTIONS_BITS_CONTEXT_ABORT (1UL<<19) + #define TPATF_ATTENTIONS_BITS_CMD_SCHEDULER_ABORT (1UL<<20) + #define TPATF_ATTENTIONS_BITS_CMD_PROCESSOR_ABORT (1UL<<21) + #define TPATF_ATTENTIONS_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) + #define TPATF_ATTENTIONS_BITS_MAC_ABORT (1UL<<23) + #define TPATF_ATTENTIONS_BITS_TIMER_ABORT (1UL<<24) + #define TPATF_ATTENTIONS_BITS_DMAE_ABORT (1UL<<25) + #define TPATF_ATTENTIONS_BITS_FLSH_ABORT (1UL<<26) + #define TPATF_ATTENTIONS_BITS_GRC_ABORT (1UL<<27) + #define TPATF_ATTENTIONS_BITS_PARITY_ERROR (1UL<<31) + + u32_t tpatf_event_enable; + u32_t tpatf_attention_enable; + u32_t tpatf_fio_status; + #define TPATF_FIO_STATUS_ENABLED (1UL<<0) + #define TPATF_FIO_STATUS_FORCE_ENA (1UL<<1) + u32_t unused_0[3]; + + u32_t tpatf_ctx_window_cid1; + #define TPATF_CTX_WINDOW_CID1_LOCK_TYPE (0x7UL<<0) + #define TPATF_CTX_WINDOW_CID1_LOCK_TYPE_VOID (0UL<<0) + #define TPATF_CTX_WINDOW_CID1_LOCK_TYPE_PROTOCOL (1UL<<0) + #define TPATF_CTX_WINDOW_CID1_LOCK_TYPE_TX (2UL<<0) + #define TPATF_CTX_WINDOW_CID1_LOCK_TYPE_TIMER (4UL<<0) + #define TPATF_CTX_WINDOW_CID1_LOCK_TYPE_COMPLETE (7UL<<0) + #define TPATF_CTX_WINDOW_CID1_VALUE (0x3fffUL<<7) + #define TPATF_CTX_WINDOW_CID1_MOD_USAGE_CNT (0x3UL<<24) + #define TPATF_CTX_WINDOW_CID1_MOD_USAGE_CNT_00 (0UL<<24) + #define TPATF_CTX_WINDOW_CID1_MOD_USAGE_CNT_01 (1UL<<24) + #define TPATF_CTX_WINDOW_CID1_MOD_USAGE_CNT_10 (2UL<<24) + #define TPATF_CTX_WINDOW_CID1_MOD_USAGE_CNT_11 (3UL<<24) + #define TPATF_CTX_WINDOW_CID1_LOCK_GRANTED (1UL<<26) + #define TPATF_CTX_WINDOW_CID1_LOCK_MODE (0x3UL<<27) + #define TPATF_CTX_WINDOW_CID1_LOCK_MODE_UNLOCK (0UL<<27) + #define TPATF_CTX_WINDOW_CID1_LOCK_MODE_IMMEDIATE (1UL<<27) + #define TPATF_CTX_WINDOW_CID1_LOCK_MODE_SURE (2UL<<27) + #define TPATF_CTX_WINDOW_CID1_NO_EXT_ACC (1UL<<29) + #define TPATF_CTX_WINDOW_CID1_LOCK_STATUS (1UL<<30) + #define TPATF_CTX_WINDOW_CID1_LOCK_REQ (1UL<<31) + + u32_t tpatf_ctx_window_cid2; + #define TPATF_CTX_WINDOW_CID2_LOCK_TYPE (0x7UL<<0) + #define TPATF_CTX_WINDOW_CID2_LOCK_TYPE_VOID (0UL<<0) + #define TPATF_CTX_WINDOW_CID2_LOCK_TYPE_PROTOCOL (1UL<<0) + #define TPATF_CTX_WINDOW_CID2_LOCK_TYPE_TX (2UL<<0) + #define TPATF_CTX_WINDOW_CID2_LOCK_TYPE_TIMER (4UL<<0) + #define TPATF_CTX_WINDOW_CID2_LOCK_TYPE_COMPLETE (7UL<<0) + #define TPATF_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) + #define TPATF_CTX_WINDOW_CID2_MOD_USAGE_CNT (0x3UL<<24) + #define TPATF_CTX_WINDOW_CID2_MOD_USAGE_CNT_00 (0UL<<24) + #define TPATF_CTX_WINDOW_CID2_MOD_USAGE_CNT_01 (1UL<<24) + #define TPATF_CTX_WINDOW_CID2_MOD_USAGE_CNT_10 (2UL<<24) + #define TPATF_CTX_WINDOW_CID2_MOD_USAGE_CNT_11 (3UL<<24) + #define TPATF_CTX_WINDOW_CID2_LOCK_GRANTED (1UL<<26) + #define TPATF_CTX_WINDOW_CID2_LOCK_MODE (0x3UL<<27) + #define TPATF_CTX_WINDOW_CID2_LOCK_MODE_UNLOCK (0UL<<27) + #define TPATF_CTX_WINDOW_CID2_LOCK_MODE_IMMEDIATE (1UL<<27) + #define TPATF_CTX_WINDOW_CID2_LOCK_MODE_SURE (2UL<<27) + #define TPATF_CTX_WINDOW_CID2_NO_EXT_ACC (1UL<<29) + #define TPATF_CTX_WINDOW_CID2_LOCK_STATUS (1UL<<30) + #define TPATF_CTX_WINDOW_CID2_LOCK_REQ (1UL<<31) + + u32_t tpatf_ctx_window_cid3; + #define TPATF_CTX_WINDOW_CID3_LOCK_TYPE (0x7UL<<0) + #define TPATF_CTX_WINDOW_CID3_LOCK_TYPE_VOID (0UL<<0) + #define TPATF_CTX_WINDOW_CID3_LOCK_TYPE_PROTOCOL (1UL<<0) + #define TPATF_CTX_WINDOW_CID3_LOCK_TYPE_TX (2UL<<0) + #define TPATF_CTX_WINDOW_CID3_LOCK_TYPE_TIMER (4UL<<0) + #define TPATF_CTX_WINDOW_CID3_LOCK_TYPE_COMPLETE (7UL<<0) + #define TPATF_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) + #define TPATF_CTX_WINDOW_CID3_MOD_USAGE_CNT (0x3UL<<24) + #define TPATF_CTX_WINDOW_CID3_MOD_USAGE_CNT_00 (0UL<<24) + #define TPATF_CTX_WINDOW_CID3_MOD_USAGE_CNT_01 (1UL<<24) + #define TPATF_CTX_WINDOW_CID3_MOD_USAGE_CNT_10 (2UL<<24) + #define TPATF_CTX_WINDOW_CID3_MOD_USAGE_CNT_11 (3UL<<24) + #define TPATF_CTX_WINDOW_CID3_LOCK_GRANTED (1UL<<26) + #define TPATF_CTX_WINDOW_CID3_LOCK_MODE (0x3UL<<27) + #define TPATF_CTX_WINDOW_CID3_LOCK_MODE_UNLOCK (0UL<<27) + #define TPATF_CTX_WINDOW_CID3_LOCK_MODE_IMMEDIATE (1UL<<27) + #define TPATF_CTX_WINDOW_CID3_LOCK_MODE_SURE (2UL<<27) + #define TPATF_CTX_WINDOW_CID3_NO_EXT_ACC (1UL<<29) + #define TPATF_CTX_WINDOW_CID3_LOCK_STATUS (1UL<<30) + #define TPATF_CTX_WINDOW_CID3_LOCK_REQ (1UL<<31) + + u32_t tpatf_ctx_window_cid4; + #define TPATF_CTX_WINDOW_CID4_LOCK_TYPE (0x7UL<<0) + #define TPATF_CTX_WINDOW_CID4_LOCK_TYPE_VOID (0UL<<0) + #define TPATF_CTX_WINDOW_CID4_LOCK_TYPE_PROTOCOL (1UL<<0) + #define TPATF_CTX_WINDOW_CID4_LOCK_TYPE_TX (2UL<<0) + #define TPATF_CTX_WINDOW_CID4_LOCK_TYPE_TIMER (4UL<<0) + #define TPATF_CTX_WINDOW_CID4_LOCK_TYPE_COMPLETE (7UL<<0) + #define TPATF_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) + #define TPATF_CTX_WINDOW_CID4_MOD_USAGE_CNT (0x3UL<<24) + #define TPATF_CTX_WINDOW_CID4_MOD_USAGE_CNT_00 (0UL<<24) + #define TPATF_CTX_WINDOW_CID4_MOD_USAGE_CNT_01 (1UL<<24) + #define TPATF_CTX_WINDOW_CID4_MOD_USAGE_CNT_10 (2UL<<24) + #define TPATF_CTX_WINDOW_CID4_MOD_USAGE_CNT_11 (3UL<<24) + #define TPATF_CTX_WINDOW_CID4_LOCK_GRANTED (1UL<<26) + #define TPATF_CTX_WINDOW_CID4_LOCK_MODE (0x3UL<<27) + #define TPATF_CTX_WINDOW_CID4_LOCK_MODE_UNLOCK (0UL<<27) + #define TPATF_CTX_WINDOW_CID4_LOCK_MODE_IMMEDIATE (1UL<<27) + #define TPATF_CTX_WINDOW_CID4_LOCK_MODE_SURE (2UL<<27) + #define TPATF_CTX_WINDOW_CID4_NO_EXT_ACC (1UL<<29) + #define TPATF_CTX_WINDOW_CID4_LOCK_STATUS (1UL<<30) + #define TPATF_CTX_WINDOW_CID4_LOCK_REQ (1UL<<31) + u32_t unused_1[4]; + + u32_t tpatf_tpat_hc_inc_stat[4]; + u32_t unused_2[8]; + u32_t tpatf_free_counter_value; + u32_t tpatf_tpat_tx_quick_cons_idx; + #define TPATF_TPAT_TX_QUICK_CONS_IDX_INDEX_VAL (0xffffUL<<0) + #define TPATF_TPAT_TX_QUICK_CONS_IDX_INDEX_NUM (0xfUL<<20) + #define TPATF_TPAT_TX_QUICK_CONS_IDX_COALESCE_NOW (1UL<<30) + #define TPATF_TPAT_TX_QUICK_CONS_IDX_REQ_N (1UL<<31) + u32_t unused_3[2]; + + u32_t tpatf_tpat_pq_cons; + #define TPATF_TPAT_PQ_CONS_PQ_CONS_VAL (0x1fffUL<<3) + + u32_t tpatf_tpat_hq_cons; + #define TPATF_TPAT_HQ_CONS_HQ_CONS_VAL (0x7ffUL<<3) + u32_t unused_4[2]; + + u32_t tpatf_ctx_window_cid5; + #define TPATF_CTX_WINDOW_CID5_LOCK_TYPE (0x7UL<<0) + #define TPATF_CTX_WINDOW_CID5_LOCK_TYPE_VOID (0UL<<0) + #define TPATF_CTX_WINDOW_CID5_LOCK_TYPE_PROTOCOL (1UL<<0) + #define TPATF_CTX_WINDOW_CID5_LOCK_TYPE_TX (2UL<<0) + #define TPATF_CTX_WINDOW_CID5_LOCK_TYPE_TIMER (4UL<<0) + #define TPATF_CTX_WINDOW_CID5_LOCK_TYPE_COMPLETE (7UL<<0) + #define TPATF_CTX_WINDOW_CID5_VALUE (0x3fffUL<<7) + #define TPATF_CTX_WINDOW_CID5_MOD_USAGE_CNT (0x3UL<<24) + #define TPATF_CTX_WINDOW_CID5_MOD_USAGE_CNT_00 (0UL<<24) + #define TPATF_CTX_WINDOW_CID5_MOD_USAGE_CNT_01 (1UL<<24) + #define TPATF_CTX_WINDOW_CID5_MOD_USAGE_CNT_10 (2UL<<24) + #define TPATF_CTX_WINDOW_CID5_MOD_USAGE_CNT_11 (3UL<<24) + #define TPATF_CTX_WINDOW_CID5_LOCK_GRANTED (1UL<<26) + #define TPATF_CTX_WINDOW_CID5_LOCK_MODE (0x3UL<<27) + #define TPATF_CTX_WINDOW_CID5_LOCK_MODE_UNLOCK (0UL<<27) + #define TPATF_CTX_WINDOW_CID5_LOCK_MODE_IMMEDIATE (1UL<<27) + #define TPATF_CTX_WINDOW_CID5_LOCK_MODE_SURE (2UL<<27) + #define TPATF_CTX_WINDOW_CID5_NO_EXT_ACC (1UL<<29) + #define TPATF_CTX_WINDOW_CID5_LOCK_STATUS (1UL<<30) + #define TPATF_CTX_WINDOW_CID5_LOCK_REQ (1UL<<31) + + u32_t tpatf_ctx_window_cid6; + #define TPATF_CTX_WINDOW_CID6_LOCK_TYPE (0x7UL<<0) + #define TPATF_CTX_WINDOW_CID6_LOCK_TYPE_VOID (0UL<<0) + #define TPATF_CTX_WINDOW_CID6_LOCK_TYPE_PROTOCOL (1UL<<0) + #define TPATF_CTX_WINDOW_CID6_LOCK_TYPE_TX (2UL<<0) + #define TPATF_CTX_WINDOW_CID6_LOCK_TYPE_TIMER (4UL<<0) + #define TPATF_CTX_WINDOW_CID6_LOCK_TYPE_COMPLETE (7UL<<0) + #define TPATF_CTX_WINDOW_CID6_VALUE (0x3fffUL<<7) + #define TPATF_CTX_WINDOW_CID6_MOD_USAGE_CNT (0x3UL<<24) + #define TPATF_CTX_WINDOW_CID6_MOD_USAGE_CNT_00 (0UL<<24) + #define TPATF_CTX_WINDOW_CID6_MOD_USAGE_CNT_01 (1UL<<24) + #define TPATF_CTX_WINDOW_CID6_MOD_USAGE_CNT_10 (2UL<<24) + #define TPATF_CTX_WINDOW_CID6_MOD_USAGE_CNT_11 (3UL<<24) + #define TPATF_CTX_WINDOW_CID6_LOCK_GRANTED (1UL<<26) + #define TPATF_CTX_WINDOW_CID6_LOCK_MODE (0x3UL<<27) + #define TPATF_CTX_WINDOW_CID6_LOCK_MODE_UNLOCK (0UL<<27) + #define TPATF_CTX_WINDOW_CID6_LOCK_MODE_IMMEDIATE (1UL<<27) + #define TPATF_CTX_WINDOW_CID6_LOCK_MODE_SURE (2UL<<27) + #define TPATF_CTX_WINDOW_CID6_NO_EXT_ACC (1UL<<29) + #define TPATF_CTX_WINDOW_CID6_LOCK_STATUS (1UL<<30) + #define TPATF_CTX_WINDOW_CID6_LOCK_REQ (1UL<<31) + u32_t unused_5[26]; + + u32_t tpatf_tpatq_cid; + #define TPATF_TPATQ_CID_VALUE (0x3fffUL<<7) + + u16_t tpatf_tpatq_nbytes; + #define TPATF_TPATQ_NBYTES_VALUE (0x3fff<<0) + + u8_t tpatf_tpatq_xnum; + u8_t tpatf_tpatq_knum; + u32_t tpatf_tpatq_flags_flags; + #define TPATF_TPATQ_FLAGS_FLAGS_PLUS_TWO (1UL<<0) + #define TPATF_TPATQ_FLAGS_FLAGS_TCP_UDP_CKSUM (1UL<<1) + #define TPATF_TPATQ_FLAGS_FLAGS_IP_CKSUM (1UL<<2) + #define TPATF_TPATQ_FLAGS_FLAGS_INCR_CMD (1UL<<3) + #define TPATF_TPATQ_FLAGS_FLAGS_COAL_NOW (1UL<<4) + #define TPATF_TPATQ_FLAGS_FLAGS_DONT_GEN_CRC (1UL<<5) + #define TPATF_TPATQ_FLAGS_FLAGS_LAST_PKT (1UL<<6) + #define TPATF_TPATQ_FLAGS_FLAGS_PKT_FRAG (1UL<<7) + #define TPATF_TPATQ_FLAGS_FLAGS_QUICK_CID_ENA (1UL<<9) + #define TPATF_TPATQ_FLAGS_FLAGS_RSVD_FUTURE (0x3UL<<10) + #define TPATF_TPATQ_FLAGS_FLAGS_L5_PAGE_MODE (1UL<<12) + #define TPATF_TPATQ_FLAGS_FLAGS_COMPLETE (1UL<<13) + #define TPATF_TPATQ_FLAGS_FLAGS_RETRAN (1UL<<14) + #define TPATF_TPATQ_FLAGS_FLAGS_END_PADDING (0xfUL<<16) + #define TPATF_TPATQ_FLAGS_FLAGS_USAGE_CNT (1UL<<20) + #define TPATF_TPATQ_FLAGS_FLAGS_USAGE_CNT_AUTODECREMENT (0UL<<20) + #define TPATF_TPATQ_FLAGS_FLAGS_USAGE_CNT_DONOTDECREMENT (1UL<<20) + #define TPATF_TPATQ_FLAGS_FLAGS_BSEQ_INVLD (1UL<<21) + #define TPATF_TPATQ_FLAGS_FLAGS_WORK_AROUND (0x3UL<<22) + #define TPATF_TPATQ_FLAGS_FLAGS_HOLE_SZ (0x3UL<<25) + #define TPATF_TPATQ_FLAGS_FLAGS_HOLE_SZ_4 (0UL<<25) + #define TPATF_TPATQ_FLAGS_FLAGS_HOLE_SZ_8 (1UL<<25) + #define TPATF_TPATQ_FLAGS_FLAGS_HOLE_SZ_12 (2UL<<25) + #define TPATF_TPATQ_FLAGS_FLAGS_HOLE_SZ_16 (3UL<<25) + #define TPATF_TPATQ_FLAGS_FLAGS_HOLE0 (1UL<<28) + #define TPATF_TPATQ_FLAGS_FLAGS_HOLE1 (1UL<<29) + #define TPATF_TPATQ_FLAGS_FLAGS_HOLE2 (1UL<<30) + + u16_t tpatf_tpatq_raw_chksum; + u16_t tpatf_tpatq_tpat_bidx; + u8_t tpatf_tpatq_status; + #define TPATF_TPATQ_STATUS_CS16_ERR (1<<0) + u8_t unused_6; + u16_t unused_7; + u32_t unused_8[9]; + + u32_t tpatf_tpatq_ftq_cmd; + #define TPATF_TPATQ_FTQ_CMD_TPATQ_CMD_POP (1UL<<30) + u32_t unused_9; + + u16_t tpatf_tasq_hdr_skip; + u16_t tpatf_tasq_hdr_post_skip; + u16_t tpatf_tasq_hdr_size; + u16_t tpatf_tasq_payload_skip; + u16_t tpatf_tasq_payload_size; + u16_t tpatf_tasq_flags; + #define TPATF_TASQ_FLAGS_PKT_END (1<<0) + #define TPATF_TASQ_FLAGS_MGMT_PACKET (1<<1) + #define TPATF_TASQ_FLAGS_CATCHUP_PACKET (1<<2) + #define TPATF_TASQ_FLAGS_DONT_GEN_CRC (1<<3) + #define TPATF_TASQ_FLAGS_DROP (1<<4) + #define TPATF_TASQ_FLAGS_RESERVED (0x3<<5) + #define TPATF_TASQ_FLAGS_MGMT_PKT_TAG_XI (0x1f<<8) + #define TPATF_TASQ_FLAGS_CS16_VLD (1<<15) + + u16_t tpatf_tasq_cs16; + #define TPATF_TASQ_CS16_VALUE (0xffff<<0) + u16_t unused_10; + u32_t unused_11[10]; + + u32_t tpatf_tasq_ftq_cmd; + #define TPATF_TASQ_FTQ_CMD_CPY_DATA (1UL<<11) + #define TPATF_TASQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define TPATF_TASQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define TPATF_TASQ_FTQ_CMD_BUSY (1UL<<31) + u32_t unused_12[429]; + + u32_t tpatf_ctx_cmd; + #define TPATF_CTX_CMD_NUM_BLOCKS (0x3UL<<0) + #define TPATF_CTX_CMD_OFFSET (0x1ffUL<<3) + #define TPATF_CTX_CMD_CID_VALUE (0x3fffUL<<12) + #define TPATF_CTX_CMD_PREFETCH_SIZE (0x3UL<<26) + #define TPATF_CTX_CMD_MOD_USAGE_CNT (0x3UL<<28) + #define TPATF_CTX_CMD_MOD_USAGE_CNT_00 (0UL<<28) + #define TPATF_CTX_CMD_MOD_USAGE_CNT_01 (1UL<<28) + #define TPATF_CTX_CMD_MOD_USAGE_CNT_10 (2UL<<28) + #define TPATF_CTX_CMD_MOD_USAGE_CNT_11 (3UL<<28) + u32_t unused_13[499]; + + u32_t tpatf_tpat_crack_cmd; + #define TPATF_TPAT_CRACK_CMD_CRC32_1_LEN (0xffffUL<<0) + #define TPATF_TPAT_CRACK_CMD_CRACK (1UL<<16) + #define TPATF_TPAT_CRACK_CMD_L2_VLAN (1UL<<17) + #define TPATF_TPAT_CRACK_CMD_L2_LLC (1UL<<18) + #define TPATF_TPAT_CRACK_CMD_PLUS_TWO (1UL<<19) + #define TPATF_TPAT_CRACK_CMD_L3_UPDATE (1UL<<20) + #define TPATF_TPAT_CRACK_CMD_L4_UDP (1UL<<21) + #define TPATF_TPAT_CRACK_CMD_L4_USE_RAW (1UL<<22) + #define TPATF_TPAT_CRACK_CMD_PART_HDR_CS (1UL<<23) + #define TPATF_TPAT_CRACK_CMD_L4_UPDATE (1UL<<24) + #define TPATF_TPAT_CRACK_CMD_CRC32_2_START (1UL<<25) + #define TPATF_TPAT_CRACK_CMD_CRC32_1_INIT (1UL<<26) + #define TPATF_TPAT_CRACK_CMD_IPV6_ADDR (1UL<<27) + #define TPATF_TPAT_CRACK_CMD_RESULT_REG_CLEAR (1UL<<28) + #define TPATF_TPAT_CRACK_CMD_DATA_PATH_CLEAR (1UL<<29) + #define TPATF_TPAT_CRACK_CMD_DONE (1UL<<31) + + u16_t tpatf_tpat_crack_ip_offset; + u16_t tpatf_tpat_crack_ip_len; + u16_t tpatf_tpat_crack_tcp_offset; + u16_t tpatf_tpat_crack_tcp_len; + u16_t tpatf_tpat_crack_l5_offset; + u16_t tpatf_tpat_crack_l5_len; + u16_t tpatf_tpat_crack_ip_chksum; + u16_t tpatf_tpat_crack_ip_pseudo_chksum; + u16_t tpatf_tpat_crack_tcp_chksum; + u16_t tpatf_tpat_crack_crc32_1_start; + u32_t tpatf_tpat_crack_crc32_1_seed; + u32_t tpatf_tpat_crack_crc32_1_result; + u32_t tpatf_tpat_crack_crc32_2_result; + u32_t tpatf_ipv6_programmable_extension0; + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN (0xffUL<<0) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER (0xffUL<<16) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN (1UL<<31) + + u32_t tpatf_ipv6_programmable_extension1; + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN (0xffUL<<0) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER (0xffUL<<16) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN (1UL<<31) + + u32_t tpatf_ipv6_programmable_extension2; + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN (0xffUL<<0) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER (0xffUL<<16) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN (1UL<<31) + + u32_t tpatf_ipv6_programmable_extension3; + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN (0xffUL<<0) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER (0xffUL<<16) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN (1UL<<31) + + u32_t tpatf_ipv6_programmable_extension4; + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN (0xffUL<<0) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER (0xffUL<<16) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN (1UL<<31) + + u32_t tpatf_ipv6_programmable_extension5; + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN (0xffUL<<0) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER (0xffUL<<16) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN (1UL<<31) + + u32_t tpatf_ipv6_programmable_extension6; + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN (0xffUL<<0) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER (0xffUL<<16) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN (1UL<<31) + + u32_t tpatf_ipv6_programmable_extension7; + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN (0xffUL<<0) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER (0xffUL<<16) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE (1UL<<30) + #define TPATF_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN (1UL<<31) + + u32_t tpatf_tpatc_debug1; + u32_t tpatf_tpatc_debug2; + u32_t unused_14[3053]; + u32_t tpatf_tx_header_queue[4096]; + u32_t tpatf_tx_payload_queue[16384]; + u32_t unused_15[40960]; + u32_t tpatf_ctx_window5[32768]; + u32_t tpatf_ctx_window6[32768]; + u32_t tpatf_ctx_window1[32768]; + u32_t tpatf_ctx_window2[32768]; + u32_t tpatf_ctx_window3[32768]; + u32_t tpatf_ctx_window4[32768]; +} tpat_fio_xi_t; + + +/* + * rxp_fio definition + * offset: 0x80000000 + */ +typedef struct rxp_fio +{ + u32_t rxpf_events_bits; + #define RXPF_EVENTS_BITS_GPIO0 (1UL<<15) + #define RXPF_EVENTS_BITS_GPIO1 (1UL<<16) + #define RXPF_EVENTS_BITS_GPIO2 (1UL<<17) + #define RXPF_EVENTS_BITS_GPIO3 (1UL<<18) + + u32_t rxpf_attentions_bits; + #define RXPF_ATTENTIONS_BITS_EPB_ERROR (1UL<<30) + + u32_t rxpf_event_enable; + u32_t rxpf_attention_enable; + u32_t rxpf_fio_status; + + u32_t rxpf_mult_result; + u32_t rxpf_mult_a; + + u32_t rxpf_mult_b; + + u32_t rxpf_ctx_window_cid1; + + u32_t rxpf_ctx_window_cid2; + #define RXPF_CTX_WINDOW_CID2_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) + + u32_t rxpf_ctx_window_cid3; + #define RXPF_CTX_WINDOW_CID3_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) + + u32_t rxpf_ctx_window_cid4; + #define RXPF_CTX_WINDOW_CID4_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) + u32_t unused_0[4]; + + u32_t rxpf_hc_inc_tcp_insegs; + u32_t rxpf_hc_inc_tcp_inerrs; + u32_t rxpf_hc_inc_ip_inreceives; + u32_t rxpf_hc_inc_ip_inhdrerrors; + u32_t rxpf_hc_inc_ip_indiscards; + u32_t rxpf_hc_inc_ip_indelivers; + u32_t rxpf_hc_inc_ip_reasmreqds; + u32_t rxpf_hc_inc_ip_reasmoks; + u32_t rxpf_hc_inc_ip_reasmfails; + u32_t rxpf_hc_inc_stat[3]; + u32_t rxpf_free_counter_value; + u32_t rxpf_timer_retran_value; + u16_t rxpf_timer_rxpush_value; + u16_t rxpf_timer_delayack_value; + u16_t rxpf_timer_keepalive_value; + u16_t rxpf_timer_nagle_value; + u32_t rxpf_rxp_rbuf_cluster; + + u32_t rxpf_rxp_rbuf_burst_offset; + #define RXPF_RXP_RBUF_BURST_OFFSET_OFFSET_TE (0x7ffUL<<3) + u32_t unused_1[30]; + + u32_t rxpf_rxpq_bits_errors; + #define RXPF_RXPQ_BITS_ERRORS_TCP_SYNC_PRESENT (1UL<<14) + + u32_t rxpf_rxpq_bits_status; + #define RXPF_RXPQ_BITS_STATUS_VALID (1UL<<20) + + u8_t rxpf_rxpq_bits_multicast_hash_idx; + u8_t rxpf_rxpq_bits_acpi_pat; + #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_TE (0x7<<0) + + u8_t rxpf_rxpq_knum; + u8_t unused_2; + u16_t rxpf_rxpq_rule_tag; + u16_t rxpf_rxpq_pkt_len; + u16_t rxpf_rxpq_vlan_tag; + u8_t rxpf_rxpq_ip_hdr_offset; + u8_t unused_3; + u16_t rxpf_rxpq_ip_xsum; + u8_t rxpf_rxpq_tcp_udp_hdr_offset; + u8_t unused_4; + u16_t rxpf_rxpq_tcp_udp_xsum; + u16_t rxpf_rxpq_tcp_payload_len; + u16_t rxpf_rxpq_pseud_xsum; + u16_t rxpf_rxpq_l2_payload_raw_xsum; + u8_t rxpf_rxpq_data_offset; + u8_t unused_5[3]; + u32_t rxpf_rxpq_mbuf_cluster; + u32_t rxpf_rxpq_cid; + u32_t unused_6[3]; + u32_t rxpf_rxpq_ftq_cmd; + + u32_t rxpf_rx_proc_ftq_trip; + + u32_t rxpf_rxpcq_cid; + u32_t rxpf_rxpcq_generic1; + u32_t rxpf_rxpcq_generic2; + u32_t unused_7[11]; + u32_t rxpf_rxpcq_ftq_cmd; + u32_t unused_8; + + u32_t rxpf_rv2ppq_cid; + u32_t rxpf_rv2ppq_mbuf_cluster; + u16_t rxpf_rv2ppq_operand_flags; + u8_t rxpf_rv2ppq_knum; + u8_t rxpf_rv2ppq_opcode; + u16_t rxpf_rv2ppq_operand16_0; // Note that 16_0 and 16_1 will be absorbed + u16_t rxpf_rv2ppq_operand16_1; // by RDMA and won't be passed to COM + u16_t rxpf_rv2ppq_operand16_2; + u16_t rxpf_rv2ppq_operand16_3; + u16_t rxpf_rv2ppq_operand16_4; + u16_t rxpf_rv2ppq_operand16_5; + u16_t rxpf_rv2ppq_operand16_6; + u16_t rxpf_rv2ppq_operand16_7; + u32_t rxpf_rv2ppq_operand32_0; // Note that 32_0 and 32_1 will be absorbed + u32_t rxpf_rv2ppq_operand32_1; // by RDMA and won't be passed to COM + u32_t rxpf_rv2ppq_operand32_2; + u32_t rxpf_rv2ppq_operand32_3; + u32_t rxpf_rv2ppq_operand32_4; + u32_t unused_9[2]; + u32_t rxpf_rv2ppq_ftq_cmd; + u32_t unused_10; + + u32_t rxpf_mcpq_bits_status; + u16_t rxpf_mcpq_pkt_len; + u16_t unused_11; + u32_t rxpf_mcpq_mbuf_cluster; + u32_t unused_12[11]; + u32_t rxpf_mcpq_ftq_cmd; + u32_t unused_13; + + u32_t rxpf_csq_cid; + u8_t rxpf_csq_flags; + u8_t unused_14; + u16_t unused_15; + u32_t unused_16[12]; + u32_t rxpf_csq_ftq_cmd; + u32_t unused_17[369]; + + u32_t rxpf_burst_base0; + + u32_t rxpf_burst_base1; + + u32_t rxpf_burst_base2; + + u32_t rxpf_burst_base3; + + u32_t rxpf_burst_cmd0; + + u32_t rxpf_burst_cmd1; + u32_t unused_18[58]; + + u32_t rxpf_burst_data0[16]; + u32_t rxpf_burst_data1[16]; + u32_t unused_19[32]; + u32_t rxpf_rbuf_burst_data[16]; + u32_t unused_20[3440]; + u32_t rxpf_rx_mbuf[4096]; + u32_t unused_21[122880]; + u32_t rxpf_ctx_window1[32768]; + u32_t rxpf_ctx_window2[32768]; + u32_t rxpf_ctx_window3[32768]; + u32_t rxpf_ctx_window4[32768]; +} rxp_fio_t; + + +/* + * rxp_fio definition + * offset: 0x80000000 + */ +typedef struct rxp_fio_xi +{ + u32_t rxpf_events_bits; + #define RXPF_EVENTS_BITS_FTQ0_VALID (1UL<<0) + #define RXPF_EVENTS_BITS_FTQ1_VALID (1UL<<1) + #define RXPF_EVENTS_BITS_FTQ2_VALID (1UL<<2) + #define RXPF_EVENTS_BITS_SCANNER_DONE (1UL<<3) + #define RXPF_EVENTS_BITS_DMA_WR_DONE (1UL<<4) + #define RXPF_EVENTS_BITS_DMA_RD_DONE (1UL<<5) + #define RXPF_EVENTS_BITS_CRACKER_DONE (1UL<<6) + #define RXPF_EVENTS_BITS_MULTIPLY_DONE (1UL<<7) + #define RXPF_EVENTS_BITS_EXP_ROM (1UL<<8) + #define RXPF_EVENTS_BITS_VPD (1UL<<9) + #define RXPF_EVENTS_BITS_FLASH (1UL<<10) + #define RXPF_EVENTS_BITS_SMB0 (1UL<<11) + #define RXPF_EVENTS_BITS_RESERVED0 (1UL<<12) + #define RXPF_EVENTS_BITS_RESERVED1 (1UL<<13) + #define RXPF_EVENTS_BITS_RESERVED2 (1UL<<14) + #define RXPF_EVENTS_BITS_GPIO (1UL<<15) + #define RXPF_EVENTS_BITS_SW_TMR_1 (1UL<<19) + #define RXPF_EVENTS_BITS_SW_TMR_2 (1UL<<20) + #define RXPF_EVENTS_BITS_SW_TMR_3 (1UL<<21) + #define RXPF_EVENTS_BITS_SW_TMR_4 (1UL<<22) + #define RXPF_EVENTS_BITS_LINK_CHANGED (1UL<<23) + #define RXPF_EVENTS_BITS_MI_INT (1UL<<25) + #define RXPF_EVENTS_BITS_MI_COMPLETE (1UL<<26) + #define RXPF_EVENTS_BITS_MAIN_PWR_INT (1UL<<27) + #define RXPF_EVENTS_BITS_NOT_ENABLED (1UL<<30) + #define RXPF_EVENTS_BITS_ATTENTIONS_VALID (1UL<<31) + + u32_t rxpf_attentions_bits; + #define RXPF_ATTENTIONS_BITS_LINK_STATE (1UL<<0) + #define RXPF_ATTENTIONS_BITS_TX_SCHEDULER_ABORT (1UL<<1) + #define RXPF_ATTENTIONS_BITS_TX_BD_READ_ABORT (1UL<<2) + #define RXPF_ATTENTIONS_BITS_TX_BD_CACHE_ABORT (1UL<<3) + #define RXPF_ATTENTIONS_BITS_TX_PROCESSOR_ABORT (1UL<<4) + #define RXPF_ATTENTIONS_BITS_TX_DMA_ABORT (1UL<<5) + #define RXPF_ATTENTIONS_BITS_TX_PATCHUP_ABORT (1UL<<6) + #define RXPF_ATTENTIONS_BITS_TX_ASSEMBLER_ABORT (1UL<<7) + #define RXPF_ATTENTIONS_BITS_RX_PARSER_MAC_ABORT (1UL<<8) + #define RXPF_ATTENTIONS_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) + #define RXPF_ATTENTIONS_BITS_RX_MBUF_ABORT (1UL<<10) + #define RXPF_ATTENTIONS_BITS_RX_LOOKUP_ABORT (1UL<<11) + #define RXPF_ATTENTIONS_BITS_RX_PROCESSOR_ABORT (1UL<<12) + #define RXPF_ATTENTIONS_BITS_RX_V2P_ABORT (1UL<<13) + #define RXPF_ATTENTIONS_BITS_RX_BD_CACHE_ABORT (1UL<<14) + #define RXPF_ATTENTIONS_BITS_RX_DMA_ABORT (1UL<<15) + #define RXPF_ATTENTIONS_BITS_COMPLETION_ABORT (1UL<<16) + #define RXPF_ATTENTIONS_BITS_HOST_COALESCE_ABORT (1UL<<17) + #define RXPF_ATTENTIONS_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) + #define RXPF_ATTENTIONS_BITS_CONTEXT_ABORT (1UL<<19) + #define RXPF_ATTENTIONS_BITS_CMD_SCHEDULER_ABORT (1UL<<20) + #define RXPF_ATTENTIONS_BITS_CMD_PROCESSOR_ABORT (1UL<<21) + #define RXPF_ATTENTIONS_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) + #define RXPF_ATTENTIONS_BITS_MAC_ABORT (1UL<<23) + #define RXPF_ATTENTIONS_BITS_TIMER_ABORT (1UL<<24) + #define RXPF_ATTENTIONS_BITS_DMAE_ABORT (1UL<<25) + #define RXPF_ATTENTIONS_BITS_FLSH_ABORT (1UL<<26) + #define RXPF_ATTENTIONS_BITS_GRC_ABORT (1UL<<27) + #define RXPF_ATTENTIONS_BITS_PARITY_ERROR (1UL<<31) + + u32_t rxpf_event_enable; + u32_t rxpf_attention_enable; + u32_t rxpf_fio_status; + #define RXPF_FIO_STATUS_ENABLED (1UL<<0) + #define RXPF_FIO_STATUS_FORCE_ENA (1UL<<1) + + u32_t rxpf_mult_result; + u32_t rxpf_mult_a; + #define RXPF_MULT_A_VALUE (0xffffUL<<0) + + u32_t rxpf_mult_b; + #define RXPF_MULT_B_VALUE (0xffffUL<<0) + + u32_t rxpf_ctx_window_cid1; + #define RXPF_CTX_WINDOW_CID1_LOCK_TYPE (0x7UL<<0) + #define RXPF_CTX_WINDOW_CID1_LOCK_TYPE_VOID (0UL<<0) + #define RXPF_CTX_WINDOW_CID1_LOCK_TYPE_PROTOCOL (1UL<<0) + #define RXPF_CTX_WINDOW_CID1_LOCK_TYPE_TX (2UL<<0) + #define RXPF_CTX_WINDOW_CID1_LOCK_TYPE_TIMER (4UL<<0) + #define RXPF_CTX_WINDOW_CID1_LOCK_TYPE_COMPLETE (7UL<<0) + #define RXPF_CTX_WINDOW_CID1_VALUE (0x3fffUL<<7) + #define RXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT (0x3UL<<24) + #define RXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_00 (0UL<<24) + #define RXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_01 (1UL<<24) + #define RXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_10 (2UL<<24) + #define RXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_11 (3UL<<24) + #define RXPF_CTX_WINDOW_CID1_LOCK_GRANTED (1UL<<26) + #define RXPF_CTX_WINDOW_CID1_LOCK_MODE (0x3UL<<27) + #define RXPF_CTX_WINDOW_CID1_LOCK_MODE_UNLOCK (0UL<<27) + #define RXPF_CTX_WINDOW_CID1_LOCK_MODE_IMMEDIATE (1UL<<27) + #define RXPF_CTX_WINDOW_CID1_LOCK_MODE_SURE (2UL<<27) + #define RXPF_CTX_WINDOW_CID1_NO_EXT_ACC (1UL<<29) + #define RXPF_CTX_WINDOW_CID1_LOCK_STATUS (1UL<<30) + #define RXPF_CTX_WINDOW_CID1_LOCK_REQ (1UL<<31) + + u32_t rxpf_ctx_window_cid2; + #define RXPF_CTX_WINDOW_CID2_LOCK_TYPE (0x7UL<<0) + #define RXPF_CTX_WINDOW_CID2_LOCK_TYPE_VOID (0UL<<0) + #define RXPF_CTX_WINDOW_CID2_LOCK_TYPE_PROTOCOL (1UL<<0) + #define RXPF_CTX_WINDOW_CID2_LOCK_TYPE_TX (2UL<<0) + #define RXPF_CTX_WINDOW_CID2_LOCK_TYPE_TIMER (4UL<<0) + #define RXPF_CTX_WINDOW_CID2_LOCK_TYPE_COMPLETE (7UL<<0) + #define RXPF_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) + #define RXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT (0x3UL<<24) + #define RXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_00 (0UL<<24) + #define RXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_01 (1UL<<24) + #define RXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_10 (2UL<<24) + #define RXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_11 (3UL<<24) + #define RXPF_CTX_WINDOW_CID2_LOCK_GRANTED (1UL<<26) + #define RXPF_CTX_WINDOW_CID2_LOCK_MODE (0x3UL<<27) + #define RXPF_CTX_WINDOW_CID2_LOCK_MODE_UNLOCK (0UL<<27) + #define RXPF_CTX_WINDOW_CID2_LOCK_MODE_IMMEDIATE (1UL<<27) + #define RXPF_CTX_WINDOW_CID2_LOCK_MODE_SURE (2UL<<27) + #define RXPF_CTX_WINDOW_CID2_NO_EXT_ACC (1UL<<29) + #define RXPF_CTX_WINDOW_CID2_LOCK_STATUS (1UL<<30) + #define RXPF_CTX_WINDOW_CID2_LOCK_REQ (1UL<<31) + + u32_t rxpf_ctx_window_cid3; + #define RXPF_CTX_WINDOW_CID3_LOCK_TYPE (0x7UL<<0) + #define RXPF_CTX_WINDOW_CID3_LOCK_TYPE_VOID (0UL<<0) + #define RXPF_CTX_WINDOW_CID3_LOCK_TYPE_PROTOCOL (1UL<<0) + #define RXPF_CTX_WINDOW_CID3_LOCK_TYPE_TX (2UL<<0) + #define RXPF_CTX_WINDOW_CID3_LOCK_TYPE_TIMER (4UL<<0) + #define RXPF_CTX_WINDOW_CID3_LOCK_TYPE_COMPLETE (7UL<<0) + #define RXPF_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) + #define RXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT (0x3UL<<24) + #define RXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_00 (0UL<<24) + #define RXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_01 (1UL<<24) + #define RXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_10 (2UL<<24) + #define RXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_11 (3UL<<24) + #define RXPF_CTX_WINDOW_CID3_LOCK_GRANTED (1UL<<26) + #define RXPF_CTX_WINDOW_CID3_LOCK_MODE (0x3UL<<27) + #define RXPF_CTX_WINDOW_CID3_LOCK_MODE_UNLOCK (0UL<<27) + #define RXPF_CTX_WINDOW_CID3_LOCK_MODE_IMMEDIATE (1UL<<27) + #define RXPF_CTX_WINDOW_CID3_LOCK_MODE_SURE (2UL<<27) + #define RXPF_CTX_WINDOW_CID3_NO_EXT_ACC (1UL<<29) + #define RXPF_CTX_WINDOW_CID3_LOCK_STATUS (1UL<<30) + #define RXPF_CTX_WINDOW_CID3_LOCK_REQ (1UL<<31) + + u32_t rxpf_ctx_window_cid4; + #define RXPF_CTX_WINDOW_CID4_LOCK_TYPE (0x7UL<<0) + #define RXPF_CTX_WINDOW_CID4_LOCK_TYPE_VOID (0UL<<0) + #define RXPF_CTX_WINDOW_CID4_LOCK_TYPE_PROTOCOL (1UL<<0) + #define RXPF_CTX_WINDOW_CID4_LOCK_TYPE_TX (2UL<<0) + #define RXPF_CTX_WINDOW_CID4_LOCK_TYPE_TIMER (4UL<<0) + #define RXPF_CTX_WINDOW_CID4_LOCK_TYPE_COMPLETE (7UL<<0) + #define RXPF_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) + #define RXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT (0x3UL<<24) + #define RXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_00 (0UL<<24) + #define RXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_01 (1UL<<24) + #define RXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_10 (2UL<<24) + #define RXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_11 (3UL<<24) + #define RXPF_CTX_WINDOW_CID4_LOCK_GRANTED (1UL<<26) + #define RXPF_CTX_WINDOW_CID4_LOCK_MODE (0x3UL<<27) + #define RXPF_CTX_WINDOW_CID4_LOCK_MODE_UNLOCK (0UL<<27) + #define RXPF_CTX_WINDOW_CID4_LOCK_MODE_IMMEDIATE (1UL<<27) + #define RXPF_CTX_WINDOW_CID4_LOCK_MODE_SURE (2UL<<27) + #define RXPF_CTX_WINDOW_CID4_NO_EXT_ACC (1UL<<29) + #define RXPF_CTX_WINDOW_CID4_LOCK_STATUS (1UL<<30) + #define RXPF_CTX_WINDOW_CID4_LOCK_REQ (1UL<<31) + u32_t unused_0[4]; + + u32_t rxpf_hc_inc_tcp_insegs; + u32_t rxpf_hc_inc_tcp_inerrs; + u32_t rxpf_hc_inc_ip_inreceives; + u32_t rxpf_hc_inc_ip_inhdrerrors; + u32_t rxpf_hc_inc_ip_indiscards; + u32_t rxpf_hc_inc_ip_indelivers; + u32_t rxpf_hc_inc_ip_reasmreqds; + u32_t rxpf_hc_inc_ip_reasmoks; + u32_t rxpf_hc_inc_ip_reasmfails; + u32_t rxpf_hc_inc_stat[3]; + u32_t rxpf_free_counter_value; + u32_t rxpf_timer_retran_value; + u16_t rxpf_timer_rxpush_value; + u16_t rxpf_timer_delayack_value; + u16_t rxpf_timer_keepalive_value; + u16_t rxpf_timer_nagle_value; + u32_t rxpf_rxp_rbuf_cluster; + #define RXPF_RXP_RBUF_CLUSTER_COUNT (0x7fUL<<0) + #define RXPF_RXP_RBUF_CLUSTER_TAIL (0x1ffUL<<7) + #define RXPF_RXP_RBUF_CLUSTER_HEAD (0x1ffUL<<16) + + u32_t rxpf_rxp_rbuf_burst_offset; + #define RXPF_RXP_RBUF_BURST_OFFSET_OFFSET_XI (0x3ffUL<<4) + #define RXPF_RXP_RBUF_BURST_OFFSET_BUSY (1UL<<31) + u32_t unused_1[2]; + + u32_t rxpf_ctx_window_cid5; + #define RXPF_CTX_WINDOW_CID5_LOCK_TYPE (0x7UL<<0) + #define RXPF_CTX_WINDOW_CID5_LOCK_TYPE_VOID (0UL<<0) + #define RXPF_CTX_WINDOW_CID5_LOCK_TYPE_PROTOCOL (1UL<<0) + #define RXPF_CTX_WINDOW_CID5_LOCK_TYPE_TX (2UL<<0) + #define RXPF_CTX_WINDOW_CID5_LOCK_TYPE_TIMER (4UL<<0) + #define RXPF_CTX_WINDOW_CID5_LOCK_TYPE_COMPLETE (7UL<<0) + #define RXPF_CTX_WINDOW_CID5_VALUE (0x3fffUL<<7) + #define RXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT (0x3UL<<24) + #define RXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_00 (0UL<<24) + #define RXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_01 (1UL<<24) + #define RXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_10 (2UL<<24) + #define RXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_11 (3UL<<24) + #define RXPF_CTX_WINDOW_CID5_LOCK_GRANTED (1UL<<26) + #define RXPF_CTX_WINDOW_CID5_LOCK_MODE (0x3UL<<27) + #define RXPF_CTX_WINDOW_CID5_LOCK_MODE_UNLOCK (0UL<<27) + #define RXPF_CTX_WINDOW_CID5_LOCK_MODE_IMMEDIATE (1UL<<27) + #define RXPF_CTX_WINDOW_CID5_LOCK_MODE_SURE (2UL<<27) + #define RXPF_CTX_WINDOW_CID5_NO_EXT_ACC (1UL<<29) + #define RXPF_CTX_WINDOW_CID5_LOCK_STATUS (1UL<<30) + #define RXPF_CTX_WINDOW_CID5_LOCK_REQ (1UL<<31) + + u32_t rxpf_ctx_window_cid6; + #define RXPF_CTX_WINDOW_CID6_LOCK_TYPE (0x7UL<<0) + #define RXPF_CTX_WINDOW_CID6_LOCK_TYPE_VOID (0UL<<0) + #define RXPF_CTX_WINDOW_CID6_LOCK_TYPE_PROTOCOL (1UL<<0) + #define RXPF_CTX_WINDOW_CID6_LOCK_TYPE_TX (2UL<<0) + #define RXPF_CTX_WINDOW_CID6_LOCK_TYPE_TIMER (4UL<<0) + #define RXPF_CTX_WINDOW_CID6_LOCK_TYPE_COMPLETE (7UL<<0) + #define RXPF_CTX_WINDOW_CID6_VALUE (0x3fffUL<<7) + #define RXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT (0x3UL<<24) + #define RXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_00 (0UL<<24) + #define RXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_01 (1UL<<24) + #define RXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_10 (2UL<<24) + #define RXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_11 (3UL<<24) + #define RXPF_CTX_WINDOW_CID6_LOCK_GRANTED (1UL<<26) + #define RXPF_CTX_WINDOW_CID6_LOCK_MODE (0x3UL<<27) + #define RXPF_CTX_WINDOW_CID6_LOCK_MODE_UNLOCK (0UL<<27) + #define RXPF_CTX_WINDOW_CID6_LOCK_MODE_IMMEDIATE (1UL<<27) + #define RXPF_CTX_WINDOW_CID6_LOCK_MODE_SURE (2UL<<27) + #define RXPF_CTX_WINDOW_CID6_NO_EXT_ACC (1UL<<29) + #define RXPF_CTX_WINDOW_CID6_LOCK_STATUS (1UL<<30) + #define RXPF_CTX_WINDOW_CID6_LOCK_REQ (1UL<<31) + u32_t unused_2[2]; + + u32_t rxpf_crc32_command; + #define RXPF_CRC32_COMMAND_OFFSET (0x7fUL<<0) + #define RXPF_CRC32_COMMAND_LENGTH (0x7fUL<<8) + #define RXPF_CRC32_COMMAND_USE_INTM_SEED (1UL<<20) + #define RXPF_CRC32_COMMAND_START (1UL<<31) + + u32_t rxpf_crc32_seed; + u32_t rxpf_crc32_result; + u32_t rxpf_crc32_intm_seed; + u32_t unused_3[20]; + u32_t rxpf_rxpq_bits_errors; + #define RXPF_RXPQ_BITS_ERRORS_L2_USE_HEADER_LENGTH (1UL<<0) // For Jumbo Frame support + #define RXPF_RXPQ_BITS_ERRORS_L2_BAD_CRC (1UL<<1) + #define RXPF_RXPQ_BITS_ERRORS_L2_PHY_DECODE (1UL<<2) + #define RXPF_RXPQ_BITS_ERRORS_L2_ALIGNMENT (1UL<<3) + #define RXPF_RXPQ_BITS_ERRORS_L2_TOO_SHORT (1UL<<4) + #define RXPF_RXPQ_BITS_ERRORS_L2_GIANT_FRAME (1UL<<5) + #define RXPF_RXPQ_BITS_ERRORS_IP_BAD_LEN (1UL<<6) + #define RXPF_RXPQ_BITS_ERRORS_IP_TOO_SHORT (1UL<<7) + #define RXPF_RXPQ_BITS_ERRORS_IP_BAD_VERSION (1UL<<8) + #define RXPF_RXPQ_BITS_ERRORS_IP_BAD_HLEN (1UL<<9) + #define RXPF_RXPQ_BITS_ERRORS_IP_BAD_XSUM (1UL<<10) + #define RXPF_RXPQ_BITS_ERRORS_TCP_TOO_SHORT (1UL<<11) + #define RXPF_RXPQ_BITS_ERRORS_TCP_BAD_XSUM (1UL<<12) + #define RXPF_RXPQ_BITS_ERRORS_TCP_BAD_OFFSET (1UL<<13) + #define RXPF_RXPQ_BITS_ERRORS_TCP_SYNC_PRESENT (1UL<<14) + #define RXPF_RXPQ_BITS_ERRORS_UDP_BAD_XSUM (1UL<<15) + #define RXPF_RXPQ_BITS_ERRORS_IP_BAD_ORDER (1UL<<16) + #define RXPF_RXPQ_BITS_ERRORS_IP_HDR_MISMATCH (1UL<<18) + + u32_t rxpf_rxpq_bits_status; + #define RXPF_RXPQ_BITS_STATUS_RULE_CLASS (0x7UL<<0) + #define RXPF_RXPQ_BITS_STATUS_RULE_P2 (1UL<<3) + #define RXPF_RXPQ_BITS_STATUS_RULE_P3 (1UL<<4) + #define RXPF_RXPQ_BITS_STATUS_RULE_P4 (1UL<<5) + #define RXPF_RXPQ_BITS_STATUS_L2_VLAN_TAG (1UL<<6) + #define RXPF_RXPQ_BITS_STATUS_L2_LLC_SNAP (1UL<<7) + #define RXPF_RXPQ_BITS_STATUS_RSS_HASH (1UL<<8) + #define RXPF_RXPQ_BITS_STATUS_SORT_VECT (0xfUL<<9) + #define RXPF_RXPQ_BITS_STATUS_IP_DATAGRAM (1UL<<13) + #define RXPF_RXPQ_BITS_STATUS_TCP_SEGMENT (1UL<<14) + #define RXPF_RXPQ_BITS_STATUS_UDP_DATAGRAM (1UL<<15) + #define RXPF_RXPQ_BITS_STATUS_CU_FRAME (1UL<<16) + #define RXPF_RXPQ_BITS_STATUS_IP_PROG_EXT (1UL<<17) + #define RXPF_RXPQ_BITS_STATUS_IP_TYPE (1UL<<18) + #define RXPF_RXPQ_BITS_STATUS_RULE_P1 (1UL<<19) + #define RXPF_RXPQ_BITS_STATUS_RLUP_HIT4 (1UL<<20) + #define RXPF_RXPQ_BITS_STATUS_IP_FRAGMENT (1UL<<21) + #define RXPF_RXPQ_BITS_STATUS_IP_OPTIONS_PRESENT (1UL<<22) + #define RXPF_RXPQ_BITS_STATUS_TCP_OPTIONS_PRESENT (1UL<<23) + #define RXPF_RXPQ_BITS_STATUS_L2_PM_IDX (0xfUL<<24) + #define RXPF_RXPQ_BITS_STATUS_L2_PM_HIT (1UL<<28) + #define RXPF_RXPQ_BITS_STATUS_L2_MC_HASH_HIT (1UL<<29) + #define RXPF_RXPQ_BITS_STATUS_RDMAC_CRC_PASS (1UL<<30) + #define RXPF_RXPQ_BITS_STATUS_MP_HIT (1UL<<31) + + u8_t rxpf_rxpq_bits_multicast_hash_idx; + u8_t rxpf_rxpq_bits_acpi_pat; + #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_XI (0xf<<0) + #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_0 (0<<0) + #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_1 (1<<0) + #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_2 (2<<0) + #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_3 (3<<0) + #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_4 (4<<0) + #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_5 (5<<0) + #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_6 (6<<0) + #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_NONE (7<<0) + #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_8 (8<<0) + + u8_t rxpf_rxpq_knum; + u8_t unused_4; + u16_t rxpf_rxpq_rule_tag; + u16_t rxpf_rxpq_pkt_len; + #define RXPF_RXPQ_PKT_LEN_VALUE (0x3fff<<0) + + u16_t rxpf_rxpq_vlan_tag; + u8_t rxpf_rxpq_ip_hdr_offset; + u8_t rxpf_rxpq_rx_qid; + #define RXPF_RXPQ_RX_QID_VALUE (0xf<<0) + + u16_t rxpf_rxpq_ip_xsum; + u16_t rxpf_rxpq_tcp_udp_hdr_offset; + u16_t rxpf_rxpq_tcp_udp_xsum; + u16_t rxpf_rxpq_tcp_payload_len; + u16_t rxpf_rxpq_pseud_xsum; + u16_t rxpf_rxpq_l2_payload_raw_xsum; + u16_t rxpf_rxpq_data_offset; + u16_t rxpf_rxpq_l3_payload_raw_xsum; + u32_t rxpf_rxpq_mbuf_cluster; + #define RXPF_RXPQ_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) + + u32_t rxpf_rxpq_cid; + #define RXPF_RXPQ_CID_VALUE (0x3fffUL<<7) + + u16_t rxpf_rxpq_cs16; + #define RXPF_RXPQ_CS16_VALUE (0xffff<<0) + u16_t unused_5; + + u16_t rxpf_rxpq_ext_status; + #define RXPF_RXPQ_EXT_STATUS_TCP_SYNC_PRESENT (1<<0) + #define RXPF_RXPQ_EXT_STATUS_RLUP_HIT2 (1<<1) + #define RXPF_RXPQ_EXT_STATUS_TCP_UDP_XSUM_IS_0 (1<<2) + #define RXPF_RXPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT (0x3<<3) + #define RXPF_RXPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_00 (0<<3) + #define RXPF_RXPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_01 (1<<3) + #define RXPF_RXPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_10 (2<<3) + #define RXPF_RXPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_11 (3<<3) + #define RXPF_RXPQ_EXT_STATUS_ACPI_MATCH (1<<5) + u16_t unused_6; + u32_t unused_7; + + u32_t rxpf_rxpq_ftq_cmd; + #define RXPF_RXPQ_FTQ_CMD_RXPQ_CMD_POP (1UL<<30) + + u32_t rxpf_rx_proc_ftq_trip; + #define RXPF_RX_PROC_FTQ_TRIP_FF (0x1ffUL<<0) + #define RXPF_RX_PROC_FTQ_TRIP_N (0x1ffUL<<16) + + u32_t rxpf_rxpcq_cid; + u32_t rxpf_rxpcq_generic1; + u32_t rxpf_rxpcq_generic2; + u32_t unused_8[11]; + u32_t rxpf_rxpcq_ftq_cmd; + #define RXPF_RXPCQ_FTQ_CMD_RXPCQ_CMD_POP (1UL<<30) + u32_t unused_9; + + u32_t rxpf_rv2ppq_cid; + u32_t rxpf_rv2ppq_mbuf_cluster; + u16_t rxpf_rv2ppq_operand_flags; + u8_t rxpf_rv2ppq_knum; + u8_t rxpf_rv2ppq_opcode; + u16_t rxpf_rv2ppq_operand16_0; + u16_t rxpf_rv2ppq_operand16_1; + u16_t rxpf_rv2ppq_operand16_2; + u16_t rxpf_rv2ppq_operand16_3; + u16_t rxpf_rv2ppq_operand16_4; + u16_t rxpf_rv2ppq_operand16_5; + u16_t rxpf_rv2ppq_operand16_6; + u16_t rxpf_rv2ppq_operand16_7; + u32_t rxpf_rv2ppq_operand32_0; + u32_t rxpf_rv2ppq_operand32_1; + u32_t rxpf_rv2ppq_operand32_2; + u32_t rxpf_rv2ppq_operand32_3; + u32_t rxpf_rv2ppq_operand32_4; + u8_t rxpf_rv2ppq_rdma_action; + #define RXPF_RV2PPQ_RDMA_ACTION_CS16_VLD (1<<6) + #define RXPF_RV2PPQ_RDMA_ACTION_NO_SNOOP (1<<7) + + u8_t rxpf_rv2ppq_cs16_pkt_len; + #define RXPF_RV2PPQ_CS16_PKT_LEN_VALUE (0x7f<<0) + + u16_t rxpf_rv2ppq_cs16; + u32_t unused_10; + u32_t rxpf_rv2ppq_ftq_cmd; + #define RXPF_RV2PPQ_FTQ_CMD_CPY_DATA (1UL<<11) + #define RXPF_RV2PPQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define RXPF_RV2PPQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define RXPF_RV2PPQ_FTQ_CMD_BUSY (1UL<<31) + u32_t unused_11; + + u32_t rxpf_mcpq_bits_status; + u16_t rxpf_mcpq_pkt_len; + u16_t unused_12; + u32_t rxpf_mcpq_mbuf_cluster; + u32_t rxpf_mcpq_rx_errors; + u16_t rxpf_mcpq_ext_status; + u16_t unused_13; + u32_t unused_14[9]; + u32_t rxpf_mcpq_ftq_cmd; + #define RXPF_MCPQ_FTQ_CMD_CPY_DATA (1UL<<11) + #define RXPF_MCPQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define RXPF_MCPQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define RXPF_MCPQ_FTQ_CMD_BUSY (1UL<<31) + u32_t unused_15; + + u32_t rxpf_csq_cid; + u8_t rxpf_csq_flags; + u8_t unused_16; + u16_t unused_17; + u32_t unused_18[12]; + u32_t rxpf_csq_ftq_cmd; + #define RXPF_CSQ_FTQ_CMD_CPY_DATA (1UL<<11) + #define RXPF_CSQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define RXPF_CSQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define RXPF_CSQ_FTQ_CMD_BUSY (1UL<<31) + u32_t unused_19; + + u32_t rxpf_tschq_cid; + #define RXPF_TSCHQ_CID_VALUE (0x3fffUL<<7) + + u8_t rxpf_tschq_flags; + #define RXPF_TSCHQ_FLAGS_DELIST (1<<0) + #define RXPF_TSCHQ_FLAGS_NORMAL (1<<1) + #define RXPF_TSCHQ_FLAGS_HIGH (1<<2) + + u8_t rxpf_tschq_rsvd_future; + #define RXPF_TSCHQ_RSVD_FUTURE_VALUE (0x3<<0) + u16_t unused_20; + u32_t unused_21[12]; + + u32_t rxpf_tschq_ftq_cmd; + #define RXPF_TSCHQ_FTQ_CMD_CPY_DATA (1UL<<11) + #define RXPF_TSCHQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define RXPF_TSCHQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define RXPF_TSCHQ_FTQ_CMD_BUSY (1UL<<31) + u32_t unused_22[353]; + + u32_t rxpf_burst_base0; + #define RXPF_BURST_BASE0_BASE_VAL0 (0x3fffUL<<7) + + u32_t rxpf_burst_base1; + #define RXPF_BURST_BASE1_BASE_VAL1 (0x3fffUL<<7) + + u32_t rxpf_burst_base2; + #define RXPF_BURST_BASE2_BASE_VAL2 (0x3fffUL<<7) + + u32_t rxpf_burst_base3; + #define RXPF_BURST_BASE3_BASE_VAL3 (0x3fffUL<<7) + + u32_t rxpf_burst_cmd0; + #define RXPF_BURST_CMD0_FTQ_SEL (0x3UL<<0) + #define RXPF_BURST_CMD0_FTQ_SEL_0 (0UL<<0) + #define RXPF_BURST_CMD0_FTQ_SEL_1 (1UL<<0) + #define RXPF_BURST_CMD0_FTQ_SEL_2 (2UL<<0) + #define RXPF_BURST_CMD0_FTQ_SEL_3 (3UL<<0) + #define RXPF_BURST_CMD0_BUSY (1UL<<2) + #define RXPF_BURST_CMD0_OFFSET (0x1ffUL<<3) + #define RXPF_BURST_CMD0_BASE_REG_SEL (1UL<<23) + #define RXPF_BURST_CMD0_MOD_USAGE_CNT (0x3UL<<24) + #define RXPF_BURST_CMD0_MOD_USAGE_CNT_00 (0UL<<24) + #define RXPF_BURST_CMD0_MOD_USAGE_CNT_01 (1UL<<24) + #define RXPF_BURST_CMD0_MOD_USAGE_CNT_10 (2UL<<24) + #define RXPF_BURST_CMD0_MOD_USAGE_CNT_11 (3UL<<24) + #define RXPF_BURST_CMD0_PREFETCH_SIZE (0x3UL<<26) + #define RXPF_BURST_CMD0_NO_RAM_ACCESS (1UL<<28) + #define RXPF_BURST_CMD0_NO_CACHE (1UL<<29) + #define RXPF_BURST_CMD0_CROSS_BOUNDARY (1UL<<30) + + u32_t rxpf_burst_cmd1; + #define RXPF_BURST_CMD1_FTQ_SEL (0x3UL<<0) + #define RXPF_BURST_CMD1_FTQ_SEL_0 (0UL<<0) + #define RXPF_BURST_CMD1_FTQ_SEL_1 (1UL<<0) + #define RXPF_BURST_CMD1_FTQ_SEL_2 (2UL<<0) + #define RXPF_BURST_CMD1_FTQ_SEL_3 (3UL<<0) + #define RXPF_BURST_CMD1_BUSY (1UL<<2) + #define RXPF_BURST_CMD1_OFFSET (0x1ffUL<<3) + #define RXPF_BURST_CMD1_BASE_REG_SEL (1UL<<23) + #define RXPF_BURST_CMD1_MOD_USAGE_CNT (0x3UL<<24) + #define RXPF_BURST_CMD1_MOD_USAGE_CNT_00 (0UL<<24) + #define RXPF_BURST_CMD1_MOD_USAGE_CNT_01 (1UL<<24) + #define RXPF_BURST_CMD1_MOD_USAGE_CNT_10 (2UL<<24) + #define RXPF_BURST_CMD1_MOD_USAGE_CNT_11 (3UL<<24) + #define RXPF_BURST_CMD1_PREFETCH_SIZE (0x3UL<<26) + #define RXPF_BURST_CMD1_NO_RAM_ACCESS (1UL<<28) + #define RXPF_BURST_CMD1_NO_CACHE (1UL<<29) + #define RXPF_BURST_CMD1_CROSS_BOUNDARY (1UL<<30) + + u32_t rxpf_burst_cmd2; + #define RXPF_BURST_CMD2_FTQ_SEL (0x3UL<<0) + #define RXPF_BURST_CMD2_FTQ_SEL_0 (0UL<<0) + #define RXPF_BURST_CMD2_FTQ_SEL_1 (1UL<<0) + #define RXPF_BURST_CMD2_FTQ_SEL_2 (2UL<<0) + #define RXPF_BURST_CMD2_FTQ_SEL_3 (3UL<<0) + #define RXPF_BURST_CMD2_BUSY (1UL<<2) + #define RXPF_BURST_CMD2_OFFSET (0x1ffUL<<3) + #define RXPF_BURST_CMD2_BASE_REG_SEL (1UL<<23) + #define RXPF_BURST_CMD2_MOD_USAGE_CNT (0x3UL<<24) + #define RXPF_BURST_CMD2_MOD_USAGE_CNT_00 (0UL<<24) + #define RXPF_BURST_CMD2_MOD_USAGE_CNT_01 (1UL<<24) + #define RXPF_BURST_CMD2_MOD_USAGE_CNT_10 (2UL<<24) + #define RXPF_BURST_CMD2_MOD_USAGE_CNT_11 (3UL<<24) + #define RXPF_BURST_CMD2_PREFETCH_SIZE (0x3UL<<26) + #define RXPF_BURST_CMD2_NO_RAM_ACCESS (1UL<<28) + #define RXPF_BURST_CMD2_NO_CACHE (1UL<<29) + #define RXPF_BURST_CMD2_CROSS_BOUNDARY (1UL<<30) + + u32_t rxpf_burst_cmd3; + #define RXPF_BURST_CMD3_FTQ_SEL (0x3UL<<0) + #define RXPF_BURST_CMD3_FTQ_SEL_0 (0UL<<0) + #define RXPF_BURST_CMD3_FTQ_SEL_1 (1UL<<0) + #define RXPF_BURST_CMD3_FTQ_SEL_2 (2UL<<0) + #define RXPF_BURST_CMD3_FTQ_SEL_3 (3UL<<0) + #define RXPF_BURST_CMD3_BUSY (1UL<<2) + #define RXPF_BURST_CMD3_OFFSET (0x1ffUL<<3) + #define RXPF_BURST_CMD3_BASE_REG_SEL (1UL<<23) + #define RXPF_BURST_CMD3_MOD_USAGE_CNT (0x3UL<<24) + #define RXPF_BURST_CMD3_MOD_USAGE_CNT_00 (0UL<<24) + #define RXPF_BURST_CMD3_MOD_USAGE_CNT_01 (1UL<<24) + #define RXPF_BURST_CMD3_MOD_USAGE_CNT_10 (2UL<<24) + #define RXPF_BURST_CMD3_MOD_USAGE_CNT_11 (3UL<<24) + #define RXPF_BURST_CMD3_PREFETCH_SIZE (0x3UL<<26) + #define RXPF_BURST_CMD3_NO_RAM_ACCESS (1UL<<28) + #define RXPF_BURST_CMD3_NO_CACHE (1UL<<29) + #define RXPF_BURST_CMD3_CROSS_BOUNDARY (1UL<<30) + + u32_t rxpf_burst_cmd4; + #define RXPF_BURST_CMD4_FTQ_SEL (0x3UL<<0) + #define RXPF_BURST_CMD4_FTQ_SEL_0 (0UL<<0) + #define RXPF_BURST_CMD4_FTQ_SEL_1 (1UL<<0) + #define RXPF_BURST_CMD4_FTQ_SEL_2 (2UL<<0) + #define RXPF_BURST_CMD4_FTQ_SEL_3 (3UL<<0) + #define RXPF_BURST_CMD4_BUSY (1UL<<2) + #define RXPF_BURST_CMD4_OFFSET (0x1ffUL<<3) + #define RXPF_BURST_CMD4_BASE_REG_SEL (1UL<<23) + #define RXPF_BURST_CMD4_MOD_USAGE_CNT (0x3UL<<24) + #define RXPF_BURST_CMD4_MOD_USAGE_CNT_00 (0UL<<24) + #define RXPF_BURST_CMD4_MOD_USAGE_CNT_01 (1UL<<24) + #define RXPF_BURST_CMD4_MOD_USAGE_CNT_10 (2UL<<24) + #define RXPF_BURST_CMD4_MOD_USAGE_CNT_11 (3UL<<24) + #define RXPF_BURST_CMD4_PREFETCH_SIZE (0x3UL<<26) + #define RXPF_BURST_CMD4_NO_RAM_ACCESS (1UL<<28) + #define RXPF_BURST_CMD4_NO_CACHE (1UL<<29) + #define RXPF_BURST_CMD4_CROSS_BOUNDARY (1UL<<30) + + u32_t rxpf_burst_cmd5; + #define RXPF_BURST_CMD5_FTQ_SEL (0x3UL<<0) + #define RXPF_BURST_CMD5_FTQ_SEL_0 (0UL<<0) + #define RXPF_BURST_CMD5_FTQ_SEL_1 (1UL<<0) + #define RXPF_BURST_CMD5_FTQ_SEL_2 (2UL<<0) + #define RXPF_BURST_CMD5_FTQ_SEL_3 (3UL<<0) + #define RXPF_BURST_CMD5_BUSY (1UL<<2) + #define RXPF_BURST_CMD5_OFFSET (0x1ffUL<<3) + #define RXPF_BURST_CMD5_BASE_REG_SEL (1UL<<23) + #define RXPF_BURST_CMD5_MOD_USAGE_CNT (0x3UL<<24) + #define RXPF_BURST_CMD5_MOD_USAGE_CNT_00 (0UL<<24) + #define RXPF_BURST_CMD5_MOD_USAGE_CNT_01 (1UL<<24) + #define RXPF_BURST_CMD5_MOD_USAGE_CNT_10 (2UL<<24) + #define RXPF_BURST_CMD5_MOD_USAGE_CNT_11 (3UL<<24) + #define RXPF_BURST_CMD5_PREFETCH_SIZE (0x3UL<<26) + #define RXPF_BURST_CMD5_NO_RAM_ACCESS (1UL<<28) + #define RXPF_BURST_CMD5_NO_CACHE (1UL<<29) + #define RXPF_BURST_CMD5_CROSS_BOUNDARY (1UL<<30) + + u32_t rxpf_burst_cmd6; + #define RXPF_BURST_CMD6_FTQ_SEL (0x3UL<<0) + #define RXPF_BURST_CMD6_FTQ_SEL_0 (0UL<<0) + #define RXPF_BURST_CMD6_FTQ_SEL_1 (1UL<<0) + #define RXPF_BURST_CMD6_FTQ_SEL_2 (2UL<<0) + #define RXPF_BURST_CMD6_FTQ_SEL_3 (3UL<<0) + #define RXPF_BURST_CMD6_BUSY (1UL<<2) + #define RXPF_BURST_CMD6_OFFSET (0x1ffUL<<3) + #define RXPF_BURST_CMD6_BASE_REG_SEL (1UL<<23) + #define RXPF_BURST_CMD6_MOD_USAGE_CNT (0x3UL<<24) + #define RXPF_BURST_CMD6_MOD_USAGE_CNT_00 (0UL<<24) + #define RXPF_BURST_CMD6_MOD_USAGE_CNT_01 (1UL<<24) + #define RXPF_BURST_CMD6_MOD_USAGE_CNT_10 (2UL<<24) + #define RXPF_BURST_CMD6_MOD_USAGE_CNT_11 (3UL<<24) + #define RXPF_BURST_CMD6_PREFETCH_SIZE (0x3UL<<26) + #define RXPF_BURST_CMD6_NO_RAM_ACCESS (1UL<<28) + #define RXPF_BURST_CMD6_NO_CACHE (1UL<<29) + #define RXPF_BURST_CMD6_CROSS_BOUNDARY (1UL<<30) + + u32_t rxpf_burst_cmd7; + #define RXPF_BURST_CMD7_FTQ_SEL (0x3UL<<0) + #define RXPF_BURST_CMD7_FTQ_SEL_0 (0UL<<0) + #define RXPF_BURST_CMD7_FTQ_SEL_1 (1UL<<0) + #define RXPF_BURST_CMD7_FTQ_SEL_2 (2UL<<0) + #define RXPF_BURST_CMD7_FTQ_SEL_3 (3UL<<0) + #define RXPF_BURST_CMD7_BUSY (1UL<<2) + #define RXPF_BURST_CMD7_OFFSET (0x1ffUL<<3) + #define RXPF_BURST_CMD7_BASE_REG_SEL (1UL<<23) + #define RXPF_BURST_CMD7_MOD_USAGE_CNT (0x3UL<<24) + #define RXPF_BURST_CMD7_MOD_USAGE_CNT_00 (0UL<<24) + #define RXPF_BURST_CMD7_MOD_USAGE_CNT_01 (1UL<<24) + #define RXPF_BURST_CMD7_MOD_USAGE_CNT_10 (2UL<<24) + #define RXPF_BURST_CMD7_MOD_USAGE_CNT_11 (3UL<<24) + #define RXPF_BURST_CMD7_PREFETCH_SIZE (0x3UL<<26) + #define RXPF_BURST_CMD7_NO_RAM_ACCESS (1UL<<28) + #define RXPF_BURST_CMD7_NO_CACHE (1UL<<29) + #define RXPF_BURST_CMD7_CROSS_BOUNDARY (1UL<<30) + + u32_t rxpf_ctx_cmd; + #define RXPF_CTX_CMD_NUM_BLOCKS (0x3UL<<0) + #define RXPF_CTX_CMD_OFFSET (0x1ffUL<<3) + #define RXPF_CTX_CMD_CID_VALUE (0x3fffUL<<12) + #define RXPF_CTX_CMD_PREFETCH_SIZE (0x3UL<<26) + #define RXPF_CTX_CMD_MOD_USAGE_CNT (0x3UL<<28) + #define RXPF_CTX_CMD_MOD_USAGE_CNT_00 (0UL<<28) + #define RXPF_CTX_CMD_MOD_USAGE_CNT_01 (1UL<<28) + #define RXPF_CTX_CMD_MOD_USAGE_CNT_10 (2UL<<28) + #define RXPF_CTX_CMD_MOD_USAGE_CNT_11 (3UL<<28) + u32_t unused_23[51]; + + u32_t rxpf_burst_data0[16]; + u32_t rxpf_burst_data1[16]; + u32_t rxpf_burst_data2[16]; + u32_t rxpf_burst_data3[16]; + u32_t rxpf_burst_data4[16]; + u32_t rxpf_burst_data5[16]; + u32_t rxpf_burst_data6[16]; + u32_t rxpf_burst_data7[16]; + u32_t unused_24[64]; + u32_t rxpf_rbuf_burst_data[32]; + u32_t unused_25[3296]; + u32_t rxpf_rx_mbuf[4096]; + u32_t unused_26[57344]; + u32_t rxpf_ctx_window5[32768]; + u32_t rxpf_ctx_window6[32768]; + u32_t rxpf_ctx_window1[32768]; + u32_t rxpf_ctx_window2[32768]; + u32_t rxpf_ctx_window3[32768]; + u32_t rxpf_ctx_window4[32768]; +} rxp_fio_xi_t; + + +/* + * com_fio definition + * offset: 0x80000000 + */ +typedef struct com_fio +{ + u32_t comf_events_bits; + #define COMF_EVENTS_BITS_GPIO0 (1UL<<15) + #define COMF_EVENTS_BITS_GPIO1 (1UL<<16) + #define COMF_EVENTS_BITS_GPIO2 (1UL<<17) + #define COMF_EVENTS_BITS_GPIO3 (1UL<<18) + + u32_t comf_attentions_bits; + #define COMF_ATTENTIONS_BITS_EPB_ERROR (1UL<<30) + + u32_t comf_event_enable; + u32_t comf_attention_enable; + u32_t comf_fio_status; + + u32_t comf_mult_result; + u32_t comf_mult_a; + + u32_t comf_mult_b; + + u32_t comf_ctx_window_cid1; + + u32_t comf_ctx_window_cid2; + #define COMF_CTX_WINDOW_CID2_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) + + u32_t comf_ctx_window_cid3; + #define COMF_CTX_WINDOW_CID3_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) + + u32_t comf_ctx_window_cid4; + #define COMF_CTX_WINDOW_CID4_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) + + u32_t comf_dma_len; + #define COMF_DMA_LEN_BYTE_SWAP (1UL<<24) + + u32_t comf_dma_status; + #define COMF_DMA_STATUS_WRITE_MASTER_ABORT (1UL<<3) + #define COMF_DMA_STATUS_READ_MASTER_ABORT (1UL<<20) + + u32_t comf_dma_addr_h; + u32_t comf_dma_addr_l; + u32_t comf_com_hc_inc_stat[12]; + u32_t comf_free_counter_value; + u32_t comf_timer_retran_value; + u16_t comf_timer_rxpush_value; + u16_t comf_timer_delayack_value; + u16_t comf_timer_keepalive_value; + u16_t comf_timer_nagle_value; + u16_t comf_com_hc_rx_quick_cons_idx[16]; + u16_t comf_com_hc_cmd; + #define COMF_COM_HC_CMD_COALESCE_NOW (1<<0) + + u16_t comf_com_hc_prod_idx; + u32_t comf_rbdc_flush; + + u32_t comf_com_rbuf_cluster; + u32_t unused_0[17]; + + u32_t comf_msi_req_value; + u32_t comf_msi_status; + #define COMF_MSI_STATUS_BUSY (1UL<<31) + + u32_t comf_msi_addr_h; + u32_t comf_msi_addr_l; + u32_t comf_comq_cid; + u32_t comf_comq_mbuf_cluster; + u16_t comf_comq_operand_flags; + u8_t comf_comq_knum; + u8_t comf_comq_opcode; + u16_t comf_comq_operand16_2; + u16_t comf_comq_operand16_3; + u16_t comf_comq_operand16_4; + u16_t comf_comq_operand16_5; + u16_t comf_comq_operand16_6; + u16_t comf_comq_operand16_7; + u32_t comf_comq_operand32_2; + u32_t comf_comq_operand32_3; + u32_t comf_comq_operand32_4; + u8_t comf_comq_rdma_action; + u8_t unused_1; + u16_t unused_2; + u32_t unused_3[4]; + u32_t comf_comq_ftq_cmd; + u32_t unused_4; + + u32_t comf_comtq_cid; + u32_t comf_comtq_val; + u8_t comf_comtq_type; + u8_t unused_5; + u16_t unused_6; + u32_t unused_7[11]; + u32_t comf_comtq_ftq_cmd; + u32_t unused_8; + + u32_t comf_comxq_cid; + u16_t comf_comxq_flags; + u16_t unused_9; + + u32_t comf_comxq_snd_next; + u32_t unused_10[11]; + u32_t comf_comxq_ftq_cmd; + u32_t unused_11; + + u32_t comf_tschq_cid; + u8_t comf_tschq_flags; + u8_t unused_12; + u16_t unused_13; + u32_t unused_14[12]; + + u32_t comf_tschq_ftq_cmd; + u32_t unused_15; + + u32_t comf_rv2ptq_cid; + u32_t unused_16[13]; + u32_t comf_rv2ptq_ftq_cmd; + u32_t unused_17; + + u32_t comf_csq_cid; + u8_t comf_csq_flags; + u8_t unused_18; + u16_t unused_19; + u32_t unused_20[12]; + + u32_t comf_csq_ftq_cmd; + u32_t unused_21; + + u32_t comf_mcpq_bits_status; + u16_t comf_mcpq_pkt_len; + u16_t unused_22; + u32_t comf_mcpq_mbuf_cluster; + u32_t unused_23[11]; + u32_t comf_mcpq_ftq_cmd; + u32_t unused_24[81]; + + u32_t comf_dma_data[128]; + u32_t unused_25[128]; + u32_t comf_burst_base0; + + u32_t comf_burst_base1; + + u32_t comf_burst_base2; + + u32_t comf_burst_base3; + + u32_t comf_burst_cmd0; + + u32_t comf_burst_cmd1; + + u32_t comf_burst_cmd2; + + u32_t comf_burst_cmd3; + u32_t unused_26[56]; + + u32_t comf_burst_data0[16]; + u32_t comf_burst_data1[16]; + u32_t comf_burst_data2[16]; + u32_t comf_burst_data3[16]; + u32_t unused_27[3456]; + u32_t comf_com_mbuf[4096]; + u32_t unused_28[122880]; + u32_t comf_ctx_window1[32768]; + u32_t comf_ctx_window2[32768]; + u32_t comf_ctx_window3[32768]; + u32_t comf_ctx_window4[32768]; +} com_fio_t; + + +/* + * com_fio definition + * offset: 0x80000000 + */ +typedef struct com_fio_xi +{ + u32_t comf_events_bits; + #define COMF_EVENTS_BITS_FTQ0_VALID (1UL<<0) + #define COMF_EVENTS_BITS_FTQ1_VALID (1UL<<1) + #define COMF_EVENTS_BITS_FTQ2_VALID (1UL<<2) + #define COMF_EVENTS_BITS_SCANNER_DONE (1UL<<3) + #define COMF_EVENTS_BITS_DMA_WR_DONE (1UL<<4) + #define COMF_EVENTS_BITS_DMA_RD_DONE (1UL<<5) + #define COMF_EVENTS_BITS_CRACKER_DONE (1UL<<6) + #define COMF_EVENTS_BITS_MULTIPLY_DONE (1UL<<7) + #define COMF_EVENTS_BITS_EXP_ROM (1UL<<8) + #define COMF_EVENTS_BITS_VPD (1UL<<9) + #define COMF_EVENTS_BITS_FLASH (1UL<<10) + #define COMF_EVENTS_BITS_SMB0 (1UL<<11) + #define COMF_EVENTS_BITS_RESERVED0 (1UL<<12) + #define COMF_EVENTS_BITS_RESERVED1 (1UL<<13) + #define COMF_EVENTS_BITS_RESERVED2 (1UL<<14) + #define COMF_EVENTS_BITS_GPIO (1UL<<15) + #define COMF_EVENTS_BITS_SW_TMR_1 (1UL<<19) + #define COMF_EVENTS_BITS_SW_TMR_2 (1UL<<20) + #define COMF_EVENTS_BITS_SW_TMR_3 (1UL<<21) + #define COMF_EVENTS_BITS_SW_TMR_4 (1UL<<22) + #define COMF_EVENTS_BITS_LINK_CHANGED (1UL<<23) + #define COMF_EVENTS_BITS_MI_INT (1UL<<25) + #define COMF_EVENTS_BITS_MI_COMPLETE (1UL<<26) + #define COMF_EVENTS_BITS_MAIN_PWR_INT (1UL<<27) + #define COMF_EVENTS_BITS_NOT_ENABLED (1UL<<30) + #define COMF_EVENTS_BITS_ATTENTIONS_VALID (1UL<<31) + + u32_t comf_attentions_bits; + #define COMF_ATTENTIONS_BITS_LINK_STATE (1UL<<0) + #define COMF_ATTENTIONS_BITS_TX_SCHEDULER_ABORT (1UL<<1) + #define COMF_ATTENTIONS_BITS_TX_BD_READ_ABORT (1UL<<2) + #define COMF_ATTENTIONS_BITS_TX_BD_CACHE_ABORT (1UL<<3) + #define COMF_ATTENTIONS_BITS_TX_PROCESSOR_ABORT (1UL<<4) + #define COMF_ATTENTIONS_BITS_TX_DMA_ABORT (1UL<<5) + #define COMF_ATTENTIONS_BITS_TX_PATCHUP_ABORT (1UL<<6) + #define COMF_ATTENTIONS_BITS_TX_ASSEMBLER_ABORT (1UL<<7) + #define COMF_ATTENTIONS_BITS_RX_PARSER_MAC_ABORT (1UL<<8) + #define COMF_ATTENTIONS_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) + #define COMF_ATTENTIONS_BITS_RX_MBUF_ABORT (1UL<<10) + #define COMF_ATTENTIONS_BITS_RX_LOOKUP_ABORT (1UL<<11) + #define COMF_ATTENTIONS_BITS_RX_PROCESSOR_ABORT (1UL<<12) + #define COMF_ATTENTIONS_BITS_RX_V2P_ABORT (1UL<<13) + #define COMF_ATTENTIONS_BITS_RX_BD_CACHE_ABORT (1UL<<14) + #define COMF_ATTENTIONS_BITS_RX_DMA_ABORT (1UL<<15) + #define COMF_ATTENTIONS_BITS_COMPLETION_ABORT (1UL<<16) + #define COMF_ATTENTIONS_BITS_HOST_COALESCE_ABORT (1UL<<17) + #define COMF_ATTENTIONS_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) + #define COMF_ATTENTIONS_BITS_CONTEXT_ABORT (1UL<<19) + #define COMF_ATTENTIONS_BITS_CMD_SCHEDULER_ABORT (1UL<<20) + #define COMF_ATTENTIONS_BITS_CMD_PROCESSOR_ABORT (1UL<<21) + #define COMF_ATTENTIONS_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) + #define COMF_ATTENTIONS_BITS_MAC_ABORT (1UL<<23) + #define COMF_ATTENTIONS_BITS_TIMER_ABORT (1UL<<24) + #define COMF_ATTENTIONS_BITS_DMAE_ABORT (1UL<<25) + #define COMF_ATTENTIONS_BITS_FLSH_ABORT (1UL<<26) + #define COMF_ATTENTIONS_BITS_GRC_ABORT (1UL<<27) + #define COMF_ATTENTIONS_BITS_PARITY_ERROR (1UL<<31) + + u32_t comf_event_enable; + u32_t comf_attention_enable; + u32_t comf_fio_status; + #define COMF_FIO_STATUS_ENABLED (1UL<<0) + #define COMF_FIO_STATUS_FORCE_ENA (1UL<<1) + + u32_t comf_mult_result; + u32_t comf_mult_a; + #define COMF_MULT_A_VALUE (0xffffUL<<0) + + u32_t comf_mult_b; + #define COMF_MULT_B_VALUE (0xffffUL<<0) + + u32_t comf_ctx_window_cid1; + #define COMF_CTX_WINDOW_CID1_LOCK_TYPE (0x7UL<<0) + #define COMF_CTX_WINDOW_CID1_LOCK_TYPE_VOID (0UL<<0) + #define COMF_CTX_WINDOW_CID1_LOCK_TYPE_PROTOCOL (1UL<<0) + #define COMF_CTX_WINDOW_CID1_LOCK_TYPE_TX (2UL<<0) + #define COMF_CTX_WINDOW_CID1_LOCK_TYPE_TIMER (4UL<<0) + #define COMF_CTX_WINDOW_CID1_LOCK_TYPE_COMPLETE (7UL<<0) + #define COMF_CTX_WINDOW_CID1_VALUE (0x3fffUL<<7) + #define COMF_CTX_WINDOW_CID1_MOD_USAGE_CNT (0x3UL<<24) + #define COMF_CTX_WINDOW_CID1_MOD_USAGE_CNT_00 (0UL<<24) + #define COMF_CTX_WINDOW_CID1_MOD_USAGE_CNT_01 (1UL<<24) + #define COMF_CTX_WINDOW_CID1_MOD_USAGE_CNT_10 (2UL<<24) + #define COMF_CTX_WINDOW_CID1_MOD_USAGE_CNT_11 (3UL<<24) + #define COMF_CTX_WINDOW_CID1_LOCK_GRANTED (1UL<<26) + #define COMF_CTX_WINDOW_CID1_LOCK_MODE (0x3UL<<27) + #define COMF_CTX_WINDOW_CID1_LOCK_MODE_UNLOCK (0UL<<27) + #define COMF_CTX_WINDOW_CID1_LOCK_MODE_IMMEDIATE (1UL<<27) + #define COMF_CTX_WINDOW_CID1_LOCK_MODE_SURE (2UL<<27) + #define COMF_CTX_WINDOW_CID1_NO_EXT_ACC (1UL<<29) + #define COMF_CTX_WINDOW_CID1_LOCK_STATUS (1UL<<30) + #define COMF_CTX_WINDOW_CID1_LOCK_REQ (1UL<<31) + + u32_t comf_ctx_window_cid2; + #define COMF_CTX_WINDOW_CID2_LOCK_TYPE (0x7UL<<0) + #define COMF_CTX_WINDOW_CID2_LOCK_TYPE_VOID (0UL<<0) + #define COMF_CTX_WINDOW_CID2_LOCK_TYPE_PROTOCOL (1UL<<0) + #define COMF_CTX_WINDOW_CID2_LOCK_TYPE_TX (2UL<<0) + #define COMF_CTX_WINDOW_CID2_LOCK_TYPE_TIMER (4UL<<0) + #define COMF_CTX_WINDOW_CID2_LOCK_TYPE_COMPLETE (7UL<<0) + #define COMF_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) + #define COMF_CTX_WINDOW_CID2_MOD_USAGE_CNT (0x3UL<<24) + #define COMF_CTX_WINDOW_CID2_MOD_USAGE_CNT_00 (0UL<<24) + #define COMF_CTX_WINDOW_CID2_MOD_USAGE_CNT_01 (1UL<<24) + #define COMF_CTX_WINDOW_CID2_MOD_USAGE_CNT_10 (2UL<<24) + #define COMF_CTX_WINDOW_CID2_MOD_USAGE_CNT_11 (3UL<<24) + #define COMF_CTX_WINDOW_CID2_LOCK_GRANTED (1UL<<26) + #define COMF_CTX_WINDOW_CID2_LOCK_MODE (0x3UL<<27) + #define COMF_CTX_WINDOW_CID2_LOCK_MODE_UNLOCK (0UL<<27) + #define COMF_CTX_WINDOW_CID2_LOCK_MODE_IMMEDIATE (1UL<<27) + #define COMF_CTX_WINDOW_CID2_LOCK_MODE_SURE (2UL<<27) + #define COMF_CTX_WINDOW_CID2_NO_EXT_ACC (1UL<<29) + #define COMF_CTX_WINDOW_CID2_LOCK_STATUS (1UL<<30) + #define COMF_CTX_WINDOW_CID2_LOCK_REQ (1UL<<31) + + u32_t comf_ctx_window_cid3; + #define COMF_CTX_WINDOW_CID3_LOCK_TYPE (0x7UL<<0) + #define COMF_CTX_WINDOW_CID3_LOCK_TYPE_VOID (0UL<<0) + #define COMF_CTX_WINDOW_CID3_LOCK_TYPE_PROTOCOL (1UL<<0) + #define COMF_CTX_WINDOW_CID3_LOCK_TYPE_TX (2UL<<0) + #define COMF_CTX_WINDOW_CID3_LOCK_TYPE_TIMER (4UL<<0) + #define COMF_CTX_WINDOW_CID3_LOCK_TYPE_COMPLETE (7UL<<0) + #define COMF_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) + #define COMF_CTX_WINDOW_CID3_MOD_USAGE_CNT (0x3UL<<24) + #define COMF_CTX_WINDOW_CID3_MOD_USAGE_CNT_00 (0UL<<24) + #define COMF_CTX_WINDOW_CID3_MOD_USAGE_CNT_01 (1UL<<24) + #define COMF_CTX_WINDOW_CID3_MOD_USAGE_CNT_10 (2UL<<24) + #define COMF_CTX_WINDOW_CID3_MOD_USAGE_CNT_11 (3UL<<24) + #define COMF_CTX_WINDOW_CID3_LOCK_GRANTED (1UL<<26) + #define COMF_CTX_WINDOW_CID3_LOCK_MODE (0x3UL<<27) + #define COMF_CTX_WINDOW_CID3_LOCK_MODE_UNLOCK (0UL<<27) + #define COMF_CTX_WINDOW_CID3_LOCK_MODE_IMMEDIATE (1UL<<27) + #define COMF_CTX_WINDOW_CID3_LOCK_MODE_SURE (2UL<<27) + #define COMF_CTX_WINDOW_CID3_NO_EXT_ACC (1UL<<29) + #define COMF_CTX_WINDOW_CID3_LOCK_STATUS (1UL<<30) + #define COMF_CTX_WINDOW_CID3_LOCK_REQ (1UL<<31) + + u32_t comf_ctx_window_cid4; + #define COMF_CTX_WINDOW_CID4_LOCK_TYPE (0x7UL<<0) + #define COMF_CTX_WINDOW_CID4_LOCK_TYPE_VOID (0UL<<0) + #define COMF_CTX_WINDOW_CID4_LOCK_TYPE_PROTOCOL (1UL<<0) + #define COMF_CTX_WINDOW_CID4_LOCK_TYPE_TX (2UL<<0) + #define COMF_CTX_WINDOW_CID4_LOCK_TYPE_TIMER (4UL<<0) + #define COMF_CTX_WINDOW_CID4_LOCK_TYPE_COMPLETE (7UL<<0) + #define COMF_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) + #define COMF_CTX_WINDOW_CID4_MOD_USAGE_CNT (0x3UL<<24) + #define COMF_CTX_WINDOW_CID4_MOD_USAGE_CNT_00 (0UL<<24) + #define COMF_CTX_WINDOW_CID4_MOD_USAGE_CNT_01 (1UL<<24) + #define COMF_CTX_WINDOW_CID4_MOD_USAGE_CNT_10 (2UL<<24) + #define COMF_CTX_WINDOW_CID4_MOD_USAGE_CNT_11 (3UL<<24) + #define COMF_CTX_WINDOW_CID4_LOCK_GRANTED (1UL<<26) + #define COMF_CTX_WINDOW_CID4_LOCK_MODE (0x3UL<<27) + #define COMF_CTX_WINDOW_CID4_LOCK_MODE_UNLOCK (0UL<<27) + #define COMF_CTX_WINDOW_CID4_LOCK_MODE_IMMEDIATE (1UL<<27) + #define COMF_CTX_WINDOW_CID4_LOCK_MODE_SURE (2UL<<27) + #define COMF_CTX_WINDOW_CID4_NO_EXT_ACC (1UL<<29) + #define COMF_CTX_WINDOW_CID4_LOCK_STATUS (1UL<<30) + #define COMF_CTX_WINDOW_CID4_LOCK_REQ (1UL<<31) + + u32_t comf_dma_len; + #define COMF_DMA_LEN_LEN (0x3ffUL<<0) + #define COMF_DMA_LEN_WRITE_START (1UL<<16) + #define COMF_DMA_LEN_WRITE_STOP (1UL<<17) + #define COMF_DMA_LEN_WRITE_EVENT_CLEAR (1UL<<18) + #define COMF_DMA_LEN_READ_START (1UL<<20) + #define COMF_DMA_LEN_READ_STOP (1UL<<21) + #define COMF_DMA_LEN_READ_EVENT_CLEAR (1UL<<22) + #define COMF_DMA_LEN_TYPE (0x3UL<<23) + #define COMF_DMA_LEN_TYPE_CONFIG (0UL<<23) + #define COMF_DMA_LEN_TYPE_DATA (1UL<<23) + #define COMF_DMA_LEN_TYPE_CONTROL (2UL<<23) + #define COMF_DMA_LEN_NO_SNOOP (1UL<<25) + #define COMF_DMA_LEN_PRIORITY (1UL<<26) + #define COMF_DMA_LEN_RELAXED_ORDERING (1UL<<27) + #define COMF_DMA_LEN_WRITE_RESET (1UL<<30) + #define COMF_DMA_LEN_READ_RESET (1UL<<31) + + u32_t comf_dma_status; + #define COMF_DMA_STATUS_WRITE_CHAN_REQ (1UL<<0) + #define COMF_DMA_STATUS_WRITE_ACTIVE (1UL<<1) + #define COMF_DMA_STATUS_WRITE_DONE (1UL<<2) + #define COMF_DMA_STATUS_READ_CHAN_REQ (1UL<<16) + #define COMF_DMA_STATUS_READ_ACTIVE (1UL<<17) + #define COMF_DMA_STATUS_READ_DONE (1UL<<19) + #define COMF_DMA_STATUS_READ_CS16_ERROR (1UL<<20) + + u32_t comf_dma_addr_h; + u32_t comf_dma_addr_l; + u32_t comf_com_hc_inc_stat[12]; + u32_t comf_free_counter_value; + u32_t comf_timer_retran_value; + u16_t comf_timer_rxpush_value; + u16_t comf_timer_delayack_value; + u16_t comf_timer_keepalive_value; + u16_t comf_timer_nagle_value; + u32_t comf_com_rx_quick_cons_idx; + #define COMF_COM_RX_QUICK_CONS_IDX_INDEX_VAL (0xffffUL<<0) + #define COMF_COM_RX_QUICK_CONS_IDX_INDEX_NUM (0xfUL<<20) + #define COMF_COM_RX_QUICK_CONS_IDX_COALESCE_NOW (1UL<<30) + #define COMF_COM_RX_QUICK_CONS_IDX_REQ_N (1UL<<31) + u32_t unused_0[3]; + + u32_t comf_ctx_window_cid5; + #define COMF_CTX_WINDOW_CID5_LOCK_TYPE (0x7UL<<0) + #define COMF_CTX_WINDOW_CID5_LOCK_TYPE_VOID (0UL<<0) + #define COMF_CTX_WINDOW_CID5_LOCK_TYPE_PROTOCOL (1UL<<0) + #define COMF_CTX_WINDOW_CID5_LOCK_TYPE_TX (2UL<<0) + #define COMF_CTX_WINDOW_CID5_LOCK_TYPE_TIMER (4UL<<0) + #define COMF_CTX_WINDOW_CID5_LOCK_TYPE_COMPLETE (7UL<<0) + #define COMF_CTX_WINDOW_CID5_VALUE (0x3fffUL<<7) + #define COMF_CTX_WINDOW_CID5_MOD_USAGE_CNT (0x3UL<<24) + #define COMF_CTX_WINDOW_CID5_MOD_USAGE_CNT_00 (0UL<<24) + #define COMF_CTX_WINDOW_CID5_MOD_USAGE_CNT_01 (1UL<<24) + #define COMF_CTX_WINDOW_CID5_MOD_USAGE_CNT_10 (2UL<<24) + #define COMF_CTX_WINDOW_CID5_MOD_USAGE_CNT_11 (3UL<<24) + #define COMF_CTX_WINDOW_CID5_LOCK_GRANTED (1UL<<26) + #define COMF_CTX_WINDOW_CID5_LOCK_MODE (0x3UL<<27) + #define COMF_CTX_WINDOW_CID5_LOCK_MODE_UNLOCK (0UL<<27) + #define COMF_CTX_WINDOW_CID5_LOCK_MODE_IMMEDIATE (1UL<<27) + #define COMF_CTX_WINDOW_CID5_LOCK_MODE_SURE (2UL<<27) + #define COMF_CTX_WINDOW_CID5_NO_EXT_ACC (1UL<<29) + #define COMF_CTX_WINDOW_CID5_LOCK_STATUS (1UL<<30) + #define COMF_CTX_WINDOW_CID5_LOCK_REQ (1UL<<31) + + u32_t comf_ctx_window_cid6; + #define COMF_CTX_WINDOW_CID6_LOCK_TYPE (0x7UL<<0) + #define COMF_CTX_WINDOW_CID6_LOCK_TYPE_VOID (0UL<<0) + #define COMF_CTX_WINDOW_CID6_LOCK_TYPE_PROTOCOL (1UL<<0) + #define COMF_CTX_WINDOW_CID6_LOCK_TYPE_TX (2UL<<0) + #define COMF_CTX_WINDOW_CID6_LOCK_TYPE_TIMER (4UL<<0) + #define COMF_CTX_WINDOW_CID6_LOCK_TYPE_COMPLETE (7UL<<0) + #define COMF_CTX_WINDOW_CID6_VALUE (0x3fffUL<<7) + #define COMF_CTX_WINDOW_CID6_MOD_USAGE_CNT (0x3UL<<24) + #define COMF_CTX_WINDOW_CID6_MOD_USAGE_CNT_00 (0UL<<24) + #define COMF_CTX_WINDOW_CID6_MOD_USAGE_CNT_01 (1UL<<24) + #define COMF_CTX_WINDOW_CID6_MOD_USAGE_CNT_10 (2UL<<24) + #define COMF_CTX_WINDOW_CID6_MOD_USAGE_CNT_11 (3UL<<24) + #define COMF_CTX_WINDOW_CID6_LOCK_GRANTED (1UL<<26) + #define COMF_CTX_WINDOW_CID6_LOCK_MODE (0x3UL<<27) + #define COMF_CTX_WINDOW_CID6_LOCK_MODE_UNLOCK (0UL<<27) + #define COMF_CTX_WINDOW_CID6_LOCK_MODE_IMMEDIATE (1UL<<27) + #define COMF_CTX_WINDOW_CID6_LOCK_MODE_SURE (2UL<<27) + #define COMF_CTX_WINDOW_CID6_NO_EXT_ACC (1UL<<29) + #define COMF_CTX_WINDOW_CID6_LOCK_STATUS (1UL<<30) + #define COMF_CTX_WINDOW_CID6_LOCK_REQ (1UL<<31) + u32_t unused_1[2]; + + u32_t comf_com_comp_prod_idx; + #define COMF_COM_COMP_PROD_IDX_INDEX_VAL (0xffffUL<<0) + #define COMF_COM_COMP_PROD_IDX_INDEX_NUM (0xfUL<<20) + #define COMF_COM_COMP_PROD_IDX_COALESCE_NOW (1UL<<30) + #define COMF_COM_COMP_PROD_IDX_REQ_N (1UL<<31) + + u32_t comf_rbdc_flush; + #define COMF_RBDC_FLUSH_TYPE (1UL<<0) + #define COMF_RBDC_FLUSH_CID (0x3fffUL<<7) + + u32_t comf_com_rbuf_cluster; + #define COMF_COM_RBUF_CLUSTER_COUNT (0x7fUL<<0) + #define COMF_COM_RBUF_CLUSTER_TAIL (0x1ffUL<<7) + #define COMF_COM_RBUF_CLUSTER_HEAD (0x1ffUL<<16) + #define COMF_COM_RBUF_CLUSTER_TYPE (1UL<<25) + #define COMF_COM_RBUF_CLUSTER_FREE (1UL<<31) + u32_t unused_2[21]; + + const u32_t comf_comq_cid; + const u32_t comf_comq_mbuf_cluster; + const u16_t comf_comq_operand_flags; + const u8_t comf_comq_knum; + const u8_t comf_comq_opcode; + const u16_t comf_comq_operand16_2; + const u16_t comf_comq_operand16_3; + const u16_t comf_comq_operand16_4; + const u16_t comf_comq_operand16_5; + const u16_t comf_comq_operand16_6; + const u16_t comf_comq_operand16_7; + const u32_t comf_comq_operand32_2; + const u32_t comf_comq_operand32_3; + const u32_t comf_comq_operand32_4; + const u8_t comf_comq_rdma_action; + const u8_t comf_comq_cs16_pkt_len; + const u16_t comf_comq_cs16; + const u32_t unused_3[4]; + u32_t comf_comq_ftq_cmd; + #define COMF_COMQ_FTQ_CMD_POP (1UL<<30) + const u32_t unused_4; + + const u32_t comf_comtq_cid; + const u32_t comf_comtq_val; + const u8_t comf_comtq_type; + const u8_t comf_comtq_rsvd_future; + const u16_t unused_5; + const u32_t unused_6[11]; + u32_t comf_comtq_ftq_cmd; + #define COMF_COMTQ_FTQ_CMD_POP (1UL<<30) + const u32_t unused_7; + const u32_t comf_comxq_cid; + const u16_t comf_comxq_flags; + #define COMF_COMXQ_FLAGS_COMPLETE (1<<8) + #define COMF_COMXQ_FLAGS_RETRAN (1<<9) + const u16_t unused_8; + const u32_t comf_comxq_snd_next; + const u8_t comf_comxq_new_flags; + const u8_t unused_9; + const u16_t unused_10; + const u32_t unused_11[10]; + u32_t comf_comxq_ftq_cmd; + #define COMF_COMXQ_FTQ_CMD_POP (1UL<<30) + u32_t unused_12; + + u32_t comf_tschq_cid; + u8_t comf_tschq_flags; + #define COMF_TSCHQ_FLAGS_DELIST (1<<0) + #define COMF_TSCHQ_FLAGS_NORMAL (1<<1) + #define COMF_TSCHQ_FLAGS_HIGH (1<<2) + + u8_t comf_tschq_rsvd_future; + u16_t unused_13; + u32_t unused_14[12]; + u32_t comf_tschq_ftq_cmd; + #define COMF_TSCHQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define COMF_TSCHQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define COMF_TSCHQ_FTQ_CMD_BUSY (1UL<<31) + u32_t unused_15; + + u32_t comf_rv2ptq_cid; + u32_t unused_16[13]; + u32_t comf_rv2ptq_ftq_cmd; + #define COMF_RV2PTQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define COMF_RV2PTQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define COMF_RV2PTQ_FTQ_CMD_BUSY (1UL<<31) + u32_t unused_17; + + u32_t comf_csq_cid; + u8_t comf_csq_flags; + #define COMF_CSQ_FLAGS_DELIST (1<<0) + #define COMF_CSQ_FLAGS_NORMAL (1<<1) + #define COMF_CSQ_FLAGS_HIGH (1<<2) + u8_t unused_18; + u16_t unused_19; + u32_t unused_20[12]; + + u32_t comf_csq_ftq_cmd; + #define COMF_CSQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define COMF_CSQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define COMF_CSQ_FTQ_CMD_BUSY (1UL<<31) + u32_t unused_21; + + u32_t comf_mcpq_bits_status; + u16_t comf_mcpq_pkt_len; + u16_t comf_mcpq_vlan_tag; + u32_t comf_mcpq_mbuf_cluster; + u32_t comf_mcpq_rx_errors; + u16_t comf_mcpq_ext_status; + u16_t unused_23; + u32_t unused_24[9]; + u32_t comf_mcpq_ftq_cmd; + #define COMF_MCPQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define COMF_MCPQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define COMF_MCPQ_FTQ_CMD_BUSY (1UL<<31) + u32_t unused_25[81]; + + u32_t comf_dma_data[128]; + u32_t unused_26[128]; + u32_t comf_burst_base0; + #define COMF_BURST_BASE0_BASE_VAL0 (0x3fffUL<<7) + + u32_t comf_burst_base1; + #define COMF_BURST_BASE1_BASE_VAL1 (0x3fffUL<<7) + + u32_t comf_burst_base2; + #define COMF_BURST_BASE2_BASE_VAL2 (0x3fffUL<<7) + + u32_t comf_burst_base3; + #define COMF_BURST_BASE3_BASE_VAL3 (0x3fffUL<<7) + + u32_t comf_burst_cmd0; + #define COMF_BURST_CMD0_FTQ_SEL (0x3UL<<0) + #define COMF_BURST_CMD0_FTQ_SEL_0 (0UL<<0) + #define COMF_BURST_CMD0_FTQ_SEL_1 (1UL<<0) + #define COMF_BURST_CMD0_FTQ_SEL_2 (2UL<<0) + #define COMF_BURST_CMD0_FTQ_SEL_3 (3UL<<0) + #define COMF_BURST_CMD0_BUSY (1UL<<2) + #define COMF_BURST_CMD0_OFFSET (0x1ffUL<<3) + #define COMF_BURST_CMD0_BASE_REG_SEL (1UL<<23) + #define COMF_BURST_CMD0_MOD_USAGE_CNT (0x3UL<<24) + #define COMF_BURST_CMD0_MOD_USAGE_CNT_00 (0UL<<24) + #define COMF_BURST_CMD0_MOD_USAGE_CNT_01 (1UL<<24) + #define COMF_BURST_CMD0_MOD_USAGE_CNT_10 (2UL<<24) + #define COMF_BURST_CMD0_MOD_USAGE_CNT_11 (3UL<<24) + #define COMF_BURST_CMD0_PREFETCH_SIZE (0x3UL<<26) + #define COMF_BURST_CMD0_NO_RAM_ACCESS (1UL<<28) + #define COMF_BURST_CMD0_NO_CACHE (1UL<<29) + #define COMF_BURST_CMD0_CROSS_BOUNDARY (1UL<<30) + + u32_t comf_burst_cmd1; + #define COMF_BURST_CMD1_FTQ_SEL (0x3UL<<0) + #define COMF_BURST_CMD1_FTQ_SEL_0 (0UL<<0) + #define COMF_BURST_CMD1_FTQ_SEL_1 (1UL<<0) + #define COMF_BURST_CMD1_FTQ_SEL_2 (2UL<<0) + #define COMF_BURST_CMD1_FTQ_SEL_3 (3UL<<0) + #define COMF_BURST_CMD1_BUSY (1UL<<2) + #define COMF_BURST_CMD1_OFFSET (0x1ffUL<<3) + #define COMF_BURST_CMD1_BASE_REG_SEL (1UL<<23) + #define COMF_BURST_CMD1_MOD_USAGE_CNT (0x3UL<<24) + #define COMF_BURST_CMD1_MOD_USAGE_CNT_00 (0UL<<24) + #define COMF_BURST_CMD1_MOD_USAGE_CNT_01 (1UL<<24) + #define COMF_BURST_CMD1_MOD_USAGE_CNT_10 (2UL<<24) + #define COMF_BURST_CMD1_MOD_USAGE_CNT_11 (3UL<<24) + #define COMF_BURST_CMD1_PREFETCH_SIZE (0x3UL<<26) + #define COMF_BURST_CMD1_NO_RAM_ACCESS (1UL<<28) + #define COMF_BURST_CMD1_NO_CACHE (1UL<<29) + #define COMF_BURST_CMD1_CROSS_BOUNDARY (1UL<<30) + + u32_t comf_burst_cmd2; + #define COMF_BURST_CMD2_FTQ_SEL (0x3UL<<0) + #define COMF_BURST_CMD2_FTQ_SEL_0 (0UL<<0) + #define COMF_BURST_CMD2_FTQ_SEL_1 (1UL<<0) + #define COMF_BURST_CMD2_FTQ_SEL_2 (2UL<<0) + #define COMF_BURST_CMD2_FTQ_SEL_3 (3UL<<0) + #define COMF_BURST_CMD2_BUSY (1UL<<2) + #define COMF_BURST_CMD2_OFFSET (0x1ffUL<<3) + #define COMF_BURST_CMD2_BASE_REG_SEL (1UL<<23) + #define COMF_BURST_CMD2_MOD_USAGE_CNT (0x3UL<<24) + #define COMF_BURST_CMD2_MOD_USAGE_CNT_00 (0UL<<24) + #define COMF_BURST_CMD2_MOD_USAGE_CNT_01 (1UL<<24) + #define COMF_BURST_CMD2_MOD_USAGE_CNT_10 (2UL<<24) + #define COMF_BURST_CMD2_MOD_USAGE_CNT_11 (3UL<<24) + #define COMF_BURST_CMD2_PREFETCH_SIZE (0x3UL<<26) + #define COMF_BURST_CMD2_NO_RAM_ACCESS (1UL<<28) + #define COMF_BURST_CMD2_NO_CACHE (1UL<<29) + #define COMF_BURST_CMD2_CROSS_BOUNDARY (1UL<<30) + + u32_t comf_burst_cmd3; + #define COMF_BURST_CMD3_FTQ_SEL (0x3UL<<0) + #define COMF_BURST_CMD3_FTQ_SEL_0 (0UL<<0) + #define COMF_BURST_CMD3_FTQ_SEL_1 (1UL<<0) + #define COMF_BURST_CMD3_FTQ_SEL_2 (2UL<<0) + #define COMF_BURST_CMD3_FTQ_SEL_3 (3UL<<0) + #define COMF_BURST_CMD3_BUSY (1UL<<2) + #define COMF_BURST_CMD3_OFFSET (0x1ffUL<<3) + #define COMF_BURST_CMD3_BASE_REG_SEL (1UL<<23) + #define COMF_BURST_CMD3_MOD_USAGE_CNT (0x3UL<<24) + #define COMF_BURST_CMD3_MOD_USAGE_CNT_00 (0UL<<24) + #define COMF_BURST_CMD3_MOD_USAGE_CNT_01 (1UL<<24) + #define COMF_BURST_CMD3_MOD_USAGE_CNT_10 (2UL<<24) + #define COMF_BURST_CMD3_MOD_USAGE_CNT_11 (3UL<<24) + #define COMF_BURST_CMD3_PREFETCH_SIZE (0x3UL<<26) + #define COMF_BURST_CMD3_NO_RAM_ACCESS (1UL<<28) + #define COMF_BURST_CMD3_NO_CACHE (1UL<<29) + #define COMF_BURST_CMD3_CROSS_BOUNDARY (1UL<<30) + u32_t unused_27[4]; + + u32_t comf_ctx_cmd; + #define COMF_CTX_CMD_NUM_BLOCKS (0x3UL<<0) + #define COMF_CTX_CMD_OFFSET (0x1ffUL<<3) + #define COMF_CTX_CMD_CID_VALUE (0x3fffUL<<12) + #define COMF_CTX_CMD_PREFETCH_SIZE (0x3UL<<26) + #define COMF_CTX_CMD_MOD_USAGE_CNT (0x3UL<<28) + #define COMF_CTX_CMD_MOD_USAGE_CNT_00 (0UL<<28) + #define COMF_CTX_CMD_MOD_USAGE_CNT_01 (1UL<<28) + #define COMF_CTX_CMD_MOD_USAGE_CNT_10 (2UL<<28) + #define COMF_CTX_CMD_MOD_USAGE_CNT_11 (3UL<<28) + u32_t unused_28[51]; + + u32_t comf_burst_data0[16]; + u32_t comf_burst_data1[16]; + u32_t comf_burst_data2[16]; + u32_t comf_burst_data3[16]; + u32_t unused_29[64896]; + u32_t comf_ctx_window5[32768]; + u32_t comf_ctx_window6[32768]; + u32_t comf_ctx_window1[32768]; + u32_t comf_ctx_window2[32768]; + u32_t comf_ctx_window3[32768]; + u32_t comf_ctx_window4[32768]; +} com_fio_xi_t; + + +/* + * cp_fio definition + * offset: 0x80000000 + */ +typedef struct cp_fio +{ + u32_t cpf_events_bits; + #define CPF_EVENTS_BITS_GPIO0 (1UL<<15) + #define CPF_EVENTS_BITS_GPIO1 (1UL<<16) + #define CPF_EVENTS_BITS_GPIO2 (1UL<<17) + #define CPF_EVENTS_BITS_GPIO3 (1UL<<18) + + u32_t cpf_attentions_bits; + #define CPF_ATTENTIONS_BITS_EPB_ERROR (1UL<<30) + + u32_t cpf_event_enable; + u32_t cpf_attention_enable; + u32_t cpf_fio_status; + + u32_t cpf_mult_result; + u32_t cpf_mult_a; + + u32_t cpf_mult_b; + + u32_t cpf_ctx_window_cid1; + + u32_t cpf_ctx_window_cid2; + #define CPF_CTX_WINDOW_CID2_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) + + u32_t cpf_ctx_window_cid3; + #define CPF_CTX_WINDOW_CID3_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) + + u32_t cpf_ctx_window_cid4; + #define CPF_CTX_WINDOW_CID4_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) + + u32_t cpf_dma_len; + #define CPF_DMA_LEN_BYTE_SWAP (1UL<<24) + + u32_t cpf_dma_status; + #define CPF_DMA_STATUS_WRITE_MASTER_ABORT (1UL<<3) + #define CPF_DMA_STATUS_READ_MASTER_ABORT (1UL<<20) + + u32_t cpf_dma_addr_h; + u32_t cpf_dma_addr_l; + u32_t cpf_cp_hc_inc_stat[8]; + u32_t unused_0[4]; + u32_t cpf_free_counter_value; + u32_t cpf_timer_retran_value; + u16_t cpf_timer_rxpush_value; + u16_t cpf_timer_delayack_value; + u16_t cpf_timer_keepalive_value; + u16_t cpf_timer_nagle_value; + u16_t cpf_cp_hc_cons_idx; + u16_t cpf_cp_hc_cmd; + #define CPF_CP_HC_CMD_COALESCE_NOW (1<<0) + u32_t unused_1[31]; + + u32_t cpf_cpq_cid; + u32_t cpf_cpq_val; + u8_t cpf_cpq_type; + u8_t unused_2; + u16_t unused_3; + u32_t unused_4[11]; + u32_t cpf_cpq_ftq_cmd; + u32_t unused_5; + + u32_t cpf_tschq_cid; + u8_t cpf_tschq_flags; + u8_t unused_6; + u16_t unused_7; + u32_t unused_8[12]; + + u32_t cpf_tschq_ftq_cmd; + u32_t unused_9; + + u32_t cpf_rxpcq_cid; + u32_t cpf_rxpcq_generic1; + u32_t cpf_rxpcq_generic2; + u32_t unused_10[11]; + u32_t cpf_rxpcq_ftq_cmd; + u32_t unused_11[145]; + + u32_t cpf_dma_data[128]; + u32_t unused_12[128]; + u32_t cpf_burst_base0; + + u32_t cpf_burst_base1; + + u32_t cpf_burst_base2; + + u32_t cpf_burst_base3; + + u32_t cpf_burst_cmd0; + + u32_t cpf_burst_cmd1; + + u32_t cpf_burst_cmd2; + + u32_t cpf_burst_cmd3; + u32_t unused_13[56]; + + u32_t cpf_burst_data0[16]; + u32_t cpf_burst_data1[16]; + u32_t cpf_burst_data2[16]; + u32_t cpf_burst_data3[16]; + u32_t unused_14[130432]; + u32_t cpf_ctx_window1[32768]; + u32_t cpf_ctx_window2[32768]; + u32_t cpf_ctx_window3[32768]; + u32_t cpf_ctx_window4[32768]; +} cp_fio_t; + + +/* + * cp_fio definition + * offset: 0x80000000 + */ +typedef struct cp_fio_xi +{ + u32_t cpf_events_bits; + #define CPF_EVENTS_BITS_FTQ0_VALID (1UL<<0) + #define CPF_EVENTS_BITS_FTQ1_VALID (1UL<<1) + #define CPF_EVENTS_BITS_FTQ2_VALID (1UL<<2) + #define CPF_EVENTS_BITS_SCANNER_DONE (1UL<<3) + #define CPF_EVENTS_BITS_DMA_WR_DONE (1UL<<4) + #define CPF_EVENTS_BITS_DMA_RD_DONE (1UL<<5) + #define CPF_EVENTS_BITS_CRACKER_DONE (1UL<<6) + #define CPF_EVENTS_BITS_MULTIPLY_DONE (1UL<<7) + #define CPF_EVENTS_BITS_EXP_ROM (1UL<<8) + #define CPF_EVENTS_BITS_VPD (1UL<<9) + #define CPF_EVENTS_BITS_FLASH (1UL<<10) + #define CPF_EVENTS_BITS_SMB0 (1UL<<11) + #define CPF_EVENTS_BITS_RESERVED0 (1UL<<12) + #define CPF_EVENTS_BITS_RESERVED1 (1UL<<13) + #define CPF_EVENTS_BITS_RESERVED2 (1UL<<14) + #define CPF_EVENTS_BITS_GPIO (1UL<<15) + #define CPF_EVENTS_BITS_SW_TMR_1 (1UL<<19) + #define CPF_EVENTS_BITS_SW_TMR_2 (1UL<<20) + #define CPF_EVENTS_BITS_SW_TMR_3 (1UL<<21) + #define CPF_EVENTS_BITS_SW_TMR_4 (1UL<<22) + #define CPF_EVENTS_BITS_LINK_CHANGED (1UL<<23) + #define CPF_EVENTS_BITS_MI_INT (1UL<<25) + #define CPF_EVENTS_BITS_MI_COMPLETE (1UL<<26) + #define CPF_EVENTS_BITS_MAIN_PWR_INT (1UL<<27) + #define CPF_EVENTS_BITS_NOT_ENABLED (1UL<<30) + #define CPF_EVENTS_BITS_ATTENTIONS_VALID (1UL<<31) + + u32_t cpf_attentions_bits; + #define CPF_ATTENTIONS_BITS_LINK_STATE (1UL<<0) + #define CPF_ATTENTIONS_BITS_TX_SCHEDULER_ABORT (1UL<<1) + #define CPF_ATTENTIONS_BITS_TX_BD_READ_ABORT (1UL<<2) + #define CPF_ATTENTIONS_BITS_TX_BD_CACHE_ABORT (1UL<<3) + #define CPF_ATTENTIONS_BITS_TX_PROCESSOR_ABORT (1UL<<4) + #define CPF_ATTENTIONS_BITS_TX_DMA_ABORT (1UL<<5) + #define CPF_ATTENTIONS_BITS_TX_PATCHUP_ABORT (1UL<<6) + #define CPF_ATTENTIONS_BITS_TX_ASSEMBLER_ABORT (1UL<<7) + #define CPF_ATTENTIONS_BITS_RX_PARSER_MAC_ABORT (1UL<<8) + #define CPF_ATTENTIONS_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) + #define CPF_ATTENTIONS_BITS_RX_MBUF_ABORT (1UL<<10) + #define CPF_ATTENTIONS_BITS_RX_LOOKUP_ABORT (1UL<<11) + #define CPF_ATTENTIONS_BITS_RX_PROCESSOR_ABORT (1UL<<12) + #define CPF_ATTENTIONS_BITS_RX_V2P_ABORT (1UL<<13) + #define CPF_ATTENTIONS_BITS_RX_BD_CACHE_ABORT (1UL<<14) + #define CPF_ATTENTIONS_BITS_RX_DMA_ABORT (1UL<<15) + #define CPF_ATTENTIONS_BITS_COMPLETION_ABORT (1UL<<16) + #define CPF_ATTENTIONS_BITS_HOST_COALESCE_ABORT (1UL<<17) + #define CPF_ATTENTIONS_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) + #define CPF_ATTENTIONS_BITS_CONTEXT_ABORT (1UL<<19) + #define CPF_ATTENTIONS_BITS_CMD_SCHEDULER_ABORT (1UL<<20) + #define CPF_ATTENTIONS_BITS_CMD_PROCESSOR_ABORT (1UL<<21) + #define CPF_ATTENTIONS_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) + #define CPF_ATTENTIONS_BITS_MAC_ABORT (1UL<<23) + #define CPF_ATTENTIONS_BITS_TIMER_ABORT (1UL<<24) + #define CPF_ATTENTIONS_BITS_DMAE_ABORT (1UL<<25) + #define CPF_ATTENTIONS_BITS_FLSH_ABORT (1UL<<26) + #define CPF_ATTENTIONS_BITS_GRC_ABORT (1UL<<27) + #define CPF_ATTENTIONS_BITS_PARITY_ERROR (1UL<<31) + + u32_t cpf_event_enable; + u32_t cpf_attention_enable; + u32_t cpf_fio_status; + #define CPF_FIO_STATUS_ENABLED (1UL<<0) + #define CPF_FIO_STATUS_FORCE_ENA (1UL<<1) + + u32_t cpf_mult_result; + u32_t cpf_mult_a; + #define CPF_MULT_A_VALUE (0xffffUL<<0) + + u32_t cpf_mult_b; + #define CPF_MULT_B_VALUE (0xffffUL<<0) + + u32_t cpf_ctx_window_cid1; + #define CPF_CTX_WINDOW_CID1_LOCK_TYPE (0x7UL<<0) + #define CPF_CTX_WINDOW_CID1_LOCK_TYPE_VOID (0UL<<0) + #define CPF_CTX_WINDOW_CID1_LOCK_TYPE_PROTOCOL (1UL<<0) + #define CPF_CTX_WINDOW_CID1_LOCK_TYPE_TX (2UL<<0) + #define CPF_CTX_WINDOW_CID1_LOCK_TYPE_TIMER (4UL<<0) + #define CPF_CTX_WINDOW_CID1_LOCK_TYPE_COMPLETE (7UL<<0) + #define CPF_CTX_WINDOW_CID1_VALUE (0x3fffUL<<7) + #define CPF_CTX_WINDOW_CID1_MOD_USAGE_CNT (0x3UL<<24) + #define CPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_00 (0UL<<24) + #define CPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_01 (1UL<<24) + #define CPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_10 (2UL<<24) + #define CPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_11 (3UL<<24) + #define CPF_CTX_WINDOW_CID1_LOCK_GRANTED (1UL<<26) + #define CPF_CTX_WINDOW_CID1_LOCK_MODE (0x3UL<<27) + #define CPF_CTX_WINDOW_CID1_LOCK_MODE_UNLOCK (0UL<<27) + #define CPF_CTX_WINDOW_CID1_LOCK_MODE_IMMEDIATE (1UL<<27) + #define CPF_CTX_WINDOW_CID1_LOCK_MODE_SURE (2UL<<27) + #define CPF_CTX_WINDOW_CID1_NO_EXT_ACC (1UL<<29) + #define CPF_CTX_WINDOW_CID1_LOCK_STATUS (1UL<<30) + #define CPF_CTX_WINDOW_CID1_LOCK_REQ (1UL<<31) + + u32_t cpf_ctx_window_cid2; + #define CPF_CTX_WINDOW_CID2_LOCK_TYPE (0x7UL<<0) + #define CPF_CTX_WINDOW_CID2_LOCK_TYPE_VOID (0UL<<0) + #define CPF_CTX_WINDOW_CID2_LOCK_TYPE_PROTOCOL (1UL<<0) + #define CPF_CTX_WINDOW_CID2_LOCK_TYPE_TX (2UL<<0) + #define CPF_CTX_WINDOW_CID2_LOCK_TYPE_TIMER (4UL<<0) + #define CPF_CTX_WINDOW_CID2_LOCK_TYPE_COMPLETE (7UL<<0) + #define CPF_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) + #define CPF_CTX_WINDOW_CID2_MOD_USAGE_CNT (0x3UL<<24) + #define CPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_00 (0UL<<24) + #define CPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_01 (1UL<<24) + #define CPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_10 (2UL<<24) + #define CPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_11 (3UL<<24) + #define CPF_CTX_WINDOW_CID2_LOCK_GRANTED (1UL<<26) + #define CPF_CTX_WINDOW_CID2_LOCK_MODE (0x3UL<<27) + #define CPF_CTX_WINDOW_CID2_LOCK_MODE_UNLOCK (0UL<<27) + #define CPF_CTX_WINDOW_CID2_LOCK_MODE_IMMEDIATE (1UL<<27) + #define CPF_CTX_WINDOW_CID2_LOCK_MODE_SURE (2UL<<27) + #define CPF_CTX_WINDOW_CID2_NO_EXT_ACC (1UL<<29) + #define CPF_CTX_WINDOW_CID2_LOCK_STATUS (1UL<<30) + #define CPF_CTX_WINDOW_CID2_LOCK_REQ (1UL<<31) + + u32_t cpf_ctx_window_cid3; + #define CPF_CTX_WINDOW_CID3_LOCK_TYPE (0x7UL<<0) + #define CPF_CTX_WINDOW_CID3_LOCK_TYPE_VOID (0UL<<0) + #define CPF_CTX_WINDOW_CID3_LOCK_TYPE_PROTOCOL (1UL<<0) + #define CPF_CTX_WINDOW_CID3_LOCK_TYPE_TX (2UL<<0) + #define CPF_CTX_WINDOW_CID3_LOCK_TYPE_TIMER (4UL<<0) + #define CPF_CTX_WINDOW_CID3_LOCK_TYPE_COMPLETE (7UL<<0) + #define CPF_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) + #define CPF_CTX_WINDOW_CID3_MOD_USAGE_CNT (0x3UL<<24) + #define CPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_00 (0UL<<24) + #define CPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_01 (1UL<<24) + #define CPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_10 (2UL<<24) + #define CPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_11 (3UL<<24) + #define CPF_CTX_WINDOW_CID3_LOCK_GRANTED (1UL<<26) + #define CPF_CTX_WINDOW_CID3_LOCK_MODE (0x3UL<<27) + #define CPF_CTX_WINDOW_CID3_LOCK_MODE_UNLOCK (0UL<<27) + #define CPF_CTX_WINDOW_CID3_LOCK_MODE_IMMEDIATE (1UL<<27) + #define CPF_CTX_WINDOW_CID3_LOCK_MODE_SURE (2UL<<27) + #define CPF_CTX_WINDOW_CID3_NO_EXT_ACC (1UL<<29) + #define CPF_CTX_WINDOW_CID3_LOCK_STATUS (1UL<<30) + #define CPF_CTX_WINDOW_CID3_LOCK_REQ (1UL<<31) + + u32_t cpf_ctx_window_cid4; + #define CPF_CTX_WINDOW_CID4_LOCK_TYPE (0x7UL<<0) + #define CPF_CTX_WINDOW_CID4_LOCK_TYPE_VOID (0UL<<0) + #define CPF_CTX_WINDOW_CID4_LOCK_TYPE_PROTOCOL (1UL<<0) + #define CPF_CTX_WINDOW_CID4_LOCK_TYPE_TX (2UL<<0) + #define CPF_CTX_WINDOW_CID4_LOCK_TYPE_TIMER (4UL<<0) + #define CPF_CTX_WINDOW_CID4_LOCK_TYPE_COMPLETE (7UL<<0) + #define CPF_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) + #define CPF_CTX_WINDOW_CID4_MOD_USAGE_CNT (0x3UL<<24) + #define CPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_00 (0UL<<24) + #define CPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_01 (1UL<<24) + #define CPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_10 (2UL<<24) + #define CPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_11 (3UL<<24) + #define CPF_CTX_WINDOW_CID4_LOCK_GRANTED (1UL<<26) + #define CPF_CTX_WINDOW_CID4_LOCK_MODE (0x3UL<<27) + #define CPF_CTX_WINDOW_CID4_LOCK_MODE_UNLOCK (0UL<<27) + #define CPF_CTX_WINDOW_CID4_LOCK_MODE_IMMEDIATE (1UL<<27) + #define CPF_CTX_WINDOW_CID4_LOCK_MODE_SURE (2UL<<27) + #define CPF_CTX_WINDOW_CID4_NO_EXT_ACC (1UL<<29) + #define CPF_CTX_WINDOW_CID4_LOCK_STATUS (1UL<<30) + #define CPF_CTX_WINDOW_CID4_LOCK_REQ (1UL<<31) + + u32_t cpf_dma_len; + #define CPF_DMA_LEN_LEN (0x3ffUL<<0) + #define CPF_DMA_LEN_WRITE_START (1UL<<16) + #define CPF_DMA_LEN_WRITE_STOP (1UL<<17) + #define CPF_DMA_LEN_WRITE_EVENT_CLEAR (1UL<<18) + #define CPF_DMA_LEN_READ_START (1UL<<20) + #define CPF_DMA_LEN_READ_STOP (1UL<<21) + #define CPF_DMA_LEN_READ_EVENT_CLEAR (1UL<<22) + #define CPF_DMA_LEN_TYPE (0x3UL<<23) + #define CPF_DMA_LEN_TYPE_CONFIG (0UL<<23) + #define CPF_DMA_LEN_TYPE_DATA (1UL<<23) + #define CPF_DMA_LEN_TYPE_CONTROL (2UL<<23) + #define CPF_DMA_LEN_NO_SNOOP (1UL<<25) + #define CPF_DMA_LEN_PRIORITY (1UL<<26) + #define CPF_DMA_LEN_RELAXED_ORDERING (1UL<<27) + #define CPF_DMA_LEN_WRITE_RESET (1UL<<30) + #define CPF_DMA_LEN_READ_RESET (1UL<<31) + + u32_t cpf_dma_status; + #define CPF_DMA_STATUS_WRITE_CHAN_REQ (1UL<<0) + #define CPF_DMA_STATUS_WRITE_ACTIVE (1UL<<1) + #define CPF_DMA_STATUS_WRITE_DONE (1UL<<2) + #define CPF_DMA_STATUS_READ_CHAN_REQ (1UL<<16) + #define CPF_DMA_STATUS_READ_ACTIVE (1UL<<17) + #define CPF_DMA_STATUS_READ_DONE (1UL<<19) + #define CPF_DMA_STATUS_READ_CS16_ERROR (1UL<<20) + + u32_t cpf_dma_addr_h; + u32_t cpf_dma_addr_l; + u32_t cpf_cp_hc_inc_stat[8]; + u32_t unused_0[4]; + u32_t cpf_free_counter_value; + u32_t cpf_timer_retran_value; + u16_t cpf_timer_rxpush_value; + u16_t cpf_timer_delayack_value; + u16_t cpf_timer_keepalive_value; + u16_t cpf_timer_nagle_value; + u32_t cpf_cp_cmd_cons_idx; + #define CPF_CP_CMD_CONS_IDX_INDEX_VAL (0xffffUL<<0) + #define CPF_CP_CMD_CONS_IDX_INDEX_NUM (0xfUL<<20) + #define CPF_CP_CMD_CONS_IDX_COALESCE_NOW (1UL<<30) + #define CPF_CP_CMD_CONS_IDX_REQ_N (1UL<<31) + u32_t unused_1[3]; + + u32_t cpf_ctx_window_cid5; + #define CPF_CTX_WINDOW_CID5_LOCK_TYPE (0x7UL<<0) + #define CPF_CTX_WINDOW_CID5_LOCK_TYPE_VOID (0UL<<0) + #define CPF_CTX_WINDOW_CID5_LOCK_TYPE_PROTOCOL (1UL<<0) + #define CPF_CTX_WINDOW_CID5_LOCK_TYPE_TX (2UL<<0) + #define CPF_CTX_WINDOW_CID5_LOCK_TYPE_TIMER (4UL<<0) + #define CPF_CTX_WINDOW_CID5_LOCK_TYPE_COMPLETE (7UL<<0) + #define CPF_CTX_WINDOW_CID5_VALUE (0x3fffUL<<7) + #define CPF_CTX_WINDOW_CID5_MOD_USAGE_CNT (0x3UL<<24) + #define CPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_00 (0UL<<24) + #define CPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_01 (1UL<<24) + #define CPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_10 (2UL<<24) + #define CPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_11 (3UL<<24) + #define CPF_CTX_WINDOW_CID5_LOCK_GRANTED (1UL<<26) + #define CPF_CTX_WINDOW_CID5_LOCK_MODE (0x3UL<<27) + #define CPF_CTX_WINDOW_CID5_LOCK_MODE_UNLOCK (0UL<<27) + #define CPF_CTX_WINDOW_CID5_LOCK_MODE_IMMEDIATE (1UL<<27) + #define CPF_CTX_WINDOW_CID5_LOCK_MODE_SURE (2UL<<27) + #define CPF_CTX_WINDOW_CID5_NO_EXT_ACC (1UL<<29) + #define CPF_CTX_WINDOW_CID5_LOCK_STATUS (1UL<<30) + #define CPF_CTX_WINDOW_CID5_LOCK_REQ (1UL<<31) + + u32_t cpf_ctx_window_cid6; + #define CPF_CTX_WINDOW_CID6_LOCK_TYPE (0x7UL<<0) + #define CPF_CTX_WINDOW_CID6_LOCK_TYPE_VOID (0UL<<0) + #define CPF_CTX_WINDOW_CID6_LOCK_TYPE_PROTOCOL (1UL<<0) + #define CPF_CTX_WINDOW_CID6_LOCK_TYPE_TX (2UL<<0) + #define CPF_CTX_WINDOW_CID6_LOCK_TYPE_TIMER (4UL<<0) + #define CPF_CTX_WINDOW_CID6_LOCK_TYPE_COMPLETE (7UL<<0) + #define CPF_CTX_WINDOW_CID6_VALUE (0x3fffUL<<7) + #define CPF_CTX_WINDOW_CID6_MOD_USAGE_CNT (0x3UL<<24) + #define CPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_00 (0UL<<24) + #define CPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_01 (1UL<<24) + #define CPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_10 (2UL<<24) + #define CPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_11 (3UL<<24) + #define CPF_CTX_WINDOW_CID6_LOCK_GRANTED (1UL<<26) + #define CPF_CTX_WINDOW_CID6_LOCK_MODE (0x3UL<<27) + #define CPF_CTX_WINDOW_CID6_LOCK_MODE_UNLOCK (0UL<<27) + #define CPF_CTX_WINDOW_CID6_LOCK_MODE_IMMEDIATE (1UL<<27) + #define CPF_CTX_WINDOW_CID6_LOCK_MODE_SURE (2UL<<27) + #define CPF_CTX_WINDOW_CID6_NO_EXT_ACC (1UL<<29) + #define CPF_CTX_WINDOW_CID6_LOCK_STATUS (1UL<<30) + #define CPF_CTX_WINDOW_CID6_LOCK_REQ (1UL<<31) + u32_t unused_2[26]; + + u32_t cpf_cpq_cid; + u32_t unused_3[13]; + u32_t cpf_cpq_ftq_cmd; + #define CPF_CPQ_FTQ_CMD_POP (1UL<<30) + u32_t unused_4; + + u32_t cpf_tschq_cid; + u8_t cpf_tschq_flags; + #define CPF_TSCHQ_FLAGS_DELIST (1<<0) + #define CPF_TSCHQ_FLAGS_NORMAL (1<<1) + #define CPF_TSCHQ_FLAGS_HIGH (1<<2) + + u8_t cpf_tschq_rsvd_future; + u16_t unused_5; + u32_t unused_6[12]; + u32_t cpf_tschq_ftq_cmd; + #define CPF_TSCHQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define CPF_TSCHQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define CPF_TSCHQ_FTQ_CMD_BUSY (1UL<<31) + u32_t unused_7; + + u32_t cpf_rxpcq_cid; + u32_t cpf_rxpcq_generic1; + u32_t cpf_rxpcq_generic2; + u32_t unused_8[11]; + u32_t cpf_rxpcq_ftq_cmd; + #define CPF_RXPCQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) + #define CPF_RXPCQ_FTQ_CMD_ADD_DATA (1UL<<28) + #define CPF_RXPCQ_FTQ_CMD_BUSY (1UL<<31) + u32_t unused_9[145]; + + u32_t cpf_dma_data[128]; + u32_t unused_10[128]; + u32_t cpf_burst_base0; + #define CPF_BURST_BASE0_BASE_VAL0 (0x3fffUL<<7) + + u32_t cpf_burst_base1; + #define CPF_BURST_BASE1_BASE_VAL1 (0x3fffUL<<7) + + u32_t cpf_burst_base2; + #define CPF_BURST_BASE2_BASE_VAL2 (0x3fffUL<<7) + + u32_t cpf_burst_base3; + #define CPF_BURST_BASE3_BASE_VAL3 (0x3fffUL<<7) + + u32_t cpf_burst_cmd0; + #define CPF_BURST_CMD0_FTQ_SEL (0x3UL<<0) + #define CPF_BURST_CMD0_FTQ_SEL_0 (0UL<<0) + #define CPF_BURST_CMD0_FTQ_SEL_1 (1UL<<0) + #define CPF_BURST_CMD0_FTQ_SEL_2 (2UL<<0) + #define CPF_BURST_CMD0_FTQ_SEL_3 (3UL<<0) + #define CPF_BURST_CMD0_BUSY (1UL<<2) + #define CPF_BURST_CMD0_OFFSET (0x1ffUL<<3) + #define CPF_BURST_CMD0_BASE_REG_SEL (1UL<<23) + #define CPF_BURST_CMD0_MOD_USAGE_CNT (0x3UL<<24) + #define CPF_BURST_CMD0_MOD_USAGE_CNT_00 (0UL<<24) + #define CPF_BURST_CMD0_MOD_USAGE_CNT_01 (1UL<<24) + #define CPF_BURST_CMD0_MOD_USAGE_CNT_10 (2UL<<24) + #define CPF_BURST_CMD0_MOD_USAGE_CNT_11 (3UL<<24) + #define CPF_BURST_CMD0_PREFETCH_SIZE (0x3UL<<26) + #define CPF_BURST_CMD0_NO_RAM_ACCESS (1UL<<28) + #define CPF_BURST_CMD0_NO_CACHE (1UL<<29) + #define CPF_BURST_CMD0_CROSS_BOUNDARY (1UL<<30) + + u32_t cpf_burst_cmd1; + #define CPF_BURST_CMD1_FTQ_SEL (0x3UL<<0) + #define CPF_BURST_CMD1_FTQ_SEL_0 (0UL<<0) + #define CPF_BURST_CMD1_FTQ_SEL_1 (1UL<<0) + #define CPF_BURST_CMD1_FTQ_SEL_2 (2UL<<0) + #define CPF_BURST_CMD1_FTQ_SEL_3 (3UL<<0) + #define CPF_BURST_CMD1_BUSY (1UL<<2) + #define CPF_BURST_CMD1_OFFSET (0x1ffUL<<3) + #define CPF_BURST_CMD1_BASE_REG_SEL (1UL<<23) + #define CPF_BURST_CMD1_MOD_USAGE_CNT (0x3UL<<24) + #define CPF_BURST_CMD1_MOD_USAGE_CNT_00 (0UL<<24) + #define CPF_BURST_CMD1_MOD_USAGE_CNT_01 (1UL<<24) + #define CPF_BURST_CMD1_MOD_USAGE_CNT_10 (2UL<<24) + #define CPF_BURST_CMD1_MOD_USAGE_CNT_11 (3UL<<24) + #define CPF_BURST_CMD1_PREFETCH_SIZE (0x3UL<<26) + #define CPF_BURST_CMD1_NO_RAM_ACCESS (1UL<<28) + #define CPF_BURST_CMD1_NO_CACHE (1UL<<29) + #define CPF_BURST_CMD1_CROSS_BOUNDARY (1UL<<30) + + u32_t cpf_burst_cmd2; + #define CPF_BURST_CMD2_FTQ_SEL (0x3UL<<0) + #define CPF_BURST_CMD2_FTQ_SEL_0 (0UL<<0) + #define CPF_BURST_CMD2_FTQ_SEL_1 (1UL<<0) + #define CPF_BURST_CMD2_FTQ_SEL_2 (2UL<<0) + #define CPF_BURST_CMD2_FTQ_SEL_3 (3UL<<0) + #define CPF_BURST_CMD2_BUSY (1UL<<2) + #define CPF_BURST_CMD2_OFFSET (0x1ffUL<<3) + #define CPF_BURST_CMD2_BASE_REG_SEL (1UL<<23) + #define CPF_BURST_CMD2_MOD_USAGE_CNT (0x3UL<<24) + #define CPF_BURST_CMD2_MOD_USAGE_CNT_00 (0UL<<24) + #define CPF_BURST_CMD2_MOD_USAGE_CNT_01 (1UL<<24) + #define CPF_BURST_CMD2_MOD_USAGE_CNT_10 (2UL<<24) + #define CPF_BURST_CMD2_MOD_USAGE_CNT_11 (3UL<<24) + #define CPF_BURST_CMD2_PREFETCH_SIZE (0x3UL<<26) + #define CPF_BURST_CMD2_NO_RAM_ACCESS (1UL<<28) + #define CPF_BURST_CMD2_NO_CACHE (1UL<<29) + #define CPF_BURST_CMD2_CROSS_BOUNDARY (1UL<<30) + + u32_t cpf_burst_cmd3; + #define CPF_BURST_CMD3_FTQ_SEL (0x3UL<<0) + #define CPF_BURST_CMD3_FTQ_SEL_0 (0UL<<0) + #define CPF_BURST_CMD3_FTQ_SEL_1 (1UL<<0) + #define CPF_BURST_CMD3_FTQ_SEL_2 (2UL<<0) + #define CPF_BURST_CMD3_FTQ_SEL_3 (3UL<<0) + #define CPF_BURST_CMD3_BUSY (1UL<<2) + #define CPF_BURST_CMD3_OFFSET (0x1ffUL<<3) + #define CPF_BURST_CMD3_BASE_REG_SEL (1UL<<23) + #define CPF_BURST_CMD3_MOD_USAGE_CNT (0x3UL<<24) + #define CPF_BURST_CMD3_MOD_USAGE_CNT_00 (0UL<<24) + #define CPF_BURST_CMD3_MOD_USAGE_CNT_01 (1UL<<24) + #define CPF_BURST_CMD3_MOD_USAGE_CNT_10 (2UL<<24) + #define CPF_BURST_CMD3_MOD_USAGE_CNT_11 (3UL<<24) + #define CPF_BURST_CMD3_PREFETCH_SIZE (0x3UL<<26) + #define CPF_BURST_CMD3_NO_RAM_ACCESS (1UL<<28) + #define CPF_BURST_CMD3_NO_CACHE (1UL<<29) + #define CPF_BURST_CMD3_CROSS_BOUNDARY (1UL<<30) + + u32_t cpf_burst_cmd4; + #define CPF_BURST_CMD4_FTQ_SEL (0x3UL<<0) + #define CPF_BURST_CMD4_FTQ_SEL_0 (0UL<<0) + #define CPF_BURST_CMD4_FTQ_SEL_1 (1UL<<0) + #define CPF_BURST_CMD4_FTQ_SEL_2 (2UL<<0) + #define CPF_BURST_CMD4_FTQ_SEL_3 (3UL<<0) + #define CPF_BURST_CMD4_BUSY (1UL<<2) + #define CPF_BURST_CMD4_OFFSET (0x1ffUL<<3) + #define CPF_BURST_CMD4_BASE_REG_SEL (1UL<<23) + #define CPF_BURST_CMD4_MOD_USAGE_CNT (0x3UL<<24) + #define CPF_BURST_CMD4_MOD_USAGE_CNT_00 (0UL<<24) + #define CPF_BURST_CMD4_MOD_USAGE_CNT_01 (1UL<<24) + #define CPF_BURST_CMD4_MOD_USAGE_CNT_10 (2UL<<24) + #define CPF_BURST_CMD4_MOD_USAGE_CNT_11 (3UL<<24) + #define CPF_BURST_CMD4_PREFETCH_SIZE (0x3UL<<26) + #define CPF_BURST_CMD4_NO_RAM_ACCESS (1UL<<28) + #define CPF_BURST_CMD4_NO_CACHE (1UL<<29) + #define CPF_BURST_CMD4_CROSS_BOUNDARY (1UL<<30) + + u32_t cpf_burst_cmd5; + #define CPF_BURST_CMD5_FTQ_SEL (0x3UL<<0) + #define CPF_BURST_CMD5_FTQ_SEL_0 (0UL<<0) + #define CPF_BURST_CMD5_FTQ_SEL_1 (1UL<<0) + #define CPF_BURST_CMD5_FTQ_SEL_2 (2UL<<0) + #define CPF_BURST_CMD5_FTQ_SEL_3 (3UL<<0) + #define CPF_BURST_CMD5_BUSY (1UL<<2) + #define CPF_BURST_CMD5_OFFSET (0x1ffUL<<3) + #define CPF_BURST_CMD5_BASE_REG_SEL (1UL<<23) + #define CPF_BURST_CMD5_MOD_USAGE_CNT (0x3UL<<24) + #define CPF_BURST_CMD5_MOD_USAGE_CNT_00 (0UL<<24) + #define CPF_BURST_CMD5_MOD_USAGE_CNT_01 (1UL<<24) + #define CPF_BURST_CMD5_MOD_USAGE_CNT_10 (2UL<<24) + #define CPF_BURST_CMD5_MOD_USAGE_CNT_11 (3UL<<24) + #define CPF_BURST_CMD5_PREFETCH_SIZE (0x3UL<<26) + #define CPF_BURST_CMD5_NO_RAM_ACCESS (1UL<<28) + #define CPF_BURST_CMD5_NO_CACHE (1UL<<29) + #define CPF_BURST_CMD5_CROSS_BOUNDARY (1UL<<30) + + u32_t cpf_burst_cmd6; + #define CPF_BURST_CMD6_FTQ_SEL (0x3UL<<0) + #define CPF_BURST_CMD6_FTQ_SEL_0 (0UL<<0) + #define CPF_BURST_CMD6_FTQ_SEL_1 (1UL<<0) + #define CPF_BURST_CMD6_FTQ_SEL_2 (2UL<<0) + #define CPF_BURST_CMD6_FTQ_SEL_3 (3UL<<0) + #define CPF_BURST_CMD6_BUSY (1UL<<2) + #define CPF_BURST_CMD6_OFFSET (0x1ffUL<<3) + #define CPF_BURST_CMD6_BASE_REG_SEL (1UL<<23) + #define CPF_BURST_CMD6_MOD_USAGE_CNT (0x3UL<<24) + #define CPF_BURST_CMD6_MOD_USAGE_CNT_00 (0UL<<24) + #define CPF_BURST_CMD6_MOD_USAGE_CNT_01 (1UL<<24) + #define CPF_BURST_CMD6_MOD_USAGE_CNT_10 (2UL<<24) + #define CPF_BURST_CMD6_MOD_USAGE_CNT_11 (3UL<<24) + #define CPF_BURST_CMD6_PREFETCH_SIZE (0x3UL<<26) + #define CPF_BURST_CMD6_NO_RAM_ACCESS (1UL<<28) + #define CPF_BURST_CMD6_NO_CACHE (1UL<<29) + #define CPF_BURST_CMD6_CROSS_BOUNDARY (1UL<<30) + + u32_t cpf_burst_cmd7; + #define CPF_BURST_CMD7_FTQ_SEL (0x3UL<<0) + #define CPF_BURST_CMD7_FTQ_SEL_0 (0UL<<0) + #define CPF_BURST_CMD7_FTQ_SEL_1 (1UL<<0) + #define CPF_BURST_CMD7_FTQ_SEL_2 (2UL<<0) + #define CPF_BURST_CMD7_FTQ_SEL_3 (3UL<<0) + #define CPF_BURST_CMD7_BUSY (1UL<<2) + #define CPF_BURST_CMD7_OFFSET (0x1ffUL<<3) + #define CPF_BURST_CMD7_BASE_REG_SEL (1UL<<23) + #define CPF_BURST_CMD7_MOD_USAGE_CNT (0x3UL<<24) + #define CPF_BURST_CMD7_MOD_USAGE_CNT_00 (0UL<<24) + #define CPF_BURST_CMD7_MOD_USAGE_CNT_01 (1UL<<24) + #define CPF_BURST_CMD7_MOD_USAGE_CNT_10 (2UL<<24) + #define CPF_BURST_CMD7_MOD_USAGE_CNT_11 (3UL<<24) + #define CPF_BURST_CMD7_PREFETCH_SIZE (0x3UL<<26) + #define CPF_BURST_CMD7_NO_RAM_ACCESS (1UL<<28) + #define CPF_BURST_CMD7_NO_CACHE (1UL<<29) + #define CPF_BURST_CMD7_CROSS_BOUNDARY (1UL<<30) + + u32_t cpf_ctx_cmd; + #define CPF_CTX_CMD_NUM_BLOCKS (0x3UL<<0) + #define CPF_CTX_CMD_OFFSET (0x1ffUL<<3) + #define CPF_CTX_CMD_CID_VALUE (0x3fffUL<<12) + #define CPF_CTX_CMD_PREFETCH_SIZE (0x3UL<<26) + #define CPF_CTX_CMD_MOD_USAGE_CNT (0x3UL<<28) + #define CPF_CTX_CMD_MOD_USAGE_CNT_00 (0UL<<28) + #define CPF_CTX_CMD_MOD_USAGE_CNT_01 (1UL<<28) + #define CPF_CTX_CMD_MOD_USAGE_CNT_10 (2UL<<28) + #define CPF_CTX_CMD_MOD_USAGE_CNT_11 (3UL<<28) + u32_t unused_11[51]; + + u32_t cpf_burst_data0[16]; + u32_t cpf_burst_data1[16]; + u32_t cpf_burst_data2[16]; + u32_t cpf_burst_data3[16]; + u32_t cpf_burst_data4[16]; + u32_t cpf_burst_data5[16]; + u32_t cpf_burst_data6[16]; + u32_t cpf_burst_data7[16]; + u32_t unused_12[64832]; + u32_t cpf_ctx_window5[32768]; + u32_t cpf_ctx_window6[32768]; + u32_t cpf_ctx_window1[32768]; + u32_t cpf_ctx_window2[32768]; + u32_t cpf_ctx_window3[32768]; + u32_t cpf_ctx_window4[32768]; +} cp_fio_xi_t; + + +/* + * mcp_fio definition + * offset: 0x80000000 + */ +typedef struct mcp_fio +{ + u32_t mcpf_events_bits; + #define MCPF_EVENTS_BITS_FTQ2_VALID (1UL<<2) + #define MCPF_EVENTS_BITS_SCANNER_DONE (1UL<<3) + #define MCPF_EVENTS_BITS_DMA_WR_DONE (1UL<<4) + #define MCPF_EVENTS_BITS_DMA_RD_DONE (1UL<<5) + #define MCPF_EVENTS_BITS_CRACKER_DONE (1UL<<6) + #define MCPF_EVENTS_BITS_MULTIPLY_DONE (1UL<<7) + #define MCPF_EVENTS_BITS_GPIO0 (1UL<<15) + #define MCPF_EVENTS_BITS_GPIO1 (1UL<<16) + #define MCPF_EVENTS_BITS_GPIO2 (1UL<<17) + #define MCPF_EVENTS_BITS_GPIO3 (1UL<<18) + + u32_t mcpf_attentions_bits; + #define MCPF_ATTENTIONS_BITS_EPB_ERROR (1UL<<30) + + u32_t mcpf_event_enable; + u32_t mcpf_attention_enable; + u32_t mcpf_fio_status; + u32_t unused_0[11]; + + u32_t mcpf_mcp_hc_inc_stat[8]; + u32_t unused_1[4]; + u32_t mcpf_free_counter_value; + u32_t unused_2[3]; + u32_t mcpf_ump_cmd; + #define MCPF_UMP_CMD_RX_FIFO_ENABLED (1UL<<0) + #define MCPF_UMP_CMD_TX_FIFO_ENABLED (1UL<<1) + #define MCPF_UMP_CMD_FLOWMODE (1UL<<3) + #define MCPF_UMP_CMD_HDFLOWSEL (1UL<<4) + #define MCPF_UMP_CMD_RX_MAC_DISABLE (1UL<<5) + #define MCPF_UMP_CMD_TX_MAC_DISABLE (1UL<<6) + #define MCPF_UMP_CMD_TX_DROP (1UL<<7) + #define MCPF_UMP_CMD_TX_DRIVE (1UL<<8) + #define MCPF_UMP_CMD_TX_RESET (1UL<<14) + + u32_t mcpf_ump_status; + #define MCPF_UMP_STATUS_TX_IDLE (1UL<<0) + #define MCPF_UMP_STATUS_FDX (1UL<<1) + #define MCPF_UMP_STATUS_RX_FRM_DROP (1UL<<3) + #define MCPF_UMP_STATUS_SRC_ADDR_CHG (1UL<<5) + #define MCPF_UMP_STATUS_XOFF_TRIP (0xffUL<<16) + #define MCPF_UMP_STATUS_XON_TRIP (0xffUL<<24) + u32_t unused_3[2]; + + u32_t mcpf_ump_frm_rd_status; + #define MCPF_UMP_FRM_RD_STATUS_NEW_FRM (1UL<<0) + #define MCPF_UMP_FRM_RD_STATUS_FRM_IN_PRO (1UL<<1) + #define MCPF_UMP_FRM_RD_STATUS_FIFO_EMPTY (1UL<<2) + #define MCPF_UMP_FRM_RD_STATUS_BCNT (0x7ffUL<<3) + #define MCPF_UMP_FRM_RD_STATUS_RX_FIFO_STATE (0x7UL<<29) + #define MCPF_UMP_FRM_RD_STATUS_RX_FIFO_STATE_IDLE (0UL<<29) + #define MCPF_UMP_FRM_RD_STATUS_RX_FIFO_STATE_READY (1UL<<29) + #define MCPF_UMP_FRM_RD_STATUS_RX_FIFO_STATE_BUSY (2UL<<29) + #define MCPF_UMP_FRM_RD_STATUS_RX_FIFO_STATE_EXTRA_RD (3UL<<29) + #define MCPF_UMP_FRM_RD_STATUS_RX_FIFO_STATE_LATCH_IP_HDR (4UL<<29) + + u32_t mcpf_ump_frm_rd_data; + u32_t mcpf_ump_frm_wr_ctl; + #define MCPF_UMP_FRM_WR_CTL_NEW_FRM (1UL<<0) + #define MCPF_UMP_FRM_WR_CTL_FIFO_RDY (1UL<<1) + #define MCPF_UMP_FRM_WR_CTL_BCNT_RDY (1UL<<2) + #define MCPF_UMP_FRM_WR_CTL_BCNT (0x7ffUL<<3) + #define MCPF_UMP_FRM_WR_CTL_TX_FIFO_STATE (0x3UL<<30) + #define MCPF_UMP_FRM_WR_CTL_TX_FIFO_STATE_IDLE (0UL<<30) + #define MCPF_UMP_FRM_WR_CTL_TX_FIFO_STATE_WAIT (1UL<<30) + #define MCPF_UMP_FRM_WR_CTL_TX_FIFO_STATE_BUSY (2UL<<30) + #define MCPF_UMP_FRM_WR_CTL_TX_FIFO_STATE_EXTRA_WR (3UL<<30) + + u32_t mcpf_ump_frm_wr_data; + u32_t mcpf_ump_frm_pre_fetch; + u32_t mcpf_ump_fifo_remain; + #define MCPF_UMP_FIFO_REMAIN_TX_FIFO_REMAIN (0x1ffUL<<0) + #define MCPF_UMP_FIFO_REMAIN_RX_FIFO_REMAIN (0x1ffUL<<16) + + u32_t mcpf_ump_rxfifo_ptrs; + #define MCPF_UMP_RXFIFO_PTRS_WA_CPU (0x1ffUL<<0) + #define MCPF_UMP_RXFIFO_PTRS_WA_TOGGLE_CPU (1UL<<9) + #define MCPF_UMP_RXFIFO_PTRS_RA (0x1ffUL<<16) + #define MCPF_UMP_RXFIFO_PTRS_RA_TOGGLE (1UL<<25) + + u32_t mcpf_ump_txfifo_ptrs; + #define MCPF_UMP_TXFIFO_PTRS_WA (0x1ffUL<<0) + #define MCPF_UMP_TXFIFO_PTRS_WA_TOGGLE (1UL<<9) + #define MCPF_UMP_TXFIFO_PTRS_RA_CPU (0x1ffUL<<16) + #define MCPF_UMP_TXFIFO_PTRS_RA_TOGGLE_CPU (1UL<<25) + + u32_t mcpf_ump_ump_debug; + #define MCPF_UMP_UMP_DEBUG_RXBUF_ALM_FULL_CORE (1UL<<0) + #define MCPF_UMP_UMP_DEBUG_FIFO_FULL_ERR (1UL<<1) + #define MCPF_UMP_UMP_DEBUG_NEW_PACKET (1UL<<2) + #define MCPF_UMP_UMP_DEBUG_LOCAL_PKT_ABT (1UL<<3) + #define MCPF_UMP_UMP_DEBUG_SETABT (1UL<<4) + u32_t unused_4[19]; + + u32_t mcpf_mcpq_bits_status; + u16_t mcpf_mcpq_pkt_len; + u16_t unused_5; + u32_t mcpf_mcpq_mbuf_cluster; + u32_t unused_6[11]; + u32_t mcpf_mcpq_cmd; + u32_t unused_7; + +} mcp_fio_t; + + +/* + * mcp_fio definition + * offset: 0x80000000 + */ +typedef struct mcp_fio_xi +{ + u32_t mcpf_events_bits; + #define MCPF_EVENTS_BITS_FTQ0_VALID (1UL<<0) + #define MCPF_EVENTS_BITS_FTQ1_VALID (1UL<<1) + #define MCPF_EVENTS_BITS_UMP_EVENT (1UL<<2) + #define MCPF_EVENTS_BITS_SMBUS_EVENT (1UL<<3) + #define MCPF_EVENTS_BITS_FLASH_EVENT (1UL<<4) + #define MCPF_EVENTS_BITS_MCP_DOORBELL (1UL<<5) + #define MCPF_EVENTS_BITS_UNUSED_A (1UL<<6) + #define MCPF_EVENTS_BITS_UNUSED_B (1UL<<7) + #define MCPF_EVENTS_BITS_EXP_ROM (1UL<<8) + #define MCPF_EVENTS_BITS_VPD (1UL<<9) + #define MCPF_EVENTS_BITS_FLASH (1UL<<10) + #define MCPF_EVENTS_BITS_SMB0 (1UL<<11) + #define MCPF_EVENTS_BITS_RESERVED0 (1UL<<12) + #define MCPF_EVENTS_BITS_RESERVED1 (1UL<<13) + #define MCPF_EVENTS_BITS_RESERVED2 (1UL<<14) + #define MCPF_EVENTS_BITS_GPIO (1UL<<15) + #define MCPF_EVENTS_BITS_SW_TMR_1 (1UL<<19) + #define MCPF_EVENTS_BITS_SW_TMR_2 (1UL<<20) + #define MCPF_EVENTS_BITS_SW_TMR_3 (1UL<<21) + #define MCPF_EVENTS_BITS_SW_TMR_4 (1UL<<22) + #define MCPF_EVENTS_BITS_LINK_CHANGED (1UL<<23) + #define MCPF_EVENTS_BITS_MI_INT (1UL<<25) + #define MCPF_EVENTS_BITS_MI_COMPLETE (1UL<<26) + #define MCPF_EVENTS_BITS_MAIN_PWR_INT (1UL<<27) + #define MCPF_EVENTS_BITS_NOT_ENABLED (1UL<<30) + #define MCPF_EVENTS_BITS_ATTENTIONS_VALID (1UL<<31) + + u32_t mcpf_attentions_bits; + #define MCPF_ATTENTIONS_BITS_LINK_STATE (1UL<<0) + #define MCPF_ATTENTIONS_BITS_TX_SCHEDULER_ABORT (1UL<<1) + #define MCPF_ATTENTIONS_BITS_TX_BD_READ_ABORT (1UL<<2) + #define MCPF_ATTENTIONS_BITS_TX_BD_CACHE_ABORT (1UL<<3) + #define MCPF_ATTENTIONS_BITS_TX_PROCESSOR_ABORT (1UL<<4) + #define MCPF_ATTENTIONS_BITS_TX_DMA_ABORT (1UL<<5) + #define MCPF_ATTENTIONS_BITS_TX_PATCHUP_ABORT (1UL<<6) + #define MCPF_ATTENTIONS_BITS_TX_ASSEMBLER_ABORT (1UL<<7) + #define MCPF_ATTENTIONS_BITS_RX_PARSER_MAC_ABORT (1UL<<8) + #define MCPF_ATTENTIONS_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) + #define MCPF_ATTENTIONS_BITS_RX_MBUF_ABORT (1UL<<10) + #define MCPF_ATTENTIONS_BITS_RX_LOOKUP_ABORT (1UL<<11) + #define MCPF_ATTENTIONS_BITS_RX_PROCESSOR_ABORT (1UL<<12) + #define MCPF_ATTENTIONS_BITS_RX_V2P_ABORT (1UL<<13) + #define MCPF_ATTENTIONS_BITS_RX_BD_CACHE_ABORT (1UL<<14) + #define MCPF_ATTENTIONS_BITS_RX_DMA_ABORT (1UL<<15) + #define MCPF_ATTENTIONS_BITS_COMPLETION_ABORT (1UL<<16) + #define MCPF_ATTENTIONS_BITS_HOST_COALESCE_ABORT (1UL<<17) + #define MCPF_ATTENTIONS_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) + #define MCPF_ATTENTIONS_BITS_CONTEXT_ABORT (1UL<<19) + #define MCPF_ATTENTIONS_BITS_CMD_SCHEDULER_ABORT (1UL<<20) + #define MCPF_ATTENTIONS_BITS_CMD_PROCESSOR_ABORT (1UL<<21) + #define MCPF_ATTENTIONS_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) + #define MCPF_ATTENTIONS_BITS_MAC_ABORT (1UL<<23) + #define MCPF_ATTENTIONS_BITS_TIMER_ABORT (1UL<<24) + #define MCPF_ATTENTIONS_BITS_DMAE_ABORT (1UL<<25) + #define MCPF_ATTENTIONS_BITS_FLSH_ABORT (1UL<<26) + #define MCPF_ATTENTIONS_BITS_GRC_ABORT (1UL<<27) + #define MCPF_ATTENTIONS_BITS_PARITY_ERROR (1UL<<31) + + u32_t mcpf_event_enable; + u32_t mcpf_attention_enable; + u32_t mcpf_fio_status; + #define MCPF_FIO_STATUS_ENABLED (1UL<<0) + #define MCPF_FIO_STATUS_FORCE_ENA (1UL<<1) + + u32_t mcpf_interrupt_status; + #define MCPF_INTERRUPT_STATUS_EVENT0 (1UL<<0) + #define MCPF_INTERRUPT_STATUS_ATTN0 (1UL<<1) + #define MCPF_INTERRUPT_STATUS_EVENT1 (1UL<<2) + #define MCPF_INTERRUPT_STATUS_ATTN1 (1UL<<3) + u32_t unused_0[10]; + + u32_t mcpf_mcp_hc_inc_stat[8]; + u32_t unused_1[4]; + u32_t mcpf_free_counter_value; + u32_t unused_2[35]; + u32_t mcpf_mcpq_bits_status; + #define MCPF_MCPQ_BITS_STATUS_RULE_CLASS (0x7UL<<0) + #define MCPF_MCPQ_BITS_STATUS_RULE_P2 (1UL<<3) + #define MCPF_MCPQ_BITS_STATUS_RULE_P3 (1UL<<4) + #define MCPF_MCPQ_BITS_STATUS_RULE_P4 (1UL<<5) + #define MCPF_MCPQ_BITS_STATUS_L2_VLAN_TAG (1UL<<6) + #define MCPF_MCPQ_BITS_STATUS_L2_LLC_SNAP (1UL<<7) + #define MCPF_MCPQ_BITS_STATUS_RSS_HASH (1UL<<8) + #define MCPF_MCPQ_BITS_STATUS_SORT_VECT (0xfUL<<9) + #define MCPF_MCPQ_BITS_STATUS_IP_DATAGRAM (1UL<<13) + #define MCPF_MCPQ_BITS_STATUS_TCP_SEGMENT (1UL<<14) + #define MCPF_MCPQ_BITS_STATUS_UDP_DATAGRAM (1UL<<15) + #define MCPF_MCPQ_BITS_STATUS_CU_FRAME (1UL<<16) + #define MCPF_MCPQ_BITS_STATUS_IP_PROG_EXT (1UL<<17) + #define MCPF_MCPQ_BITS_STATUS_IP_TYPE (1UL<<18) + #define MCPF_MCPQ_BITS_STATUS_RULE_P1 (1UL<<19) + #define MCPF_MCPQ_BITS_STATUS_RLUP_HIT4 (1UL<<20) + #define MCPF_MCPQ_BITS_STATUS_IP_FRAGMENT (1UL<<21) + #define MCPF_MCPQ_BITS_STATUS_IP_OPTIONS_PRESENT (1UL<<22) + #define MCPF_MCPQ_BITS_STATUS_TCP_OPTIONS_PRESENT (1UL<<23) + #define MCPF_MCPQ_BITS_STATUS_L2_PM_IDX (0xfUL<<24) + #define MCPF_MCPQ_BITS_STATUS_L2_PM_HIT (1UL<<28) + #define MCPF_MCPQ_BITS_STATUS_L2_MC_HASH_HIT (1UL<<29) + #define MCPF_MCPQ_BITS_STATUS_RDMAC_CRC_PASS (1UL<<30) + #define MCPF_MCPQ_BITS_STATUS_MP_HIT (1UL<<31) + + u16_t mcpf_mcpq_pkt_len; + #define MCPF_MCPQ_PKT_LEN_VALUE (0x3fff<<0) + + u16_t mcpf_mcpq_vlan_tag; + u32_t mcpf_mcpq_mbuf_cluster; + #define MCPF_MCPQ_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) + + u32_t mcpf_mcpq_frm_errors; + #define MCPF_MCPQ_FRM_ERRORS_L2_BAD_CRC (1UL<<1) + #define MCPF_MCPQ_FRM_ERRORS_L2_PHY_DECODE (1UL<<2) + #define MCPF_MCPQ_FRM_ERRORS_L2_ALIGNMENT (1UL<<3) + #define MCPF_MCPQ_FRM_ERRORS_L2_TOO_SHORT (1UL<<4) + #define MCPF_MCPQ_FRM_ERRORS_L2_GIANT_FRAME (1UL<<5) + #define MCPF_MCPQ_FRM_ERRORS_IP_BAD_LEN (1UL<<6) + #define MCPF_MCPQ_FRM_ERRORS_IP_TOO_SHORT (1UL<<7) + #define MCPF_MCPQ_FRM_ERRORS_IP_BAD_VERSION (1UL<<8) + #define MCPF_MCPQ_FRM_ERRORS_IP_BAD_HLEN (1UL<<9) + #define MCPF_MCPQ_FRM_ERRORS_IP_BAD_XSUM (1UL<<10) + #define MCPF_MCPQ_FRM_ERRORS_TCP_TOO_SHORT (1UL<<11) + #define MCPF_MCPQ_FRM_ERRORS_TCP_BAD_XSUM (1UL<<12) + #define MCPF_MCPQ_FRM_ERRORS_TCP_BAD_OFFSET (1UL<<13) + #define MCPF_MCPQ_FRM_ERRORS_UDP_BAD_XSUM (1UL<<15) + #define MCPF_MCPQ_FRM_ERRORS_IP_BAD_ORDER (1UL<<16) + #define MCPF_MCPQ_FRM_ERRORS_IP_HDR_MISMATCH (1UL<<18) + + u16_t mcpf_mcpq_ext_status; + #define MCPF_MCPQ_EXT_STATUS_TCP_SYNC_PRESENT (1<<0) + #define MCPF_MCPQ_EXT_STATUS_RLUP_HIT2 (1<<1) + #define MCPF_MCPQ_EXT_STATUS_TCP_UDP_XSUM_IS_0 (1<<2) + #define MCPF_MCPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT (0x3<<3) + #define MCPF_MCPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_00 (0<<3) + #define MCPF_MCPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_01 (1<<3) + #define MCPF_MCPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_10 (2<<3) + #define MCPF_MCPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_11 (3<<3) + #define MCPF_MCPQ_EXT_STATUS_ACPI_MATCH (1<<5) + + u16_t mcpf_mcpq_reserved; + u32_t unused_3[9]; + u32_t mcpf_mcpq_cmd; + #define MCPF_MCPQ_CMD_MCPQ_CMD_POP (1UL<<30) + u32_t unused_4[39089]; + + u32_t mcpf_nvm_command; + #define MCPF_NVM_COMMAND_RST (1UL<<0) + #define MCPF_NVM_COMMAND_DONE (1UL<<3) + #define MCPF_NVM_COMMAND_DOIT (1UL<<4) + #define MCPF_NVM_COMMAND_WR (1UL<<5) + #define MCPF_NVM_COMMAND_ERASE (1UL<<6) + #define MCPF_NVM_COMMAND_FIRST (1UL<<7) + #define MCPF_NVM_COMMAND_LAST (1UL<<8) + #define MCPF_NVM_COMMAND_WREN (1UL<<16) + #define MCPF_NVM_COMMAND_WRDI (1UL<<17) + #define MCPF_NVM_COMMAND_RD_ID (1UL<<20) + #define MCPF_NVM_COMMAND_RD_STATUS (1UL<<21) + #define MCPF_NVM_COMMAND_MODE_256 (1UL<<22) + + u32_t mcpf_nvm_status; + #define MCPF_NVM_STATUS_SPI_FSM_STATE (0x1fUL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE (0UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0 (1UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1 (2UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0 (3UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1 (4UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0 (5UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0 (6UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1 (7UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2 (8UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0 (9UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1 (10UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2 (11UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0 (12UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1 (13UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2 (14UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3 (15UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4 (16UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0 (17UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN (18UL<<0) + #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT (19UL<<0) + + u32_t mcpf_nvm_write; + #define MCPF_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffUL<<0) + #define MCPF_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0UL<<0) + #define MCPF_NVM_WRITE_NVM_WRITE_VALUE_SI (1UL<<0) + #define MCPF_NVM_WRITE_NVM_WRITE_VALUE_SO (2UL<<0) + #define MCPF_NVM_WRITE_NVM_WRITE_VALUE_CS_B (4UL<<0) + #define MCPF_NVM_WRITE_NVM_WRITE_VALUE_SCLK (8UL<<0) + + u32_t mcpf_nvm_addr; + #define MCPF_NVM_ADDR_NVM_ADDR_VALUE (0xffffffUL<<0) + #define MCPF_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0UL<<0) + #define MCPF_NVM_ADDR_NVM_ADDR_VALUE_SI (1UL<<0) + #define MCPF_NVM_ADDR_NVM_ADDR_VALUE_SO (2UL<<0) + #define MCPF_NVM_ADDR_NVM_ADDR_VALUE_CS_B (4UL<<0) + #define MCPF_NVM_ADDR_NVM_ADDR_VALUE_SCLK (8UL<<0) + + u32_t mcpf_nvm_read; + #define MCPF_NVM_READ_NVM_READ_VALUE (0xffffffffUL<<0) + #define MCPF_NVM_READ_NVM_READ_VALUE_BIT_BANG (0UL<<0) + #define MCPF_NVM_READ_NVM_READ_VALUE_SI (1UL<<0) + #define MCPF_NVM_READ_NVM_READ_VALUE_SO (2UL<<0) + #define MCPF_NVM_READ_NVM_READ_VALUE_CS_B (4UL<<0) + #define MCPF_NVM_READ_NVM_READ_VALUE_SCLK (8UL<<0) + + u32_t mcpf_nvm_cfg1; + #define MCPF_NVM_CFG1_FLASH_MODE (1UL<<0) + #define MCPF_NVM_CFG1_BUFFER_MODE (1UL<<1) + #define MCPF_NVM_CFG1_PASS_MODE (1UL<<2) + #define MCPF_NVM_CFG1_BITBANG_MODE (1UL<<3) + #define MCPF_NVM_CFG1_STATUS_BIT (0x7UL<<4) + #define MCPF_NVM_CFG1_SPI_CLK_DIV (0xfUL<<7) + #define MCPF_NVM_CFG1_SEE_CLK_DIV (0x7ffUL<<11) + #define MCPF_NVM_CFG1_STRAP_CONTROL_0 (1UL<<23) + #define MCPF_NVM_CFG1_PROTECT_MODE (1UL<<24) + #define MCPF_NVM_CFG1_FLASH_SIZE (1UL<<25) + #define MCPF_NVM_CFG1_FW_USTRAP_1 (1UL<<26) + #define MCPF_NVM_CFG1_FW_USTRAP_0 (1UL<<27) + #define MCPF_NVM_CFG1_FW_USTRAP_2 (1UL<<28) + #define MCPF_NVM_CFG1_FW_USTRAP_3 (1UL<<29) + #define MCPF_NVM_CFG1_FW_FLASH_TYPE_EN (1UL<<30) + #define MCPF_NVM_CFG1_COMPAT_BYPASSS (1UL<<31) + + u32_t mcpf_nvm_cfg2; + #define MCPF_NVM_CFG2_ERASE_CMD (0xffUL<<0) + #define MCPF_NVM_CFG2_STATUS_CMD (0xffUL<<16) + #define MCPF_NVM_CFG2_READ_ID (0xffUL<<24) + + u32_t mcpf_nvm_cfg3; + #define MCPF_NVM_CFG3_BUFFER_RD_CMD (0xffUL<<0) + #define MCPF_NVM_CFG3_WRITE_CMD (0xffUL<<8) + #define MCPF_NVM_CFG3_READ_CMD (0xffUL<<24) + + u32_t mcpf_nvm_sw_arb; + #define MCPF_NVM_SW_ARB_ARB_REQ_SET0 (1UL<<0) + #define MCPF_NVM_SW_ARB_ARB_REQ_SET1 (1UL<<1) + #define MCPF_NVM_SW_ARB_ARB_REQ_SET2 (1UL<<2) + #define MCPF_NVM_SW_ARB_ARB_REQ_SET3 (1UL<<3) + #define MCPF_NVM_SW_ARB_ARB_REQ_CLR0 (1UL<<4) + #define MCPF_NVM_SW_ARB_ARB_REQ_CLR1 (1UL<<5) + #define MCPF_NVM_SW_ARB_ARB_REQ_CLR2 (1UL<<6) + #define MCPF_NVM_SW_ARB_ARB_REQ_CLR3 (1UL<<7) + #define MCPF_NVM_SW_ARB_ARB_ARB0 (1UL<<8) + #define MCPF_NVM_SW_ARB_ARB_ARB1 (1UL<<9) + #define MCPF_NVM_SW_ARB_ARB_ARB2 (1UL<<10) + #define MCPF_NVM_SW_ARB_ARB_ARB3 (1UL<<11) + #define MCPF_NVM_SW_ARB_REQ0 (1UL<<12) + #define MCPF_NVM_SW_ARB_REQ1 (1UL<<13) + #define MCPF_NVM_SW_ARB_REQ2 (1UL<<14) + #define MCPF_NVM_SW_ARB_REQ3 (1UL<<15) + + u32_t mcpf_nvm_access_enable; + #define MCPF_NVM_ACCESS_ENABLE_EN (1UL<<0) + #define MCPF_NVM_ACCESS_ENABLE_WR_EN (1UL<<1) + + u32_t mcpf_nvm_write1; + #define MCPF_NVM_WRITE1_WREN_CMD (0xffUL<<0) + #define MCPF_NVM_WRITE1_WRDI_CMD (0xffUL<<8) + + u32_t mcpf_nvm_cfg4; + #define MCPF_NVM_CFG4_FLASH_SIZE (0x7UL<<0) + #define MCPF_NVM_CFG4_FLASH_SIZE_1MBIT (0UL<<0) + #define MCPF_NVM_CFG4_FLASH_SIZE_2MBIT (1UL<<0) + #define MCPF_NVM_CFG4_FLASH_SIZE_4MBIT (2UL<<0) + #define MCPF_NVM_CFG4_FLASH_SIZE_8MBIT (3UL<<0) + #define MCPF_NVM_CFG4_FLASH_SIZE_16MBIT (4UL<<0) + #define MCPF_NVM_CFG4_FLASH_SIZE_32MBIT (5UL<<0) + #define MCPF_NVM_CFG4_FLASH_SIZE_64MBIT (6UL<<0) + #define MCPF_NVM_CFG4_FLASH_SIZE_128MBIT (7UL<<0) + #define MCPF_NVM_CFG4_FLASH_VENDOR (1UL<<3) + #define MCPF_NVM_CFG4_FLASH_VENDOR_ST (0UL<<3) + #define MCPF_NVM_CFG4_FLASH_VENDOR_ATMEL (1UL<<3) + #define MCPF_NVM_CFG4_MODE_256_EMPTY_BIT_LOC (0x3UL<<4) + #define MCPF_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 (0UL<<4) + #define MCPF_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9 (1UL<<4) + #define MCPF_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10 (2UL<<4) + #define MCPF_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11 (3UL<<4) + #define MCPF_NVM_CFG4_STATUS_BIT_POLARITY (1UL<<6) + #define MCPF_NVM_CFG4_RESERVED (0x1ffffffUL<<7) + + u32_t mcpf_nvm_reconfig; + #define MCPF_NVM_RECONFIG_ORIG_STRAP_VALUE (0xfUL<<0) + #define MCPF_NVM_RECONFIG_ORIG_STRAP_VALUE_ST (0UL<<0) + #define MCPF_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL (1UL<<0) + #define MCPF_NVM_RECONFIG_RECONFIG_STRAP_VALUE (0xfUL<<4) + #define MCPF_NVM_RECONFIG_RESERVED (0x7fffffUL<<8) + #define MCPF_NVM_RECONFIG_RECONFIG_DONE (1UL<<31) + u32_t unused_5[1779]; + + u32_t mcpf_smbus_config; + #define MCPF_SMBUS_CONFIG_HW_ARP_ASSIGN_ADDR (1UL<<7) + #define MCPF_SMBUS_CONFIG_ARP_EN0 (1UL<<8) + #define MCPF_SMBUS_CONFIG_ARP_EN1 (1UL<<9) + #define MCPF_SMBUS_CONFIG_MASTER_RTRY_CNT (0xfUL<<16) + #define MCPF_SMBUS_CONFIG_TIMESTAMP_CNT_EN (1UL<<26) + #define MCPF_SMBUS_CONFIG_PROMISCOUS_MODE (1UL<<27) + #define MCPF_SMBUS_CONFIG_EN_NIC_SMB_ADDR_0 (1UL<<28) + #define MCPF_SMBUS_CONFIG_BIT_BANG_EN (1UL<<29) + #define MCPF_SMBUS_CONFIG_SMB_EN (1UL<<30) + #define MCPF_SMBUS_CONFIG_RESET (1UL<<31) + + u32_t mcpf_smbus_timing_config; + #define MCPF_SMBUS_TIMING_CONFIG_SMBUS_IDLE_TIME (0xffUL<<8) + #define MCPF_SMBUS_TIMING_CONFIG_PERIODIC_SLAVE_STRETCH (0xffUL<<16) + #define MCPF_SMBUS_TIMING_CONFIG_RANDOM_SLAVE_STRETCH (0x7fUL<<24) + #define MCPF_SMBUS_TIMING_CONFIG_MODE_400 (1UL<<31) + + u32_t mcpf_smbus_address; + #define MCPF_SMBUS_ADDRESS_NIC_SMB_ADDR0 (0x7fUL<<0) + #define MCPF_SMBUS_ADDRESS_EN_NIC_SMB_ADDR0 (1UL<<7) + #define MCPF_SMBUS_ADDRESS_NIC_SMB_ADDR1 (0x7fUL<<8) + #define MCPF_SMBUS_ADDRESS_EN_NIC_SMB_ADDR1 (1UL<<15) + #define MCPF_SMBUS_ADDRESS_NIC_SMB_ADDR2 (0x7fUL<<16) + #define MCPF_SMBUS_ADDRESS_EN_NIC_SMB_ADDR2 (1UL<<23) + #define MCPF_SMBUS_ADDRESS_NIC_SMB_ADDR3 (0x7fUL<<24) + #define MCPF_SMBUS_ADDRESS_EN_NIC_SMB_ADDR3 (1UL<<31) + + u32_t mcpf_smbus_master_fifo_control; + #define MCPF_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_THRESHOLD (0x7fUL<<8) + #define MCPF_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_PKT_COUNT (0x7fUL<<16) + #define MCPF_SMBUS_MASTER_FIFO_CONTROL_MASTER_TX_FIFO_FLUSH (1UL<<30) + #define MCPF_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_FLUSH (1UL<<31) + + u32_t mcpf_smbus_slave_fifo_control; + #define MCPF_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_THRESHOLD (0x7fUL<<8) + #define MCPF_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_PKT_COUNT (0x7fUL<<16) + #define MCPF_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_TX_FIFO_FLUSH (1UL<<30) + #define MCPF_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_FLUSH (1UL<<31) + + u32_t mcpf_smbus_bit_bang_control; + #define MCPF_SMBUS_BIT_BANG_CONTROL_SMBDAT_OUT_EN (1UL<<28) + #define MCPF_SMBUS_BIT_BANG_CONTROL_SMBDAT_IN (1UL<<29) + #define MCPF_SMBUS_BIT_BANG_CONTROL_SMBCLK_OUT_EN (1UL<<30) + #define MCPF_SMBUS_BIT_BANG_CONTROL_SMBCLK_IN (1UL<<31) + + u32_t mcpf_smbus_watchdog; + #define MCPF_SMBUS_WATCHDOG_WATCHDOG (0xffffUL<<0) + + u32_t mcpf_smbus_heartbeat; + #define MCPF_SMBUS_HEARTBEAT_HEARTBEAT (0xffffUL<<0) + + u32_t mcpf_smbus_poll_asf; + #define MCPF_SMBUS_POLL_ASF_POLL_ASF (0xffffUL<<0) + + u32_t mcpf_smbus_poll_legacy; + #define MCPF_SMBUS_POLL_LEGACY_POLL_LEGACY (0xffffUL<<0) + + u32_t mcpf_smbus_retran; + #define MCPF_SMBUS_RETRAN_RETRAN (0xffUL<<0) + + u32_t mcpf_smbus_timestamp; + #define MCPF_SMBUS_TIMESTAMP_TIMESTAMP (0xffffffffUL<<0) + + u32_t mcpf_smbus_master_command; + #define MCPF_SMBUS_MASTER_COMMAND_RD_BYTE_COUNT (0xffUL<<0) + #define MCPF_SMBUS_MASTER_COMMAND_PEC (1UL<<8) + #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL (0xfUL<<9) + #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0000 (0UL<<9) + #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0001 (1UL<<9) + #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0010 (2UL<<9) + #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0011 (3UL<<9) + #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0100 (4UL<<9) + #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0101 (5UL<<9) + #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0110 (6UL<<9) + #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0111 (7UL<<9) + #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1000 (8UL<<9) + #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1001 (9UL<<9) + #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1010 (10UL<<9) + #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1011 (11UL<<9) + #define MCPF_SMBUS_MASTER_COMMAND_STATUS (0x7UL<<25) + #define MCPF_SMBUS_MASTER_COMMAND_STATUS_000 (0UL<<25) + #define MCPF_SMBUS_MASTER_COMMAND_STATUS_001 (1UL<<25) + #define MCPF_SMBUS_MASTER_COMMAND_STATUS_010 (2UL<<25) + #define MCPF_SMBUS_MASTER_COMMAND_STATUS_011 (3UL<<25) + #define MCPF_SMBUS_MASTER_COMMAND_STATUS_100 (4UL<<25) + #define MCPF_SMBUS_MASTER_COMMAND_STATUS_101 (5UL<<25) + #define MCPF_SMBUS_MASTER_COMMAND_STATUS_110 (6UL<<25) + #define MCPF_SMBUS_MASTER_COMMAND_STATUS_111 (7UL<<25) + #define MCPF_SMBUS_MASTER_COMMAND_ABORT (1UL<<30) + #define MCPF_SMBUS_MASTER_COMMAND_START_BUSY (1UL<<31) + + u32_t mcpf_smbus_slave_command; + #define MCPF_SMBUS_SLAVE_COMMAND_PEC (1UL<<8) + #define MCPF_SMBUS_SLAVE_COMMAND_STATUS (0x7UL<<23) + #define MCPF_SMBUS_SLAVE_COMMAND_STATUS_000 (0UL<<23) + #define MCPF_SMBUS_SLAVE_COMMAND_STATUS_101 (5UL<<23) + #define MCPF_SMBUS_SLAVE_COMMAND_STATUS_111 (7UL<<23) + #define MCPF_SMBUS_SLAVE_COMMAND_ABORT (1UL<<30) + #define MCPF_SMBUS_SLAVE_COMMAND_START (1UL<<31) + + u32_t mcpf_smbus_event_enable; + #define MCPF_SMBUS_EVENT_ENABLE_WATCHDOG_TO_EN (1UL<<0) + #define MCPF_SMBUS_EVENT_ENABLE_HEARTBEAT_TO_EN (1UL<<1) + #define MCPF_SMBUS_EVENT_ENABLE_POLL_ASF_TO_EN (1UL<<2) + #define MCPF_SMBUS_EVENT_ENABLE_POLL_LEGACY_TO_EN (1UL<<3) + #define MCPF_SMBUS_EVENT_ENABLE_RETRANSMIT_TO_EN (1UL<<4) + #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_ARP_EVENT_EN (1UL<<20) + #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_RD_EVENT_EN (1UL<<21) + #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_TX_UNDERRUN_EN (1UL<<22) + #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_START_BUSY_EN (1UL<<23) + #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_RX_EVENT_EN (1UL<<24) + #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_RX_THRESHOLD_HIT_EN (1UL<<25) + #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_RX_FIFO_FULL_EN (1UL<<26) + #define MCPF_SMBUS_EVENT_ENABLE_MASTER_TX_UNDERRUN_EN (1UL<<27) + #define MCPF_SMBUS_EVENT_ENABLE_MASTER_START_BUSY_EN (1UL<<28) + #define MCPF_SMBUS_EVENT_ENABLE_MASTER_RX_EVENT_EN (1UL<<29) + #define MCPF_SMBUS_EVENT_ENABLE_MASTER_RX_THRESHOLD_HIT_EN (1UL<<30) + #define MCPF_SMBUS_EVENT_ENABLE_MASTER_RX_FIFO_FULL_EN (1UL<<31) + + u32_t mcpf_smbus_event_status; + #define MCPF_SMBUS_EVENT_STATUS_WATCHDOG_TO (1UL<<0) + #define MCPF_SMBUS_EVENT_STATUS_HEARTBEAT_TO (1UL<<1) + #define MCPF_SMBUS_EVENT_STATUS_POLL_ASF_TO (1UL<<2) + #define MCPF_SMBUS_EVENT_STATUS_POLL_LEGACY_TO (1UL<<3) + #define MCPF_SMBUS_EVENT_STATUS_RETRANSMIT_TO (1UL<<4) + #define MCPF_SMBUS_EVENT_STATUS_SLAVE_ARP_EVENT (1UL<<20) + #define MCPF_SMBUS_EVENT_STATUS_SLAVE_RD_EVENT (1UL<<21) + #define MCPF_SMBUS_EVENT_STATUS_SLAVE_TX_UNDERRUN (1UL<<22) + #define MCPF_SMBUS_EVENT_STATUS_SLAVE_START_BUSY (1UL<<23) + #define MCPF_SMBUS_EVENT_STATUS_SLAVE_RX_EVENT (1UL<<24) + #define MCPF_SMBUS_EVENT_STATUS_SLAVE_RX_THRESHOLD_HIT (1UL<<25) + #define MCPF_SMBUS_EVENT_STATUS_SLAVE_RX_FIFO_FULL (1UL<<26) + #define MCPF_SMBUS_EVENT_STATUS_MASTER_TX_UNDERRUN (1UL<<27) + #define MCPF_SMBUS_EVENT_STATUS_MASTER_START_BUSY (1UL<<28) + #define MCPF_SMBUS_EVENT_STATUS_MASTER_RX_EVENT (1UL<<29) + #define MCPF_SMBUS_EVENT_STATUS_MASTER_RX_THRESHOLD_HIT (1UL<<30) + #define MCPF_SMBUS_EVENT_STATUS_MASTER_RX_FIFO_FULL (1UL<<31) + + u32_t mcpf_smbus_master_data_write; + #define MCPF_SMBUS_MASTER_DATA_WRITE_MASTER_SMBUS_WR_DATA (0xffUL<<0) + #define MCPF_SMBUS_MASTER_DATA_WRITE_WR_STATUS (1UL<<31) + + u32_t mcpf_smbus_master_data_read; + #define MCPF_SMBUS_MASTER_DATA_READ_MASTER_SMBUS_RD_DATA (0xffUL<<0) + #define MCPF_SMBUS_MASTER_DATA_READ_PEC_ERR (1UL<<29) + #define MCPF_SMBUS_MASTER_DATA_READ_RD_STATUS (0x3UL<<30) + #define MCPF_SMBUS_MASTER_DATA_READ_RD_STATUS_00 (0UL<<30) + #define MCPF_SMBUS_MASTER_DATA_READ_RD_STATUS_01 (1UL<<30) + #define MCPF_SMBUS_MASTER_DATA_READ_RD_STATUS_10 (2UL<<30) + #define MCPF_SMBUS_MASTER_DATA_READ_RD_STATUS_11 (3UL<<30) + + u32_t mcpf_smbus_slave_data_write; + #define MCPF_SMBUS_SLAVE_DATA_WRITE_SLAVE_SMBUS_WR_DATA (0xffUL<<0) + #define MCPF_SMBUS_SLAVE_DATA_WRITE_WR_STATUS (1UL<<31) + #define MCPF_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_0 (0UL<<31) + #define MCPF_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_1 (1UL<<31) + + u32_t mcpf_smbus_slave_data_read; + #define MCPF_SMBUS_SLAVE_DATA_READ_SLAVE_SMBUS_RD_DATA (0xffUL<<0) + #define MCPF_SMBUS_SLAVE_DATA_READ_ERR_STATUS (0x3UL<<28) + #define MCPF_SMBUS_SLAVE_DATA_READ_ERR_STATUS_00 (0UL<<28) + #define MCPF_SMBUS_SLAVE_DATA_READ_ERR_STATUS_01 (1UL<<28) + #define MCPF_SMBUS_SLAVE_DATA_READ_ERR_STATUS_10 (2UL<<28) + #define MCPF_SMBUS_SLAVE_DATA_READ_ERR_STATUS_11 (3UL<<28) + #define MCPF_SMBUS_SLAVE_DATA_READ_RD_STATUS (0x3UL<<30) + #define MCPF_SMBUS_SLAVE_DATA_READ_RD_STATUS_00 (0UL<<30) + #define MCPF_SMBUS_SLAVE_DATA_READ_RD_STATUS_01 (1UL<<30) + #define MCPF_SMBUS_SLAVE_DATA_READ_RD_STATUS_10 (2UL<<30) + #define MCPF_SMBUS_SLAVE_DATA_READ_RD_STATUS_11 (3UL<<30) + u32_t unused_6[12]; + + u32_t mcpf_smbus_arp_state; + #define MCPF_SMBUS_ARP_STATE_AV_FLAG0 (1UL<<0) + #define MCPF_SMBUS_ARP_STATE_AR_FLAG0 (1UL<<1) + #define MCPF_SMBUS_ARP_STATE_AV_FLAG1 (1UL<<4) + #define MCPF_SMBUS_ARP_STATE_AR_FLAG1 (1UL<<5) + u32_t unused_7[3]; + + u32_t mcpf_smbus_udid0_3; + #define MCPF_SMBUS_UDID0_3_BYTE_12 (0xffUL<<0) + #define MCPF_SMBUS_UDID0_3_BYTE_13 (0xffUL<<8) + #define MCPF_SMBUS_UDID0_3_BYTE_14 (0xffUL<<16) + #define MCPF_SMBUS_UDID0_3_BYTE_15 (0xffUL<<24) + + u32_t mcpf_smbus_udid0_2; + #define MCPF_SMBUS_UDID0_2_BYTE_8 (0xffUL<<0) + #define MCPF_SMBUS_UDID0_2_BYTE_9 (0xffUL<<8) + #define MCPF_SMBUS_UDID0_2_BYTE_10 (0xffUL<<16) + #define MCPF_SMBUS_UDID0_2_BYTE_11 (0xffUL<<24) + + u32_t mcpf_smbus_udid0_1; + #define MCPF_SMBUS_UDID0_1_BYTE_4 (0xffUL<<0) + #define MCPF_SMBUS_UDID0_1_BYTE_5 (0xffUL<<8) + #define MCPF_SMBUS_UDID0_1_BYTE_6 (0xffUL<<16) + #define MCPF_SMBUS_UDID0_1_BYTE_7 (0xffUL<<24) + + u32_t mcpf_smbus_udid0_0; + #define MCPF_SMBUS_UDID0_0_BYTE_0 (0xffUL<<0) + #define MCPF_SMBUS_UDID0_0_BYTE_1 (0xffUL<<8) + #define MCPF_SMBUS_UDID0_0_BYTE_2 (0xffUL<<16) + #define MCPF_SMBUS_UDID0_0_BYTE_3 (0xffUL<<24) + + u32_t mcpf_smbus_udid1_3; + #define MCPF_SMBUS_UDID1_3_BYTE_12 (0xffUL<<0) + #define MCPF_SMBUS_UDID1_3_BYTE_13 (0xffUL<<8) + #define MCPF_SMBUS_UDID1_3_BYTE_14 (0xffUL<<16) + #define MCPF_SMBUS_UDID1_3_BYTE_15 (0xffUL<<24) + + u32_t mcpf_smbus_udid1_2; + #define MCPF_SMBUS_UDID1_2_BYTE_8 (0xffUL<<0) + #define MCPF_SMBUS_UDID1_2_BYTE_9 (0xffUL<<8) + #define MCPF_SMBUS_UDID1_2_BYTE_10 (0xffUL<<16) + #define MCPF_SMBUS_UDID1_2_BYTE_11 (0xffUL<<24) + + u32_t mcpf_smbus_udid1_1; + #define MCPF_SMBUS_UDID1_1_BYTE_4 (0xffUL<<0) + #define MCPF_SMBUS_UDID1_1_BYTE_5 (0xffUL<<8) + #define MCPF_SMBUS_UDID1_1_BYTE_6 (0xffUL<<16) + #define MCPF_SMBUS_UDID1_1_BYTE_7 (0xffUL<<24) + + u32_t mcpf_smbus_udid1_0; + #define MCPF_SMBUS_UDID1_0_BYTE_0 (0xffUL<<0) + #define MCPF_SMBUS_UDID1_0_BYTE_1 (0xffUL<<8) + #define MCPF_SMBUS_UDID1_0_BYTE_2 (0xffUL<<16) + #define MCPF_SMBUS_UDID1_0_BYTE_3 (0xffUL<<24) + u32_t unused_8[468]; + + u32_t mcpf_legacy_smb_asf_control; + #define MCPF_LEGACY_SMB_ASF_CONTROL_ASF_RST (1UL<<0) + #define MCPF_LEGACY_SMB_ASF_CONTROL_TSC_EN (1UL<<1) + #define MCPF_LEGACY_SMB_ASF_CONTROL_WG_TO (1UL<<2) + #define MCPF_LEGACY_SMB_ASF_CONTROL_HB_TO (1UL<<3) + #define MCPF_LEGACY_SMB_ASF_CONTROL_PA_TO (1UL<<4) + #define MCPF_LEGACY_SMB_ASF_CONTROL_PL_TO (1UL<<5) + #define MCPF_LEGACY_SMB_ASF_CONTROL_RT_TO (1UL<<6) + #define MCPF_LEGACY_SMB_ASF_CONTROL_SMB_EVENT (1UL<<7) + #define MCPF_LEGACY_SMB_ASF_CONTROL_STRETCH_EN (1UL<<8) + #define MCPF_LEGACY_SMB_ASF_CONTROL_STRETCH_PULSE (1UL<<9) + #define MCPF_LEGACY_SMB_ASF_CONTROL_RES (0x3UL<<10) + #define MCPF_LEGACY_SMB_ASF_CONTROL_SMB_EN (1UL<<12) + #define MCPF_LEGACY_SMB_ASF_CONTROL_SMB_BB_EN (1UL<<13) + #define MCPF_LEGACY_SMB_ASF_CONTROL_SMB_NO_ADDR_FILT (1UL<<14) + #define MCPF_LEGACY_SMB_ASF_CONTROL_SMB_AUTOREAD (1UL<<15) + #define MCPF_LEGACY_SMB_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fUL<<16) + #define MCPF_LEGACY_SMB_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fUL<<23) + #define MCPF_LEGACY_SMB_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1UL<<30) + #define MCPF_LEGACY_SMB_ASF_CONTROL_SMB_EARLY_ATTN (1UL<<31) + + u32_t mcpf_legacy_smb_in; + #define MCPF_LEGACY_SMB_IN_DAT_IN (0xffUL<<0) + #define MCPF_LEGACY_SMB_IN_RDY (1UL<<8) + #define MCPF_LEGACY_SMB_IN_DONE (1UL<<9) + #define MCPF_LEGACY_SMB_IN_FIRSTBYTE (1UL<<10) + #define MCPF_LEGACY_SMB_IN_STATUS (0x7UL<<11) + #define MCPF_LEGACY_SMB_IN_STATUS_OK (0UL<<11) + #define MCPF_LEGACY_SMB_IN_STATUS_PEC (1UL<<11) + #define MCPF_LEGACY_SMB_IN_STATUS_OFLOW (2UL<<11) + #define MCPF_LEGACY_SMB_IN_STATUS_STOP (3UL<<11) + #define MCPF_LEGACY_SMB_IN_STATUS_TIMEOUT (4UL<<11) + + u32_t mcpf_legacy_smb_out; + #define MCPF_LEGACY_SMB_OUT_DAT_OUT (0xffUL<<0) + #define MCPF_LEGACY_SMB_OUT_RDY (1UL<<8) + #define MCPF_LEGACY_SMB_OUT_START (1UL<<9) + #define MCPF_LEGACY_SMB_OUT_LAST (1UL<<10) + #define MCPF_LEGACY_SMB_OUT_ACC_TYPE (1UL<<11) + #define MCPF_LEGACY_SMB_OUT_ENB_PEC (1UL<<12) + #define MCPF_LEGACY_SMB_OUT_GET_RX_LEN (1UL<<13) + #define MCPF_LEGACY_SMB_OUT_SMB_READ_LEN (0x3fUL<<14) + #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS (0xfUL<<20) + #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_OK (0UL<<20) + #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1UL<<20) + #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_UFLOW (2UL<<20) + #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_STOP (3UL<<20) + #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4UL<<20) + #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5UL<<20) + #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_BADACK (6UL<<20) + #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9UL<<20) + #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (13UL<<20) + #define MCPF_LEGACY_SMB_OUT_SMB_OUT_SLAVEMODE (1UL<<24) + #define MCPF_LEGACY_SMB_OUT_SMB_OUT_DAT_EN (1UL<<25) + #define MCPF_LEGACY_SMB_OUT_SMB_OUT_DAT_IN (1UL<<26) + #define MCPF_LEGACY_SMB_OUT_SMB_OUT_CLK_EN (1UL<<27) + #define MCPF_LEGACY_SMB_OUT_SMB_OUT_CLK_IN (1UL<<28) + + u32_t mcpf_legacy_smb_watchdog; + #define MCPF_LEGACY_SMB_WATCHDOG_WATCHDOG (0xffffUL<<0) + + u32_t mcpf_legacy_smb_heartbeat; + #define MCPF_LEGACY_SMB_HEARTBEAT_HEARTBEAT (0xffffUL<<0) + + u32_t mcpf_legacy_smb_poll_asf; + #define MCPF_LEGACY_SMB_POLL_ASF_POLL_ASF (0xffffUL<<0) + + u32_t mcpf_legacy_smb_poll_legacy; + #define MCPF_LEGACY_SMB_POLL_LEGACY_POLL_LEGACY (0xffffUL<<0) + + u32_t mcpf_legacy_smb_retran; + #define MCPF_LEGACY_SMB_RETRAN_RETRAN (0xffUL<<0) + + u32_t mcpf_legacy_smb_timestamp; + #define MCPF_LEGACY_SMB_TIMESTAMP_TIMESTAMP (0xffffffffUL<<0) + u32_t unused_9[15863]; + + u32_t mcpf_ump_cmd; + #define MCPF_UMP_CMD_EGRESS_FIFO_ENABLED (1UL<<0) + #define MCPF_UMP_CMD_INGRESS_FIFO_ENABLED (1UL<<1) + #define MCPF_UMP_CMD_FC_EN (1UL<<2) + #define MCPF_UMP_CMD_MAC_LOOPBACK (1UL<<3) + #define MCPF_UMP_CMD_EGRESS_MAC_DISABLE (1UL<<5) + #define MCPF_UMP_CMD_INGRESS_MAC_DISABLE (1UL<<6) + #define MCPF_UMP_CMD_INGRESS_DRIVE (1UL<<8) + #define MCPF_UMP_CMD_SW_PAUSE (1UL<<9) + #define MCPF_UMP_CMD_AUTO_DRIVE (1UL<<13) + #define MCPF_UMP_CMD_INGRESS_RESET (1UL<<14) + #define MCPF_UMP_CMD_NO_PLUS_TWO (1UL<<15) + #define MCPF_UMP_CMD_EGRESS_PKT_FLUSH (1UL<<16) + #define MCPF_UMP_CMD_CMD_IPG (0x1fUL<<17) + #define MCPF_UMP_CMD_EGRESS_FIO_RESET (1UL<<28) + #define MCPF_UMP_CMD_INGRESS_FIO_RESET (1UL<<29) + #define MCPF_UMP_CMD_EGRESS_MAC_RESET (1UL<<30) + #define MCPF_UMP_CMD_INGRESS_MAC_RESET (1UL<<31) + + u32_t mcpf_ump_config; + #define MCPF_UMP_CONFIG_RMII_MODE (1UL<<4) + #define MCPF_UMP_CONFIG_RVMII_MODE (1UL<<6) + #define MCPF_UMP_CONFIG_INGRESS_MODE (1UL<<7) + #define MCPF_UMP_CONFIG_INGRESS_WORD_ACCM (0xffUL<<8) + + u32_t mcpf_ump_fc_trip; + #define MCPF_UMP_FC_TRIP_XON_TRIP (0x1ffUL<<0) + #define MCPF_UMP_FC_TRIP_XOFF_TRIP (0x1ffUL<<16) + u32_t unused_10[33]; + + u32_t mcpf_ump_egress_frm_rd_status; + #define MCPF_UMP_EGRESS_FRM_RD_STATUS_NEW_FRM (1UL<<0) + #define MCPF_UMP_EGRESS_FRM_RD_STATUS_FRM_IN_PRO (1UL<<1) + #define MCPF_UMP_EGRESS_FRM_RD_STATUS_FIFO_EMPTY (1UL<<2) + #define MCPF_UMP_EGRESS_FRM_RD_STATUS_BCNT (0x7ffUL<<3) + #define MCPF_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE (0x1fUL<<27) + #define MCPF_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_IDLE (0UL<<27) + #define MCPF_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_READY (1UL<<27) + #define MCPF_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_BUSY (2UL<<27) + #define MCPF_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_EXTRA_RD (3UL<<27) + #define MCPF_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_LATCH_IP_HDR (4UL<<27) + + u32_t mcpf_ump_egress_frm_rd_data; + u32_t mcpf_ump_ingress_frm_wr_ctl; + #define MCPF_UMP_INGRESS_FRM_WR_CTL_NEW_FRM (1UL<<0) + #define MCPF_UMP_INGRESS_FRM_WR_CTL_FIFO_RDY (1UL<<1) + #define MCPF_UMP_INGRESS_FRM_WR_CTL_BCNT_RDY (1UL<<2) + #define MCPF_UMP_INGRESS_FRM_WR_CTL_BCNT (0x7ffUL<<3) + #define MCPF_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE (0x3UL<<30) + #define MCPF_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_IDLE (0UL<<30) + #define MCPF_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_WAIT (1UL<<30) + #define MCPF_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_BUSY (2UL<<30) + #define MCPF_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_EXTRA_WR (3UL<<30) + + u32_t mcpf_ump_ingress_frm_wr_data; + u32_t mcpf_ump_egress_frame_type; + u32_t mcpf_ump_fifo_remaining_words; + #define MCPF_UMP_FIFO_REMAINING_WORDS_EGRESS_FIFO_DEPTH (0x7ffUL<<0) + #define MCPF_UMP_FIFO_REMAINING_WORDS_INGRESS_FIFO_DEPTH (0x3ffUL<<16) + + u32_t mcpf_ump_egress_fifo_ptrs; + #define MCPF_UMP_EGRESS_FIFO_PTRS_EGRESS_FIFO_RD_PTR (0xfffUL<<0) + #define MCPF_UMP_EGRESS_FIFO_PTRS_UPDATE_RDPTR (1UL<<15) + #define MCPF_UMP_EGRESS_FIFO_PTRS_EGRESS_FIFO_WR_PTR (0xfffUL<<16) + #define MCPF_UMP_EGRESS_FIFO_PTRS_UPDATE_WRPTR (1UL<<31) + + u32_t mcpf_ump_ingress_fifo_ptrs; + #define MCPF_UMP_INGRESS_FIFO_PTRS_INGRESS_FIFO_RD_PTR (0x7ffUL<<0) + #define MCPF_UMP_INGRESS_FIFO_PTRS_UPDATE_RDPTR (1UL<<15) + #define MCPF_UMP_INGRESS_FIFO_PTRS_INGRESS_FIFO_WR_PTR (0x7ffUL<<16) + #define MCPF_UMP_INGRESS_FIFO_PTRS_UPDATE_WRPTR (1UL<<31) + u32_t unused_11; + + u32_t mcpf_ump_egress_packet_sa_0; + #define MCPF_UMP_EGRESS_PACKET_SA_0_EGRESS_SA (0xffffUL<<0) + + u32_t mcpf_ump_egress_packet_sa_1; + #define MCPF_UMP_EGRESS_PACKET_SA_1_EGRESS_SA (0xffffffffUL<<0) + + u32_t mcpf_ump_ingress_burst_command; + #define MCPF_UMP_INGRESS_BURST_COMMAND_INGRESS_DMA_START (1UL<<0) + #define MCPF_UMP_INGRESS_BURST_COMMAND_INGRESS_PORT (1UL<<1) + #define MCPF_UMP_INGRESS_BURST_COMMAND_DMA_LENGTH (0x7ffUL<<2) + #define MCPF_UMP_INGRESS_BURST_COMMAND_RBUF_OFFSET (0x3fffUL<<16) + + u32_t mcpf_ump_ingress_rbuf_cluster; + #define MCPF_UMP_INGRESS_RBUF_CLUSTER_RBUF_CLUSTER (0x1ffffffUL<<0) + + u32_t mcpf_ump_ingress_vlan; + #define MCPF_UMP_INGRESS_VLAN_INGRESS_VLAN_TAG (0xffffUL<<0) + #define MCPF_UMP_INGRESS_VLAN_VLAN_INS (1UL<<16) + #define MCPF_UMP_INGRESS_VLAN_VLAN_DEL (1UL<<17) + + u32_t mcpf_ump_ingress_burst_status; + #define MCPF_UMP_INGRESS_BURST_STATUS_RESULT (0x3UL<<0) + #define MCPF_UMP_INGRESS_BURST_STATUS_RESULT_BUSY (0UL<<0) + #define MCPF_UMP_INGRESS_BURST_STATUS_RESULT_DONE (1UL<<0) + #define MCPF_UMP_INGRESS_BURST_STATUS_RESULT_ERR (2UL<<0) + #define MCPF_UMP_INGRESS_BURST_STATUS_RESULT_ERR1 (3UL<<0) + + u32_t mcpf_ump_egress_burst_command; + #define MCPF_UMP_EGRESS_BURST_COMMAND_EGRESS_DMA_START (1UL<<0) + #define MCPF_UMP_EGRESS_BURST_COMMAND_EGRESS_PORT (1UL<<1) + #define MCPF_UMP_EGRESS_BURST_COMMAND_DMA_LENGTH (0x7ffUL<<2) + #define MCPF_UMP_EGRESS_BURST_COMMAND_TPBUF_OFFSET (0x1fffUL<<16) + + u32_t mcpf_ump_egress_vlan; + #define MCPF_UMP_EGRESS_VLAN_EGRESS_VLAN_TAG (0xffffUL<<0) + #define MCPF_UMP_EGRESS_VLAN_VLAN_INS (1UL<<16) + #define MCPF_UMP_EGRESS_VLAN_VLAN_DEL (1UL<<17) + + u32_t mcpf_ump_egress_burst_status; + #define MCPF_UMP_EGRESS_BURST_STATUS_RESULT (0x3UL<<0) + #define MCPF_UMP_EGRESS_BURST_STATUS_RESULT_BUSY (0UL<<0) + #define MCPF_UMP_EGRESS_BURST_STATUS_RESULT_DONE (1UL<<0) + #define MCPF_UMP_EGRESS_BURST_STATUS_RESULT_ERR0 (2UL<<0) + #define MCPF_UMP_EGRESS_BURST_STATUS_RESULT_RSVD (3UL<<0) + + u32_t mcpf_ump_egress_statistic; + #define MCPF_UMP_EGRESS_STATISTIC_EGRESS_GOOD_CNT (0xffffUL<<0) + #define MCPF_UMP_EGRESS_STATISTIC_EGRESS_ERROR_CNT (0xffUL<<16) + #define MCPF_UMP_EGRESS_STATISTIC_EGRESS_DROP_CNT (0xffUL<<24) + + u32_t mcpf_ump_ingress_statistic; + #define MCPF_UMP_INGRESS_STATISTIC_INGRESS_PKT_CNT (0xffffUL<<0) + + u32_t mcpf_ump_arb_cmd; + #define MCPF_UMP_ARB_CMD_UMP_ID (0x7UL<<0) + #define MCPF_UMP_ARB_CMD_UMP_ARB_DISABLE (1UL<<4) + #define MCPF_UMP_ARB_CMD_UMP_ARB_START (1UL<<5) + #define MCPF_UMP_ARB_CMD_UMP_ARB_BYPASS (1UL<<6) + #define MCPF_UMP_ARB_CMD_UMP_ARB_AUTOBYPASS (1UL<<7) + #define MCPF_UMP_ARB_CMD_UMP_ARB_TOKEN_IPG (0x1fUL<<8) + #define MCPF_UMP_ARB_CMD_UMP_ARB_TOKEN_VALID (1UL<<13) + #define MCPF_UMP_ARB_CMD_UMP_ARB_FC_DISABLE (1UL<<15) + #define MCPF_UMP_ARB_CMD_UMP_ARB_TIMEOUT (0xffffUL<<16) + u32_t unused_12[3]; + + u32_t mcpf_ump_egress_statistic_ac; + #define MCPF_UMP_EGRESS_STATISTIC_AC_EGRESS_GOOD_CNT (0xffffUL<<0) + #define MCPF_UMP_EGRESS_STATISTIC_AC_EGRESS_ERROR_CNT (0xffUL<<16) + #define MCPF_UMP_EGRESS_STATISTIC_AC_EGRESS_DROP_CNT (0xffUL<<24) + + u32_t mcpf_ump_ingress_statistic_ac; + #define MCPF_UMP_INGRESS_STATISTIC_AC_INGRESS_PKT_CNT (0xffffUL<<0) + + u32_t mcpf_ump_event; + #define MCPF_UMP_EVENT_INGRESS_RDY_EVENT (1UL<<0) + #define MCPF_UMP_EVENT_EGRESS_RDY_EVENT (1UL<<1) + #define MCPF_UMP_EVENT_INGRESSBURST_DONE_EVENT (1UL<<2) + #define MCPF_UMP_EVENT_EGRESSBURST_DONE_EVENT (1UL<<3) + #define MCPF_UMP_EVENT_EGRESS_FRAME_DROP_EVENT (1UL<<4) + #define MCPF_UMP_EVENT_INGRESS_RDY_EVENT_EN (1UL<<16) + #define MCPF_UMP_EVENT_EGRESS_RDY_EVENT_EN (1UL<<17) + #define MCPF_UMP_EVENT_INGRESSBURST_DONE_EVENT_EN (1UL<<18) + #define MCPF_UMP_EVENT_EGRESSBURST_DONE_EVENT_EN (1UL<<19) + #define MCPF_UMP_EVENT_EGRESS_FRAME_DROP_EVENT_EN (1UL<<20) + u32_t unused_13[4033]; + + u32_t mcpf_ump_egress_fifo_flat_space[1920]; + u32_t unused_14[128]; + u32_t mcpf_ump_ingress_fifo_flat_space[768]; +} mcp_fio_xi_t; + + + + + + + +/* + * msqe_b definition + */ +typedef struct msqe_b +{ + u8_t msqe_cmd_type; + u8_t msqe_retx_num; + u16_t msqe_ctx_index; + u32_t msqe_tcp_seq; +} msqe_b_t; + + + +/* + * msqe_b definition + */ +typedef struct msqe_b_xi +{ + u8_t msqe_cmd_type; + u8_t msqe_retx_num; + u16_t msqe_ctx_index; + u32_t msqe_tcp_seq; +} msqe_b_xi_t; + + +/* + * msqe_l definition + */ +typedef struct msqe_l +{ + u16_t msqe_ctx_index; + u8_t msqe_retx_num; + u8_t msqe_cmd_type; + u32_t msqe_tcp_seq; +} msqe_l_t; + + + +/* + * msqe_l definition + */ +typedef struct msqe_l_xi +{ + u16_t msqe_ctx_index; + u8_t msqe_retx_num; + u8_t msqe_cmd_type; + u32_t msqe_tcp_seq; +} msqe_l_xi_t; + + +/* + * msqe select + */ +#if defined(LITTLE_ENDIAN) + typedef msqe_l_t msqe_t; + typedef msqe_l_xi_t msqe_xi_t; +#elif defined(BIG_ENDIAN) + typedef msqe_b_t msqe_t; + typedef msqe_b_xi_t msqe_xi_t; +#endif + + +/* + * msq_context_b definition + */ +typedef struct msq_context_b +{ + u8_t msq_ctx_type; + + u8_t msq_ctx_size; + u8_t msq_pidx; + u8_t msq_cidx; + u32_t msq_joe; + msqe_b_t msq_q[15]; +} msq_context_b_t; + + + +/* + * msq_context_b definition + */ +typedef struct msq_context_b_xi +{ + u8_t msq_ctx_type; + #define MSQ_CTX_TYPE_TYPE (0xf<<4) + #define MSQ_CTX_TYPE_TYPE_EMPTY (0<<4) + #define MSQ_CTX_TYPE_TYPE_L2 (1<<4) + #define MSQ_CTX_TYPE_TYPE_TCP (2<<4) + #define MSQ_CTX_TYPE_TYPE_L5 (3<<4) + #define MSQ_CTX_TYPE_TYPE_L2_BD_CHN (4<<4) + #define MSQ_CTX_TYPE_TYPE_CP_MSG (5<<4) + + u8_t msq_ctx_size; + u8_t msq_pidx; + u8_t msq_cidx; + u32_t msq_joe; + msqe_b_xi_t msq_q[15]; +} msq_context_b_xi_t; + + +/* + * msq_context_l definition + */ +typedef struct msq_context_l +{ + u8_t msq_cidx; + u8_t msq_pidx; + u8_t msq_ctx_size; + u8_t msq_ctx_type; + + u32_t msq_joe; + msqe_l_t msq_q[15]; +} msq_context_l_t; + + + +/* + * msq_context_l definition + */ +typedef struct msq_context_l_xi +{ + u8_t msq_cidx; + u8_t msq_pidx; + u8_t msq_ctx_size; + u8_t msq_ctx_type; + #define MSQ_CTX_TYPE_TYPE (0xf<<4) + #define MSQ_CTX_TYPE_TYPE_EMPTY (0<<4) + #define MSQ_CTX_TYPE_TYPE_L2 (1<<4) + #define MSQ_CTX_TYPE_TYPE_TCP (2<<4) + #define MSQ_CTX_TYPE_TYPE_L5 (3<<4) + #define MSQ_CTX_TYPE_TYPE_L2_BD_CHN (4<<4) + #define MSQ_CTX_TYPE_TYPE_CP_MSG (5<<4) + + u32_t msq_joe; + msqe_l_xi_t msq_q[15]; +} msq_context_l_xi_t; + + +/* + * msq_context select + */ +#if defined(LITTLE_ENDIAN) + typedef msq_context_l_t msq_context_t; + typedef msq_context_l_xi_t msq_context_xi_t; +#elif defined(BIG_ENDIAN) + typedef msq_context_b_t msq_context_t; + typedef msq_context_b_xi_t msq_context_xi_t; +#endif + + +#define ROFFSET(_field) \ + ((u32_t) (((u8_t *) &(((reg_space_t *) 0)->_field)) - ((u8_t *) 0))) + +/* + * TX header Q and payload Q + */ +#define HDRQ_NBYTES (1<<13) +#define HDRQ_MASK (u16_t)(HDRQ_NBYTES - 1) +#define PLDQ_NBYTES (1<<13) +#define PLDQ_MASK (u32_t)(PLDQ_NBYTES - 1) + + +#endif + diff --git a/usr/src/uts/common/io/bnx/570x/common/include/com_hsi.h b/usr/src/uts/common/io/bnx/570x/common/include/com_hsi.h new file mode 100644 index 0000000000..c9897c508e --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/com_hsi.h @@ -0,0 +1,168 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _COM_HSI_H +#define _COM_HSI_H + +// Offset of xxx_hsi in 32 bit words from beginning of scratchpad +#define COM_HSI_OFFSET 0x4 + +typedef struct _com_hsi_t { + fw_version_t version; + u32_t fw_doorbell; + #define KCQ_READY (1<<0) + #define KCQ1_READY (1<<1) + #define KCQ2_READY (1<<2) + #define KCQ3_READY (1<<3) + u32_t dups; + u32_t dacks; + u32_t pushs; + u32_t compbits; + u32_t num_comq; + u32_t num_comtq; + u32_t num_comxq; + u32_t unused_num_fail_reloads; + u32_t rx_place; + u32_t rtxs; // max_retx_cnt : maximum number of tcp retries + u32_t min_rto_tick; // min_rto (in ticks of retx timer) + u32_t max_rto_tick; // max_rto (in ticks of retx timer) + u32_t max_caf; // max allowed ack frequency + u32_t false_ooo_fin_cnt; + u32_t l2_forward_to_mcp; + u32_t l2_drop_mcpq_busy; + u32_t drtxs; // doubt reacheability tx count threshold (rfc 2923) + // drtxs - maximum number of times that the offload target should + // retransmit a segment before indicating to the host stack that + // the reachability of a neighbor is in doubt. + u32_t abort_ooo_fin_cnt; + u32_t total_ooo_fin_cnt; + u32_t caus; + u32_t dtic; + u32_t defer_ooo_fin_cnt; + u32_t l4_drop_cnt; // number of l4 packets dropped by RV2P + u32_t cozr; + u32_t com_l2_no_buffer; + u32_t com_cu_host_bseq; + u32_t tnda; + u32_t tcnas; + u32_t tccas; + u32_t caf; // ack frequency + u32_t cmpl_dbg_cnt; + u32_t hcwa_kwq_cons_idx; + u32_t hcwa_last_kwq_cons_idx; + u32_t eaiv; + u32_t reload_aft_fin_cnt; // Number of reload after FIN + u32_t enable_fast_iscsi_response; + u32_t tsch_restart; + u64_t volatile idle_count; + u32_t iscsi_rtxs; // Number of retransmissions in iSCSI + u32_t iscsi_cq_size; // Number of elements in queue. Its k lsb bits must be 0. bit 0 - arm bit - means CQ is armed + u32_t iscsi_cq_cqes_per_page; // Number of CQEs per page + u32_t iscsi_cq_num_pages; // Number of pages of CQ ( = entries in page table) + u32_t iscsi_cq_cqes_per_page_log2; // Log2 of the Number of CQEs per page + u32_t iscsi_data_dig_err; // Indication on Error="1" / Warning="0" of data digest + u32_t iscsi_tcp_config; // Configuration register - Enable/Disable of DA/KA mechanisms + u32_t iscsi_teton_l4_cmd_offset; // Teton Only: offset of L4 ccell command array + u32_t iscsi_teton_l5_offset; // Teton Only: offset of L5 section + u32_t iscsi_teton_l5_cmd_offset; // Teton Only: offset of L5 ccell command array + u32_t iscsi_task_offset; // offset of the task array + u32_t iscsi_r2tq_offset; // offset of R2TQ section + u32_t iscsi_max_num_of_tasks; // maximal number of pending tasks + u32_t iscsi_max_num_of_ccells; // maximal number of ccells + u32_t com_cu_buf_size; + u32_t com_l2_iscsi_no_buffer; + u32_t com_unicast_no_buffer; + u32_t com_mcast_no_buffer; + u32_t com_bcast_no_buffer; + u32_t l2_drop_pkt_cnt; // keep tracks of packet drop requested by RXP (e.g. not enough bytes in BD to place the pkt) + u32_t com_cu_free_cnt; + u32_t cu_rate_limiter_enable; +}com_hsi_t; + +// This macro can be used for little or big endian 32-bit system +#define COM_HSI_OFFSETOFF(m) (OFFSETOF(com_hsi_t,m) + 0x10) +#define COM_HSI_SIZEOF(m) (sizeof (((com_hsi_t *)0)->m)) + +// Calling the following macro will actually get optimized during compile +// time. Its sole purpose is to ensure HSI variables cannot be modified/moved +// unnoticed scratch[10240] 0x120000 (RW/Reset: undefined) +#define TEST_COM_HSI(){ \ +if (0){ \ + 1/(COM_HSI_OFFSETOFF(version) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x000) && \ + COM_HSI_OFFSETOFF(fw_doorbell) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x010) && \ + COM_HSI_OFFSETOFF(dups) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x014) && \ + COM_HSI_OFFSETOFF(dacks) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x018) && \ + COM_HSI_OFFSETOFF(pushs) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x01c) && \ + COM_HSI_OFFSETOFF(compbits) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x020) && \ + COM_HSI_OFFSETOFF(num_comq) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x024) && \ + COM_HSI_OFFSETOFF(num_comtq) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x028) && \ + COM_HSI_OFFSETOFF(num_comxq) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x02c) && \ + COM_HSI_OFFSETOFF(unused_num_fail_reloads) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x030) && \ + COM_HSI_OFFSETOFF(rx_place) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x034) && \ + COM_HSI_OFFSETOFF(rtxs) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x038) && \ + COM_HSI_OFFSETOFF(min_rto_tick) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x03c) && \ + COM_HSI_OFFSETOFF(max_rto_tick) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x040) && \ + COM_HSI_OFFSETOFF(max_caf) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x044) && \ + COM_HSI_OFFSETOFF(false_ooo_fin_cnt) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x048) && \ + COM_HSI_OFFSETOFF(l2_forward_to_mcp) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x04c) && \ + COM_HSI_OFFSETOFF(l2_drop_mcpq_busy) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x050) && \ + COM_HSI_OFFSETOFF(drtxs) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x054) && \ + COM_HSI_OFFSETOFF(abort_ooo_fin_cnt) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x058) && \ + COM_HSI_OFFSETOFF(total_ooo_fin_cnt) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x05c) && \ + COM_HSI_OFFSETOFF(caus) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x060) && \ + COM_HSI_OFFSETOFF(dtic) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x064) && \ + COM_HSI_OFFSETOFF(defer_ooo_fin_cnt) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x068) && \ + COM_HSI_OFFSETOFF(l4_drop_cnt) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x06c) && \ + COM_HSI_OFFSETOFF(cozr) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x070) && \ + COM_HSI_OFFSETOFF(com_l2_no_buffer) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x074) && \ + COM_HSI_OFFSETOFF(com_cu_host_bseq) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x078) && \ + COM_HSI_OFFSETOFF(tnda) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x07c) && \ + COM_HSI_OFFSETOFF(tcnas) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x080) && \ + COM_HSI_OFFSETOFF(tccas) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x084) && \ + COM_HSI_OFFSETOFF(caf) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x088) && \ + COM_HSI_OFFSETOFF(cmpl_dbg_cnt) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x08c) && \ + COM_HSI_OFFSETOFF(hcwa_kwq_cons_idx) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x090) && \ + COM_HSI_OFFSETOFF(hcwa_last_kwq_cons_idx) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x094) && \ + COM_HSI_OFFSETOFF(eaiv) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x098) && \ + COM_HSI_OFFSETOFF(reload_aft_fin_cnt) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x09c) && \ + COM_HSI_OFFSETOFF(enable_fast_iscsi_response) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0a0) && \ + COM_HSI_OFFSETOFF(tsch_restart) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0a4) && \ + COM_HSI_OFFSETOFF(idle_count) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0a8) && \ + COM_HSI_OFFSETOFF(iscsi_rtxs) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0b0) && \ + COM_HSI_OFFSETOFF(iscsi_cq_size) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0b4) && \ + COM_HSI_OFFSETOFF(iscsi_cq_cqes_per_page) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0b8) && \ + COM_HSI_OFFSETOFF(iscsi_cq_num_pages) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0bc) && \ + COM_HSI_OFFSETOFF(iscsi_cq_cqes_per_page_log2) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0c0) && \ + COM_HSI_OFFSETOFF(iscsi_data_dig_err) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0c4) && \ + COM_HSI_OFFSETOFF(iscsi_tcp_config) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0c8) && \ + COM_HSI_OFFSETOFF(iscsi_teton_l4_cmd_offset) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0cc) && \ + COM_HSI_OFFSETOFF(iscsi_teton_l5_offset) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0d0) && \ + COM_HSI_OFFSETOFF(iscsi_teton_l5_cmd_offset) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0d4) && \ + COM_HSI_OFFSETOFF(iscsi_task_offset) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0d8) && \ + COM_HSI_OFFSETOFF(iscsi_r2tq_offset) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0dc) && \ + COM_HSI_OFFSETOFF(iscsi_max_num_of_tasks) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0e0) && \ + COM_HSI_OFFSETOFF(iscsi_max_num_of_ccells) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0e4) && \ + COM_HSI_OFFSETOFF(com_cu_buf_size) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0e8) && \ + COM_HSI_OFFSETOFF(com_l2_iscsi_no_buffer) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0ec) && \ + COM_HSI_OFFSETOFF(com_unicast_no_buffer) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0f0) && \ + COM_HSI_OFFSETOFF(com_mcast_no_buffer) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0f4) && \ + COM_HSI_OFFSETOFF(com_bcast_no_buffer) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0f8) && \ + COM_HSI_OFFSETOFF(l2_drop_pkt_cnt) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x0fc) && \ + COM_HSI_OFFSETOFF(com_cu_free_cnt) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x100) && \ + COM_HSI_OFFSETOFF(cu_rate_limiter_enable) == (COM_HSI_OFFSET * sizeof(u32_t) + 0x104) && \ + COM_HSI_OFFSETOFF(cu_rate_limiter_enable)+COM_HSI_SIZEOF(cu_rate_limiter_enable) == (COM_HSI_OFFSET * sizeof(u32_t) + sizeof(com_hsi_t)));}} + +#endif + diff --git a/usr/src/uts/common/io/bnx/570x/common/include/cp_hsi.h b/usr/src/uts/common/io/bnx/570x/common/include/cp_hsi.h new file mode 100644 index 0000000000..d9cf4ab973 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/cp_hsi.h @@ -0,0 +1,125 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _CP_HSI_H +#define _CP_HSI_H + +// Offset of xxx_hsi in 32 bit words from beginning of scratchpad +#define CP_HSI_OFFSET 0x4 + +typedef struct _fio_dbg_b_t { + u8_t cpu_src; + u8_t is_read; + u16_t fio_addr; + u32_t fio_data; +}fio_dbg_b_t; + +typedef struct _fio_dbg_l_t { + u16_t fio_addr; + u8_t is_read; + u8_t cpu_src; + u32_t fio_data; +}fio_dbg_l_t; + +#if defined(LITTLE_ENDIAN) + typedef fio_dbg_l_t fio_dbg_t; +#elif defined(BIG_ENDIAN) + typedef fio_dbg_b_t fio_dbg_t; +#endif + +/* + * Runtime Configurable Parameters + */ +typedef struct _cp_hsi_t { + fw_version_t version; + u32_t fw_doorbell; + #define KWQ_READY (1<<0) + #define KWQ1_READY (1<<1) + #define KWQ2_READY (1<<2) + #define KWQ3_READY (1<<3) + u32_t iscsi_sq_size; // Number of elements in queue. Its k lsb bits must be 0. + u32_t cp_cpq_kwq[2]; + u32_t iscsi_xinan_unit; // Xinan only: number of VCIDs for an iscsi connection + u32_t pg_ctx_map; /* Xinan only: pg ctx start and end */ + u64_t volatile idle_count; + u32_t iscsi_sq_wqes_per_page; // Number of WQEs per page + u32_t iscsi_sq_num_pages; // Number of pages ( = entries in SQ page table) + u32_t cp_gen_bd_max; + u32_t iscsi_teton_l4_cmd_offset; // Teton Only: offset of L4 ccell command array + u32_t iscsi_teton_l5_offset; // Teton Only: offset of L5 section + u32_t iscsi_teton_l5_cmd_offset; // Teton Only: offset of L5 ccell command array + u32_t iscsi_task_offset; // offset of the task array + u32_t iscsi_r2tq_offset; // offset of R2TQ section + u32_t iscsi_max_num_of_tasks; // maximal number of pending tasks + u32_t iscsi_max_num_of_ccells; // maximal number of ccells + u32_t iscsi_dbg_ctx_addr_h; + u32_t iscsi_dbg_ctx_addr_l; + u32_t iscsi_dbg_ctx_cid; + u32_t iscsi_ctx_map; /* Xinan only: iscsi ctx start and end */ + u32_t num_tcp_nagle_allow; /* threshold of num of TOE conn that we allow + for stricter tcp nagle alogrithm. */ + u32_t timer_scan_freq; /* Xinan only: control timer scan frequency */ + u32_t iscsi_max_conn; /* Read only parameter for the host to read */ + u32_t num_kwqe_limit; /* restrict number kwqes to be process per dma */ + u32_t idle_ts_period; /* time slice period for each tasks during idle loop */ + u32_t toe_ofld_retx_cnt; /* Number of TOE connections that is oflded with retx */ + fio_dbg_t fio_dbg_info; /* for debugging fio access */ + u32_t l2_cid_cnt; /* Track erroneous cpq entry */ + u32_t unused; +}cp_hsi_t; + + +// This macro can be used for little or big endian 32-bit system +#define CP_HSI_OFFSETOFF(m) (OFFSETOF(cp_hsi_t,m) + 0x10) +#define CP_HSI_SIZEOF(m) (sizeof (((cp_hsi_t *)0)->m)) + +// Calling the following macro will actually get optimized during compile +// time. Its sole purpose is to ensure HSI variables cannot be modified/moved +// unnoticed scratch[10240] 0x1a0000 (RW/Reset: undefined) +#define TEST_CP_HSI(){ \ +if (0){ \ + 1/(CP_HSI_OFFSETOFF(version) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x000) && \ + CP_HSI_OFFSETOFF(fw_doorbell) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x010) && \ + CP_HSI_OFFSETOFF(iscsi_sq_size) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x014) && \ + CP_HSI_OFFSETOFF(cp_cpq_kwq[0]) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x018) && \ + CP_HSI_OFFSETOFF(cp_cpq_kwq[1]) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x01c) && \ + CP_HSI_OFFSETOFF(iscsi_xinan_unit) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x020) && \ + CP_HSI_OFFSETOFF(pg_ctx_map) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x024) && \ + CP_HSI_OFFSETOFF(idle_count) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x028) && \ + CP_HSI_OFFSETOFF(iscsi_sq_wqes_per_page) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x030) && \ + CP_HSI_OFFSETOFF(iscsi_sq_num_pages) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x034) && \ + CP_HSI_OFFSETOFF(cp_gen_bd_max) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x038) && \ + CP_HSI_OFFSETOFF(iscsi_teton_l4_cmd_offset) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x03c) && \ + CP_HSI_OFFSETOFF(iscsi_teton_l5_offset) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x040) && \ + CP_HSI_OFFSETOFF(iscsi_teton_l5_cmd_offset) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x044) && \ + CP_HSI_OFFSETOFF(iscsi_task_offset) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x048) && \ + CP_HSI_OFFSETOFF(iscsi_r2tq_offset) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x04c) && \ + CP_HSI_OFFSETOFF(iscsi_max_num_of_tasks) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x050) && \ + CP_HSI_OFFSETOFF(iscsi_max_num_of_ccells) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x054) && \ + CP_HSI_OFFSETOFF(iscsi_dbg_ctx_addr_h) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x058) && \ + CP_HSI_OFFSETOFF(iscsi_dbg_ctx_addr_l) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x05c) && \ + CP_HSI_OFFSETOFF(iscsi_dbg_ctx_cid) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x060) && \ + CP_HSI_OFFSETOFF(iscsi_ctx_map) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x064) && \ + CP_HSI_OFFSETOFF(num_tcp_nagle_allow) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x068) && \ + CP_HSI_OFFSETOFF(timer_scan_freq) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x06c) && \ + CP_HSI_OFFSETOFF(iscsi_max_conn) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x070) && \ + CP_HSI_OFFSETOFF(num_kwqe_limit) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x074) && \ + CP_HSI_OFFSETOFF(idle_ts_period) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x078) && \ + CP_HSI_OFFSETOFF(toe_ofld_retx_cnt) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x07c) && \ + CP_HSI_OFFSETOFF(fio_dbg_info) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x080) && \ + CP_HSI_OFFSETOFF(l2_cid_cnt) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x088) && \ + CP_HSI_OFFSETOFF(unused) == (CP_HSI_OFFSET * sizeof(u32_t) + 0x08C) && \ + CP_HSI_OFFSETOFF(unused)+CP_HSI_SIZEOF(unused) == (CP_HSI_OFFSET * sizeof(u32_t) + sizeof(cp_hsi_t)));}} + +#endif diff --git a/usr/src/uts/common/io/bnx/570x/common/include/l2_defs.h b/usr/src/uts/common/io/bnx/570x/common/include/l2_defs.h new file mode 100644 index 0000000000..880bfe2bd8 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/l2_defs.h @@ -0,0 +1,550 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _l2_defs_h_ +#define _l2_defs_h_ + + +typedef struct tx_bidx_boff_b{ + u16_t bidx; + u16_t boff; +}tx_bidx_boff_b_t; + +typedef struct tx_bidx_boff_l{ + u16_t boff; + u16_t bidx; +}tx_bidx_boff_l_t; + +#if defined(LITTLE_ENDIAN) + typedef tx_bidx_boff_l_t tx_bidx_boff_t; +#elif defined(BIG_ENDIAN) + typedef tx_bidx_boff_b_t tx_bidx_boff_t; +#endif + + +typedef struct bd_scan_b{ + u32_t cmd; + + u32_t len; + + u16_t flags; + u16_t vlan_tag; + u16_t reserved; + u16_t unused_13; + tx_bidx_boff_t bidx_boff_current; + tx_bidx_boff_t bidx_boff_prev; + u32_t bseq_current; + u32_t bseq_prev; +}bd_scan_b_t; + +typedef struct bd_scan_l{ + u32_t cmd; + + u32_t len; + + u16_t vlan_tag; + u16_t flags; + + u16_t unused_13; + u16_t reserved; + tx_bidx_boff_t bidx_boff_current; + tx_bidx_boff_t bidx_boff_prev; + u32_t bseq_current; + u32_t bseq_prev; +}bd_scan_l_t; + +#if defined(LITTLE_ENDIAN) + typedef bd_scan_l_t bd_scan_t; +#elif defined(BIG_ENDIAN) + typedef bd_scan_b_t bd_scan_t; +#endif + + +#if defined(LITTLE_ENDIAN) +struct idx16_fields_t { + u16_t idx : 15; + u16_t msb : 1; +}; +#elif defined(BIG_ENDIAN) +struct idx16_fields_t { + u16_t msb : 1; + u16_t idx : 15; +}; +#endif + +union idx16_union_t { + struct idx16_fields_t fields; + u16_t idx16; +}; + +// Refer to Timer Architecture document. +// The timers have different sizes, however, the LSB of each timer indicates +// whether the timer is armed or dis-armed (a value of '1' indicates that the +// timer is dis-armed, a value of '0' indicates that the timer is armed). The +// MSB of each timer indicates whether the timer value has rolled over during +// the course of operation. Thus a 32-bit timer is essentially a 30-bit timer +// with the MSB and LSB used for different purposes. +#define MAX_TMR1_CNT_LIMIT 0x3FFFFFFF // 30-bit timer +#define TMR1_TICKS_PER_SEC 1000 +#define TMR1_MSEC(x) \ + ((u32_t)((x) * TMR1_TICKS_PER_SEC/1000) ? \ + (u32_t)((x) * TMR1_TICKS_PER_SEC/1000) : 1) + +#define MAX_TMR2_CNT_LIMIT 0x3FFF // 14-bit timer +#define TMR2_TICKS_PER_SEC 100 +#define TMR2_MSEC(x) \ + ((u32_t)((x) * TMR2_TICKS_PER_SEC/1000) ? \ + (u32_t)((x) * TMR2_TICKS_PER_SEC/1000) : 1) + +#define MAX_TMR3_CNT_LIMIT 0x3FFF // 14-bit timer +#define TMR3_TICKS_PER_SEC 1000 +#define TMR3_MSEC(x) \ + ((u32_t)((x) * TMR3_TICKS_PER_SEC/1000) ? \ + (u32_t)((x) * TMR3_TICKS_PER_SEC/1000) : 1) + +#define MAX_TMR4_CNT_LIMIT 0x3FFF // 14-bit timer +#define TMR4_TICKS_PER_SEC 10 +#define TMR4_MSEC(x) \ + ((u32_t)((x) * TMR4_TICKS_PER_SEC/1000) ? \ + (u32_t)((x) * TMR4_TICKS_PER_SEC/1000) : 1) + +#define MAX_TMR5_CNT_LIMIT 0x3FFF // 14-bit timer +#define TMR5_TICKS_PER_SEC 10000 +#define TMR5_MSEC(x) \ + ((u32_t)((x) * TMR5_TICKS_PER_SEC/1000) ? \ + (u32_t)((x) * TMR5_TICKS_PER_SEC/1000) : 1) + + +/* + * l2_bd_chain_context_b definition + */ +typedef struct l2_bd_chain_context_b +{ + u8_t l2ctx_ctx_type; + #define L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<4) + #define L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<4) + #define L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<4) + + u8_t l2ctx_ctx_size; + u8_t l2ctx_bd_pre_read; + // L2 flow control watermarks b0-b3 and b4-b7 are the low and high + // watermark respectively + u8_t l2ctx_watermarks; + u8_t l2ctx_sb_num; + u8_t l2ctx_krnlq_id; + u16_t l2ctx_host_bdidx; + u32_t l2ctx_host_bseq; + u32_t l2ctx_nx_bseq; + u32_t l2ctx_nx_bdhaddr_hi; + u32_t l2ctx_nx_bdhaddr_lo; + u16_t l2ctx_v2p_flags; + // only valid in Linux for Flow control (maintained by RV2P) + #define L2CTX_V2P_FLAGS_PAUSE (1<<0) + u16_t l2ctx_nx_bdidx; + u8_t unused_1; + u8_t l2ctx_queue_type; + u8_t l2ctx_filter_type; + u8_t reserved; + u16_t unused_2; + u16_t l2ctx_max_pkt_len; // max L2 pkt length the RX BD can accomodate + u32_t unused[7]; + u16_t l2ctx_vmq_lookahead_sz; /* VMQ look ahead size */ + // Following fields are for LINUX only (jumbo pkt mode) + u8_t l2ctx_pg_bd_pre_read; + u8_t unused_4; + u16_t unused_5; + u16_t l2ctx_host_pg_bidx; + u16_t l2ctx_skb_buf_size; + u16_t l2ctx_pg_buf_size; + u16_t unused_6; + u16_t l2ctx_rbdc_key; + u32_t l2ctx_nx_pg_bdhaddr_hi; + u32_t l2ctx_nx_pg_bdhaddr_lo; + u16_t unused_7; + u16_t l2ctx_nx_pg_bdidx; + u32_t unused_8[9]; +} l2_bd_chain_context_b_t; + + +/* + * l2_bd_chain_context_l definition + */ +typedef struct l2_bd_chain_context_l +{ + // L2 flow control watermarks b0-b3 and b4-b7 are the low and high + // watermark respectively (Linux L2 flow control only) + u8_t l2ctx_watermarks; + u8_t l2ctx_bd_pre_read; + u8_t l2ctx_ctx_size; + u8_t l2ctx_ctx_type; + #define L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<4) + #define L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<4) + #define L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<4) + + u16_t l2ctx_host_bdidx; + u8_t l2ctx_krnlq_id; + u8_t l2ctx_sb_num; // Linux only + u32_t l2ctx_host_bseq; + u32_t l2ctx_nx_bseq; + u32_t l2ctx_nx_bdhaddr_hi; + u32_t l2ctx_nx_bdhaddr_lo; + u16_t l2ctx_nx_bdidx; + u16_t l2ctx_v2p_flags; + // only valid in Linux for Flow control (maintained by RV2P) + #define L2CTX_V2P_FLAGS_PAUSE (1<<0) + u8_t reserved; + u8_t l2ctx_filter_type; + u8_t l2ctx_queue_type; + u8_t unused_1; + u16_t l2ctx_max_pkt_len; // max L2 pkt length the RX BD can accomodate + u16_t unused_2; + u32_t unused[7]; + u8_t unused_4; + u8_t l2ctx_pg_bd_pre_read; // Linux jumbo pkt mode only + u16_t l2ctx_vmq_lookahead_sz; + // Following fields are for LINUX only (jumbo pkt mode) + u16_t l2ctx_host_pg_bidx; + u16_t unused_5; + u16_t l2ctx_pg_buf_size; + u16_t l2ctx_skb_buf_size; + u16_t l2ctx_rbdc_key; + u16_t unused_6; + u32_t l2ctx_nx_pg_bdhaddr_hi; + u32_t l2ctx_nx_pg_bdhaddr_lo; + u16_t l2ctx_nx_pg_bdidx; + u16_t unused_7; + u32_t unused_8[9]; +} l2_bd_chain_context_l_t; + + +/* + * l2_bd_chain_context select + */ +#if defined(LITTLE_ENDIAN) + typedef l2_bd_chain_context_l_t l2_bd_chain_context_t; +#elif defined(BIG_ENDIAN) +#if defined(CONFIG_PPC64) || defined(__sparc) + typedef l2_bd_chain_context_l_t l2_bd_chain_context_t; +#else + typedef l2_bd_chain_context_b_t l2_bd_chain_context_t; +#endif +#endif + +/* + * tcp_context_cmd_cell_b_te definition + */ +typedef struct tcp_context_cmd_cell_b_te +{ + u8_t ccell_cmd_type; + + u8_t ccell_est_nbd; + u16_t ccell_tx_host_bidx; + u32_t ccell_tx_mss; + + u32_t ccell_tx_host_bseq; + u32_t ccell_tsch_bseq; + u32_t ccell_tbdr_bseq; + tx_bidx_boff_t ccell_tbdr_bidx_boff; +#if defined(_ANSI_C_) + // compiler switch is to avoid complaints from some ANSI compilers + // (e.g. Solaris) that don't support unnamed union + struct { + u32_t hi; + u32_t lo; + } ccell_tbdr_bhaddr; +#else + union { + struct { + u32_t ccell_tbdr_bhaddr_hi; + u32_t ccell_tbdr_bhaddr_lo; + }; + u64_t ccell_tbdr_bhaddr; + }; +#endif + tx_bidx_boff_t ccell_txp_bidx_boff; + u32_t ccell_txp_bseq; +} tcp_context_cmd_cell_b_te_t; + + + +/* + * tcp_context_cmd_cell_l_te definition + */ +typedef struct tcp_context_cmd_cell_l_te +{ + u16_t ccell_tx_host_bidx; + u8_t ccell_est_nbd; + u8_t ccell_cmd_type; + u32_t ccell_tx_mss; + + u32_t ccell_tx_host_bseq; + u32_t ccell_tsch_bseq; + u32_t ccell_tbdr_bseq; + tx_bidx_boff_t ccell_tbdr_bidx_boff; + struct { + u32_t hi; + u32_t lo; + } ccell_tbdr_bhaddr; + tx_bidx_boff_t ccell_txp_bidx_boff; + u32_t ccell_txp_bseq; +} tcp_context_cmd_cell_l_te_t; + + +typedef struct tcp_context_cmd_cell_b_xi +{ + u8_t ccell_cmd_type; + #define CCELL_CMD_TYPE_TYPE (0xf<<0) + #define CCELL_CMD_TYPE_TYPE_L2 (0<<0) + #define CCELL_CMD_TYPE_TYPE_TCP (1<<0) + #define CCELL_CMD_TYPE_TYPE_L5_CHAIN (2<<0) + #define CCELL_CMD_TYPE_TYPE_SEND_L5_PGTBL (3<<0) + #define CCELL_CMD_TYPE_TYPE_WRITE_L5_PGTBL (4<<0) + #define CCELL_CMD_TYPE_TYPE_RDREQ_L5_PGTBL (5<<0) + #define CCELL_CMD_TYPE_TYPE_L5_DONOTHING (6<<0) + #define CCELL_CMD_TYPE_TYPE_7_L5_PGTBL (7<<0) + #define CCELL_CMD_TYPE_TYPE_8_CHAIN (8<<0) + #define CCELL_CMD_TYPE_TYPE_9_CHAIN (9<<0) + #define CCELL_CMD_TYPE_TYPE_10_CHAIN (10<<0) + #define CCELL_CMD_TYPE_TYPE_11_PGTBL (11<<0) + #define CCELL_CMD_TYPE_TYPE_12_PGTBL (12<<0) + #define CCELL_CMD_TYPE_TYPE_13_PGTBL (13<<0) + #define CCELL_CMD_TYPE_TYPE_14_PGTBL (14<<0) + #define CCELL_CMD_TYPE_TYPE_15_PGTBL (15<<0) + #define CCELL_CMD_TYPE_PG_SZ (0xf<<4) + #define CCELL_CMD_TYPE_PG_SZ_256 (0<<4) + #define CCELL_CMD_TYPE_PG_SZ_512 (1<<4) + #define CCELL_CMD_TYPE_PG_SZ_1K (2<<4) + #define CCELL_CMD_TYPE_PG_SZ_2K (3<<4) + #define CCELL_CMD_TYPE_PG_SZ_4K (4<<4) + #define CCELL_CMD_TYPE_PG_SZ_8K (5<<4) + #define CCELL_CMD_TYPE_PG_SZ_16K (6<<4) + #define CCELL_CMD_TYPE_PG_SZ_32K (7<<4) + #define CCELL_CMD_TYPE_PG_SZ_64K (8<<4) + #define CCELL_CMD_TYPE_PG_SZ_128K (9<<4) + #define CCELL_CMD_TYPE_PG_SZ_256K (10<<4) + #define CCELL_CMD_TYPE_PG_SZ_512K (11<<4) + #define CCELL_CMD_TYPE_PG_SZ_1M (12<<4) + #define CCELL_CMD_TYPE_PG_SZ_2M (13<<4) + #define CCELL_CMD_TYPE_PG_SZ_4M (14<<4) + #define CCELL_CMD_TYPE_PG_SZ_8M (15<<4) + u8_t ccell_est_nbd; + u16_t ccell_tx_host_bidx; + u32_t ccell_tx_mss; + #define CCELL_TX_MSS_MSS (0x3fffL<<0) + #define CCELL_TX_MSS_MULT (0x7ffL<<14) + #define CCELL_TX_MSS_PESS_ON (1UL<<25) + #define CCELL_TX_MSS_OH (0x3fL<<26) + u32_t ccell_tx_host_bseq; + u32_t ccell_tsch_bseq; + u32_t ccell_tbdr_bseq; + tx_bidx_boff_t ccell_tbdr_bidx_boff; +#if defined(_ANSI_C_) + // compiler switch is to avoid complaints from some ANSI compilers + // (e.g. Solaris) that don't support unnamed union + struct { + u32_t hi; + u32_t lo; + } ccell_tbdr_bhaddr; +#else + union { + struct { + u32_t ccell_tbdr_bhaddr_hi; + u32_t ccell_tbdr_bhaddr_lo; + }; + u64_t ccell_tbdr_bhaddr; + }; +#endif + tx_bidx_boff_t ccell_txp_bidx_boff; + u32_t ccell_txp_bseq; + u8_t ccell_reserved0[3]; + const u8_t ccell_tcmd_fnum; // NOTE: FW must NEVER change or initialize this field! + u32_t reserved1; // 8 byte alignment +} tcp_context_cmd_cell_b_xi_t; + + + + +/* + * tcp_context_cmd_cell_l_xi definition + */ +typedef struct tcp_context_cmd_cell_l_xi +{ + u16_t ccell_tx_host_bidx; + u8_t ccell_est_nbd; + u8_t ccell_cmd_type; + #define CCELL_CMD_TYPE_TYPE (0xf<<0) + #define CCELL_CMD_TYPE_TYPE_L2 (0<<0) + #define CCELL_CMD_TYPE_TYPE_TCP (1<<0) + #define CCELL_CMD_TYPE_TYPE_L5_CHAIN (2<<0) + #define CCELL_CMD_TYPE_TYPE_SEND_L5_PGTBL (3<<0) + #define CCELL_CMD_TYPE_TYPE_WRITE_L5_PGTBL (4<<0) + #define CCELL_CMD_TYPE_TYPE_RDREQ_L5_PGTBL (5<<0) + #define CCELL_CMD_TYPE_TYPE_L5_DONOTHING (6<<0) + #define CCELL_CMD_TYPE_TYPE_7_L5_PGTBL (7<<0) + #define CCELL_CMD_TYPE_TYPE_8_CHAIN (8<<0) + #define CCELL_CMD_TYPE_TYPE_9_CHAIN (9<<0) + #define CCELL_CMD_TYPE_TYPE_10_CHAIN (10<<0) + #define CCELL_CMD_TYPE_TYPE_11_PGTBL (11<<0) + #define CCELL_CMD_TYPE_TYPE_12_PGTBL (12<<0) + #define CCELL_CMD_TYPE_TYPE_13_PGTBL (13<<0) + #define CCELL_CMD_TYPE_TYPE_14_PGTBL (14<<0) + #define CCELL_CMD_TYPE_TYPE_15_PGTBL (15<<0) + #define CCELL_CMD_TYPE_PG_SZ (0xf<<4) + #define CCELL_CMD_TYPE_PG_SZ_256 (0<<4) + #define CCELL_CMD_TYPE_PG_SZ_512 (1<<4) + #define CCELL_CMD_TYPE_PG_SZ_1K (2<<4) + #define CCELL_CMD_TYPE_PG_SZ_2K (3<<4) + #define CCELL_CMD_TYPE_PG_SZ_4K (4<<4) + #define CCELL_CMD_TYPE_PG_SZ_8K (5<<4) + #define CCELL_CMD_TYPE_PG_SZ_16K (6<<4) + #define CCELL_CMD_TYPE_PG_SZ_32K (7<<4) + #define CCELL_CMD_TYPE_PG_SZ_64K (8<<4) + #define CCELL_CMD_TYPE_PG_SZ_128K (9<<4) + #define CCELL_CMD_TYPE_PG_SZ_256K (10<<4) + #define CCELL_CMD_TYPE_PG_SZ_512K (11<<4) + #define CCELL_CMD_TYPE_PG_SZ_1M (12<<4) + #define CCELL_CMD_TYPE_PG_SZ_2M (13<<4) + #define CCELL_CMD_TYPE_PG_SZ_4M (14<<4) + #define CCELL_CMD_TYPE_PG_SZ_8M (15<<4) + + u32_t ccell_tx_mss; + #define CCELL_TX_MSS_MSS (0x3fffL<<0) + #define CCELL_TX_MSS_MULT (0x7ffL<<14) + #define CCELL_TX_MSS_PESS_ON (1UL<<25) + #define CCELL_TX_MSS_OH (0x3fL<<26) + + u32_t ccell_tx_host_bseq; + u32_t ccell_tsch_bseq; + u32_t ccell_tbdr_bseq; + tx_bidx_boff_t ccell_tbdr_bidx_boff; + struct { + u32_t hi; + u32_t lo; + } ccell_tbdr_bhaddr; + tx_bidx_boff_t ccell_txp_bidx_boff; + u32_t ccell_txp_bseq; + const u8_t ccell_tcmd_fnum; // NOTE: FW must NEVER change or initialize this field! + u8_t ccell_reserved0[3]; + u32_t reserved1; // 8 byte alignment +} tcp_context_cmd_cell_l_xi_t; + + +/* + * tcp_context_cmd_cell select + */ +#if defined(LITTLE_ENDIAN) + typedef tcp_context_cmd_cell_l_te_t tcp_context_cmd_cell_te_t; + typedef tcp_context_cmd_cell_l_xi_t tcp_context_cmd_cell_xi_t; +#elif defined(BIG_ENDIAN) +#if defined(CONFIG_PPC64) || defined(__sparc) + typedef tcp_context_cmd_cell_l_te_t tcp_context_cmd_cell_te_t; + typedef tcp_context_cmd_cell_l_xi_t tcp_context_cmd_cell_xi_t; +#else + typedef tcp_context_cmd_cell_b_te_t tcp_context_cmd_cell_te_t; + typedef tcp_context_cmd_cell_b_xi_t tcp_context_cmd_cell_xi_t; +#endif +#endif + +/* + * pg_context_b definition + */ +typedef struct pg_context_b +{ + u8_t pg_type; + #define PG_TYPE_TYPE (0xf<<4) + #define PG_TYPE_TYPE_EMPTY (0<<4) + #define PG_TYPE_TYPE_L2 (1<<4) + #define PG_TYPE_TYPE_TCP (2<<4) + #define PG_TYPE_TYPE_L5 (3<<4) + #define PG_TYPE_TYPE_L2_BD_CHN (4<<4) + #define PG_TYPE_TYPE_PG (5<<4) + + u8_t pg_size; + u8_t pg_krnlq_id; // Xinan and X1V only + u8_t unused_0; + u32_t unused_1[2]; + u32_t pg_timer1; + u16_t pg_timer2; + u16_t pg_timer3; + u16_t pg_timer4; + u16_t pg_timer5; + u8_t pg_l2hdr_nbytes; + u8_t pg_flags; + #define PG_FLAGS_SNAP_ENCAP (1<<0) + #define PG_FLAGS_VLAN_TAGGING (1<<1) + + u8_t pg_da[6]; + u8_t pg_sa[6]; + u16_t pg_etype; + u16_t pg_vlan_tag; + u16_t pg_ipid_start; + u16_t pg_ipid_count; + u16_t unused_2; +} pg_context_b_t; + + +/* + * pg_context_l definition + */ +typedef struct pg_context_l +{ + u8_t unused_0; + u8_t pg_krnlq_id; // Xinan and X1V only + u8_t pg_size; + u8_t pg_type; + #define PG_TYPE_TYPE (0xf<<4) + #define PG_TYPE_TYPE_EMPTY (0<<4) + #define PG_TYPE_TYPE_L2 (1<<4) + #define PG_TYPE_TYPE_TCP (2<<4) + #define PG_TYPE_TYPE_L5 (3<<4) + #define PG_TYPE_TYPE_L2_BD_CHN (4<<4) + #define PG_TYPE_TYPE_PG (5<<4) + u32_t unused_1[2]; + + u32_t pg_timer1; + u16_t pg_timer3; + u16_t pg_timer2; + u16_t pg_timer5; + u16_t pg_timer4; + u8_t pg_da[6]; + u8_t pg_flags; + #define PG_FLAGS_SNAP_ENCAP (1<<0) + #define PG_FLAGS_VLAN_TAGGING (1<<1) + + u8_t pg_l2hdr_nbytes; + u8_t pg_sa[6]; + u16_t pg_etype; + u16_t pg_ipid_start; + u16_t pg_vlan_tag; + u16_t unused_2; + u16_t pg_ipid_count; +} pg_context_l_t; + + +/* + * pg_context select + */ +#if defined(LITTLE_ENDIAN) + typedef pg_context_l_t pg_context_t; +#elif defined(BIG_ENDIAN) + typedef pg_context_b_t pg_context_t; +#endif + + + + +#endif /* _l2_defs_h_ */ + + diff --git a/usr/src/uts/common/io/bnx/570x/common/include/l2_ftq.h b/usr/src/uts/common/io/bnx/570x/common/include/l2_ftq.h new file mode 100644 index 0000000000..d7c1f51103 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/l2_ftq.h @@ -0,0 +1,978 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _l2_ftq_h_ +#define _l2_ftq_h_ + +#include "l2_defs.h" + +// This is to avoid compiling error for drivers compilation +#if !defined (TARGET_CHIP) + #define TARGET_CHIP 5709 +#endif + + + + +/* + * rxp cmd enqueue definition + * offset: 0000 + */ + + +#if defined(LITTLE_ENDIAN) + typedef struct rxpcq_l + { + u32_t cid; + union{ + u32_t host_opaque; + u32_t generic1; + }u1; + union{ + struct { + u16_t status; + u8_t opcode; + u8_t flags; + }s1; + u32_t generic2; + }u2; + } rxpcq_l_t; + + typedef rxpcq_l_t rxpcq_t; +#elif defined(BIG_ENDIAN) + typedef struct rxpcq_b + { + u32_t cid; + union{ + u32_t host_opaque; + u32_t generic1; + } u1; + union{ + struct { + u8_t flags; + u8_t opcode; + u16_t status; + } s1; + u32_t generic2; + } u2; + } rxpcq_b_t; + + typedef rxpcq_b_t rxpcq_t; +#endif + + +/* + * rxp enqueue definition + * offset: 0000 + */ +typedef struct rxpq_b +{ + u32_t bits_errors; + u32_t bits_status; + + u8_t bit_mcast_hash_idx; + u8_t bits_acpi_pat; + u8_t knum; + u8_t unused1; + + u16_t rule_tag; + u16_t pkt_len; + + u16_t vlan_tag; + u8_t ip_hdr_offset; + u8_t rx_qid; + + u16_t ip_xsum; + // this field has been extended to 2-byte in Xinan +#if (TARGET_CHIP == 5706) + u8_t tcp_udp_hdr_offset; + u8_t unused2; +#else + u16_t tcp_udp_hdr_offset; +#endif + u16_t tcp_udp_xsum; + u16_t tcp_payload_len; + + u16_t pseud_xsum; + u16_t l2_payload_raw_xsum; + // this field has been extended to 2-byte in Xinan +#if (TARGET_CHIP == 5706) + u8_t data_offset; + u8_t unused3; +#else + u16_t data_offset; +#endif + u16_t l3_payload_raw_xsum; + + u32_t mbuf_cluster; + u32_t cid; + + u16_t cs16; + u16_t unused4; + + u16_t ext_status; + u16_t unused5; + +} rxpq_b_t; + +typedef struct rxpq_l +{ + u32_t bits_errors; + u32_t bits_status; + + u8_t unused1; + u8_t knum; + u8_t bits_acpi_pat; + u8_t bit_mcast_hash_idx; + + u16_t pkt_len; + u16_t rule_tag; + + u8_t rx_qid; + u8_t ip_hdr_offset; + u16_t vlan_tag; + + // this field has been extended to 2-byte in Xinan +#if (TARGET_CHIP == 5706) + u8_t unused2; + u8_t tcp_udp_hdr_offset; +#else + u16_t tcp_udp_hdr_offset; +#endif + u16_t ip_xsum; + + u16_t tcp_payload_len; + u16_t tcp_udp_xsum; + + u16_t l2_payload_raw_xsum; + u16_t pseud_xsum; + + u16_t l3_payload_raw_xsum; + // this field has been extended to 2-byte in Xinan +#if (TARGET_CHIP == 5706) + u8_t unused3; + u8_t data_offset; +#else + u16_t data_offset; +#endif + u32_t mbuf_cluster; + u32_t cid; + + u16_t unused4; + u16_t cs16; + + u16_t unused5; + u16_t ext_status; + +} rxpq_l_t; + +#if defined(LITTLE_ENDIAN) + typedef rxpq_l_t rxpq_t; +#elif defined(BIG_ENDIAN) + typedef rxpq_b_t rxpq_t; +#endif + +/* + * rv2ppq_generic definition + */ +typedef struct rv2ppq_generic_b +{ + u32_t cid; + u32_t mbuf_cluster; + u16_t operand_flags; + u8_t knum; + u8_t opcode; + #define GENERIC_OPCODE_RV2PPQ_VALUE_UNUSED 0 + #define GENERIC_OPCODE_RV2PPQ_VALUE_NOP 1 + #define GENERIC_OPCODE_RV2PPQ_VALUE_OPAQUE 2 + #define GENERIC_OPCODE_RV2PPQ_VALUE_L2_PLACE 3 + #define GENERIC_OPCODE_RV2PPQ_VALUE_L4_PLACE 4 + #define GENERIC_OPCODE_RV2PPQ_VALUE_L4_FLUSH 5 + #define GENERIC_OPCODE_RV2PPQ_VALUE_L5_PLACE 10 + #define GENERIC_OPCODE_RV2PPQ_VALUE_L5_FLUSH 14 + #define GENERIC_OPCODE_RV2PPQ_VALUE_DBG_RDMA 17 + #define GENERIC_OPCODE_RV2PPQ_VALUE_DBG_RV2P 18 + #define GENERIC_OPCODE_RV2PPQ_VALUE_L4_INDICATE_TIMEOUT 20 + #define GENERIC_OPCODE_RV2PPQ_VALUE_L2_JUMBO_PLACE 26 + #define GENERIC_OPCODE_RV2PPQ_VALUE_L2_FLUSH_BD_CHAIN 28 + #define GENERIC_OPCODE_RV2PPQ_VALUE_FLR 29 // X1V only + + u16_t operand16_0; // Note that 16_0 and 16_1 will be absorbed + u16_t operand16_1; // by RDMA and won't be passed to COM + u16_t operand16_2; + u16_t operand16_3; + u16_t operand16_4; + u16_t operand16_5; + u16_t operand16_6; + u16_t operand16_7; + u32_t operand32_0; // Note that 32_0 and 32_1 will be absorbed + u32_t operand32_1; // by RDMA and won't be passed to COM + u32_t operand32_2; + u32_t operand32_3; + u32_t operand32_4; + u8_t rdma_action; // no need to be cleared by RXP, RV2P will do it + u8_t cs16_pkt_len; + u16_t cs16; +} rv2ppq_generic_b_t; + +typedef struct rv2ppq_generic_l +{ + u32_t cid; + u32_t mbuf_cluster; + u8_t opcode; + u8_t knum; + u16_t operand_flags; + u16_t operand16_1; // by RDMA and won't be passed to COM + u16_t operand16_0; // Note that 16_0 and 16_1 will be absorbed + u16_t operand16_3; + u16_t operand16_2; + u16_t operand16_5; + u16_t operand16_4; + u16_t operand16_7; + u16_t operand16_6; + u32_t operand32_0; // Note that 32_0 and 32_1 will be absorbed + u32_t operand32_1; // by RDMA and won't be passed to COM + u32_t operand32_2; + u32_t operand32_3; + u32_t operand32_4; + u16_t cs16; + u8_t cs16_pkt_len; + u8_t rdma_action; // no need to be cleared by RXP, RV2P will do it +} rv2ppq_generic_l_t; + +#if defined(LITTLE_ENDIAN) + typedef rv2ppq_generic_l_t rv2ppq_generic_t; +#elif defined(BIG_ENDIAN) + typedef rv2ppq_generic_b_t rv2ppq_generic_t; +#endif + + + +/* + * rv2ppq_l2_place definition + */ +typedef struct rv2ppq_l2_place_b +{ + u32_t cid; + u32_t mbuf_cluster; + u16_t operand_flags; + #define L2_OPERAND_FLAGS_PREPEND_L2_FRAME_HEADER (1<<0) + #define L2_OPERAND_FLAGS_LAST (1<<1) + #define L2_OPERAND_FLAGS_ENQUEUE_TO_MCP (1<<2) + #define L2_OPERAND_FLAGS_DROP_PKT (1<<3) + #define L2_OPERAND_FLAGS_MCAST (1<<4) + #define L2_OPERAND_FLAGS_BCAST (1<<5) + #define L2_OPERAND_FLAGS_VMQ (1<<6) + #define L2_OPERAND_FLAGS_OOO_PLACE (1<<7) + #define L2_OPERAND_FLAGS_CU_PKT (1<<14) + + u8_t knum; + u8_t opcode; + u16_t offset; + u16_t length; // represent look-ahead_hdr length if VMQ flag is set (total pkt len otherwise) + u16_t bits_status; + u16_t vlan_tag; + u16_t ip_xsum; + u16_t udp_tcp_xsum; + u16_t unused_0; + u16_t packet_length; // represent total packet length + u32_t unused_1[2]; + u16_t unused_2; + u16_t error_flags; + #define L2_ERROR_FLAGS_CRC_ERROR (1<<1) + #define L2_ERROR_FLAGS_PHY_DECODE_ERROR (1<<2) + #define L2_ERROR_FLAGS_ALIGNMENT_ERROR (1<<3) + #define L2_ERROR_FLAGS_TOO_SHORT_ERROR (1<<4) + #define L2_ERROR_FLAGS_GIANT_FRAME_ERROR (1<<5) + + u32_t hash; + u32_t rt_bt; + u8_t rdma_action; // no need to be cleared by RXP, RV2P will do it + u8_t cs16_pkt_len; + u16_t cs16; + +} rv2ppq_l2_place_b_t; + +typedef struct rv2ppq_l2_place_l +{ + u32_t cid; + u32_t mbuf_cluster; + u8_t opcode; + u8_t knum; + u16_t operand_flags; + u16_t length; // represent look-ahead_hdr_length if VMQ flag is set (total pkt len otherwise) + u16_t offset; + u16_t vlan_tag; + u16_t bits_status; + u16_t udp_tcp_xsum; + u16_t ip_xsum; + u16_t packet_length; // represent total packet length if VMQ flag is set + u16_t unused_0; + u32_t unused_1[2]; + u16_t error_flags; + u16_t unused_2; + u32_t hash; + u32_t rt_bt; + u16_t cs16; + u8_t cs16_pkt_len; + u8_t rdma_action; // no need to be cleared by RXP, RV2P will do it + +} rv2ppq_l2_place_l_t; + +#if defined(LITTLE_ENDIAN) + typedef rv2ppq_l2_place_l_t rv2ppq_l2_place_t; +#elif defined(BIG_ENDIAN) + typedef rv2ppq_l2_place_b_t rv2ppq_l2_place_t; +#endif + + +/* + * rv2ppq_l2_flush_bd_chain definition + */ +typedef struct rv2ppq_l2_flush_bd_chain_b +{ + u32_t cid; + u32_t unused_0; + u16_t unused_1; + u8_t unused_2; + u8_t opcode; + u32_t unused_3[9]; + u8_t rdma_action; // no need to be cleared by RXP, RV2P will do it + u8_t cs16_pkt_len; + u16_t cs16; + +} rv2ppq_l2_flush_bd_chain_b_t; + +typedef struct rv2ppq_l2_flush_bd_chain_l +{ + u32_t cid; + u32_t unused_0; + u8_t opcode; + u8_t unused_2; + u16_t unused_1; + u32_t unused_3[9]; + u16_t cs16; + u8_t cs16_pkt_len; + u8_t rdma_action; // no need to be cleared by RXP, RV2P will do it + +} rv2ppq_l2_flush_bd_chain_l_t; + +#if defined(LITTLE_ENDIAN) + typedef rv2ppq_l2_flush_bd_chain_l_t rv2ppq_l2_flush_bd_chain_t; +#elif defined(BIG_ENDIAN) + typedef rv2ppq_l2_flush_bd_chain_b_t rv2ppq_l2_flush_bd_chain_t; +#endif + +/* + * comq_generic definition + */ +typedef enum +{ + GENERIC_OPCODE_COMQ_VALUE_UNUSED = 0, + GENERIC_OPCODE_COMQ_VALUE_NOP = GENERIC_OPCODE_RV2PPQ_VALUE_NOP , + GENERIC_OPCODE_COMQ_VALUE_OPAQUE = GENERIC_OPCODE_RV2PPQ_VALUE_OPAQUE , + GENERIC_OPCODE_COMQ_VALUE_L2_COMPLETION = GENERIC_OPCODE_RV2PPQ_VALUE_L2_PLACE , + GENERIC_OPCODE_COMQ_VALUE_L4_COMPLETION = GENERIC_OPCODE_RV2PPQ_VALUE_L4_PLACE , + GENERIC_OPCODE_COMQ_VALUE_L4_FLUSH = GENERIC_OPCODE_RV2PPQ_VALUE_L4_FLUSH , + GENERIC_OPCODE_COMQ_VALUE_L4_STARTGEN = 6, + GENERIC_OPCODE_COMQ_VALUE_L4_ADDGEN = 7, + GENERIC_OPCODE_COMQ_VALUE_L4_PLACE = 8, + GENERIC_OPCODE_COMQ_VALUE_L4_DISCARDGEN = 9, + GENERIC_OPCODE_COMQ_VALUE_L5_PLACE = GENERIC_OPCODE_RV2PPQ_VALUE_L5_PLACE, + GENERIC_OPCODE_COMQ_VALUE_L2_NOBUFFER = 11, + GENERIC_OPCODE_COMQ_VALUE_L4_ARMPUSH = 12, + GENERIC_OPCODE_COMQ_VALUE_L4_RWINUPDATE = 13, + GENERIC_OPCODE_COMQ_VALUE_L5_FLUSH = GENERIC_OPCODE_RV2PPQ_VALUE_L5_FLUSH, + GENERIC_OPCODE_COMQ_VALUE_L4_INDICATE = 15, + GENERIC_OPCODE_COMQ_VALUE_L4_COPYGEN = 16, + GENERIC_OPCODE_COMQ_VALUE_DBG_RDMA = GENERIC_OPCODE_RV2PPQ_VALUE_DBG_RDMA, + GENERIC_OPCODE_COMQ_VALUE_DBG_RV2P = GENERIC_OPCODE_RV2PPQ_VALUE_DBG_RV2P, + GENERIC_OPCODE_COMQ_VALUE_L4_MQUPLOAD = 19, + GENERIC_OPCODE_COMQ_VALUE_ISCSI_SGL_PLACE = 22, + GENERIC_OPCODE_COMQ_VALUE_ISCSI_RQ_PLACE = 23, + GENERIC_OPCODE_COMQ_VALUE_ISCSI_RQ_FLUSH = 24, + GENERIC_OPCODE_COMQ_VALUE_ISCSI_SGL_FLUSH = 25, + + // Jumbo mode and L2 FLUSH are for Linux only + GENERIC_OPCODE_COMQ_VALUE_L2_JUMBO_COMPLETION = GENERIC_OPCODE_RV2PPQ_VALUE_L2_JUMBO_PLACE, + GENERIC_OPCODE_COMQ_VALUE_L2_JUMBO_NOBUFFER = 27, + GENERIC_OPCODE_COMQ_VALUE_L2_FLUSH_BD_CHAIN = GENERIC_OPCODE_RV2PPQ_VALUE_L2_FLUSH_BD_CHAIN, + GENERIC_OPCODE_COMQ_VALUE_FLR = GENERIC_OPCODE_RV2PPQ_VALUE_FLR, + MAX_COMQ_OPCODE +}GENERIC_OPCODE_COMQ_t ; + + +typedef struct comq_generic_b +{ + u32_t cid; + u32_t mbuf_cluster; + u16_t operand_flags; + u8_t knum; + u8_t opcode; + #define GENERIC_OPCODE_COMQ_VALUE (0xff<<0) + u16_t operand16_2; + u16_t operand16_3; + u16_t operand16_4; + u16_t operand16_5; + u16_t operand16_6; + u16_t operand16_7; + u32_t operand32_2; + u32_t operand32_3; + u32_t operand32_4; + u8_t rdma_action; + u8_t cs16_pkt_len; + u16_t cs16; +} comq_generic_b_t; + +typedef struct comq_generic_l +{ + u32_t cid; + u32_t mbuf_cluster; + u8_t opcode; + u8_t knum; + u16_t operand_flags; + u16_t operand16_3; + u16_t operand16_2; + u16_t operand16_5; + u16_t operand16_4; + u16_t operand16_7; + u16_t operand16_6; + u32_t operand32_2; + u32_t operand32_3; + u32_t operand32_4; + u16_t cs16; + u8_t cs16_pkt_len; + u8_t rdma_action; +} comq_generic_l_t; + +#if defined(LITTLE_ENDIAN) + typedef comq_generic_l_t comq_generic_t; +#elif defined(BIG_ENDIAN) + typedef comq_generic_b_t comq_generic_t; +#endif + + +/* + * comq_l2_completion definition + */ +typedef struct comq_l2_completion_b +{ + u32_t cid; + u32_t mbuf_cluster; + u16_t operand_flags; + u8_t knum; + u8_t opcode; + u16_t bits_status; + u16_t vlan_tag; + u16_t ip_xsum; + u16_t udp_tcp_xsum; + u16_t nx_bidx; + u16_t packet_length; // total pkt len (MCP will need this info) + u16_t unused_0; + u16_t error_flags; + u32_t hash; + u32_t rt_bt; + u8_t rdma_action; + u8_t cs16_pkt_len; + u16_t cs16; + +} comq_l2_completion_b_t; + +typedef struct comq_l2_completion_l +{ + u32_t cid; + u32_t mbuf_cluster; + u8_t opcode; + u8_t knum; + u16_t operand_flags; + u16_t vlan_tag; + u16_t bits_status; + u16_t udp_tcp_xsum; + u16_t ip_xsum; + u16_t packet_length; // total pkt len (MCP will need this info) + u16_t nx_bidx; + u16_t error_flags; + u16_t unused_0; + u32_t hash; + u32_t rt_bt; + u16_t cs16; + u8_t cs16_pkt_len; + u8_t rdma_action; + +} comq_l2_completion_l_t; + +#if defined(LITTLE_ENDIAN) + typedef comq_l2_completion_l_t comq_l2_completion_t; +#elif defined(BIG_ENDIAN) + typedef comq_l2_completion_b_t comq_l2_completion_t; +#endif + +/* + * comq_l2_nobuffer definition + */ +typedef struct comq_l2_nobuffer_b +{ + u32_t l2_nobuff_cid; + u32_t l2_nobuff_mbuf_cluster; + u16_t l2_nobuff_operand_flags; + u8_t l2_nobuff_knum; + u8_t l2_nobuff_opcode; + u16_t l2_nobuff_bits_status; + u16_t l2_nobuff_vlan_tag; + u16_t l2_nobuff_ip_xsum; + u16_t l2_nobuff_udp_tcp_xsum; + u16_t l2_nobuff_nx_bidx; + u16_t l2_nobuff_packet_length; // total pkt len (MCP will need this info) + u16_t unused_1; + u16_t l2_nobuff_error_flags; + u32_t l2_nobuff_hash; + u32_t unused_2; + u8_t l2_nobuff_rdma_action; + u8_t l2_nobuff_cs16_pkt_len; + u16_t l2_nobuff_cs16; + +} comq_l2_nobuffer_b_t; + +typedef struct comq_l2_nobuffer_l +{ + u32_t l2_nobuff_cid; + u32_t l2_nobuff_mbuf_cluster; + u8_t l2_nobuff_opcode; + u8_t l2_nobuff_knum; + u16_t l2_nobuff_operand_flags; + u16_t l2_nobuff_vlan_tag; + u16_t l2_nobuff_bits_status; + u16_t l2_nobuff_udp_tcp_xsum; + u16_t l2_nobuff_ip_xsum; + u16_t l2_nobuff_packet_length; // total pkt len (MCP will need this info) + u16_t l2_nobuff_nx_bidx; + u16_t l2_nobuff_error_flags; + u16_t unused_1; + u32_t l2_nobuff_hash; + u32_t unused_2; + u16_t l2_nobuff_cs16; + u8_t l2_nobuff_cs16_pkt_len; + u8_t l2_nobuff_rdma_action; + +} comq_l2_nobuffer_l_t; + +#if defined(LITTLE_ENDIAN) + typedef comq_l2_nobuffer_l_t comq_l2_nobuffer_t; +#elif defined(BIG_ENDIAN) + typedef comq_l2_nobuffer_b_t comq_l2_nobuffer_t; +#endif + + +/* + * comq_l2_flr definition + */ +typedef struct comq_l2_flr_b +{ + u32_t cid; + u32_t mbuf_cluster; + u16_t operand_flags; + u8_t knum; + u8_t opcode; + u16_t bits_status; + u16_t vlan_tag; + u16_t ip_xsum; + u16_t udp_tcp_xsum; + u16_t nx_bidx; + u16_t unused_0; + u16_t unused_1; + u16_t error_flags; + u32_t hash; + u32_t unused_2; + u8_t rdma_action; + u8_t cs16_pkt_len; + u16_t cs16; + +} comq_l2_flr_b_t; + +typedef struct comq_l2_flr_l +{ + u32_t cid; + u32_t mbuf_cluster; + u8_t opcode; + u8_t knum; + u16_t operand_flags; + u16_t vlan_tag; + u16_t bits_status; + u16_t udp_tcp_xsum; + u16_t ip_xsum; + u16_t unused_0; + u16_t nx_bidx; + u16_t error_flags; + u16_t unused_1; + u32_t hash; + u32_t unused_2; + u16_t cs16; + u8_t cs16_pkt_len; + u8_t rdma_action; + +} comq_l2_flr_l_t; + +#if defined(LITTLE_ENDIAN) + typedef comq_l2_flr_l_t comq_l2_flr_t; +#elif defined(BIG_ENDIAN) + typedef comq_l2_flr_b_t comq_l2_flr_t; +#endif + +/* + * comxq_t + */ +typedef struct comxq_b +{ + u32_t cid; + u16_t flags; + u16_t unused1; + u32_t snd_next; +}comxq_b_t; + +typedef struct comxq_l +{ + u32_t cid; + u16_t unused1; + u16_t flags; + u32_t snd_next; +}comxq_l_t; + +#if defined(LITTLE_ENDIAN) + typedef comxq_l_t comxq_t; +#elif defined(BIG_ENDIAN) + typedef comxq_b_t comxq_t; +#endif + +/* + * comtq_t + */ +typedef struct comtq_b +{ + u32_t cid; + u32_t val; + u8_t type; + u8_t unused[3]; +}comtq_b_t; + +typedef struct comtq_l +{ + u32_t cid; + u32_t val; + u8_t unused[3]; + u8_t type; +}comtq_l_t; + +#if defined(LITTLE_ENDIAN) + typedef comtq_l_t comtq_t; +#elif defined(BIG_ENDIAN) + typedef comtq_b_t comtq_t; +#endif + +/* + * csq_t + */ +typedef struct csq_b +{ + u32_t cid; + // bit 7 lsb of CID is always 0, but CSQ can be enqueued by MQ or COM. + // For L4, we can use this bit to indicate the source + // Note that 7 lsb is ALWAYS masked out to be zero by HW + #define CSQ_SRC_MQ 0 + #define CSQ_SRC_COM 0x80 + #define CSQ_SRC_MASK 0xFF + u8_t flags; + u8_t unused[3]; +}csq_b_t; + +typedef struct csq_l +{ + u32_t cid; + u8_t unused[3]; + u8_t flags; +}csq_l_t; + +#if defined(LITTLE_ENDIAN) + typedef csq_l_t csq_t; +#elif defined(BIG_ENDIAN) + typedef csq_b_t csq_t; +#endif + +/* + * cpq_t + */ +typedef struct cpq_b +{ + u32_t cid; +}cpq_b_t; + +typedef struct cpq_l +{ + u32_t cid; +}cpq_l_t; + +#if defined(LITTLE_ENDIAN) + typedef cpq_l_t cpq_t; +#elif defined(BIG_ENDIAN) + typedef cpq_b_t cpq_t; +#endif + +/* + * rv2ptq_t + */ +typedef struct rv2ptq_b +{ + u32_t cid; +}rv2ptq_b_t; + +typedef struct rv2ptq_l +{ + u32_t cid; +}rv2ptq_l_t; + +#if defined(LITTLE_ENDIAN) + typedef rv2ptq_l_t rv2ptq_t; +#elif defined(BIG_ENDIAN) + typedef rv2ptq_b_t rv2ptq_t; +#endif + + + /* TX FTQs */ + +typedef struct tschq_b +{ + u32_t cid; + u8_t flags; + u8_t unused[3]; +}tschq_b_t; + +typedef struct tschq_l +{ + u32_t cid; + u8_t unused[3]; + u8_t flags; +}tschq_l_t; + +#if defined(LITTLE_ENDIAN) + typedef tschq_l_t tschq_t; +#elif defined(BIG_ENDIAN) + typedef tschq_b_t tschq_t; +#endif + +typedef struct txpq_b +{ + u32_t cid; + u32_t bseq; + u8_t flags_flags; + u8_t cmd; + u8_t xnum; + u8_t protocol_flags; + u32_t tcp_rcv_nxt; +}txpq_b_t; + +typedef struct txpq_l +{ + u32_t cid; + u32_t bseq; + u8_t protocol_flags; + u8_t xnum; + u8_t cmd; + u8_t flags_flags; + u32_t tcp_rcv_nxt; +}txpq_l_t; + +#if defined(LITTLE_ENDIAN) + typedef txpq_l_t txpq_t; +#elif defined(BIG_ENDIAN) + typedef txpq_b_t txpq_t; +#endif + +typedef struct tdmaq_b +{ + u32_t cid; + tx_bidx_boff_t bidx_boff; + u32_t bseq; + u32_t snd_next; + u8_t cmd; + u8_t xnum; + u8_t knum; + u8_t unused1; + u32_t flags_flags; + u16_t nbytes; + u16_t hole0_boff; + u16_t hole1_boff; + u16_t hole2_boff; + u32_t hole0_fill; + u32_t hole1_fill; + u32_t hole2_fill; + u8_t fnum; + u8_t txp_act_cmd; + u16_t unused2; +}tdmaq_b_t; + +typedef struct tdmaq_l +{ + u32_t cid; + tx_bidx_boff_t bidx_boff; + u32_t bseq; + u32_t snd_next; + u8_t unused1; + u8_t knum; + u8_t xnum; + u8_t cmd; + u32_t flags_flags; + u16_t hole0_boff; + u16_t nbytes; + u16_t hole2_boff; + u16_t hole1_boff; + u32_t hole0_fill; + u32_t hole1_fill; + u32_t hole2_fill; + u16_t unused2; + u8_t txp_act_cmd; + u8_t fnum; +}tdmaq_l_t; + +#if defined(LITTLE_ENDIAN) + typedef tdmaq_l_t tdmaq_t; +#elif defined(BIG_ENDIAN) + typedef tdmaq_b_t tdmaq_t; +#endif + +typedef struct tpatq_b +{ + u32_t cid; + u16_t nbytes; + u8_t xnum; + u8_t knum; + u32_t flags_flags; + u16_t raw_chksum; + u16_t tpat_bidx; +}tpatq_b_t; + +typedef struct tpatq_l +{ + u32_t cid; + u8_t knum; + u8_t xnum; + u16_t nbytes; + u32_t flags_flags; + u16_t tpat_bidx; + u16_t raw_chksum; +}tpatq_l_t; + +#if defined(LITTLE_ENDIAN) + typedef tpatq_l_t tpatq_t; +#elif defined(BIG_ENDIAN) + typedef tpatq_b_t tpatq_t; +#endif + +typedef struct taspq_b +{ + u16_t taspq_hdr_skip; + u16_t taspq_hdr_post_skip; + u16_t taspq_hdr_size; + u16_t taspq_payload_skip; + u16_t taspq_payload_size; + u16_t taspq_flags; +#if (TARGET_CHIP == 5709) + #define TASPQ_FLAGS_PKT_END TPATF_TASQ_FLAGS_PKT_END + #define TASPQ_FLAGS_MGMT_PACKET TPATF_TASQ_FLAGS_MGMT_PACKET + #define TASPQ_FLAGS_DEST_RPC_CATCHUP TPATF_TASQ_FLAGS_CATCHUP_PACKET + #define TASPQ_FLAGS_DONT_GEN_CRC TPATF_TASQ_FLAGS_DONT_GEN_CRC + #define TASPQ_FLAGS_RESERVED TPATF_TASQ_FLAGS_RESERVED + #define TASPQ_FLAGS_DEST_EMAC TPATF_TASQ_FLAGS_DEST_EMAC + #define TASPQ_FLAGS_DEST_RPC_MIRROR TPATF_TASQ_FLAGS_DEST_RPC_MIRROR + #define TASPQ_FLAGS_DEST_RPC_LOOPBACK TPATF_TASQ_FLAGS_DEST_RPC_LOOPBACK + #define TASPQ_FLAGS_MGMT_PKT_TAG TPATF_TASQ_FLAGS_MGMT_PKT_TAG + #define TASPQ_FLAGS_CS16_VLD TPATF_TASQ_FLAGS_CS16_VLD +#else + #define TASPQ_FLAGS_PKT_END TPATF_TASPQ_FLAGS_PKT_END + #define TASPQ_FLAGS_MGMT_PACKET TPATF_TASPQ_FLAGS_MGMT_PACKET + #define TASPQ_FLAGS_DEST_RPC_CATCHUP TPATF_TASPQ_FLAGS_DEST_RPC_CATCHUP + #define TASPQ_FLAGS_DONT_GEN_CRC TPATF_TASPQ_FLAGS_DONT_GEN_CRC + #define TASPQ_FLAGS_RESERVED TPATF_TASPQ_FLAGS_RESERVED + #define TASPQ_FLAGS_DEST_EMAC TPATF_TASPQ_FLAGS_DEST_EMAC + #define TASPQ_FLAGS_DEST_RPC_MIRROR TPATF_TASPQ_FLAGS_DEST_RPC_MIRROR + #define TASPQ_FLAGS_DEST_RPC_LOOPBACK TPATF_TASPQ_FLAGS_DEST_RPC_LOOPBACK + #define TASPQ_FLAGS_MGMT_PKT_TAG TPATF_TASPQ_FLAGS_MGMT_PKT_TAG + #define TASPQ_FLAGS_CS16_VLD TPATF_TASPQ_FLAGS_CS16_VLD +#endif + u16_t taspq_cs16; + u16_t taspq_uftq_cmd; /* Only the upper 16 bit of the ftq cmd is used */ +#if (TARGET_CHIP == 5709) + #define TASPQ_FTQ_CMD_CPY_DATA TPATF_TASQ_FTQ_CMD_CPY_DATA + #define TASPQ_FTQ_CMD_ADD_INTERVEN TPATF_TASQ_FTQ_CMD_ADD_INTERVEN + #define TASPQ_FTQ_CMD_ADD_DATA TPATF_TASQ_FTQ_CMD_ADD_DATA + #define TASPQ_FTQ_CMD_BUSY TPATF_TASQ_FTQ_CMD_BUSY +#else + #define TASPQ_FTQ_CMD_CPY_DATA TPATF_TASPQ_FTQ_CMD_CPY_DATA + #define TASPQ_FTQ_CMD_ADD_INTERVEN TPATF_TASPQ_FTQ_CMD_ADD_INTERVEN + #define TASPQ_FTQ_CMD_ADD_DATA TPATF_TASPQ_FTQ_CMD_ADD_DATA + #define TASPQ_FTQ_CMD_BUSY TPATF_TASPQ_FTQ_CMD_BUSY +#endif +} taspq_b_t; + +typedef struct taspq_l +{ + u16_t taspq_hdr_post_skip; + u16_t taspq_hdr_skip; + u16_t taspq_payload_skip; + u16_t taspq_hdr_size; + u16_t taspq_flags; +#if (TARGET_CHIP == 5709) + #define TASPQ_FLAGS_PKT_END TPATF_TASQ_FLAGS_PKT_END + #define TASPQ_FLAGS_MGMT_PACKET TPATF_TASQ_FLAGS_MGMT_PACKET + #define TASPQ_FLAGS_DEST_RPC_CATCHUP TPATF_TASQ_FLAGS_CATCHUP_PACKET + #define TASPQ_FLAGS_DONT_GEN_CRC TPATF_TASQ_FLAGS_DONT_GEN_CRC + #define TASPQ_FLAGS_RESERVED TPATF_TASQ_FLAGS_RESERVED + #define TASPQ_FLAGS_DEST_EMAC TPATF_TASQ_FLAGS_DEST_EMAC + #define TASPQ_FLAGS_DEST_RPC_MIRROR TPATF_TASQ_FLAGS_DEST_RPC_MIRROR + #define TASPQ_FLAGS_DEST_RPC_LOOPBACK TPATF_TASQ_FLAGS_DEST_RPC_LOOPBACK + #define TASPQ_FLAGS_MGMT_PKT_TAG TPATF_TASQ_FLAGS_MGMT_PKT_TAG + #define TASPQ_FLAGS_CS16_VLD TPATF_TASQ_FLAGS_CS16_VLD +#else + #define TASPQ_FLAGS_PKT_END TPATF_TASPQ_FLAGS_PKT_END + #define TASPQ_FLAGS_MGMT_PACKET TPATF_TASPQ_FLAGS_MGMT_PACKET + #define TASPQ_FLAGS_DEST_RPC_CATCHUP TPATF_TASPQ_FLAGS_DEST_RPC_CATCHUP + #define TASPQ_FLAGS_DONT_GEN_CRC TPATF_TASPQ_FLAGS_DONT_GEN_CRC + #define TASPQ_FLAGS_RESERVED TPATF_TASPQ_FLAGS_RESERVED + #define TASPQ_FLAGS_DEST_EMAC TPATF_TASPQ_FLAGS_DEST_EMAC + #define TASPQ_FLAGS_DEST_RPC_MIRROR TPATF_TASPQ_FLAGS_DEST_RPC_MIRROR + #define TASPQ_FLAGS_DEST_RPC_LOOPBACK TPATF_TASPQ_FLAGS_DEST_RPC_LOOPBACK + #define TASPQ_FLAGS_MGMT_PKT_TAG TPATF_TASPQ_FLAGS_MGMT_PKT_TAG + #define TASPQ_FLAGS_CS16_VLD TPATF_TASPQ_FLAGS_CS16_VLD +#endif + u16_t taspq_payload_size; + u16_t taspq_uftq_cmd; /* Only the upper 16 bit of the ftq cmd is used */ +#if (TARGET_CHIP == 5709) + #define TASPQ_FTQ_CMD_CPY_DATA TPATF_TASQ_FTQ_CMD_CPY_DATA + #define TASPQ_FTQ_CMD_ADD_INTERVEN TPATF_TASQ_FTQ_CMD_ADD_INTERVEN + #define TASPQ_FTQ_CMD_ADD_DATA TPATF_TASQ_FTQ_CMD_ADD_DATA + #define TASPQ_FTQ_CMD_BUSY TPATF_TASQ_FTQ_CMD_BUSY +#else + #define TASPQ_FTQ_CMD_CPY_DATA TPATF_TASPQ_FTQ_CMD_CPY_DATA + #define TASPQ_FTQ_CMD_ADD_INTERVEN TPATF_TASPQ_FTQ_CMD_ADD_INTERVEN + #define TASPQ_FTQ_CMD_ADD_DATA TPATF_TASPQ_FTQ_CMD_ADD_DATA + #define TASPQ_FTQ_CMD_BUSY TPATF_TASPQ_FTQ_CMD_BUSY +#endif + u16_t taspq_cs16; +} taspq_l_t; + +#if defined(LITTLE_ENDIAN) + typedef taspq_l_t taspq_t; +#elif defined(BIG_ENDIAN) + typedef taspq_b_t taspq_t; +#endif + +#endif /* _l2_ftq_h_ */ diff --git a/usr/src/uts/common/io/bnx/570x/common/include/l5_defs.h b/usr/src/uts/common/io/bnx/570x/common/include/l5_defs.h new file mode 100644 index 0000000000..39d8c51efb --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/l5_defs.h @@ -0,0 +1,2618 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _l5_defs_h_ +#define _l5_defs_h_ + +#include "5706_reg.h" +#include "l2_defs.h" +#include "l2_ftq.h" + +/* data structure defs: */ + +typedef struct ddp_tagged_msg_header +{ + u16_t mpa_length; + u16_t control; + u32_t stag; + u64_t to; +} ddp_tagged_msg_header_t; + +typedef struct ddp_untagged_msg_header +{ + u16_t mpa_length; + u16_t control; + union + { + u32_t reserved; + u32_t invalidated_stag; + } rdmap_rsvd; + u32_t queue_number; + u32_t msn; + u32_t mo; +} ddp_untagged_msg_header_t; + +typedef struct rdmap_read_request_header +{ + ddp_untagged_msg_header_t ddp_header; + u32_t sink_stag; + u64_t sink_to; + u32_t length; + u32_t source_stag; + u64_t source_to; +} rdmap_read_request_header_t; + + +/**************************************************************************** + * L5 Window Reference Count Table Entry + ****************************************************************************/ + +typedef struct l5_window_ref_cnt_table_entry +{ + u8_t wrcte_pidx; /* Incremented by CP whenever a SQ work request or + incoming RDMA Read Request is processed that + references the associated window for source data. */ + + u8_t wrcte_cidx; /* Incremented by COM whenever an entry is removed from + the command queue where the associated window is + the data source. */ + +} l5_window_ref_cnt_table_entry_t; + + +/* constants and macros: */ + +#define RDMA_WRITE_CMD 0 +#define RDMA_READ_REQ_CMD 1 +#define RDMA_READ_RSP_CMD 2 +#define RDMA_SEND_CMD 3 +#define RDMA_SEND_W_EVENT 4 + +#define RDMA_MPA_HDR_LENGTH 2 +#define RDMA_MPA_CRC_LENGTH 4 +#define RDMA_MPA_MARKER_SIZE 4 + +#define RDMA_DDP_TAGGED_HDR_LENGTH 14 +#define RDMA_DDP_UNTAGGED_HDR_LENGTH 18 + +#define RDMA_READ_REQ_MSG_LENGTH 28 + +#define RDMA_WRITE_HDR_LENGTH (RDMA_MPA_HDR_LENGTH + RDMA_DDP_TAGGED_HDR_LENGTH) +#define RDMA_SEND_MSG_HDR_LENGTH (RDMA_MPA_HDR_LENGTH + RDMA_DDP_UNTAGGED_HDR_LENGTH) +#define RDMA_READ_REQ_HDR_LENGTH (RDMA_MPA_HDR_LENGTH + RDMA_DDP_UNTAGGED_HDR_LENGTH + RDMA_READ_REQ_MSG_LENGTH) +#define RDMA_READ_RESP_HDR_LENGTH (RDMA_MPA_HDR_LENGTH + RDMA_DDP_TAGGED_HDR_LENGTH) + +#define RDMA_STANDARD_L5_OVERHEAD (RDMA_STANDARD_HDR_LENGTH + RDMA_MPA_HDR_LENGTH + RDMA_MPA_CRC_LENGTH) +#define RDMA_READ_REQ_L5_OVERHEAD (RDMA_READ_REQ_HDR_LENGTH + RDMA_MPA_HDR_LENGTH + RDMA_MPA_CRC_LENGTH) + +#define RDMA_SEND_QUEUE_NUMBER 0x00000000 +#define RDMA_READ_QUEUE_NUMBER 0x00000001 +#define RDMA_TERM_QUEUE_NUMBER 0x00000002 + +#define RDMA_MPA_MARKER_INTERVAL 512 /* MPA marker interval */ +#define RDMA_DATA_MARKER_INTERVAL (RDMA_MPA_MARKER_INTERVAL - RDMA_MPA_MARKER_SIZE) /* Data between markers */ +#define RDMA_MPA_MARKER_INTERVAL_SHIFT 9 + +#define DDP_CTRL_RDMA_WRITE 0x8000 +#define DDP_CTRL_RDMA_READ_REQ 0x0001 +#define DDP_CTRL_RDMA_READ_RSP 0x8002 +#define DDP_CTRL_SEND_MSG 0x0003 +#define DDP_CTRL_SEND_INV_MSG 0x0004 +#define DDP_CTRL_SEND_EVT_MSG 0x0005 +#define DDP_CTRL_SEND_INV_EVT_MSG 0x0006 + +#define DDP_CTRL_L_BIT 0x4000 +#define DDP_CTRL_T_BIT 0x8000 + +#define DDP_CTRL_DDP_VERSION_MASK 0x0300 +#define DDP_CTRL_DDP_VERSION 0x0000 + +#define DDP_TAGGED_HDR_LENGTH 14 +#define DDP_UNTAGGED_HDR_LENGTH 18 + +#define DDP_QN_SEND_MESSAGE_QUEUE 0x00000000 +#define DDP_QN_RDMA_READ_REQUEST_QUEUE 0x00000001 +#define DDP_QN_RDMA_TERMINATE_QUEUE 0x00000002 + +#define DDP_MAX_UNTAGGED_QUEUES 0x00000003 + +#define RDMAP_CTRL_RDMAP_VERSION_MASK 0x00C0 +#define RDMAP_CTRL_RDMAP_VERSION 0x0000 + +#define RDMAP_CTRL_RDMAP_OPCODE_MASK 0x0F + +#define RDMAP_CTRL_RDMA_WRITE 0x00 +#define RDMAP_CTRL_RDMA_READ_REQ 0x01 +#define RDMAP_CTRL_RDMA_READ_RSP 0x02 +#define RDMAP_CTRL_SEND_MSG 0x03 +#define RDMAP_CTRL_SEND_W_INV_MSG 0x04 +#define RDMAP_CTRL_SEND_W_EVT_MSG 0x05 +#define RDMAP_CTRL_SEND_W_INV_EVT_MSG 0x06 + +#define L5_MEMORY_REGION_STAG_BIT 0x00800000 +#define L5_STAG_INDEX_MASK 0x00FFFFFF +#define L5_STAG_KEY_MASK 0xFF000000 +#define L5_MIN_HOST_PAGE_SIZE 0x100 /* 256 bytes */ +#define L5_WINDOW_CACHE_KEY_BASE 0x2000 + + +/* define context memory-related constants for things + like STag validation: */ + +#define L5_RX_VCID_SIZE 128 + + +/* L5 RxP protocol errors: */ + +#define RX_PROTO_ERR_MPA_LEN_NON_MULT_FOUR 0x00000001 +#define RX_PROTO_ERR_INVALID_MPA_LEN 0x00000002 +#define RX_PROTO_ERR_INVALID_MARKER 0x00000003 +#define RX_PROTO_ERR_INVALID_TAGGED_OPCODE 0x00000004 +#define RX_PROTO_ERR_INVALID_UNTAGGED_OPCODE 0x00000005 + +#define RX_PROTO_ERR_STAG_INVALID 0x00000006 +#define RX_PROTO_ERR_STAG_BASE_BOUNDS 0x00000007 +#define RX_PROTO_ERR_STAG_ACCESS_RIGHTS 0x00000008 +#define RX_PROTO_ERR_STAG_PROTECTION 0x00000009 +#define RX_PROTO_ERR_STAG_TO_WRAP 0x0000000A + +#define RX_PROTO_ERR_INVALID_DDP_VERSION 0x0000000B +#define RX_PROTO_ERR_INVALID_RDMAP_VERSION 0x0000000C +#define RX_PROTO_ERR_INVALID_DDP_QUEUE_NUMBER 0x0000000D +#define RX_PROTO_ERR_IRD_EXCEEDED 0x0000000E + +#define RX_PROTO_ERR_MSN_GAP 0x0000000F +#define RX_PROTO_ERR_MSN_RANGE 0x00000010 + +#define RX_PROTO_ERR_NO_RCV_BUFF_AVAIL 0x00000011 +#define RX_PROTO_ERR_RCV_BASE_BOUNDS 0x00000012 +#define RX_PROTO_ERR_RCV_MO_WRAP 0x00000013 + +#define RX_PROTO_ERR_INVALID_MPA_CRC 0x00000014 + +#define RX_PROTO_ERR_NO_RCV_BUFF_POSTED 0x00000080 + +#define RX_PROTO_ERR_TERM_MSG_RECEIVED 0x000000FF + +/* L5 */ +#define L5_TCP_MAX_DACK 2 + +/* Iscsi */ + +//#define THIN_CONN_ESTAB + +#define RDMA_CONFIG_CRC_OFFSET_SHIFT 18 + +#define VCID_SIZE 128 +#define VCID_SHIFT 7 + +#define CID_ENC(_idx) ((_idx)<<VCID_SHIFT) + +#define CID_ISCSI_CONF_PARAMS CID_ENC(46) // context ID of iSCSI configuration params + +#define MAX_RQ_BUF_SIZE 256 +#define ISCSI_CRC_SIZE 4 +#define ISCSI_CRC_SIZE_LOG2 2 +#define ISCSI_HDR_SIZE 48 +#define ISCSI_CRC_RESULT 0x1c2d19ed + +#define ISCSI_CRC_TABLE_SIZE 256 + +#define ISCSI_PROCESS_ERROR (-1) +#define ISCSI_PROCESS_WARNING (-2) +#define ISCSI_SILENT_DROP (-3) + +/* Completion types */ +#define ISCSI_COMP_TYPE_MP (0<<0) +#define ISCSI_COMP_TYPE_FP (1<<0) + +/* Command types for placement in RV2P */ +#define ISCSI_PLACE_TYPE_RQ (0<<0) +#define ISCSI_PLACE_TYPE_SGL (1<<0) + +/* RV2P iscsi placement opcodes */ +#define GENERIC_OPCODE_RV2PPQ_VALUE_ISCSI_SGL_PLACE (22<<0) +#define GENERIC_OPCODE_RV2PPQ_VALUE_ISCSI_RQ_PLACE (23<<0) +#define GENERIC_OPCODE_RV2PPQ_VALUE_ISCSI_RQ_FLUSH (24<<0) +#define GENERIC_OPCODE_RV2PPQ_VALUE_ISCSI_SGL_FLUSH (25<<0) + +/* COM L5 (iSCSI/RDMA) opaque types */ +#define L5_OPAQUE_TCP_ACK_TYPE (0x80) +#define L5_OPAQUE_TCP_ERROR_TYPE (0x81) + +/* COM iSCSI opaque types */ +#define ISCSI_OPAQUE_COMPLETION_TYPE (0x82) +#define ISCSI_OPAQUE_FREE_MBUF_TYPE (0x83) +#define ISCSI_OPAQUE_ERROR_TYPE (0x84) +#define ISCSI_OPAQUE_FREE_CU_MBUF_TYPE (0x85) + +#define HDR_ISCSI_OPCODE (0x3f<<0) + +#define ISCSI_INVALID_VALUE (0xffffffff) + +#define TCP_L5CM_MAX_RETRIES 3 + +typedef struct iscsi_ctx_offsets +{ + u32_t task_offset; // offset of the task array + u32_t r2tq_offset; // offset of R2TQ section + + u32_t max_num_of_tasks; // maximal number of pending tasks + u32_t max_num_of_ccells; // maximal number of ccells +} iscsi_ctx_offsets_t; + + +/* + * rv2ppq_iscsi_sgl_place definition + */ +typedef struct rv2ppq_iscsi_sgl_place +{ + u32_t iscsi_sgl_place_cid; + u32_t iscsi_sgl_place_mbuf_cluster; + u16_t iscsi_sgl_place_operand_flags; + #define ISCSI_PLACE_OPERAND_FLAGS_LAST_PKT (1<<7) + #define ISCSI_PLACE_OPERAND_FLAGS_FLUSH (1<<11) + #define ISCSI_PLACE_OPERAND_FLAGS_USE_SEED (1<<12) + #define ISCSI_PLACE_OPERAND_FLAGS_DIGEST_EN (1<<13) + #define ISCSI_PLACE_OPERAND_FLAGS_COMPLETE (1<<14) + /* overloading bit 14 */ + #define ISCSI_PLACE_OPERAND_FLAGS_CU_PKT (1<<14) + #define ISCSI_PLACE_OPERAND_FLAGS_FREE_MBUF (1<<15) + + u8_t iscsi_sgl_place_tcp_flags; + u8_t iscsi_sgl_place_opcode; + u16_t iscsi_sgl_place_offset; //cut in COM + u16_t iscsi_sgl_place_length; //cut in COM + u16_t iscsi_sgl_place_ctx_offset_to_pad_baddr; + u16_t iscsi_sgl_place_num_pad_bytes; + u32_t iscsi_sgl_place_reserved1; + u32_t iscsi_sgl_place_tcp_ack_sn; + u32_t iscsi_sgl_place_reserved2[2]; //cut in COM + u32_t iscsi_sgl_place_crc_seed; + #define ISCSI_PLACE_CRC_SEED_VAL (0xFFFFFFFF) + + u32_t iscsi_sgl_place_task_cache_key; + u32_t iscsi_sgl_place_task_cid; + u32_t iscsi_sgl_place_rdma_action; +} rv2ppq_iscsi_sgl_place_t; + +/* + * rv2ppq_iscsi_rq_place definition + */ +typedef struct rv2ppq_iscsi_rq_place +{ + u32_t iscsi_rq_place_cid; + u32_t iscsi_rq_place_mbuf_cluster; + u16_t iscsi_rq_place_operand_flags; + #define ISCSI_PLACE_OPERAND_FLAGS_PAGE_SIZE_SHIFT (8) + #define ISCSI_PLACE_OPERAND_FLAGS_PAGE_SIZE_MASK (0xf<<8) + + u8_t iscsi_rq_place_tcp_flags; + u8_t iscsi_rq_place_opcode; + u16_t iscsi_rq_place_offset; //cut in COM + u16_t iscsi_rq_place_length; //cut in COM + u16_t iscsi_rq_place_ctx_offset_to_pad_baddr; + u16_t iscsi_rq_place_num_pad_bytes; + u32_t iscsi_rq_place_first_page_offset; + u32_t iscsi_rq_place_tcp_ack_sn; + u32_t iscsi_rq_place_page_table_base_addr_h; //cut in COM + u32_t iscsi_rq_place_page_table_base_addr_l; //cut in COM + u32_t iscsi_rq_place_crc_seed; + u32_t iscsi_rq_place_rbdc_key; + u32_t iscsi_rq_place_rq_buffer_offset; + u32_t iscsi_rq_place_rdma_action; +} rv2ppq_iscsi_rq_place_t; + +/* + * rv2ppq_iscsi_sgl_flush definition + */ +typedef struct rv2ppq_iscsi_sgl_flush +{ + u32_t iscsi_sgl_flush_task_cid; + u32_t iscsi_sgl_flush_unused_a; + u16_t iscsi_sgl_flush_unsused_b; + u8_t iscsi_sgl_flush_unsused_c; + u8_t iscsi_sgl_flush_opcode; + u32_t iscsi_sgl_flush_unsused_d[9]; +} rv2ppq_iscsi_sgl_flush_t; + +/* + * rv2ppq_iscsi_rq_flush definition + */ +typedef struct rv2ppq_iscsi_rq_flush +{ + u32_t iscsi_rq_flush_cid; + u32_t iscsi_rq_flush_unsused_a; + u16_t iscsi_rq_flush_unsused_b; + u8_t iscsi_rq_flush_unsused_c; + u8_t iscsi_rq_flush_opcode; + u32_t iscsi_rq_flush_unsused_d; + u16_t iscsi_rq_flush_rbdc_key; + u16_t iscsi_rq_flush_unsused_e; + u32_t iscsi_rq_flush_unsused_f[7]; + u32_t iscsi_rq_flush_rdma_spec; +} rv2ppq_iscsi_rq_flush_t; + +/* + * comq_iscsi_sgl_place definition + */ +typedef struct comq_iscsi_sgl_place +{ + u32_t cid; + u32_t mbuf_cluster; + u16_t operand_flags; + u8_t tcp_flags; + u8_t opcode; + u16_t ctx_offset_to_pad_baddr; + u16_t num_pad_bytes; + u32_t unused; + u32_t tcp_ack_sn; + u32_t crc_result; + u32_t reserved; + u32_t task_cid; + +} comq_iscsi_sgl_place_t; + +typedef struct itt32_fields +{ + u32_t task_rsrv : 16; + u32_t task_type : 2; + u32_t task_idx : 14; + +} itt32_fields_t; + +typedef union itt32_union +{ + itt32_fields_t fields; + u32_t itt32; + +} itt32_union_t; + +/* + * rv2ppq_opaque_iscsi definition + */ +typedef struct rv2ppq_opaque_iscsi_comp_msg_a +{ + u32_t cid; + u8_t unused_a; + u8_t iscsi_err_code; + u16_t hdr_itt; + u16_t opaque_flags_opcode; + u8_t tcp_flags; // Only 8 bits relevant + u8_t opcode; + u16_t o_iscsi_unused_b[2]; + u32_t hdr_dword0; + u32_t hdr_dword1; + u32_t tcp_ack_sn; + u32_t o_iscsi_unused_c[2]; + u32_t hdr_exp_cmd_sn; + u32_t hdr_max_cmd_sn; + u32_t hdr_res_count; +} rv2ppq_opaque_iscsi_comp_msg_a_t; + +typedef struct rv2ppq_opaque_iscsi_comp_msg_b +{ + u32_t cid; + u32_t reserved0; + u16_t opaque_flags_opcode; + u8_t reserved1; + u8_t opcode; + u16_t o_iscsi_unused_a[2]; + u32_t hdr_dword2; + u32_t hdr_dword3; + u32_t hdr_ttt; + u32_t o_iscsi_unused_b[2]; + u32_t hdr_stat_sn; + u32_t hdr_dword9; + u32_t hdr_dword10; +} rv2ppq_opaque_iscsi_comp_msg_b_t; + +typedef struct rv2ppq_opaque_iscsi_free_mbuf +{ + u32_t cid; + u32_t mbuf_cluster; + u16_t opaque_flags_opcode; + u8_t rsrv; + u8_t opcode; + u16_t o_iscsi_unused_a[2]; + u16_t o_iscsi_allowed16[6]; + u32_t o_iscsi_unused_b[2]; + u32_t o_iscsi_allowed32[3]; +} rv2ppq_opaque_iscsi_free_mbuf_t; + +typedef union rv2ppq_opaque_iscsi +{ + rv2ppq_opaque_iscsi_comp_msg_a_t rv2p_o_comp_msg_a; + rv2ppq_opaque_iscsi_comp_msg_b_t rv2p_o_comp_msg_b; + rv2ppq_opaque_iscsi_free_mbuf_t rv2p_o_free_mbuf; + +} rv2ppq_opaque_iscsi_t; + +// Used for TCP messages from RXP to COM (Mutual to RDMA and iSCSI) +typedef struct rv2ppq_opaque_l5 +{ + u32_t cid; + u32_t o_l5_allowed32_a; + u16_t opaque_flags_opcode; + u8_t tcp_flags; + u8_t opcode; + u16_t o_l5_unused_a[2]; + u16_t o_l5_allowed16[4]; + u32_t tcp_ack_sn; + u32_t o_l5_unused_b[2]; + u32_t o_l5_allowed32_b[3]; +} rv2ppq_opaque_l5_t; + +/* + * comq_opaque_iscsi definition + */ +typedef struct comq_opaque_iscsi_comp_msg_a +{ + u32_t cid; + u8_t unused; + u8_t iscsi_err_code; + u16_t hdr_itt; + u16_t opaque_flags_opcode; + u8_t tcp_flags; // Only 8 bits relevant + u8_t opcode; + u32_t hdr_dword0; + u32_t hdr_dword1; + u32_t tcp_ack_sn; + u32_t hdr_exp_cmd_sn; + u32_t hdr_max_cmd_sn; + u32_t hdr_res_count; + +} comq_opaque_iscsi_comp_msg_a_t; + +typedef struct comq_opaque_iscsi_comp_msg_b +{ + u32_t cid; + u32_t reserved0; + u16_t opaque_flags_opcode; + u8_t reserved1; + u8_t opcode; + u32_t hdr_dword2; + u32_t hdr_dword3; + u32_t hdr_ttt; + u32_t hdr_stat_sn; + u32_t hdr_dword9; + u32_t hdr_dword10; + +} comq_opaque_iscsi_comp_msg_b_t; + +typedef union comq_opaque_iscsi +{ + comq_opaque_iscsi_comp_msg_a_t com_o_comp_msg_a; + comq_opaque_iscsi_comp_msg_b_t com_o_comp_msg_b; + +} comq_opaque_iscsi_t; + +// TCP opaque message for L5 (no data) +typedef struct comq_opaque_l5 +{ + u32_t cid; + u32_t o_l5_allowed32_a; + u16_t opaque_flags_opcode; + u8_t tcp_flags; + u8_t opcode; + u16_t o_l5_allowed16[4]; + u32_t tcp_ack_sn; + u32_t o_l5_allowed32_b[3]; + +} comq_opaque_l5_t; + +typedef struct rv2ppq_opaque_iscsi_kcqe_comp +{ + u32_t cid; + u32_t iscsi_conn_id; + u16_t opaque_flags_opcode; + u8_t reserved1; + u8_t opcode; + u16_t unused_a[2]; + u32_t reserved2[3]; + u32_t unused_b[2]; + u32_t status_code; + u32_t reserved3[2]; +} rv2ppq_opaque_iscsi_kcqe_comp_t; + +typedef struct comq_opaque_iscsi_kcqe_comp +{ + u32_t cid; + u32_t iscsi_conn_id; + u16_t opaque_flags_opcode; + u8_t reserved1; + u8_t opcode; + u32_t reserved2[3]; + u32_t status_code; + u32_t reserved3[2]; + +} comq_opaque_iscsi_kcqe_comp_t; + +// L5 context manager parameters context struct +typedef struct l5_cm_fixed_connect_context +{ + u32_t fixed_seed /* 32 bits of secret passed by the driver for port 0 */; + u32_t rsrv[31] /* */; + +} l5_cm_fixed_connect_context_t; + +// TCP general message for L5 +typedef struct comq_l5_tcp +{ + u32_t cid; + u32_t reserved0; + u16_t reserved1; + u8_t tcp_flags; + #define L5_FLAGS_TCP_SMALL_WIN (1<<0) + #define L5_FLAGS_TCP_SILENT_DROP (1<<1) + #define L5_FLAGS_TCP_RELEASE_MBUF (1<<2) + #define L5_FLAGS_TCP_ACK_PROCESS (1<<3) + #define L5_FLAGS_TCP_PURE_ACK (1<<4) // No payload and no window update + #define L5_FLAGS_TCP_IP_FRAG (1<<5) + #define L5_FLAGS_TCP_IP_OPTION (1<<6) + #define L5_FLAGS_TCP_URGENT_FLAG (1<<7) + + u8_t reserved2; + u32_t reserved3[2]; + u32_t tcp_ack_sn; + u32_t reserved4[3]; + +} comq_l5_tcp_t; + + + + +/* + * rv2ppq_l5_place definition + */ +typedef struct rv2ppq_l5_place_b +{ + u32_t l5_place_cid; + u32_t l5_place_mbuf_cluster; + u16_t l5_place_operand_flags; + #define L5_PLACE_OPERAND_FLAGS_MARKERS_PRESENT (1<<0) + #define L5_PLACE_OPERAND_FLAGS_NEW_ISLAND (1<<1) + #define L5_PLACE_OPERAND_FLAGS_TCP_HOLE_CLOSED (1<<2) + #define L5_PLACE_OPERAND_FLAGS_IN_ORDER (1<<3) + #define L5_PLACE_OPERAND_FLAGS_LBIT_STATUS (1<<4) + #define L5_PLACE_OPERAND_FLAGS_FLUSH (1<<5) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ (0xf<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_256 (0<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_512 (1<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_1K (2<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_2K (3<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_4K (4<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_8K (5<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_16K (6<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_32K (7<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_64K (8<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_128K (9<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_256K (10<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_512K (11<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_1M (12<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_2M (13<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_4M (14<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_8M (15<<8) + + u8_t l5_place_knum; + u8_t l5_place_opcode; + u16_t l5_place_offset; + u16_t l5_place_length; + u16_t l5_place_offset_to_first_marker; + u16_t l5_place_rbdc_key; + u32_t l5_place_first_page_offset; + u16_t l5_place_l5_header_length; + u16_t l5_place_l5_cmd_type; + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE (0xf<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_UNDEFINED (0<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_SEND (1<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_SEND_W_SE (2<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_SEND_W_INV (3<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_SEND_W_SE_INV (4<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_RDMA_WRITE (5<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_RDMA_READ (6<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_RDMA_READ_W_INV (7<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_WINDOW_BIND (8<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_FAST_REGISTER (9<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_LOCAL_INVALIDATE (10<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_RDMA_READ_RESPONSE (11<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_TCP_ACK (12<<0) + + u32_t l5_place_page_table_base_addr_h; + u32_t l5_place_page_table_base_addr_l; + u32_t l5_place_tcp_ack_seq; + u32_t l5_place_sink_bfr_target_offset_h; + u32_t l5_place_sink_bfr_target_offset_l; + u8_t l5_place_rdma_action; // no need to be cleared by RXP, RV2P will do it + u8_t l5_place_cs16_pkt_len; + u16_t l5_place_cs16; +} rv2ppq_l5_place_b_t; + +typedef struct rv2ppq_l5_place_l +{ + u32_t l5_place_cid; + u32_t l5_place_mbuf_cluster; + u8_t l5_place_opcode; + u8_t l5_place_knum; + u16_t l5_place_operand_flags; + u16_t l5_place_length; + u16_t l5_place_offset; + u16_t l5_place_rbdc_key; + u16_t l5_place_offset_to_first_marker; + u32_t l5_place_first_page_offset; + u16_t l5_place_l5_cmd_type; + u16_t l5_place_l5_header_length; + u32_t l5_place_page_table_base_addr_h; + u32_t l5_place_page_table_base_addr_l; + u32_t l5_place_tcp_ack_seq; + u32_t l5_place_sink_bfr_target_offset_h; + u32_t l5_place_sink_bfr_target_offset_l; + u16_t l5_place_cs16; + u8_t l5_place_cs16_pkt_len; + u8_t l5_place_rdma_action; // no need to be cleared by RXP, RV2P will do it +} rv2ppq_l5_place_l_t; + +#if defined(LITTLE_ENDIAN) + typedef rv2ppq_l5_place_l_t rv2ppq_l5_place_t; +#elif defined(BIG_ENDIAN) + typedef rv2ppq_l5_place_b_t rv2ppq_l5_place_t; +#endif + + +/* + * rv2ppq_l5_flush definition + */ +typedef struct rv2ppq_l5_flush_b +{ + u32_t unused_0[2]; + u16_t unused_1; + u8_t unused_2; + u8_t l5_flush_opcode; + u32_t unused_3; + u16_t l5_flush_rbdc_key; + u16_t unused_4; + u32_t unused_5[7]; + u8_t l5_flush_rdma_action; // no need to be cleared by RXP, RV2P will do it + u8_t l5_flush_cs16_pkt_len; + u16_t l5_flush_cs16; +} rv2ppq_l5_flush_b_t; + +typedef struct rv2ppq_l5_flush_l +{ + u32_t unused_0[2]; + u8_t l5_flush_opcode; + u8_t unused_2; + u16_t unused_1; + u32_t unused_3; + u16_t unused_4; + u16_t l5_flush_rbdc_key; + u32_t unused_5[7]; + u16_t l5_flush_cs16; + u8_t l5_flush_cs16_pkt_len; + u8_t l5_flush_rdma_action; // no need to be cleared by RXP, RV2P will do it +} rv2ppq_l5_flush_l_t; + +#if defined(LITTLE_ENDIAN) + typedef rv2ppq_l5_flush_l_t rv2ppq_l5_flush_t; +#elif defined(BIG_ENDIAN) + typedef rv2ppq_l5_flush_b_t rv2ppq_l5_flush_t; +#endif + + + +/* + * comq_l5_place definition + */ +typedef struct comq_l5_place_b +{ + u32_t l5_place_cid; + u32_t l5_place_mbuf_cluster; + u16_t l5_place_operand_flags; + #define L5_PLACE_OPERAND_FLAGS_MARKERS_PRESENT (1<<0) + #define L5_PLACE_OPERAND_FLAGS_NEW_ISLAND (1<<1) + #define L5_PLACE_OPERAND_FLAGS_TCP_HOLE_CLOSED (1<<2) + #define L5_PLACE_OPERAND_FLAGS_IN_ORDER (1<<3) + #define L5_PLACE_OPERAND_FLAGS_LBIT_STATUS (1<<4) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ (0xf<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_256 (0<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_512 (1<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_1K (2<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_2K (3<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_4K (4<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_8K (5<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_16K (6<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_32K (7<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_64K (8<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_128K (9<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_256K (10<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_512K (11<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_1M (12<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_2M (13<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_4M (14<<8) + #define L5_PLACE_OPERAND_FLAGS_PG_SZ_8M (15<<8) + + u8_t l5_place_knum; + u8_t l5_place_opcode; + u16_t l5_place_offset_to_first_marker; + u16_t l5_place_rbdc_key; + u32_t l5_place_first_page_offset; + u16_t l5_place_l5_header_length; + u16_t l5_place_l5_cmd_type; + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE (0xf<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_UNDEFINED (0<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_SEND (1<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_SEND_W_SE (2<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_SEND_W_INV (3<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_SEND_W_SE_INV (4<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_RDMA_WRITE (5<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_RDMA_READ (6<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_RDMA_READ_W_INV (7<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_WINDOW_BIND (8<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_FAST_REGISTER (9<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_LOCAL_INVALIDATE (10<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_RDMA_READ_RESPONSE (11<<0) + #define L5_PLACE_L5_CMD_TYPE_CMD_VALUE_TCP_ACK (12<<0) + + u32_t l5_place_tcp_ack_seq; + u32_t l5_place_sink_bfr_target_offset_h; + u32_t l5_place_sink_bfr_target_offset_l; + u8_t l5_place_rdma_action; + u8_t l5_place_cs16_pkt_len; + u16_t l5_place_cs16; +} comq_l5_place_b_t; + +typedef struct comq_l5_place_l + +{ + u32_t l5_place_cid; + u32_t l5_place_mbuf_cluster; + u8_t l5_place_opcode; + u8_t l5_place_knum; + u16_t l5_place_operand_flags; + u16_t l5_place_rbdc_key; + u16_t l5_place_offset_to_first_marker; + u32_t l5_place_first_page_offset; + u16_t l5_place_l5_cmd_type; + u16_t l5_place_l5_header_length; + u32_t l5_place_tcp_ack_seq; + u32_t l5_place_sink_bfr_target_offset_h; + u32_t l5_place_sink_bfr_target_offset_l; + u16_t l5_place_cs16; + u8_t l5_place_cs16_pkt_len; + u8_t l5_place_rdma_action; +} comq_l5_place_l_t; + +#if defined(LITTLE_ENDIAN) + typedef comq_l5_place_l_t comq_l5_place_t; +#elif defined(BIG_ENDIAN) + typedef comq_l5_place_b_t comq_l5_place_t; +#endif + + +/* + * comq_l5_flush definition + */ +typedef struct comq_l5_flush_b +{ + u32_t unused_0[2]; + u16_t unused_1; + u8_t unused_2; + u8_t l5_flush_opcode; + u16_t l5_flush_rbdc_key; + u16_t unused_3; + u32_t unused_4[5]; + u8_t l5_flush_rdma_action; + u8_t l5_flush_cs16_pkt_len; + u16_t l5_flush_cs16; +} comq_l5_flush_b_t; + +typedef struct comq_l5_flush_l +{ + u32_t unused_0[2]; + u8_t l5_flush_opcode; + u8_t unused_2; + u16_t unused_1; + u16_t unused_3; + u16_t l5_flush_rbdc_key; + u32_t unused_4[5]; + u16_t l5_flush_cs16; + u8_t l5_flush_cs16_pkt_len; + u8_t l5_flush_rdma_action; +} comq_l5_flush_l_t; + +#if defined(LITTLE_ENDIAN) + typedef comq_l5_flush_l_t comq_l5_flush_t; +#elif defined(BIG_ENDIAN) + typedef comq_l5_flush_b_t comq_l5_flush_t; +#endif + +/* + * l5_local_region_table_entry_b definition + */ +typedef struct l5_local_region_table_entry_b +{ + u8_t rte_flags; + + u8_t rte_bind_cnt; + u16_t rte_pd; +} l5_local_region_table_entry_b_t; + + + +/* + * l5_local_region_table_entry_b definition + */ +typedef struct l5_local_region_table_entry_b_xi +{ + u8_t rte_flags; + #define RTE_FLAGS_FLAGS_MASK (0xff<<0) + #define RTE_FLAGS_FLAGS_MASK_UNDEFINED (0<<0) + #define RTE_FLAGS_FLAGS_MASK_VALID (1<<0) + #define RTE_FLAGS_FLAGS_MASK_LOCAL_READ (2<<0) + #define RTE_FLAGS_FLAGS_MASK_LOCAL_WRITE (4<<0) + #define RTE_FLAGS_FLAGS_MASK_REMOTE_REGION (8<<0) + #define RTE_FLAGS_FLAGS_MASK_ALLOW_WIND_BIND (16<<0) + #define RTE_FLAGS_FLAGS_MASK_INVALIDATE_IN_PROGRESS (32<<0) + #define RTE_FLAGS_FLAGS_MASK_RX_FLUSH_IN_PROGRESS (64<<0) + + u8_t rte_bind_cnt; + u16_t rte_pd; +} l5_local_region_table_entry_b_xi_t; + + +/* + * l5_local_region_table_entry_l definition + */ +typedef struct l5_local_region_table_entry_l +{ + u16_t rte_pd; + u8_t rte_bind_cnt; + u8_t rte_flags; + +} l5_local_region_table_entry_l_t; + + + +/* + * l5_local_region_table_entry_l definition + */ +typedef struct l5_local_region_table_entry_l_xi +{ + u16_t rte_pd; + u8_t rte_bind_cnt; + u8_t rte_flags; + #define RTE_FLAGS_FLAGS_MASK (0xff<<0) + #define RTE_FLAGS_FLAGS_MASK_UNDEFINED (0<<0) + #define RTE_FLAGS_FLAGS_MASK_VALID (1<<0) + #define RTE_FLAGS_FLAGS_MASK_LOCAL_READ (2<<0) + #define RTE_FLAGS_FLAGS_MASK_LOCAL_WRITE (4<<0) + #define RTE_FLAGS_FLAGS_MASK_REMOTE_REGION (8<<0) + #define RTE_FLAGS_FLAGS_MASK_ALLOW_WIND_BIND (16<<0) + #define RTE_FLAGS_FLAGS_MASK_INVALIDATE_IN_PROGRESS (32<<0) + #define RTE_FLAGS_FLAGS_MASK_RX_FLUSH_IN_PROGRESS (64<<0) + +} l5_local_region_table_entry_l_xi_t; + + +/* + * l5_local_region_table_entry select + */ +#if defined(LITTLE_ENDIAN) + typedef l5_local_region_table_entry_l_t l5_local_region_table_entry_t; + typedef l5_local_region_table_entry_l_xi_t l5_local_region_table_entry_xi_t; +#elif defined(BIG_ENDIAN) + typedef l5_local_region_table_entry_b_t l5_local_region_table_entry_t; + typedef l5_local_region_table_entry_b_xi_t l5_local_region_table_entry_xi_t; +#endif + + +/* + * l5_remote_region_table_entry_b definition + */ +typedef struct l5_remote_region_table_entry_b +{ + u8_t rte_flags; + + u8_t rte_wintbl_stag_hi; + u16_t rte_wintbl_stag_lo; +} l5_remote_region_table_entry_b_t; + + + +/* + * l5_remote_region_table_entry_b definition + */ +typedef struct l5_remote_region_table_entry_b_xi +{ + u8_t rte_flags; + #define RTE_FLAGS_FLAGS_MASK (0xff<<0) + #define RTE_FLAGS_FLAGS_MASK_UNDEFINED (0<<0) + #define RTE_FLAGS_FLAGS_MASK_VALID (1<<0) + #define RTE_FLAGS_FLAGS_MASK_LOCAL_READ (2<<0) + #define RTE_FLAGS_FLAGS_MASK_LOCAL_WRITE (4<<0) + #define RTE_FLAGS_FLAGS_MASK_REMOTE_REGION (8<<0) + #define RTE_FLAGS_FLAGS_MASK_ALLOW_WIND_BIND (16<<0) + #define RTE_FLAGS_FLAGS_MASK_INVALIDATE_IN_PROGRESS (32<<0) + #define RTE_FLAGS_FLAGS_MASK_RX_FLUSH_IN_PROGRESS (64<<0) + + u8_t rte_wintbl_stag_hi; + u16_t rte_wintbl_stag_lo; +} l5_remote_region_table_entry_b_xi_t; + + +/* + * l5_remote_region_table_entry_l definition + */ +typedef struct l5_remote_region_table_entry_l +{ + u16_t rte_wintbl_stag_lo; + u8_t rte_wintbl_stag_hi; + u8_t rte_flags; + +} l5_remote_region_table_entry_l_t; + + + +/* + * l5_remote_region_table_entry_l definition + */ +typedef struct l5_remote_region_table_entry_l_xi +{ + u16_t rte_wintbl_stag_lo; + u8_t rte_wintbl_stag_hi; + u8_t rte_flags; + #define RTE_FLAGS_FLAGS_MASK (0xff<<0) + #define RTE_FLAGS_FLAGS_MASK_UNDEFINED (0<<0) + #define RTE_FLAGS_FLAGS_MASK_VALID (1<<0) + #define RTE_FLAGS_FLAGS_MASK_LOCAL_READ (2<<0) + #define RTE_FLAGS_FLAGS_MASK_LOCAL_WRITE (4<<0) + #define RTE_FLAGS_FLAGS_MASK_REMOTE_REGION (8<<0) + #define RTE_FLAGS_FLAGS_MASK_ALLOW_WIND_BIND (16<<0) + #define RTE_FLAGS_FLAGS_MASK_INVALIDATE_IN_PROGRESS (32<<0) + #define RTE_FLAGS_FLAGS_MASK_RX_FLUSH_IN_PROGRESS (64<<0) + +} l5_remote_region_table_entry_l_xi_t; + + +/* + * l5_remote_region_table_entry select + */ +#if defined(LITTLE_ENDIAN) + typedef l5_remote_region_table_entry_l_t l5_remote_region_table_entry_t; + typedef l5_remote_region_table_entry_l_xi_t l5_remote_region_table_entry_xi_t; +#elif defined(BIG_ENDIAN) + typedef l5_remote_region_table_entry_b_t l5_remote_region_table_entry_t; + typedef l5_remote_region_table_entry_b_xi_t l5_remote_region_table_entry_xi_t; +#endif + + +/* + * l5_region_ref_cnt_table_entry_b definition + */ +typedef struct l5_region_ref_cnt_table_entry_b +{ + u16_t rrcte_pidx; + u16_t rrcte_cidx; +} l5_region_ref_cnt_table_entry_b_t; + + + +/* + * l5_region_ref_cnt_table_entry_b definition + */ +typedef struct l5_region_ref_cnt_table_entry_b_xi +{ + u16_t rrcte_pidx; + u16_t rrcte_cidx; +} l5_region_ref_cnt_table_entry_b_xi_t; + + +/* + * l5_region_ref_cnt_table_entry_l definition + */ +typedef struct l5_region_ref_cnt_table_entry_l +{ + u16_t rrcte_cidx; + u16_t rrcte_pidx; +} l5_region_ref_cnt_table_entry_l_t; + + + +/* + * l5_region_ref_cnt_table_entry_l definition + */ +typedef struct l5_region_ref_cnt_table_entry_l_xi +{ + u16_t rrcte_cidx; + u16_t rrcte_pidx; +} l5_region_ref_cnt_table_entry_l_xi_t; + + +/* + * l5_region_ref_cnt_table_entry select + */ +#if defined(LITTLE_ENDIAN) + typedef l5_region_ref_cnt_table_entry_l_t l5_region_ref_cnt_table_entry_t; + typedef l5_region_ref_cnt_table_entry_l_xi_t l5_region_ref_cnt_table_entry_xi_t; +#elif defined(BIG_ENDIAN) + typedef l5_region_ref_cnt_table_entry_b_t l5_region_ref_cnt_table_entry_t; + typedef l5_region_ref_cnt_table_entry_b_xi_t l5_region_ref_cnt_table_entry_xi_t; +#endif + + +/* + * l5_window_table_entry_b definition + */ +typedef struct l5_window_table_entry_b +{ + u32_t wte_virtual_base_addr_hi; + u32_t wte_virtual_base_addr_lo; + u32_t wte_pt_phy_base_addr_hi; + u32_t wte_pt_phy_base_addr_lo; + u32_t wte_length; + u32_t wte_qp_or_pd; + u16_t wte_region_table_index; + u16_t wte_cache_key; + u16_t wte_flags; + + u8_t wte_bind_cnt; + u8_t wte_stag_key; +} l5_window_table_entry_b_t; + + + +/* + * l5_window_table_entry_b definition + */ +typedef struct l5_window_table_entry_b_xi +{ + u32_t wte_virtual_base_addr_hi; + u32_t wte_virtual_base_addr_lo; + u32_t wte_pt_phy_base_addr_hi; + u32_t wte_pt_phy_base_addr_lo; + u32_t wte_length; + u32_t wte_qp_or_pd; + u16_t wte_region_table_index; + u16_t wte_cache_key; + u16_t wte_flags; + #define WTE_FLAGS_REGION_PAGE_SIZE (0xf<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_256 (0<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_512 (1<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_1K (2<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_2K (3<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_4K (4<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_8K (5<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_16K (6<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_32K (7<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_64K (8<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_128K (9<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_256K (10<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_512K (11<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_1M (12<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_2M (13<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_4M (14<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_8M (15<<0) + #define WTE_FLAGS_WT_FLAGS (0xfff<<4) + #define WTE_FLAGS_WT_FLAGS_WT_UNDEFINED (0<<4) + #define WTE_FLAGS_WT_FLAGS_VALID (1<<4) + #define WTE_FLAGS_WT_FLAGS_REGION (2<<4) + #define WTE_FLAGS_WT_FLAGS_UNBOUND_WINDOW (4<<4) + #define WTE_FLAGS_WT_FLAGS_BOUND_WINDOW (8<<4) + #define WTE_FLAGS_WT_FLAGS_REMOTE_READ (16<<4) + #define WTE_FLAGS_WT_FLAGS_REMOTE_WRITE (32<<4) + #define WTE_FLAGS_WT_FLAGS_ALLOW_WINDOW_BINDS (64<<4) + #define WTE_FLAGS_WT_FLAGS_INVALIDATE_IN_PROGRESS (128<<4) + #define WTE_FLAGS_WT_FLAGS_RX_FLUSH_IN_PROGRESS (256<<4) + #define WTE_FLAGS_WT_FLAGS_READ_W_LINV_IN_PROGRESS (512<<4) + #define WTE_FLAGS_WT_FLAGS_DEALLOCATE_FLUSH_INITIATED (1024<<4) + #define WTE_FLAGS_WT_FLAGS_DEALLOCATE_FLUSH_COMPLETE (2048<<4) + + u8_t wte_bind_cnt; + u8_t wte_stag_key; +} l5_window_table_entry_b_xi_t; + + +/* + * l5_window_table_entry_l definition + */ +typedef struct l5_window_table_entry_l +{ + u32_t wte_virtual_base_addr_hi; + u32_t wte_virtual_base_addr_lo; + u32_t wte_pt_phy_base_addr_hi; + u32_t wte_pt_phy_base_addr_lo; + u32_t wte_length; + u32_t wte_qp_or_pd; + u16_t wte_cache_key; + u16_t wte_region_table_index; + u8_t wte_stag_key; + u8_t wte_bind_cnt; + u16_t wte_flags; + +} l5_window_table_entry_l_t; + + + +/* + * l5_window_table_entry_l definition + */ +typedef struct l5_window_table_entry_l_xi +{ + u32_t wte_virtual_base_addr_hi; + u32_t wte_virtual_base_addr_lo; + u32_t wte_pt_phy_base_addr_hi; + u32_t wte_pt_phy_base_addr_lo; + u32_t wte_length; + u32_t wte_qp_or_pd; + u16_t wte_cache_key; + u16_t wte_region_table_index; + u8_t wte_stag_key; + u8_t wte_bind_cnt; + u16_t wte_flags; + #define WTE_FLAGS_REGION_PAGE_SIZE (0xf<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_256 (0<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_512 (1<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_1K (2<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_2K (3<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_4K (4<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_8K (5<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_16K (6<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_32K (7<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_64K (8<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_128K (9<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_256K (10<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_512K (11<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_1M (12<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_2M (13<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_4M (14<<0) + #define WTE_FLAGS_REGION_PAGE_SIZE_8M (15<<0) + #define WTE_FLAGS_WT_FLAGS (0xfff<<4) + #define WTE_FLAGS_WT_FLAGS_WT_UNDEFINED (0<<4) + #define WTE_FLAGS_WT_FLAGS_VALID (1<<4) + #define WTE_FLAGS_WT_FLAGS_REGION (2<<4) + #define WTE_FLAGS_WT_FLAGS_UNBOUND_WINDOW (4<<4) + #define WTE_FLAGS_WT_FLAGS_BOUND_WINDOW (8<<4) + #define WTE_FLAGS_WT_FLAGS_REMOTE_READ (16<<4) + #define WTE_FLAGS_WT_FLAGS_REMOTE_WRITE (32<<4) + #define WTE_FLAGS_WT_FLAGS_ALLOW_WINDOW_BINDS (64<<4) + #define WTE_FLAGS_WT_FLAGS_INVALIDATE_IN_PROGRESS (128<<4) + #define WTE_FLAGS_WT_FLAGS_RX_FLUSH_IN_PROGRESS (256<<4) + #define WTE_FLAGS_WT_FLAGS_READ_W_LINV_IN_PROGRESS (512<<4) + #define WTE_FLAGS_WT_FLAGS_DEALLOCATE_FLUSH_INITIATED (1024<<4) + #define WTE_FLAGS_WT_FLAGS_DEALLOCATE_FLUSH_COMPLETE (2048<<4) + +} l5_window_table_entry_l_xi_t; + + +/* + * l5_window_table_entry select + */ +#if defined(LITTLE_ENDIAN) + typedef l5_window_table_entry_l_t l5_window_table_entry_t; + typedef l5_window_table_entry_l_xi_t l5_window_table_entry_xi_t; +#elif defined(BIG_ENDIAN) + typedef l5_window_table_entry_b_t l5_window_table_entry_t; + typedef l5_window_table_entry_b_xi_t l5_window_table_entry_xi_t; +#endif + + +/* + * l5_cq_table_entry_b definition + */ +typedef struct l5_cq_table_entry_b +{ + u32_t cqte_pgtbl_phaddr_hi; + u8_t cqte_pgtbl_phaddr_lo[3]; + u8_t cqte_flags; + + u16_t cqte_pidx; + u16_t cqte_cqes_per_page; + u16_t cqte_max_cqes; + u16_t cqte_nx_qe_self_seq; + u16_t cqte_nx_pg_qidx; + u16_t cqte_pgtbl_pgidx; + u16_t cqte_pgtbl_npages; + u16_t cqte_cqe_pidx; + u32_t cqte_cached_pte_phaddr_hi; + u32_t cqte_cached_pte_phaddr_lo; +} l5_cq_table_entry_b_t; + + +/* + * l5_cq_table_entry_b definition + */ +typedef struct l5_cq_table_entry_b_xi +{ + u32_t cqte_pgtbl_phaddr_hi; + u8_t cqte_pgtbl_phaddr_lo[3]; + u8_t cqte_flags; + #define CQTE_FLAGS_PAGE_SIZE (0xf<<0) + #define CQTE_FLAGS_PAGE_SIZE_256 (0<<0) + #define CQTE_FLAGS_PAGE_SIZE_512 (1<<0) + #define CQTE_FLAGS_PAGE_SIZE_1K (2<<0) + #define CQTE_FLAGS_PAGE_SIZE_2K (3<<0) + #define CQTE_FLAGS_PAGE_SIZE_4K (4<<0) + #define CQTE_FLAGS_PAGE_SIZE_8K (5<<0) + #define CQTE_FLAGS_PAGE_SIZE_16K (6<<0) + #define CQTE_FLAGS_PAGE_SIZE_32K (7<<0) + #define CQTE_FLAGS_PAGE_SIZE_64K (8<<0) + #define CQTE_FLAGS_PAGE_SIZE_128K (9<<0) + #define CQTE_FLAGS_PAGE_SIZE_256K (10<<0) + #define CQTE_FLAGS_PAGE_SIZE_512K (11<<0) + #define CQTE_FLAGS_PAGE_SIZE_1M (12<<0) + #define CQTE_FLAGS_PAGE_SIZE_2M (13<<0) + #define CQTE_FLAGS_FLAGS (0xf<<4) + #define CQTE_FLAGS_FLAGS_UNDEFINED (0<<4) + #define CQTE_FLAGS_FLAGS_VALID (1<<4) + #define CQTE_FLAGS_FLAGS_ARMED (2<<4) + #define CQTE_FLAGS_FLAGS_ARMED_SEND_SE (4<<4) + #define CQTE_FLAGS_FLAGS_CQE_NOT_ARMED (8<<4) + + u16_t cqte_pidx; + u16_t cqte_cqes_per_page; + u16_t cqte_max_cqes; + u16_t cqte_nx_qe_self_seq; + u16_t cqte_nx_pg_qidx; + u16_t cqte_pgtbl_pgidx; + u16_t cqte_pgtbl_npages; + u16_t cqte_cqe_pidx; + u32_t cqte_cached_pte_phaddr_hi; + u32_t cqte_cached_pte_phaddr_lo; +} l5_cq_table_entry_b_xi_t; + + +/* + * l5_cq_table_entry_l definition + */ +typedef struct l5_cq_table_entry_l +{ + u32_t cqte_pgtbl_phaddr_hi; + u8_t cqte_flags; + + u8_t cqte_pgtbl_phaddr_lo[3]; + u16_t cqte_cqes_per_page; + u16_t cqte_pidx; + u16_t cqte_nx_qe_self_seq; + u16_t cqte_max_cqes; + u16_t cqte_pgtbl_pgidx; + u16_t cqte_nx_pg_qidx; + u16_t cqte_cqe_pidx; + u16_t cqte_pgtbl_npages; + u32_t cqte_cached_pte_phaddr_hi; + u32_t cqte_cached_pte_phaddr_lo; +} l5_cq_table_entry_l_t; + + + +/* + * l5_cq_table_entry_l definition + */ +typedef struct l5_cq_table_entry_l_xi +{ + u32_t cqte_pgtbl_phaddr_hi; + u8_t cqte_flags; + #define CQTE_FLAGS_PAGE_SIZE (0xf<<0) + #define CQTE_FLAGS_PAGE_SIZE_256 (0<<0) + #define CQTE_FLAGS_PAGE_SIZE_512 (1<<0) + #define CQTE_FLAGS_PAGE_SIZE_1K (2<<0) + #define CQTE_FLAGS_PAGE_SIZE_2K (3<<0) + #define CQTE_FLAGS_PAGE_SIZE_4K (4<<0) + #define CQTE_FLAGS_PAGE_SIZE_8K (5<<0) + #define CQTE_FLAGS_PAGE_SIZE_16K (6<<0) + #define CQTE_FLAGS_PAGE_SIZE_32K (7<<0) + #define CQTE_FLAGS_PAGE_SIZE_64K (8<<0) + #define CQTE_FLAGS_PAGE_SIZE_128K (9<<0) + #define CQTE_FLAGS_PAGE_SIZE_256K (10<<0) + #define CQTE_FLAGS_PAGE_SIZE_512K (11<<0) + #define CQTE_FLAGS_PAGE_SIZE_1M (12<<0) + #define CQTE_FLAGS_PAGE_SIZE_2M (13<<0) + #define CQTE_FLAGS_FLAGS (0xf<<4) + #define CQTE_FLAGS_FLAGS_UNDEFINED (0<<4) + #define CQTE_FLAGS_FLAGS_VALID (1<<4) + #define CQTE_FLAGS_FLAGS_ARMED (2<<4) + #define CQTE_FLAGS_FLAGS_ARMED_SEND_SE (4<<4) + #define CQTE_FLAGS_FLAGS_CQE_NOT_ARMED (8<<4) + + u8_t cqte_pgtbl_phaddr_lo[3]; + u16_t cqte_cqes_per_page; + u16_t cqte_pidx; + u16_t cqte_nx_qe_self_seq; + u16_t cqte_max_cqes; + u16_t cqte_pgtbl_pgidx; + u16_t cqte_nx_pg_qidx; + u16_t cqte_cqe_pidx; + u16_t cqte_pgtbl_npages; + u32_t cqte_cached_pte_phaddr_hi; + u32_t cqte_cached_pte_phaddr_lo; +} l5_cq_table_entry_l_xi_t; + + +/* + * l5_cq_table_entry select + */ +#if defined(LITTLE_ENDIAN) + typedef l5_cq_table_entry_l_t l5_cq_table_entry_t; + typedef l5_cq_table_entry_l_xi_t l5_cq_table_entry_xi_t; +#elif defined(BIG_ENDIAN) + typedef l5_cq_table_entry_b_t l5_cq_table_entry_t; + typedef l5_cq_table_entry_b_xi_t l5_cq_table_entry_xi_t; +#endif + + +/* + * l5_cmd_cell_b definition + */ +typedef struct l5_cmd_cell_b +{ + u16_t l5ccell_cmd_type; + + u16_t l5ccell_wq_idx; + u8_t unused_0; + u8_t l5ccell_cmd_val; + u16_t l5ccell_distance_to_first_marker; + u32_t unused_1; + u32_t l5ccell_ddp_hdr_word1; + u32_t l5ccell_ddp_hdr_word2; + u32_t l5ccell_ddp_hdr_word3; + u32_t l5ccell_tcp_sn_first_byte; + u32_t l5ccell_tcp_sn_last_byte; +} l5_cmd_cell_b_t; + + + +/* + * l5_cmd_cell_l definition + */ +typedef struct l5_cmd_cell_l +{ + u16_t l5ccell_wq_idx; + u16_t l5ccell_cmd_type; + + u16_t l5ccell_distance_to_first_marker; + u8_t l5ccell_cmd_val; + u8_t unused_0; + u32_t unused_1; + u32_t l5ccell_ddp_hdr_word1; + u32_t l5ccell_ddp_hdr_word2; + u32_t l5ccell_ddp_hdr_word3; + u32_t l5ccell_tcp_sn_first_byte; + u32_t l5ccell_tcp_sn_last_byte; +} l5_cmd_cell_l_t; + + + +/* + * l5_cmd_cell select + */ +#if defined(LITTLE_ENDIAN) + typedef l5_cmd_cell_l_t l5_cmd_cell_t; +#elif defined(BIG_ENDIAN) + typedef l5_cmd_cell_b_t l5_cmd_cell_t; +#endif + + +/* + * l5_abuf_cell_b definition + */ +typedef struct l5_abuf_cell_b +{ + u32_t l5acell_pgtbl_phaddr_hi; + u8_t l5acell_pgtbl_phaddr_lo[3]; + u8_t l5acell_flags; + + u16_t l5acell_wq_idx; + u16_t l5acell_first_page_offset; + u32_t l5acell_buffer_offset; + u16_t l5acell_rbdc_key; + u16_t l5acell_receive_length; + u32_t l5acell_buffer_length; + u32_t l5acell_tcp_sn_L_bit_segment; +} l5_abuf_cell_b_t; + + + +/* + * l5_abuf_cell_b definition + */ +typedef struct l5_abuf_cell_b_xi +{ + u32_t l5acell_pgtbl_phaddr_hi; + u8_t l5acell_pgtbl_phaddr_lo[3]; + u8_t l5acell_flags; + #define L5ACELL_FLAGS_REGION_PAGE_SIZE (0xf<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_256 (0<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_512 (1<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_1K (2<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_2K (3<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_4K (4<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_8K (5<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_16K (6<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_32K (7<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_64K (8<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_128K (9<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_256K (10<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_512K (11<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_1M (12<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_2M (13<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_4M (14<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_8M (15<<0) + #define L5ACELL_FLAGS_ABUF_FLAGS (0xf<<4) + #define L5ACELL_FLAGS_ABUF_FLAGS_ABUF_UNDEFINED (0<<4) + #define L5ACELL_FLAGS_ABUF_FLAGS_L_BIT_RCVD (1<<4) + #define L5ACELL_FLAGS_ABUF_FLAGS_GEN_EVT (2<<4) + #define L5ACELL_FLAGS_ABUF_FLAGS_INV_STAG (4<<4) + #define L5ACELL_FLAGS_ABUF_FLAGS_COMP_ERROR (8<<4) + + u16_t l5acell_wq_idx; + u16_t l5acell_first_page_offset; + u32_t l5acell_buffer_offset; + u16_t l5acell_rbdc_key; + u16_t l5acell_receive_length; + u32_t l5acell_buffer_length; + u32_t l5acell_tcp_sn_L_bit_segment; +} l5_abuf_cell_b_xi_t; + + +/* + * l5_abuf_cell_l definition + */ +typedef struct l5_abuf_cell_l +{ + u32_t l5acell_pgtbl_phaddr_hi; + u8_t l5acell_flags; + + u8_t l5acell_pgtbl_phaddr_lo[3]; + u16_t l5acell_first_page_offset; + u16_t l5acell_wq_idx; + u32_t l5acell_buffer_offset; + u16_t l5acell_receive_length; + u16_t l5acell_rbdc_key; + u32_t l5acell_buffer_length; + u32_t l5acell_tcp_sn_L_bit_segment; +} l5_abuf_cell_l_t; + + + +/* + * l5_abuf_cell_l definition + */ +typedef struct l5_abuf_cell_l_xi +{ + u32_t l5acell_pgtbl_phaddr_hi; + u8_t l5acell_flags; + #define L5ACELL_FLAGS_REGION_PAGE_SIZE (0xf<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_256 (0<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_512 (1<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_1K (2<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_2K (3<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_4K (4<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_8K (5<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_16K (6<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_32K (7<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_64K (8<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_128K (9<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_256K (10<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_512K (11<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_1M (12<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_2M (13<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_4M (14<<0) + #define L5ACELL_FLAGS_REGION_PAGE_SIZE_8M (15<<0) + #define L5ACELL_FLAGS_ABUF_FLAGS (0xf<<4) + #define L5ACELL_FLAGS_ABUF_FLAGS_ABUF_UNDEFINED (0<<4) + #define L5ACELL_FLAGS_ABUF_FLAGS_L_BIT_RCVD (1<<4) + #define L5ACELL_FLAGS_ABUF_FLAGS_GEN_EVT (2<<4) + #define L5ACELL_FLAGS_ABUF_FLAGS_INV_STAG (4<<4) + #define L5ACELL_FLAGS_ABUF_FLAGS_COMP_ERROR (8<<4) + + u8_t l5acell_pgtbl_phaddr_lo[3]; + u16_t l5acell_first_page_offset; + u16_t l5acell_wq_idx; + u32_t l5acell_buffer_offset; + u16_t l5acell_receive_length; + u16_t l5acell_rbdc_key; + u32_t l5acell_buffer_length; + u32_t l5acell_tcp_sn_L_bit_segment; +} l5_abuf_cell_l_xi_t; + + +/* + * l5_abuf_cell select + */ +#if defined(LITTLE_ENDIAN) + typedef l5_abuf_cell_l_t l5_abuf_cell_t; + typedef l5_abuf_cell_l_xi_t l5_abuf_cell_xi_t; +#elif defined(BIG_ENDIAN) + typedef l5_abuf_cell_b_t l5_abuf_cell_t; + typedef l5_abuf_cell_b_xi_t l5_abuf_cell_xi_t; +#endif + + +/* + * l5_irrq_entry_b definition + */ +typedef struct l5_irrq_entry_b +{ + u32_t irrqe_sink_stag; + u32_t irrqe_sink_to_hi; + u32_t irrqe_sink_to_lo; + u32_t irrqe_msg_length; + u32_t irrqe_source_stag; + u32_t irrqe_source_to_hi; + u32_t irrqe_source_to_lo; +} l5_irrq_entry_b_t; + + + +/* + * l5_irrq_entry_b definition + */ +typedef struct l5_irrq_entry_b_xi +{ + u32_t irrqe_sink_stag; + u32_t irrqe_sink_to_hi; + u32_t irrqe_sink_to_lo; + u32_t irrqe_msg_length; + u32_t irrqe_source_stag; + u32_t irrqe_source_to_hi; + u32_t irrqe_source_to_lo; +} l5_irrq_entry_b_xi_t; + + +/* + * l5_irrq_entry_l definition + */ +typedef struct l5_irrq_entry_l +{ + u32_t irrqe_sink_stag; + u32_t irrqe_sink_to_hi; + u32_t irrqe_sink_to_lo; + u32_t irrqe_msg_length; + u32_t irrqe_source_stag; + u32_t irrqe_source_to_hi; + u32_t irrqe_source_to_lo; +} l5_irrq_entry_l_t; + + + +/* + * l5_irrq_entry_l definition + */ +typedef struct l5_irrq_entry_l_xi +{ + u32_t irrqe_sink_stag; + u32_t irrqe_sink_to_hi; + u32_t irrqe_sink_to_lo; + u32_t irrqe_msg_length; + u32_t irrqe_source_stag; + u32_t irrqe_source_to_hi; + u32_t irrqe_source_to_lo; +} l5_irrq_entry_l_xi_t; + + +/* + * l5_irrq_entry select + */ +#if defined(LITTLE_ENDIAN) + typedef l5_irrq_entry_l_t l5_irrq_entry_t; + typedef l5_irrq_entry_l_xi_t l5_irrq_entry_xi_t; +#elif defined(BIG_ENDIAN) + typedef l5_irrq_entry_b_t l5_irrq_entry_t; + typedef l5_irrq_entry_b_xi_t l5_irrq_entry_xi_t; +#endif + + +/* + * l5_orrq_entry_b definition + */ +typedef struct l5_orrq_entry_b +{ + u32_t orrqe_tcp_sn_read_rsp_L_bit_segment; + u32_t orrqe_source_to_hi; + u32_t orrqe_source_to_low; +} l5_orrq_entry_b_t; + + + +/* + * l5_orrq_entry_b definition + */ +typedef struct l5_orrq_entry_b_xi +{ + u32_t orrqe_tcp_sn_read_rsp_L_bit_segment; + u32_t orrqe_source_to_hi; + u32_t orrqe_source_to_low; +} l5_orrq_entry_b_xi_t; + + +/* + * l5_orrq_entry_l definition + */ +typedef struct l5_orrq_entry_l +{ + u32_t orrqe_tcp_sn_read_rsp_L_bit_segment; + u32_t orrqe_source_to_hi; + u32_t orrqe_source_to_low; +} l5_orrq_entry_l_t; + + + +/* + * l5_orrq_entry_l definition + */ +typedef struct l5_orrq_entry_l_xi +{ + u32_t orrqe_tcp_sn_read_rsp_L_bit_segment; + u32_t orrqe_source_to_hi; + u32_t orrqe_source_to_low; +} l5_orrq_entry_l_xi_t; + + +/* + * l5_orrq_entry select + */ +#if defined(LITTLE_ENDIAN) + typedef l5_orrq_entry_l_t l5_orrq_entry_t; + typedef l5_orrq_entry_l_xi_t l5_orrq_entry_xi_t; +#elif defined(BIG_ENDIAN) + typedef l5_orrq_entry_b_t l5_orrq_entry_t; + typedef l5_orrq_entry_b_xi_t l5_orrq_entry_xi_t; +#endif + + +/* + * l5_context_b definition + */ +typedef struct l5_context_b +{ + u8_t l5ctx_type; + + u8_t l5ctx_size; + u16_t l5ctx_cq_cidx; + u8_t l5ctx_gen_bd_max; + u8_t l5ctx_oubits; + + u16_t l5ctx_sq_pidx; + u16_t l5ctx_tcp_pgid; + u16_t l5ctx_rq_pidx; + u32_t l5ctx_tcp_timer1; + + u16_t l5ctx_tcp_timer2; + + u16_t l5ctx_tcp_timer3; + + u16_t l5ctx_tcp_timer4; + + u16_t l5ctx_tcp_timer5; + + u32_t l5ctx_tcp_snd_wl1; + u32_t l5ctx_tcp_snd_wl2; + u8_t l5ctx_tcp_ttl; + u8_t l5ctx_tcp_tos; + u8_t l5ctx_tcp_dack; + u8_t l5ctx_tcp_modes; + + u32_t l5ctx_tcp_max_adv_win; + u32_t l5ctx_tcp_timer; + u32_t l5ctx_tcp_ip_src; + u32_t l5ctx_tcp_ip_dst; + u8_t l5ctx_tcp_iphdr_nbytes; + u8_t l5ctx_tcp_snd_seg_scale; + u8_t l5ctx_tcp_rcv_seg_scale; + u8_t l5ctx_tcp_tcp_hlen; + u16_t l5ctx_tcp_src_port; + u16_t l5ctx_tcp_dst_port; + u16_t l5ctx_tcp_mss; + u8_t l5ctx_tcp_flags; + + u8_t l5ctx_tcp_state; + + u32_t l5ctx_tcp_rcv_next; + u32_t l5ctx_last_ack_sent; + u32_t l5ctx_tcp_rcv_win_seq; + u32_t l5ctx_tcp_snd_una; + u32_t l5ctx_tcp_snd_next; + u32_t l5ctx_tcp_snd_max; + u32_t l5ctx_tcp_snd_win; + u32_t l5ctx_tcp_snd_cwin; + u32_t l5ctx_tcp_tstamp; + u32_t l5ctx_tcp_ssthresh; + u16_t l5ctx_tcp_sm_rtt; + u16_t l5ctx_tcp_sm_delta; + u32_t l5ctx_tcp_max_snd_win; + u32_t l5ctx_tcp_tsch_snd_next; + u32_t l5ctx_tcp_slot_size; + + u8_t l5ctx_tcp_cp_cmd; + u8_t l5ctx_tcp_tsch_cmd; + u8_t l5ctx_tcp_cons_retx_num; + u8_t l5ctx_tcp_tsch_xnum; + + u8_t l5ctx_tcp_num_dupack; + u8_t l5ctx_tcp_tx_protocol_flags; + + u8_t l5ctx_tcp_prod_retx_num; + u8_t l5ctx_tcp_tsch_cons_retx_num; + u8_t l5ctx_tcp_comp_cons_retx_num; + u8_t l5ctx_tcp_num_retx; + u8_t l5ctx_tcp_upload_reason; + + u8_t l5ctx_tcp_txp_cmd; + u32_t unused_0; + tcp_context_cmd_cell_b_te_t l5ctx_cmd[3]; + u16_t l5ctx_snd_q_max_wqes; + u16_t l5ctx_snd_q_fw_qidx; + u16_t l5ctx_snd_q_nx_pg_qidx; + u16_t l5ctx_snd_q_pgtbl_pgidx; + u16_t l5ctx_snd_q_wqes_per_page; + u16_t l5ctx_snd_q_num_pages; + u8_t l5ctx_snd_q_pidx; + u8_t l5ctx_snd_q_cidx; + u8_t l5ctx_snd_q_max_cached_wqes; + u8_t l5ctx_snd_q_flags; + + u32_t l5ctx_snd_q_pgtbl_phaddr_hi; + u8_t l5ctx_snd_q_pgtbl_phaddr_lo[3]; + u8_t l5ctx_snd_q_read_rsp_wait; + u32_t l5ctx_snd_q_cached_pte_phaddr_hi; + u32_t l5ctx_snd_q_cached_pte_phaddr_lo; + l5_cmd_cell_b_t l5ctx_snd_q_cmd[3]; + u16_t l5ctx_rcv_q_max_wqes; + u16_t l5ctx_rcv_q_fw_qidx; + u16_t l5ctx_rcv_q_nx_pg_qidx; + u16_t l5ctx_rcv_q_pgtbl_pgidx; + u16_t l5ctx_rcv_q_wqes_per_page; + u16_t l5ctx_rcv_q_num_pages; + u8_t l5ctx_rcv_q_pidx; + u8_t l5ctx_rcv_q_rxp_cidx; + u8_t l5ctx_rcv_q_com_cidx; + u8_t l5ctx_rcv_q_flags; + + u32_t l5ctx_rcv_q_pgtbl_phaddr_hi; + u8_t l5ctx_rcv_q_pgtbl_phaddr_lo[3]; + u8_t l5ctx_rcv_q_qp_ou_state; + #define L5CTX_RCV_Q_QP_OU_STATE_UPLOADED (1<<0) + #define L5CTX_RCV_Q_QP_OU_STATE_OFFLOADED (1<<1) + #define L5CTX_RCV_Q_QP_OU_STATE_UPLOAD_REQ (1<<2) + #define L5CTX_RCV_Q_QP_OU_STATE_OFFLOAD_REQ (1<<3) + + u32_t l5ctx_rcv_q_cached_pte_phaddr_hi; + u32_t l5ctx_rcv_q_cached_pte_phaddr_lo; + l5_abuf_cell_b_t l5ctx_rcv_q_abuf[2]; + u32_t l5ctx_cq_cid; + u32_t l5ctx_curr_send_msn; + u32_t l5ctx_curr_rdma_read_msn; + u16_t l5ctx_pd; + u8_t l5ctx_rcv_path_op_state; + + u8_t l5ctx_ird; + u32_t l5ctx_tx_initial_tcp_sn; + u16_t l5ctx_tsch_mult_value; + u8_t l5ctx_null_cmd_cell_pidx; + u8_t l5ctx_null_cmd_cell_cidx; + l5_orrq_entry_b_t l5ctx_orrq[1]; + l5_irrq_entry_b_t l5ctx_irrq[1]; + u8_t l5ctx_miq_index; + u8_t l5ctx_rx_comp_flags; + + u8_t l5ctx_qp_flags; + + u8_t l5ctx_upload_flag; + + u8_t l5ctx_upload_rxp; + + u8_t l5ctx_ooo_read_resp_segs_w_L_bit; + u8_t l5ctx_ooo_send_msg_segs_w_L_bit; + u8_t l5ctx_ooo_read_request_msgs; + u32_t l5ctx_high_tcp_ack_sn_rcvd; + u32_t l5ctx_rx_initial_tcp_sn; + u32_t l5ctx_send_msg_high_msn_completed; + u32_t l5ctx_read_req_high_msn_queued; + u32_t l5ctx_rsvd_l4_hole_mgmt[3]; + u16_t l5ctx_cam_index; + u16_t l5ctx_offload_flag; +} l5_context_b_t; + + + +/* + * l5_context_b definition + */ +typedef struct l5_context_b_xi +{ + u32_t l5ctx_tcp_tsch_snd_next; + u32_t l5ctx_tcp_snd_max; + u8_t l5ctx_tcp_cp_cmd; + u8_t l5ctx_tcp_tsch_cmd; + u8_t l5ctx_tcp_cons_retx_num; + u8_t l5ctx_tcp_tsch_xnum; + #define L5CTX_TCP_TSCH_XNUM_VAL (0x7f<<0) + #define L5CTX_TCP_TSCH_XNUM_L4 (1<<7) + + u16_t l5ctx_tcp_pgid; + #define L5CTX_TCP_PGID_VAL (0x3fff<<0) + + u8_t l5ctx_tcp_prod_retx_num; + u8_t l5ctx_tcp_tsch_cons_retx_num; + u8_t l5ctx_tcp_l2_slot_size; + u8_t unused_0; + u16_t unused_1; + u32_t unused_2; + u8_t l5ctx_tcp_ttl; + u8_t l5ctx_tcp_tos; + u8_t l5ctx_tcp_dack; + u8_t l5ctx_tcp_modes; + #define L5CTX_TCP_MODES_RST_INDICATED (1<<0) + #define L5CTX_TCP_MODES_DISC_BD (1<<1) + #define L5CTX_TCP_MODES_UPLOAD_INITED (1<<2) + #define L5CTX_TCP_MODES_RMT_DISC (1<<3) + #define L5CTX_TCP_MODES_PG_INVALIDATED (1<<4) + #define L5CTX_TCP_MODES_ABORT_PENDING (1<<5) + #define L5CTX_TCP_MODES_DISC_PENDING (1<<6) + #define L5CTX_TCP_MODES_SS (1<<7) + + u32_t l5ctx_tcp_max_adv_win; + u32_t l5ctx_timer; + u32_t l5ctx_tcp_ip_src; + u32_t l5ctx_tcp_ip_dst; + u8_t l5ctx_tcp_iphdr_nbytes; + u8_t l5ctx_tcp_snd_seg_scale; + u8_t l5ctx_tcp_rcv_seg_scale; + u8_t l5ctx_tcp_tcp_hlen; + u16_t l5ctx_tcp_src_port; + u16_t l5ctx_tcp_dst_port; + u32_t l5ctx_tx_initial_tcp_sn; + u8_t l5ctx_upload_flag; + #define L5CTX_UPLOAD_FLAG_TXP (1<<0) + #define L5CTX_UPLOAD_FLAG_TXP_COM (1<<1) + u8_t unused_3; + u16_t unused_4; + u32_t unused_5[17]; + + u8_t l5ctx_type; + #define L5CTX_TYPE_TYPE (0xf<<4) + #define L5CTX_TYPE_TYPE_EMPTY (0<<4) + #define L5CTX_TYPE_TYPE_L2 (1<<4) + #define L5CTX_TYPE_TYPE_TCP (2<<4) + #define L5CTX_TYPE_TYPE_L5 (3<<4) + #define L5CTX_TYPE_TYPE_L2_BD_CHN (4<<4) + + u8_t l5ctx_size; + #define L5CTX_SIZE_ARM_CQ (1<<0) + + u16_t l5ctx_cq_cidx; + u8_t l5ctx_gen_bd_max; + u8_t l5ctx_oubits; + #define L5CTX_OUBITS_ACTIVATE (1<<0) + #define L5CTX_OUBITS_CP_UPLOAD (1<<1) + #define L5CTX_OUBITS_RXP_UPLOAD (1<<2) + #define L5CTX_OUBITS_TXP_UPLOAD (1<<3) + #define L5CTX_OUBITS_COM_RX_UPLOAD (1<<4) + #define L5CTX_OUBITS_COM_TX_UPLOAD (1<<5) + #define L5CTX_OUBITS_CP_UPLOAD_COMP (1<<6) + #define L5CTX_OUBITS_HOST_ACK (1<<7) + + u16_t l5ctx_sq_pidx; + u16_t unused_6; + u16_t l5ctx_rq_pidx; + u32_t l5ctx_tcp_timer1; + #define L5CTX_TCP_TIMER1_DISABLE (1UL<<0) + #define L5CTX_TCP_TIMER1_VALUE (0x7fffffffL<<1) + + u16_t l5ctx_tcp_timer2; + #define L5CTX_TCP_TIMER2_DISABLE (1<<0) + #define L5CTX_TCP_TIMER2_VALUE (0x7fff<<1) + + u16_t l5ctx_tcp_timer3; + #define L5CTX_TCP_TIMER3_DISABLE (1<<0) + #define L5CTX_TCP_TIMER3_VALUE (0x7fff<<1) + + u16_t l5ctx_tcp_timer4; + #define L5CTX_TCP_TIMER4_DISABLE (1<<0) + #define L5CTX_TCP_TIMER4_VALUE (0x7fff<<1) + + u16_t l5ctx_tcp_timer5; + #define L5CTX_TCP_TIMER5_DISABLE (1<<0) + #define L5CTX_TCP_TIMER5_VALUE (0x7fff<<1) + + u32_t l5ctx_tcp_slot_size; + #define L5CTX_TCP_SLOT_SIZE_SLOT_SIZE (0xffffffL<<0) + #define L5CTX_TCP_SLOT_SIZE_CMD_MAX (0x7fL<<24) + #define L5CTX_TCP_SLOT_SIZE_STOP (1UL<<31) + + u32_t l5ctx_tcp_snd_cwin; + u32_t l5ctx_tcp_snd_win; + u8_t l5ctx_tcp_num_dupack; + u8_t l5ctx_tcp_tx_protocol_flags; + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_TIMER_DELAY_ACK (1<<0) + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_UPLOAD (1<<1) + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_FORCE_ACK (1<<2) + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_LAST_ACK (1<<3) + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_LAST_RST (1<<4) + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_FORCE_RST (1<<5) + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_FORCE_ACK_MINUS (1<<6) + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_TSCH_WA (1<<7) + + u8_t l5ctx_upload_rxp; + #define L5CTX_UPLOAD_RXP_COM (1<<0) + + u8_t l5ctx_qp_ou_state; + #define L5CTX_QP_OU_STATE_UPLOADED (1<<0) + #define L5CTX_QP_OU_STATE_OFFLOADED (1<<1) + #define L5CTX_QP_OU_STATE_UPLOAD_REQ (1<<2) + #define L5CTX_QP_OU_STATE_OFFLOAD_REQ (1<<3) + u32_t unused_7; + + u16_t l5ctx_tcp_mss; + u8_t l5ctx_tcp_flags; + #define L5CTX_TCP_FLAGS_NO_DELAY_ACK (1<<0) + #define L5CTX_TCP_FLAGS_KEEP_ALIVE (1<<1) + #define L5CTX_TCP_FLAGS_NAGLE (1<<2) + #define L5CTX_TCP_FLAGS_TIME_STAMP (1<<3) + #define L5CTX_TCP_FLAGS_SACK (1<<4) + #define L5CTX_TCP_FLAGS_SEG_SCALING (1<<5) + + u8_t l5ctx_tcp_state; + #define L5CTX_TCP_STATE_VALUE (0xff<<0) + #define L5CTX_TCP_STATE_VALUE_UNDEFINED (0<<0) + #define L5CTX_TCP_STATE_VALUE_LISTEN (2<<0) + #define L5CTX_TCP_STATE_VALUE_SYN_SENT (4<<0) + #define L5CTX_TCP_STATE_VALUE_SYN_RECV (6<<0) + #define L5CTX_TCP_STATE_VALUE_CLOSE_WAIT (8<<0) + #define L5CTX_TCP_STATE_VALUE_ESTABLISHED (10<<0) + #define L5CTX_TCP_STATE_VALUE_FIN_WAIT1 (12<<0) + #define L5CTX_TCP_STATE_VALUE_FIN_WAIT2 (14<<0) + #define L5CTX_TCP_STATE_VALUE_TIME_WAIT (16<<0) + #define L5CTX_TCP_STATE_VALUE_CLOSE (18<<0) + #define L5CTX_TCP_STATE_VALUE_LAST_ACK (20<<0) + #define L5CTX_TCP_STATE_VALUE_CLOSING (22<<0) + + u32_t l5ctx_tcp_rcv_next; + u32_t l5ctx_last_ack_sent; + u32_t l5ctx_tcp_rcv_win_seq; + u32_t l5ctx_tcp_snd_una; + u32_t l5ctx_tcp_snd_next; + u32_t l5ctx_tcp_tstamp; + u32_t l5ctx_tcp_ssthresh; + u16_t l5ctx_tcp_sm_rtt; + u16_t l5ctx_tcp_sm_delta; + u32_t l5ctx_tcp_max_snd_win; + u8_t l5ctx_tcp_comp_cons_retx_num; + u8_t l5ctx_tcp_num_retx; + u8_t unused_8; + u8_t l5ctx_tcp_txp_cmd; + u32_t unused_9; + u8_t l5ctx_snd_q_max_cached_wqes; + u8_t l5ctx_null_cmd_cell_pidx; + u8_t l5ctx_null_cmd_cell_cidx; + u8_t l5ctx_qp_flags; + #define L5CTX_QP_FLAGS_QP_VALID (1<<0) + #define L5CTX_QP_FLAGS_SUPPORTS_LAZY_WQES (1<<1) + #define L5CTX_QP_FLAGS_INBOUND_RDMA_READ_DISABLED (1<<2) + #define L5CTX_QP_FLAGS_INBOUND_RDMA_WRITE_DISABLED (1<<3) + #define L5CTX_QP_FLAGS_WINDOW_BINDS_ENABLED (1<<4) + #define L5CTX_QP_FLAGS_LOCAL_INVALIDATE_IN_PROGRESS (1<<5) + + l5_orrq_entry_b_xi_t l5ctx_orrq[1]; + u32_t l5ctx_cq_cid; + u32_t unused_10[4]; + u32_t l5ctx_rdma_crc; + u32_t l5ctx_tcp_snd_wl1; + u32_t l5ctx_tcp_snd_wl2; + u16_t unused_11; + u8_t l5ctx_tcp_upload_reason; + #define L5CTX_TCP_UPLOAD_REASON_KEEP_ALIVE (1<<0) + #define L5CTX_TCP_UPLOAD_REASON_FIN (1<<1) + #define L5CTX_TCP_UPLOAD_REASON_URG (1<<2) + #define L5CTX_TCP_UPLOAD_REASON_FRAGMENT (1<<3) + #define L5CTX_TCP_UPLOAD_REASON_IP_OPTION (1<<4) + #define L5CTX_TCP_UPLOAD_REASON_RST (1<<5) + #define L5CTX_TCP_UPLOAD_REASON_SYN (1<<6) + #define L5CTX_TCP_UPLOAD_REASON_TIMEOUT (1<<7) + u8_t unused_12; + + u32_t l5ctx_tcp_offload_seq; + u32_t l5ctx_pg_cwin; + u32_t l5ctx_high_tcp_ack_sn_rcvd; + u16_t l5ctx_pd; + u8_t l5ctx_snd_q_cidx; + u8_t l5ctx_snd_q_pidx; + u8_t l5ctx_read_rsp_wait; + u8_t l5ctx_rcv_q_flags; + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE (0xf<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_256 (0<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_512 (1<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_1K (2<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_2K (3<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_4K (4<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_8K (5<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_16K (6<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_32K (7<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_64K (8<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_128K (9<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_256K (10<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_512K (11<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_1M (12<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_2M (13<<0) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE (0xf<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_1 (0<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_2 (1<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_4 (2<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_8 (3<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_16 (4<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_32 (5<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_64 (6<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_128 (7<<4) + + u8_t l5ctx_rcv_q_pidx; + u8_t l5ctx_rcv_q_rxp_cidx; + u8_t l5ctx_rcv_q_com_cidx; + u8_t l5ctx_ird; + u8_t l5ctx_rx_comp_flags; + #define L5CTX_RX_COMP_FLAGS_TCP_HOLE_EXISTS (1<<0) + #define L5CTX_RX_COMP_FLAGS_MARKER_IN_ISLAND (1<<1) + #define L5CTX_RX_COMP_FLAGS_READ_REQ_OUTSTANDING (1<<2) + #define L5CTX_RX_COMP_FLAGS_TCP_ISLAND_CREATED (1<<3) + + u8_t l5ctx_ooo_read_resp_segs_w_L_bit; + u8_t l5ctx_ooo_send_msg_segs_w_L_bit; + u8_t l5ctx_ooo_read_request_msgs; + u8_t l5ctx_miq_index; + u8_t l5ctx_rcv_path_op_state; + #define L5CTX_RCV_PATH_OP_STATE_OPERATIONAL (1<<0) + #define L5CTX_RCV_PATH_OP_STATE_BYPASS (1<<1) + + u32_t l5ctx_send_msg_high_msn_completed; + u32_t l5ctx_read_req_high_msn_queued; + u32_t l5ctx_rx_initial_tcp_sn; + u32_t l5ctx_rsvd_l4_hole_mgmt[4]; + l5_irrq_entry_b_xi_t l5ctx_irrq[1]; + l5_abuf_cell_b_xi_t l5ctx_rcv_q_abuf[2]; + u32_t unused_13[9]; + u16_t l5ctx_snd_q_max_wqes; + u16_t l5ctx_snd_q_fw_qidx; + u16_t l5ctx_snd_q_pgtbl_pgidx; + u16_t l5ctx_snd_q_wqes_per_page; + u16_t l5ctx_snd_q_num_pages; + u16_t l5ctx_snd_q_nx_pg_qidx; + u32_t l5ctx_snd_q_pgtbl_phaddr_hi; + u8_t l5ctx_snd_q_pgtbl_phaddr_lo[3]; + u8_t l5ctx_snd_q_flags; + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE (0xf<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_256 (0<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_512 (1<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_1K (2<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_2K (3<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_4K (4<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_8K (5<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_16K (6<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_32K (7<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_64K (8<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_128K (9<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_256K (10<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_512K (11<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_1M (12<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_2M (13<<0) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE (0xf<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_1 (0<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_2 (1<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_4 (2<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_8 (3<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_16 (4<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_32 (5<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_64 (6<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_128 (7<<4) + + u32_t l5ctx_rcv_q_pgtbl_phaddr_hi; + u8_t l5ctx_rcv_q_pgtbl_phaddr_lo[3]; + u8_t l5ctx_ord; + u16_t l5ctx_rcv_q_nx_pg_qidx; + u16_t l5ctx_tsch_mult_value; + u16_t l5ctx_rcv_q_max_wqes; + u16_t l5ctx_rcv_q_fw_qidx; + u16_t l5ctx_rcv_q_pgtbl_pgidx; + u16_t l5ctx_rcv_q_wqes_per_page; + u16_t l5ctx_rcv_q_num_pages; + u8_t l5ctx_max_scatter_list_elements; + u8_t l5ctx_max_gather_list_elements; + u32_t l5ctx_curr_send_msn; + u32_t l5ctx_curr_rdma_read_msn; + u32_t l5ctx_snd_q_cached_pte_phaddr_hi; + u32_t l5ctx_snd_q_cached_pte_phaddr_lo; + u32_t l5ctx_rcv_q_cached_pte_phaddr_hi; + u32_t l5ctx_rcv_q_cached_pte_phaddr_lo; + u32_t unused_14[15]; + tcp_context_cmd_cell_b_xi_t l5ctx_cmd[3]; +} l5_context_b_xi_t; + + +/* + * l5_context_l definition + */ +typedef struct l5_context_l +{ + u16_t l5ctx_cq_cidx; + u8_t l5ctx_size; + u8_t l5ctx_type; + + u16_t l5ctx_sq_pidx; + u8_t l5ctx_oubits; + + u8_t l5ctx_gen_bd_max; + u16_t l5ctx_rq_pidx; + u16_t l5ctx_tcp_pgid; + u32_t l5ctx_tcp_timer1; + + u16_t l5ctx_tcp_timer3; + + u16_t l5ctx_tcp_timer2; + + u16_t l5ctx_tcp_timer5; + + u16_t l5ctx_tcp_timer4; + + u32_t l5ctx_tcp_snd_wl1; + u32_t l5ctx_tcp_snd_wl2; + u8_t l5ctx_tcp_modes; + + u8_t l5ctx_tcp_dack; + u8_t l5ctx_tcp_tos; + u8_t l5ctx_tcp_ttl; + u32_t l5ctx_tcp_max_adv_win; + u32_t l5ctx_tcp_timer; + u32_t l5ctx_tcp_ip_src; + u32_t l5ctx_tcp_ip_dst; + u8_t l5ctx_tcp_tcp_hlen; + u8_t l5ctx_tcp_rcv_seg_scale; + u8_t l5ctx_tcp_snd_seg_scale; + u8_t l5ctx_tcp_iphdr_nbytes; + u16_t l5ctx_tcp_dst_port; + u16_t l5ctx_tcp_src_port; + u8_t l5ctx_tcp_state; + + u8_t l5ctx_tcp_flags; + + u16_t l5ctx_tcp_mss; + u32_t l5ctx_tcp_rcv_next; + u32_t l5ctx_last_ack_sent; + u32_t l5ctx_tcp_rcv_win_seq; + u32_t l5ctx_tcp_snd_una; + u32_t l5ctx_tcp_snd_next; + u32_t l5ctx_tcp_snd_max; + u32_t l5ctx_tcp_snd_win; + u32_t l5ctx_tcp_snd_cwin; + u32_t l5ctx_tcp_tstamp; + u32_t l5ctx_tcp_ssthresh; + u16_t l5ctx_tcp_sm_delta; + u16_t l5ctx_tcp_sm_rtt; + u32_t l5ctx_tcp_max_snd_win; + u32_t l5ctx_tcp_tsch_snd_next; + u32_t l5ctx_tcp_slot_size; + + u8_t l5ctx_tcp_tsch_xnum; + + u8_t l5ctx_tcp_cons_retx_num; + u8_t l5ctx_tcp_tsch_cmd; + u8_t l5ctx_tcp_cp_cmd; + u8_t l5ctx_tcp_tsch_cons_retx_num; + u8_t l5ctx_tcp_prod_retx_num; + u8_t l5ctx_tcp_tx_protocol_flags; + + u8_t l5ctx_tcp_num_dupack; + u8_t l5ctx_tcp_txp_cmd; + u8_t l5ctx_tcp_upload_reason; + + u8_t l5ctx_tcp_num_retx; + u8_t l5ctx_tcp_comp_cons_retx_num; + u32_t unused_0; + tcp_context_cmd_cell_l_te_t l5ctx_cmd[3]; + u16_t l5ctx_snd_q_fw_qidx; + u16_t l5ctx_snd_q_max_wqes; + u16_t l5ctx_snd_q_pgtbl_pgidx; + u16_t l5ctx_snd_q_nx_pg_qidx; + u16_t l5ctx_snd_q_num_pages; + u16_t l5ctx_snd_q_wqes_per_page; + u8_t l5ctx_snd_q_flags; + + u8_t l5ctx_snd_q_max_cached_wqes; + u8_t l5ctx_snd_q_cidx; + u8_t l5ctx_snd_q_pidx; + u32_t l5ctx_snd_q_pgtbl_phaddr_hi; + u8_t l5ctx_snd_q_read_rsp_wait; + u8_t l5ctx_snd_q_pgtbl_phaddr_lo[3]; + u32_t l5ctx_snd_q_cached_pte_phaddr_hi; + u32_t l5ctx_snd_q_cached_pte_phaddr_lo; + l5_cmd_cell_l_t l5ctx_snd_q_cmd[3]; + u16_t l5ctx_rcv_q_fw_qidx; + u16_t l5ctx_rcv_q_max_wqes; + u16_t l5ctx_rcv_q_pgtbl_pgidx; + u16_t l5ctx_rcv_q_nx_pg_qidx; + u16_t l5ctx_rcv_q_num_pages; + u16_t l5ctx_rcv_q_wqes_per_page; + u8_t l5ctx_rcv_q_flags; + + u8_t l5ctx_rcv_q_com_cidx; + u8_t l5ctx_rcv_q_rxp_cidx; + u8_t l5ctx_rcv_q_pidx; + u32_t l5ctx_rcv_q_pgtbl_phaddr_hi; + u8_t l5ctx_rcv_q_qp_ou_state; + #define L5CTX_RCV_Q_QP_OU_STATE_UPLOADED (1<<0) + #define L5CTX_RCV_Q_QP_OU_STATE_OFFLOADED (1<<1) + #define L5CTX_RCV_Q_QP_OU_STATE_UPLOAD_REQ (1<<2) + #define L5CTX_RCV_Q_QP_OU_STATE_OFFLOAD_REQ (1<<3) + + u8_t l5ctx_rcv_q_pgtbl_phaddr_lo[3]; + u32_t l5ctx_rcv_q_cached_pte_phaddr_hi; + u32_t l5ctx_rcv_q_cached_pte_phaddr_lo; + l5_abuf_cell_l_t l5ctx_rcv_q_abuf[2]; + u32_t l5ctx_cq_cid; + u32_t l5ctx_curr_send_msn; + u32_t l5ctx_curr_rdma_read_msn; + u8_t l5ctx_ird; + u8_t l5ctx_rcv_path_op_state; + + u16_t l5ctx_pd; + u32_t l5ctx_tx_initial_tcp_sn; + u8_t l5ctx_null_cmd_cell_cidx; + u8_t l5ctx_null_cmd_cell_pidx; + u16_t l5ctx_tsch_mult_value; + l5_orrq_entry_l_t l5ctx_orrq[1]; + l5_irrq_entry_l_t l5ctx_irrq[1]; + u8_t l5ctx_upload_flag; + + u8_t l5ctx_qp_flags; + + u8_t l5ctx_rx_comp_flags; + + u8_t l5ctx_miq_index; + u8_t l5ctx_ooo_read_request_msgs; + u8_t l5ctx_ooo_send_msg_segs_w_L_bit; + u8_t l5ctx_ooo_read_resp_segs_w_L_bit; + u8_t l5ctx_upload_rxp; + + u32_t l5ctx_high_tcp_ack_sn_rcvd; + u32_t l5ctx_rx_initial_tcp_sn; + u32_t l5ctx_send_msg_high_msn_completed; + u32_t l5ctx_read_req_high_msn_queued; + u32_t l5ctx_rsvd_l4_hole_mgmt[3]; + u16_t l5ctx_offload_flag; + u16_t l5ctx_cam_index; +} l5_context_l_t; + + + +/* + * l5_context_l definition + */ +typedef struct l5_context_l_xi +{ + u32_t l5ctx_tcp_tsch_snd_next; + u32_t l5ctx_tcp_snd_max; + u8_t l5ctx_tcp_tsch_xnum; + #define L5CTX_TCP_TSCH_XNUM_VAL (0x7f<<0) + #define L5CTX_TCP_TSCH_XNUM_L4 (1<<7) + + u8_t l5ctx_tcp_cons_retx_num; + u8_t l5ctx_tcp_tsch_cmd; + u8_t l5ctx_tcp_cp_cmd; + u8_t l5ctx_tcp_tsch_cons_retx_num; + u8_t l5ctx_tcp_prod_retx_num; + u16_t l5ctx_tcp_pgid; + #define L5CTX_TCP_PGID_VAL (0x3fff<<0) + u16_t unused_0; + u8_t unused_1; + + u8_t l5ctx_tcp_l2_slot_size; + u32_t unused_2; + u8_t l5ctx_tcp_modes; + #define L5CTX_TCP_MODES_RST_INDICATED (1<<0) + #define L5CTX_TCP_MODES_DISC_BD (1<<1) + #define L5CTX_TCP_MODES_UPLOAD_INITED (1<<2) + #define L5CTX_TCP_MODES_RMT_DISC (1<<3) + #define L5CTX_TCP_MODES_PG_INVALIDATED (1<<4) + #define L5CTX_TCP_MODES_ABORT_PENDING (1<<5) + #define L5CTX_TCP_MODES_DISC_PENDING (1<<6) + #define L5CTX_TCP_MODES_SS (1<<7) + + u8_t l5ctx_tcp_dack; + u8_t l5ctx_tcp_tos; + u8_t l5ctx_tcp_ttl; + u32_t l5ctx_tcp_max_adv_win; + u32_t l5ctx_timer; + u32_t l5ctx_tcp_ip_src; + u32_t l5ctx_tcp_ip_dst; + u8_t l5ctx_tcp_tcp_hlen; + u8_t l5ctx_tcp_rcv_seg_scale; + u8_t l5ctx_tcp_snd_seg_scale; + u8_t l5ctx_tcp_iphdr_nbytes; + u16_t l5ctx_tcp_dst_port; + u16_t l5ctx_tcp_src_port; + u32_t l5ctx_tx_initial_tcp_sn; + u16_t unused_3; + u8_t unused_4; + u8_t l5ctx_upload_flag; + #define L5CTX_UPLOAD_FLAG_TXP (1<<0) + #define L5CTX_UPLOAD_FLAG_TXP_COM (1<<1) + u32_t unused_5[17]; + + u16_t l5ctx_cq_cidx; + u8_t l5ctx_size; + #define L5CTX_SIZE_ARM_CQ (1<<0) + + u8_t l5ctx_type; + #define L5CTX_TYPE_TYPE (0xf<<4) + #define L5CTX_TYPE_TYPE_EMPTY (0<<4) + #define L5CTX_TYPE_TYPE_L2 (1<<4) + #define L5CTX_TYPE_TYPE_TCP (2<<4) + #define L5CTX_TYPE_TYPE_L5 (3<<4) + #define L5CTX_TYPE_TYPE_L2_BD_CHN (4<<4) + + u16_t l5ctx_sq_pidx; + u8_t l5ctx_oubits; + #define L5CTX_OUBITS_ACTIVATE (1<<0) + #define L5CTX_OUBITS_CP_UPLOAD (1<<1) + #define L5CTX_OUBITS_RXP_UPLOAD (1<<2) + #define L5CTX_OUBITS_TXP_UPLOAD (1<<3) + #define L5CTX_OUBITS_COM_RX_UPLOAD (1<<4) + #define L5CTX_OUBITS_COM_TX_UPLOAD (1<<5) + #define L5CTX_OUBITS_CP_UPLOAD_COMP (1<<6) + #define L5CTX_OUBITS_HOST_ACK (1<<7) + + u8_t l5ctx_gen_bd_max; + u16_t l5ctx_rq_pidx; + u16_t unused_6; + u32_t l5ctx_tcp_timer1; + #define L5CTX_TCP_TIMER1_DISABLE (1UL<<0) + #define L5CTX_TCP_TIMER1_VALUE (0x7fffffffL<<1) + + u16_t l5ctx_tcp_timer3; + #define L5CTX_TCP_TIMER3_DISABLE (1<<0) + #define L5CTX_TCP_TIMER3_VALUE (0x7fff<<1) + + u16_t l5ctx_tcp_timer2; + #define L5CTX_TCP_TIMER2_DISABLE (1<<0) + #define L5CTX_TCP_TIMER2_VALUE (0x7fff<<1) + + u16_t l5ctx_tcp_timer5; + #define L5CTX_TCP_TIMER5_DISABLE (1<<0) + #define L5CTX_TCP_TIMER5_VALUE (0x7fff<<1) + + u16_t l5ctx_tcp_timer4; + #define L5CTX_TCP_TIMER4_DISABLE (1<<0) + #define L5CTX_TCP_TIMER4_VALUE (0x7fff<<1) + + u32_t l5ctx_tcp_slot_size; + #define L5CTX_TCP_SLOT_SIZE_SLOT_SIZE (0xffffffL<<0) + #define L5CTX_TCP_SLOT_SIZE_CMD_MAX (0x7fL<<24) + #define L5CTX_TCP_SLOT_SIZE_STOP (1UL<<31) + + u32_t l5ctx_tcp_snd_cwin; + u32_t l5ctx_tcp_snd_win; + u8_t l5ctx_qp_ou_state; + #define L5CTX_QP_OU_STATE_UPLOADED (1<<0) + #define L5CTX_QP_OU_STATE_OFFLOADED (1<<1) + #define L5CTX_QP_OU_STATE_UPLOAD_REQ (1<<2) + #define L5CTX_QP_OU_STATE_OFFLOAD_REQ (1<<3) + + u8_t l5ctx_upload_rxp; + #define L5CTX_UPLOAD_RXP_COM (1<<0) + + u8_t l5ctx_tcp_tx_protocol_flags; + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_TIMER_DELAY_ACK (1<<0) + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_UPLOAD (1<<1) + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_FORCE_ACK (1<<2) + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_LAST_ACK (1<<3) + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_LAST_RST (1<<4) + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_FORCE_RST (1<<5) + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_FORCE_ACK_MINUS (1<<6) + #define L5CTX_TCP_TX_PROTOCOL_FLAGS_TSCH_WA (1<<7) + + u8_t l5ctx_tcp_num_dupack; + u32_t unused_7; + u8_t l5ctx_tcp_state; + #define L5CTX_TCP_STATE_VALUE (0xff<<0) + #define L5CTX_TCP_STATE_VALUE_UNDEFINED (0<<0) + #define L5CTX_TCP_STATE_VALUE_LISTEN (2<<0) + #define L5CTX_TCP_STATE_VALUE_SYN_SENT (4<<0) + #define L5CTX_TCP_STATE_VALUE_SYN_RECV (6<<0) + #define L5CTX_TCP_STATE_VALUE_CLOSE_WAIT (8<<0) + #define L5CTX_TCP_STATE_VALUE_ESTABLISHED (10<<0) + #define L5CTX_TCP_STATE_VALUE_FIN_WAIT1 (12<<0) + #define L5CTX_TCP_STATE_VALUE_FIN_WAIT2 (14<<0) + #define L5CTX_TCP_STATE_VALUE_TIME_WAIT (16<<0) + #define L5CTX_TCP_STATE_VALUE_CLOSE (18<<0) + #define L5CTX_TCP_STATE_VALUE_LAST_ACK (20<<0) + #define L5CTX_TCP_STATE_VALUE_CLOSING (22<<0) + + u8_t l5ctx_tcp_flags; + #define L5CTX_TCP_FLAGS_NO_DELAY_ACK (1<<0) + #define L5CTX_TCP_FLAGS_KEEP_ALIVE (1<<1) + #define L5CTX_TCP_FLAGS_NAGLE (1<<2) + #define L5CTX_TCP_FLAGS_TIME_STAMP (1<<3) + #define L5CTX_TCP_FLAGS_SACK (1<<4) + #define L5CTX_TCP_FLAGS_SEG_SCALING (1<<5) + + u16_t l5ctx_tcp_mss; + u32_t l5ctx_tcp_rcv_next; + u32_t l5ctx_last_ack_sent; + u32_t l5ctx_tcp_rcv_win_seq; + u32_t l5ctx_tcp_snd_una; + u32_t l5ctx_tcp_snd_next; + u32_t l5ctx_tcp_tstamp; + u32_t l5ctx_tcp_ssthresh; + u16_t l5ctx_tcp_sm_delta; + u16_t l5ctx_tcp_sm_rtt; + u32_t l5ctx_tcp_max_snd_win; + u8_t l5ctx_tcp_txp_cmd; + u8_t unused_8; + u8_t l5ctx_tcp_num_retx; + u8_t l5ctx_tcp_comp_cons_retx_num; + u32_t unused_9; + u8_t l5ctx_qp_flags; + #define L5CTX_QP_FLAGS_QP_VALID (1<<0) + #define L5CTX_QP_FLAGS_SUPPORTS_LAZY_WQES (1<<1) + #define L5CTX_QP_FLAGS_INBOUND_RDMA_READ_DISABLED (1<<2) + #define L5CTX_QP_FLAGS_INBOUND_RDMA_WRITE_DISABLED (1<<3) + #define L5CTX_QP_FLAGS_WINDOW_BINDS_ENABLED (1<<4) + #define L5CTX_QP_FLAGS_LOCAL_INVALIDATE_IN_PROGRESS (1<<5) + + u8_t l5ctx_null_cmd_cell_cidx; + u8_t l5ctx_null_cmd_cell_pidx; + u8_t l5ctx_snd_q_max_cached_wqes; + l5_orrq_entry_l_xi_t l5ctx_orrq[1]; + u32_t l5ctx_cq_cid; + u32_t unused_10[4]; + u32_t l5ctx_rdma_crc; + u32_t l5ctx_tcp_snd_wl1; + u32_t l5ctx_tcp_snd_wl2; + u8_t unused_11; + u8_t l5ctx_tcp_upload_reason; + #define L5CTX_TCP_UPLOAD_REASON_KEEP_ALIVE (1<<0) + #define L5CTX_TCP_UPLOAD_REASON_FIN (1<<1) + #define L5CTX_TCP_UPLOAD_REASON_URG (1<<2) + #define L5CTX_TCP_UPLOAD_REASON_FRAGMENT (1<<3) + #define L5CTX_TCP_UPLOAD_REASON_IP_OPTION (1<<4) + #define L5CTX_TCP_UPLOAD_REASON_RST (1<<5) + #define L5CTX_TCP_UPLOAD_REASON_SYN (1<<6) + #define L5CTX_TCP_UPLOAD_REASON_TIMEOUT (1<<7) + u16_t unused_12; + + u32_t l5ctx_tcp_offload_seq; + u32_t l5ctx_pg_cwin; + u32_t l5ctx_high_tcp_ack_sn_rcvd; + u8_t l5ctx_snd_q_pidx; + u8_t l5ctx_snd_q_cidx; + u16_t l5ctx_pd; + u8_t l5ctx_rcv_q_rxp_cidx; + u8_t l5ctx_rcv_q_pidx; + u8_t l5ctx_rcv_q_flags; + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE (0xf<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_256 (0<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_512 (1<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_1K (2<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_2K (3<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_4K (4<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_8K (5<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_16K (6<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_32K (7<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_64K (8<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_128K (9<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_256K (10<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_512K (11<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_1M (12<<0) + #define L5CTX_RCV_Q_FLAGS_PAGE_SIZE_2M (13<<0) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE (0xf<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_1 (0<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_2 (1<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_4 (2<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_8 (3<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_16 (4<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_32 (5<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_64 (6<<4) + #define L5CTX_RCV_Q_FLAGS_QUEUE_SIZE_128 (7<<4) + + u8_t l5ctx_read_rsp_wait; + u8_t l5ctx_ooo_read_resp_segs_w_L_bit; + u8_t l5ctx_rx_comp_flags; + #define L5CTX_RX_COMP_FLAGS_TCP_HOLE_EXISTS (1<<0) + #define L5CTX_RX_COMP_FLAGS_MARKER_IN_ISLAND (1<<1) + #define L5CTX_RX_COMP_FLAGS_READ_REQ_OUTSTANDING (1<<2) + #define L5CTX_RX_COMP_FLAGS_TCP_ISLAND_CREATED (1<<3) + + u8_t l5ctx_ird; + u8_t l5ctx_rcv_q_com_cidx; + u8_t l5ctx_rcv_path_op_state; + #define L5CTX_RCV_PATH_OP_STATE_OPERATIONAL (1<<0) + #define L5CTX_RCV_PATH_OP_STATE_BYPASS (1<<1) + + u8_t l5ctx_miq_index; + u8_t l5ctx_ooo_read_request_msgs; + u8_t l5ctx_ooo_send_msg_segs_w_L_bit; + u32_t l5ctx_send_msg_high_msn_completed; + u32_t l5ctx_read_req_high_msn_queued; + u32_t l5ctx_rx_initial_tcp_sn; + u32_t l5ctx_rsvd_l4_hole_mgmt[4]; + l5_irrq_entry_l_xi_t l5ctx_irrq[1]; + l5_abuf_cell_l_xi_t l5ctx_rcv_q_abuf[2]; + u32_t unused_13[9]; + u16_t l5ctx_snd_q_fw_qidx; + u16_t l5ctx_snd_q_max_wqes; + u16_t l5ctx_snd_q_wqes_per_page; + u16_t l5ctx_snd_q_pgtbl_pgidx; + u16_t l5ctx_snd_q_nx_pg_qidx; + u16_t l5ctx_snd_q_num_pages; + u32_t l5ctx_snd_q_pgtbl_phaddr_hi; + u8_t l5ctx_snd_q_flags; + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE (0xf<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_256 (0<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_512 (1<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_1K (2<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_2K (3<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_4K (4<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_8K (5<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_16K (6<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_32K (7<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_64K (8<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_128K (9<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_256K (10<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_512K (11<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_1M (12<<0) + #define L5CTX_SND_Q_FLAGS_PAGE_SIZE_2M (13<<0) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE (0xf<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_1 (0<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_2 (1<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_4 (2<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_8 (3<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_16 (4<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_32 (5<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_64 (6<<4) + #define L5CTX_SND_Q_FLAGS_QUEUE_SIZE_128 (7<<4) + + u8_t l5ctx_snd_q_pgtbl_phaddr_lo[3]; + u32_t l5ctx_rcv_q_pgtbl_phaddr_hi; + u8_t l5ctx_ord; + u8_t l5ctx_rcv_q_pgtbl_phaddr_lo[3]; + u16_t l5ctx_tsch_mult_value; + u16_t l5ctx_rcv_q_nx_pg_qidx; + u16_t l5ctx_rcv_q_fw_qidx; + u16_t l5ctx_rcv_q_max_wqes; + u16_t l5ctx_rcv_q_wqes_per_page; + u16_t l5ctx_rcv_q_pgtbl_pgidx; + u8_t l5ctx_max_gather_list_elements; + u8_t l5ctx_max_scatter_list_elements; + u16_t l5ctx_rcv_q_num_pages; + u32_t l5ctx_curr_send_msn; + u32_t l5ctx_curr_rdma_read_msn; + u32_t l5ctx_snd_q_cached_pte_phaddr_hi; + u32_t l5ctx_snd_q_cached_pte_phaddr_lo; + u32_t l5ctx_rcv_q_cached_pte_phaddr_hi; + u32_t l5ctx_rcv_q_cached_pte_phaddr_lo; + u32_t unused_14[15]; + tcp_context_cmd_cell_l_xi_t l5ctx_cmd[3]; +} l5_context_l_xi_t; + + +/* + * l5_context select + */ +#if defined(LITTLE_ENDIAN) + typedef l5_context_l_t l5_context_t; + typedef l5_context_l_xi_t l5_context_xi_t; +#elif defined(BIG_ENDIAN) + typedef l5_context_b_t l5_context_t; + typedef l5_context_b_xi_t l5_context_xi_t; +#endif + + +#endif /* _l5_defs_h_ */ diff --git a/usr/src/uts/common/io/bnx/570x/common/include/license.h b/usr/src/uts/common/io/bnx/570x/common/include/license.h new file mode 100644 index 0000000000..2cfc84376b --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/license.h @@ -0,0 +1,160 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _LICENSE_H +#define _LICENSE_H + +#include "bcmtype.h" + +#if !defined(LITTLE_ENDIAN) && !defined(BIG_ENDIAN) + #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." +#endif + + +#define HASH_VALUE_SIZE 12 +/* + * license_key_b definition + */ + +typedef struct _license_key_b +{ + u8_t digest[HASH_VALUE_SIZE]; + /* KEY_VALID_PATTERN is used when no actual digest is needed */ + #define KEY_VALID_PATTERN_BYTE 0x5a + #define KEY_VALID_PATTERN_DWORD 0x5a5a5a5a + + u8_t key_type; + #define KEY_TYPE_ENUM_BCM5706 0x0 + #define KEY_TYPE_ENUM_BCM5710 0x2 /* Special modification for Everest */ + u8_t version; + #define VERSION_CURRENT 0x0 + u8_t dword_length; /* Not including the digest */ + u8_t oem_id; + #define OEM_ID_BRCM 0 + #define OEM_ID_HPQ 0x3c + + u16_t capability; + #define CAP_RESERVED 0x0001 /* Xinan/Teton Only */ + #define CAP_USER_RDMA 0x0002 /* Xinan/Teton Only */ + #define CAP_TOE 0x0004 /* Xinan/Teton Only */ + #define CAP_ISCSI_INIT 0x0008 /* Xinan/Teton Only */ + #define CAP_ISCSI_TRGT 0x0010 /* Xinan/Teton Only */ + #define CAP_ISER_INIT 0x0020 /* Xinan/Teton Only */ + #define CAP_ISER_TRGT 0x0040 /* Xinan/Teton Only */ + #define CAP_ISCSI_BOOT 0x0080 /* Xinan/Teton Only */ + #define CAP_ISCSI_FULL_ACCL 0x0100 /* Xinan/Teton Only */ + #define CAP_ISCSI_HDR_DGST 0x0200 /* Xinan/Teton Only */ + #define CAP_ISCSI_BODY_DGST 0x0400 /* Xinan/Teton Only */ + #define CAP_SERDES_2_5G 0x0800 /* Xinan/Teton Only */ + #define CAP_SPEED_12G 0x0800 /* Everest Only */ + #define CAP_SPEED_12_5G 0x1000 + #define CAP_SPEED_13G 0x2000 + #define CAP_SPEED_15G 0x4000 + #define CAP_SPEED_16G 0x8000 + u16_t max_toe_conn; + #define CONN_UNLIMITED 0xffff + + u16_t reserved; + u16_t max_um_rdma_conn; + + u16_t max_iscsi_init_conn; + u16_t max_iscsi_trgt_conn; + + u16_t max_iser_init_conn; + u16_t max_iser_trgt_conn; + + u32_t reserved_a[3]; + + u32_t sn; + + u16_t reserved_b; + u16_t expiration; + #define EXPIRATION_NEVER 0xffff + +} license_key_b_t; + +/* + * license_key_l definition + */ + +#define KEY_VALID_PATTERN_BYTE 0x5a +#define KEY_VALID_PATTERN_DWORD 0x5a5a5a5a +typedef struct _license_key_l +{ + u8_t digest[HASH_VALUE_SIZE]; + /* KEY_VALID_PATTERN is used when no actual digest is needed */ + + u8_t oem_id; + #define OEM_ID_BRCM 0 + #define OEM_ID_HPQ 0x3c + u8_t dword_length; /* Not including the digest */ + u8_t version; + #define VERSION_CURRENT 0x0 + u8_t key_type; + #define KEY_TYPE_ENUM_BCM5706 0x0 + #define KEY_TYPE_ENUM_BCM5710 0x2 /* Special modification for Everest */ + + u16_t max_toe_conn; + #define CONN_UNLIMITED 0xffff + u16_t capability; + #define CAP_RESERVED 0x0001 /* Xinan/Teton Only */ + #define CAP_USER_RDMA 0x0002 /* Xinan/Teton Only */ + #define CAP_TOE 0x0004 /* Xinan/Teton Only */ + #define CAP_ISCSI_INIT 0x0008 /* Xinan/Teton Only */ + #define CAP_ISCSI_TRGT 0x0010 /* Xinan/Teton Only */ + #define CAP_ISER_INIT 0x0020 /* Xinan/Teton Only */ + #define CAP_ISER_TRGT 0x0040 /* Xinan/Teton Only */ + #define CAP_ISCSI_BOOT 0x0080 /* Xinan/Teton Only */ + #define CAP_ISCSI_FULL_ACCL 0x0100 /* Xinan/Teton Only */ + #define CAP_ISCSI_HDR_DGST 0x0200 /* Xinan/Teton Only */ + #define CAP_ISCSI_BODY_DGST 0x0400 /* Xinan/Teton Only */ + #define CAP_SERDES_2_5G 0x0800 /* Xinan/Teton Only */ + #define CAP_SPEED_12G 0x0800 /* Everest Only */ + #define CAP_SPEED_12_5G 0x1000 + #define CAP_SPEED_13G 0x2000 + #define CAP_SPEED_15G 0x4000 + #define CAP_SPEED_16G 0x8000 + + u16_t max_um_rdma_conn; + u16_t reserved; + + u16_t max_iscsi_trgt_conn; + u16_t max_iscsi_init_conn; + + u16_t max_iser_trgt_conn; + u16_t max_iser_init_conn; + + u32_t reserved_a[3]; + + u32_t sn; + + u16_t expiration; + #define EXPIRATION_NEVER 0xffff + u16_t reserved_b; + +} license_key_l_t; + + +#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e +#define FW_ENCODE_16BIT_PATTERN 0x1e1e +#define FW_ENCODE_8BIT_PATTERN 0x1e + + +#if defined(BIG_ENDIAN) + typedef license_key_b_t license_key_t; +#elif defined(LITTLE_ENDIAN) + typedef license_key_l_t license_key_t; +#endif + +#endif /* _LICENSE_H */ diff --git a/usr/src/uts/common/io/bnx/570x/common/include/netlink.h b/usr/src/uts/common/io/bnx/570x/common/include/netlink.h new file mode 100644 index 0000000000..775c549f3b --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/netlink.h @@ -0,0 +1,209 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _netlink_h_ +#define _netlink_h_ + +#include "bcmtype.h" + +/* The values are defined to adapt the previous IMD firmware definitions */ +#define NETLINK_STATUS_SUCCESS 0 +#define NETLINK_STATUS_DENY_PHY_ACCESS_FAILURE 0x10005 +#define NETLINK_STATUS_PHY_FAILURE 0x1000a +#define NETLINK_STATUS_WRONG_MEDIA_FAILURE 0x20006 +#define NETLINK_STATUS_BAD_LINK_SETTING_FAILURE 0x20007 +#define NETLINK_STATUS_PWR_MGMT_CONFLICT_FAILURE 0x20008 +#define NETLINK_STATUS_INVALID_INPUT_FAILURE 0x20002 +#define NETLINK_STATUS_NOT_SUPPORTED_FAILURE 0x2000b +#define NETLINK_STATUS_BAD_SPEED_FAILURE 0x80000001 +#define NETLINK_STATUS_LINK_ALREADY_UP_FAILURE 0x80000002 + + + + +/* Link status codes: definition based on what's in shmem.h */ +#define NETLINK_GET_LINK_STATUS_INIT_VALUE 0xffffffff +#define NETLINK_GET_LINK_STATUS_LINK_UP 0x1 +#define NETLINK_GET_LINK_STATUS_LINK_DOWN 0x0 +#define NETLINK_GET_LINK_STATUS_SPEED_MASK 0x1e +#define NETLINK_GET_LINK_STATUS_AN_INCOMPLETE (0<<1) + +#define NETLINK_GET_LINK_STATUS_10HALF (1<<1) +#define NETLINK_GET_LINK_STATUS_10FULL (2<<1) +#define NETLINK_GET_LINK_STATUS_100HALF (3<<1) +#define NETLINK_GET_LINK_STATUS_100BASE_T4 (4<<1) +#define NETLINK_GET_LINK_STATUS_100FULL (5<<1) +#define NETLINK_GET_LINK_STATUS_1000HALF (6<<1) +#define NETLINK_GET_LINK_STATUS_1000FULL (7<<1) +#define NETLINK_GET_LINK_STATUS_2500HALF (8<<1) + +#define NETLINK_GET_LINK_STATUS_2500FULL (9<<1) + +#define NETLINK_GET_LINK_STATUS_AN_ENABLED 0x000020L +#define NETLINK_GET_LINK_STATUS_AN_COMPLETE 0x000040L +#define NETLINK_GET_LINK_STATUS_PARALLEL_DET 0x000080L +#define NETLINK_GET_LINK_STATUS_RESERVED 0x000100L +#define NETLINK_GET_LINK_STATUS_PARTNER_AD_1000FULL 0x000200L +#define NETLINK_GET_LINK_STATUS_PARTNER_AD_1000HALF 0x000400L +#define NETLINK_GET_LINK_STATUS_PARTNER_AD_100BT4 0x000800L +#define NETLINK_GET_LINK_STATUS_PARTNER_AD_100FULL 0x001000L +#define NETLINK_GET_LINK_STATUS_PARTNER_AD_100HALF 0x002000L +#define NETLINK_GET_LINK_STATUS_PARTNER_AD_10FULL 0x004000L +#define NETLINK_GET_LINK_STATUS_PARTNER_AD_10HALF 0x008000L +#define NETLINK_GET_LINK_STATUS_TX_FC_ENABLED 0x010000L +#define NETLINK_GET_LINK_STATUS_RX_FC_ENABLED 0x020000L +#define NETLINK_GET_LINK_STATUS_PARTNER_SYM_PAUSE_CAP 0x040000L +#define NETLINK_GET_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP 0x080000L +#define NETLINK_GET_LINK_STATUS_SERDES_LINK 0x100000L +#define NETLINK_GET_LINK_STATUS_PARTNER_AD_2500FULL 0x200000L +#define NETLINK_GET_LINK_STATUS_PARTNER_AD_2500HALF 0x400000L + +#define NETLINK_GET_LINK_STATUS_NO_MEDIA_DETECTED 0x20000000L +#define NETLINK_GET_LINK_STATUS_CABLESENSE 0x40000000L +#define NETLINK_GET_LINK_STATUS_SW_TIMER_EVENT 0x80000000L + + +/* netlink_get_link_status(): + * Input: A pointer to a u32_t type storage + * Output: bit-wise OR'd of any NETLINK_GET_LINK_STATUS_* constants + * Return: 0 for success, non-zero for failure (see NETLINK_CODE_* constants). + */ +typedef u32_t (* netlink_get_link_status_t)(u32_t *get_link_attrib); + +u32_t netlink_get_link_status ( u32_t *get_link_attrib ); + + + +/* netlink_drv_set_link() + * Input: A u32_t value indicating the desired link + * Output: None, in fact, the link may not be effective right away + * (subject to the time needed to establish the link). + * Return: 0 for success, non-zero for failure (see NETLINK_CODE_* constants). + */ +u32_t netlink_drv_set_link( u32_t drv_link_attrib ); + +#define NETLINK_DRV_SET_LINK_SPEED_10HALF (1<<0) +#define NETLINK_DRV_SET_LINK_SPEED_10FULL (1<<1) +#define NETLINK_DRV_SET_LINK_SPEED_100HALF (1<<2) +#define NETLINK_DRV_SET_LINK_SPEED_100FULL (1<<3) + +#define NETLINK_DRV_SET_LINK_SPEED_1GHALF (1<<4) +#define NETLINK_DRV_SET_LINK_SPEED_1GFULL (1<<5) + +#define NETLINK_DRV_SET_LINK_SPEED_2G5HALF (1<<6) +#define NETLINK_DRV_SET_LINK_SPEED_2G5FULL (1<<7) + +#define NETLINK_DRV_SET_LINK_SPEED_10GHALF (1<<8) // place holder for now. +#define NETLINK_DRV_SET_LINK_SPEED_10GFULL (1<<9) // place holder for now. +#define NETLINK_DRV_SET_LINK_ENABLE_AUTONEG (1<<10) + /* (vs Forced): If autoeng enabled, the speed + * bits above dictate what capability advertisement. + * Otherwise, only one of the applicable speed/duplex + * bits above can be set, and it will be used to + * establish the forced link. + */ +#define NETLINK_DRV_SET_LINK_PHY_APP_MASK (1<<11) +#define NETLINK_DRV_SET_LINK_PHY_APP_REMOTE (1<<11) +#define NETLINK_DRV_SET_LINK_PHY_APP_LOCAL (0<<11) + + /* (Local vs Remote): The setting will be stored as + * driver preference. If the media type matches the + * current setup, the setting will also be applied + * immediately. + */ + +#define NETLINK_DRV_SET_LINK_FC_SYM_PAUSE (1<<12) +#define NETLINK_DRV_SET_LINK_FC_ASYM_PAUSE (1<<13) + +#define NETLINK_DRV_SET_LINK_ETH_AT_WIRESPEED_ENABLE (1<<14) +#define NETLINK_DRV_SET_LINK_PHY_RESET (1<<15) + /* Local serdes will be reset. If remote Cu PHY + * is present, MDIO write will be issued to the + * remote PHY to reset it. Then, whatever other + * settings will be applied. + */ + + +/* This override bit tells the set_link() routine to set the link + * again even if the link is already up at a desired speed */ +#define NETLINK_SET_LINK_OVERRIDE 0x80000000 + +/* Setting this will advertise all capability that the power budget (e.g. + * overdraw Vaux current in absence of main power) and design capability + * (e.g. 2.5G) allow. + * In case of the 5708 Serdes, fall back is assumed. */ +#define NETLINK_SET_LINK_SPEED_AUTONEG 0x00 + +/* These speed values are used for forced speed unless selective autoneg + * is selected. Do NOT try to bit-wise OR them. In the case of selective + * autoneg, that speed will be advertised. */ +#define NETLINK_SET_LINK_SPEED_UNKNOWN 0x00 +#define NETLINK_SET_LINK_SPEED_10MBPS 0x01 +#define NETLINK_SET_LINK_SPEED_100MBPS 0x02 +#define NETLINK_SET_LINK_SPEED_1000MBPS 0x04 +#define NETLINK_SET_LINK_SPEED_2500MBPS 0x08 +#define NETLINK_SET_LINK_SPEED_MASK 0xff + +#define NETLINK_SET_LINK_DUPLEX_HALF 0x0100 +#define NETLINK_SET_LINK_DUPLEX_FULL 0x0000 + +#define NETLINK_SET_LINK_PAUSE_CAP 0x0200 +#define NETLINK_SET_LINK_ASYM_PAUSE 0x0400 + +/* When selective autoneg is enabled, only one speed will be used for + * capability advertisement. */ +#define NETLINK_SET_LINK_SELECTIVE_AUTONEG 0x10000 + +/* netlink_set_link(): + * Input: bit-wise OR'd of any NETLINK_SET_LINK_* constants (except the speed) + * Output: None. + * Return: 0 for success, non-zero for failure (see NETLINK_CODE_* constants). + * + * Example 1: To set 100Full forced speed, the parameter would look like + * NETLINK_SET_LINK_SPEED_100MBPS | + * NETLINK_SET_LINK_DUPLEX_FULL. + * Example 2: To set selective autoneg at 100Full with pause capability, + * the parameter would look like + * NETLINK_SET_LINK_SPEED_100MBPS | + * NETLINK_SET_LINK_PAUSE_CAP | + * NETLINK_SET_LINK_SELECTIVE_AUTONEG | + * NETLINK_SET_LINK_DUPLEX_FULL. + * + * Note 1: If caller passes any speed settings, and if the system is + * in OSPresent mode, no action will be taken, the actual speed + * advertisement will be done by OS Driver. + * Note 2: If caller passes "NETLINK_SET_LINK_SPEED_AUTONEG" parameter, + * if the system is in OSAbsent mode and if the system has + * Vmain power the link speed 2500/1000/100/10 will be advertised. + * Note 3: If caller passes "NETLINK_SET_LINK_SPEED_AUTONEG" parameter, + * if the system is in OSAbsent mode and if the system does + * not have Vmain power (Vaux power mode) and the " + * PowerOverDrawn" bit is set (OK to consume more power in + * order to acquire highest link speed), the link speed + * 2500/1000/100/10 will be advertised. + * Note 4: If caller passes "NETLINK_SET_LINK_SPEED_AUTONEG" parameter, + * if the system is in OSAbsent mode, and if the system does + * not have Vmain power (Vaux power mode) and the + * "PowerOverDrawn" bit is cleared (don't consume more power + * than necessary), the link speed 100/10 will be advertised. + * + */ +typedef u32_t (* netlink_set_link_t)(u32_t set_link_attrib); + +u32_t netlink_set_link ( u32_t set_link_attrib ); + + +void netlink_serdes_fallback ( void ); + +#endif /* _netlink_h_ */ diff --git a/usr/src/uts/common/io/bnx/570x/common/include/rxp_hsi.h b/usr/src/uts/common/io/bnx/570x/common/include/rxp_hsi.h new file mode 100644 index 0000000000..0c3c312a02 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/rxp_hsi.h @@ -0,0 +1,152 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RXP_HSI_H +#define _RXP_HSI_H + +#define RSS_TABLE_MAX 128 + +// Offset of xxx_hsi in 32 bit words from beginning of scratchpad +#define RXP_HSI_OFFSET 0x4 + +typedef struct _rxp_hsi_t { + fw_version_t version; + u32_t rxp_knum; + u32_t rxp_flood; + u32_t ric; + u32_t l2_forward_to_mcp; + u32_t tcp_syn_dos_defense; + u32_t rss_enable; + u32_t rss_table_size; + u8_t rss_table[RSS_TABLE_MAX]; + u32_t rxp_os_flag; + u32_t discard_all; + u32_t rxp_num_discard_all; + u32_t rtca; + u32_t rtcc; + u32_t rxp_pm_ctrl; + #define L2_NORMAL_MODE 0 + #define L2_EMC_RXQ_MODE_ENABLE 1 + #define L2_EMC_RXQ_MODE_DISABLE 2 + u32_t ooo_pkt_cnt; + u32_t l2_cu_cnt; + u32_t rxp_invalid_context_cnt; + u64_t rxp_unicast_bytes_rcvd; + u64_t rxp_multicast_bytes_rcvd; + u64_t rxp_broadcast_bytes_rcvd; + u64_t volatile idle_count; + u32_t hash_lookup[12][256]; + u32_t ulp_out_of_order_packets; // number of OOO packets that were received in L5 connections + u32_t cps_index; + u32_t cps_array[32]; + u32_t iscsi_rq_size; // number of RQ buffers. Note this is not size of page table + u32_t iscsi_rq_buf_size; // size of receive buffer in RQ + u32_t iscsi_err_bitmap[2]; // Error/Warning bitmap ("1" for warning) + u32_t iscsi_tcp_config; // Configuration register - Enable/Disable of DA/KA mechanisms + u32_t iscsi_teton_l4_cmd_offset; // Teton only: offset of L4 ccell command array + u32_t iscsi_teton_l5_offset; // Teton only: offset of L5 section + u32_t iscsi_teton_l5_cmd_offset; // Teton only: offset of L5 ccell command array + u32_t iscsi_task_offset; // offset of the task array + u32_t iscsi_r2tq_offset; // offset of R2TQ section + u32_t iscsi_max_num_of_tasks; // maximal number of pending tasks + u32_t iscsi_max_num_of_ccells; // maximal number of ccells + + u64_t iscsi_rxp_unicast_bytes_rcvd; + u64_t iscsi_rxp_multicast_bytes_rcvd; + u64_t iscsi_rxp_broadcast_bytes_rcvd; + u32_t after_fin_pkt_cnt; // number of packets that came after FIN + u32_t extra_fin_pkt_cnt; // extra FIN packets that came after FIN + u32_t vmq_netq_cnt; // number of vmq or netq + u32_t hw_filter_ctx_offset; + u32_t iooo_rx_cid; + u32_t iooo_flags; + u32_t iooo_dbg_size; + u32_t iooo_dbg_ptr; + u32_t ooo_cu_pkt_cnt; + u32_t ooo_cu_pkt_drop_cnt; + u32_t ooo_max_blk_reach_cnt; + u32_t ooo_max_blk_pkt_drop_cnt; + u32_t cu_rate_limiter_enable; + u32_t ooo_max_blk_per_conn; + u64_t rxp_total_bytes_rcvd; +} rxp_hsi_t; + +// This macro can be used for little or big endian 32-bit system +#define RXP_HSI_OFFSETOFF(m) (OFFSETOF(rxp_hsi_t,m) + 0x10) +#define RXP_HSI_SIZEOF(m) (sizeof (((rxp_hsi_t *)0)->m)) + +// Calling the following macro will actually get optimized during compile +// time. Its sole purpose is to ensure HSI variables cannot be modified/moved +// unnoticed scratch[10240] 0xe0000 (RW/Reset: undefined) +#define TEST_RXP_HSI(){ \ +if (0){ \ + 1/(RXP_HSI_OFFSETOFF(version) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x000) && \ + RXP_HSI_OFFSETOFF(rxp_knum) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x010) && \ + RXP_HSI_OFFSETOFF(rxp_flood) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x014) && \ + RXP_HSI_OFFSETOFF(ric) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x018) && \ + RXP_HSI_OFFSETOFF(l2_forward_to_mcp) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x01c) && \ + RXP_HSI_OFFSETOFF(tcp_syn_dos_defense) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x020) && \ + RXP_HSI_OFFSETOFF(rss_enable) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x024) && \ + RXP_HSI_OFFSETOFF(rss_table_size) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x028) && \ + RXP_HSI_OFFSETOFF(rss_table) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x02c) && \ + RXP_HSI_OFFSETOFF(rxp_os_flag) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x0ac) && \ + RXP_HSI_OFFSETOFF(discard_all) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x0b0) && \ + RXP_HSI_OFFSETOFF(rxp_num_discard_all) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x0b4) && \ + RXP_HSI_OFFSETOFF(rtca) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x0b8) && \ + RXP_HSI_OFFSETOFF(rtcc) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x0bc) && \ + RXP_HSI_OFFSETOFF(rxp_pm_ctrl) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x0c0) && \ + RXP_HSI_OFFSETOFF(ooo_pkt_cnt) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x0c4) && \ + RXP_HSI_OFFSETOFF(l2_cu_cnt) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x0c8) && \ + RXP_HSI_OFFSETOFF(rxp_invalid_context_cnt) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x0cc) && \ + RXP_HSI_OFFSETOFF(rxp_unicast_bytes_rcvd) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x0d0) && \ + RXP_HSI_OFFSETOFF(rxp_multicast_bytes_rcvd) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x0d8) && \ + RXP_HSI_OFFSETOFF(rxp_broadcast_bytes_rcvd) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x0e0) && \ + RXP_HSI_OFFSETOFF(idle_count) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x0e8) && \ + RXP_HSI_OFFSETOFF(hash_lookup) == (RXP_HSI_OFFSET * sizeof(u32_t) + 0x0f0) && \ + RXP_HSI_OFFSETOFF(ulp_out_of_order_packets) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x30f0) && \ + RXP_HSI_OFFSETOFF(cps_index) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x30f4) && \ + RXP_HSI_OFFSETOFF(cps_array) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x30f8) && \ + RXP_HSI_OFFSETOFF(iscsi_rq_size) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x3178) && \ + RXP_HSI_OFFSETOFF(iscsi_rq_buf_size) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x317c) && \ + RXP_HSI_OFFSETOFF(iscsi_err_bitmap[0]) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x3180) && \ + RXP_HSI_OFFSETOFF(iscsi_err_bitmap[1]) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x3184) && \ + RXP_HSI_OFFSETOFF(iscsi_tcp_config) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x3188) && \ + RXP_HSI_OFFSETOFF(iscsi_teton_l4_cmd_offset) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x318c) && \ + RXP_HSI_OFFSETOFF(iscsi_teton_l5_offset) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x3190) && \ + RXP_HSI_OFFSETOFF(iscsi_teton_l5_cmd_offset) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x3194) && \ + RXP_HSI_OFFSETOFF(iscsi_task_offset) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x3198) && \ + RXP_HSI_OFFSETOFF(iscsi_r2tq_offset) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x319c) && \ + RXP_HSI_OFFSETOFF(iscsi_max_num_of_tasks) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31a0) && \ + RXP_HSI_OFFSETOFF(iscsi_max_num_of_ccells) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31a4) && \ + RXP_HSI_OFFSETOFF(iscsi_rxp_unicast_bytes_rcvd) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31a8) && \ + RXP_HSI_OFFSETOFF(iscsi_rxp_multicast_bytes_rcvd)== (RXP_HSI_OFFSET * sizeof(u32_t) +0x31b0) && \ + RXP_HSI_OFFSETOFF(iscsi_rxp_broadcast_bytes_rcvd)== (RXP_HSI_OFFSET * sizeof(u32_t) +0x31b8) && \ + RXP_HSI_OFFSETOFF(after_fin_pkt_cnt) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31c0) && \ + RXP_HSI_OFFSETOFF(extra_fin_pkt_cnt) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31c4) && \ + RXP_HSI_OFFSETOFF(vmq_netq_cnt) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31c8) && \ + RXP_HSI_OFFSETOFF(hw_filter_ctx_offset) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31cc) && \ + RXP_HSI_OFFSETOFF(iooo_rx_cid) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31d0) && \ + RXP_HSI_OFFSETOFF(iooo_flags) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31d4) && \ + RXP_HSI_OFFSETOFF(iooo_dbg_size) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31d8) && \ + RXP_HSI_OFFSETOFF(iooo_dbg_ptr) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31dc) && \ + RXP_HSI_OFFSETOFF(ooo_cu_pkt_cnt) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31e0) && \ + RXP_HSI_OFFSETOFF(ooo_cu_pkt_drop_cnt) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31e4) && \ + RXP_HSI_OFFSETOFF(ooo_max_blk_reach_cnt) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31e8) && \ + RXP_HSI_OFFSETOFF(ooo_max_blk_pkt_drop_cnt) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31ec) && \ + RXP_HSI_OFFSETOFF(cu_rate_limiter_enable) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31f0) && \ + RXP_HSI_OFFSETOFF(ooo_max_blk_per_conn) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31f4) && \ + RXP_HSI_OFFSETOFF(rxp_total_bytes_rcvd) == (RXP_HSI_OFFSET * sizeof(u32_t) +0x31f8) && \ + RXP_HSI_OFFSETOFF(rxp_total_bytes_rcvd)+RXP_HSI_SIZEOF(rxp_total_bytes_rcvd) == (RXP_HSI_OFFSET * sizeof(u32_t) + sizeof(rxp_hsi_t)));}} +#endif + diff --git a/usr/src/uts/common/io/bnx/570x/common/include/serdes.h b/usr/src/uts/common/io/bnx/570x/common/include/serdes.h new file mode 100644 index 0000000000..cd37baa140 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/serdes.h @@ -0,0 +1,724 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _serdes_h_ +#define _serdes_h_ + +#include "bcmtype.h" + + +/* + * This structure defines the MDIO registers for the 2.5G Serdes block + * Only those registers relevant to normal operation and configuration + * are described. Extra verbage is provided based on TetonII teams + * experience with the core. Bible for all registers is still + * the spreadsheet provided by the serdes group. + */ +typedef struct serdes_reg +{ + u16_t mii_ctrl; /* RW offset 0x00 */ + #define MII_CTRL_RESET (1<<15) /* SC */ /* Reset:0 */ + /* Write of '1' initiate reset and will self clear when reset + is complete. Read of '1' indicates if PHY is currently + executing reset. */ + #define MII_CTRL_LOOPBACK (1<<14) /* RW */ + /* Value of '1' sets global loopback mode. */ + #define MII_CTRL_MANUAL_SPD0 (1<<13) /* RW */ + /* Combine with <b>MANUAL_SPD1</b> and is valid in SGMII mode + only.<br> + 00 = 10Mb/s<br> + 01 = 100Mb/s<br> + 10 = 1000Mb/s<br> + 11 = reserved */ + #define MII_CTRL_ANEG_ENA (1<<12) /* Reset:1 */ + #define MII_CTRL_POWER_DOWN (1<<11) + /* Value of '1 enables low power mode. */ + #define MII_CTRL_RESTART_ANEG (1<<9) /* SC */ + /* Write of '1' initiate auto-negotiation and will self clear + when auto-negotiation + is complete. */ + #define MII_CTRL_DUPLEX_MODE (1<<8) + /* Value of '1' indicates full duplex mode is set. */ + #define MII_CTRL_COLLISION_TEST (1<<7) + /* Value of '1' enables collision test mode. */ + #define MII_CTRL_MANUAL_SPD1 (1<<6) /* RW */ + /* Combine with <b>MANUAL_SPD0</b> and is valid in SGMII mode + only. */ + #define MII_CTRL_MANUAL_FORCE_2500 (1<<5) /* RW */ /* Reset:0 */ + /* Force 2.5G mode when autoneg is disabled and <b>USE_IEEE</b> + is set. Otherwise write as 0, ignore on read. */ + /* Reset value is from <b>serdes_control_reg[13]</b> value in + the misc block. */ + u16_t mii_status; /* RO offset 0x01 */ + #define MII_STAT_100BASE_T4_CAP (1<<15) /* RO */ /* Reset:0 */ + #define MII_STAT_100BASE_X_FULL_DUP_CAP (1<<14) /* RO */ /* Reset:0 */ + #define MII_STAT_100BASE_X_HALF_DUP_CAP (1<<13) /* RO */ /* Reset:0 */ + #define MII_STAT_10BASE_T_FULL_DUP_CAP (1<<12) /* RO */ /* Reset:0 */ + #define MII_STAT_10BASE_T_HALF_DUP_CAP (1<<11) /* RO */ /* Reset:0 */ + #define MII_STAT_100BASE_T2_FULL_DUP_CAP (1<<10) /* RO */ /* Reset:0 */ + #define MII_STAT_100BASE_T2_HALF_DUP_CAP (1<<9) /* RO */ /* Reset:0 */ + #define MII_STAT_EXT_STATUS (1<<8) /* RO */ /* Reset:1 */ + /* Indicates that extended status information is in register f'h. + */ + #define MII_STAT_MF_PREAMBLE_SUPP (1<<6) /* RO */ /* Reset:1 */ + /* Indicates that preamble is not require on all MII accesses. */ + #define MII_STAT_ANEG_CMPL (1<<5) /* RO */ /* Reset:0 */ + /* Value of '1' indicates auto-negotiation complete. */ + /* Value of '0' indicates auto-negotiation is in progress. */ + #define MII_STAT_REMOTE_FAULT (1<<4) /* AC */ /* Reset:0 */ + /* Value of '1' indicates remote fault detected. */ + /* This bit latches high until read. */ + #define MII_STAT_ANEG_ABILITY (1<<3) /* RO */ /* Reset:1 */ + /* Value of '1' indicates auto-negotiation capable. */ + #define MII_STAT_LINK_STATUS (1<<2) /* RO */ /* Reset:0 */ + /* Value of '1' indicates line pass. */ + /* Value of '0' indicates line fail. */ + /* This bit latches low until read. */ + #define MII_STAT_JABBER_DETECT (1<<1) /* RO */ /* Reset:0 */ + /* Value of '1' indicates jabber condition detected. */ + #define MII_STAT_EXTENDED_CAP (1<<0) /* RO */ /* Reset:1 */ + /* Value of '1' indicates that extended register capabilities are + supported. */ + u16_t mii_phy_id_msb; /* Reset:0x143 offset 0x02 */ + /* Bits [3:18] of organizationally unique identifier. */ + u16_t mii_phy_id_lsb; /* offset 0x03 */ + #define MII_PHY_ID_OUI (0x3f<<10) /* RO */ /* Reset:0x2f */ + /* Bits [19:24] of organizationally unique identifier. */ + #define MII_PHY_ID_MODEL (0x3f<<4) /* RO */ /* Reset:0x15 */ + /* Device Mode number. */ + #define MII_PHY_ID_REV (0xf<<0) /* RO */ /* Reset:0 */ + /* Device revision number. */ + + u16_t mii_aneg_advert; /* RW offset 0x04 */ + #define MII_ADVERT_NXT_PG (1<<15) /* RO */ + /* Value of '0' indicates that next page ability capability can + not be advertised. */ + #define MII_ADVERT_REM_FAULT (0x3<<12) /* RW */ + #define MII_ADVERT_REM_FAULT_NO_FAULT (0<<12) + /* No remote fault */ + #define MII_ADVERT_REM_FAULT_LINK_FAILURE (1<<12) + /* Link failure */ + #define MII_ADVERT_REM_FAULT_OFFLINE (2<<12) + /* offline */ + #define MII_ADVERT_REM_FAULT_AUTONEG_ERR (3<<12) + /* auto-negotiation error */ + #define MII_ADVERT_PAUSE (3<<7) /* RW */ /* Reset:0x3 */ + #define MII_ADVERT_NO_PAUSE (0x0<<7) + /* Advertise no Pause */ + #define MII_ADVERT_SYM_PAUSE (0x1<<7) + /* Advertise symmetric Pause */ + #define MII_ADVERT_ASYM_PAUSE (0x2<<7) + /* Advertise asymmetric Pause toward link partner */ +// #define MII_ADVERT_PAUSE (0x3<<7) + /* Advertise both symmetric pause and asymmetric pause + toward local device. */ + #define MII_ADVERT_HALF (1<<6) /* RW */ /* Reset:1 */ + /* Advertise half duplex capability. */ + #define MII_ADVERT_FULL (1<<5) /* RW */ /* Reset:1 */ + u16_t mii_aneg_ability; /* RW offset 0x05 */ + #define MII_ABILITY_NXT_PG (1<<15) /* RO */ + /* Value of '1' indicates that link partner has next page ability. + */ + #define MII_ABILITY_ACKNOWLEDGE (1<<14) /* RO */ + /* Value of '1' indicates that link partner has receive link code + word. */ + #define MII_ABILITY_REM_FAULT (3<<12) /* RO */ + #define MII_ABILITY_REM_FAULT_AUTONEG_ERR (0<<12) /* RO */ + /* auto-negotiation error. */ + #define MII_ABILITY_REM_FAULT_OFFLINE (1<<12) /* RO */ + /* Offline. */ + #define MII_ABILITY_REM_FAULT_LINK_FAILURE (2<<12) /* RO */ + /* Link Failure. */ + #define MII_ABILITY_REM_FAULT_NO_FAULT (3<<12) /* RO */ + /* No remote fault detected. */ + #define MII_ABILITY_PAUSE (3<<7) /* RO */ /* Reset:0x3 */ + #define MII_ADVERT_NO_PAUSE (0x0<<7) + /* Line partner indicates No Pause capable */ + #define MII_ADVERT_SYM_PAUSE (0x1<<7) + /* Line partner wants Symmetric Pause capable */ + #define MII_ADVERT_ASYM_PAUSE (0x2<<7) + /* Line partner wants Asymetric Pause toward link partner + capable */ +// #define MII_ADVERT_PAUSE (0x3<<7) + /* Line partner wants Both symmetric pause and asymmetric pause + toward local device capable. */ + #define MII_ABILITY_HALF (1<<6) /* RO */ /* Reset:1 */ + /* Value of '1' indicates Link partner is half duplex capable. + */ + #define MII_ABILITY_FULL (1<<5) /* RO */ /* Reset:1 */ + /* Value of '1' indicates Link partner is full duplex capable. + */ + #define MII_ABILITY_SGMII (1<<0) /* RO */ + /* Value of '1' indicates link partner is in SGMII mode. */ + /* When SGMII mode is enabled, reading values reflect values sent by + link partner where:<br> + [15] = copper link<br> + [14] = acknowledge<br> + [12] = copper duplex<br> + [11:10] = copper speed<br> + [0] = SGMII selector */ + u16_t mii_aneg_exp; /* RW offset 0x06 */ + #define MII_ANEG_EXP_NP_ABLE (1<<2) /* RO */ + /* Value of '1' indicates local device is next page capable. + */ + #define MII_ANEG_EXP_PG_RCV (1<<1) /* AC */ + /* Value of '1' indicates a new link code word has been received. + */ + u16_t mii_aneg_nxt_pg; /* RW offset 0x07 */ + #define MII_ANEG_NXT_PG_NX_PG (1<<15) /* RW */ + /* During SW controlled auto-negotiation, this value controls the + next_page value in the next page generated. */ + #define MII_ANEG_NXT_PG_ACK (1<<14) /* RW */ + /* During SW controlled auto-negotiation, this value is controlled + by autoneg state machine to confirm page reception. */ + #define MII_ANEG_NXT_PG_MP (1<<13) /* RW */ + /* During SW controlled auto-negotiation, this value controls the + message page bit value in the next page generated. */ + #define MII_ANEG_NXT_PG_ACK2 (1<<12) /* RW */ + /* During SW controlled auto-negotiation, this value is controlled + by autoneg state machine to confirm page reception. */ + #define MII_ANEG_NXT_PG_TOG (1<<11) /* RW */ + /* During SW controlled auto-negotiation, this value is controlled + by autoneg state machine to confirm page reception. */ + #define MII_ANEG_NXT_PG_VALUE (0x7ff<<0) /* RW */ + /* During SW controlled auto-negotiation, this value controls the + 11-bit message page or unformatted code field in the next page + generated. */ + u16_t mii_aneg_nxt_ability; /* RW offset 0x08 */ + #define MII_ANEG_NXT_ABIL_NX_PG (1<<15) /* RW */ + /* During SW controlled auto-negotiation, this value reflects the + next_page value in the last page received. */ + #define MII_ANEG_NXT_ABIL_ACK (1<<14) /* RW */ + /* During SW controlled auto-negotiation, this value is used + by autoneg state machine to confirm page reception. */ + #define MII_ANEG_NXT_ABIL_MP (1<<13) /* RW */ + /* During SW controlled auto-negotiation, this value reflects the + message page bit value in the last page received. */ + #define MII_ANEG_NXT_ABIL_ACK2 (1<<12) /* RW */ + /* During SW controlled auto-negotiation, this value is used + by autoneg state machine to confirm page reception. */ + #define MII_ANEG_NXT_ABIL_TOG (1<<11) /* RW */ + /* During SW controlled auto-negotiation, this value is used + by autoneg state machine to confirm page reception. */ + #define MII_ANEG_NXT_ABIL_VALUE (0x7ff<<0) /* RW */ + /* During SW controlled auto-negotiation, this value reflects the + 11-bit message page or unformatted code field in the last page + received. */ + u16_t mii_reserved_9[2]; /* offset 0x09-0x0a */ + u16_t mii_aneg_nxt_pg_xmit1; /* RW offset 0x0b */ + /* If <b>USE_IEEE</b> is set, this page is transmitted after + the message page of value 1024 is sent. */ + #define MII_ANEG_NXT_PG_XMIT1_VALUE (0x3ff<<1) /* RW */ + /* Advertise reserved BRCM proprietary values. */ + #define MII_ANEG_NXT_PG_XMIT1_2G5 (1<<0) /* RW */ + /* Reset value is defined by the + value of <b>serdes_control_reg[11]</b> value in the misc block. + Value advertizes 2.5G capability by BRCM + proprietary convention. + */ + u16_t mii_aneg_nxt_pg_xmit2; /* RW offset 0x0c */ + /* If <b>USE_IEEE</b> is set, this page is transmitted after + the <b>auto_nxt_pg_xmit1</b> page is sent. */ + #define MII_ANEG_NXT_PG_XMIT2_VALUE (0x7ff<<0) /* RW */ /* Reset:0 */ + /* By BRCM proprietary convention, these bits advertize the + pre-compensation value to be used for backplane media and should + be non-zero if local end knows the nature of the backplane + media. */ + u16_t mii_aneg_nxt_pg_rcv1; /* RW offset 0x0d */ + /* This register shows the value received after the + message page of value 1024 is received when + <b>USE_IEEE</b> is set. */ + #define MII_ANEG_NXT_PG_RCV1_VALUE (0x3ff<<1) /* RW */ + /* The advertized capability of link partner for reserved + BRCM proprietary values. + */ + #define MII_ANEG_NXT_PG_RCV1_2G5 (1<<0) /* RW */ + /* The link partner advertized 2.5G capability by + BRCM proprietary convention. + */ + u16_t mii_aneg_nxt_pg_rcv2; /* RW offset 0x0e */ + /* This register shows the value received after the + <b>auto_nxt_pg_rcv1</b> page is received when + <b>USE_IEEE</b> is set. */ + #define MII_ANEG_NXT_PG_RCV2_VALUE (0x7ff<<0) /* RW */ /* Reset:0 */ + /* By BRCM proprietary convention, bits [3:0] of this value are the + advertized value of pre-emphasis value to be used for backplane + media and should be non-zero if remote end knows the nature of + the backplane media. + Firmware must manually move this value to the <b>PREEMPHASIS</b> + value in 5*0x17 and re-start auto-negotiation with the new + pre-emphasis value in use. + */ + u16_t mii_extend_stat; /* RO offset 0x0f */ + #define MII_EXT_STAT_X_FULL_CAP (1<<15) /* RO */ + /* This bit indicates that the negotiated link is 1000Base-X + full duplex capable. */ + #define MII_EXT_STAT_X_HALF_CAP (1<<14) /* RO */ + /* This bit indicates that the negotiated link is 1000Base-X + half duplex capable. */ + #define MII_EXT_STAT_T_FULL_CAP (1<<13) /* RO */ + /* This bit indicates that the negotiated link is 1000Base-T + full duplex capable. */ + #define MII_EXT_STAT_T_HALF_CAP (1<<12) /* RO */ + /* This bit indicates that the negotiated link is 1000Base-T + half duplex capable. */ + u16_t mii_block[15]; /* RW offset 0x10-0x1e */ + u16_t mii_block_addr; /* RW offset 0x1f */ + #define MII_BLK_ADDR_VALUE (0x1f<<0) /* RW */ /* VALUE: */ + /* Writes to this value set the block address value. */ + #define MII_BLK_ADDR_DIGITAL (0x0<<0) + /* This block value selects the digital register block. */ + /* This block is partially documented in this spec. */ + /* See SERDES documentation for full details on this + register block. */ + #define MII_BLK_ADDR_TEST (0x1<<0) + /* This block value selects the test register block. */ + /* See SERDES documentation for details on this register + block. */ + #define MII_BLK_ADDR_DIGITAL3 (0x2<<0) + /* This block value selects the test register block. */ + /* This block is partially documented in this spec. */ + /* See SERDES documentation for full details on this + register block. */ + #define MII_BLK_ADDR_PLL (0x3<<0) + /* This block value selects the PLL register block. */ + /* See SERDES documentation for details on this register + block. */ + #define MII_BLK_ADDR_RX (0x4<<0) + /* This block value selects the RX register block. */ + /* See SERDES documentation for details on this register + block. */ + #define MII_BLK_ADDR_TXMISC (0x5<<0) + /* This block value selects the TX/Misc register block. */ + /* This block is partially documented in this spec. */ + /* See SERDES documentation for full details on this + register block. */ + +} serdes_reg_t; + + +/* + * DIGITAL Block selected in <b>block</b> section of serdes + * registers when <b>block_addr</b> value is 0. + */ +typedef struct serdes_digital_reg +{ + u16_t mii_1000x_ctl1; /* RW */ + #define MII_1000X_CTL1_MSTR_MDIO_PHY_SEL (1<<13) /* RW */ + /* When set to '1', all MDIO write accesses to PHY address + "00000" will write this PHY in addition to its own PHY + address. */ + #define MII_1000X_CTL1_TX_AMPL_ORIDE (1<<12) /* RW */ + /* When set to '1', the transmit amplitude of the serdes + will com from register 1*10h, bit 14. + When set to '0', the amplitude is selected by fiber or + SGMII mode. */ + #define MII_1000X_CTL1_SEL_RX_PKTS_CNT (1<<11) /* RW */ + /* When set to '1', received packets will be selected for + the 0*17h counter register. */ + #define MII_1000X_CTL1_REM_LOOP (1<<10) /* RW */ + /* When set to '1', remote loopback is enabled. This mode + only operates at gigabit speed. */ + #define MII_1000X_CTL1_ZERO_COMMA_PHASE (1<<9) /* RW */ + /* When set to '1', the comma phase detector is forced to + zero. */ + #define MII_1000X_CTL1_COMMA_DET_EN (1<<8) /* RW */ /* Reset:1 */ + /* When set to '1', the comma detector is enabled. */ + #define MII_1000X_CTL1_CRC_CHK_DIS (1<<7) /* RW */ /* Reset:1 */ + /* When set to '1', the CRC checker is disabled by gating + the clock to that logic to save power. */ + #define MII_1000X_CTL1_PLL_PWR_DWN_DIS (1<<6) /* RW */ /* Reset:0 */ + /* When set to '1', the PLL will never be powered down. + This is used when the MAC/Switch uses the tx_wclk_o + output of the SERDES core. */ + #define MII_1000X_CTL1_SGMII_MSTR (1<<5) /* RW */ /* Reset:0 */ + /* When set to '1', the SGMII mode operates in "PHY mode", + sending out link, speed, and duplex settings from + register 0 of the copper PHY to the SERDES link partner. + */ + #define MII_1000X_CTL1_AUTODET_EN (1<<4) /* RW */ /* Reset:0 */ + /* when set to '1', the PHY will switch between SGMII mode + and fiber mode when an auto-negotiation page is + received with the wrong selector field in bit 0. + When set to '0', selection of fiber/SGMII mode is + controlled by <b>FIBER_MODE</b> bit. */ + #define MII_1000X_CTL1_INV_SIG_DET (1<<3) /* RW */ /* Reset:0 */ + /* When set to '1', the signal detect sense of the signal + detect input is active low, instead of active high. */ + #define MII_1000X_CTL1_SIG_DET_EN (1<<2) /* RW */ /* Reset:1 */ + /* When set to '1', the signal detect input of the chip + must be active to link. In SGMII mode, the signal + detect input is always ignored, regardless of the + setting of this bit. */ + #define MII_1000X_CTL1_TBI_INTF (1<<1) /* RW */ /* Reset:0 */ + /* This bit must always be set to '0' for proper operation + of TetonII. */ + #define MII_1000X_CTL1_FIBER_MODE (1<<0) /* RW */ + /* Reset value of this register is controlled by the + value of <b>serdes_control_reg[12]</b> value in the misc + block. + When this bit is '0', SGMII mode is selected. + When this bit is '1', Fiber mode (Clause 37 mode) is + selected. + Automatic mode selection, overiding this bit's value is + enabled by the <b>AUTONEG_EN</b> bit. */ + u16_t mii_1000x_ctl2; /* RW */ + #define MII_1000X_CTL2_TEST_CNTR (1<<11) /* RW */ /* Reset:0 */ + /* When this bit is '1', the counter at location 0*17h + counts on each clock for testing. */ + #define MII_1000X_CTL2_BYP_PCS_TX (1<<10) /* RW */ /* Reset:0 */ + /* When this bit is '1', the PCS transmit section + is bypassed. */ + #define MII_1000X_CTL2_BYP_PCS_RX (1<<9) /* RW */ /* Reset:0 */ + /* When this bit is '1', the PCS receive section + is bypassed. */ + #define MII_1000X_CTL2_TRRR_GEN_DIS (1<<8) /* RW */ /* Reset:0 */ + /* When this bit is '1', the TRRR generation in the PCS + transmit is disabled. */ + #define MII_1000X_CTL2_CARRIER_EXT_DIS (1<<7) /* RW */ /* Reset:0 */ + /* When this bit is '1', carrier extension in the PCS + receive is disabled. */ + #define MII_1000X_CTL2_FAST_TIMERS (1<<6) /* RW */ /* Reset:0 */ + /* When this bit is '1', timers during auto-negotiation are + sped-up for testing. */ + #define MII_1000X_CTL2_FRCE_XMIT_DATA (1<<5) /* RW */ /* Reset:0 */ + /* When this bit is '1', packets are allowed to transmit + regardless of the condition of link or synchronization. + */ + #define MII_1000X_CTL2_REM_FAULT_SENSE_DIS (1<<4) /* RW */ /* Reset:0 */ + /* When this bit is '1', sensing of remote faults such as + auto-negotiation errors is disabled. + When this bit is '0', SERDES automatically detects + remote faults and sends remote fault status to link + partner via auto-negotiation when fiber mode is + selected. SGMII mode does not support remote faults. */ + #define MII_1000X_CTL2_ANEG_ERR_TMR_EN (1<<3) /* RW */ /* Reset:0 */ + /* When this bit is '1', it enables the auto-negotiation + error timer. Error occurs when timer expires in + ability-detect, ack-detect, or idle-detect. When the + error occurs, config words of all zeros are sent until + an ability match occurs, then the autoneg-enable state + is entered. */ + #define MII_1000X_CTL2_FILTER_FORCE_LINK (1<<2) /* RW */ /* Reset:0 */ + /* When this bit is '1', sync-status must be set for a + solid 10ms before a valid link will be established when + auto-negotiation is disabled. This is useful for fiber + application where the user does not have the signal + detect pin connnection to the fiber module and + auto-negotiation is turned off. */ + #define MII_1000X_CTL2_FLASE_LINK_DIS (1<<1) /* RW */ /* Reset:0 */ + /* When this bit is '1', do not allow link to be + established when auto-negotiation is disabled and + receiving auto-negotiation code words. The link will + only be established in this case after idles are + received. This bit does not need to be set if + <b>PAR_DET_EN</b> is set. */ + #define MII_1000X_CTL2_PAR_DET_EN (1<<0) /* RW */ /* Reset:0 */ + /* Reset value of this register is controlled by the + value of <b>serdes_control_reg[15]</b> value in the misc + block. + When this bit is '1', parallel detection will be + enabled. This will turn auto-negotiation on and off as + needed to properly link up with the link partner. The + idles and auto-negotiation code words received from the + link partner are used to make decision. */ + u16_t mii_1000x_ctl3; /* RW */ + #define MII_1000X_CTL3_DIS_TX_CRS (1<<13) /* RW */ /* Reset:0 */ + /* When this bit is '1', generating CRS from transmitting + in half duplex mode is disabled. Only receiving will + generate CRS. */ + #define MII_1000X_CTL3_INV_EXT_CRS (1<<12) /* RW */ /* Reset:0 */ + /* When this bit is '1', the "receive rcs from PHY" pin + value will be inverted. */ + #define MII_1000X_CTL3_EXT_PHY_CRS (1<<11) /* RW */ /* Reset:0 */ + /* When this bit is '1', use external pin for PHY's + "receive only" CRS output. This is useful in 10/100 + half-duplex applications to reduce the collision domain + latency. This requires a PHY which generates a "receive + only" CRS output to a pin. */ + #define MII_1000X_CTL3_JAM_FALSE (1<<10) /* RW */ /* Reset:0 */ + /* When this bit is '1', change false carriers received + into packets with preamble only. Not necessary if MAC + uses CRS to determine collision. */ + #define MII_1000X_CTL3_BLOCK_TXEN (1<<9) /* RW */ /* Reset:0 */ + /* When this bit is '1', block TXEN when necessary to + guarantee an IPG of at least 6.5 bytes in 10/100 mode + and 7 byte in 1G mode. */ + #define MII_1000X_CTL3_FORCE_TXFIFO_ON (1<<8) /* RW */ /* Reset:0 */ + /* When this bit is '1', force transmit FIFO to free-run in + 1G mode. This requires clk_IN and tx_wclk_o to be + frequency locked. */ + #define MII_1000X_CTL3_BYP_TXFIFO1000 (1<<7) /* RW */ /* Reset:0 */ + /* When this bit is '1', bypass transmit FIFO in 1G mode. + This is useful for fiber or gigabit only applications + where the MAC is using tx_wclk_o as the clk_in port. + MAC must meet timing to the tx_wclk_o domain. */ + #define MII_1000X_CTL3_FREQ_LOCK_ELAST_TX (1<<6) /* RW */ /* Reset:0 */ + /* When this bit is '1', minimum FIFO latency to properly + handle a clock which is frequency locked, but out of + phase. This over-rides bits [2:1] of this register. + Note: tx_wclk_o and clk_in must be using the same + crystal. */ + #define MII_1000X_CTL3_FREQ_LOCK_ELAST_RX (1<<5) /* RW */ /* Reset:0 */ + /* When this bit is '1', minimum FIFO latency to properly + handle a clock which is frequency locked, but out of + phase. Not necessary if MAC users CRS to determine + collision. This over-rides bits [2:1] of this register. + Note: MAC and PHY must be using the same crystal for + this mode to be enabled. */ + #define MII_1000X_CTL3_ERLY_PREAMBLE_RX (1<<4) /* RW */ /* Reset:0 */ + /* When this bit is '1', send extra bytes of preamble to + avoid FIFO latency. Not needed if MAC uses CRS to + determine collision. */ + #define MII_1000X_CTL3_ERLY_PREAMBLE_TX (1<<3) /* RW */ /* Reset:0 */ + /* When this bit is '1', send extra bytes of preamble to + avoid FIFO latency. Uses in half-duplex applications to + reduce collision domain latency. MAC must send 5 bytes + of preamble or less to avoid non-compliant behavior. */ + #define MII_1000X_CTL3_FIFO_ELAST (3<<1) /* RW */ /* Reset:0 */ + #define MII_1000X_CTL3_FIFO_ELAST_5K (0<<1) + /* Supports packets up to 5k bytes. */ + #define MII_1000X_CTL3_FIFO_ELAST_10K (1<<1) + /* Supports packets up to 10k bytes. */ + #define MII_1000X_CTL3_FIFO_ELAST_13K5 (2<<1) + /* Supports packets up to 13.5k bytes. */ + #define MII_1000X_CTL3_TX_FIFO_RXT (1<<0) + /* When this bit is set to '1', the transmit FIFO is reset. + FIFO will remain in reset until this bit is cleared. */ + u16_t mii_reserved1; /* RW */ + u16_t mii_1000x_stat1; /* RO */ + #define MII_1000X_STAT1_TXFIFO_ERR_DET (1<<15) /* AC */ /* Reset:0 */ + /* When this bit is '1', transmit FIFO error has been + detected since last read. */ + #define MII_1000X_STAT1_RXFIFO_ERR_DET (1<<14) /* AC */ /* Reset:0 */ + /* When this bit is '1', receive FIFO error has been + detected since last read. */ + #define MII_1000X_STAT1_FALSE_CARRIER_DET (1<<13) /* AC */ /* Reset:0 */ + /* When this bit is '1', flase carrier has been + detected since last read. */ + #define MII_1000X_STAT1_CRC_ERR_DET (1<<12) /* AC */ /* Reset:0 */ + /* When this bit is '1', CRC error has been detected since + last read. */ + #define MII_1000X_STAT1_TX_ERR_DET (1<<11) /* AC */ /* Reset:0 */ + /* When this bit is '1', a transmit error has been + detected. This indicates tx_data_error_state in PCS + receive FSM has been reached since the last read. */ + #define MII_1000X_STAT1_RX_ERR_DET (1<<10) /* AC */ /* Reset:0 */ + /* When this bit is '1', a receive error has been + detected. This indicates early_end_state in PCS + receive FSM has been reached since the last read. */ + #define MII_1000X_STAT1_CARRIER_EXT_ERR_DET (1<<9) /* AC */ /* Reset:0 */ + /* When this bit is '1', a carrier extend error code has + been detected. This indicates extend_err_state in PCS + receive FSM has been reached since the last read. */ + #define MII_1000X_STAT1_EARLY_END_EXT_ERR_DET (1<<8) /* AC */ /* Reset:0 */ + /* When this bit is '1', a early end extension error code + has been detected. This indicates early_end_ext_state + in PCS receive FSM has been reached since the last + read. */ + #define MII_1000X_STAT1_LINK_STATUS (1<<7) /* RO */ /* Reset:0 */ + /* When this bit is '1', it indicates that link has been up + the entire time since the last read. + This bit latches low until next read and return to '1' + upon read when link is up. */ + #define MII_1000X_STAT1_PAUSE_RX_RESOLVE (1<<6) /* RO */ /* Reset:0 */ + /* This bit will read as '1' when auto-negotiation has + resolved to allow reception of pause frames locally. */ + #define MII_1000X_STAT1_PAUSE_TX_RESOLVE (1<<5) /* RO */ /* Reset:0 */ + /* This bit will read as '1' when auto-negotiation has + resolved to allow transmission of pause frames + locally. */ + #define MII_1000X_STAT1_SPEED (3<<3) /* RO */ /* Reset:0 */ + /* These bits indicate the current speed status. */ + #define MII_1000X_STAT1_SPEED_10 (0<<3) /* 10 MBPS */ + #define MII_1000X_STAT1_SPEED_100 (1<<3) /* 100 MBPS */ + #define MII_1000X_STAT1_SPEED_1G (2<<3) /* 1 GBPS */ + #define MII_1000X_STAT1_SPEED_2G5 (3<<3) /* 2.5 GBPS */ + #define MII_1000X_STAT1_DUPLEX (1<<2) /* RO */ /* Reset:0 */ + /* When this bit is '0', half duplex is enabled. + When this bit is '1', full duplex is enabled. */ + #define MII_1000X_STAT1_LINK (1<<1) /* RO */ /* Reset:0 */ + /* When this bit is '1', the link is up. + When this bit is '0', the link is down. */ + #define MII_1000X_STAT1_SGMII_MODE (1<<0) /* RO */ /* Reset:0 */ + /* When this bit is '1', SGMII mode has been selected. + When this bit is '0', Fiber mode has been selected. */ + u16_t mii_1000x_stat2; /* RW */ + #define MII_1000X_STAT2_SGMII_CHG (1<<15) /* AC */ /* Reset:0 */ + /* When this bit is '1', SGMII mode has changed since the + last read. SGMII mode has been enabled or disabled. + This bit is useful when the auto-detection is enabled + in 0*10h, bit 4. */ + #define MII_1000X_STAT2_CONS_MISMATCH (1<<14) /* AC */ /* Reset:0 */ + /* When this bit is '1', a consistency mismatch has been + detected since the last read. */ + #define MII_1000X_STAT2_ANEG_RES_ERR (1<<13) /* AC */ /* Reset:0 */ + /* When this bit is '1', a auto-negotiation HCD error has + been detected since the last read. */ + #define MII_1000X_STAT2_SGMII_SEL_MISMATCH (1<<12) /* AC */ /* Reset:0 */ + /* When this bit is '1', a SGMII selector mismatch has + been detected since the last read. An auto-negotiation + page has been received from link partner with bit 0 = 0 + while in SGMII mode. */ + #define MII_1000X_STAT2_SYN_STAT_FAIL (1<<11) /* AC */ /* Reset:0 */ + /* When this bit is '1', sync_status has failed since the + last read. Synchronization has been lost. */ + #define MII_1000X_STAT2_SYN_STAT_OK (1<<10) /* AC */ /* Reset:0 */ + /* When this bit is '1', sync_status ok has been detected + since the last read. Synchronization has been achieved. + */ + #define MII_1000X_STAT2_RUDI_C (1<<9) /* AC */ /* Reset:0 */ + /* When this bit is '1', rudi_c has been detected + since the last read. */ + #define MII_1000X_STAT2_RUDI_I (1<<8) /* AC */ /* Reset:0 */ + /* When this bit is '1', rudi_i has been detected + since the last read. */ + #define MII_1000X_STAT2_RUDI_INVALID (1<<7) /* AC */ /* Reset:0 */ + /* When this bit is '1', rudi_invalid has been detected + since the last read. */ + #define MII_1000X_STAT2_AN_SYNC_STAT (1<<6) /* RO */ /* Reset:0 */ + /* When this bit is '1', an_sync_status in auto-negotiation + block has not failed since last read. + When this bit is '0', an_sync_status in auto-negotiation + block has failed since last read. Value sticks at '0' + until read. */ + #define MII_1000X_STAT2_IDLE_DET (1<<5) /* AC */ /* Reset:0 */ + /* When this bit is '1', the idle detect state in + auto-negotiation fsm has been entered since last read. + */ + #define MII_1000X_STAT2_CMPL_ACK (1<<4) /* AC */ /* Reset:0 */ + /* When this bit is '1', the complete acknowledge state in + auto-negotiation fsm has been entered since last read. */ + #define MII_1000X_STAT2_ACK_DET (1<<3) /* AC */ /* Reset:0 */ + /* When this bit is '1', the acknowledge detect state in + auto-negotiation fsm has been entered since last read. */ + #define MII_1000X_STAT2_ABIL_DET (1<<2) /* AC */ /* Reset:0 */ + /* When this bit is '1', the ability detect state in + auto-negotiation fsm has been entered since last read. */ + #define MII_1000X_STAT2_AN_ERR_DET (1<<1) /* AC */ /* Reset:0 */ + /* When <b>ANEG_ERR_TMR_EN</b> is '1' and this bit is '1', + the an_error state in auto-negotiation fsm has been + entered since last read. */ + /* When <b>ANEG_ERR_TMR_EN</b> is '0' and this bit is '1', + the an_disable_link_ok state in auto-negotiation fsm has + been entered since last read. */ + #define MII_1000X_STAT2_AN_EN_DET (1<<0) /* AC */ /* Reset:0 */ + /* When this bit is '1', the an_enable state in + auto-negotiation fsm has been entered since last read. */ + u16_t mii_reserved2[9]; /* RW */ + +} serdes_digital_reg_t; + +/* + * DIGITAL3 Block selected in <b>block</b> section of serdes + * registers when <b>block_addr</b> value is 2. + */ +typedef struct serdes_digital3_reg +{ + u16_t mii_digctl_3_0; /* RW */ + #define MII_DIG3_USE_IEEE (1<<0) /* RW */ /* USE_IEEE: */ + /* When this bit is '0', extended auto-negotiation + capabilities + and results are in digital_3 block registers. + When this bit is '1', extended auto-negotiation + capabilities and results are stored in digital block + registers. */ + u16_t mii_reserved1[14]; /* RW */ + +} serdes_digital3_reg_t; + +/* + * TX/Misc Block selected in <b>block</b> section of serdes + * registers when <b>block_addr</b> value is 5. + */ +typedef struct serdes_tx_misc_reg +{ + u16_t mii_2500status1; /* RW */ + #define MII_2500STAT1_HCDOVER1G (1<<12) /* RW */ + /* When this bit is '1', the HCD is over 1G. */ + #define MII_2500STAT1_HCDOVER1G_STKY (1<<11) /* AC */ + /* When this bit is '1', the HCD has been over 1G since the + last read. */ + #define MII_2500STAT1_BC_REG_RST (1<<10) /* AC */ + /* When this bit is '1', then advertisement of over 1G has + been disabled due to repeated failures to link over 1G + since the last read. */ + #define MII_2500STAT1_COMPLETE (1<<9) /* AC */ + /* 2.5G state machine has reached complete state since last + read. */ + #define MII_2500STAT1_WAIT4LINK (1<<8) /* AC */ + /* 2.5G state machine has reached wait4link state since last + read. */ + #define MII_2500STAT1_PLLSWIT (1<<7) /* AC */ + /* 2.5G state machine has reached pllswit state since last + read. */ + #define MII_2500STAT1_FORCE2500 (1<<6) /* AC */ + /* 2.5G state machine has reached force2500 state since + last read. */ + #define MII_2500STAT1_DEAD (1<<5) /* AC */ + /* 2.5G state machine has reached dead state since + last read. */ + #define MII_2500STAT1_WAIT2RES (1<<4) /* AC */ + /* 2.5G state machine has reached wait2res state since + last read. */ + u16_t mii_reserved1[4]; /* RW */ + + u16_t mii_txactl1; /* RW */ + /* Use read-modify-write procedure for changing this register with + firmware because default values may change from chip version to chip + version, based on foundry, process, etc. */ + #define MII_TXACTL1_DRIVER_VCM (0x3<<4) /* RW */ + /* Reset:1 */ + #define MII_TXACTL1_PREEMPHASIS_PRE (0x7<<6) /* RW */ + #define MII_TXACTL1_DRIVEMODE (0x1<<9) /* RW */ + #define MII_TXACTL1_TX_TDATAEN (0x1<<10) /* RW */ + #define MII_TXACTL1_REFH_TX (0x1<<11) /* RW */ + #define MII_TXACTL1_REFL_TX (0x1<<12) /* RW */ + #define MII_TXACTL1_ID2C_2 (0x1<<13) /* RW */ + /* Bits [2] of ID2C. */ + + u16_t mii_reserved2; /* RW */ + + u16_t mii_txactl3; /* RW */ + /* Use read-modify-write procedure for changing this register with + firmware because default values may change from chip version to chip + version, based on foundry, process, etc. */ + #define MII_TXACTL3_PREEMPHASIS (0xf<<12) /* RW */ + /* This value controls transmitter pre-emphasis. + Value is A where pre-emphasis=A/(40-A). For example, if + register is set to 0x1, then pre-empasis co-efficient + is 1/(40-1)=0.025 or 1/39th of main tap current. */ + /* This value is bit flipped such that the value is [0:3] + within the field. */ + #define MII_TXACTL3_IDRIVER (0xf<<8) /* RW */ /* Reset:0xe */ + /* This value is bit flipped such that the value is [0:3] + within the field. */ + #define MII_TXACTL3_IPREDRIVER (0xf<<4) /* RW */ /* Reset:0x9 */ + /* This value is bit flipped such that the value is [0:3] + within the field. */ + #define MII_TXACTL3_IFULLSPD (0x7<<1) /* RW */ /* Reset:0 */ + /* This value is bit flipped such that the value is [0:2] + within the field. */ + #define MII_TXACTL3_ICBUF1T (0x1<<0) /* RW */ /* Reset:0 */ + + u16_t mii_reserved3[7]; /* RW */ + +} serdes_tx_misc_reg_t; + +#endif /* _serdes_h_ */ + +/**************************************************************************** + * End of file + ****************************************************************************/ + diff --git a/usr/src/uts/common/io/bnx/570x/common/include/shmem.h b/usr/src/uts/common/io/bnx/570x/common/include/shmem.h new file mode 100644 index 0000000000..db4a4c662f --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/shmem.h @@ -0,0 +1,881 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _SHMEM_H +#define _SHMEM_H + +#include "bcmtype.h" +#include "5706_reg.h" +#include "license.h" + + + +/* This structure will be located at the beginning of the MCP scratchpad. + * All firmwares need to be compiled to specify a starting address + * (> 0x08000010). + */ +typedef struct _shm_hdr_t +{ + u32_t shm_hdr_signature; + #define SHM_ADDR_SIGN_MASK 0xffff0000 + #define SHM_ADDR_SIGNATURE 0x53530000 + /* The dword count is meaningful only for version 0x2 or after */ + #define SHM_ADDR_DWORD_SIZE_MASK 0xff00 + #define SHM_ADDR_HDR_VER_MASK 0xff + #define SHM_ADDR_HDR_CURR_VER 0x1 + #define SHM_ADDR_HDR_FIXED_LEN_VER 0x1 /* version 0 & 1 uses fixed length of SHM_ADDR_HDR_FIXED_LEN_SIZE (0x10) */ + #define SHM_ADDR_HDR_FIXED_LEN_SIZE 0x10 + u32_t shm_addr[2]; + /* The address value is the host view address. The first one is + * for primary port, and the second one is for the secondary + * port (applicable in Xinan). We don't know if the shared + * memory will be part of the MCP scratchpad, thus, it is safer + * to show the host view and let firmware to calculate the CPU + * view. + */ + u32_t reserved; +} shm_hdr_t; + + + +/* This value (in milliseconds) determines the frequency of the driver + * issuing the PULSE message code. The firmware monitors this periodic + * pulse to determine when to switch to an OS-absent mode. */ +#define DRV_PULSE_PERIOD_MS 250 + +/* This value (in milliseconds) determines how long the driver should + * wait for an acknowledgement from the firmware before timing out. Once + * the firmware has timed out, the driver will assume there is no firmware + * running and there won't be any firmware-driver synchronization during a + * driver reset. */ +#define FW_ACK_TIME_OUT_MS 50 + +/* This value (in usec) is the period before which the BIOS can ask us + * to disassociate the primary MAC address when checking on license. The + * entire handshake must be complete within this time. */ +#define HWKEY_SKIP_MAC_TIMEOUT_US 10000000 /* OEM specific */ + + +typedef struct _drv_fw_mb_t +{ + u32_t drv_reset_signature; + #define DRV_RESET_SIGNATURE 0x47495352 + #define BIOS_SIGNATURE 0x534f4942 + /* During BIOS POST, this field will also be used for handshake + * of challenge-response with the BIOS to confirm its intent. + * The details of the challenge-response is defined in the + * implementation. */ + + u32_t drv_mb; + #define DRV_MSG_CODE 0xff000000 + #define DRV_MSG_CODE_RESET 0x01000000 + #define DRV_MSG_CODE_UNLOAD 0x02000000 + #define DRV_MSG_CODE_SHUTDOWN 0x03000000 + #define DRV_MSG_CODE_SUSPEND_WOL 0x04000000 + #define DRV_MSG_CODE_FW_TIMEOUT 0x05000000 + #define DRV_MSG_CODE_UNUSED 0x06000000 + #define DRV_MSG_CODE_DIAG 0x07000000 + #define DRV_MSG_CODE_VALIDATE_KEY 0x08000000 + #define DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 + #define DRV_MSG_CODE_GET_CURR_KEY 0x0a000000 + #define DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000 + #define DRV_MSG_CODE_FIO_ACCESS 0x0c000000 + #define DRV_MSG_CODE_KEEP_VLAN_UPDATE 0x0d000000 + #define DRV_MSG_CODE_CMD_SET_LINK 0x10000000 + #define DRV_MSG_CODE_CMD_REMOTE_PHY_MDIO 0x40000000 + #define BIOS_MSG_CODE_HANDSHAKE 0xff000000 /* OEM specific */ + + #define DRV_MSG_DATA 0x00ff0000 + #define DRV_MSG_DATA_WAIT0 0x00010000 + #define DRV_MSG_DATA_WAIT1 0x00020000 + #define DRV_MSG_DATA_WAIT2 0x00030000 + #define DRV_MSG_DATA_WAIT3 0x00040000 + #define DRV_MSG_DATA_WAIT_RESET 0x00050000 + #define DRV_MSG_DATA_WAIT4 0x00060000 + /* Used by DRV_MSG_CODE_VALIDATE_KEY command */ + #define DRV_MSG_DATA_MANUF_KEY 0x00010000 + #define DRV_MSG_DATA_UPGRADE_KEY 0x00020000 + /* Used by BIOS_MSG_CODE_HANDSHAKE command */ + #define BIOS_MSG_DATA_REQ 0x00010000 /* OEM specific */ + #define BIOS_MSG_DATA_CONFIRM 0x00020000 /* OEM specific */ + /* Used by BIOS_MSG_CODE_HANDSHAKE command and... + The VIRT_*_MAC command requires two arguments in mb_args[]. + The top 16 bit of the first argument needs to be + VIRT_MAC_SIGNATURE. The remaining six bytes (two from first + argument, four from the second one) will be the MAC address. + However, if all F's are used as MAC, boot code will treat + this as reverting back to the original MAC in the NVRAM. + */ + #define BIOS_MSG_DATA_USE_VIRT_PRIM_MAC 0x00030000 /* OEM specific */ + #define BIOS_MSG_DATA_USE_VIRT_ISCSI_MAC 0x00040000 /* OEM specific */ + /* Used by DRV_MSG_CODE_FIO_ACCESS command */ + #define DRV_MSG_DATA_FIO_READ 0x00000000 + #define DRV_MSG_DATA_FIO_WRITE 0x00010000 + + #define DRV_MSG_SEQ 0x0000ffff + + u32_t fw_mb; + #define FW_SIGN_PRESERVE_MEMORY 0x55aa5a5a + #define FW_MSG_ACK 0x0000ffff + #define FW_MSG_STATUS_MASK 0x00ff0000 + #define FW_MSG_STATUS_OK 0x00000000 + #define FW_MSG_STATUS_FAILURE 0x00ff0000 + #define FW_MSG_STATUS_INVALID_ARGS 0x00010000 + #define FW_MSG_STATUS_DRV_PRSNT 0x00020000 + /* This "signature" is used to preserve memory content from + * the hard reset issued by the boot code. + */ + + u32_t link_status; + /* See netlink.h for bit definitions */ + #define FW_LINK_STATUS_BUSY 0x0005A000 + #define FW_LINK_STATUS_CABLE_SENSE_MASK 0x40000000 + #define FW_LINK_STATUS_SW_TIMER_EVENT_MASK 0x80000000 + + u32_t drv_pulse_mb; + #define DRV_PULSE_SEQ_MASK 0x00007fff + #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 + /* The system time is in the format of + * (year-2001)*12*32 + month*32 + day. */ + #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 + /* Indicate to the firmware not to go into the + * OS absent when it is not getting driver pulse. + * This is used for debugging as well for PXE(MBA). */ + + u32_t mb_args[2]; + /* This can be used to pass arguments to handshake with + * firmware. */ + + u32_t reserved[1]; +} drv_fw_mb_t; + + + +typedef struct _shared_hw_cfg_t +{ + u8_t part_num[16]; /* Up to 16 bytes of NULL-terminated string */ + u32_t power_dissipated; + #define SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 + #define SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 + #define SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 + #define SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff + u32_t power_consumed; + u32_t config; + #define SHARED_HW_CFG_DESIGN_NIC 0 + #define SHARED_HW_CFG_DESIGN_LOM 0x1 + #define SHARED_HW_CFG_PORT_SWAP 0x2 /* Xinan only */ + #define SHARED_HW_CFG_VAUX_OVERDRAW 0x4 + #define SHARED_HW_CFG_UMP_USE_MII 0 /* TetonII */ + #define SHARED_HW_CFG_UMP_USE_RMII 0x8 /* TetonII */ + #define SHARED_HW_CFG_WOL_ENABLE_BEACON 0x10 /* TetonII, on by hw default */ + #define SHARED_HW_CFG_PHY_FIBER_2_5G 0x20 /* TetonII/Xinan, off (1G only) by default */ + #define SHARED_HW_CFG_BACKPLANE_APP 0x40 /* TetonII/Xinan fiber */ + #define SHARED_HW_CFG_CRS_DV_SRC_SELECT_RXDV 0 + #define SHARED_HW_CFG_CRS_DV_SRC_SELECT_CRS 0x80 /* TetonII B0 and after */ + #define SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 /* Teton/TetonII only */ + #define SHARED_HW_CFG_LED_MODE_MASK 0x700 /* Teton/TetonII only */ + #define SHARED_HW_CFG_LED_MODE_MAC 0 /* Teton/TetonII only */ + #define SHARED_HW_CFG_LED_MODE_GPHY1 0x100 /* Teton/TetonII only */ + #define SHARED_HW_CFG_LED_MODE_GPHY2 0x200 /* Teton/TetonII only */ + #define SHARED_HW_CFG_LED_MODE_GPHY3 0x300 /* Teton/TetonII only */ + #define SHARED_HW_CFG_LED_MODE_GPHY4 0x400 /* Teton/TetonII only */ + #define SHARED_HW_CFG_LED_MODE_GPHY5 0x500 /* Teton/TetonII only */ + #define SHARED_HW_CFG_LED_MODE_GPHY6 0x600 /* Teton/TetonII only */ + #define SHARED_HW_CFG_LED_MODE_GPHY7 0x700 /* Teton/TetonII only */ + #define SHARED_HW_CFG_UMP_PHY_TIMING_ENABLE 0x800 /* TetonII B0 and after */ + #define SHARED_HW_CFG_UMP_PHY_TIMING_DISABLE 0 /* TetonII B0 and after */ + /* Select a GPIO to determine what mgmt fw to run, GPIO1 for ignore */ + #define SHARED_HW_CFG_MFW_CHOICE_SHIFT_BITS 12 + #define SHARED_HW_CFG_MFW_CHOICE_GPIO_MASK 0x7000 /* Teton/TetonII only */ + #define SHARED_HW_CFG_MFW_CHOICE_IGNORE 0x0000 /* Teton/TetonII only */ + #define SHARED_HW_CFG_MFW_CHOICE_UNUSED1 0x1000 /* Teton/TetonII only */ + #define SHARED_HW_CFG_MFW_CHOICE_UNUSED2 0x2000 /* Teton/TetonII only */ + #define SHARED_HW_CFG_MFW_CHOICE_GPIO3 0x3000 /* Teton/TetonII only */ + #define SHARED_HW_CFG_MFW_CHOICE_GPIO4 0x4000 /* Teton/TetonII only */ + #define SHARED_HW_CFG_MFW_CHOICE_GPIO5 0x5000 /* Teton/TetonII only */ + #define SHARED_HW_CFG_MFW_CHOICE_GPIO6 0x6000 /* Teton/TetonII only */ + #define SHARED_HW_CFG_MFW_CHOICE_GPIO7 0x7000 /* Teton/TetonII only */ + #define SHARED_HW_CFG_MFW_CHOICE_MASK 0x7000 /* Xinan only */ + #define SHARED_HW_CFG_MFW_CHOICE_ANY 0x0000 /* Xinan only */ + #define SHARED_HW_CFG_MFW_CHOICE_NCSI 0x1000 /* Xinan only */ + #define SHARED_HW_CFG_MFW_CHOICE_UMP 0x2000 /* Xinan only */ + #define SHARED_HW_CFG_MFW_CHOICE_IPMI 0x3000 /* Xinan only */ + #define SHARED_HW_CFG_MFW_CHOICE_SPIO4_NCSI0_IPMI1 0x4000 /* Xinan only */ + #define SHARED_HW_CFG_MFW_CHOICE_SPIO4_UMP0_IPMI1 0x5000 /* Xinan only */ + #define SHARED_HW_CFG_MFW_CHOICE_SPIO4_NCSI0_UMP1 0x6000 /* Xinan only */ + #define SHARED_HW_CFG_MFW_CHOICE_RESERVED 0x7000 /* Xinan only */ + #define SHARED_HW_CFG_GIG_LINK_ON_VAUX 0x8000 + #define SHARED_HW_CFG_LED_APP_MASK 0x30000 /* TetonII fiber (A0 and B0) only */ + #define SHARED_HW_CFG_LED_APP_INDEPENDENT 0x00000 /* TetonII fiber (A0 and B0) only */ + #define SHARED_HW_CFG_LED_APP_MULTI_COLOR 0x10000 /* TetonII fiber (A0 and B0) only */ + #define SHARED_HW_CFG_LED_APP_ALL_TIED 0x20000 /* TetonII fiber (A0 and B0) only */ + #define SHARED_HW_CFG_DUAL_MAC_MASK 0x30000 /* Xinan only */ + #define SHARED_HW_CFG_DUAL_MAC_BOTH 0x00000 /* Xinan only */ + #define SHARED_HW_CFG_DUAL_MAC_RESERVED 0x10000 /* Xinan only */ + #define SHARED_HW_CFG_DUAL_MAC_HIDE_FN1 0x20000 /* Xinan only */ + #define SHARED_HW_CFG_DUAL_MAC_INVALID 0x30000 /* Xinan only */ + #define SHARED_HW_CFG_PCIE_GEN2_ENABLE 0x40000 /* Xinan only */ + #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x0 /* Xinan only */ + #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x80000 /* Xinan only */ + #define SHARED_HW_CFG_PREVENT_PCIE_L1_ENTRY 0x100000 /* Xinan only */ + #define SHARED_HW_CFG_DUAL_MEDIA_CFG_MASK 0xe00000 /* Xinan only: reserved for future support */ + #define SHARED_HW_CFG_NO_LINK_FLAP 0x1000000 /* Xinan copper AN only */ + #define SHARED_HW_CFG_DUAL_MEDIA_OVERRIDE 0x2000000 /* Xinan only: reserved for future support */ + #define SHARED_HW_CFG_GEN2_TX_PREEMP_MASK 0xf0000000 /* Xinan only */ + #define SHARED_HW_CFG_GEN2_TX_PREEMP_HW 0x00000000 /* Xinan only: HW and 0_0DB are swapped in hw register */ + #define SHARED_HW_CFG_GEN2_TX_PREEMP_0_0DB 0xc0000000 /* Xinan only: HW and 0_0DB are swapped in hw register */ + #define SHARED_HW_CFG_GEN2_TX_PREEMP_3_5DB 0xa0000000 /* Xinan only */ + #define SHARED_HW_CFG_GEN2_TX_PREEMP_6_0DB 0xe0000000 /* Xinan only */ + u32_t config2; + #define SHARED_HW_CFG2_NVM_SIZE_MASK 0xfff000 + u32_t shared_eco_ctl; + /* The bit definitions below are for TetonII only */ + #define SHARED_ECO_CTL_ECO203_EPB_0x78_BIT02 0x4 + #define SHARED_ECO_CTL_ECO204_EPB_0x78_BIT31 0x80000000 + #define SHARED_ECO_CTL_ECO206_EPB_0x78_BIT03 0x8 + #define SHARED_ECO_CTL_ECO207_EPB_0x48_BIT24 0x100 /* Need to shift 16 bits to left */ + #define SHARED_ECO_CTL_EPB_0x48_SHIFT_BITS 16 /* Need to shift 16 bits to left */ + #define SHARED_ECO_CTL_ECO208_EPB_0x7C_BIT30 0x40000000 + #define SHARED_ECO_CTL_ECO209_EPB_0x7C_BIT24 0x1000000 + #define SHARED_ECO_CTL_ECO210_EPB_0x78_BIT26 0x4000000 + #define SHARED_ECO_CTL_EPB_0x78_MASK (SHARED_ECO_CTL_ECO203_EPB_0x78_BIT02 | \ + SHARED_ECO_CTL_ECO206_EPB_0x78_BIT03 | \ + SHARED_ECO_CTL_ECO210_EPB_0x78_BIT26 | \ + SHARED_ECO_CTL_ECO204_EPB_0x78_BIT31) + #define SHARED_ECO_CTL_EPB_0x7C_MASK (SHARED_ECO_CTL_ECO209_EPB_0x7C_BIT24 | \ + SHARED_ECO_CTL_ECO208_EPB_0x7C_BIT30) + #define SHARED_ECO_CTL_EPB_0x48_MASK (SHARED_ECO_CTL_ECO207_EPB_0x48_BIT24) + u32_t reserved[1]; /* Any common info to all ports */ +} shared_hw_cfg_t; + + + + +#define PORT_HW_CFG_RESERVED_WORD_CNT 6 +typedef struct _port_hw_cfg_t +{ + /* Fields below are port specific (in anticipation of dual port devices */ + u32_t mac_upper; + #define PORT_HW_CFG_UPPERMAC_MASK 0xffff + u32_t mac_lower; + u32_t config; + #define PORT_HW_CFG_SERDES_TXCTL3_MASK 0xffff + #define PORT_HW_CFG_DEFAULT_LINK_MASK 0x1f0000 + #define PORT_HW_CFG_DEFAULT_LINK_AN 0x0 + #define PORT_HW_CFG_DEFAULT_LINK_SPEED_MASK 0x070000 + #define PORT_HW_CFG_DEFAULT_LINK_1G 0x030000 + #define PORT_HW_CFG_DEFAULT_LINK_2_5G 0x040000 + #define PORT_HW_CFG_DEFAULT_LINK_AN_FALLBACK_MASK 0x100000 + #define PORT_HW_CFG_DEFAULT_LINK_AN_1G_FALLBACK 0x130000 + #define PORT_HW_CFG_DEFAULT_LINK_AN_2_5G_FALLBACK 0x140000 + #define PORT_HW_CFG_DISABLE_PCIE_RELAX_ORDER 0x200000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_MASK 0x0f000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_MAC 0x00000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_PHY1 0x01000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_PHY2 0x02000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_PHY3 0x03000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_MAC2 0x04000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_PHY4 0x05000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_PHY5 0x06000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_PHY6 0x07000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_MAC3 0x08000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_PHY7 0x09000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_PHY8 0x0a000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_PHY9 0x0b000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_MAC4 0x0c000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_PHY10 0x0d000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_PHY11 0x0e000000 /* Xinan only */ + #define PORT_HW_CFG_XI_LED_MODE_UNUSED 0x0f000000 /* Xinan only */ + u32_t l2_reserved[5]; + u32_t pci_id; /* Xinan only */ + #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 + #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0ffff + u32_t pci_sub_id; /* Xinan only */ + #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 + #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0ffff + u32_t iscsi_mac_upper; /* Upper 16 bits are always zeroes */ + u32_t iscsi_mac_lower; + u32_t backup_l2_mac_upper; /* Upper 16 bits are reserved, could be... */ + u32_t backup_l2_mac_lower; /* non-zeroes, used by OEM software (BIOS?) */ + u32_t port_eco_ctl; + + /* The reserved fields must have values of 0 */ + /* Reserving fields for L4, L5, and iSCSI config for a specific port. */ + u32_t reserved[PORT_HW_CFG_RESERVED_WORD_CNT]; + +} port_hw_cfg_t; + + +typedef struct _shared_feat_cfg_t +{ + u32_t config; /* Any features common to all ports */ + #define SHARED_FEATURE_ENABLE_ISCSI_OFLD 0x1 /* For Linux of one OEM */ + #define SHARED_FEATURE_RESERVED_MASK 0xfffffffe + u32_t reserved[3]; +} shared_feat_cfg_t; + + +typedef struct _res_alloc_t +{ + u32_t version; + #define RES_VER_STRING 'A' + #define RES_VER_STRING_MASK 0xff000000 + #define RES_VER_STRING_SHIFT_BITS 24 + /* These bits are maintained by BACS, no other SW/FW entity + * should manipulate them. They are consumed by TOE/iSCSI FW. */ + #define RES_RES_CFG_TOE_IPV6 (0x1 << 0) + #define RES_RES_CFG_ISCSI_IPV6 (0x1 << 1) + + u32_t res_cfg; + /* Used for the users to decide what they want */ + #define RES_RES_CFG_VALID 0x01 + /* Overloading with VPD FDO, should be okay. */ + #define RES_RES_CFG_DIAG 0x02 + #define RES_RES_CFG_L2 0x04 + #define RES_RES_CFG_ISCSI 0x08 + #define RES_RES_CFG_RDMA 0x10 + #define RES_RES_CFG_FCFS_DISABLED 0x80000000UL + u32_t enum_val; + /* Used for the base driver to figure out what to enumerate */ + #define RES_ENUM_VALID RES_RES_CFG_VALID + #define RES_ENUM_VAL_DIAG RES_RES_CFG_DIAG + #define RES_ENUM_VAL_L2 RES_RES_CFG_L2 + #define RES_ENUM_VAL_ISCSI RES_RES_CFG_ISCSI + #define RES_ENUM_VAL_RDMA RES_RES_CFG_RDMA + #define RES_ENUM_VAL_UNUSED RES_RES_CFG_FCFS_DISABLED + + u32_t conn_resource1; + #define RES_CONN_RDMA_MASK 0xffff0000 + #define RES_CONN_TOE_MASK 0xffff + u32_t conn_resource2; + #define RES_CONN_ISCSI_MASK 0xffff0000 + #define RES_CONN_ISER_MASK 0xffff + u32_t conn_resource3; + #define RES_CONN_UNUSED 0xffff0000 + /* iSCSI pending tasks: range from 32 to 2048, relevent when + * RES_RES_CFG_ISCSI flag is set. */ + #define RES_CONN_ISCSI_PTASK_MASK 0xffff + u32_t conn_resource4; + +} res_alloc_t; + + +#define PORT_FEAT_CFG_RESERVED_WORD_CNT 14 +typedef struct _port_feat_cfg_t +{ + u32_t config; + #define PORT_FEATURE_FORCE_EXPROM_ENABLED 0x00800000 + #define PORT_FEATURE_WOL_ENABLED 0x01000000 + #define PORT_FEATURE_MBA_ENABLED 0x02000000 + #define PORT_FEATURE_MFW_ENABLED 0x04000000 + #define PORT_FEATURE_RPHY_ENABLED 0x08000000 + #define PORT_FEATURE_PCIE_CAPABILITY_MASK 0xf0 /* Xinan only */ + #define PORT_FEATURE_PCIE_CAPABILITY_ALL 0xf0 /* Xinan only */ + #define PORT_FEATURE_PCIE_CAPABILITY_ALL_DEF 0x0 /* Xinan only */ + #define PORT_FEATURE_BAR1_SIZE_MASK 0xf + #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 + #define PORT_FEATURE_BAR1_SIZE_64K 0x1 + #define PORT_FEATURE_BAR1_SIZE_128K 0x2 + #define PORT_FEATURE_BAR1_SIZE_256K 0x3 + #define PORT_FEATURE_BAR1_SIZE_512K 0x4 + #define PORT_FEATURE_BAR1_SIZE_1M 0x5 + #define PORT_FEATURE_BAR1_SIZE_2M 0x6 + #define PORT_FEATURE_BAR1_SIZE_4M 0x7 + #define PORT_FEATURE_BAR1_SIZE_8M 0x8 + #define PORT_FEATURE_BAR1_SIZE_16M 0x9 + #define PORT_FEATURE_BAR1_SIZE_32M 0xa + #define PORT_FEATURE_BAR1_SIZE_64M 0xb + #define PORT_FEATURE_BAR1_SIZE_128M 0xc + #define PORT_FEATURE_BAR1_SIZE_256M 0xd + #define PORT_FEATURE_BAR1_SIZE_512M 0xe + #define PORT_FEATURE_BAR1_SIZE_1G 0xf + u32_t wol_config; + /* Default is used when driver sets to "auto" mode */ + #define FEATURE_WOL_DEFAULT_SHIFT_BITS 4 + #define FEATURE_WOL_DEFAULT_MASK 0x30 + #define FEATURE_WOL_DEFAULT_DISABLE 0 + #define FEATURE_WOL_DEFAULT_MAGIC 0x10 + #define FEATURE_WOL_DEFAULT_ACPI 0x20 + #define FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 + #define FEATURE_WOL_LINK_SPEED_MASK 0xf + #define FEATURE_WOL_LINK_SPEED_AUTONEG 0 + #define FEATURE_WOL_LINK_SPEED_10HALF 1 + #define FEATURE_WOL_LINK_SPEED_10FULL 2 + #define FEATURE_WOL_LINK_SPEED_100HALF 3 + #define FEATURE_WOL_LINK_SPEED_100FULL 4 + #define FEATURE_WOL_LINK_SPEED_1000HALF 5 + #define FEATURE_WOL_LINK_SPEED_1000FULL 6 + #define FEATURE_WOL_LINK_SPEED_2500HALF 7 + #define FEATURE_WOL_LINK_SPEED_2500FULL 8 + #define FEATURE_WOL_AUTONEG_LIMIT_MASK 0xc0 + #define FEATURE_WOL_AUTONEG_LIMIT_10 0x80 + #define FEATURE_WOL_AUTONEG_LIMIT_100 0x00 + #define FEATURE_WOL_AUTONEG_LIMIT_1000 0x40 + #define FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 + #define FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 + #define FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 + u32_t mba_config; + #define FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 + #define FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS2 20 + #define FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x400003 + #define FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 + #define FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 + #define FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 + #define FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 3 + #define FEATURE_MBA_BOOT_AGENT_TYPE_FCOE 0x400000 + #define FEATURE_MBA_BOOT_AGENT_TYPE_RESERVED_1 0x400001 + #define FEATURE_MBA_BOOT_AGENT_TYPE_RESERVED_2 0x400002 + #define FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x400003 + #define FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 + #define FEATURE_MBA_LINK_SPEED_MASK 0x3c + #define FEATURE_MBA_LINK_SPEED_AUTONEG 0 + #define FEATURE_MBA_LINK_SPEED_10HALF 0x4 + #define FEATURE_MBA_LINK_SPEED_10FULL 0x8 + #define FEATURE_MBA_LINK_SPEED_100HALF 0xc + #define FEATURE_MBA_LINK_SPEED_100FULL 0x10 + #define FEATURE_MBA_LINK_SPEED_1000HALF 0x14 + #define FEATURE_MBA_LINK_SPEED_1000FULL 0x18 + #define FEATURE_MBA_LINK_SPEED_2500HALF 0x1c + #define FEATURE_MBA_LINK_SPEED_2500FULL 0x20 + #define FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 + #define FEATURE_MBA_HOTKEY_CTRL_S 0 + #define FEATURE_MBA_HOTKEY_CTRL_B 0x80 + #define FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 + #define FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 + #define FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 + #define FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 + #define FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 + #define FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 + #define FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 + #define FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 + #define FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 + #define FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 + #define FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 + #define FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 + #define FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 + #define FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 + #define FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 + #define FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 + #define FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 + #define FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 + #define FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 + #define FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 + #define FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 + #define FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 + #define FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 + #define FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 + #define FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 + #define FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 + #define FEATURE_MBA_BOOT_RETRY_MASK 0x3800000 /* bit 25 24 23*/ + #define FEATURE_MBA_BOOT_RETRY_SHIFT_BITS 23 + u32_t bmc_common; + #define FEATURE_BMC_CMN_UNUSED_0 0x1 /* Used to be link override */ + #define FEATURE_BMC_CMN_ECHO_MODE_ENABLE 0x2 + #define FEATURE_BMC_CMN_UNUSED_2 0x4 + #define FEATURE_BMC_CMN_UMP_ID_ENABLE 0x8 /* Xinan only */ + #define FEATURE_BMC_CMN_UMP_ID_MASK 0x30 /* Xinan only */ + u32_t mba_vlan_cfg; + #define FEATURE_MBA_VLAN_TAG_MASK 0xffffL + #define FEATURE_MBA_VLAN_ENABLE 0x10000L + + res_alloc_t resource; + + u32_t smbus_config; + #define FEATURE_SMBUS_ENABLE 1 /* Obsolete */ + #define FEATURE_SMBUS_ADDR_MASK 0xfe + + u32_t iscsib_basic_config; + #define FEATURE_ISCSIB_SKIP_TARGET_BOOT 1 + + union u_t + { + u32_t t2_epb_cfg; + #define T2_EPB_CFG_ENABLED 0x80000000 + #define T2_EPB_CFG_OPT_L23 0x40000000 + #define T2_EPB_CFG_OPT_NIC_D3 0x20000000 + #define T2_EPB_CFG_OPT_INACTIVITY_CHK 0x10000000 + #define T2_EPB_CFG_OPT_ACTIVITY_CHK 0x8000000 + #define T2_EPB_CFG_OPT_PREP_L23 0x4000000 + #define T2_EPB_CFG_IDLE_TMR_MS_MASK 0xffff + #define T2_EPB_FORCED_L1_VALUE 0xd8000bb8 +#ifdef SOLARIS + } u1; +#else + } u; +#endif + + u32_t reserved[PORT_FEAT_CFG_RESERVED_WORD_CNT]; + +} port_feat_cfg_t; + + + +#ifdef SOLARIS +typedef struct _bnx2shm_dev_info_t +#else +typedef struct _dev_info_t +#endif +{ + u32_t signature; + #define DEV_INFO_SIGNATURE_MASK 0xffffff00 + #define DEV_INFO_SIGNATURE 0x44564900 + #define DEV_INFO_FEATURE_CFG_VALID 0x01 + #define DEV_INFO_KEY_IN_EFFECT_MASK 0x06 + #define DEV_INFO_MANUF_KEY_IN_EFFECT 0x02 + #define DEV_INFO_UPGRADE_KEY_IN_EFFECT 0x04 + #define DEV_INFO_NO_KEY_IN_EFFECT 0x06 + #define DEV_INFO_DRV_ALWAYS_ALIVE 0x40 + //#define DEV_INFO_SECONDARY_PORT 0x80 + + shared_hw_cfg_t shared_hw_config; + + u32_t bc_rev; /* 8 bits each: Major, minor, build, 0x05 */ + + port_hw_cfg_t port_hw_config; + + u32_t virt_prim_mac_upper; /* Upper 16 bits are a signature */ + #define VIRT_MAC_SIGN_MASK 0xffff0000 + #define VIRT_MAC_SIGNATURE 0x564d0000 + u32_t virt_prim_mac_lower; + u32_t virt_iscsi_mac_upper; /* Upper 16 bits are a signature */ + u32_t virt_iscsi_mac_lower; + u32_t unused_a[4]; + + /* Format revision: applies to shared and port features */ + u32_t format_rev; + #define FEATURE_FORMAT_REV_MASK 0xff000000 + #define FEATURE_FORMAT_REV_ID ('A' << 24) + shared_feat_cfg_t shared_feature_config; + port_feat_cfg_t port_feature_config; + + u32_t mfw_ver_ptr; + /* Valid only when mgmt FW is loaded (see CONDITION_MFW_RUN_MASK field). */ + #define MFW_VER_PTR_MASK 0x00ffffff + u32_t inv_table_ptr; + /* This is a scratchpad address for mgmt FW to use. */ + u32_t unused_b[(sizeof(port_feat_cfg_t))/4 - 2]; + +#ifdef SOLARIS +} bnx2shm_dev_info_t; +#else +} dev_info_t; +#endif + + + +typedef struct _bc_state_t +{ + u32_t reset_type; + #define RESET_TYPE_SIGNATURE_MASK 0x0000ffff + #define RESET_TYPE_SIGNATURE 0x00005254 + #define RESET_TYPE_NONE (RESET_TYPE_SIGNATURE |\ + 0x00010000) + #define RESET_TYPE_PCI (RESET_TYPE_SIGNATURE |\ + 0x00020000) + #define RESET_TYPE_VAUX (RESET_TYPE_SIGNATURE |\ + 0x00030000) + #define RESET_TYPE_DRV_MASK DRV_MSG_CODE + #define RESET_TYPE_DRV_RESET (RESET_TYPE_SIGNATURE |\ + DRV_MSG_CODE_RESET) + #define RESET_TYPE_DRV_UNLOAD (RESET_TYPE_SIGNATURE |\ + DRV_MSG_CODE_UNLOAD) + #define RESET_TYPE_DRV_SHUTDOWN (RESET_TYPE_SIGNATURE |\ + DRV_MSG_CODE_SHUTDOWN) + #define RESET_TYPE_DRV_SUSPEND_NO_WOL (RESET_TYPE_SIGNATURE |\ + DRV_MSG_CODE_SUSPEND_NO_WOL) + #define RESET_TYPE_DRV_SUSPEND_WOL (RESET_TYPE_SIGNATURE |\ + DRV_MSG_CODE_SUSPEND_WOL) + #define RESET_TYPE_DRV_FW_TIMEOUT (RESET_TYPE_SIGNATURE |\ + DRV_MSG_CODE_FW_TIMEOUT) + #define RESET_TYPE_DRV_DIAG (RESET_TYPE_SIGNATURE |\ + DRV_MSG_CODE_DIAG) + #define RESET_TYPE_DRV_UNLOAD_LNK_DN (RESET_TYPE_SIGNATURE |\ + DRV_MSG_CODE_UNLOAD_LNK_DN) + #define RESET_TYPE_VALUE(msg_code) (RESET_TYPE_SIGNATURE |\ + (msg_code)) + u32_t state; + #define BC_STATE_ERR_MASK 0x0000ff00 + #define BC_STATE_SIGN_MASK 0xffff0000 + #define BC_STATE_SIGN 0x42530000 + #define BC_STATE_BC1_START (BC_STATE_SIGN | 0x1) /* not used */ + #define BC_STATE_GET_NVM_CFG1 (BC_STATE_SIGN | 0x2) /* not used */ + #define BC_STATE_PROG_BAR (BC_STATE_SIGN | 0x3) /* not used */ + #define BC_STATE_INIT_VID (BC_STATE_SIGN | 0x4) /* not used */ + #define BC_STATE_GET_NVM_CFG2 (BC_STATE_SIGN | 0x5) /* not used */ + #define BC_STATE_APPLY_WKARND (BC_STATE_SIGN | 0x6) /* not used */ + #define BC_STATE_LOAD_BC2 (BC_STATE_SIGN | 0x7) /* not used */ + #define BC_STATE_GOING_BC2 (BC_STATE_SIGN | 0x8) /* not used */ + #define BC_STATE_GOING_DIAG (BC_STATE_SIGN | 0x9) /* not used */ + #define BC_STATE_RT_FINAL_INIT (BC_STATE_SIGN | 0x81) /* not used */ + #define BC_STATE_RT_WKARND (BC_STATE_SIGN | 0x82) /* not used */ + #define BC_STATE_RT_DRV_PULSE (BC_STATE_SIGN | 0x83) /* not used */ + #define BC_STATE_RT_FIOEVTS (BC_STATE_SIGN | 0x84) /* not used */ + #define BC_STATE_RT_DRV_CMD (BC_STATE_SIGN | 0x85) /* not used */ + #define BC_STATE_RT_LOW_POWER (BC_STATE_SIGN | 0x86) /* not used */ + #define BC_STATE_RT_SET_WOL (BC_STATE_SIGN | 0x87) /* not used */ + #define BC_STATE_RT_OTHER_FW (BC_STATE_SIGN | 0x88) /* not used */ + #define BC_STATE_RT_GOING_D3 (BC_STATE_SIGN | 0x89) /* not used */ + #define BC_STATE_ERROR_SET 0x8000 + #define BC_STATE_ERR_BAD_VERSION (BC_STATE_SIGN | 0x8001) + #define BC_STATE_ERR_BAD_BC2_CRC (BC_STATE_SIGN | 0x8002) + #define BC_STATE_ERR_BC1_LOOP (BC_STATE_SIGN | 0x8003) + #define BC_STATE_ERR_UNKNOWN_CMD (BC_STATE_SIGN | 0x8004) + #define BC_STATE_ERR_DRV_DEAD (BC_STATE_SIGN | 0x8005) + #define BC_STATE_ERR_NO_RXP (BC_STATE_SIGN | 0x8006) + #define BC_STATE_ERR_TOO_MANY_RBUF (BC_STATE_SIGN | 0x8007) + #define BC_STATE_ERR_BAD_PCI_ID (BC_STATE_SIGN | 0x8008) + #define BC_STATE_ERR_FW_TIMEOUT (BC_STATE_SIGN | 0x8009) + #define BC_STATE_ERR_BAD_VPD_REQ (BC_STATE_SIGN | 0x800a) + #define BC_STATE_ERR_NO_LIC_KEY (BC_STATE_SIGN | 0x800b) + #define BC_STATE_ERR_NO_MGMT_FW (BC_STATE_SIGN | 0x800c) + #define BC_STATE_ERR_STACK_OVERFLOW (BC_STATE_SIGN | 0x800d) + #define BC_STATE_ERR_PCIE_LANE_DOWN (BC_STATE_SIGN | 0x800e) + #define BC_STATE_ERR_MEM_PARITY (BC_STATE_SIGN | 0x800f) + #define BC_STATE_ERR_WKARND_TOO_LONG (BC_STATE_SIGN | 0x8010) + u32_t condition; + #define CONDITION_INIT_POR 0x00000001 + #define CONDITION_INIT_VAUX_AVAIL 0x00000002 + #define CONDITION_INIT_PCI_AVAIL 0x00000004 + /* The INIT_PCI_RESET is really a reset type, but defining as + * RESET_TYPE may break backward compatibility. */ + #define CONDITION_INIT_PCI_RESET 0x00000008 + #define CONDITION_INIT_HD_RESET 0x00000010 /* Xinan only */ + #define CONDITION_DRV_PRESENT 0x00000100 + #define CONDITION_LOW_POWER_LINK 0x00000200 + #define CONDITION_CORE_RST_OCCURRED 0x00000400 /* Xinan only */ + #define CONDITION_UNUSED 0x00000800 /* Obsolete */ + #define CONDITION_BUSY_EXPROM 0x00001000 /* Teton/TetonII only */ + #define CONDITION_MFW_RUN_MASK 0x0000e000 + #define CONDITION_MFW_RUN_UNKNOWN 0x00000000 + #define CONDITION_MFW_RUN_IPMI 0x00002000 + #define CONDITION_MFW_RUN_UMP 0x00004000 + #define CONDITION_MFW_RUN_NCSI 0x00006000 + #define CONDITION_MFW_RUN_NONE 0x0000e000 + /* The followings are for Xinan in managing chip power on both ports */ + #define CONDITION_PM_STATE_MASK 0x00030000 /* Xinan only */ + #define CONDITION_PM_STATE_FULL 0x00030000 /* Xinan only */ + #define CONDITION_PM_STATE_PREP 0x00020000 /* Xinan only */ + #define CONDITION_PM_STATE_UNPREP 0x00010000 /* Xinan only */ + #define CONDITION_PM_RESERVED 0x00000000 /* Xinan only */ + + #define CONDITION_WANT_FULL_POWER 0x00030000 /* Obsolete */ + #define CONDITION_WANT_PM_POWER 0x00010000 /* Can still have gigabit in LOMs */ /* Obsolete */ + #define CONDITION_WANT_ZERO_POWER 0x00000000 /* Obsolete */ + + #define CONDITION_RXMODE_KEEP_VLAN 0x00040000 /* Mirroring RX_MODE_KEEP_VLAN bit in EMAC */ + #define CONDITION_DRV_WOL_ENABLED 0x00080000 /* Xinan only */ + #define CONDITION_PORT_DISABLED 0x00100000 /* Xinan only: meant to tell driver about port disabled */ + #define CONDITION_DRV_MAYBE_OUT 0x00200000 /* Xinan only for now */ + #define CONDITION_DPFW_DEAD 0x00400000 /* Xinan only for now */ + u32_t override; + #define OVERRIDE_SIGNATURE_MASK 0xffff0000 + #define OVERRIDE_SIGNATURE 0x424f0000 + #define OVERRIDE_MFW_CHOICE_MASK (CONDITION_MFW_RUN_MASK >> 13) // 0x7 + #define OVERRIDE_MFW_DONTCARE (CONDITION_MFW_RUN_UNKNOWN >> 13) // 0x0 + #define OVERRIDE_MFW_LOAD_IPMI (CONDITION_MFW_RUN_IPMI >> 13) // 0x1 + #define OVERRIDE_MFW_LOAD_UMP (CONDITION_MFW_RUN_UMP >> 13) // 0x2 + #define OVERRIDE_MFW_LOAD_NCSI (CONDITION_MFW_RUN_NCSI >> 13) // 0x3 + #define OVERRIDE_MFW_LOAD_NONE (CONDITION_MFW_RUN_NONE >> 13) // 0x7 + u32_t misc; + #define BC_MISC_PHY_ADDR_MASK 0x1f + u32_t wol_signature; + /* This is a simple signature value to indicate WOL being enabled + * on the next boot code invocation (reset). This allows driver to + * override the NVRAM setting for S5 WOL. */ + #define WOL_ENABLE_SIGNATURE 0x574f4c00 + u32_t reserved[1]; + u32_t debug_cmd; /* Not used */ + #define BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 + #define BC_DBG_CMD_SIGNATURE 0x42440000 + #define BC_DBG_CMD_LOOP_CNT_MASK 0xffff + #define BC_DBG_CMD_LOOP_INFINITE 0xffff +} bc_state_t; + +/* This macro is used by to determine whether another + * software entity exists before making changes to the hardware. + * FW_TIMEOUT is included to handle the communication loss with the driver. + * It's better to assume that driver is still running to avoid messing up + * the driver in this case. */ +#define DRV_PRESENT(s) ( \ + ((shmem_region_t volatile *)s)->bc_state.condition & CONDITION_DRV_PRESENT) + +#define PORT_DISABLED(s) ( \ + ((shmem_region_t volatile *)s)->bc_state.condition & CONDITION_PORT_DISABLED) + +#ifdef DEBUG +#define SET_BC_STATE(p,s) \ + { \ + u32_t *ptr; \ + ptr = (u32_t *)&(((shmem_region_t volatile *)p)->bc_state.state); \ + if ((*ptr & BC_STATE_ERR_MASK) == 0) *ptr = s; \ + } +#else +#define SET_BC_STATE(p,s) +#endif + +#define MGMTFW_STATE_WORD_SIZE 80 +typedef struct _mgmtfw_state_t +{ + /* Allocate 320 bytes for management firmware: still not known exactly + * how much IMD needs. */ + u32_t opaque[MGMTFW_STATE_WORD_SIZE]; +} mgmtfw_state_t; + +typedef struct _fw_evt_mb_t +{ + u32_t fw_evt_code_mb; + #define FW_EVT_CODE_LINK_STATUS_CHANGE_EVENT 0x00000001 + #define FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT 0x00000000 + + u32_t fw_evt_data_mb[3]; + +} fw_evt_mb_t; + + +typedef struct drv_fw_cap_mb +{ + u32_t drv_ack_cap_mb; + #define CAPABILITY_SIGNATURE_MASK 0xFFFF0000 + #define DRV_ACK_CAP_SIGNATURE 0x35450000 + #define FW_ACK_DRV_SIGNATURE 0x52500000 + u32_t fw_cap_mb; + #define FW_CAP_SIGNATURE 0xAA550000 + + #define FW_CAP_REMOTE_PHY_CAPABLE 0x00000001 + #define FW_CAP_REMOTE_PHY_PRESENT 0x00000002 //bit 1 indicates absence or presence of remote phy HW + #define FW_CAP_UNUSED_BIT3 0x00000004 + #define FW_CAP_MFW_CAN_KEEP_VLAN 0x00000008 + #define FW_CAP_BC_CAN_UPDATE_VLAN 0x00000010 + +} drv_fw_cap_mb_t; + +typedef struct remotephy +{ + u32_t load_signature; + #define REMOTE_PHY_LOAD_SIGNATURE 0x5a5a5a5a + #define REMOTE_PHY_LEGACY_MODE_SIGNATURE 0xFFDEADFF + + u32_t flags; + + u32_t serdes_link_pref; + + u32_t copper_phy_link_pref; + + u32_t serdes_autoneg_pref; /* Xinan only, not supported in TetonII */ + u32_t copper_autoneg_pref; /* Xinan only, not supported in TetonII */ + /* The bit definitions follow those in netlink.h */ + + u32_t link_backup; /* Teton II only; Xinan does not restart on driver load */ + +} remotephy_t; + +typedef struct _rt_param_t +{ + /* These parameters are loaded with defaults by bootcode just before + * ack'ing WAIT1. Since there are two instances of shmem, if the + * parameter is shared for both ports, only the parameter of the + * first instance counts. */ + u32_t drv_timeout_val; /* Xinan only, in (val * 1.5) sec */ + u32_t dpfw_timeout_val; /* Xinan only, in timer_25mhz_free_run format */ + u32_t reserved[3]; +} rt_param_t; + +/* Total size should be exactly 1k bytes */ +#define KEY_RSVD_DW_CNT ((52-sizeof(license_key_t))/4) +typedef struct _shmem_region_t +{ + drv_fw_mb_t drv_fw_mb; /* 0x000 - 0x01f */ +#ifdef SOLARIS + bnx2shm_dev_info_t dev_info; /* 0x020 - 0x1bf */ +#else + dev_info_t dev_info; /* 0x020 - 0x1bf */ +#endif + bc_state_t bc_state; /* 0x1c0 - 0x1df */ + license_key_t fw_lic_key; /* 0x1e0 - 0x213 */ + mgmtfw_state_t mgmtfw_state; /* 0x214 - 0x353 */ + fw_evt_mb_t fw_evt_mb; /* 0x354 - 0x363 */ + drv_fw_cap_mb_t drv_fw_cap_mb; /* 0x364 - 0x36b */ + remotephy_t remotephy; /* 0x36c - 0x387 */ + u32_t dpfw_mb; /* 0x388 - 0x38b */ + rt_param_t rt_param; /* 0x38c - 0x39f */ + #define DPFW_MB_FW_ALIVE 0x00000001 + /* Xinan only: Datapath firmware keeps writing 1 to it and + * BC keeps clearing it. */ +#ifdef SOLARIS + u32_t reserved[256 \ + - sizeof(drv_fw_mb_t)/4 \ + - sizeof(bnx2shm_dev_info_t)/4 \ + - sizeof(bc_state_t)/4 \ + - sizeof(license_key_t)/4 \ + - KEY_RSVD_DW_CNT \ + - sizeof(mgmtfw_state_t)/4 \ + - sizeof(fw_evt_mb_t)/4 \ + - sizeof(drv_fw_cap_mb_t)/4 \ + - sizeof(remotephy_t)/4 \ + - sizeof(u32_t)/4 \ + - sizeof(rt_param_t)/4 \ + - sizeof(license_key_t)/4 \ + - KEY_RSVD_DW_CNT \ + - 2 \ + ]; +#else + u32_t reserved[256 \ + - sizeof(drv_fw_mb_t)/4 \ + - sizeof(dev_info_t)/4 \ + - sizeof(bc_state_t)/4 \ + - sizeof(license_key_t)/4 \ + - KEY_RSVD_DW_CNT \ + - sizeof(mgmtfw_state_t)/4 \ + - sizeof(fw_evt_mb_t)/4 \ + - sizeof(drv_fw_cap_mb_t)/4 \ + - sizeof(remotephy_t)/4 \ + - sizeof(u32_t)/4 \ + - sizeof(rt_param_t)/4 \ + - sizeof(license_key_t)/4 \ + - KEY_RSVD_DW_CNT \ + - 2 \ + ]; +#endif + u32_t l1_wkarnd_dbg0; /* 0x3c4: used by TetonII BC only */ + u32_t l1_wkarnd_dbg1; /* 0x3c8: used by TetonII BC only */ + license_key_t drv_lic_key; /* 0x3cc - 0x3ff */ +} shmem_region_t; + + +#ifdef DOS16BIT_DRIVER +/* These will be generated in 5706_reg.h for 16-bit DOS driver */ +#define MCP_SCRATCH 0x160000 +#define MCP_UNUSED_E 0x168000 +/****************************************/ +#define MCP_SCRATCHPAD_START MCP_SCRATCH +#define MCP_SCRATCHPAD_END MCP_UNUSED_E +#else +#define MCP_SCRATCHPAD_START ROFFSET(mcp.mcp_scratch) +#define MCP_SCRATCHPAD_END ROFFSET(mcp.mcp_unused_e) +#endif + +#define MCP_TETON_SCRATCH_SIZE 0x8000 + +/* Add the following to the original shared memory offset if the chip + * is 5708B0 or after, since it has 8kB more of scratchpad. + */ +#define MCP_SHMEM_5708B0_DELTA 0x2000 +#define HOST_VIEW_SHMEM_BASE (MCP_SCRATCHPAD_START + \ + MCP_TETON_SCRATCH_SIZE - \ + sizeof(shmem_region_t)) /* 0x167c00 */ +#define SHMEM_BASE (HOST_VIEW_SHMEM_BASE - MCP_SCRATCHPAD_START) /* 0x7C00 */ + + +#endif /* _SHMEM_H */ + diff --git a/usr/src/uts/common/io/bnx/570x/common/include/tcp_ctx.h b/usr/src/uts/common/io/bnx/570x/common/include/tcp_ctx.h new file mode 100644 index 0000000000..06cc9693a2 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/tcp_ctx.h @@ -0,0 +1,270 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _TCP_CTX_H +#define _TCP_CTX_H + +#include "bcmtype.h" +#include "l2_defs.h" + +///////////////////////////////////////////////////////////////////// +// TCP TX section +///////////////////////////////////////////////////////////////////// + +#if defined(LITTLE_ENDIAN) + typedef struct { + u32_t tcp_tsch_snd_next; // TSCH copy of snd_next, used for window calculations + u32_t tcp_snd_max; // TCP snd_max + u8_t tcp_tsch_xnum; // last slot number that was scheduled by TSCH + u8_t tcp_cons_retx_num; // last retransmit flush index that COM has received completion for + u8_t tcp_tsch_cmd; // Index of next ccell to be scheduled by TSCH + u8_t tcp_cp_cmd; // Command Queue producer + u8_t tcp_tsch_cons_retx_num; // last retransmit flush index that was sent by TSCH + u8_t tcp_prod_retx_num; // Retransmit flush is initiated by incrementing this member + u16_t tcp_pgid; // L2 context cid that belong to this connection + u8_t cam_pending; // number of free entries in the CAM that are reserved for offloading the connection + u8_t tcp_tcp_hlen; // size of TCP header in 32 bit words + u8_t tcp_iphdr_nbytes; // size of IP header in bytes + u8_t l2_slot_size; // N/A for iSCSI + u32_t tcp_max_adv_win; // Maximum advertised window to the remote peer + u8_t tcp_modes; + u8_t tcp_dack; + u8_t tcp_tos; + u8_t tcp_ttl; + union { + u32_t tcp_ip_dst; // destination IP address + u32_t tcp_ipv6_dst[4]; // destination IP v6 address + }u1; + union { + u32_t tcp_ip_src; // source IP address + u32_t tcp_ipv6_src[4]; // source IP v6 address + }u2; + u16_t tcp_dst_port; // TCP destination port number + u16_t tcp_src_port; // TCP source port number + } tcp_tx_ctx_l_t; + typedef tcp_tx_ctx_l_t tcp_tx_ctx_t; +#elif defined(BIG_ENDIAN) + typedef struct { + u32_t tcp_tsch_snd_next; // TSCH copy of snd_next, used for window calculations + u32_t tcp_snd_max; // TCP snd_max + u8_t tcp_cp_cmd; // Command Queue producer + u8_t tcp_tsch_cmd; // Index of next ccell to be scheduled by TSCH + u8_t tcp_cons_retx_num; // last retransmit flush index that COM has received completion for + u8_t tcp_tsch_xnum; // last slot number that was scheduled by TSCH + u16_t tcp_pgid; // L2 context cid that belong to this connection + u8_t tcp_prod_retx_num; // Retransmit flush is initiated by incrementing this member + u8_t tcp_tsch_cons_retx_num; // last retransmit flush index that was sent by TSCH + u8_t l2_slot_size; // N/A for iSCSI + u8_t tcp_iphdr_nbytes; // size of IP header in bytes + u8_t tcp_tcp_hlen; // size of TCP header in 32 bit words + u8_t cam_pending; // number of free entries in the CAM that are reserved for offloading the connection + u32_t tcp_max_adv_win; // Maximum advertised window to the remote peer + u8_t tcp_ttl; + u8_t tcp_tos; + u8_t tcp_dack; + u8_t tcp_modes; + #define L4CTX_TCP_MODES_RST_INDICATED_PENDING (1<<0) + #define L4CTX_TCP_MODES_DISC_BD (1<<1) + #define L4CTX_TCP_MODES_UPLOAD_INITED (1<<2) + #define L4CTX_TCP_MODES_RMT_DISC (1<<3) + #define L4CTX_TCP_MODES_PG_INVALIDATED (1<<4) + #define L4CTX_TCP_MODES_ABORT_PENDING (1<<5) + #define L4CTX_TCP_MODES_DISC_PENDING (1<<6) + #define L4CTX_TCP_MODES_STOP_TX (1<<7) + union { + u32_t tcp_ip_dst; // destination IP address + u32_t tcp_ipv6_dst[4]; // destination IP v6 address + }; + union { + u32_t tcp_ip_src; // source IP address + u32_t tcp_ipv6_src[4]; // source IP v6 address + }; + u16_t tcp_src_port; // TCP source port number + u16_t tcp_dst_port; // TCP destination port number + } tcp_tx_ctx_b_t; + + typedef tcp_tx_ctx_b_t tcp_tx_ctx_t; +#endif +///////////////////////////////////////////////////////////////////// +// TCP CMN section +///////////////////////////////////////////////////////////////////// + +// Congestion avoidance and slow start require that two variables be maintained +// for each connection: a congestion window, cwnd, and a slow start threshold +// size, ssthresh. Initialization for a given connection sets cwnd to one segment +// and ssthresh to 65535 (or 0xFFFF)bytes. (but MS passed down 0xFFFFFFFF as +// initial value) +#define INITIAL_SSTHRESH_VAL 0xFFFFFFFF +#define MAX_SSTHRESH_VAL 0x7FFFFFFF + +typedef struct { + u8_t ctx_type; // 0x0 context type enum + #define CTX_TYPE_ISCSI (5<<4) + u8_t size; // 0x1 context size in bytes + u8_t bd_pre_read; // 0x2 + u8_t gen_bd_cid; // 0x3 + u8_t gen_bd_max; // 0x4 + u8_t oubits; // 0x5 + u16_t sq_prod; // 0x6 SQ producer, updated by host via mailbox. wraps at size: bits 0 - (k-1): queue element index within page, bits k - 15: page index in page table + u8_t tcp_flags; // 0x8 + u8_t tcp_state; // 0x9 TCP state machine + union idx16_union_t rq_prod; // 0xa RQ producer, updated by driver, wraps at rq_size + u32_t tcp_timer1; // 0xc retransmit timer + u16_t tcp_timer2; // 0x10 + u16_t tcp_timer3; // + u16_t tcp_timer4; // 0x14 + u16_t tcp_timer5; // + u32_t tcp_slot_size; // 0x18 + #define L4CTX_TCP_SLOT_SIZE_SLOT_SIZE (0xffffffL<<0) + #define L4CTX_TCP_SLOT_SIZE_CMD_MAX (0x7fL<<24) + #define L4CTX_TCP_SLOT_SIZE_STOP (1UL<<31) + u32_t tcp_snd_cwin; // 0x1c + u32_t tcp_snd_win; // 0x20 + u8_t tcp_num_dupack; // 0x24 number of consecutive duplicate ACK received + u8_t tcp_tx_protocol_flags; // 0x25 ack/rst/syn/fin indication + u8_t tcp_comp_cons_retx_num; // Last retransmit flush index that was completed by TXP + u8_t tcp_num_retx; // + u32_t tcp_fl; // TCP flow label for IPV6 + u32_t tcp_ssthresh; // 0x2c TCP slow start threshold + u32_t tcp_rcv_next; // 0x30 TCP receive next sequence number + u32_t tcp_rcv_win_seq; // unused in iSCSI + u32_t tcp_snd_una; // + u32_t tcp_snd_next; // + u32_t tcp_sm_rtt; // 0x40 + u32_t tcp_sm_delta; // + u32_t tcp_max_snd_win; // + u8_t tcp_txp_cmd; // 0x4c index of the ccell that the TXP is currently transmitting + u8_t tcp_upload_reason; // + u8_t tcp_rcv_seg_scale; // TCP segment scale that is advertised by Xinan + u8_t tcp_ulp_ooo_flags; +#define TCP_ULP_OOO_DETECTED (0x01) + u32_t last_ack_sent; // TCP ack sequence of the previous packet transmitted + u32_t tcp_offload_seq; // initial TCP seq number of the Xinan sid (i.e. bseq + offload_seq = tcp_seq) + u32_t tcp_tstamp; // + u16_t tcp_mss; // mss of the connection + u8_t ka_probe_cnt; + u8_t ka_max_probe_cnt; + u8_t force_ack_pending; + u8_t krnlq_id; // indicate which krnlq that kcqe should be written to. + u16_t ka_timeout_tick; + u16_t ka_interval_tick; + u8_t unused2; + u8_t challenge_ack_state; // refer to tcpm-tcpsecure-09 requirement + #define CHALLENGE_ACK_NOT_SENT 0 // Challenge Ack not sent + #define CHALLENGE_ACK_SENT_KA_DISABLED 1 // Challenge ACK is sent while KA was disabled + #define CHALLENGE_ACK_SENT_KA_ENABLED 2 // Challenge ACK is sent while KA was enabled +} tcp_cmn_ctx_b_t; + +typedef struct { + u8_t gen_bd_cid; // 0x0 + u8_t bd_pre_read; // 0x1 + u8_t size; // 0x2 + u8_t ctx_type; // 0x3 context type enum + u16_t sq_prod; // 0x4 SQ producer, updated by host via mailbox. wraps at size: bits 0 - (k-1): queue element index within page, bits k - 15: page index in page table + u8_t oubits; // 0x6 ??? + u8_t gen_bd_max; // 0x7 + u16_t rq_prod; // 0x8 RQ producer, updated by driver, wraps at rq_size + u8_t tcp_state; // 0xa TCP state machine + u8_t tcp_flags; // 0xb + u32_t tcp_timer1; // 0xc retransmit timer + u16_t tcp_timer3; // + u16_t tcp_timer2; // 0x10 + u16_t tcp_timer5; // + u16_t tcp_timer4; // 0x14 + u32_t tcp_slot_size; // 0x18 + u32_t tcp_snd_cwin; // 0x1c + u32_t tcp_snd_win; // 0x20 + u8_t tcp_num_retx; // + u8_t tcp_comp_cons_retx_num; // Last retransmit flush index that was completed by TXP + u8_t tcp_tx_protocol_flags; // 0x25 ack/rst/syn/fin indication + u8_t tcp_num_dupack; // 0x24 number of consecutive duplicate ACK received + u32_t tcp_fl; // 0x28 TCP flow label for IPV6 + u32_t tcp_ssthresh; // 0x2c TCP slow start threshold + u32_t tcp_rcv_next; // 0x30 TCP receive next sequence number + u32_t tcp_rcv_win_seq; // unused in iSCSI + u32_t tcp_snd_una; // + u32_t tcp_snd_next; // + u32_t tcp_sm_rtt; // 0x40 + u32_t tcp_sm_delta; // + u32_t tcp_max_snd_win; // + u8_t tcp_ulp_ooo_flags; + u8_t tcp_rcv_seg_scale; // TCP segment scale that is advertised by Xinan + u8_t tcp_upload_reason; // + u8_t tcp_txp_cmd; // 0x4c index of the ccell that the TXP is currently transmitting + u32_t last_ack_sent; // TCP ack sequence of the previous packet transmitted + u32_t tcp_offload_seq; // initial TCP seq number of the Xinan side (i.e. bseq + offload_seq = tcp_seq) + u32_t tcp_tstamp; // + u8_t ka_max_probe_cnt; + u8_t ka_probe_cnt; + u16_t tcp_mss; // mss of the connection + u16_t ka_timeout_tick; + u8_t krnlq_id; // indicate which krnlq that kcqe should be written to. + u8_t force_ack_pending; + u8_t challenge_ack_state; // refer to tcpm-tcpsecure-09 requirement + u8_t unused2; + u16_t ka_interval_tick; +} tcp_cmn_ctx_l_t; + +#if defined(LITTLE_ENDIAN) + typedef tcp_cmn_ctx_l_t tcp_cmn_ctx_t; +#elif defined(BIG_ENDIAN) + typedef tcp_cmn_ctx_b_t tcp_cmn_ctx_t; +#endif +///////////////////////////////////////////////////////////////////// +// TCP RX section +///////////////////////////////////////////////////////////////////// +typedef struct { + u8_t state; // iooo state + u8_t spill_mode:1; + u8_t mode:7; +} iooo_tcp_b_t; + +typedef struct { + u8_t mode:7; + u8_t spill_mode:1; + u8_t state; // iooo state +} iooo_tcp_l_t; + +typedef struct { + u32_t tcp_snd_wl1; // + u32_t tcp_snd_wl2; // + u8_t tcp_snd_seg_scale; // TCP segment scale that is advertised by the remote peer +#if (ISCSI_OOO_SUPPORT) + iooo_tcp_b_t iooo_tcp; // iSCSI OOO tcp manager structure + u8_t reserved0; +#else + u8_t reserved0[3]; +#endif +} tcp_rx_ctx_b_t; + +typedef struct { + u32_t tcp_snd_wl1; // + u32_t tcp_snd_wl2; // +#if (ISCSI_OOO_SUPPORT) + iooo_tcp_l_t iooo_tcp; // iSCSI OOO tcp manager structure + u8_t reserved0; +#else + u8_t reserved0[3]; +#endif + u8_t tcp_snd_seg_scale; // TCP segment scale that is advertised by the remote peer +} tcp_rx_ctx_l_t; + +#if defined(LITTLE_ENDIAN) + typedef tcp_rx_ctx_l_t tcp_rx_ctx_t; +#elif defined(BIG_ENDIAN) + typedef tcp_rx_ctx_b_t tcp_rx_ctx_t; +#endif + +#endif /* _TCP_CTX_H */ + diff --git a/usr/src/uts/common/io/bnx/570x/common/include/toe_ctx.h b/usr/src/uts/common/io/bnx/570x/common/include/toe_ctx.h new file mode 100644 index 0000000000..30b2347371 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/toe_ctx.h @@ -0,0 +1,898 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _TOE_CTX_H +#define _TOE_CTX_H + +#include "tcp_ctx.h" + + + +///////////////////////////////////////////////////////////////////// +// TOE TX section +///////////////////////////////////////////////////////////////////// +typedef struct { + u32_t rto_intvl; // current unbounded rto interval (in ticks) + u32_t unused; + u32_t tcp_last_rcv_win_seq; + u8_t tx_in_coalesce; + u8_t tx_ind_silly_win; + u8_t tx_large_bd; + u8_t tx_comp_defer; + u16_t max_rt_tick; // maximum total retransmit timeout (in ticks) + u16_t total_rt_tick; // total retransmit timeout (in ticks) + u32_t tcp_sack_start; // keep track of rx SACK + u8_t tx_comp_prod; + u8_t tx_comp_cons; + u8_t persist_probe_cnt; + u8_t in_generic; + u32_t tx_comp_step; + u32_t reply_ts; + #define TOE_RTT_SAMPLED (1<<0) + u32_t tcp_save_cwin; + u32_t unused2; + u32_t host_win_update; +} toe_l4_tx_ctx_b_t; + +typedef struct { + u32_t rto_intvl; // current unbounded rto interval (in ticks) + u32_t unused; + u32_t tcp_last_rcv_win_seq; + u8_t tx_comp_defer; + u8_t tx_large_bd; + u8_t tx_ind_silly_win; + u8_t tx_in_coalesce; + u16_t total_rt_tick; // total retransmit timeout (in ticks) + u16_t max_rt_tick; // maximum total retransmit timeout (in ticks) + u32_t tcp_sack_start; // keep track of rx SACK + u8_t in_generic; + u8_t persist_probe_cnt; + u8_t tx_comp_cons; + u8_t tx_comp_prod; + u32_t tx_comp_step; + u32_t reply_ts; + #define TOE_RTT_SAMPLED (1<<0) + u32_t tcp_save_cwin; + u32_t unused2; + u32_t host_win_update; +} toe_l4_tx_ctx_l_t; + +#if defined(LITTLE_ENDIAN) + typedef toe_l4_tx_ctx_l_t toe_l4_tx_ctx_t; +#elif defined(BIG_ENDIAN) + typedef toe_l4_tx_ctx_b_t toe_l4_tx_ctx_t; +#endif + + typedef struct { + tcp_tx_ctx_t tcp; + toe_l4_tx_ctx_t toe; +} toe_tx_ctx_t; + +///////////////////////////////////////////////////////////////////// +// TOE CMN section +///////////////////////////////////////////////////////////////////// +typedef struct { + u32_t tcp_disconnect_seq; // last snd seq # before disconnecting + u32_t last_fin_seq; // last rx seq # in FIN packet + u8_t tcp_retx_defer; + u8_t tcp_flow_state; + #define TOE_FLOW_STATE_NORMAL_INIT (0<<0) + #define TOE_FLOW_STATE_NORMAL_RUNNING (1<<0) + #define TOE_FLOW_STATE_LIMIT_TX_ACTIVE (2<<0) + #define TOE_FLOW_STATE_IN_LOSS_RECOVERY (3<<0) + #define TOE_FLOW_STATE_FAST_RETX_INIT1 (4<<0) + #define TOE_FLOW_STATE_FAST_RETX_INIT2 (5<<0) + #define TOE_FLOW_STATE_FAST_RETX_RELOAD (6<<0) + #define TOE_FLOW_STATE_FAST_RETX_ACTIVE1 (7<<0) + #define TOE_FLOW_STATE_FAST_RETX_ACTIVE2 (8<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_INIT1 (9<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_INIT2 (10<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_ACTIVE (11<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_EXIT (12<<0) + u8_t tcp_partial_ack_cnt; + u8_t timer1_mode; // timer1 is overloaded for retx, persist, sws prevention and FIN_WAIT2 timer + u32_t tcp_snd_recover; + u16_t gen_buff_accum; + u8_t ooo_fin_upload_state; + #define OOO_FIN_UPLOAD_IDLE (0<<0) + #define OOO_FIN_UPLOAD_DEFER (1<<0) + #define OOO_FIN_UPLOAD_NOW (2<<0) + #define OOO_FIN_UPLOAD_DONE (3<<0) + #define OOO_FIN_UPLOAD_DEFER_PENDING (4<<0) + #define OOO_FIN_UPLOAD_UNKNOWN (5<<0) + u8_t reload_comp_status; + #define RELOAD_COMP_IDLE (0<<0) + #define RELOAD_COMP_HOST_PENDING (1<<0) + #define RELOAD_COMP_ONCHIP_PENDING (2<<0) + u32_t ooo_fin_seq; +} toe_l4_cmn_ctx_b_t; + +typedef struct { + u32_t tcp_disconnect_seq; // last snd seq # before disconnecting + u32_t last_fin_seq; // last rx seq # in FIN packet + u8_t timer1_mode; // timer1 is overloaded for retx, persist, sws prevention and FIN_WAIT2 timer + #define TIMER1_RETX_MODE (0) + #define TIMER1_PERSIST_MODE (1) + #define TIMER1_SWS_PREVENT_MODE (2) + #define TIMER1_FIN_WAIT2_MODE (3) + u8_t tcp_partial_ack_cnt; + u8_t tcp_flow_state; + #define TOE_FLOW_STATE_NORMAL_INIT (0<<0) + #define TOE_FLOW_STATE_NORMAL_RUNNING (1<<0) + #define TOE_FLOW_STATE_LIMIT_TX_ACTIVE (2<<0) + #define TOE_FLOW_STATE_IN_LOSS_RECOVERY (3<<0) + #define TOE_FLOW_STATE_FAST_RETX_INIT1 (4<<0) + #define TOE_FLOW_STATE_FAST_RETX_INIT2 (5<<0) + #define TOE_FLOW_STATE_FAST_RETX_RELOAD (6<<0) + #define TOE_FLOW_STATE_FAST_RETX_ACTIVE1 (7<<0) + #define TOE_FLOW_STATE_FAST_RETX_ACTIVE2 (8<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_INIT1 (9<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_INIT2 (10<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_ACTIVE (11<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_EXIT (12<<0) + u8_t tcp_retx_defer; + u32_t tcp_snd_recover; + u8_t reload_comp_status; + #define RELOAD_COMP_IDLE (0<<0) + #define RELOAD_COMP_HOST_PENDING (1<<0) + #define RELOAD_COMP_ONCHIP_PENDING (2<<0) + u8_t ooo_fin_upload_state; + u16_t gen_buff_accum; + u32_t ooo_fin_seq; +} toe_l4_cmn_ctx_l_t; + +#if defined(LITTLE_ENDIAN) + typedef toe_l4_cmn_ctx_l_t toe_l4_cmn_ctx_t; +#elif defined(BIG_ENDIAN) + typedef toe_l4_cmn_ctx_b_t toe_l4_cmn_ctx_t; +#endif + +typedef struct { + tcp_cmn_ctx_t tcp; + toe_l4_cmn_ctx_t toe; +} toe_cmn_ctx_t; + +///////////////////////////////////////////////////////////////////// +// TOE RX section +///////////////////////////////////////////////////////////////////// +typedef struct { + u32_t ccell_hist_bseq; + u32_t ccell_hist_bhaddr_hi; + u32_t ccell_hist_bhaddr_lo; + u16_t ccell_hist_bidx; + u16_t ccell_hist_bd_nbytes; +} toe_ccell_hist_b_t; + +typedef struct { + u32_t ccell_hist_bseq; + u32_t ccell_hist_bhaddr_hi; + u32_t ccell_hist_bhaddr_lo; + u16_t ccell_hist_bd_nbytes; + u16_t ccell_hist_bidx; +} toe_ccell_hist_l_t; + +#if defined(LITTLE_ENDIAN) + typedef toe_ccell_hist_l_t toe_ccell_hist_t; +#elif defined(BIG_ENDIAN) + typedef toe_ccell_hist_b_t toe_ccell_hist_t; +#endif + +#define MAX_CCELL_HIST_ENTRY 9 + +typedef struct { + u8_t l4_bd_chain_v2p_proc1flags; + u8_t l4_bd_chain_host_gen_count; + u16_t l4_bd_chain_host_bdidx; + u32_t l4_bd_chain_host_bseq; + u32_t l4_bd_chain_nx_bdhaddr_hi; + u32_t l4_bd_chain_nx_bdhaddr_lo; + u32_t l4_bd_chain_nx_seq; + u8_t l4_bd_chain_v2p_flags; + u8_t l4_bd_chain_v2p_gen_count; + u16_t l4_bd_chain_nx_bdidx; + u16_t l4_bd_chain_gen_used; + u16_t l4_bd_chain_nx_boff; + u32_t l4_bd_chain_cmpl_seq; + u32_t l4_bd_chain_cmpl_bdhaddr_hi; + u32_t l4_bd_chain_cmpl_bdhaddr_lo; + u16_t l4_bd_chain_gen_size; + u16_t l4_bd_chain_cmpl_bdidx; + u32_t l4_bd_chain_io_seq; + u32_t l4_bd_chain_hole_seq; + u32_t l4_bd_chain_end_seq; + u32_t l4_bd_chain_bseq_lead; + u32_t l4_bd_chain_push_seq; + u32_t l4_bd_chain_gen_start_seq; + u32_t l4_bd_chain_gen_seq; + u32_t l4_bd_chain_gen_bfr_hi; + u32_t l4_bd_chain_gen_bfr_lo; + u32_t l4_bd_chain_hole2_seq; // to keep track of 2nd holes + u32_t l4_bd_chain_end2_seq; + u8_t ccell_hist_prod_idx; + u8_t ccell_hist_cons_idx; + u8_t ccell_hist_num_entry; + u8_t unused; + toe_ccell_hist_t ccell_hist_tbl[MAX_CCELL_HIST_ENTRY]; +} toe_l4_rx_ctx_b_t; + +typedef struct { + u16_t l4_bd_chain_host_bdidx; + u8_t l4_bd_chain_host_gen_count; + u8_t l4_bd_chain_v2p_proc1flags; + u32_t l4_bd_chain_host_bseq; + u32_t l4_bd_chain_nx_bdhaddr_hi; + u32_t l4_bd_chain_nx_bdhaddr_lo; + u32_t l4_bd_chain_nx_seq; + u16_t l4_bd_chain_nx_bdidx; + u8_t l4_bd_chain_v2p_gen_count; + u8_t l4_bd_chain_v2p_flags; + u16_t l4_bd_chain_nx_boff; + u16_t l4_bd_chain_gen_used; + u32_t l4_bd_chain_cmpl_seq; + u32_t l4_bd_chain_cmpl_bdhaddr_hi; + u32_t l4_bd_chain_cmpl_bdhaddr_lo; + u16_t l4_bd_chain_cmpl_bdidx; + u16_t l4_bd_chain_gen_size; + u32_t l4_bd_chain_io_seq; + u32_t l4_bd_chain_hole_seq; + u32_t l4_bd_chain_end_seq; + u32_t l4_bd_chain_bseq_lead; + u32_t l4_bd_chain_push_seq; + u32_t l4_bd_chain_gen_start_seq; + u32_t l4_bd_chain_gen_seq; + u32_t l4_bd_chain_gen_bfr_hi; + u32_t l4_bd_chain_gen_bfr_lo; + u32_t l4_bd_chain_hole2_seq; // to keep track of 2nd holes + u32_t l4_bd_chain_end2_seq; + toe_ccell_hist_t ccell_hist_tbl[MAX_CCELL_HIST_ENTRY]; + u8_t unused; + u8_t ccell_hist_num_entry; + u8_t ccell_hist_cons_idx; + u8_t ccell_hist_prod_idx; +} toe_l4_rx_ctx_l_t; + +#if defined(LITTLE_ENDIAN) + typedef toe_l4_rx_ctx_l_t toe_l4_rx_ctx_t; +#elif defined(BIG_ENDIAN) + typedef toe_l4_rx_ctx_b_t toe_l4_rx_ctx_t; +#endif + +typedef struct { + tcp_rx_ctx_t tcp; + toe_l4_rx_ctx_t toe; +} toe_rx_ctx_t; + +/* container structure for entire L4 ctx, it is mainly used by VBD debugging tools */ +typedef struct { + toe_tx_ctx_t toe_tx; + u8_t unused_0[128 - sizeof(toe_tx_ctx_t)]; + toe_cmn_ctx_t toe_cmn; /* ctx_cmn is full */ +// u8_t unused_0[128 - sizeof(toe_cmn_ctx_t)]; + toe_rx_ctx_t toe_rx; + u8_t unused_1[256 - sizeof(toe_rx_ctx_t)]; + u8_t reserved[64]; + tcp_context_cmd_cell_te_t toe_cmd_cell; +} toe_ctx_t; + + + +// Calling the following macro will actually get optimized during compile +// time. Its sole purpose is to ensure the context variable locations are +// not moved by accident +#define TEST_TOE_CTX(){ \ +if (0){ \ + 1/((sizeof(toe_ctx_t) == 0x268) && \ + (OFFSETOF(toe_ctx_t, toe_cmn) == 128) && \ + (OFFSETOF(toe_ctx_t, toe_rx) == 128+128) && \ + (OFFSETOF(toe_ctx_t, toe_cmd_cell) == 128+128+256+64));}} + + +/* + * l4_bd_chain_context_b definition + */ +typedef struct l4_bd_chain_context_b +{ + u8_t l4bdctx_v2p_proc1flags; + #define L4BDCTX_V2P_PROC1FLAGS_BD_CHN_FLUSH (1<<0) + #define L4BDCTX_V2P_PROC1FLAGS_BD_FORCE_PUSH (1<<1) + + u8_t l4bdctx_host_gen_count; + u16_t l4bdctx_host_bdidx; + u32_t l4bdctx_host_bseq; + u32_t l4bdctx_nx_bdhaddr_hi; + u32_t l4bdctx_nx_bdhaddr_lo; + u32_t l4bdctx_nx_seq; + u8_t l4bdctx_v2p_flags; + u8_t l4bdctx_v2p_gen_count; + u16_t l4bdctx_nx_bdidx; + u16_t l4bdctx_gen_used; + u16_t l4bdctx_nx_boff; + u32_t l4bdctx_cmpl_seq; + u32_t l4bdctx_cmpl_bdhaddr_hi; + u32_t l4bdctx_cmpl_bdhaddr_lo; + u16_t l4bdctx_gen_size; + u16_t l4bdctx_cmpl_bdidx; + u32_t l4bdctx_io_seq; + u32_t l4bdctx_hole_seq; + u32_t l4bdctx_end_seq; + u32_t l4bdctx_bseq_lead; + u32_t l4bdctx_push_seq; + u32_t l4bdctx_gen_start_seq; + u32_t l4bdctx_gen_seq; + u32_t l4bdctx_gen_bfr_hi; + u32_t l4bdctx_gen_bfr_lo; +} l4_bd_chain_context_b_t; + + +/* + * l4_bd_chain_context_l definition + */ +typedef struct l4_bd_chain_context_l +{ + u16_t l4bdctx_host_bdidx; + u8_t l4bdctx_host_gen_count; + u8_t l4bdctx_v2p_proc1flags; + #define L4BDCTX_V2P_PROC1FLAGS_BD_CHN_FLUSH (1<<0) + #define L4BDCTX_V2P_PROC1FLAGS_BD_FORCE_PUSH (1<<1) + + u32_t l4bdctx_host_bseq; + u32_t l4bdctx_nx_bdhaddr_hi; + u32_t l4bdctx_nx_bdhaddr_lo; + u32_t l4bdctx_nx_seq; + u16_t l4bdctx_nx_bdidx; + u8_t l4bdctx_v2p_gen_count; + u8_t l4bdctx_v2p_flags; + u16_t l4bdctx_nx_boff; + u16_t l4bdctx_gen_used; + u32_t l4bdctx_cmpl_seq; + u32_t l4bdctx_cmpl_bdhaddr_hi; + u32_t l4bdctx_cmpl_bdhaddr_lo; + u16_t l4bdctx_cmpl_bdidx; + u16_t l4bdctx_gen_size; + u32_t l4bdctx_io_seq; + u32_t l4bdctx_hole_seq; + u32_t l4bdctx_end_seq; + u32_t l4bdctx_bseq_lead; + u32_t l4bdctx_push_seq; + u32_t l4bdctx_gen_start_seq; + u32_t l4bdctx_gen_seq; + u32_t l4bdctx_gen_bfr_hi; + u32_t l4bdctx_gen_bfr_lo; +} l4_bd_chain_context_l_t; + + +/* + * l4_bd_chain_context select + */ +#if defined(LITTLE_ENDIAN) + typedef l4_bd_chain_context_l_t l4_bd_chain_context_t; +#elif defined(BIG_ENDIAN) + typedef l4_bd_chain_context_b_t l4_bd_chain_context_t; +#endif + +/* + * l4_context_b definition + */ +typedef struct l4_context_b +{ + u8_t l4ctx_ctx_type; + #define L4CTX_TYPE_TYPE (0xf<<4) + #define L4CTX_TYPE_TYPE_EMPTY (0<<4) + #define L4CTX_TYPE_TYPE_L2 (1<<4) + #define L4CTX_TYPE_TYPE_TCP (2<<4) + #define L4CTX_TYPE_TYPE_L5 (3<<4) + #define L4CTX_TYPE_TYPE_L2_BD_CHN (4<<4) + #define L4CTX_TYPE_TYPE_ISCSI (5<<4) + + u8_t l4ctx_size; + u8_t l4ctx_bd_pre_read; + u8_t l4ctx_gen_bd_cid; + u8_t l4ctx_gen_bd_max; + u8_t l4ctx_oubits; + #define L4CTX_OUBITS_ACTIVATE (1<<0) + #define L4CTX_OUBITS_CP_UPLOAD (1<<1) + #define L4CTX_OUBITS_RXP_UPLOAD (1<<2) + #define L4CTX_OUBITS_TXP_UPLOAD (1<<3) + #define L4CTX_OUBITS_COM_RX_UPLOAD (1<<4) + #define L4CTX_OUBITS_COM_TX_UPLOAD (1<<5) + #define L4CTX_OUBITS_CP_UPLOAD_COMP (1<<6) + + u8_t l4ctx_force_ack_pending; + u8_t l4ctx_challenge_ack_state; // refer to tcpm-tcpsecure-09 requirement + #define CHALLENGE_ACK_NOT_SENT 0 // Challenge Ack not sent + #define CHALLENGE_ACK_SENT_KA_DISABLED 1 // Challenge ACK is sent while KA was disabled + #define CHALLENGE_ACK_SENT_KA_ENABLED 2 // Challenge ACK is sent while KA was enabled + u16_t l4ctx_tcp_pgid; + u8_t unused; + u8_t l4ctx_tcp_retx_defer; + u32_t l4ctx_tcp_timer1; + #define L4CTX_TCP_TIMER1_DISABLE (1UL<<0) + #define L4CTX_TCP_TIMER1_VALUE (0x7fffffffL<<1) + + u16_t l4ctx_tcp_timer2; + #define L4CTX_TCP_TIMER2_DISABLE (1<<0) + #define L4CTX_TCP_TIMER2_VALUE (0x7fff<<1) + + u16_t l4ctx_tcp_timer3; + #define L4CTX_TCP_TIMER3_DISABLE (1<<0) + #define L4CTX_TCP_TIMER3_VALUE (0x7fff<<1) + + u16_t l4ctx_tcp_timer4; + #define L4CTX_TCP_TIMER4_DISABLE (1<<0) + #define L4CTX_TCP_TIMER4_VALUE (0x7fff<<1) + + u16_t l4ctx_tcp_timer5; + #define L4CTX_TCP_TIMER5_DISABLE (1<<0) + #define L4CTX_TCP_TIMER5_VALUE (0x7fff<<1) + + u32_t l4ctx_tcp_snd_wl1; + u32_t l4ctx_tcp_snd_wl2; + u8_t l4ctx_tcp_ttl; + u8_t l4ctx_tcp_tos; + u8_t l4ctx_tcp_dack; + u8_t l4ctx_tcp_modes; + #define L4CTX_TCP_MODES_RST_INDICATED_PENDING (1<<0) + #define L4CTX_TCP_MODES_DISC_BD (1<<1) + #define L4CTX_TCP_MODES_UPLOAD_INITED (1<<2) + #define L4CTX_TCP_MODES_RMT_DISC (1<<3) + #define L4CTX_TCP_MODES_PG_INVALIDATED (1<<4) + #define L4CTX_TCP_MODES_ABORT_PENDING (1<<5) + #define L4CTX_TCP_MODES_DISC_PENDING (1<<6) + #define L4CTX_TCP_MODES_STOP_TX (1<<7) + + u32_t l4ctx_tcp_max_adv_win; + u32_t l4ctx_rto_intvl; // current unbounded retransmission timeout (RTO) + u32_t l4ctx_tcp_ip_src; + u32_t l4ctx_tcp_ip_dst; + u8_t l4ctx_tcp_iphdr_nbytes; + u8_t l4ctx_tcp_snd_seg_scale; + u8_t l4ctx_tcp_rcv_seg_scale; + u8_t l4ctx_tcp_tcp_hlen; + u16_t l4ctx_tcp_src_port; + u16_t l4ctx_tcp_dst_port; + u16_t l4ctx_tcp_mss; + u8_t l4ctx_tcp_flags; + #define L4CTX_TCP_FLAGS_NO_DELAY_ACK (1<<0) + #define L4CTX_TCP_FLAGS_KEEP_ALIVE (1<<1) + #define L4CTX_TCP_FLAGS_NAGLE (1<<2) + #define L4CTX_TCP_FLAGS_TIME_STAMP (1<<3) + #define L4CTX_TCP_FLAGS_SACK (1<<4) + #define L4CTX_TCP_FLAGS_SEG_SCALING (1<<5) + #define L4CTX_TCP_FLAGS_OPTION2 (1<<6) + + u8_t l4ctx_tcp_state; + #define L4CTX_TCP_STATE_VALUE (0xff<<0) + #define L4CTX_TCP_STATE_VALUE_UNDEFINED (0<<0) + #define L4CTX_TCP_STATE_VALUE_LISTEN (2<<0) + #define L4CTX_TCP_STATE_VALUE_SYN_SENT (4<<0) + #define L4CTX_TCP_STATE_VALUE_SYN_RECV (6<<0) + #define L4CTX_TCP_STATE_VALUE_CLOSE_WAIT (8<<0) + #define L4CTX_TCP_STATE_VALUE_ESTABLISHED (10<<0) + #define L4CTX_TCP_STATE_VALUE_FIN_WAIT1 (12<<0) + #define L4CTX_TCP_STATE_VALUE_FIN_WAIT2 (14<<0) + #define L4CTX_TCP_STATE_VALUE_TIME_WAIT (16<<0) + #define L4CTX_TCP_STATE_VALUE_CLOSED (18<<0) + #define L4CTX_TCP_STATE_VALUE_LAST_ACK (20<<0) + #define L4CTX_TCP_STATE_VALUE_CLOSING (22<<0) + #define L4CTX_TCP_STATE_VALUE_ABORT_CONNECTION (24<<0) + + u32_t l4ctx_tcp_rcv_next; + u32_t l4ctx_last_ack_sent; + u32_t l4ctx_tcp_rcv_win_seq; + u32_t l4ctx_tcp_snd_una; + u32_t l4ctx_tcp_snd_next; + u32_t l4ctx_tcp_snd_max; + u32_t l4ctx_tcp_snd_win; + u32_t l4ctx_tcp_snd_cwin; + u32_t l4ctx_tcp_tstamp; + u32_t l4ctx_tcp_ssthresh; + u16_t l4ctx_tcp_sm_rtt; + u16_t l4ctx_tcp_sm_delta; + u32_t l4ctx_tcp_max_snd_win; + u32_t l4ctx_tcp_tsch_snd_next; + u32_t l4ctx_tcp_slot_size; + #define L4CTX_TCP_SLOT_SIZE_SLOT_SIZE (0xffffffL<<0) + #define L4CTX_TCP_SLOT_SIZE_CMD_MAX (0x7fL<<24) + #define L4CTX_TCP_SLOT_SIZE_STOP (1UL<<31) + + u8_t l4ctx_tcp_cp_cmd; + u8_t l4ctx_tcp_tsch_cmd; + u8_t l4ctx_tcp_cons_retx_num; + u8_t l4ctx_tcp_tsch_xnum; + #define L4CTX_TCP_TSCH_XNUM_VAL (0x7f<<0) + #define L4CTX_TCP_TSCH_XNUM_L4 (1<<7) + + u8_t l4ctx_tcp_num_dupack; + u8_t l4ctx_tcp_tx_protocol_flags; + #define L4CTX_TCP_TX_PROTOCOL_FLAGS_TIMER_DELAY_ACK (1<<0) + #define L4CTX_TCP_TX_PROTOCOL_FLAGS_UPLOAD (1<<1) + #define L4CTX_TCP_TX_PROTOCOL_FLAGS_FORCE_ACK (1<<2) + #define L4CTX_TCP_TX_PROTOCOL_FLAGS_LAST_ACK (1<<3) + #define L4CTX_TCP_TX_PROTOCOL_FLAGS_LAST_RST (1<<4) + /* TOE stack overload bit 4 to signal TXP to sends out pure ack + * TOE stack should never use last RST bit + */ + #define L4CTX_TCP_TX_PROTOCOL_FLAGS_PURE_ACK L4CTX_TCP_TX_PROTOCOL_FLAGS_LAST_RST + #define L4CTX_TCP_TX_PROTOCOL_FLAGS_FORCE_RST (1<<5) + #define L4CTX_TCP_TX_PROTOCOL_FLAGS_FORCE_ACK_MINUS (1<<6) + #define L4CTX_TCP_TX_PROTOCOL_FLAGS_SKIP_KA (1<<7) + + u8_t l4ctx_tcp_prod_retx_num; + u8_t l4ctx_tcp_tsch_cons_retx_num; + u8_t l4ctx_tcp_comp_cons_retx_num; + u8_t l4ctx_tcp_num_retx; + u8_t l4ctx_tcp_upload_reason; + #define L4CTX_TCP_UPLOAD_REASON_KEEP_ALIVE (1<<0) + #define L4CTX_TCP_UPLOAD_REASON_FIN (1<<1) + #define L4CTX_TCP_UPLOAD_REASON_URG (1<<2) + #define L4CTX_TCP_UPLOAD_REASON_FRAGMENT (1<<3) + #define L4CTX_TCP_UPLOAD_REASON_IP_OPTION (1<<4) + #define L4CTX_TCP_UPLOAD_REASON_RST (1<<5) + #define L4CTX_TCP_UPLOAD_REASON_SYN (1<<6) + #define L4CTX_TCP_UPLOAD_REASON_TIMEOUT (1<<7) + + u8_t l4ctx_tcp_txp_cmd; + u32_t l4ctx_tcp_offload_seq; + tcp_context_cmd_cell_te_t l4ctx_cmd[1]; + u8_t l4ctx_l4_bd_chain_v2p_proc1flags; + #define L4CTX_L4_BD_CHAIN_V2P_PROC1FLAGS_BD_CHN_FLUSH (1<<0) + #define L4CTX_L4_BD_CHAIN_V2P_PROC1FLAGS_BD_CHN_FORCE_PUSH (1<<1) + + u8_t l4ctx_l4_bd_chain_host_gen_count; + u16_t l4ctx_l4_bd_chain_host_bdidx; + u32_t l4ctx_l4_bd_chain_host_bseq; + u32_t l4ctx_l4_bd_chain_nx_bdhaddr_hi; + u32_t l4ctx_l4_bd_chain_nx_bdhaddr_lo; + u32_t l4ctx_l4_bd_chain_nx_seq; + u8_t l4ctx_l4_bd_chain_v2p_flags; + #define L4CTX_L4_BD_CHAIN_V2P_FLAGS_GEN_BD_IN_USE (1<<1) + #define L4CTX_L4_BD_CHAIN_V2P_FLAGS_HOLE_MODE (1<<2) + #define L4CTX_L4_BD_CHAIN_V2P_FLAGS_INDICATED (1<<3) + #define L4CTX_L4_BD_CHAIN_V2P_FLAGS_PUSH_ARMED (1<<4) + #define L4CTX_L4_BD_CHAIN_V2P_FLAGS_PUSH_PENDING (1<<5) + #define L4CTX_L4_BD_CHAIN_V2P_FLAGS_2ND_HOLE_MODE (1<<6) + #define L4CTX_L4_BD_CHAIN_V2P_FLAGS_NEW_ISLAND (1<<7) // 0 : 1st (inside) island is newer + // 1 : 2nd (outside) island is newer + u8_t l4ctx_l4_bd_chain_v2p_gen_count; + u16_t l4ctx_l4_bd_chain_nx_bdidx; + u16_t l4ctx_l4_bd_chain_gen_used; + u16_t l4ctx_l4_bd_chain_nx_boff; + u32_t l4ctx_l4_bd_chain_cmpl_seq; + u32_t l4ctx_l4_bd_chain_cmpl_bdhaddr_hi; + u32_t l4ctx_l4_bd_chain_cmpl_bdhaddr_lo; + u16_t l4ctx_l4_bd_chain_gen_size; + u16_t l4ctx_l4_bd_chain_cmpl_bdidx; + u32_t l4ctx_l4_bd_chain_io_seq; + u32_t l4ctx_l4_bd_chain_hole_seq; + u32_t l4ctx_l4_bd_chain_end_seq; + u32_t l4ctx_l4_bd_chain_bseq_lead; + u32_t l4ctx_l4_bd_chain_push_seq; + u32_t l4ctx_l4_bd_chain_gen_start_seq; + u32_t l4ctx_l4_bd_chain_gen_seq; + u32_t l4ctx_l4_bd_chain_gen_bfr_hi; + u32_t l4ctx_l4_bd_chain_gen_bfr_lo; + u32_t l4ctx_tx_comp_step; + u16_t l4ctx_max_rt_tick; // maximum total retransmit timeout (in ticks) + u16_t l4ctx_total_rt_tick; // total retransmit timeout (in ticks) + u32_t l4ctx_ooo_fin_seq; + u32_t l4ctx_unused; + u32_t l4ctx_tcp_last_rcv_win_seq; + u32_t l4ctx_tcp_save_cwin; + u8_t l4ctx_tcp_flow_state; + #define TOE_FLOW_STATE_NORMAL_INIT (0<<0) + #define TOE_FLOW_STATE_NORMAL_RUNNING (1<<0) + #define TOE_FLOW_STATE_LIMIT_TX_ACTIVE (2<<0) + #define TOE_FLOW_STATE_IN_LOSS_RECOVERY (3<<0) + #define TOE_FLOW_STATE_FAST_RETX_INIT1 (4<<0) + #define TOE_FLOW_STATE_FAST_RETX_INIT2 (5<<0) + #define TOE_FLOW_STATE_FAST_RETX_RELOAD (6<<0) + #define TOE_FLOW_STATE_FAST_RETX_ACTIVE1 (7<<0) + #define TOE_FLOW_STATE_FAST_RETX_ACTIVE2 (8<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_INIT1 (9<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_INIT2 (10<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_ACTIVE (11<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_EXIT (12<<0) + #define TCP_FLOW_NORMAL(x) ((x) <= TOE_FLOW_STATE_NORMAL_RUNNING) + #define TCP_FLOW_LIMIT_TX(x) ((x) == TOE_FLOW_STATE_LIMIT_TX_ACTIVE ) + #define TCP_FLOW_LOSS_RECOVERY(x) ((x) == TOE_FLOW_STATE_LOSS_RECOVERY ) + #define TCP_FLOW_FAST_RETX(x) ((x) >= TOE_FLOW_STATE_FAST_RETX_INIT1 \ + && (x) <= TOE_FLOW_STATE_FAST_RECOVERY_ACTIVE) + #define TCP_FLOW_FAST_RECOVERY(x) ((x) >= TOE_FLOW_STATE_FAST_RECOVERY_INIT1) + u8_t l4ctx_tcp_partial_ack_cnt; + u8_t l4ctx_timer1_mode; // timer1 is overloaded for retx, persist, sws prevention and FIN_WAIT2 timer + #define TIMER1_RETX_MODE (0) + #define TIMER1_PERSIST_MODE (1) + #define TIMER1_SWS_PREVENT_MODE (2) + #define TIMER1_FIN_WAIT2_MODE (3) + u8_t l4ctx_ooo_fin_upload_state; + #define OOO_FIN_UPLOAD_IDLE (0<<0) + #define OOO_FIN_UPLOAD_DEFER (1<<0) + #define OOO_FIN_UPLOAD_NOW (2<<0) + #define OOO_FIN_UPLOAD_DONE (3<<0) + #define OOO_FIN_UPLOAD_DEFER_PENDING (4<<0) + #define OOO_FIN_UPLOAD_UNKNOWN (5<<0) + u32_t l4ctx_last_fin_seq; // last rx seq # in FIN packet + u8_t l4ctx_persist_probe_cnt; + u8_t l4ctx_reload_comp_status; + #define RELOAD_COMP_IDLE (0<<0) + #define RELOAD_COMP_HOST_PENDING (1<<0) + #define RELOAD_COMP_ONCHIP_PENDING (2<<0) + u8_t l4ctx_tx_flags; + #define L4CTX_TX_FLAGS_IN_COALESCE (1<<1) + #define L4CTX_TX_FLAGS_IND_SILLY_WIN (1<<2) + #define L4CTX_TX_FLAGS_LARGE_BD (1<<3) + u8_t l4ctx_ka_probe_cnt; + + u32_t l4ctx_tcp_disconnect_seq; // last snd seq # before disconnecting + u32_t l4ctx_tcp_snd_recover; + u32_t l4ctx_reply_ts; + #define TOE_RTT_SAMPLED (1<<0) + u16_t l4ctx_ka_timeout_tick; + u16_t l4ctx_ka_interval_tick; + + u8_t l4ctx_tx_comp_prod; + u8_t l4ctx_tx_comp_cons; + u8_t l4ctx_ka_max_probe_cnt; + u8_t l4ctx_in_generic; + + u32_t l4ctx_host_win_update; + u16_t l4ctx_cam_index; + u16_t l4ctx_gen_buff_accum; +} l4_context_b_t; + + + + +/* + * l4_context_l definition + */ +typedef struct l4_context_l +{ + u8_t l4ctx_gen_bd_cid; + u8_t l4ctx_bd_pre_read; + u8_t l4ctx_size; + u8_t l4ctx_ctx_type; + #define L4CTX_TYPE_TYPE (0xf<<4) + #define L4CTX_TYPE_TYPE_EMPTY (0<<4) + #define L4CTX_TYPE_TYPE_L2 (1<<4) + #define L4CTX_TYPE_TYPE_TCP (2<<4) + #define L4CTX_TYPE_TYPE_L5 (3<<4) + #define L4CTX_TYPE_TYPE_L2_BD_CHN (4<<4) + #define L4CTX_TYPE_TYPE_ISCSI (5<<4) + + u8_t l4ctx_challenge_ack_state; // refer to tcpm-tcpsecure-09 requirement + u8_t l4ctx_force_ack_pending; + u8_t l4ctx_oubits; + #define L4CTX_OUBITS_ACTIVATE (1<<0) + #define L4CTX_OUBITS_CP_UPLOAD (1<<1) + #define L4CTX_OUBITS_RXP_UPLOAD (1<<2) + #define L4CTX_OUBITS_TXP_UPLOAD (1<<3) + #define L4CTX_OUBITS_COM_RX_UPLOAD (1<<4) + #define L4CTX_OUBITS_COM_TX_UPLOAD (1<<5) + #define L4CTX_OUBITS_CP_UPLOAD_COMP (1<<6) + + u8_t l4ctx_gen_bd_max; + u8_t l4ctx_tcp_retx_defer; + u8_t unused; + u16_t l4ctx_tcp_pgid; + u32_t l4ctx_tcp_timer1; + #define L4CTX_TCP_TIMER1_DISABLE (1UL<<0) + #define L4CTX_TCP_TIMER1_VALUE (0x7fffffffL<<1) + + u16_t l4ctx_tcp_timer3; + #define L4CTX_TCP_TIMER3_DISABLE (1<<0) + #define L4CTX_TCP_TIMER3_VALUE (0x7fff<<1) + + u16_t l4ctx_tcp_timer2; + #define L4CTX_TCP_TIMER2_DISABLE (1<<0) + #define L4CTX_TCP_TIMER2_VALUE (0x7fff<<1) + + u16_t l4ctx_tcp_timer5; + #define L4CTX_TCP_TIMER5_DISABLE (1<<0) + #define L4CTX_TCP_TIMER5_VALUE (0x7fff<<1) + + u16_t l4ctx_tcp_timer4; + #define L4CTX_TCP_TIMER4_DISABLE (1<<0) + #define L4CTX_TCP_TIMER4_VALUE (0x7fff<<1) + + u32_t l4ctx_tcp_snd_wl1; + u32_t l4ctx_tcp_snd_wl2; + u8_t l4ctx_tcp_modes; + #define L4CTX_TCP_MODES_RST_INDICATED (1<<0) + #define L4CTX_TCP_MODES_DISC_BD (1<<1) + #define L4CTX_TCP_MODES_UPLOAD_INITED (1<<2) + #define L4CTX_TCP_MODES_RMT_DISC (1<<3) + #define L4CTX_TCP_MODES_PG_INVALIDATED (1<<4) + #define L4CTX_TCP_MODES_ABORT_PENDING (1<<5) + #define L4CTX_TCP_MODES_DISC_PENDING (1<<6) + #define L4CTX_TCP_MODES_SS (1<<7) + + u8_t l4ctx_tcp_dack; + u8_t l4ctx_tcp_tos; + u8_t l4ctx_tcp_ttl; + u32_t l4ctx_tcp_max_adv_win; + u32_t l4ctx_tcp_rto_intvl; // current unbounded retransmission timeout (RTO) + u32_t l4ctx_tcp_ip_src; + u32_t l4ctx_tcp_ip_dst; + u8_t l4ctx_tcp_tcp_hlen; + u8_t l4ctx_tcp_rcv_seg_scale; + u8_t l4ctx_tcp_snd_seg_scale; + u8_t l4ctx_tcp_iphdr_nbytes; + u16_t l4ctx_tcp_dst_port; + u16_t l4ctx_tcp_src_port; + u8_t l4ctx_tcp_state; + #define L4CTX_TCP_STATE_VALUE (0xff<<0) + #define L4CTX_TCP_STATE_VALUE_UNDEFINED (0<<0) + #define L4CTX_TCP_STATE_VALUE_LISTEN (2<<0) + #define L4CTX_TCP_STATE_VALUE_SYN_SENT (4<<0) + #define L4CTX_TCP_STATE_VALUE_SYN_RECV (6<<0) + #define L4CTX_TCP_STATE_VALUE_CLOSE_WAIT (8<<0) + #define L4CTX_TCP_STATE_VALUE_ESTABLISHED (10<<0) + #define L4CTX_TCP_STATE_VALUE_FIN_WAIT1 (12<<0) + #define L4CTX_TCP_STATE_VALUE_FIN_WAIT2 (14<<0) + #define L4CTX_TCP_STATE_VALUE_TIME_WAIT (16<<0) + #define L4CTX_TCP_STATE_VALUE_CLOSED (18<<0) + #define L4CTX_TCP_STATE_VALUE_LAST_ACK (20<<0) + #define L4CTX_TCP_STATE_VALUE_CLOSING (22<<0) + #define L4CTX_TCP_STATE_VALUE_ABORT_CONNECTION (24<<0) + + u8_t l4ctx_tcp_flags; + #define L4CTX_TCP_FLAGS_NO_DELAY_ACK (1<<0) + #define L4CTX_TCP_FLAGS_KEEP_ALIVE (1<<1) + #define L4CTX_TCP_FLAGS_NAGLE (1<<2) + #define L4CTX_TCP_FLAGS_TIME_STAMP (1<<3) + #define L4CTX_TCP_FLAGS_SACK (1<<4) + #define L4CTX_TCP_FLAGS_SEG_SCALING (1<<5) + #define L4CTX_TCP_FLAGS_OPTION2 (1<<6) + #define L4CTX_TCP_FLAGS_SEND_SYN (1<<7) + + u16_t l4ctx_tcp_mss; + u32_t l4ctx_tcp_rcv_next; + u32_t l4ctx_last_ack_sent; + u32_t l4ctx_tcp_rcv_win_seq; + u32_t l4ctx_tcp_snd_una; + u32_t l4ctx_tcp_snd_next; + u32_t l4ctx_tcp_snd_max; + u32_t l4ctx_tcp_snd_win; + u32_t l4ctx_tcp_snd_cwin; + u32_t l4ctx_tcp_tstamp; + u32_t l4ctx_tcp_ssthresh; + u16_t l4ctx_tcp_sm_delta; + u16_t l4ctx_tcp_sm_rtt; + u32_t l4ctx_tcp_max_snd_win; + u32_t l4ctx_tcp_tsch_snd_next; + u32_t l4ctx_tcp_slot_size; + #define L4CTX_TCP_SLOT_SIZE_SLOT_SIZE (0xffffffL<<0) + #define L4CTX_TCP_SLOT_SIZE_CMD_MAX (0x7fL<<24) + #define L4CTX_TCP_SLOT_SIZE_STOP (1UL<<31) + + u8_t l4ctx_tcp_tsch_xnum; + #define L4CTX_TCP_TSCH_XNUM_VAL (0x7f<<0) + #define L4CTX_TCP_TSCH_XNUM_L4 (1<<7) + + u8_t l4ctx_tcp_cons_retx_num; + u8_t l4ctx_tcp_tsch_cmd; + u8_t l4ctx_tcp_cp_cmd; + u8_t l4ctx_tcp_tsch_cons_retx_num; + u8_t l4ctx_tcp_prod_retx_num; + u8_t l4ctx_tcp_tx_protocol_flags; + u8_t l4ctx_tcp_num_dupack; + u8_t l4ctx_tcp_txp_cmd; + u8_t l4ctx_tcp_upload_reason; + #define L4CTX_TCP_UPLOAD_REASON_KEEP_ALIVE (1<<0) + #define L4CTX_TCP_UPLOAD_REASON_FIN (1<<1) + #define L4CTX_TCP_UPLOAD_REASON_URG (1<<2) + #define L4CTX_TCP_UPLOAD_REASON_FRAGMENT (1<<3) + #define L4CTX_TCP_UPLOAD_REASON_IP_OPTION (1<<4) + #define L4CTX_TCP_UPLOAD_REASON_RST (1<<5) + #define L4CTX_TCP_UPLOAD_REASON_SYN (1<<6) + #define L4CTX_TCP_UPLOAD_REASON_TIMEOUT (1<<7) + + u8_t l4ctx_tcp_num_retx; + u8_t l4ctx_tcp_comp_cons_retx_num; + u32_t l4ctx_tcp_offload_seq; + tcp_context_cmd_cell_te_t l4ctx_cmd[1]; + u16_t l4ctx_l4_bd_chain_host_bdidx; + u8_t l4ctx_l4_bd_chain_host_gen_count; + u8_t l4ctx_l4_bd_chain_v2p_proc1flags; + #define L4CTX_L4_BD_CHAIN_V2P_PROC1FLAGS_BD_CHN_FLUSH (1<<0) + #define L4CTX_L4_BD_CHAIN_V2P_PROC1FLAGS_BD_CHN_FORCE_PUSH (1<<1) + u32_t l4ctx_l4_bd_chain_host_bseq; + u32_t l4ctx_l4_bd_chain_nx_bdhaddr_hi; + u32_t l4ctx_l4_bd_chain_nx_bdhaddr_lo; + u32_t l4ctx_l4_bd_chain_nx_seq; + u16_t l4ctx_l4_bd_chain_nx_bdidx; + u8_t l4ctx_l4_bd_chain_v2p_gen_count; + u8_t l4ctx_l4_bd_chain_v2p_flags; + u16_t l4ctx_l4_bd_chain_nx_boff; + u16_t l4ctx_l4_bd_chain_gen_used; + u32_t l4ctx_l4_bd_chain_cmpl_seq; + u32_t l4ctx_l4_bd_chain_cmpl_bdhaddr_hi; + u32_t l4ctx_l4_bd_chain_cmpl_bdhaddr_lo; + u16_t l4ctx_l4_bd_chain_cmpl_bdidx; + u16_t l4ctx_l4_bd_chain_gen_size; + u32_t l4ctx_l4_bd_chain_io_seq; + u32_t l4ctx_l4_bd_chain_hole_seq; + u32_t l4ctx_l4_bd_chain_end_seq; + u32_t l4ctx_l4_bd_chain_bseq_lead; + u32_t l4ctx_l4_bd_chain_push_seq; + u32_t l4ctx_l4_bd_chain_gen_start_seq; + u32_t l4ctx_l4_bd_chain_gen_seq; + u32_t l4ctx_l4_bd_chain_gen_bfr_hi; + u32_t l4ctx_l4_bd_chain_gen_bfr_lo; + u32_t l4ctx_tx_comp_step; + u16_t l4ctx_total_rt_tick; // total retransmit timeout (in ticks) + u16_t l4ctx_max_rt_tick; // maximum total retransmit timeout (in ticks) + u32_t l4ctx_ooo_fin_seq; + u32_t l4ctx_unused; + u32_t l4ctx_tcp_last_rcv_win_seq; + u32_t l4ctx_tcp_save_cwin; + u8_t l4ctx_ooo_fin_upload_state; + u8_t l4ctx_timer1_mode; // timer1 is overloaded for retx, persist, sws prevention and FIN_WAIT2 timer + u8_t l4ctx_tcp_partial_ack_cnt; + u8_t l4ctx_tcp_flow_state; + #define TOE_FLOW_STATE_NORMAL_INIT (0<<0) + #define TOE_FLOW_STATE_NORMAL_RUNNING (1<<0) + #define TOE_FLOW_STATE_LIMIT_TX_ACTIVE (2<<0) + #define TOE_FLOW_STATE_IN_LOSS_RECOVERY (3<<0) + #define TOE_FLOW_STATE_FAST_RETX_INIT1 (4<<0) + #define TOE_FLOW_STATE_FAST_RETX_INIT2 (5<<0) + #define TOE_FLOW_STATE_FAST_RETX_RELOAD (6<<0) + #define TOE_FLOW_STATE_FAST_RETX_ACTIVE1 (7<<0) + #define TOE_FLOW_STATE_FAST_RETX_ACTIVE2 (8<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_INIT1 (9<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_INIT2 (10<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_ACTIVE (11<<0) + #define TOE_FLOW_STATE_FAST_RECOVERY_EXIT (12<<0) + u32_t l4ctx_last_fin_seq; // last rx seq # in FIN packet + u8_t l4ctx_ka_probe_cnt; + u8_t l4ctx_tx_flags; + #define L4CTX_TX_FLAGS_IN_COALESCE (1<<1) + #define L4CTX_TX_FLAGS_IND_SILLY_WIN (1<<2) + u8_t l4ctx_reload_comp_status; + #define RELOAD_COMP_IDLE (0<<0) + #define RELOAD_COMP_HOST_PENDING (1<<0) + #define RELOAD_COMP_ONCHIP_PENDING (2<<0) + u8_t l4ctx_persist_probe_cnt; + u32_t l4ctx_tcp_disconnect_seq; // last snd seq # before disconnecting + u32_t l4ctx_tcp_snd_recover; + u32_t l4ctx_reply_ts; + #define TOE_RTT_SAMPLED (1<<0) + u16_t l4ctx_ka_interval; + u16_t l4ctx_ka_timeout; + u8_t l4ctx_in_generic; + u8_t l4ctx_ka_max_probe_cnt; + u8_t l4ctx_tx_comp_con; + u8_t l4ctx_tx_comp_prod; + u32_t l4ctx_host_win_update; + u16_t l4ctx_gen_buff_accum; + u16_t l4ctx_cam_index; +} l4_context_l_t; + + + + + +/* + * l4_context select + */ +#if defined(LITTLE_ENDIAN) + typedef l4_context_l_t l4_context_t; +#elif defined(BIG_ENDIAN) + typedef l4_context_b_t l4_context_t; +#endif + + +#endif /* _TOE_CTX_H */ + diff --git a/usr/src/uts/common/io/bnx/570x/common/include/tpat_hsi.h b/usr/src/uts/common/io/bnx/570x/common/include/tpat_hsi.h new file mode 100644 index 0000000000..16d019df63 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/tpat_hsi.h @@ -0,0 +1,79 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _TPAT_HSI_H +#define _TPAT_HSI_H + +// Offset of xxx_hsi in 32 bit words from beginning of scratchpad +#define TPAT_HSI_OFFSET 0x104 + +typedef struct _tpat_hsi_t { + fw_version_t version; + u32_t l2_pseudo_checksum; + u32_t num_catchup_processed; + u32_t num_catchup_pause ; + // Debug + u32_t tpat_num_complete; + u32_t tpat_udp_patchup; + u32_t fault_insertion; + u32_t l4_segment_count; + // Catchup overide for RSS + u32_t catchup_overide; + u64_t unicast_bytes_xmit; + u64_t multicast_bytes_xmit; + u64_t broadcast_bytes_xmit; + u64_t volatile idle_count; + u32_t iscsi_ctx_num_tasks; // size of task array in iSCSI context + u32_t iscsi_ctx_num_ccells; // size of command queue in iSCSI context + u64_t iscsi_unicast_bytes_xmit; + u64_t iscsi_multicast_bytes_xmit; + u64_t iscsi_broadcast_bytes_xmit; + u32_t iscsi_teton_task_offset; // Teton only: offset of the task array + u32_t iscsi_teton_l5_offset; // Teton only: offset of L5 section + u64_t total_bytes_xmit; +}tpat_hsi_t; + +// This macro can be used for little or big endian 32-bit system +#define TPAT_HSI_OFFSETOFF(m) (OFFSETOF(tpat_hsi_t,m) + 0x410) +#define TPAT_HSI_SIZEOF(m) (sizeof (((tpat_hsi_t *)0)->m)) + +// Calling the following macro will actually get optimized during compile +// time. Its sole purpose is to ensure HSI variables cannot be modified/moved +// unnoticed scratch[3072] 0xa0000 (RW/Reset: undefined) +#define TEST_TPAT_HSI(){ \ +if (0){ \ + 1/(TPAT_HSI_OFFSETOFF(version) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x000) && \ + TPAT_HSI_OFFSETOFF(l2_pseudo_checksum) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x010) && \ + TPAT_HSI_OFFSETOFF(num_catchup_processed) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x014) && \ + TPAT_HSI_OFFSETOFF(num_catchup_pause) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x018) && \ + TPAT_HSI_OFFSETOFF(tpat_num_complete) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x01c) && \ + TPAT_HSI_OFFSETOFF(tpat_udp_patchup) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x020) && \ + TPAT_HSI_OFFSETOFF(fault_insertion) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x024) && \ + TPAT_HSI_OFFSETOFF(l4_segment_count) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x028) && \ + TPAT_HSI_OFFSETOFF(catchup_overide) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x02c) && \ + TPAT_HSI_OFFSETOFF(unicast_bytes_xmit) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x030) && \ + TPAT_HSI_OFFSETOFF(multicast_bytes_xmit) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x038) && \ + TPAT_HSI_OFFSETOFF(broadcast_bytes_xmit) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x040) && \ + TPAT_HSI_OFFSETOFF(idle_count) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x048) && \ + TPAT_HSI_OFFSETOFF(iscsi_ctx_num_tasks) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x050) && \ + TPAT_HSI_OFFSETOFF(iscsi_ctx_num_ccells) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x054) && \ + TPAT_HSI_OFFSETOFF(iscsi_unicast_bytes_xmit) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x058) && \ + TPAT_HSI_OFFSETOFF(iscsi_multicast_bytes_xmit) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x060) && \ + TPAT_HSI_OFFSETOFF(iscsi_broadcast_bytes_xmit) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x068) && \ + TPAT_HSI_OFFSETOFF(iscsi_teton_task_offset) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x070) && \ + TPAT_HSI_OFFSETOFF(iscsi_teton_l5_offset) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x074) && \ + TPAT_HSI_OFFSETOFF(total_bytes_xmit) == (TPAT_HSI_OFFSET * sizeof(u32_t) + 0x078) && \ + TPAT_HSI_OFFSETOFF(total_bytes_xmit)+TPAT_HSI_SIZEOF(total_bytes_xmit) == (TPAT_HSI_OFFSET * sizeof(u32_t) + sizeof(tpat_hsi_t)));}} +#endif + diff --git a/usr/src/uts/common/io/bnx/570x/common/include/txp_hsi.h b/usr/src/uts/common/io/bnx/570x/common/include/txp_hsi.h new file mode 100644 index 0000000000..16a3a6bce7 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/common/include/txp_hsi.h @@ -0,0 +1,103 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _TXP_HSI_H +#define _TXP_HSI_H + +// Offset of xxx_hsi in 32 bit words from beginning of scratchpad +#define TXP_HSI_OFFSET 0x4 + +typedef struct _txp_hsi_t { + fw_version_t version; + u32_t cu_rate_limiter_enable; + u32_t min_rto_tick; + u32_t max_rto_tick; + u32_t txp_os_flag; + #define OS_LH (1<<0) + u32_t invalid_ctx_cnt; // unknown context type entries + u32_t cmpl_cnt; // count of tx completion + u32_t non_zero_slot_cnt; + u32_t txp_cid_last; + u32_t txp_oubits; + u32_t txpq_protocol_flags; + u32_t txp_append_context; + u32_t txp_overide_catchup; + u32_t txp_comxq_seq; + u32_t tsch_reset; + u32_t iscsi_ctx_num_tasks; // size of task array in iSCSI context + u32_t iscsi_ctx_num_ccells; // size of command queue in iSCSI context + u32_t txp_tdbcThrhld; + u32_t num_retx_flushes; // number of retransmit flush + u64_t volatile idle_count; + u64_t volatile idle_tdma; + u64_t volatile idle_ctx_lock; + u64_t volatile idle_hdrq; + u32_t txp_coalsce_cnt; + u32_t iscsi_teton_task_offset; // Teton only: offset of the task array + u32_t iscsi_teton_l5_offset; // Teton only: offset of L5 section + u32_t neg_slot_cnt; + u32_t sws_prevention_ticks; // sws (silly window syndrome) prevention timer (in Timer1 tick resolution) + u32_t tx_after_fin_cnt; // number of tx occurs after FIN + u32_t mtu_size; + u32_t bd_validation; +} txp_hsi_t; + +// This the default cache line parameter that used by tcp nagle alogrithm +#define DEFAULT_TDBCTRHLD 29 /* 29 cached line free */ +#define NAGLE_TDBCTRHLD 22 /* 22 cached line free */ + +// This macro can be used for little or big endian 32-bit system +#define TXP_HSI_OFFSETOFF(m) (OFFSETOF(txp_hsi_t,m) + 0x10) +#define TXP_HSI_SIZEOF(m) (sizeof (((txp_hsi_t *)0)->m)) + +// Calling the following macro will actually get optimized during compile +// time. Its sole purpose is to ensure HSI variables cannot be modified/moved +// unnoticed scratch[8192] 0x60000 (RW/Reset: undefined) +#define TEST_TXP_HSI(){ \ +if (0){ \ + 1/(TXP_HSI_OFFSETOFF(version) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x000) && \ + TXP_HSI_OFFSETOFF(cu_rate_limiter_enable) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x010) && \ + TXP_HSI_OFFSETOFF(min_rto_tick) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x014) && \ + TXP_HSI_OFFSETOFF(max_rto_tick) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x018) && \ + TXP_HSI_OFFSETOFF(txp_os_flag) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x01c) && \ + TXP_HSI_OFFSETOFF(invalid_ctx_cnt) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x020) && \ + TXP_HSI_OFFSETOFF(cmpl_cnt) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x024) && \ + TXP_HSI_OFFSETOFF(non_zero_slot_cnt) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x028) && \ + TXP_HSI_OFFSETOFF(txp_cid_last) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x02c) && \ + TXP_HSI_OFFSETOFF(txp_oubits) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x030) && \ + TXP_HSI_OFFSETOFF(txpq_protocol_flags) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x034) && \ + TXP_HSI_OFFSETOFF(txp_append_context) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x038) && \ + TXP_HSI_OFFSETOFF(txp_overide_catchup) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x03c) && \ + TXP_HSI_OFFSETOFF(txp_comxq_seq) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x040) && \ + TXP_HSI_OFFSETOFF(tsch_reset) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x044) && \ + TXP_HSI_OFFSETOFF(iscsi_ctx_num_tasks) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x048) && \ + TXP_HSI_OFFSETOFF(iscsi_ctx_num_ccells) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x04c) && \ + TXP_HSI_OFFSETOFF(txp_tdbcThrhld) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x050) && \ + TXP_HSI_OFFSETOFF(num_retx_flushes) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x054) && \ + TXP_HSI_OFFSETOFF(idle_count) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x058) && \ + TXP_HSI_OFFSETOFF(idle_tdma) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x060) && \ + TXP_HSI_OFFSETOFF(idle_ctx_lock) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x068) && \ + TXP_HSI_OFFSETOFF(idle_hdrq) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x070) && \ + TXP_HSI_OFFSETOFF(txp_coalsce_cnt) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x078) && \ + TXP_HSI_OFFSETOFF(iscsi_teton_task_offset) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x07c) && \ + TXP_HSI_OFFSETOFF(iscsi_teton_l5_offset) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x080) && \ + TXP_HSI_OFFSETOFF(neg_slot_cnt) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x084) && \ + TXP_HSI_OFFSETOFF(sws_prevention_ticks) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x088) && \ + TXP_HSI_OFFSETOFF(tx_after_fin_cnt) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x08c) && \ + TXP_HSI_OFFSETOFF(mtu_size) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x090) && \ + TXP_HSI_OFFSETOFF(bd_validation) == (TXP_HSI_OFFSET * sizeof(u32_t) + 0x094) && \ + TXP_HSI_OFFSETOFF(bd_validation)+TXP_HSI_SIZEOF(bd_validation) == (TXP_HSI_OFFSET * sizeof(u32_t) + sizeof(txp_hsi_t)));}} + +#endif + diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_cpu.c b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_cpu.c new file mode 100644 index 0000000000..aa5cfd9069 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_cpu.c @@ -0,0 +1,858 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "lm5706.h" +#include "rxpfw.h" +#include "txpfw.h" +#include "tpatfw.h" +#include "comfw.h" +#include "cpfw.h" +#include "rv2p_p1.h" +#include "rv2p_p2.h" +#include "xi_rv2p_p1.h" +#include "xi_rv2p_p2.h" +#include "xi90_rv2p_p1.h" +#include "xi90_rv2p_p2.h" +#include "xinanfw.h" + + + +/******************************************************************************* + * CPU register info. + ******************************************************************************/ + +typedef struct _cpu_reg_t +{ + u32_t mode; + u32_t mode_value_halt; + u32_t mode_value_sstep; + + u32_t state; + u32_t state_value_clear; + + u32_t gpr0; + u32_t evmask; + u32_t pc; + u32_t inst; + u32_t bp; + + u32_t spad_base; + + u32_t mips_view_base; +} cpu_reg_t; + + + +/******************************************************************************* + * Firmware info. + ******************************************************************************/ + +typedef struct _fw_info_t +{ + u32_t ver_major; + u32_t ver_minor; + u32_t ver_fix; + + u32_t start_addr; + + /* Text section. */ + u32_t text_addr; + u32_t text_len; + u32_t text_index; + u32_t *text; + + /* Data section. */ + u32_t data_addr; + u32_t data_len; + u32_t data_index; + u32_t *data; + + /* SBSS section. */ + u32_t sbss_addr; + u32_t sbss_len; + u32_t sbss_index; + u32_t *sbss; + + /* BSS section. */ + u32_t bss_addr; + u32_t bss_len; + u32_t bss_index; + u32_t *bss; + + /* Read-only section. */ + u32_t rodata_addr; + u32_t rodata_len; + u32_t rodata_index; + u32_t *rodata; +} fw_info_t; + + + +#define RV2P_PROC1 0 +#define RV2P_PROC2 1 +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +load_rv2p_fw( + lm_device_t *pdev, + u32_t *rv2p_code, + u32_t rv2p_code_len, + u32_t rv2p_proc) +{ + u32_t idx; + u32_t val; + + DbgBreakIf(rv2p_proc != RV2P_PROC1 && rv2p_proc != RV2P_PROC2); + + for(idx = 0; idx < rv2p_code_len; idx += 8) + { + REG_WR(pdev, rv2p.rv2p_instr_high, *rv2p_code); + rv2p_code++; + REG_WR(pdev, rv2p.rv2p_instr_low, *rv2p_code); + rv2p_code++; + + if(rv2p_proc == RV2P_PROC1) + { + val = (idx/8) | RV2P_PROC1_ADDR_CMD_RDWR; + REG_WR(pdev, rv2p.rv2p_proc1_addr_cmd, val); + } + else + { + val = (idx/8) | RV2P_PROC2_ADDR_CMD_RDWR; + REG_WR(pdev, rv2p.rv2p_proc2_addr_cmd, val); + } + } + + /* Reset the processor, un-stall is done later. */ + if(rv2p_proc == RV2P_PROC1) + { + REG_WR(pdev, rv2p.rv2p_command, RV2P_COMMAND_PROC1_RESET); + } + else + { + REG_WR(pdev, rv2p.rv2p_command, RV2P_COMMAND_PROC2_RESET); + } +} /* load_rv2p_fw */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +load_cpu_fw( + lm_device_t *pdev, + cpu_reg_t *cpu_reg, + fw_info_t *fw) +{ + u32_t val; + + /* Halt the CPU. */ + REG_RD_IND(pdev, cpu_reg->mode, &val); + val |= cpu_reg->mode_value_halt; + REG_WR_IND(pdev, cpu_reg->mode, val); + REG_WR_IND(pdev, cpu_reg->state, cpu_reg->state_value_clear); + + /* Load the Text area. */ + if(fw->text) + { + lm_reg_wr_blk( + pdev, + cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base), + fw->text, + fw->text_len/4); + } + + /* Load the Data area. */ + if(fw->data) + { + lm_reg_wr_blk( + pdev, + cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base), + fw->data, + fw->data_len/4); + } + + /* Load the SBSS area. */ + if(fw->sbss) + { + lm_reg_wr_blk( + pdev, + cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base), + fw->sbss, + fw->sbss_len/4); + } + + /* Load the BSS area. */ + if(fw->bss) + { + lm_reg_wr_blk( + pdev, + cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base), + fw->bss, + fw->bss_len/4); + } + + /* Load the Read-Only area. */ + if(fw->rodata) + { + lm_reg_wr_blk( + pdev, + cpu_reg->spad_base + (fw->rodata_addr - cpu_reg->mips_view_base), + fw->rodata, + fw->rodata_len/4); + } + + /* Clear the pre-fetch instruction. */ + REG_WR_IND(pdev, cpu_reg->inst, 0); + REG_WR_IND(pdev, cpu_reg->pc, fw->start_addr); + + /* Start the CPU. */ + REG_RD_IND(pdev, cpu_reg->mode, &val); + val &= ~cpu_reg->mode_value_halt; + REG_WR_IND(pdev, cpu_reg->state, cpu_reg->state_value_clear); + REG_WR_IND(pdev, cpu_reg->mode, val); +} /* load_cpu_fw */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_5706_cpus( + lm_device_t *pdev, + u32_t cpu_mask) +{ + cpu_reg_t cpu_reg; + fw_info_t fw; + + DbgBreakIf( + CHIP_NUM(pdev) != CHIP_NUM_5706 && + CHIP_NUM(pdev) != CHIP_NUM_5708); + + if(cpu_mask & CPU_RXP) + { + cpu_reg.mode = OFFSETOF(reg_space_t, rxp.rxp_cpu_mode); + cpu_reg.mode_value_halt = RXP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = RXP_CPU_MODE_STEP_ENA; + cpu_reg.state = OFFSETOF(reg_space_t, rxp.rxp_cpu_state); + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = OFFSETOF(reg_space_t, rxp.rxp_cpu_reg_file[0]); + cpu_reg.evmask = OFFSETOF(reg_space_t, rxp.rxp_cpu_event_mask); + cpu_reg.pc = OFFSETOF(reg_space_t, rxp.rxp_cpu_program_counter); + cpu_reg.inst = OFFSETOF(reg_space_t, rxp.rxp_cpu_instruction); + cpu_reg.bp = OFFSETOF(reg_space_t, rxp.rxp_cpu_hw_breakpoint); + cpu_reg.spad_base = OFFSETOF(reg_space_t, rxp.rxp_scratch[0]); + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = RXP_b06FwReleaseMajor; + fw.ver_minor = RXP_b06FwReleaseMinor; + fw.ver_fix = RXP_b06FwReleaseFix; + fw.start_addr = RXP_b06FwStartAddr; + + fw.text_addr = RXP_b06FwTextAddr; + fw.text_len = RXP_b06FwTextLen; + fw.text_index = 0; + fw.text = RXP_b06FwText; + + fw.data_addr = RXP_b06FwDataAddr; + fw.data_len = RXP_b06FwDataLen; + fw.data_index = 0; + fw.data = RXP_b06FwData; + + fw.sbss_addr = RXP_b06FwSbssAddr; + fw.sbss_len = RXP_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = RXP_b06FwSbss; + + fw.bss_addr = RXP_b06FwBssAddr; + fw.bss_len = RXP_b06FwBssLen; + fw.bss_index = 0; + fw.bss = RXP_b06FwBss; + + fw.rodata_addr = RXP_b06FwRodataAddr; + fw.rodata_len = RXP_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = RXP_b06FwRodata; + + load_cpu_fw(pdev, &cpu_reg, &fw); + } + + if(cpu_mask & CPU_TXP) + { + cpu_reg.mode = OFFSETOF(reg_space_t, txp.txp_cpu_mode); + cpu_reg.mode_value_halt = TXP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = TXP_CPU_MODE_STEP_ENA; + cpu_reg.state = OFFSETOF(reg_space_t, txp.txp_cpu_state); + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = OFFSETOF(reg_space_t, txp.txp_cpu_reg_file[0]); + cpu_reg.evmask = OFFSETOF(reg_space_t, txp.txp_cpu_event_mask); + cpu_reg.pc = OFFSETOF(reg_space_t, txp.txp_cpu_program_counter); + cpu_reg.inst = OFFSETOF(reg_space_t, txp.txp_cpu_instruction); + cpu_reg.bp = OFFSETOF(reg_space_t, txp.txp_cpu_hw_breakpoint); + cpu_reg.spad_base = OFFSETOF(reg_space_t, txp.txp_scratch[0]); + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = TXP_b06FwReleaseMajor; + fw.ver_minor = TXP_b06FwReleaseMinor; + fw.ver_fix = TXP_b06FwReleaseFix; + fw.start_addr = TXP_b06FwStartAddr; + + fw.text_addr = TXP_b06FwTextAddr; + fw.text_len = TXP_b06FwTextLen; + fw.text_index = 0; + fw.text = TXP_b06FwText; + + fw.data_addr = TXP_b06FwDataAddr; + fw.data_len = TXP_b06FwDataLen; + fw.data_index = 0; + fw.data = TXP_b06FwData; + + fw.sbss_addr = TXP_b06FwSbssAddr; + fw.sbss_len = TXP_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = TXP_b06FwSbss; + + fw.bss_addr = TXP_b06FwBssAddr; + fw.bss_len = TXP_b06FwBssLen; + fw.bss_index = 0; + fw.bss = TXP_b06FwBss; + + fw.rodata_addr = TXP_b06FwRodataAddr; + fw.rodata_len = TXP_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = TXP_b06FwRodata; + + load_cpu_fw(pdev, &cpu_reg, &fw); + } + + if(cpu_mask & CPU_TPAT) + { + cpu_reg.mode = OFFSETOF(reg_space_t, tpat.tpat_cpu_mode); + cpu_reg.mode_value_halt = TPAT_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = TPAT_CPU_MODE_STEP_ENA; + cpu_reg.state = OFFSETOF(reg_space_t, tpat.tpat_cpu_state); + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = OFFSETOF(reg_space_t, tpat.tpat_cpu_reg_file[0]); + cpu_reg.evmask = OFFSETOF(reg_space_t, tpat.tpat_cpu_event_mask); + cpu_reg.pc = OFFSETOF(reg_space_t, tpat.tpat_cpu_program_counter); + cpu_reg.inst = OFFSETOF(reg_space_t, tpat.tpat_cpu_instruction); + cpu_reg.bp = OFFSETOF(reg_space_t, tpat.tpat_cpu_hw_breakpoint); + cpu_reg.spad_base = OFFSETOF(reg_space_t, tpat.tpat_scratch[0]); + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = TPAT_b06FwReleaseMajor; + fw.ver_minor = TPAT_b06FwReleaseMinor; + fw.ver_fix = TPAT_b06FwReleaseFix; + fw.start_addr = TPAT_b06FwStartAddr; + + fw.text_addr = TPAT_b06FwTextAddr; + fw.text_len = TPAT_b06FwTextLen; + fw.text_index = 0; + fw.text = TPAT_b06FwText; + + fw.data_addr = TPAT_b06FwDataAddr; + fw.data_len = TPAT_b06FwDataLen; + fw.data_index = 0; + fw.data = TPAT_b06FwData; + + fw.sbss_addr = TPAT_b06FwSbssAddr; + fw.sbss_len = TPAT_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = TPAT_b06FwSbss; + + fw.bss_addr = TPAT_b06FwBssAddr; + fw.bss_len = TPAT_b06FwBssLen; + fw.bss_index = 0; + fw.bss = TPAT_b06FwBss; + + fw.rodata_addr = TPAT_b06FwRodataAddr; + fw.rodata_len = TPAT_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = TPAT_b06FwRodata; + + load_cpu_fw(pdev, &cpu_reg, &fw); + } + + if(cpu_mask & CPU_COM) + { + cpu_reg.mode = OFFSETOF(reg_space_t, com.com_cpu_mode); + cpu_reg.mode_value_halt = COM_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = COM_CPU_MODE_STEP_ENA; + cpu_reg.state = OFFSETOF(reg_space_t, com.com_cpu_state); + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = OFFSETOF(reg_space_t, com.com_cpu_reg_file[0]); + cpu_reg.evmask = OFFSETOF(reg_space_t, com.com_cpu_event_mask); + cpu_reg.pc = OFFSETOF(reg_space_t, com.com_cpu_program_counter); + cpu_reg.inst = OFFSETOF(reg_space_t, com.com_cpu_instruction); + cpu_reg.bp = OFFSETOF(reg_space_t, com.com_cpu_hw_breakpoint); + cpu_reg.spad_base = OFFSETOF(reg_space_t, com.com_scratch[0]); + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = COM_b06FwReleaseMajor; + fw.ver_minor = COM_b06FwReleaseMinor; + fw.ver_fix = COM_b06FwReleaseFix; + fw.start_addr = COM_b06FwStartAddr; + + fw.text_addr = COM_b06FwTextAddr; + fw.text_len = COM_b06FwTextLen; + fw.text_index = 0; + fw.text = COM_b06FwText; + + fw.data_addr = COM_b06FwDataAddr; + fw.data_len = COM_b06FwDataLen; + fw.data_index = 0; + fw.data = COM_b06FwData; + + fw.sbss_addr = COM_b06FwSbssAddr; + fw.sbss_len = COM_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = COM_b06FwSbss; + + fw.bss_addr = COM_b06FwBssAddr; + fw.bss_len = COM_b06FwBssLen; + fw.bss_index = 0; + fw.bss = COM_b06FwBss; + + fw.rodata_addr = COM_b06FwRodataAddr; + fw.rodata_len = COM_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = COM_b06FwRodata; + + load_cpu_fw(pdev, &cpu_reg, &fw); + } + + if(cpu_mask & CPU_CP) + { + cpu_reg.mode = OFFSETOF(reg_space_t, cp.cp_cpu_mode); + cpu_reg.mode_value_halt = CP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = CP_CPU_MODE_STEP_ENA; + cpu_reg.state = OFFSETOF(reg_space_t, cp.cp_cpu_state); + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = OFFSETOF(reg_space_t, cp.cp_cpu_reg_file[0]); + cpu_reg.evmask = OFFSETOF(reg_space_t, cp.cp_cpu_event_mask); + cpu_reg.pc = OFFSETOF(reg_space_t, cp.cp_cpu_program_counter); + cpu_reg.inst = OFFSETOF(reg_space_t, cp.cp_cpu_instruction); + cpu_reg.bp = OFFSETOF(reg_space_t, cp.cp_cpu_hw_breakpoint); + cpu_reg.spad_base = OFFSETOF(reg_space_t, cp.cp_scratch[0]); + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = CP_b06FwReleaseMajor; + fw.ver_minor = CP_b06FwReleaseMinor; + fw.ver_fix = CP_b06FwReleaseFix; + fw.start_addr = CP_b06FwStartAddr; + + fw.text_addr = CP_b06FwTextAddr; + fw.text_len = CP_b06FwTextLen; + fw.text_index = 0; + fw.text = CP_b06FwText; + + fw.data_addr = CP_b06FwDataAddr; + fw.data_len = CP_b06FwDataLen; + fw.data_index = 0; + fw.data = CP_b06FwData; + + fw.sbss_addr = CP_b06FwSbssAddr; + fw.sbss_len = CP_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = CP_b06FwSbss; + + fw.bss_addr = CP_b06FwBssAddr; + fw.bss_len = CP_b06FwBssLen; + fw.bss_index = 0; + fw.bss = CP_b06FwBss; + + fw.rodata_addr = CP_b06FwRodataAddr; + fw.rodata_len = CP_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = CP_b06FwRodata; + + load_cpu_fw(pdev, &cpu_reg, &fw); + } +} /* init_5706_cpus */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_5709_cpus( + lm_device_t *pdev, + u32_t cpu_mask) +{ + cpu_reg_t cpu_reg; + fw_info_t fw; + + DbgBreakIf(CHIP_NUM(pdev) != CHIP_NUM_5709); + + if(cpu_mask & CPU_RXP) + { + cpu_reg.mode = OFFSETOF(reg_space_t, rxp.rxp_cpu_mode); + cpu_reg.mode_value_halt = RXP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = RXP_CPU_MODE_STEP_ENA; + cpu_reg.state = OFFSETOF(reg_space_t, rxp.rxp_cpu_state); + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = OFFSETOF(reg_space_t, rxp.rxp_cpu_reg_file[0]); + cpu_reg.evmask = OFFSETOF(reg_space_t, rxp.rxp_cpu_event_mask); + cpu_reg.pc = OFFSETOF(reg_space_t, rxp.rxp_cpu_program_counter); + cpu_reg.inst = OFFSETOF(reg_space_t, rxp.rxp_cpu_instruction); + cpu_reg.bp = OFFSETOF(reg_space_t, rxp.rxp_cpu_hw_breakpoint); + cpu_reg.spad_base = OFFSETOF(reg_space_t, rxp.rxp_scratch[0]); + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = RXP_b09FwReleaseMajor; + fw.ver_minor = RXP_b09FwReleaseMinor; + fw.ver_fix = RXP_b09FwReleaseFix; + fw.start_addr = RXP_b09FwStartAddr; + + fw.text_addr = RXP_b09FwTextAddr; + fw.text_len = RXP_b09FwTextLen; + fw.text_index = 0; + fw.text = RXP_b09FwText; + + fw.data_addr = RXP_b09FwDataAddr; + fw.data_len = RXP_b09FwDataLen; + fw.data_index = 0; + fw.data = RXP_b09FwData; + + fw.sbss_addr = RXP_b09FwSbssAddr; + fw.sbss_len = RXP_b09FwSbssLen; + fw.sbss_index = 0; + fw.sbss = RXP_b09FwSbss; + + fw.bss_addr = RXP_b09FwBssAddr; + fw.bss_len = RXP_b09FwBssLen; + fw.bss_index = 0; + fw.bss = RXP_b09FwBss; + + fw.rodata_addr = RXP_b09FwRodataAddr; + fw.rodata_len = RXP_b09FwRodataLen; + fw.rodata_index = 0; + fw.rodata = RXP_b09FwRodata; + + load_cpu_fw(pdev, &cpu_reg, &fw); + } + + if(cpu_mask & CPU_TXP) + { + cpu_reg.mode = OFFSETOF(reg_space_t, txp.txp_cpu_mode); + cpu_reg.mode_value_halt = TXP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = TXP_CPU_MODE_STEP_ENA; + cpu_reg.state = OFFSETOF(reg_space_t, txp.txp_cpu_state); + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = OFFSETOF(reg_space_t, txp.txp_cpu_reg_file[0]); + cpu_reg.evmask = OFFSETOF(reg_space_t, txp.txp_cpu_event_mask); + cpu_reg.pc = OFFSETOF(reg_space_t, txp.txp_cpu_program_counter); + cpu_reg.inst = OFFSETOF(reg_space_t, txp.txp_cpu_instruction); + cpu_reg.bp = OFFSETOF(reg_space_t, txp.txp_cpu_hw_breakpoint); + cpu_reg.spad_base = OFFSETOF(reg_space_t, txp.txp_scratch[0]); + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = TXP_b09FwReleaseMajor; + fw.ver_minor = TXP_b09FwReleaseMinor; + fw.ver_fix = TXP_b09FwReleaseFix; + fw.start_addr = TXP_b09FwStartAddr; + + fw.text_addr = TXP_b09FwTextAddr; + fw.text_len = TXP_b09FwTextLen; + fw.text_index = 0; + fw.text = TXP_b09FwText; + + fw.data_addr = TXP_b09FwDataAddr; + fw.data_len = TXP_b09FwDataLen; + fw.data_index = 0; + fw.data = TXP_b09FwData; + + fw.sbss_addr = TXP_b09FwSbssAddr; + fw.sbss_len = TXP_b09FwSbssLen; + fw.sbss_index = 0; + fw.sbss = TXP_b09FwSbss; + + fw.bss_addr = TXP_b09FwBssAddr; + fw.bss_len = TXP_b09FwBssLen; + fw.bss_index = 0; + fw.bss = TXP_b09FwBss; + + fw.rodata_addr = TXP_b09FwRodataAddr; + fw.rodata_len = TXP_b09FwRodataLen; + fw.rodata_index = 0; + fw.rodata = TXP_b09FwRodata; + + load_cpu_fw(pdev, &cpu_reg, &fw); + } + + if(cpu_mask & CPU_TPAT) + { + cpu_reg.mode = OFFSETOF(reg_space_t, tpat.tpat_cpu_mode); + cpu_reg.mode_value_halt = TPAT_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = TPAT_CPU_MODE_STEP_ENA; + cpu_reg.state = OFFSETOF(reg_space_t, tpat.tpat_cpu_state); + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = OFFSETOF(reg_space_t, tpat.tpat_cpu_reg_file[0]); + cpu_reg.evmask = OFFSETOF(reg_space_t, tpat.tpat_cpu_event_mask); + cpu_reg.pc = OFFSETOF(reg_space_t, tpat.tpat_cpu_program_counter); + cpu_reg.inst = OFFSETOF(reg_space_t, tpat.tpat_cpu_instruction); + cpu_reg.bp = OFFSETOF(reg_space_t, tpat.tpat_cpu_hw_breakpoint); + cpu_reg.spad_base = OFFSETOF(reg_space_t, tpat.tpat_scratch[0]); + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = TPAT_b09FwReleaseMajor; + fw.ver_minor = TPAT_b09FwReleaseMinor; + fw.ver_fix = TPAT_b09FwReleaseFix; + fw.start_addr = TPAT_b09FwStartAddr; + + fw.text_addr = TPAT_b09FwTextAddr; + fw.text_len = TPAT_b09FwTextLen; + fw.text_index = 0; + fw.text = TPAT_b09FwText; + + fw.data_addr = TPAT_b09FwDataAddr; + fw.data_len = TPAT_b09FwDataLen; + fw.data_index = 0; + fw.data = TPAT_b09FwData; + + fw.sbss_addr = TPAT_b09FwSbssAddr; + fw.sbss_len = TPAT_b09FwSbssLen; + fw.sbss_index = 0; + fw.sbss = TPAT_b09FwSbss; + + fw.bss_addr = TPAT_b09FwBssAddr; + fw.bss_len = TPAT_b09FwBssLen; + fw.bss_index = 0; + fw.bss = TPAT_b09FwBss; + + fw.rodata_addr = TPAT_b09FwRodataAddr; + fw.rodata_len = TPAT_b09FwRodataLen; + fw.rodata_index = 0; + fw.rodata = TPAT_b09FwRodata; + + load_cpu_fw(pdev, &cpu_reg, &fw); + } + + if(cpu_mask & CPU_COM) + { + cpu_reg.mode = OFFSETOF(reg_space_t, com.com_cpu_mode); + cpu_reg.mode_value_halt = COM_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = COM_CPU_MODE_STEP_ENA; + cpu_reg.state = OFFSETOF(reg_space_t, com.com_cpu_state); + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = OFFSETOF(reg_space_t, com.com_cpu_reg_file[0]); + cpu_reg.evmask = OFFSETOF(reg_space_t, com.com_cpu_event_mask); + cpu_reg.pc = OFFSETOF(reg_space_t, com.com_cpu_program_counter); + cpu_reg.inst = OFFSETOF(reg_space_t, com.com_cpu_instruction); + cpu_reg.bp = OFFSETOF(reg_space_t, com.com_cpu_hw_breakpoint); + cpu_reg.spad_base = OFFSETOF(reg_space_t, com.com_scratch[0]); + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = COM_b09FwReleaseMajor; + fw.ver_minor = COM_b09FwReleaseMinor; + fw.ver_fix = COM_b09FwReleaseFix; + fw.start_addr = COM_b09FwStartAddr; + + fw.text_addr = COM_b09FwTextAddr; + fw.text_len = COM_b09FwTextLen; + fw.text_index = 0; + fw.text = COM_b09FwText; + + fw.data_addr = COM_b09FwDataAddr; + fw.data_len = COM_b09FwDataLen; + fw.data_index = 0; + fw.data = COM_b09FwData; + + fw.sbss_addr = COM_b09FwSbssAddr; + fw.sbss_len = COM_b09FwSbssLen; + fw.sbss_index = 0; + fw.sbss = COM_b09FwSbss; + + fw.bss_addr = COM_b09FwBssAddr; + fw.bss_len = COM_b09FwBssLen; + fw.bss_index = 0; + fw.bss = COM_b09FwBss; + + fw.rodata_addr = COM_b09FwRodataAddr; + fw.rodata_len = COM_b09FwRodataLen; + fw.rodata_index = 0; + fw.rodata = COM_b09FwRodata; + + load_cpu_fw(pdev, &cpu_reg, &fw); + } + + if(cpu_mask & CPU_CP) + { + cpu_reg.mode = OFFSETOF(reg_space_t, cp.cp_cpu_mode); + cpu_reg.mode_value_halt = CP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = CP_CPU_MODE_STEP_ENA; + cpu_reg.state = OFFSETOF(reg_space_t, cp.cp_cpu_state); + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = OFFSETOF(reg_space_t, cp.cp_cpu_reg_file[0]); + cpu_reg.evmask = OFFSETOF(reg_space_t, cp.cp_cpu_event_mask); + cpu_reg.pc = OFFSETOF(reg_space_t, cp.cp_cpu_program_counter); + cpu_reg.inst = OFFSETOF(reg_space_t, cp.cp_cpu_instruction); + cpu_reg.bp = OFFSETOF(reg_space_t, cp.cp_cpu_hw_breakpoint); + cpu_reg.spad_base = OFFSETOF(reg_space_t, cp.cp_scratch[0]); + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = CP_b09FwReleaseMajor; + fw.ver_minor = CP_b09FwReleaseMinor; + fw.ver_fix = CP_b09FwReleaseFix; + fw.start_addr = CP_b09FwStartAddr; + + fw.text_addr = CP_b09FwTextAddr; + fw.text_len = CP_b09FwTextLen; + fw.text_index = 0; + fw.text = CP_b09FwText; + + fw.data_addr = CP_b09FwDataAddr; + fw.data_len = CP_b09FwDataLen; + fw.data_index = 0; + fw.data = CP_b09FwData; + + fw.sbss_addr = CP_b09FwSbssAddr; + fw.sbss_len = CP_b09FwSbssLen; + fw.sbss_index = 0; + fw.sbss = CP_b09FwSbss; + + fw.bss_addr = CP_b09FwBssAddr; + fw.bss_len = CP_b09FwBssLen; + fw.bss_index = 0; + fw.bss = CP_b09FwBss; + + fw.rodata_addr = CP_b09FwRodataAddr; + fw.rodata_len = CP_b09FwRodataLen; + fw.rodata_index = 0; + fw.rodata = CP_b09FwRodata; + + load_cpu_fw(pdev, &cpu_reg, &fw); + } +} /* init_5709_cpus */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_init_cpus( + lm_device_t *pdev, + u32_t cpu_mask) +{ + DbgBreakIf( + CHIP_NUM(pdev) != CHIP_NUM_5706 && + CHIP_NUM(pdev) != CHIP_NUM_5708 && + CHIP_NUM(pdev) != CHIP_NUM_5709); + + if(CHIP_NUM(pdev) == CHIP_NUM_5706 || CHIP_NUM(pdev) == CHIP_NUM_5708) + { + if(cpu_mask & CPU_RV2P_1) + { + // Calling this macro prior to loading will change value of POST_WAIT_TIMEOUT + // This parameter dictates how long to wait before dropping L2 packet + // due to insufficient posted buffers + // 0 mean no waiting before dropping, 0xFFFF means maximum wait + if (pdev->params.fw_flow_control) + { + RV2P_PROC1_CHG_POST_WAIT_TIMEOUT(pdev->params.fw_flow_control_wait); + } + else + { + // No waiting if fw_flow_control is not enabled + RV2P_PROC1_CHG_POST_WAIT_TIMEOUT(0); + } + load_rv2p_fw(pdev, rv2p_proc1, sizeof(rv2p_proc1), RV2P_PROC1); + } + + if(cpu_mask & CPU_RV2P_2) + { + load_rv2p_fw(pdev, rv2p_proc2, sizeof(rv2p_proc2), RV2P_PROC2); + } + + init_5706_cpus(pdev, cpu_mask); + } + else if(CHIP_ID(pdev) == CHIP_ID_5709_A0 || CHIP_ID(pdev) == CHIP_ID_5709_A1) + { + if(cpu_mask & CPU_RV2P_1) + { + // Calling this macro prior to loading will change value of POST_WAIT_TIMEOUT + // This parameter dictates how long to wait before dropping L2 packet + // due to insufficient posted buffers + // 0 mean no waiting before dropping, 0xFFFF means maximum wait + if (pdev->params.fw_flow_control) + { + XI90_RV2P_PROC1_CHG_POST_WAIT_TIMEOUT(pdev->params.fw_flow_control_wait); + } + else + { + // No waiting if fw_flow_control is not enabled + XI90_RV2P_PROC1_CHG_POST_WAIT_TIMEOUT(0); + } + load_rv2p_fw( + pdev, + xi90_rv2p_proc1, + sizeof(xi90_rv2p_proc1), + RV2P_PROC1); + } + + if(cpu_mask & CPU_RV2P_2) + { + load_rv2p_fw( + pdev, + xi90_rv2p_proc2, + sizeof(xi90_rv2p_proc2), + RV2P_PROC2); + } + + init_5709_cpus(pdev, cpu_mask); + } + else + { + if(cpu_mask & CPU_RV2P_1) + { + // Calling this macro prior to loading will change value of POST_WAIT_TIMEOUT + // This parameter dictates how long to wait before dropping L2 packet + // due to insufficient posted buffers + // 0 mean no waiting before dropping, 0xFFFF means maximum wait + if (pdev->params.fw_flow_control) + { + XI_RV2P_PROC1_CHG_POST_WAIT_TIMEOUT(pdev->params.fw_flow_control_wait); + } + else + { + // No waiting if fw_flow_control is not enabled + XI_RV2P_PROC1_CHG_POST_WAIT_TIMEOUT(0); + } + load_rv2p_fw(pdev,xi_rv2p_proc1,sizeof(xi_rv2p_proc1),RV2P_PROC1); + } + + if(cpu_mask & CPU_RV2P_2) + { + load_rv2p_fw(pdev,xi_rv2p_proc2,sizeof(xi_rv2p_proc2),RV2P_PROC2); + } + + init_5709_cpus(pdev, cpu_mask); + } +} /* lm_init_cpus */ + diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c new file mode 100644 index 0000000000..d80d227bbf --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c @@ -0,0 +1,606 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "lm5706.h" + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_set_mac_addr( + lm_device_t *pdev, + u32_t addr_idx, + u8_t *mac_addr) +{ + u32_t val; + + if(addr_idx >= 16) + { + DbgBreakMsg("Invalid mac address index.\n"); + + return LM_STATUS_FAILURE; + } + + val = (mac_addr[0]<<8) | mac_addr[1]; + REG_WR(pdev, emac.emac_mac_match[addr_idx*2], val); + + val = (mac_addr[2]<<24) | (mac_addr[3]<<16) | + (mac_addr[4]<<8) | mac_addr[5]; + REG_WR(pdev, emac.emac_mac_match[addr_idx*2+1], val); + + return LM_STATUS_SUCCESS; +} /* lm_set_mac_addr */ + + + +/******************************************************************************* + * Description: + * + * Return: + * None. + * + * Note: + * The caller is responsible for synchronizing calls to lm_reg_rd_ind and + * lm_reg_wr_ind. + ******************************************************************************/ +void +lm_reg_rd_ind( + lm_device_t *pdev, + u32_t offset, + u32_t *ret) +{ + /* DbgBreakIf(offset & 0x3); // this can occur for some shmem accesses */ + + mm_acquire_ind_reg_lock(pdev); + + REG_WR(pdev, pci_config.pcicfg_reg_window_address, offset); + REG_RD(pdev, pci_config.pcicfg_reg_window, ret); + + mm_release_ind_reg_lock(pdev); +} /* lm_reg_rd_ind */ + + + +/******************************************************************************* + * Description: + * + * Return: + * None. + * + * Note: + * The caller is responsible for synchronizing calls to lm_reg_rd_ind and + * lm_reg_wr_ind. + ******************************************************************************/ +void +lm_reg_wr_ind( + lm_device_t *pdev, + u32_t offset, + u32_t val) +{ + DbgBreakIf(offset & 0x3); + + mm_acquire_ind_reg_lock(pdev); + + REG_WR(pdev, pci_config.pcicfg_reg_window_address, offset); + REG_WR(pdev, pci_config.pcicfg_reg_window, val); + + mm_release_ind_reg_lock(pdev); +} /* lm_reg_wr_ind */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_ctx_wr( + lm_device_t *pdev, + u32_t cid_addr, + u32_t offset, + u32_t val) +{ + u32_t retry_cnt; + u32_t idx; + + DbgBreakIf(cid_addr > MAX_CID_ADDR || offset & 0x3 || cid_addr & CTX_MASK); + + offset += cid_addr; + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + if (CHIP_REV(pdev) == CHIP_REV_IKOS) + { + retry_cnt = 2000; + } + else + { + retry_cnt = 250; + } + + REG_WR(pdev, context.ctx_ctx_data, val); + REG_WR(pdev, context.ctx_ctx_ctrl, offset | CTX_CTX_CTRL_WRITE_REQ); + + for(idx=0; idx < retry_cnt; idx++) + { + REG_RD(pdev, context.ctx_ctx_ctrl, &val); + + if((val & CTX_CTX_CTRL_WRITE_REQ) == 0) + { + break; + } + + mm_wait(pdev, 10); + } + + DbgBreakIf(idx == retry_cnt); + } + else + { + REG_WR(pdev, context.ctx_data_adr, offset); + REG_WR(pdev, context.ctx_data, val); + } +} /* lm_ctx_wr */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +u32_t +lm_ctx_rd( + lm_device_t *pdev, + u32_t cid_addr, + u32_t offset) +{ + u32_t retry_cnt; + u32_t val; + u32_t idx; + + DbgBreakIf(cid_addr > MAX_CID_ADDR || offset & 0x3 || cid_addr & CTX_MASK); + + offset += cid_addr; + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + if(CHIP_REV(pdev) == CHIP_REV_IKOS) + { + retry_cnt = 1000; + } + else + { + retry_cnt = 25; + } + + REG_WR(pdev, context.ctx_ctx_ctrl, offset | CTX_CTX_CTRL_READ_REQ); + + for(idx = 0; idx < retry_cnt; idx++) + { + REG_RD(pdev, context.ctx_ctx_ctrl, &val); + + if((val & CTX_CTX_CTRL_READ_REQ) == 0) + { + break; + } + + mm_wait(pdev, 5); + } + + DbgBreakIf(idx == retry_cnt); + + REG_RD(pdev, context.ctx_ctx_data, &val); + } + else + { + REG_WR(pdev, context.ctx_data_adr, offset); + REG_RD(pdev, context.ctx_data, &val); + } + + return val; +} /* lm_ctx_rd */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_disable_int( + lm_device_t *pdev) +{ + u32_t sb_idx; + u32_t val; + + switch(CHIP_NUM(pdev)) + { + case CHIP_NUM_5706: + case CHIP_NUM_5708: + REG_RD(pdev, pci_config.pcicfg_int_ack_cmd, &val); + val |= PCICFG_INT_ACK_CMD_MASK_INT; + REG_WR(pdev, pci_config.pcicfg_int_ack_cmd, val); + break; + + case CHIP_NUM_5709: + for(sb_idx = 0; sb_idx < 9; sb_idx++) + { + val = PCICFG_INT_ACK_CMD_MASK_INT | (sb_idx << 24); + REG_WR(pdev, pci_config.pcicfg_int_ack_cmd, val); + } + break; + + default: + DbgBreakMsg("Unsupported chip.\n"); + break; + } +} /* lm_disable_int */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_enable_int( + lm_device_t *pdev) +{ + u32_t val; + + switch(CHIP_NUM(pdev)) + { + case CHIP_NUM_5706: + case CHIP_NUM_5708: + REG_RD(pdev, pci_config.pcicfg_int_ack_cmd, &val); + val &= ~PCICFG_INT_ACK_CMD_MASK_INT; + REG_WR(pdev, pci_config.pcicfg_int_ack_cmd, val); + break; + + case CHIP_NUM_5709: + REG_RD(pdev, hc.hc_config, &val); + val |= HC_CONFIG_UNMASK_ALL; + REG_WR(pdev, hc.hc_config, val); + break; + + default: + DbgBreakMsg("Unsupported chip.\n"); + break; + } +} /* lm_enable_int */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_reg_rd_blk( + lm_device_t *pdev, + u32_t reg_offset, + u32_t *buf_ptr, + u32_t u32t_cnt) +{ + u32_t grc_win_offset; + u32_t grc_win_base; + + DbgBreakIf(reg_offset & 0x3); + + grc_win_offset = reg_offset & (GRC_WINDOW_SIZE - 1); + grc_win_base = reg_offset & ~(GRC_WINDOW_SIZE - 1); + + REG_WR(pdev, pci.pci_grc_window_addr, grc_win_base); + + while(u32t_cnt) + { + if(grc_win_offset >= GRC_WINDOW_SIZE) + { + grc_win_offset = 0; + grc_win_base += GRC_WINDOW_SIZE; + + REG_WR(pdev, pci.pci_grc_window_addr, grc_win_base); + } + + REG_RD_OFFSET(pdev, GRC_WINDOW_BASE + grc_win_offset, buf_ptr); + + buf_ptr++; + u32t_cnt--; + grc_win_offset += 4; + } + + REG_WR(pdev, pci.pci_grc_window_addr, pdev->hw_info.shmem_base & ~0x7fff); +} /* lm_reg_rd_blk */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_reg_rd_blk_ind( + lm_device_t *pdev, + u32_t reg_offset, + u32_t *buf_ptr, + u32_t u32t_cnt) +{ + DbgBreakIf(reg_offset & 0x3); + + mm_acquire_ind_reg_lock(pdev); + + while(u32t_cnt) + { + REG_WR(pdev, pci_config.pcicfg_reg_window_address, reg_offset); + REG_RD(pdev, pci_config.pcicfg_reg_window, buf_ptr); + + buf_ptr++; + u32t_cnt--; + reg_offset += 4; + } + + mm_release_ind_reg_lock(pdev); +} /* lm_reg_rd_blk_ind */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_reg_wr_blk( + lm_device_t *pdev, + u32_t reg_offset, + u32_t *data_ptr, + u32_t u32t_cnt) +{ + u32_t grc_win_offset; + u32_t grc_win_base; + u32_t grc_win_size; + + DbgBreakIf(reg_offset & 0x3); + + if (CHIP_NUM(pdev) == CHIP_NUM_5709) + { + grc_win_size = GRC_WINDOW_SIZE / 4; + } + else + { + grc_win_size = GRC_WINDOW_SIZE; + } + + grc_win_offset = reg_offset & (grc_win_size - 1); + grc_win_base = reg_offset & ~(grc_win_size - 1); + + REG_WR(pdev, pci.pci_grc_window_addr, grc_win_base); + + while(u32t_cnt) + { + if(grc_win_offset >= grc_win_size) + { + grc_win_offset = 0; + grc_win_base += grc_win_size; + + REG_WR(pdev, pci.pci_grc_window_addr, grc_win_base); + } + + REG_WR_OFFSET(pdev, GRC_WINDOW_BASE + grc_win_offset, *data_ptr); + + data_ptr++; + u32t_cnt--; + grc_win_offset += 4; + } + + REG_WR(pdev, pci.pci_grc_window_addr, pdev->hw_info.shmem_base & ~0x7fff); +} /* lm_reg_wr_blk */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_reg_wr_blk_ind( + lm_device_t *pdev, + u32_t reg_offset, + u32_t *data_ptr, + u32_t u32t_cnt) +{ + DbgBreakIf(reg_offset & 0x3); + + mm_acquire_ind_reg_lock(pdev); + + while(u32t_cnt) + { + REG_WR(pdev, pci_config.pcicfg_reg_window_address, reg_offset); + REG_WR(pdev, pci_config.pcicfg_reg_window, *data_ptr); + + data_ptr++; + u32t_cnt--; + reg_offset += 4; + } + + mm_release_ind_reg_lock(pdev); +} /* lm_reg_wr_blk_ind */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_submit_fw_cmd( + lm_device_t *pdev, + u32_t drv_msg) +{ + u32_t val; + + if(pdev->vars.fw_timed_out) + { + DbgMessage(pdev, WARN, "fw timed out.\n"); + + return LM_STATUS_FAILURE; + } + + DbgBreakIf(drv_msg & 0xffff); + + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + OFFSETOF(shmem_region_t, drv_fw_mb.fw_mb), + &val); + if((val & FW_MSG_ACK) != (pdev->vars.fw_wr_seq & DRV_MSG_SEQ)) + { + DbgMessage(pdev, WARN, "command pending.\n"); + + return LM_STATUS_FAILURE; + } + + pdev->vars.fw_wr_seq++; + + drv_msg |= (pdev->vars.fw_wr_seq & DRV_MSG_SEQ); + + REG_WR_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, drv_fw_mb.drv_mb), + drv_msg); + + return LM_STATUS_SUCCESS; +} /* lm_submit_fw_cmd */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_last_fw_cmd_status( + lm_device_t *pdev) +{ + u32_t val; + + if(pdev->vars.fw_timed_out) + { + DbgMessage(pdev, WARN, "fw timed out.\n"); + + return LM_STATUS_TIMEOUT; + } + + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, drv_fw_mb.fw_mb), + &val); + if((val & FW_MSG_ACK) != (pdev->vars.fw_wr_seq & DRV_MSG_SEQ)) + { + return LM_STATUS_BUSY; + } + + if((val & FW_MSG_STATUS_MASK) != FW_MSG_STATUS_OK) + { + return LM_STATUS_FAILURE; + } + + return LM_STATUS_SUCCESS; +} /* lm_last_fw_cmd_status */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +u32_t +lm_mb_get_cid_addr( + lm_device_t *pdev, + u32_t cid) +{ + u32_t mq_offset; + + DbgBreakIf(pdev->params.bin_mq_mode && CHIP_NUM(pdev) != CHIP_NUM_5709); + + if(cid < 256 || pdev->params.bin_mq_mode == FALSE) + { + mq_offset = 0x10000 + (cid << MB_KERNEL_CTX_SHIFT); + } + else + { + DbgBreakIf(cid < pdev->hw_info.first_l4_l5_bin); + + mq_offset = 0x10000 + + ((((cid - pdev->hw_info.first_l4_l5_bin) / + pdev->hw_info.bin_size) + 256) << MB_KERNEL_CTX_SHIFT); + } + + DbgBreakIf(mq_offset > pdev->hw_info.bar_size); + + return mq_offset; +} /* lm_mb_get_cid_addr */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +u32_t +lm_mb_get_bypass_addr( + lm_device_t *pdev, + u32_t cid) +{ + u32_t mq_offset; + + DbgBreakIf(pdev->params.bin_mq_mode && CHIP_NUM(pdev) != CHIP_NUM_5709); + + if(cid < 256 || pdev->params.bin_mq_mode == FALSE) + { + mq_offset = 0x10000 + + MB_KERNEL_CTX_SIZE * MAX_CID_CNT + + cid * LM_PAGE_SIZE; + } + else + { + DbgBreakIf(cid < pdev->hw_info.first_l4_l5_bin); + + mq_offset = 0x10000 + + MB_KERNEL_CTX_SIZE * MAX_CID_CNT + + (((cid - pdev->hw_info.first_l4_l5_bin) / + pdev->hw_info.bin_size) + 256) * LM_PAGE_SIZE; + } + + DbgBreakIf(mq_offset > pdev->hw_info.bar_size); + + return mq_offset; +} /* lm_mb_get_bypass_addr */ + diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c new file mode 100644 index 0000000000..1764b74c16 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c @@ -0,0 +1,1344 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "lm5706.h" + + +/******************************************************************************* + * Constants. + ******************************************************************************/ + +/* Buffered flash (Atmel: AT45DB011B) specific information */ +#define SEEPROM_SHIFT_BITS 2 +#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_SHIFT_BITS) +#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) +#define SEEPROM_PAGE_SIZE 4 +#define SEEPROM_TOTAL_SIZE 65536 + +#define BUFFERED_FLASH_SHIFT_BITS 9 +#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_SHIFT_BITS) +#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) +#define BUFFERED_FLASH_PAGE_SIZE 264 +#define BUFFERED_FLASH_TOTAL_SIZE 0x21000 + +#define SAIFUN_FLASH_SHIFT_BITS 8 +#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_SHIFT_BITS) +#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) +#define SAIFUN_FLASH_PAGE_SIZE 256 +#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 + +#define ST_MICRO_FLASH_SHIFT_BITS 8 +#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_SHIFT_BITS) +#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) +#define ST_MICRO_FLASH_PAGE_SIZE 256 +#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 +#define ST_MICRO_FLASH_1MBIT 0x20000 + +/* NVRAM flags for nvram_write_dword and nvram_read_dword. */ +#define NVRAM_FLAG_NONE 0x00 +#define NVRAM_FLAG_SET_FIRST_CMD_BIT 0x01 +#define NVRAM_FLAG_SET_LAST_CMD_BIT 0x02 +#define NVRAM_FLAG_BUFFERED_FLASH 0x04 + +#define NVRAM_TIMEOUT_COUNT 30000 + + +#define FLASH_STRAP_MASK (NVM_CFG1_FLASH_MODE | \ + NVM_CFG1_BUFFER_MODE | \ + NVM_CFG1_PROTECT_MODE | \ + NVM_CFG1_FLASH_SIZE) +#define FLASH_BACKUP_STRAP_MASK (0xf << 26) + + +typedef struct _new_nvm_cfg_t +{ + /* Strapping to indicate the flash type (original | backup) */ + u32_t strapping; + /* New configuration values */ + u32_t config1; + u32_t config2; + u32_t config3; + u32_t write1; + u32_t buffered; + u32_t shift_bits; + u32_t page_size; + u32_t addr_mask; + u32_t total_size; + char *name; +} new_nvm_cfg_t; + +/* This table is indexed by the strap values */ +static const new_nvm_cfg_t cfg_table[] = +{ + /* Slow EEPROM */ + {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, + 1, SEEPROM_SHIFT_BITS, SEEPROM_PAGE_SIZE, + SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, + "EEPROM - slow"}, + /* Expansion entry 0001 */ + {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_SHIFT_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 0001"}, + /* Saifun SA25F010 (non-buffered flash) */ + {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, /* strap, cfg1, & write1 need updates */ + 0, SAIFUN_FLASH_SHIFT_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, + "Non-buffered flash (128kB)"}, + /* Saifun SA25F020 (non-buffered flash) */ + {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, /* strap, cfg1, & write1 need updates */ + 0, SAIFUN_FLASH_SHIFT_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, + "Non-buffered flash (256kB)"}, + /* Expansion entry 0100 */ + {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_SHIFT_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 0100"}, + /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ + {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, + 0, ST_MICRO_FLASH_SHIFT_BITS, ST_MICRO_FLASH_PAGE_SIZE, + ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, + "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, + /* Entry 0110: ST M45PE20 (non-buffered flash)*/ + {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, + 0, ST_MICRO_FLASH_SHIFT_BITS, ST_MICRO_FLASH_PAGE_SIZE, + ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, + "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, + /* Saifun SA25F005 (non-buffered flash) */ + {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, /* strap, cfg1, & write1 need updates */ + 0, SAIFUN_FLASH_SHIFT_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, + "Non-buffered flash (64kB)"}, + /* Fast EEPROM */ + {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, + 1, SEEPROM_SHIFT_BITS, SEEPROM_PAGE_SIZE, + SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, + "EEPROM - fast"}, + /* Expansion entry 1001 */ + {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_SHIFT_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1001"}, + /* Expansion entry 1010 */ + {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_SHIFT_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1010"}, + /* ATMEL AT45DB011B (buffered flash) */ + {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, + 1, BUFFERED_FLASH_SHIFT_BITS, BUFFERED_FLASH_PAGE_SIZE, + BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, + "Buffered flash (128kB)"}, + /* Expansion entry 1100 */ + {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_SHIFT_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1100"}, + /* Expansion entry 1101 */ + {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_SHIFT_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1101"}, + /* Ateml Expansion entry 1110 */ + {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, + 1, BUFFERED_FLASH_SHIFT_BITS, BUFFERED_FLASH_PAGE_SIZE, + BUFFERED_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1110 (Atmel)"}, + /* ATMEL AT45DB021B (buffered flash) */ + {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, + 1, BUFFERED_FLASH_SHIFT_BITS, BUFFERED_FLASH_PAGE_SIZE, + BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, + "Buffered flash (256kB)"}, +}; + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +acquire_nvram_lock( + lm_device_t *pdev) +{ + lm_status_t lm_status; + u32_t j, cnt; + u32_t val; + + /* Adjust timeout for emulation/FPGA */ + cnt = NVRAM_TIMEOUT_COUNT; + if (CHIP_REV(pdev) == CHIP_REV_FPGA) cnt *= 10; + else if (CHIP_REV(pdev) == CHIP_REV_IKOS) cnt *= 100; + + val = 0; + + /* Request access to the flash interface. */ + REG_WR(pdev, nvm.nvm_sw_arb, NVM_SW_ARB_ARB_REQ_SET2); + + for(j = 0; j < cnt*10; j++) + { + REG_RD(pdev, nvm.nvm_sw_arb, &val); + if(val & NVM_SW_ARB_ARB_ARB2) + { + break; + } + mm_wait(pdev, 5); + } + + if(val & NVM_SW_ARB_ARB_ARB2) + { + lm_status = LM_STATUS_SUCCESS; + } + else + { + DbgBreakMsg("Cannot get access to nvram interface.\n"); + + lm_status = LM_STATUS_BUSY; + } + return lm_status; +} /* acquire_nvram_lock */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +release_nvram_lock( + lm_device_t *pdev) +{ + u32_t j, cnt; + u32_t val; + + /* Relinquish nvram interface. */ + REG_WR(pdev, nvm.nvm_sw_arb, NVM_SW_ARB_ARB_REQ_CLR2); + + /* Adjust timeout for emulation/FPGA */ + cnt = NVRAM_TIMEOUT_COUNT; + if (CHIP_REV(pdev) == CHIP_REV_FPGA) cnt *= 10; + else if (CHIP_REV(pdev) == CHIP_REV_IKOS) cnt *= 100; + + val = 0; + + for(j = 0; j < cnt; j++) + { + REG_RD(pdev, nvm.nvm_sw_arb, &val); + if(!(val & NVM_SW_ARB_ARB_ARB2)) + { + break; + } + + mm_wait(pdev, 5); + } + + DbgBreakIf(val & NVM_SW_ARB_ARB_ARB2); +} /* release_nvram_lock */ + + + +/******************************************************************************* + * Description: + * + * Return: + * + ******************************************************************************/ +STATIC lm_status_t +enable_nvram_write( + lm_device_t *pdev) +{ + u32_t val, j, cnt; + lm_status_t lm_status; + + REG_RD(pdev, misc.misc_cfg, &val); + REG_WR(pdev, misc.misc_cfg, val | MISC_CFG_NVM_WR_EN_PCI); + + lm_status = LM_STATUS_SUCCESS; + + if (!pdev->hw_info.flash_spec.buffered) + { + REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_DONE); + REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_WREN | + NVM_COMMAND_DOIT); + + /* Adjust timeout for emulation/FPGA */ + cnt = NVRAM_TIMEOUT_COUNT; + if (CHIP_REV(pdev) == CHIP_REV_FPGA) cnt *= 10; + else if (CHIP_REV(pdev) == CHIP_REV_IKOS) cnt *= 100; + + lm_status = LM_STATUS_BUSY; + + for(j = 0; j < cnt; j++) + { + mm_wait(pdev, 5); + + REG_RD(pdev, nvm.nvm_command, &val); + if(val & NVM_COMMAND_DONE) + { + lm_status = LM_STATUS_SUCCESS; + break; + } + } + } + + return lm_status; +} /* enable_nvram_write */ + + + +/******************************************************************************* + * Description: + * + * Return: + * + ******************************************************************************/ +STATIC lm_status_t +disable_nvram_write( + lm_device_t *pdev) +{ + lm_status_t lm_status; + u32_t val; + + REG_RD(pdev, misc.misc_cfg, &val); + REG_WR(pdev, misc.misc_cfg, val & ~MISC_CFG_NVM_WR_EN); + lm_status = LM_STATUS_SUCCESS; + +#if 0 /* On Saifun and ST parts, WP kicks in at the end of the write. + So, no need to have this. */ + if (!pdev->hw_info.flash_spec.buffered) + { + /* Restoring protection causes the next read at a wrong location; + * leave this out for now. */ + REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_DONE); + REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_WRDI | + NVM_COMMAND_DOIT); + + /* Adjust timeout for emulation/FPGA */ + cnt = NVRAM_TIMEOUT_COUNT; + if (CHIP_REV(pdev) == CHIP_REV_FPGA) cnt *= 10; + else if (CHIP_REV(pdev) == CHIP_REV_IKOS) cnt *= 100; + + lm_status = LM_STATUS_BUSY; + for(j = 0; j < cnt; j++) + { + mm_wait(pdev, 5); + + REG_RD(pdev, nvm.nvm_command, &val); + if(val & NVM_COMMAND_DONE) + { + lm_status = LM_STATUS_SUCCESS; + break; + } + } + } +#endif + + return lm_status; +} /* disable_nvram_write */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +enable_nvram_access( + lm_device_t *pdev) +{ + u32_t val; + + REG_RD(pdev, nvm.nvm_access_enable, &val); + + /* Enable both bits, even on read. */ + REG_WR( + pdev, + nvm.nvm_access_enable, + val | NVM_ACCESS_ENABLE_EN | NVM_ACCESS_ENABLE_WR_EN); + + return LM_STATUS_SUCCESS; +} /* enable_nvram_access */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +disable_nvram_access( + lm_device_t *pdev) +{ + u32_t val; + + REG_RD(pdev, nvm.nvm_access_enable, &val); + + /* Disable both bits, even after read. */ + REG_WR( + pdev, + nvm.nvm_access_enable, + val & ~(NVM_ACCESS_ENABLE_EN | NVM_ACCESS_ENABLE_WR_EN)); + + return LM_STATUS_SUCCESS; +} /* disable_nvram_access */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +nvram_erase_page( + lm_device_t *pdev, + u32_t offset) +{ + lm_status_t lm_status; + u32_t cmd_flags; + u32_t val; + u32_t j, cnt; + + if (pdev->hw_info.flash_spec.buffered) + { + /* Buffered flash, no erase needed */ + return LM_STATUS_SUCCESS; + } + + /* Build an erase command */ + cmd_flags = NVM_COMMAND_ERASE | NVM_COMMAND_WR | NVM_COMMAND_DOIT; + + /* Need to clear DONE bit separately. */ + REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_DONE); + + /* Address of the NVRAM to read from. */ + REG_WR(pdev, nvm.nvm_addr, offset & NVM_ADDR_NVM_ADDR_VALUE); + + /* Issue an erase command. */ + REG_WR(pdev, nvm.nvm_command, cmd_flags); + + /* Adjust timeout for emulation/FPGA */ + cnt = NVRAM_TIMEOUT_COUNT; + if (CHIP_REV(pdev) == CHIP_REV_FPGA) cnt *= 10; + else if (CHIP_REV(pdev) == CHIP_REV_IKOS) cnt *= 100; + + /* Wait for completion. */ + lm_status = LM_STATUS_BUSY; + for(j = 0; j < cnt; j++) + { + mm_wait(pdev, 5); + + REG_RD(pdev, nvm.nvm_command, &val); + if(val & NVM_COMMAND_DONE) + { + lm_status = LM_STATUS_SUCCESS; + break; + } + } + + return lm_status; + +} /* nvram_erase_page */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +nvram_read_dword( + lm_device_t *pdev, + u32_t offset, + u32_t *ret_val, + u32_t nvram_flags) +{ + lm_status_t lm_status; + u32_t cmd_flags; + u32_t val; + u32_t j, cnt; + + /* Build the command word. */ + cmd_flags = NVM_COMMAND_DOIT; + if(nvram_flags & NVRAM_FLAG_SET_FIRST_CMD_BIT) + { + cmd_flags |= NVM_COMMAND_FIRST; + } + + if(nvram_flags & NVRAM_FLAG_SET_LAST_CMD_BIT) + { + cmd_flags |= NVM_COMMAND_LAST; + } + + if ((CHIP_NUM(pdev) == CHIP_NUM_5706) || (CHIP_NUM(pdev) == CHIP_NUM_5708)) + { + /* Calculate an offset of a buffered flash. */ + if(nvram_flags & NVRAM_FLAG_BUFFERED_FLASH) + { + offset = ((offset / pdev->hw_info.flash_spec.page_size) << + pdev->hw_info.flash_spec.shift_bits) + + (offset % pdev->hw_info.flash_spec.page_size); + } + + /* Need to clear DONE bit separately. */ + REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_DONE); + } + + /* Address of the NVRAM to read from. */ + if (cmd_flags & NVM_COMMAND_FIRST) { + REG_WR(pdev, nvm.nvm_addr, offset & NVM_ADDR_NVM_ADDR_VALUE); + } + + /* Issue a read command. */ + REG_WR(pdev, nvm.nvm_command, cmd_flags); + + /* Adjust timeout for emulation/FPGA */ + cnt = NVRAM_TIMEOUT_COUNT; + if (CHIP_REV(pdev) == CHIP_REV_FPGA) cnt *= 10; + else if (CHIP_REV(pdev) == CHIP_REV_IKOS) cnt *= 100; + + /* Wait for completion. */ + lm_status = LM_STATUS_BUSY; + for(j = 0; j < cnt; j++) + { + mm_wait(pdev, 5); + + REG_RD(pdev, nvm.nvm_command, &val); + if(val & NVM_COMMAND_DONE) + { + REG_RD(pdev, nvm.nvm_read, &val); + + /* Change to little endian. */ + #if defined(LITTLE_ENDIAN) + val = ((val & 0xff) << 24) | ((val & 0xff00) << 8) | + ((val & 0xff0000) >> 8) | ((val >> 24) & 0xff); + #endif + + *ret_val = val; + + lm_status = LM_STATUS_SUCCESS; + + break; + } + } + + return lm_status; +} /* nvram_read_dword */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +nvram_write_dword( + lm_device_t *pdev, + u32_t offset, + u32_t val, + u32_t nvram_flags) +{ + lm_status_t lm_status; + u32_t cmd_flags; + u32_t j, cnt; + + /* Build the command word. */ + cmd_flags = NVM_COMMAND_DOIT | NVM_COMMAND_WR; + if(nvram_flags & NVRAM_FLAG_SET_FIRST_CMD_BIT) + { + cmd_flags |= NVM_COMMAND_FIRST; + } + + if(nvram_flags & NVRAM_FLAG_SET_LAST_CMD_BIT) + { + cmd_flags |= NVM_COMMAND_LAST; + } + if ((CHIP_NUM(pdev) == CHIP_NUM_5706) || (CHIP_NUM(pdev) == CHIP_NUM_5708)) + { + /* Calculate an offset of a buffered flash. */ + if(nvram_flags & NVRAM_FLAG_BUFFERED_FLASH) + { + offset = ((offset / pdev->hw_info.flash_spec.page_size) << + pdev->hw_info.flash_spec.shift_bits) + + (offset % pdev->hw_info.flash_spec.page_size); + } + + /* Need to clear DONE bit separately. */ + REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_DONE); + } + + /* Change to little endian. */ + #if defined(LITTLE_ENDIAN) + val = ((val & 0xff) << 24) | ((val & 0xff00) << 8) | + ((val & 0xff0000) >> 8) | ((val >> 24) & 0xff); + #endif + + /* Write the data. */ + REG_WR(pdev, nvm.nvm_write, val); + + /* Address of the NVRAM to write to. */ + if (cmd_flags & NVM_COMMAND_FIRST) { + REG_WR(pdev, nvm.nvm_addr, offset & NVM_ADDR_NVM_ADDR_VALUE); + } + + /* Issue the write command. */ + REG_WR(pdev, nvm.nvm_command, cmd_flags); + + /* Adjust timeout for emulation/FPGA */ + cnt = NVRAM_TIMEOUT_COUNT; + if (CHIP_REV(pdev) == CHIP_REV_FPGA) cnt *= 10; + else if (CHIP_REV(pdev) == CHIP_REV_IKOS) cnt *= 100; + + /* Wait for completion. */ + lm_status = LM_STATUS_BUSY; + for(j = 0; j < cnt; j++) + { + mm_wait(pdev, 5); + + REG_RD(pdev, nvm.nvm_command, &val); + if(val & NVM_COMMAND_DONE) + { + lm_status = LM_STATUS_SUCCESS; + break; + } + } + + return lm_status; +} /* nvram_write_dword */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u32_t +find_atmel_size( + lm_device_t *pdev) +{ + u32_t orig, val, done=0, size=BUFFERED_FLASH_TOTAL_SIZE; + + if (CHIP_NUM(pdev) == CHIP_NUM_5709) + { + REG_RD(pdev, nvm.nvm_cfg4, &val); + val &= 0x07; + return (1 << val) ; + } + + /* It is assumed that the flash is enabled and locked for exclusive access */ + REG_RD(pdev, nvm.nvm_cfg3, &orig); + REG_WR(pdev, nvm.nvm_cfg3, 0x57848353); + REG_WR(pdev, nvm.nvm_read, 0); + REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_DONE); + REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_DOIT | + NVM_COMMAND_FIRST | + NVM_COMMAND_LAST); + while (!done) + { + REG_RD(pdev, nvm.nvm_command, &val); + if (val & NVM_COMMAND_DONE) + { + done = 1; + } + } + REG_RD(pdev, nvm.nvm_read, &val); + REG_WR(pdev, nvm.nvm_cfg3, orig); + val &= 0x3c; + switch (val) + { + case 0x24: + size *= 8; + break; + case 0x1c: + size *= 4; + break; + case 0x14: + size *= 2; + break; + case 0x0c: + size *= 1; + break; + default: + size *= 0; + break; + } + return size; +} + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u32_t +find_stm_size( + lm_device_t *pdev) +{ + u32_t idx, val, result, bit; + + if (CHIP_NUM(pdev) == CHIP_NUM_5709) + { + REG_RD(pdev, nvm.nvm_cfg4, &val); + val &= 0x07; + return (1 << val) ; + } + + /* It is assumed that the flash is enabled and locked for exclusive access */ + /* Set CS, SO, SCLK as output, SI as input */ + REG_WR(pdev, nvm.nvm_addr, NVM_ADDR_NVM_ADDR_VALUE_EECLK_TE | + NVM_ADDR_NVM_ADDR_VALUE_EEDATA_TE | + NVM_ADDR_NVM_ADDR_VALUE_SI_TE + ); + /* Set initial data CS=1, SO=0, SCLK=0, SI=n/a */ + REG_WR(pdev, nvm.nvm_write, NVM_WRITE_NVM_WRITE_VALUE_EECLK_TE | + NVM_WRITE_NVM_WRITE_VALUE_EEDATA_TE | + NVM_WRITE_NVM_WRITE_VALUE_CS_B_TE + ); + /* Enable bit-bang mode */ + REG_RD(pdev, nvm.nvm_cfg1, &val); + REG_WR(pdev, nvm.nvm_cfg1, val | NVM_CFG1_BITBANG_MODE); + mm_wait(pdev, 1); + + /* Bit-bang the command */ + + val = 0xf9; + + REG_WR(pdev, nvm.nvm_write, 0); + mm_wait(pdev, 1); + for (idx=0; idx < 8; idx++) + { + bit = ((val >> idx) & 0x1) << 4; + REG_WR(pdev, nvm.nvm_write, bit); + mm_wait(pdev, 1); + REG_WR(pdev, nvm.nvm_write, NVM_WRITE_NVM_WRITE_VALUE_SCLK_TE | bit); + mm_wait(pdev, 1); + } + REG_WR(pdev, nvm.nvm_write, 0); + mm_wait(pdev, 1); + + /* Bit-bang to read ID, 1st byte: manuf ID; + * 2nd byte: memory type; 3rd byte: memory capacity */ + result = 0; + for (idx = 0; idx < 24; idx++) + { + REG_RD(pdev, nvm.nvm_read, &val); + bit = (val & NVM_WRITE_NVM_WRITE_VALUE_SI_TE) >> 5; + result = (result << 1) | bit; + + REG_WR(pdev, nvm.nvm_write, NVM_WRITE_NVM_WRITE_VALUE_SCLK_TE); + mm_wait(pdev, 1); + REG_WR(pdev, nvm.nvm_write, 0); + mm_wait(pdev, 1); + } + REG_WR(pdev, nvm.nvm_write, NVM_WRITE_NVM_WRITE_VALUE_CS_B_TE); + mm_wait(pdev, 1); + + val = ST_MICRO_FLASH_1MBIT; + switch (result) + { + case 0x00204014: + val *= 8; + break; + case 0x00204013: + val *= 4; + break; + case 0x00204012: + val *= 2; + break; + case 0x00204011: + val *= 1; + break; + default: + val *= 0; + break; + } + + /* Get out of bit-bang mode */ + REG_RD(pdev, nvm.nvm_cfg1, &idx); + REG_WR(pdev, nvm.nvm_cfg1, idx & ~NVM_CFG1_BITBANG_MODE); + mm_wait(pdev, 1); + + return val; +} + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u32_t +find_nvram_size( + lm_device_t *pdev, + u32_t table_idx) +{ + lm_status_t lm_status; + u32_t size, val; + + if (CHIP_NUM(pdev) == CHIP_NUM_5709) + { + REG_RD(pdev, nvm.nvm_cfg4, &val); + val &= 0x07; + return ((1 << val) * 1024 * 1024 / 8); + } + + /* Request access to the flash interface. */ + lm_status = acquire_nvram_lock(pdev); + if(lm_status != LM_STATUS_SUCCESS) return 0; + + /* Enable access to flash interface */ + lm_status = enable_nvram_access(pdev); + if(lm_status != LM_STATUS_SUCCESS) return 0; + + switch (table_idx) + { + case 11: + case 14: + case 15: + /* ATMEL */ + size = find_atmel_size(pdev); + break; + case 5: + case 6: + size = find_stm_size(pdev); + break; + case 2: + case 3: + case 7: + /* This one is static */ + size = cfg_table[table_idx].total_size; + break; + default: + size = 0; + break; + } + /* Disable access to flash interface */ + (void) disable_nvram_access(pdev); + release_nvram_lock(pdev); + return size; +} + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_nvram_init( + lm_device_t *pdev, + u8_t reset_flash_block) +{ + u32_t idx, val; + lm_status_t lm_status; + + DbgMessage(pdev, INFORM, "### lm_nvram_init\n"); + + if (CHIP_NUM(pdev) == CHIP_NUM_5709) + { + REG_RD(pdev, nvm.nvm_cfg4, &val); + + pdev->hw_info.flash_spec.buffered = 0; + pdev->hw_info.flash_spec.shift_bits = 0; + pdev->hw_info.flash_spec.page_size = SAIFUN_FLASH_PAGE_SIZE; + pdev->hw_info.flash_spec.addr_mask = 0; + pdev->hw_info.flash_spec.total_size = (1 << (val & 0x07)) * 1024 * 1024 / 8; + return; + } + + idx = lm_nvram_query(pdev, reset_flash_block, FALSE); + + if (idx == (u32_t)-1) + { + /* Not necessarily an error, it could mean that the flash block has + * been reconfigured. + */ + return; + } + + DbgMessage(pdev, INFORM, cfg_table[idx].name); + DbgMessage(pdev, INFORM, " reconfiguring.\n"); + + /* Request access to the flash interface. */ + lm_status = acquire_nvram_lock(pdev); + if(lm_status != LM_STATUS_SUCCESS) return; + + /* Enable access to flash interface */ + lm_status = enable_nvram_access(pdev); + if(lm_status != LM_STATUS_SUCCESS) return; + + /* Reconfigure the flash interface */ + /* Program the SPI and SEE clocks faster if FPGA or IKOS */ + val = cfg_table[idx].config1; + + if(CHIP_REV(pdev) == CHIP_REV_FPGA) + { + val &= ~(NVM_CFG1_SPI_CLK_DIV | NVM_CFG1_SEE_CLK_DIV); + val |= (0x0<<7) | (0x6<<11); + } + else if(CHIP_REV(pdev) == CHIP_REV_IKOS) + { + val &= ~(NVM_CFG1_SPI_CLK_DIV | NVM_CFG1_SEE_CLK_DIV); + val |= (0x0<<7) | (0x0<<11); + } + else + { + /* No change, leave it */ + } + + REG_WR(pdev, nvm.nvm_cfg1, val); + REG_WR(pdev, nvm.nvm_cfg2, cfg_table[idx].config2); + REG_WR(pdev, nvm.nvm_cfg3, cfg_table[idx].config3); + REG_WR(pdev, nvm.nvm_write1, cfg_table[idx].write1); + + /* Disable access to flash interface */ + (void) disable_nvram_access(pdev); + release_nvram_lock(pdev); + +} /* lm_nvram_init */ + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +u32_t +lm_nvram_query( + lm_device_t *pdev, + u8_t reset_flash_block, + u8_t no_hw_mod) +{ + u32_t val; + u32_t j; + u32_t cnt, idx, ret_val = (u32_t)-1; + u8_t reconfigured = FALSE; + u32_t entry_count, mask; + + + DbgMessage(pdev, INFORM, "### lm_nvram_query\n"); + + if (CHIP_NUM(pdev) == CHIP_NUM_5709) + { + REG_RD(pdev, nvm.nvm_cfg4, &val); + + pdev->hw_info.flash_spec.buffered = 0; + pdev->hw_info.flash_spec.shift_bits = 0; + pdev->hw_info.flash_spec.page_size = SAIFUN_FLASH_PAGE_SIZE; + pdev->hw_info.flash_spec.addr_mask = 0; + pdev->hw_info.flash_spec.total_size = (1 << (val & 0x07)) * 1024 * 1024 / 8; + return (u32_t)-1; + } + + /* Adjust timeout for emulation/FPGA */ + cnt = NVRAM_TIMEOUT_COUNT; + if(CHIP_REV(pdev) == CHIP_REV_FPGA) cnt *= 10; + else if(CHIP_REV(pdev) == CHIP_REV_IKOS) cnt *= 100; + + /* Reset the NVRAM interface block. */ + if(reset_flash_block) + { + val = 0; + + /* Get access to write flash block register */ + (void) enable_nvram_access(pdev); + + REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_RST); + for(j = 0; j < cnt; j++) + { + mm_wait(pdev, 5); + + REG_RD(pdev, nvm.nvm_command, &val); + if(!(val & NVM_COMMAND_RST)) + { + break; + } + } + + DbgBreakIf(val & NVM_COMMAND_RST); + } + + /* Determine the selected interface. */ + REG_RD(pdev, nvm.nvm_cfg1, &val); + + entry_count = sizeof(cfg_table)/sizeof(new_nvm_cfg_t); + + if (val & (1<<30)) + { + /* Flash interface has been reconfigured */ + mask = FLASH_BACKUP_STRAP_MASK; + for (idx=0; idx<entry_count; idx++) + { + if ((val & mask) == (cfg_table[idx].strapping & mask)) + { + DbgMessage(pdev, INFORM, "Reconfigured "); + DbgMessage(pdev, INFORM, cfg_table[idx].name); + DbgMessage(pdev, INFORM, " detected.\n"); + + reconfigured = TRUE; + ret_val = idx; + break; + } + } + } + else + { + /* Not yet been reconfigured */ + + /* A new bit to indicate where to look for strapping (backup vs. original) */ + mask = (val & (1<<23)) ? FLASH_BACKUP_STRAP_MASK : FLASH_STRAP_MASK; + + for (idx=0; idx<entry_count; idx++) + { + + if ((val & mask) == (cfg_table[idx].strapping & mask)) + { + DbgMessage(pdev, INFORM, cfg_table[idx].name); + DbgMessage(pdev, INFORM, " detected.\n"); + + ret_val = idx; + break; + } + } + } /* if (val & (1<<30)) */ + + /* Check for exceptions: entries that are supported by TetonII B0, + * but not earlier chips + */ + if ((ret_val == 5) && (CHIP_ID(pdev) < CHIP_ID_5708_B0)) + { + pdev->hw_info.flash_spec.total_size = 0; + + DbgBreakMsg("Unsupported type.\n"); + } + else if (ret_val != (u32_t)-1) + { + /* Track what's been configured */ + pdev->hw_info.flash_spec.buffered = cfg_table[ret_val].buffered; + pdev->hw_info.flash_spec.shift_bits = cfg_table[ret_val].shift_bits; + pdev->hw_info.flash_spec.page_size = cfg_table[ret_val].page_size; + pdev->hw_info.flash_spec.addr_mask = cfg_table[ret_val].addr_mask; + /* Determine the size before reconfiguring, dynamically */ + if (no_hw_mod) + { + pdev->hw_info.flash_spec.total_size = cfg_table[ret_val].total_size; + } + else + { + pdev->hw_info.flash_spec.total_size = find_nvram_size(pdev, idx); + } + } + else + { + pdev->hw_info.flash_spec.total_size = 0; + + DbgBreakMsg("Unknown flash/EEPROM type.\n"); + } + + return (reconfigured) ? (u32_t)-1 : ret_val; + +} /* lm_nvram_query */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_nvram_read( + lm_device_t *pdev, + u32_t offset, + u32_t *ret_buf, + u32_t buf_size) +{ + lm_status_t lm_status; + u32_t cmd_flags; + + DbgMessage(pdev, VERBOSE, "### lm_nvram_read\n"); + + if((buf_size & 0x03) || (offset & 0x03)) + { + DbgBreakMsg("Invalid paramter.\n"); + + return LM_STATUS_FAILURE; + } + if(offset + buf_size > pdev->hw_info.flash_spec.total_size) + { + DbgBreakMsg("Invalid paramter.\n"); + + return LM_STATUS_FAILURE; + } + + if (pdev->hw_info.flash_spec.buffered) + { + cmd_flags = NVRAM_FLAG_BUFFERED_FLASH; + } + else + { + cmd_flags = NVRAM_FLAG_NONE; + } + + /* Request access to the flash interface. */ + lm_status = acquire_nvram_lock(pdev); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + /* Enable access to flash interface */ + lm_status = enable_nvram_access(pdev); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + if(buf_size <= sizeof(u32_t)) + { + /* Address of the NVRAM to read from. */ + cmd_flags |= NVRAM_FLAG_SET_FIRST_CMD_BIT | + NVRAM_FLAG_SET_LAST_CMD_BIT; + lm_status = nvram_read_dword(pdev, offset, ret_buf, cmd_flags); + } + else + { + /* Read the first word. */ + cmd_flags |= NVRAM_FLAG_SET_FIRST_CMD_BIT; + lm_status = nvram_read_dword(pdev, offset, ret_buf, cmd_flags); + cmd_flags &= ~NVRAM_FLAG_SET_FIRST_CMD_BIT; + if(lm_status == LM_STATUS_SUCCESS) + { + /* Advance to the next dword. */ + offset += sizeof(u32_t); + ret_buf++; + buf_size -= sizeof(u32_t); + + while(buf_size > sizeof(u32_t) && lm_status == LM_STATUS_SUCCESS) + { + lm_status = nvram_read_dword(pdev, offset, ret_buf, cmd_flags); + + /* Advance to the next dword. */ + offset += sizeof(u32_t); + ret_buf++; + buf_size -= sizeof(u32_t); + } + + if(lm_status == LM_STATUS_SUCCESS) + { + cmd_flags |= NVRAM_FLAG_SET_LAST_CMD_BIT; + lm_status = nvram_read_dword(pdev, offset, ret_buf, cmd_flags); + } + } + } + + /* Disable access to flash interface */ + (void) disable_nvram_access(pdev); + + release_nvram_lock(pdev); + + return lm_status; +} /* lm_nvram_read */ + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_nvram_write( + lm_device_t *pdev, + u32_t offset, + u32_t *data_buf, + u32_t buf_size) +{ + lm_status_t lm_status; + u32_t cmd_flags; + u32_t written_so_far, page_start, page_end, data_start, data_end; + u32_t idx, *ptr32, addr, base_flags; + static u32_t flash_buffer[66]; + + DbgMessage(pdev, VERBOSE, "### lm_nvram_write\n"); + + if(offset & 0x03) + { + DbgBreakMsg("Invalid paramter.\n"); + + return LM_STATUS_FAILURE; + } + + if(offset + buf_size > pdev->hw_info.flash_spec.total_size) + { + DbgBreakMsg("Invalid paramter.\n"); + return LM_STATUS_FAILURE; + } + + lm_status = LM_STATUS_SUCCESS; + + written_so_far = 0; + ptr32 = data_buf; + + if ((CHIP_NUM(pdev) == CHIP_NUM_5706) || (CHIP_NUM(pdev) == CHIP_NUM_5708)) + { + base_flags = (pdev->hw_info.flash_spec.buffered) ? + NVRAM_FLAG_BUFFERED_FLASH : NVRAM_FLAG_NONE; + while (written_so_far < buf_size) + { + /* Find the page_start addr */ + page_start = offset + written_so_far; + page_start -= (page_start % pdev->hw_info.flash_spec.page_size); + /* Find the page_end addr */ + page_end = page_start + pdev->hw_info.flash_spec.page_size; + /* Find the data_start addr */ + data_start = (written_so_far==0) ? offset : page_start; + /* Find the data_end addr */ + data_end = (page_end > offset + buf_size) ? + (offset+buf_size) : page_end; + + /* Request access to the flash interface. */ + lm_status = acquire_nvram_lock(pdev); + if(lm_status != LM_STATUS_SUCCESS) return lm_status; + + /* Enable access to flash interface */ + lm_status = enable_nvram_access(pdev); + if(lm_status != LM_STATUS_SUCCESS) return lm_status; + + if (pdev->hw_info.flash_spec.buffered == 0) + { + /* Read the whole page into the buffer (non-buffer flash only) */ + for (idx=0; idx<pdev->hw_info.flash_spec.page_size; idx+=4) + { + cmd_flags = base_flags; + if (idx==0) + { + cmd_flags |= NVRAM_FLAG_SET_FIRST_CMD_BIT; + } + if (idx==pdev->hw_info.flash_spec.page_size-4) + { + cmd_flags |= NVRAM_FLAG_SET_LAST_CMD_BIT; + } + lm_status |= nvram_read_dword(pdev, page_start+idx, + &flash_buffer[idx/4], + cmd_flags); + } + if(lm_status != LM_STATUS_SUCCESS) return lm_status; + } + + /* Enable writes to flash interface (unlock write-protect) */ + lm_status = enable_nvram_write(pdev); + if(lm_status != LM_STATUS_SUCCESS) return lm_status; + + /* Erase the page */ + lm_status = nvram_erase_page(pdev, page_start); + if(lm_status != LM_STATUS_SUCCESS) return lm_status; + + /* Re-enable the write again for the actual write */ + lm_status = enable_nvram_write(pdev); + if(lm_status != LM_STATUS_SUCCESS) return lm_status; + + /* Loop to write back the buffer data from page_start to data_start */ + cmd_flags = NVRAM_FLAG_SET_FIRST_CMD_BIT | base_flags; + idx = 0; + for (addr=page_start; addr<data_start; addr+=4, idx++) + { + if (pdev->hw_info.flash_spec.buffered == 0) + { + /* Write back only for non-buffered flash */ + (void) nvram_write_dword(pdev, addr, flash_buffer[idx], cmd_flags); + cmd_flags = base_flags; + } + } + + /* Loop to write the new data from data_start to data_end */ + for (addr=data_start; addr<data_end; addr+=4, idx++) + { + if ((addr==page_end-4) || + ((pdev->hw_info.flash_spec.buffered) && (addr>=data_end-4))) + { + /* End of a page (page_end==data_end) + * OR end of new data (in buffered flash case) */ + cmd_flags |= NVRAM_FLAG_SET_LAST_CMD_BIT; + } + (void) nvram_write_dword(pdev, addr, *ptr32, cmd_flags); + cmd_flags = base_flags; + ptr32++; + } + + /* Loop to write back the buffer data from data_end to page_end */ + for (addr=data_end; addr<page_end; addr+=4, idx++) + { + if (pdev->hw_info.flash_spec.buffered == 0) + { + /* Write back only for non-buffered flash */ + if (addr == page_end-4) + { + cmd_flags = NVRAM_FLAG_SET_LAST_CMD_BIT | base_flags; + } + (void) nvram_write_dword(pdev, addr, flash_buffer[idx], cmd_flags); + cmd_flags = base_flags; + } + } + + /* Disable writes to flash interface (lock write-protect) */ + (void) disable_nvram_write(pdev); + + /* Disable access to flash interface */ + (void) disable_nvram_access(pdev); + release_nvram_lock(pdev); + + /* Increment written_so_far */ + written_so_far += data_end - data_start; + } // while + } + else if (CHIP_NUM(pdev) == CHIP_NUM_5709) + { + /* Request access to the flash interface. */ + lm_status = acquire_nvram_lock(pdev); + if(lm_status != LM_STATUS_SUCCESS) return lm_status; + + /* Enable access to flash interface */ + lm_status = enable_nvram_access(pdev); + if(lm_status != LM_STATUS_SUCCESS) return lm_status; + + cmd_flags = NVRAM_FLAG_SET_FIRST_CMD_BIT; + addr = offset; + while (written_so_far < buf_size) + { + if (written_so_far == (buf_size - 4)) + cmd_flags |= NVRAM_FLAG_SET_LAST_CMD_BIT; + else if (((addr & 0xff) + 4) == 256) + cmd_flags |= NVRAM_FLAG_SET_LAST_CMD_BIT; + if ((addr & 0xff) == 0) + cmd_flags |= NVRAM_FLAG_SET_FIRST_CMD_BIT; + (void) nvram_write_dword(pdev, addr, *ptr32, cmd_flags); + ptr32++; + addr += 4; + written_so_far += 4; + cmd_flags = 0; + } + /* Disable access to flash interface */ + (void) disable_nvram_access(pdev); + release_nvram_lock(pdev); + } + + return lm_status; + +} /* lm_nvram_write */ diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c new file mode 100644 index 0000000000..c0084fcd8f --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c @@ -0,0 +1,4100 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "54xx_reg.h" +#include "serdes.h" +#include "lm5706.h" +#include "netlink.h" + + + +/******************************************************************************* + * Macros. + ******************************************************************************/ + +#define MII_REG(_type, _field) (OFFSETOF(_type, _field)/2) + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_mwrite( + lm_device_t *pdev, + u32_t phy_addr, + u32_t reg, + u32_t val) +{ + lm_status_t lm_status; + u32_t tmp; + u32_t cnt; + + DbgBreakIf(pdev->params.enable_remote_phy); + + if(pdev->params.phy_int_mode == PHY_INT_MODE_AUTO_POLLING) + { + REG_RD(pdev, emac.emac_mdio_mode, &tmp); + tmp &= ~EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(pdev, emac.emac_mdio_mode, tmp); + + mm_wait(pdev, 40); + } + + tmp = (phy_addr << 21) | + (reg << 16) | + val | + EMAC_MDIO_COMM_COMMAND_WRITE_TE | + EMAC_MDIO_COMM_START_BUSY | + EMAC_MDIO_COMM_DISEXT; + + REG_WR(pdev, emac.emac_mdio_comm, tmp); + + for(cnt = 0; cnt < 1000; cnt++) + { + mm_wait(pdev, 10); + + REG_RD(pdev, emac.emac_mdio_comm, &tmp); + if(!(tmp & EMAC_MDIO_COMM_START_BUSY)) + { + mm_wait(pdev, 5); + break; + } + } + + if(tmp & EMAC_MDIO_COMM_START_BUSY) + { + DbgBreakMsg("Write phy register failed\n"); + + lm_status = LM_STATUS_FAILURE; + } + else + { + lm_status = LM_STATUS_SUCCESS; + } + + if(pdev->params.phy_int_mode == PHY_INT_MODE_AUTO_POLLING) + { + REG_RD(pdev, emac.emac_mdio_mode, &tmp); + tmp |= EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(pdev, emac.emac_mdio_mode, tmp); + } + + return lm_status; +} /* lm_mwrite */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_mread( + lm_device_t *pdev, + u32_t phy_addr, + u32_t reg, + u32_t *ret_val) +{ + lm_status_t lm_status; + u32_t val; + u32_t cnt; + + DbgBreakIf(pdev->params.enable_remote_phy); + + if(pdev->params.phy_int_mode == PHY_INT_MODE_AUTO_POLLING) + { + REG_RD(pdev, emac.emac_mdio_mode, &val); + val &= ~EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(pdev, emac.emac_mdio_mode, val); + + mm_wait(pdev, 40); + } + + val = (phy_addr << 21) | + (reg << 16) | + EMAC_MDIO_COMM_COMMAND_READ_TE | + EMAC_MDIO_COMM_DISEXT | + EMAC_MDIO_COMM_START_BUSY; + + REG_WR(pdev, emac.emac_mdio_comm, val); + + for(cnt = 0; cnt < 1000; cnt++) + { + mm_wait(pdev, 10); + + REG_RD(pdev, emac.emac_mdio_comm, &val); + if(!(val & EMAC_MDIO_COMM_START_BUSY)) + { + /* There is a bug here. The MI_COM_BUSY bit may be cleared + * before the data is loaded into the register. */ + REG_RD(pdev, emac.emac_mdio_comm, &val); + + REG_RD(pdev, emac.emac_mdio_comm, &val); + val &= EMAC_MDIO_COMM_DATA; + + break; + } + } + + if(val & EMAC_MDIO_COMM_START_BUSY) + { + DbgBreakMsg("Read phy register failed\n"); + + val = 0; + + lm_status = LM_STATUS_FAILURE; + } + else + { + lm_status = LM_STATUS_SUCCESS; + } + + *ret_val = val; + + if(pdev->params.phy_int_mode == PHY_INT_MODE_AUTO_POLLING) + { + REG_RD(pdev, emac.emac_mdio_mode, &val); + val |= EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(pdev, emac.emac_mdio_mode, val); + } + + return lm_status; +} /* lm_mread */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u32_t +phy_ad_settings( + lm_device_t *pdev, + lm_medium_t req_medium, + lm_flow_control_t flow_ctrl) +{ + u32_t val; + + val = 0; + + /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */ + if((flow_ctrl == LM_FLOW_CONTROL_AUTO_PAUSE) || + ((flow_ctrl & LM_FLOW_CONTROL_RECEIVE_PAUSE) && + (flow_ctrl & LM_FLOW_CONTROL_TRANSMIT_PAUSE))) + { + if(GET_MEDIUM_TYPE(req_medium) == LM_MEDIUM_TYPE_FIBER) + { + if(CHIP_NUM(pdev) == CHIP_NUM_5706) + { + val |= PHY_AN_AD_1000X_PAUSE_CAPABLE | + PHY_AN_AD_1000X_ASYM_PAUSE; + } + else + { + val |= MII_ADVERT_PAUSE; + } + } + else + { + val |= PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE; + } + } + else if(flow_ctrl & LM_FLOW_CONTROL_TRANSMIT_PAUSE) + { + if(GET_MEDIUM_TYPE(req_medium) == LM_MEDIUM_TYPE_FIBER) + { + if(CHIP_NUM(pdev) == CHIP_NUM_5706) + { + val |= PHY_AN_AD_1000X_ASYM_PAUSE; + } + else + { + val |= MII_ADVERT_ASYM_PAUSE; + } + } + else + { + val |= PHY_AN_AD_ASYM_PAUSE; + } + } + else if(flow_ctrl & LM_FLOW_CONTROL_RECEIVE_PAUSE) + { + if(GET_MEDIUM_TYPE(req_medium) == LM_MEDIUM_TYPE_FIBER) + { + if(CHIP_NUM(pdev) == CHIP_NUM_5706) + { + val |= PHY_AN_AD_1000X_PAUSE_CAPABLE | + PHY_AN_AD_1000X_ASYM_PAUSE; + } + else + { + val |= MII_ADVERT_PAUSE; + } + } + else + { + val |= PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE; + } + } + + return val; +} /* phy_ad_settings */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +init_utp( + lm_device_t *pdev, + lm_medium_t req_medium, + lm_flow_control_t flow_ctrl, + u32_t selective_autoneg, + u32_t wire_speed, + u32_t wait_link_timeout_us) +{ + u32_t restart_autoneg; + lm_status_t lm_status; + lm_medium_t duplex; + lm_medium_t speed; + u32_t val; + u32_t cnt; + + if(GET_MEDIUM_TYPE(req_medium) != LM_MEDIUM_TYPE_UTP) + { + return LM_STATUS_INVALID_PARAMETER; + } + + speed = GET_MEDIUM_SPEED(req_medium); + duplex = GET_MEDIUM_DUPLEX(req_medium); + + lm_status = LM_STATUS_SUCCESS; + + (void) lm_mwrite(pdev, pdev->params.phy_addr, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); + for(cnt = 0; cnt < 1000; cnt++) + { + mm_wait(pdev, 5); + + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_CTRL_REG, &val); + + if(!(val & PHY_CTRL_PHY_RESET)) + { + mm_wait(pdev, 5); + + break; + } + } + + DbgBreakIf(val & PHY_CTRL_PHY_RESET); + + /* Get the PHY id. */ + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_ID1_REG, &val); + pdev->hw_info.phy_id = val << 16; + DbgMessage1(pdev, INFORM, "Phy Id1 0x%x\n", val); + + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_ID2_REG, &val); + pdev->hw_info.phy_id |= val & 0xffff; + DbgMessage1(pdev, INFORM, "Phy Id2 0x%x\n", val); + + DbgBreakIf( + (pdev->hw_info.phy_id & 0x0fffffff) == 0x0fffffff || + pdev->hw_info.phy_id == 0); + + if(CHIP_REV(pdev) == CHIP_REV_FPGA) + { + /* Configure how the MAC obtain link from the external PHY. + * On the FPGA board, LED2 is used as a link signal into the + * MAC. Configure LED2 to a link event on the AC101L PHY. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 28, 0x3044); + (void) lm_mwrite(pdev, pdev->params.phy_addr, 29, 0x0100); + } + else + { + if(CHIP_NUM(pdev) == CHIP_NUM_5706 || CHIP_NUM(pdev) == CHIP_NUM_5708) + { + /* Gen6 PHY core has a slight increase in CRC error. + * This will workaround the problem which will be + * fixed in Gen7 PHY core. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x18, 0x0c00); + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x17, 0x000a); + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x15, 0x310b); + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x17, 0x201f); + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x15, 0x9506); + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x17, 0x401f); + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x15, 0x14e2); + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x18, 0x0400); + } + + /* Enable/Disable Ethernet@WireSpeed. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x18, 0x7007); + (void) lm_mread(pdev, pdev->params.phy_addr, 0x18, &val); + + val &= 0x0ff8; + + if(wire_speed) + { + val |= 0x10; + } + else + { + val &= ~0x10; + } + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x18, val | 0x8000 | 0x7); + + /* + * Cont00039501 Issue Description: Auto MDIX mode doesn't work in forced speed + * while two 5716 connected back-to-back + */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x18, 0x7007); + (void) lm_mread(pdev, pdev->params.phy_addr, 0x18, &val); + val |= BIT_9; /*auto mdix*/ + (void) lm_mwrite(pdev, pdev->params.phy_addr, BCM5401_AUX_CTRL, val | 0x8000 | 0x7); + + } + + /* Expansion register 0x8 is the 10BT control register. BIT 8 of this + * register controls the Early DAC Wakeup Enable. this bit allows the + * transmitter to be shutdown in 10BT mode except for sending out link + * pulses. This allows for a low power operation in 10BT mode which is + * useful in WOL application. The default value of this register bit + * gets loaded from a strap value on the GPHY provided by the chip that + * instantiates the PHY. in Xinan this strap value is 1, meaning that + * the early DAC Wakeup Enable bit is set by default. FW/Driver needs to + * clear this bit when bringing the PHY out of reset. */ + if(CHIP_ID(pdev) == CHIP_ID_5709_A0 || + CHIP_ID(pdev) == CHIP_ID_5709_A1 || + CHIP_ID(pdev) == CHIP_ID_5709_B0 || + CHIP_ID(pdev) == CHIP_ID_5709_B1) + { + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x17, 0xf08); + (void) lm_mread(pdev, pdev->params.phy_addr, 0x15, &val); + val &= ~0x100; + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x15, val); + } + + /* Configure the PHY for jumbo frame. */ + if(pdev->params.mtu > MAX_ETHERNET_PACKET_SIZE) + { + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x10, 0x0001); + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x18, 0x4400); + } + else + { + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x10, 0x0000); + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x18, 0x0400); + } + + /* Configure line speed. */ + restart_autoneg = FALSE; + + switch(speed) + { + case LM_MEDIUM_SPEED_10MBPS: + /* Don't advertise 1000mb. This register is undefined on a + * 10/100 Mb PHY. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, PHY_1000BASET_CTRL_REG, 0); + + /* Setup AN_AD to advertise 10mb. */ + val = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + val |= phy_ad_settings(pdev, req_medium, flow_ctrl); + + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + val |= PHY_AN_AD_10BASET_FULL; + + if(selective_autoneg == SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS) + { + val |= PHY_AN_AD_10BASET_HALF; + } + } + else + { + val |= PHY_AN_AD_10BASET_HALF; + } + + (void) lm_mwrite(pdev, pdev->params.phy_addr, PHY_AN_AD_REG, val); + + /* Forcing or advertising 10mb. */ + if(selective_autoneg) + { + restart_autoneg = TRUE; + + DbgMessage(pdev, INFORM, "autoneg 10mb hd\n"); + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + DbgMessage(pdev, INFORM, "and 10mb fd\n"); + } + } + else + { + if(duplex == LM_MEDIUM_HALF_DUPLEX) + { + DbgMessage(pdev, INFORM, "force 10mb hd\n"); + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + PHY_CTRL_REG, + PHY_CTRL_SPEED_SELECT_10MBPS); + } + else + { + DbgMessage(pdev, INFORM, "force 10mb fd\n"); + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + PHY_CTRL_REG, + PHY_CTRL_SPEED_SELECT_10MBPS | + PHY_CTRL_FULL_DUPLEX_MODE); + } + } + + break; + + case LM_MEDIUM_SPEED_100MBPS: + /* Don't advertise 1000mb. This register is undefined on a + * 10/100 PHY. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, PHY_1000BASET_CTRL_REG, 0); + + /* Setup AN_AD to advertise 10/100mb. */ + val = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + val |= phy_ad_settings(pdev, req_medium, flow_ctrl); + + if(selective_autoneg == SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS) + { + val |= PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL; + } + + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + val |= PHY_AN_AD_100BASETX_FULL; + + if(selective_autoneg == SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS) + { + val |= PHY_AN_AD_100BASETX_HALF; + } + } + else + { + val |= PHY_AN_AD_100BASETX_HALF; + } + + (void) lm_mwrite(pdev, pdev->params.phy_addr, PHY_AN_AD_REG, val); + + /* Forcing or advertising 100mb. */ + if(selective_autoneg) + { + restart_autoneg = TRUE; + + DbgMessage(pdev, INFORM, "autoneg 10mb and 100mb hd\n"); + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + DbgMessage(pdev, INFORM, "and 100mb fd\n"); + } + } + else + { + if(duplex == LM_MEDIUM_HALF_DUPLEX) + { + DbgMessage(pdev, INFORM, "force 100mb hd\n"); + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + PHY_CTRL_REG, + PHY_CTRL_SPEED_SELECT_100MBPS); + } + else + { + DbgMessage(pdev, INFORM, "force 100mb fd\n"); + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + PHY_CTRL_REG, + PHY_CTRL_SPEED_SELECT_100MBPS | + PHY_CTRL_FULL_DUPLEX_MODE); + } + } + + break; + + case LM_MEDIUM_SPEED_1000MBPS: + /* Don't advertise 10/100mb. */ + val = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + val |= phy_ad_settings(pdev, req_medium, flow_ctrl); + + if(selective_autoneg == SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS) + { + val |= PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL; + val |= PHY_AN_AD_100BASETX_HALF | PHY_AN_AD_100BASETX_FULL; + } + + (void) lm_mwrite(pdev, pdev->params.phy_addr, PHY_AN_AD_REG, val); + + /* Setup AN_AD to advertise 1000mb. This register is defined on + * a 10/100 Mb PHY. */ + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + val |= PHY_AN_AD_1000BASET_FULL; + + if(selective_autoneg == SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS) + { + val |= PHY_AN_AD_1000BASET_HALF; + } + } + else + { + val |= PHY_AN_AD_1000BASET_HALF; + } + + /* Forcing or advertising 1000mb. */ + if(selective_autoneg) + { + DbgMessage(pdev, INFORM, "autoneg 10/100mb and 1000mb hd\n"); + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + DbgMessage(pdev, INFORM, "and 1000mb fd\n"); + } + + restart_autoneg = TRUE; + } + else + { + /* external loopback at 1gb link. */ + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + PHY_CTRL_REG, + PHY_CTRL_SPEED_SELECT_1000MBPS); + + (void) lm_mwrite(pdev, pdev->params.phy_addr, BCM5401_AUX_CTRL, 0x7); + (void) lm_mread(pdev, pdev->params.phy_addr, BCM5401_AUX_CTRL, &val); + val |= BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK; + (void) lm_mwrite(pdev, pdev->params.phy_addr, BCM5401_AUX_CTRL, val); + + val = PHY_CONFIG_AS_MASTER | PHY_ENABLE_CONFIG_AS_MASTER; + } + + (void) lm_mwrite(pdev, pdev->params.phy_addr, PHY_1000BASET_CTRL_REG, val); + break; + + default: + val = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | + PHY_AN_AD_10BASET_HALF | + PHY_AN_AD_10BASET_FULL | + PHY_AN_AD_100BASETX_FULL | + PHY_AN_AD_100BASETX_HALF; + val |= phy_ad_settings(pdev, req_medium, flow_ctrl); + + /* Set up the 10/100 advertisement register. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, PHY_AN_AD_REG, val); + + /* Advertise 1000Mbps. This register is undefined on a + * 10/100 Mb PHY. */ + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + PHY_1000BASET_CTRL_REG, + PHY_AN_AD_1000BASET_HALF | + PHY_AN_AD_1000BASET_FULL); + + restart_autoneg = TRUE; + speed = LM_MEDIUM_SPEED_AUTONEG; + break; + } + + /* exit mac loopback. we could be in mac loopback mode if previously + * the upper module calls lm_init_phy with LM_MEDIUM_TYPE_MAC_LOOPBACK + * medium type for diagnostic. */ + REG_RD(pdev, emac.emac_mode, &val); + val &= ~(EMAC_MODE_MAC_LOOP | EMAC_MODE_FORCE_LINK); + REG_WR(pdev, emac.emac_mode, val); + + /* Restart auto-negotation. */ + if(restart_autoneg) + { + DbgMessage(pdev, INFORM, "phy init - restart autoneg\n"); + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + PHY_CTRL_REG, + PHY_CTRL_AUTO_NEG_ENABLE | PHY_CTRL_RESTART_AUTO_NEG); + } + + /* Save current medium settings. */ + SET_MEDIUM_TYPE(pdev->vars.medium, LM_MEDIUM_TYPE_UTP); + SET_MEDIUM_SPEED(pdev->vars.medium, speed); + SET_MEDIUM_DUPLEX(pdev->vars.medium, duplex); + + pdev->vars.cable_is_attached = FALSE; + + /* Wait for link. */ + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_STATUS_REG, &val); + + if(CHIP_REV(pdev) != CHIP_REV_FPGA) + { + /* Wait for link only if the cable is connected. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1c, 0x7c00); + (void) lm_mread(pdev, pdev->params.phy_addr, 0x1c, &val); + if(val & 0x20) + { + for(; ;) + { + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_STATUS_REG, &val); + if(val & PHY_STATUS_LINK_PASS) + { + break; + } + + mm_wait(pdev, 10); + + if(wait_link_timeout_us <= 10) + { + break; + } + + wait_link_timeout_us -= 10; + } + + pdev->vars.cable_is_attached = TRUE; + } + } + + /* Need to read a second time to get the current link status. */ + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_STATUS_REG, &val); + if(val & PHY_STATUS_LINK_PASS) + { + pdev->vars.link_status = LM_STATUS_LINK_ACTIVE; + DbgMessage(pdev, INFORM, "phy init link up\n"); + + pdev->vars.cable_is_attached = TRUE; + } + else + { + pdev->vars.link_status = LM_STATUS_LINK_DOWN; + DbgMessage(pdev, INFORM, "phy init link down\n"); + } + + return lm_status; +} /* init_utp */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u32_t +mii_get_serdes_link_status( + lm_device_t *pdev) +{ + u32_t val; + + /* The link status in the MII status register is not reliable for + * the SERDES part. We need to get the link info from the MAC. */ + if(CHIP_NUM(pdev) == CHIP_NUM_5706 && + lm_get_medium(pdev) == LM_MEDIUM_TYPE_FIBER) + { + REG_RD(pdev, emac.emac_status, &val); + if(val & EMAC_STATUS_LINK) + { + val = PHY_STATUS_LINK_PASS; + } + else + { + val = 0; + } + } + else + { + /* The second read returns the current status. */ + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_STATUS_REG, &val); + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_STATUS_REG, &val); + } + + return val; +} /* mii_get_serdes_link_status */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u8_t +set_5708_serdes_pre_emphasis( + lm_device_t *pdev, + u32_t pre_emphasis) +{ + u8_t restart_autoneg; + u32_t val; + + restart_autoneg = FALSE; + + if(pre_emphasis == 0) + { + (void) lm_mread( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_aneg_nxt_pg_rcv2), + &pre_emphasis); + pre_emphasis &= 0xf; + + if(pre_emphasis != pdev->vars.serdes_pre_emphasis) + { + pdev->vars.serdes_pre_emphasis = pre_emphasis; + + restart_autoneg = TRUE; + + /* Switch to Bank 5. */ + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_block_addr), + MII_BLK_ADDR_TXMISC); + + /* Write the new pre-emphasis. */ + (void) lm_mread( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_tx_misc_reg_t, mii_txactl3), + &val); + + pre_emphasis = + ((pre_emphasis & 0x1) << 15) | + ((pre_emphasis & 0x2) << 13) | + ((pre_emphasis & 0x4) << 11) | + ((pre_emphasis & 0x8) << 9); + val = (val & 0x0fff) | pre_emphasis; + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_tx_misc_reg_t, mii_txactl3), + val); + + /* Select Bank 0. */ + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_block_addr), + MII_BLK_ADDR_DIGITAL); + + /* Restart autoneg. */ + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_ctrl), + MII_CTRL_RESTART_ANEG | MII_CTRL_ANEG_ENA); + } + } + else + { + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_block_addr), + MII_BLK_ADDR_TXMISC); + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_tx_misc_reg_t, mii_txactl3), + pre_emphasis); + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_block_addr), + MII_BLK_ADDR_DIGITAL); + } + + return restart_autoneg; +} /* set_5708_serdes_pre_emphasis */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +init_5708_serdes( + lm_device_t *pdev, + lm_medium_t req_medium, + lm_flow_control_t flow_ctrl, + u32_t selective_autoneg, + u32_t wait_link_timeout_us) +{ + lm_medium_t duplex; + lm_medium_t speed; + u32_t cnt; + u32_t val; + + if(GET_MEDIUM_SPEED(req_medium) == LM_MEDIUM_SPEED_UNKNOWN) + { + selective_autoneg = FALSE; + } + + speed = GET_MEDIUM_SPEED(req_medium); + duplex = GET_MEDIUM_DUPLEX(req_medium); + + if(speed == LM_MEDIUM_SPEED_HARDWARE_DEFAULT) + { + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, dev_info.port_hw_config.config), + &val); + + switch(val & PORT_HW_CFG_DEFAULT_LINK_MASK) + { + case PORT_HW_CFG_DEFAULT_LINK_1G: + speed = LM_MEDIUM_SPEED_1000MBPS; + break; + + case PORT_HW_CFG_DEFAULT_LINK_2_5G: + speed = LM_MEDIUM_SPEED_2500MBPS; + break; + + default: + speed = LM_MEDIUM_SPEED_UNKNOWN; + break; + } + } + + /* Reset the SERDES. */ + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_ctrl), + MII_CTRL_RESET); + + for(cnt = 0; cnt < 1000; cnt++) + { + mm_wait(pdev, 5); + + (void) lm_mread( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_ctrl), + &val); + + if(!(val & MII_CTRL_RESET)) + { + mm_wait(pdev, 5); + + break; + } + } + + DbgBreakIf(val & MII_CTRL_RESET); + + /* Workaround for 5708A0 and B0. + * + * Errata 1.75: Tx peak-to-peak amplitude was measured as low + * as 765mV under full PVT testing, whereas 800mV is considered + * a passing result. */ + if(CHIP_NUM(pdev) == CHIP_NUM_5708) + { + /* Switch to Bank 5. */ + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_block_addr), + MII_BLK_ADDR_TXMISC); + + (void) lm_mread( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_tx_misc_reg_t, mii_txactl1), + &val); + + val &= ~ MII_TXACTL1_DRIVER_VCM; + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_tx_misc_reg_t, mii_txactl1), + val); + } + + /* Set up pre-emphasis for a backplane application. */ + if(pdev->hw_info.nvm_hw_config & SHARED_HW_CFG_BACKPLANE_APP) + { + (void) set_5708_serdes_pre_emphasis(pdev, pdev->params.serdes_pre_emphasis); + } + + /* Reset the pre_emphasis. */ + pdev->vars.serdes_pre_emphasis = 0; + + /* Get the PHY id. */ + (void) lm_mread( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_phy_id_msb), + &val); + pdev->hw_info.phy_id = val << 16; + DbgMessage1(pdev, INFORM, "Phy Id1 0x%x\n", val); + + (void) lm_mread( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_phy_id_lsb), + &val); + pdev->hw_info.phy_id |= val & 0xffff; + DbgMessage1(pdev, INFORM, "Phy Id2 0x%x\n", val); + + DbgBreakIf((pdev->hw_info.phy_id & 0x0fffffff) == 0x0fffffff || + pdev->hw_info.phy_id == 0); + + /* Enable 2.5G register set to be accessible in the IEEE registers. */ + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_block_addr), + MII_BLK_ADDR_DIGITAL3); + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_digital3_reg_t, mii_digctl_3_0), + MII_DIG3_USE_IEEE); + + /* Switch back to the IEEE Bank. */ + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_block_addr), + MII_BLK_ADDR_DIGITAL); + + /* Enable SGMII/Fiber mode autodetection. */ + (void) lm_mread( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1), + &val); + + val |= MII_1000X_CTL1_FIBER_MODE | MII_1000X_CTL1_AUTODET_EN; + + /* Sigdet is enabled by default. For backplane application, we need + * to disable Sigdet by clearing 0*0x10.2 of the Digital Bank. */ + if(pdev->hw_info.nvm_hw_config & SHARED_HW_CFG_BACKPLANE_APP) + { + val &= ~MII_1000X_CTL1_SIG_DET_EN; + } + else + { + val |= MII_1000X_CTL1_SIG_DET_EN; + } + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1), + val); + + /* We should always enable parallel detection. */ + (void) lm_mread( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl2), + &val); + + val |= MII_1000X_CTL2_PAR_DET_EN; + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl2), + val); + + /* Enable/disable 2.5G capability. */ + (void) lm_mread( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_aneg_nxt_pg_xmit1), + &val); + + val &= ~MII_ANEG_NXT_PG_XMIT1_2G5; + + if(selective_autoneg) + { + if(speed == LM_MEDIUM_SPEED_2500MBPS) + { + val |= MII_ANEG_NXT_PG_XMIT1_2G5; + } + } + else if(speed == LM_MEDIUM_SPEED_AUTONEG) + { + if(pdev->hw_info.nvm_hw_config & SHARED_HW_CFG_PHY_FIBER_2_5G) + { + val |= MII_ANEG_NXT_PG_XMIT1_2G5; + } + } + else if(speed == LM_MEDIUM_SPEED_2500MBPS) + { + val |= MII_ANEG_NXT_PG_XMIT1_2G5; + } + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_aneg_nxt_pg_xmit1), + val); + + val = 0; + + if(selective_autoneg || speed == LM_MEDIUM_SPEED_UNKNOWN) + { + val |= phy_ad_settings(pdev, req_medium, flow_ctrl); + + if((selective_autoneg && speed == LM_MEDIUM_SPEED_1000MBPS) || + speed == LM_MEDIUM_SPEED_UNKNOWN) + { + val |= MII_ABILITY_HALF | MII_ABILITY_FULL; + } + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_aneg_advert), + val); + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_ctrl), + MII_CTRL_RESTART_ANEG | MII_CTRL_ANEG_ENA); + + speed = LM_MEDIUM_SPEED_AUTONEG; + } + else + { + switch(speed) + { + case LM_MEDIUM_SPEED_10MBPS: + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + val |= MII_CTRL_DUPLEX_MODE; + } + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_ctrl), + val); + /* Switch to SGMII mode and disable auto-detect */ + (void) lm_mread( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1), + &val); + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1), + val & ~(MII_1000X_CTL1_FIBER_MODE | MII_1000X_CTL1_AUTODET_EN)); + break; + + case LM_MEDIUM_SPEED_100MBPS: + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + val |= MII_CTRL_DUPLEX_MODE; + } + + val |= MII_CTRL_MANUAL_SPD0; + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_ctrl), + val); + /* Switch to SGMII mode and disable auto-detect */ + (void) lm_mread( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1), + &val); + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1), + val & ~(MII_1000X_CTL1_FIBER_MODE | MII_1000X_CTL1_AUTODET_EN)); + break; + + case LM_MEDIUM_SPEED_1000MBPS: + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + val |= MII_CTRL_DUPLEX_MODE; + } + + val |= MII_CTRL_MANUAL_SPD1; + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_ctrl), + val); + break; + + case LM_MEDIUM_SPEED_2500MBPS: + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + val |= MII_CTRL_DUPLEX_MODE; + } + + val |= MII_CTRL_MANUAL_FORCE_2500; + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_ctrl), + val); + break; + } + } + + /* exit mac loopback. we could be in mac loopback mode if previously + * the upper module calls lm_init_phy with LM_MEDIUM_TYPE_MAC_LOOPBACK + * medium type for diagnostic. */ + REG_RD(pdev, emac.emac_mode, &val); + val &= ~(EMAC_MODE_MAC_LOOP | EMAC_MODE_FORCE_LINK); + REG_WR(pdev, emac.emac_mode, val); + + /* Configure the PHY for jumbo frame. */ + if(pdev->params.mtu > MAX_ETHERNET_PACKET_SIZE) + { + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl3), + MII_1000X_CTL3_FIFO_ELAST_10K); + } + else + { + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl3), + 0); + } + + /* Save current medium settings. */ + SET_MEDIUM_TYPE(pdev->vars.medium, LM_MEDIUM_TYPE_FIBER); + SET_MEDIUM_SPEED(pdev->vars.medium, speed); + SET_MEDIUM_DUPLEX(pdev->vars.medium, duplex); + + pdev->vars.cable_is_attached = FALSE; + + /* Wait for link. */ + (void) lm_mread( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_status), + &val); + + for(; ;) + { + (void) lm_mread( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_status), + &val); + if(val & MII_STAT_LINK_STATUS) + { + break; + } + + mm_wait(pdev, 10); + + if(wait_link_timeout_us <= 10) + { + break; + } + + wait_link_timeout_us -= 10; + } + + /* Need to read a second time to get the current link status. */ + (void) lm_mread( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_status), + &val); + if(val & MII_STAT_LINK_STATUS) + { + pdev->vars.link_status = LM_STATUS_LINK_ACTIVE; + DbgMessage(pdev, INFORM, "phy init link up\n"); + + pdev->vars.cable_is_attached = TRUE; + } + else + { + pdev->vars.link_status = LM_STATUS_LINK_DOWN; + DbgMessage(pdev, INFORM, "phy init link down\n"); + } + + return LM_STATUS_SUCCESS; +} /* init_5708_serdes */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +force_5709_serdes_link( + lm_device_t *pdev, + lm_medium_t speed, + lm_medium_t duplex) +{ + u32_t val; + + /* select serdes digital block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0x8300); + + /* disable sgmii/fiber mode autodetection. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x10, &val); + val &= ~0x10; + + /* sgmii or 1000x_fiber mode. */ + val &= ~1; + if(speed == LM_MEDIUM_SPEED_2500MBPS) + { + val |= 1; + } + + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x10, val); + + /* select combo ieee0 block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0xffe0); + + /* phy control register. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x10, &val); + + val &= ~0x1000; /* autoneg. */ + val &= ~0x100; /* duplex. */ + val &= ~0x2060; /* speed. */ + + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + val |= 0x100; + } + + if(speed == LM_MEDIUM_SPEED_10MBPS) + { + /* bit 13 and 6 are already cleared. */ + ; + } + else if(speed == LM_MEDIUM_SPEED_100MBPS) + { + val |= 0x2000; + } + else if(speed == LM_MEDIUM_SPEED_1000MBPS) + { + val |= 0x2040; + } + else if(speed == LM_MEDIUM_SPEED_2500MBPS) + { + val |= 0x20; + } + else + { + DbgBreakMsg("unknown forced speed.\n"); + } + + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x10, val); + + /* set speed. */ + if(speed == LM_MEDIUM_SPEED_2500MBPS) + { + /* select serdes digital block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0x8300); + + /* set 2.5g speed. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x18, &val); + val &= 0xfff0; + val |= 0x10; + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x18, val); + } +} /* force_5709_serdes_link */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_5709_serdes_for_autoneg( + lm_device_t *pdev, + lm_medium_t req_medium, + lm_flow_control_t flow_ctrl, + u32_t selective_autoneg) +{ + u32_t val; + + if(GET_MEDIUM_SPEED(req_medium) == LM_MEDIUM_SPEED_UNKNOWN) + { + selective_autoneg = FALSE; + } + + if(!(pdev->hw_info.nvm_hw_config & SHARED_HW_CFG_PHY_FIBER_2_5G) || + (selective_autoneg && + GET_MEDIUM_SPEED(req_medium) != LM_MEDIUM_SPEED_2500MBPS)) + { + /* disable 2.5g adv */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0x8320); + (void) lm_mread(pdev, pdev->params.phy_addr, 0x19, &val); + val &= ~1; + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x19, val); + } + + /* select serdes digital block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0x8300); + + /* enable sgmii/fiber mode autodetection. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x10, &val); + val |= 0x10; + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x10, val); + + /* disable parallel detection. */ + if(selective_autoneg) + { + (void) lm_mread(pdev, pdev->params.phy_addr, 0x11, &val); + val &= ~0x1; + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x11, val); + } + + /* select bam next page block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0x8350); + + /* mp5_next_page_control. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x10, &val); + val &= ~3; + val |= 1; /* set bam mode. */ + val |= 2; /* enable t2 mode. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x10, val); + + /* select cl73_userb0 block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0x8370); + + /* enable bam_en, bam_station_mngr_en, bam_np_after_bp_en. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x12, 0xe000); + + /* select ieee1 block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0x10); + + /* advertise 1000kx. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x1, &val); + val |= 0x20; + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1, val); + + /* select ieee0 block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0); + + /* enable cl73 aneg. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x0, &val); + val |= 0x1200; + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x0, val); + + /* select combo ieee0 block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0xffe0); + + /* advertise pause capability and duplex mode. */ + val = phy_ad_settings(pdev, req_medium, flow_ctrl); + if(selective_autoneg && + GET_MEDIUM_SPEED(req_medium) == LM_MEDIUM_SPEED_2500MBPS) + { + val &= ~0x60; + } + else + { + val |= 0x60; /* half/full duplex. */ + } + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x14, val); + + /* autoneg_enable and restart. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x10, &val); + val |= 0x1200; + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x10, val); +} /* init_5709_serdes_for_autoneg */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +init_5709_serdes( + lm_device_t *pdev, + lm_medium_t req_medium, + lm_flow_control_t flow_ctrl, + u32_t selective_autoneg, + u32_t wait_link_timeout_us) +{ + lm_medium_t duplex; + lm_medium_t speed; + u32_t idx; + u32_t val; + + speed = GET_MEDIUM_SPEED(req_medium); + duplex = GET_MEDIUM_DUPLEX(req_medium); + + /* use nvram link speed configuration. */ + if(speed == LM_MEDIUM_SPEED_HARDWARE_DEFAULT) + { + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, dev_info.port_hw_config.config), + &val); + + switch(val & PORT_HW_CFG_DEFAULT_LINK_MASK) + { + case PORT_HW_CFG_DEFAULT_LINK_1G: + speed = LM_MEDIUM_SPEED_1000MBPS; + break; + + case PORT_HW_CFG_DEFAULT_LINK_2_5G: + speed = LM_MEDIUM_SPEED_2500MBPS; + break; + + default: + speed = LM_MEDIUM_SPEED_UNKNOWN; + break; + } + + selective_autoneg = FALSE; + } + + /* set an_mmd. an_mmd is the only register set we need for + * programming xinan serdes. all other registers are can + * be access through an_mmd. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0xffd0); + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1e, 0x3800); + + /* select combo_ieee0 block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0xffe0); + + /* reset. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x10, MII_CTRL_RESET); + for(idx = 0; idx < 1000; idx++) + { + mm_wait(pdev, 5); + + (void) lm_mread(pdev, pdev->params.phy_addr, 0x10, &val); + if(!(val & MII_CTRL_RESET)) + { + mm_wait(pdev, 5); + break; + } + } + DbgBreakIf(val & MII_CTRL_RESET); + + /* get phy id. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x12, &val); + pdev->hw_info.phy_id = val << 16; + (void) lm_mread(pdev, pdev->params.phy_addr, 0x13, &val); + pdev->hw_info.phy_id |= val & 0xffff; + + if(speed == LM_MEDIUM_SPEED_AUTONEG_1G_FALLBACK) + { + speed = LM_MEDIUM_SPEED_AUTONEG; + } + + /* config link speed or autoneg setting. */ + if(speed == LM_MEDIUM_SPEED_AUTONEG || selective_autoneg) + { + init_5709_serdes_for_autoneg( + pdev, + req_medium, + flow_ctrl, + selective_autoneg); + } + else + { + force_5709_serdes_link(pdev, speed, duplex); + } + + /* exit mac loopback. we could be in mac loopback mode if previously + * the upper module calls lm_init_phy with LM_MEDIUM_TYPE_MAC_LOOPBACK + * medium type for diagnostic. */ + REG_RD(pdev, emac.emac_mode, &val); + val &= ~(EMAC_MODE_MAC_LOOP | EMAC_MODE_FORCE_LINK); + REG_WR(pdev, emac.emac_mode, val); + + SET_MEDIUM_TYPE(pdev->vars.medium, LM_MEDIUM_TYPE_FIBER); + SET_MEDIUM_SPEED(pdev->vars.medium, speed); + SET_MEDIUM_DUPLEX(pdev->vars.medium, duplex); + + pdev->vars.cable_is_attached = FALSE; + + /* select combo_ieee0 block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0xffe0); + + /* wait for link. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x11, &val); + + for(; ;) + { + (void) lm_mread(pdev, pdev->params.phy_addr, 0x11, &val); + if(val & 0x4) + { + break; + } + + mm_wait(pdev, 10); + + if(wait_link_timeout_us <= 10) + { + break; + } + + wait_link_timeout_us -= 10; + } + + /* need to read a second time to get the current link status. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x11, &val); + + if(val & MII_STAT_LINK_STATUS) + { + pdev->vars.link_status = LM_STATUS_LINK_ACTIVE; + pdev->vars.cable_is_attached = TRUE; + } + else + { + pdev->vars.link_status = LM_STATUS_LINK_DOWN; + } + + return LM_STATUS_SUCCESS; +} /* init_5709_serdes */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +init_5706_serdes( + lm_device_t *pdev, + lm_medium_t req_medium, + lm_flow_control_t flow_ctrl, + u32_t wait_link_timeout_us) +{ + lm_medium_t duplex; + lm_medium_t speed; + u32_t val; + u32_t cnt; + + speed = GET_MEDIUM_SPEED(req_medium); + duplex = GET_MEDIUM_DUPLEX(req_medium); + + if(speed == LM_MEDIUM_SPEED_HARDWARE_DEFAULT) + { + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, dev_info.port_hw_config.config), + &val); + switch(val & PORT_HW_CFG_DEFAULT_LINK_MASK) + { + case PORT_HW_CFG_DEFAULT_LINK_1G: + speed = LM_MEDIUM_SPEED_1000MBPS; + break; + + case PORT_HW_CFG_DEFAULT_LINK_2_5G: + speed = LM_MEDIUM_SPEED_2500MBPS; + break; + + case PORT_HW_CFG_DEFAULT_LINK_AN_1G_FALLBACK: + speed = LM_MEDIUM_SPEED_AUTONEG_1G_FALLBACK; + break; + + case PORT_HW_CFG_DEFAULT_LINK_AN_2_5G_FALLBACK: + speed = LM_MEDIUM_SPEED_AUTONEG_2_5G_FALLBACK; + break; + + default: + speed = LM_MEDIUM_SPEED_UNKNOWN; + } + } + + (void) lm_mwrite(pdev, pdev->params.phy_addr, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); + for(cnt = 0; cnt < 1000; cnt++) + { + mm_wait(pdev, 5); + + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_CTRL_REG, &val); + + if(!(val & PHY_CTRL_PHY_RESET)) + { + mm_wait(pdev, 5); + + break; + } + } + + DbgBreakIf(val & PHY_CTRL_PHY_RESET); + + /* Get the PHY id. */ + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_ID1_REG, &val); + pdev->hw_info.phy_id = val << 16; + DbgMessage1(pdev, INFORM, "Phy Id1 0x%x\n", val); + + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_ID2_REG, &val); + pdev->hw_info.phy_id |= val & 0xffff; + DbgMessage1(pdev, INFORM, "Phy Id2 0x%x\n", val); + + DbgBreakIf((pdev->hw_info.phy_id & 0x0fffffff) == 0x0fffffff || + pdev->hw_info.phy_id == 0); + + /* The 5706S has problem determining link so getting link from + * the MII status register is not reliable. This will force + * the MAC to qualify the link ready signal with signal detect. + * We will need to get the link status from the MAC instead of + * the SERDES (MII status register). */ + if(CHIP_NUM(pdev) == CHIP_NUM_5706 && + lm_get_medium(pdev) == LM_MEDIUM_TYPE_FIBER) + { + REG_WR(pdev, misc.misc_gp_hw_ctl0, + MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE | + MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE); + } + + /* Setup flow control capabilities advertisement. */ + val = PHY_AN_AD_1000X_HALF_DUPLEX; + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + val |= PHY_AN_AD_1000X_FULL_DUPLEX; + } + val |= phy_ad_settings(pdev, req_medium, flow_ctrl); + + (void) lm_mwrite(pdev, pdev->params.phy_addr, PHY_AN_AD_REG, val); + + /* Determine the fallback selection. */ + switch(speed) + { + case LM_MEDIUM_SPEED_AUTONEG_1G_FALLBACK: + DbgMessage(pdev, INFORM, "enable serdes_fallback_1g\n"); + pdev->vars.serdes_fallback_select = SERDES_FALLBACK_1G; + break; + + case LM_MEDIUM_SPEED_AUTONEG_2_5G_FALLBACK: + DbgMessage(pdev, INFORM, "enable serdes_fallback_2.5g\n"); + pdev->vars.serdes_fallback_select = SERDES_FALLBACK_2_5G; + break; + + default: + DbgMessage(pdev, INFORM, "disable serdes_fallback.\n"); + pdev->vars.serdes_fallback_select = SERDES_FALLBACK_NONE; + pdev->vars.serdes_fallback_status = SERDES_FALLBACK_NONE; + break; + } + + /* This routine could be called anytime. So if has not gone down + * yet, we want to perserve the fallback setting. */ + if(pdev->vars.serdes_fallback_select != SERDES_FALLBACK_NONE) + { + speed = LM_MEDIUM_SPEED_AUTONEG; + + if(pdev->vars.link_status == LM_STATUS_LINK_ACTIVE) + { + if(pdev->vars.serdes_fallback_status == SERDES_FALLBACK_1G) + { + speed = LM_MEDIUM_SPEED_1000MBPS; + } + else if(pdev->vars.serdes_fallback_status == SERDES_FALLBACK_2_5G) + { + speed = LM_MEDIUM_SPEED_2500MBPS; + } + } + } + + if(speed == LM_MEDIUM_SPEED_1000MBPS) + { + val = PHY_CTRL_SPEED_SELECT_1000MBPS; + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + val |= PHY_CTRL_FULL_DUPLEX_MODE; + } + + (void) lm_mwrite(pdev, pdev->params.phy_addr, PHY_CTRL_REG, val); + } + else + { + val = PHY_CTRL_AUTO_NEG_ENABLE | PHY_CTRL_RESTART_AUTO_NEG; + + (void) lm_mwrite(pdev, pdev->params.phy_addr, PHY_CTRL_REG, val); + + speed = LM_MEDIUM_SPEED_AUTONEG; + } + + /* exit mac loopback. we could be in mac loopback mode if previously + * the upper module calls lm_init_phy with LM_MEDIUM_TYPE_MAC_LOOPBACK + * medium type for diagnostic. */ + REG_RD(pdev, emac.emac_mode, &val); + val &= ~(EMAC_MODE_MAC_LOOP | EMAC_MODE_FORCE_LINK); + REG_WR(pdev, emac.emac_mode, val); + + /* Configure the PHY for jumbo frame. */ + if(pdev->params.mtu > MAX_ETHERNET_PACKET_SIZE) + { + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x18, 0x4400); + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1c, 0xec87); + } + else + { + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x18, 0x0400); + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1c, 0xec85); + } + + SET_MEDIUM_TYPE(pdev->vars.medium, LM_MEDIUM_TYPE_FIBER); + SET_MEDIUM_SPEED(pdev->vars.medium, speed); + SET_MEDIUM_DUPLEX(pdev->vars.medium, duplex); + + pdev->vars.cable_is_attached = FALSE; + + /* Clear the latch bits. The second read below will get the + * current status. */ + val = mii_get_serdes_link_status(pdev); + + /* Wait for link only if the cable is connected. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1c, 0x7c00); + (void) lm_mread(pdev, pdev->params.phy_addr, 0x1c, &val); + if(val & 0x10) + { + for(; ;) + { + val = mii_get_serdes_link_status(pdev); + + if(val & PHY_STATUS_LINK_PASS) + { + break; + } + + mm_wait(pdev, 10); + + if(wait_link_timeout_us <= 10) + { + break; + } + + wait_link_timeout_us -= 10; + } + + pdev->vars.cable_is_attached = TRUE; + } + + /* Need to read a second time to get the current link status. */ + val = mii_get_serdes_link_status(pdev); + + if(val & PHY_STATUS_LINK_PASS) + { + pdev->vars.link_status = LM_STATUS_LINK_ACTIVE; + DbgMessage(pdev, INFORM, "phy init link up\n"); + } + else + { + pdev->vars.link_status = LM_STATUS_LINK_DOWN; + DbgMessage(pdev, INFORM, "phy init link down\n"); + } + + return LM_STATUS_SUCCESS; +} /* init_5706_serdes */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_serdes_or_phy_loopback( + lm_device_t *pdev) +{ + u32_t cnt; + u32_t val; + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + PHY_CTRL_REG, + PHY_CTRL_PHY_RESET); + for(cnt = 0; cnt < 1000; cnt++) + { + mm_wait(pdev, 5); + + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_CTRL_REG, &val); + + if(!(val & PHY_CTRL_PHY_RESET)) + { + mm_wait(pdev, 5); + break; + } + } + + DbgBreakIf(val & PHY_CTRL_PHY_RESET); + + /* Get the PHY id. */ + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_ID1_REG, &val); + pdev->hw_info.phy_id = val << 16; + DbgMessage1(pdev, INFORM, "Phy Id1 0x%x\n", val); + + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_ID2_REG, &val); + pdev->hw_info.phy_id |= val & 0xffff; + DbgMessage1(pdev, INFORM, "Phy Id2 0x%x\n", val); + + DbgBreakIf((pdev->hw_info.phy_id & 0x0fffffff) == 0x0fffffff || + pdev->hw_info.phy_id == 0); + + REG_WR(pdev, emac.emac_tx_lengths, 0x26ff); + + /* Set the phy into loopback mode. */ + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + PHY_CTRL_REG, + PHY_CTRL_LOOPBACK_MODE | + PHY_CTRL_FULL_DUPLEX_MODE | + PHY_CTRL_SPEED_SELECT_1000MBPS); +} /* init_serdes_or_phy_loopback */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_5709_serdes_loopback( + lm_device_t *pdev) +{ + u32_t val; + + /* + * reset causes the speed not be back to 2.5g intermittently + * after phy lookback test when connecting to a switch. + */ +#if 0 + /* select combo_ieee0 block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0xffe0); + + /* reset. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x10, MII_CTRL_RESET); + for(idx = 0; idx < 1000; idx++) + { + mm_wait(pdev, 5); + + (void) lm_mread(pdev, pdev->params.phy_addr, 0x10, &val); + if(!(val & MII_CTRL_RESET)) + { + mm_wait(pdev, 5); + break; + } + } + DbgBreakIf(val & MII_CTRL_RESET); +#endif + + /* set an_mmd. an_mmd is the only register set we need for + * programming xinan serdes. all other registers are can + * be access through an_mmd. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0xffd0); + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1e, 0x3800); + + /* get phy id. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x12, &val); + pdev->hw_info.phy_id = val << 16; + (void) lm_mread(pdev, pdev->params.phy_addr, 0x13, &val); + pdev->hw_info.phy_id |= val & 0xffff; + + /* select combo_ieee0 block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0xffe0); + + /*CQ31687:set autoneg_enable bit too.*/ + /* Set the phy into loopback mode. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x10, 0x5140); + +} /* init_5709_serdes_loopback */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +init_loopback_mac_link( + lm_device_t *pdev, + lm_medium_t req_medium, + lm_flow_control_t flow_ctrl) +{ + lm_status_t lm_status; + u32_t val; + + lm_status = LM_STATUS_SUCCESS; + + if(GET_MEDIUM_TYPE(req_medium) == LM_MEDIUM_TYPE_PHY_LOOPBACK) + { + if(CHIP_NUM(pdev) == CHIP_NUM_5709 && + lm_get_medium(pdev) == LM_MEDIUM_TYPE_FIBER) + { + init_5709_serdes_loopback(pdev); + } + else + { + init_serdes_or_phy_loopback(pdev); + } + + REG_WR(pdev, emac.emac_tx_lengths, 0x26ff); + + REG_RD(pdev, emac.emac_mode, &val); + val &= ~(EMAC_MODE_MAC_LOOP | EMAC_MODE_PORT); + val |= EMAC_MODE_FORCE_LINK | EMAC_MODE_PORT_GMII; + REG_WR(pdev, emac.emac_mode, val); + + SET_MEDIUM_TYPE(pdev->vars.medium, LM_MEDIUM_TYPE_PHY_LOOPBACK); + SET_MEDIUM_SPEED(pdev->vars.medium, LM_MEDIUM_SPEED_UNKNOWN); + SET_MEDIUM_DUPLEX(pdev->vars.medium, LM_MEDIUM_FULL_DUPLEX); + + /* Save current link status. */ + pdev->vars.link_status = LM_STATUS_LINK_ACTIVE; + + pdev->vars.cable_is_attached = TRUE; + } + else if(GET_MEDIUM_TYPE(req_medium) == LM_MEDIUM_TYPE_MAC_LOOPBACK) + { + DbgMessage(pdev, INFORM, "Set up MAC loopback mode.\n"); + + /* Set the MAC into loopback mode. Mac loopback will intermittenly + * fail if half_duplex bit is set. CQ#24594. */ + REG_RD(pdev, emac.emac_mode, &val); + val &= ~(EMAC_MODE_PORT | EMAC_MODE_HALF_DUPLEX); + val |= EMAC_MODE_MAC_LOOP | EMAC_MODE_FORCE_LINK; + + /* The port mode must be set to none on the real chip. */ + if(CHIP_REV(pdev) == CHIP_REV_FPGA) + { + val |= EMAC_MODE_PORT_GMII; + } + + REG_WR(pdev, emac.emac_mode, val); + + SET_MEDIUM_TYPE(pdev->vars.medium, LM_MEDIUM_TYPE_MAC_LOOPBACK); + SET_MEDIUM_SPEED(pdev->vars.medium, LM_MEDIUM_SPEED_UNKNOWN); + SET_MEDIUM_DUPLEX(pdev->vars.medium, LM_MEDIUM_FULL_DUPLEX); + + /* Save current link status. */ + pdev->vars.link_status = LM_STATUS_LINK_ACTIVE; + + pdev->vars.cable_is_attached = TRUE; + } + else + { + DbgBreakMsg("Not loopback medium type.\n"); + + lm_status = LM_STATUS_FAILURE; + + /* Save current link status. */ + pdev->vars.link_status = LM_STATUS_LINK_DOWN; + + pdev->vars.cable_is_attached = FALSE; + } + + /* Enable status block link attention. */ + REG_RD(pdev, hc.hc_attn_bits_enable, &val); + val |= STATUS_ATTN_BITS_LINK_STATE; + REG_WR(pdev, hc.hc_attn_bits_enable, val); + + return lm_status; +} /* init_loopback_mac_link */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +init_null_phy( + lm_device_t *pdev, + lm_medium_t req_medium, + lm_flow_control_t flow_ctrl, + u32_t wait_link_timeout_us) +{ + DbgMessage(pdev, INFORM, "### init_null_phy\n"); + + if(GET_MEDIUM_TYPE(req_medium) != LM_MEDIUM_TYPE_NULL) + { + return LM_STATUS_INVALID_PARAMETER; + } + + /* Save current medium settings. */ + SET_MEDIUM_TYPE(pdev->vars.medium, LM_MEDIUM_TYPE_NULL); + SET_MEDIUM_SPEED(pdev->vars.medium, LM_MEDIUM_SPEED_1000MBPS); + SET_MEDIUM_DUPLEX(pdev->vars.medium, LM_MEDIUM_FULL_DUPLEX); + + pdev->vars.cable_is_attached = TRUE; + + return LM_STATUS_SUCCESS; +} /* init_null_phy */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u32_t +netlink_pause_ad( + lm_flow_control_t flow_ctrl) +{ + u32_t pause_ad; + + pause_ad = 0; + + if((flow_ctrl == LM_FLOW_CONTROL_AUTO_PAUSE) || + ((flow_ctrl & LM_FLOW_CONTROL_RECEIVE_PAUSE) && + (flow_ctrl & LM_FLOW_CONTROL_TRANSMIT_PAUSE))) + { + pause_ad |= NETLINK_DRV_SET_LINK_FC_SYM_PAUSE | + NETLINK_DRV_SET_LINK_FC_ASYM_PAUSE; + } + else if(flow_ctrl & LM_FLOW_CONTROL_TRANSMIT_PAUSE) + { + pause_ad |= NETLINK_DRV_SET_LINK_FC_ASYM_PAUSE; + } + else if(flow_ctrl & LM_FLOW_CONTROL_RECEIVE_PAUSE) + { + pause_ad |= NETLINK_DRV_SET_LINK_FC_SYM_PAUSE | + NETLINK_DRV_SET_LINK_FC_ASYM_PAUSE; + } + + return pause_ad; +} /* netlink_pause_ad */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u32_t +link_setting_to_netlink( + lm_link_settings_t *link_settings, + u32_t serdes) +{ + lm_medium_t duplex; + lm_medium_t speed; + u32_t netlink; + + speed = GET_MEDIUM_SPEED(link_settings->req_medium); + duplex = GET_MEDIUM_DUPLEX(link_settings->req_medium); + netlink = 0; + + switch(speed) + { + case LM_MEDIUM_SPEED_10MBPS: + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + netlink |= NETLINK_DRV_SET_LINK_SPEED_10FULL; + + if((link_settings->flag & LINK_FLAG_SELECTIVE_AUTONEG_MASK) == + LINK_FLAG_SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS) + { + netlink |= NETLINK_DRV_SET_LINK_SPEED_10HALF; + } + } + else + { + netlink |= NETLINK_DRV_SET_LINK_SPEED_10HALF; + } + break; + + case LM_MEDIUM_SPEED_100MBPS: + if((link_settings->flag & LINK_FLAG_SELECTIVE_AUTONEG_MASK) == + LINK_FLAG_SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS) + { + netlink |= NETLINK_DRV_SET_LINK_SPEED_10FULL; + netlink |= NETLINK_DRV_SET_LINK_SPEED_10HALF; + } + + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + netlink |= NETLINK_DRV_SET_LINK_SPEED_100FULL; + + if((link_settings->flag & LINK_FLAG_SELECTIVE_AUTONEG_MASK) == + LINK_FLAG_SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS) + { + netlink |= NETLINK_DRV_SET_LINK_SPEED_100HALF; + } + } + else + { + netlink |= NETLINK_DRV_SET_LINK_SPEED_100HALF; + } + break; + + case LM_MEDIUM_SPEED_1000MBPS: + if((link_settings->flag & LINK_FLAG_SELECTIVE_AUTONEG_MASK) == + LINK_FLAG_SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS) + { + netlink |= NETLINK_DRV_SET_LINK_SPEED_10FULL; + netlink |= NETLINK_DRV_SET_LINK_SPEED_10HALF; + netlink |= NETLINK_DRV_SET_LINK_SPEED_100FULL; + netlink |= NETLINK_DRV_SET_LINK_SPEED_100HALF; + } + + if(duplex == LM_MEDIUM_FULL_DUPLEX) + { + netlink |= NETLINK_DRV_SET_LINK_SPEED_1GFULL; + + if((link_settings->flag & LINK_FLAG_SELECTIVE_AUTONEG_MASK) == + LINK_FLAG_SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS) + { + netlink |= NETLINK_DRV_SET_LINK_SPEED_1GHALF; + } + } + else + { + netlink |= NETLINK_DRV_SET_LINK_SPEED_1GHALF; + } + break; + + default: + if (serdes) + { + netlink |= NETLINK_DRV_SET_LINK_ENABLE_AUTONEG | + NETLINK_DRV_SET_LINK_SPEED_1GHALF | + NETLINK_DRV_SET_LINK_SPEED_1GFULL; + } + else + { + netlink |= NETLINK_DRV_SET_LINK_ENABLE_AUTONEG | + NETLINK_DRV_SET_LINK_SPEED_10HALF | + NETLINK_DRV_SET_LINK_SPEED_10FULL | + NETLINK_DRV_SET_LINK_SPEED_100HALF | + NETLINK_DRV_SET_LINK_SPEED_100FULL | + NETLINK_DRV_SET_LINK_SPEED_1GHALF | + NETLINK_DRV_SET_LINK_SPEED_1GFULL; + } + break; + } + + netlink |= NETLINK_DRV_SET_LINK_PHY_RESET; + + if(link_settings->flag & LINK_FLAG_SELECTIVE_AUTONEG_MASK) + { + netlink |= NETLINK_DRV_SET_LINK_ENABLE_AUTONEG; + } + + if(link_settings->flag & LINK_FLAG_WIRE_SPEED) + { + netlink |= NETLINK_DRV_SET_LINK_ETH_AT_WIRESPEED_ENABLE; + } + + netlink |= netlink_pause_ad(link_settings->flow_ctrl); + + return netlink; +} /* link_settings_to_netlink */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_init_remote_phy( + lm_device_t *pdev, + lm_link_settings_t *serdes_link, + lm_link_settings_t *rphy_link) +{ + u32_t serdes_netlink; + u32_t rphy_netlink; + u32_t set_link_arg; + u32_t val; + + DbgBreakIf(pdev->params.enable_remote_phy == FALSE); + + serdes_netlink = link_setting_to_netlink(serdes_link, TRUE); + rphy_netlink = link_setting_to_netlink(rphy_link, FALSE); + + REG_WR_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, remotephy.serdes_link_pref), + serdes_netlink); + + REG_WR_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, remotephy.copper_phy_link_pref), + rphy_netlink | NETLINK_DRV_SET_LINK_PHY_APP_REMOTE); + + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, drv_fw_mb.link_status), + &val); + if(val & NETLINK_GET_LINK_STATUS_SERDES_LINK) + { + set_link_arg = serdes_netlink; + } + else + { + set_link_arg = rphy_netlink | NETLINK_DRV_SET_LINK_PHY_APP_REMOTE; + } + + REG_WR_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, drv_fw_mb.mb_args[0]), + set_link_arg); + + (void) lm_submit_fw_cmd(pdev, DRV_MSG_CODE_CMD_SET_LINK); + + return LM_STATUS_SUCCESS; +} /* lm_init_remote_phy */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_init_phy( + lm_device_t *pdev, + lm_medium_t req_medium, + lm_flow_control_t flow_ctrl, + u32_t selective_autoneg, + u32_t wire_speed, + u32_t wait_link_timeout_us) +{ + lm_status_t lm_status; + + DbgBreakIf(pdev->params.enable_remote_phy); + + if(GET_MEDIUM_AUTONEG_MODE(req_medium) == LM_MEDIUM_SELECTIVE_AUTONEG) + { + selective_autoneg = TRUE; + } + + if(GET_MEDIUM_TYPE(req_medium) == LM_MEDIUM_AUTO_DETECT) + { + if(CHIP_REV(pdev) == CHIP_REV_IKOS) + { + req_medium = LM_MEDIUM_TYPE_NULL; + } + else if(CHIP_REV(pdev) == CHIP_REV_FPGA) + { + selective_autoneg = TRUE; + req_medium = LM_MEDIUM_TYPE_UTP | + LM_MEDIUM_SPEED_10MBPS | + LM_MEDIUM_FULL_DUPLEX; + } + else if(lm_get_medium(pdev) == LM_MEDIUM_TYPE_FIBER) + { + if(req_medium == LM_MEDIUM_AUTO_DETECT) + { + req_medium = LM_MEDIUM_TYPE_FIBER; + } + else + { + SET_MEDIUM_TYPE(req_medium, LM_MEDIUM_TYPE_FIBER); + } + } + else + { + if(req_medium == LM_MEDIUM_AUTO_DETECT) + { + req_medium = LM_MEDIUM_TYPE_UTP; + } + else + { + SET_MEDIUM_TYPE(req_medium, LM_MEDIUM_TYPE_UTP); + } + } + } + + switch(GET_MEDIUM_TYPE(req_medium)) + { + case LM_MEDIUM_TYPE_UTP: + lm_status = init_utp( + pdev, + req_medium, + flow_ctrl, + selective_autoneg, + wire_speed, + wait_link_timeout_us); + break; + + case LM_MEDIUM_TYPE_FIBER: + DbgBreakIf(CHIP_NUM(pdev) != CHIP_NUM_5706 && + CHIP_NUM(pdev) != CHIP_NUM_5708 && + CHIP_NUM(pdev) != CHIP_NUM_5709); + + if(CHIP_NUM(pdev) == CHIP_NUM_5706) + { + lm_status = init_5706_serdes( + pdev, + req_medium, + flow_ctrl, + wait_link_timeout_us); + } + else if(CHIP_NUM(pdev) == CHIP_NUM_5708) + { + lm_status = init_5708_serdes( + pdev, + req_medium, + flow_ctrl, + selective_autoneg, + wait_link_timeout_us); + } + else + { + lm_status = init_5709_serdes( + pdev, + req_medium, + flow_ctrl, + selective_autoneg, + wait_link_timeout_us); + } + + break; + + case LM_MEDIUM_TYPE_NULL: + lm_status = init_null_phy( + pdev, + req_medium, + flow_ctrl, + wait_link_timeout_us); + break; + + case LM_MEDIUM_TYPE_PHY_LOOPBACK: + case LM_MEDIUM_TYPE_MAC_LOOPBACK: + lm_status = init_loopback_mac_link( + pdev, + req_medium, + flow_ctrl); + break; + + default: + lm_status = LM_STATUS_UNKNOWN_MEDIUM; + break; + } + + return lm_status; +} /* lm_init_phy */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +get_serdes_phy_ad( + lm_device_t *pdev, + u32_t *local_phy_ad, + u32_t *remote_phy_ad) +{ + u32_t val; + + *local_phy_ad = 0; + *remote_phy_ad = 0; + + if(CHIP_NUM(pdev) == CHIP_NUM_5706 || CHIP_NUM(pdev) == CHIP_NUM_5708) + { + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_AN_AD_REG, &val); + + if(val & PHY_AN_AD_1000X_PAUSE_CAPABLE) + { + *local_phy_ad |= PHY_AN_AD_PAUSE_CAPABLE; + } + + if(val & PHY_AN_AD_1000X_ASYM_PAUSE) + { + *local_phy_ad |= PHY_AN_AD_ASYM_PAUSE; + } + + (void) lm_mread(pdev,pdev->params.phy_addr,PHY_LINK_PARTNER_ABILITY_REG,&val); + + if(val & PHY_AN_AD_1000X_PAUSE_CAPABLE) + { + *remote_phy_ad |= PHY_AN_AD_PAUSE_CAPABLE; + } + + if(val & PHY_AN_AD_1000X_ASYM_PAUSE) + { + *remote_phy_ad |= PHY_AN_AD_ASYM_PAUSE; + } + } + else + { + /* select combo ieee0 block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0xffe0); + + /* local advertisement. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x14, &val); + + if(val & 0x80) + { + *local_phy_ad |= PHY_AN_AD_PAUSE_CAPABLE; + } + + if(val & 0x100) + { + *local_phy_ad |= PHY_AN_AD_ASYM_PAUSE; + } + + /* remote advertisement. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x15, &val); + + if(val & 0x80) + { + *remote_phy_ad |= PHY_AN_AD_PAUSE_CAPABLE; + } + + if(val & 0x100) + { + *remote_phy_ad |= PHY_AN_AD_ASYM_PAUSE; + } + } +} /* get_serdes_phy_ad */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_flow_control_t +set_mac_flow_control( + lm_device_t *pdev, + lm_medium_t medium, + lm_flow_control_t flow_control_cap) +{ + lm_flow_control_t flow_ctrl; + u32_t remote_phy_link; + u32_t remote_phy_ad; + u32_t local_phy_ad; + u32_t val; + lm_rx_chain_t *rxq; + u32_t idx; + + if(pdev->params.enable_remote_phy) + { + local_phy_ad = 0; + + if((flow_control_cap == LM_FLOW_CONTROL_AUTO_PAUSE) || + ((flow_control_cap & LM_FLOW_CONTROL_RECEIVE_PAUSE) && + (flow_control_cap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)) || + (flow_control_cap & LM_FLOW_CONTROL_RECEIVE_PAUSE)) + { + local_phy_ad |= (PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE); + } + else if(flow_control_cap & LM_FLOW_CONTROL_TRANSMIT_PAUSE) + { + local_phy_ad |= PHY_AN_AD_ASYM_PAUSE; + } + + remote_phy_ad = 0; + + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, drv_fw_mb.link_status), + &remote_phy_link); + + if(remote_phy_link & NETLINK_GET_LINK_STATUS_PARTNER_SYM_PAUSE_CAP) + { + remote_phy_ad |= PHY_LINK_PARTNER_PAUSE_CAPABLE; + } + + if(remote_phy_link & NETLINK_GET_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP) + { + remote_phy_ad |= PHY_LINK_PARTNER_ASYM_PAUSE; + } + } + else + { + if(GET_MEDIUM_TYPE(medium) == LM_MEDIUM_TYPE_FIBER) + { + get_serdes_phy_ad(pdev, &local_phy_ad, &remote_phy_ad); + } + else + { + (void) lm_mread( + pdev, + pdev->params.phy_addr, + PHY_AN_AD_REG, + &local_phy_ad); + + (void) lm_mread( + pdev, + pdev->params.phy_addr, + PHY_LINK_PARTNER_ABILITY_REG, + &remote_phy_ad); + } + } + + DbgMessage(pdev, INFORM, "Local flow control settings.\n"); + + if(local_phy_ad & PHY_AN_AD_PAUSE_CAPABLE) + { + DbgMessage(pdev, INFORM, " PAUSE capable.\n"); + } + + if(local_phy_ad & PHY_AN_AD_ASYM_PAUSE) + { + DbgMessage(pdev, INFORM, " ASYM_PAUSE capable.\n"); + } + + DbgMessage(pdev, INFORM, "Remote flow control settings.\n"); + + if(remote_phy_ad & PHY_LINK_PARTNER_PAUSE_CAPABLE) + { + DbgMessage(pdev, INFORM, " PAUSE capable.\n"); + } + + if(remote_phy_ad & PHY_LINK_PARTNER_ASYM_PAUSE) + { + DbgMessage(pdev, INFORM, " ASYM_PAUSE capable.\n"); + } + + /* Resultant flow control setting. */ + flow_ctrl = LM_FLOW_CONTROL_NONE; + + if((flow_control_cap & LM_FLOW_CONTROL_AUTO_PAUSE) || + pdev->params.flow_control_reporting_mode) + { + /* See Table 28B-3 of 802.3ab-1999 spec. */ + if(local_phy_ad & PHY_AN_AD_PAUSE_CAPABLE) + { + if(local_phy_ad & PHY_AN_AD_ASYM_PAUSE) + { + if(remote_phy_ad & PHY_LINK_PARTNER_PAUSE_CAPABLE) + { + DbgMessage(pdev, INFORM, "FlowCap: tx/rx\n"); + + flow_ctrl = + LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + else if(remote_phy_ad & PHY_LINK_PARTNER_ASYM_PAUSE) + { + DbgMessage(pdev, INFORM, "FlowCap: rx PAUSE\n"); + + flow_ctrl = LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } + else + { + if(remote_phy_ad & PHY_LINK_PARTNER_PAUSE_CAPABLE) + { + DbgMessage(pdev, INFORM, "FlowCap: tx/rx\n"); + + flow_ctrl = + LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } + } + else if(local_phy_ad & PHY_AN_AD_ASYM_PAUSE) + { + if((remote_phy_ad & PHY_LINK_PARTNER_PAUSE_CAPABLE) && + (remote_phy_ad & PHY_LINK_PARTNER_ASYM_PAUSE)) + { + DbgMessage(pdev, INFORM, "FlowCap: tx PAUSE\n"); + + flow_ctrl = LM_FLOW_CONTROL_TRANSMIT_PAUSE; + } + } + } + else + { + flow_ctrl = flow_control_cap; + } + + DbgMessage(pdev, INFORM, "Flow control capabilities.\n"); + + if(flow_ctrl & LM_FLOW_CONTROL_TRANSMIT_PAUSE) + { + DbgMessage(pdev, INFORM, " tx PAUSE\n"); + } + + if(flow_ctrl & LM_FLOW_CONTROL_RECEIVE_PAUSE) + { + DbgMessage(pdev, INFORM, " rx PAUSE\n"); + } + + if(flow_ctrl == LM_FLOW_CONTROL_NONE) + { + DbgMessage(pdev, INFORM, " none.\n"); + } + + /* Enable/disable rx PAUSE. */ + REG_RD(pdev, emac.emac_rx_mode, &val); + val &= ~EMAC_RX_MODE_FLOW_EN; + + if(flow_ctrl & LM_FLOW_CONTROL_RECEIVE_PAUSE) + { + val |= EMAC_RX_MODE_FLOW_EN; + DbgMessage(pdev, INFORM, "Enable rx PAUSE.\n"); + } + REG_WR(pdev, emac.emac_rx_mode, val); + + /* Enable/disable tx PAUSE. */ + REG_RD(pdev, emac.emac_tx_mode, &val); + val &= ~EMAC_TX_MODE_FLOW_EN; + + if(flow_ctrl & LM_FLOW_CONTROL_TRANSMIT_PAUSE) + { + val |= EMAC_TX_MODE_FLOW_EN; + DbgMessage(pdev, INFORM, "Enable tx PAUSE.\n"); + } + REG_WR(pdev, emac.emac_tx_mode, val); + + for(idx = 0; idx < pdev->rx_info.num_rxq; idx++) + { + rxq = &pdev->rx_info.chain[idx]; + val = CTX_RD( + pdev, + rxq->cid_addr, + WORD_ALIGNED_OFFSETOF(l2_bd_chain_context_t, l2ctx_ctx_type)); + + /* Enable/disable RV2P wait (i.e. watermark field) for buffer post based on flow control setting. */ + if(flow_ctrl & LM_FLOW_CONTROL_TRANSMIT_PAUSE) + { + val |= 0xFF; + } + else + { + // RV2P is checking for non-zero in this byte field + val &= ~0xFF; + } + CTX_WR( + pdev, + rxq->cid_addr, + WORD_ALIGNED_OFFSETOF(l2_bd_chain_context_t, l2ctx_ctx_type), + val); + } + + return flow_ctrl; +} /* set_mac_flow_control */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +get_copper_phy_link( + lm_device_t *pdev, + lm_medium_t *medium) +{ + lm_medium_t duplex; + lm_medium_t speed; + lm_status_t link; + u32_t phy_status; + u32_t remote_adv; + u32_t local_adv; + u32_t phy_ctrl; + u32_t val; + + DbgMessage(pdev, INFORM, "### get_copper_phy_link\n"); + + *medium = LM_MEDIUM_TYPE_UTP | + LM_MEDIUM_SPEED_UNKNOWN | + LM_MEDIUM_FULL_DUPLEX; + + pdev->vars.cable_is_attached = FALSE; + + /* Check for link. The first read returns the latched value, the + * second read returns the current value. */ + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_STATUS_REG, &phy_status); + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_STATUS_REG, &phy_status); + if((phy_status & PHY_STATUS_LINK_PASS) == 0) + { + DbgMessage(pdev, INFORM, "link down.\n"); + + if(CHIP_REV(pdev) != CHIP_REV_FPGA) + { + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1c, 0x7c00); + (void) lm_mread(pdev, pdev->params.phy_addr, 0x1c, &val); + if(val & 0x20) + { + pdev->vars.cable_is_attached = TRUE; + } + } + + return LM_STATUS_LINK_DOWN; + } + + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_CTRL_REG, &phy_ctrl); + + /* Make sure the PHY control register is valid. */ + DbgBreakIf(phy_ctrl & ( + PHY_CTRL_COLLISION_TEST_ENABLE | + PHY_CTRL_RESTART_AUTO_NEG | + PHY_CTRL_ISOLATE_PHY | + PHY_CTRL_LOOPBACK_MODE | + PHY_CTRL_PHY_RESET)); + + link = LM_STATUS_LINK_ACTIVE; + pdev->vars.cable_is_attached = TRUE; + + /* Determine duplex mode. Link is present also means autoneg is done. */ + if(phy_ctrl & PHY_CTRL_AUTO_NEG_ENABLE) + { + /* Autonegotiation is enabled. And since we have link, we know + * autonegotiation has completed. + * + * Infer the link speed by figuring out the highest common speed + * between us and our link partner. */ + + /* Get local and remote 1000BASET advertisement. */ + (void) lm_mread( + pdev, + pdev->params.phy_addr, + PHY_1000BASET_CTRL_REG, + &local_adv); + (void) lm_mread( + pdev, + pdev->params.phy_addr, + PHY_1000BASET_STATUS_REG, + &remote_adv); + + val = local_adv & (remote_adv >> 2); + if(val & PHY_AN_AD_1000BASET_FULL) + { + DbgMessage(pdev, INFORM, "detected 1gb full autoneg.\n"); + + speed = LM_MEDIUM_SPEED_1000MBPS; + duplex = LM_MEDIUM_FULL_DUPLEX; + } + else if(val & PHY_AN_AD_1000BASET_HALF) + { + DbgMessage(pdev, INFORM, "detected 1gb half autoneg.\n"); + + speed = LM_MEDIUM_SPEED_1000MBPS; + duplex = LM_MEDIUM_HALF_DUPLEX; + } + else + { + /* Get local and remote 10/100 mb advertisement. */ + (void) lm_mread( + pdev, + pdev->params.phy_addr, + PHY_AN_AD_REG, + &local_adv); + + (void) lm_mread( + pdev, + pdev->params.phy_addr, + PHY_LINK_PARTNER_ABILITY_REG, + &remote_adv); + + val = local_adv & remote_adv; + if(val & PHY_AN_AD_100BASETX_FULL) + { + DbgMessage(pdev, INFORM, "detected 100mb full autoneg.\n"); + + speed = LM_MEDIUM_SPEED_100MBPS; + duplex = LM_MEDIUM_FULL_DUPLEX; + } + else if(val & PHY_AN_AD_100BASETX_HALF) + { + DbgMessage(pdev, INFORM, "detected 100mb half autoneg.\n"); + + speed = LM_MEDIUM_SPEED_100MBPS; + duplex = LM_MEDIUM_HALF_DUPLEX; + } + else if(val & PHY_AN_AD_10BASET_FULL) + { + DbgMessage(pdev, INFORM, "detected 10mb full autoneg.\n"); + + speed = LM_MEDIUM_SPEED_10MBPS; + duplex = LM_MEDIUM_FULL_DUPLEX; + } + else if(val & PHY_AN_AD_10BASET_HALF) + { + DbgMessage(pdev, INFORM, "detected 10mb half autoneg.\n"); + + speed = LM_MEDIUM_SPEED_10MBPS; + duplex = LM_MEDIUM_HALF_DUPLEX; + } + else + { + DbgBreakMsg("unable to determine autoneg speed.\n"); + + speed = LM_MEDIUM_SPEED_UNKNOWN; + duplex = LM_MEDIUM_FULL_DUPLEX; + link = LM_STATUS_LINK_DOWN; + } + } + } + else + { + /* The link speed speed and duplex mode are forced. Get the forced + * line settings from the PHY control register. */ + if(phy_ctrl & PHY_CTRL_SPEED_SELECT_100MBPS) + { + DbgMessage(pdev, INFORM, "PHY forced to 100mb.\n"); + speed = LM_MEDIUM_SPEED_100MBPS; + } + else if(phy_ctrl & PHY_CTRL_SPEED_SELECT_1000MBPS) + { + DbgMessage(pdev, INFORM, "PHY forced to 1gb.\n"); + + speed = LM_MEDIUM_SPEED_1000MBPS; + } + else + { + DbgMessage(pdev, INFORM, "PHY forced to 10mb.\n"); + + speed = LM_MEDIUM_SPEED_10MBPS; + } + + if(phy_ctrl & PHY_CTRL_FULL_DUPLEX_MODE) + { + DbgMessage(pdev, INFORM, "PHY forced to full duplex.\n"); + + duplex = LM_MEDIUM_FULL_DUPLEX; + } + else + { + DbgMessage(pdev, INFORM, "PHY forced to half duplex.\n"); + + duplex = LM_MEDIUM_HALF_DUPLEX; + } + } + + *medium = LM_MEDIUM_TYPE_UTP | speed | duplex; + + return link; +} /* get_copper_phy_link */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_mac_link( + lm_device_t *pdev, + lm_status_t link, + lm_medium_t medium, + lm_flow_control_t flow_ctrl) +{ + u32_t val; + + /* Configure slot time, IPG, and 802.3 flow control. */ + REG_WR(pdev, emac.emac_tx_lengths, 0x2620); + if(link == LM_STATUS_LINK_ACTIVE) + { + if(GET_MEDIUM_SPEED(medium) == LM_MEDIUM_SPEED_1000MBPS && + GET_MEDIUM_DUPLEX(medium) == LM_MEDIUM_HALF_DUPLEX) + { + REG_WR(pdev, emac.emac_tx_lengths, 0x26ff); + } + + pdev->vars.flow_control = set_mac_flow_control(pdev, medium, flow_ctrl); + } + + /* Configure the EMAC mode register. */ + REG_RD(pdev, emac.emac_mode, &val); + + val &= ~(EMAC_MODE_PORT | EMAC_MODE_FORCE_LINK); + + if(link == LM_STATUS_LINK_ACTIVE) + { + if(GET_MEDIUM_SPEED(medium) == LM_MEDIUM_SPEED_10MBPS) + { + if(CHIP_NUM(pdev) == CHIP_NUM_5706) + { + val |= EMAC_MODE_PORT_MII; + } + else + { + /* 5708 setting. */ + val |= EMAC_MODE_PORT_MII_10M; + } + } + else if(GET_MEDIUM_SPEED(medium) == LM_MEDIUM_SPEED_100MBPS) + { + val |= EMAC_MODE_PORT_MII; + } + else + { + val |= EMAC_MODE_PORT_GMII; + } + + if(GET_MEDIUM_SPEED(medium) == LM_MEDIUM_SPEED_2500MBPS) + { + val |= EMAC_MODE_25G_MODE; + } + + /* We need to set the port mode to GMII when we are running in + * the FPGA mode, regardless of the actual line speed. */ + if(CHIP_REV(pdev) == CHIP_REV_FPGA) + { + val &= ~EMAC_MODE_PORT; + val |= EMAC_MODE_PORT_GMII; + } + } + else + { + val |= EMAC_MODE_PORT_GMII; + } + + if(GET_MEDIUM_TYPE(medium) == LM_MEDIUM_TYPE_NULL) + { + val |= EMAC_MODE_FORCE_LINK; + } + + /* Set the MAC to operate in the appropriate duplex mode. */ + val &= ~EMAC_MODE_HALF_DUPLEX; + if(GET_MEDIUM_DUPLEX(medium) == LM_MEDIUM_HALF_DUPLEX) + { + val |= EMAC_MODE_HALF_DUPLEX; + } + REG_WR(pdev, emac.emac_mode, val); + + /* Acknowledge the interrupt. */ + REG_WR(pdev, emac.emac_status, EMAC_STATUS_LINK_CHANGE); + + /* Enable phy link change attention. */ + if(pdev->params.phy_int_mode == PHY_INT_MODE_MI_INTERRUPT) + { + REG_WR(pdev, emac.emac_attention_ena, EMAC_ATTENTION_ENA_MI_INT); + } + else + { + REG_WR(pdev, emac.emac_attention_ena, EMAC_ATTENTION_ENA_LINK); + } + + /* Enable status block link attention. */ + REG_RD(pdev, hc.hc_attn_bits_enable, &val); + val &= ~STATUS_ATTN_BITS_LINK_STATE; + if(pdev->params.link_chng_mode == LINK_CHNG_MODE_USE_STATUS_BLOCK) + { + val |= STATUS_ATTN_BITS_LINK_STATE; + } + REG_WR(pdev, hc.hc_attn_bits_enable, val); + + pdev->vars.medium = medium; + pdev->vars.link_status = link; +} /* init_mac_link */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +serdes_fallback( + lm_device_t *pdev, + u8_t fallback_select) +{ + u32_t intr_exp_status; + u8_t fallback_to; + u32_t phy_status; + u32_t phy_ctrl; + u32_t val; + u32_t cnt; + + pdev->vars.serdes_fallback_status = SERDES_FALLBACK_NONE; + + if(fallback_select == SERDES_FALLBACK_NONE) + { + return LM_STATUS_LINK_DOWN; + } + + /* See if the cable is connected. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1c, 0x7c00); + (void) lm_mread(pdev, pdev->params.phy_addr, 0x1c, &val); + + /* We think the cable is not attached, set up the serdes to + * autoneg as the default. */ + if(!(val & 0x10)) /* SIG_DETECT */ + { + DbgMessage(pdev, INFORM, "no cable, default to autoneg.\n"); + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + PHY_CTRL_REG, + PHY_CTRL_AUTO_NEG_ENABLE); + + return LM_STATUS_LINK_DOWN; + } + + /* Read the interrupt expansion register to see if rudi_c is set. + * rudi_c is set when we are receiving config words which means + * the link partner is attempting to autonegotiate. + * + * When the link partner is attempting to autonegotiate and we + * are not able to get linke, it could mean our transmit cable + * is not plugged in. In this case we don't want to fallback + * to the force mode. We want to remain in autonegotiation mode. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x17, 0x0f01); + (void) lm_mread(pdev, pdev->params.phy_addr, 0x15, &intr_exp_status); + (void) lm_mread(pdev, pdev->params.phy_addr, 0x15, &intr_exp_status); + + /* See if autoneg is enabled and the remote is not sending us + * configs. If this is the case and link is currently down, we + * will switch to the force mode and disable autonegotiation. + * + * If we are current in the forced mode or the link partner is + * sending use configs, we'll enable autoneg and restart it. */ + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_CTRL_REG, &phy_ctrl); + if((phy_ctrl & PHY_CTRL_AUTO_NEG_ENABLE) && !(intr_exp_status & 0x20)) + { + DbgMessage(pdev, INFORM, "switch to force mode - 1G full\n"); + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + PHY_CTRL_REG, + PHY_CTRL_SPEED_SELECT_1000MBPS | PHY_CTRL_FULL_DUPLEX_MODE); + + fallback_to = SERDES_FALLBACK_1G; + } + else + { + DbgMessage(pdev, INFORM, "switch to autoneg mode - 1G full\n"); + + /* Switch to autoneg mode. */ + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + PHY_CTRL_REG, + PHY_CTRL_AUTO_NEG_ENABLE | PHY_CTRL_RESTART_AUTO_NEG); + + fallback_to = SERDES_FALLBACK_NONE; + } + + for(cnt = 0; cnt < 100; cnt++) + { + mm_wait(pdev, 10); + } + + phy_status = mii_get_serdes_link_status(pdev); + + if(phy_status & PHY_STATUS_LINK_PASS) + { + pdev->vars.serdes_fallback_status = fallback_to; + + return LM_STATUS_LINK_ACTIVE; + } + + return LM_STATUS_LINK_DOWN; +} /* serdes_fallback */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +get_5708_serdes_link( + lm_device_t *pdev, + lm_medium_t *medium) +{ + u8_t restarted_autoneg; + lm_medium_t duplex; + lm_medium_t speed; + lm_status_t link; + u32_t val; + u32_t idx; + + *medium = LM_MEDIUM_TYPE_FIBER | + LM_MEDIUM_SPEED_UNKNOWN | + LM_MEDIUM_FULL_DUPLEX; + + pdev->vars.cable_is_attached = FALSE; + + /* Check for link. The first read returns the latched value, the + * second read returns the current value. */ + (void) lm_mread( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_status), + &val); + (void) lm_mread( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_status), + &val); + + /* CQ#23742 - Link status in the status block and the link status + * in the mii_status are not consistent. mii_status appears to + * return invalid value. Added a workaround here. */ + for(idx = 0; idx < 10 && val == 0; idx++) + { + mm_wait(pdev, 10); + + (void) lm_mread( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_status), + &val); + } + + if((val & MII_STAT_LINK_STATUS) == 0) + { + DbgMessage(pdev, INFORM, "serdes link down.\n"); + + pdev->vars.cable_is_attached = FALSE; + + return LM_STATUS_LINK_DOWN; + } + + link = LM_STATUS_LINK_ACTIVE; + pdev->vars.cable_is_attached = TRUE; + + /* Determine duplex mode. Link is present also means autoneg is done. */ + (void) lm_mread( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_ctrl), + &val); + if(val & MII_CTRL_ANEG_ENA) + { + /* Select Bank 0. */ + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_block_addr), + MII_BLK_ADDR_DIGITAL); + + /* Get the negotiated speed and duplex mode. */ + (void) lm_mread( + pdev, + pdev->params.phy_addr, + 0x10+MII_REG(serdes_digital_reg_t, mii_1000x_stat1), + &val); + switch(val & MII_1000X_STAT1_SPEED) + { + case MII_1000X_STAT1_SPEED_2G5: + DbgMessage(pdev, INFORM, "serdes autoneg to 2.5gb.\n"); + speed = LM_MEDIUM_SPEED_2500MBPS; + break; + + case MII_1000X_STAT1_SPEED_1G: + DbgMessage(pdev, INFORM, "serdes autoneg to 1gb.\n"); + speed = LM_MEDIUM_SPEED_1000MBPS; + break; + + case MII_1000X_STAT1_SPEED_100: + DbgMessage(pdev, INFORM, "serdes autoneg to 100mb.\n"); + speed = LM_MEDIUM_SPEED_100MBPS; + break; + + case MII_1000X_STAT1_SPEED_10: + default: + DbgMessage(pdev, INFORM, "serdes autoneg to 10mb.\n"); + speed = LM_MEDIUM_SPEED_10MBPS; + break; + } + + /* Get the duplex mode. */ + duplex = LM_MEDIUM_FULL_DUPLEX; + if(val & MII_1000X_STAT1_DUPLEX) + { + DbgMessage(pdev, INFORM, "serdes autoneg to full duplex.\n"); + } + else + { + (void) lm_mread( + pdev, + pdev->params.phy_addr, + MII_REG(serdes_reg_t, mii_status), + &val); + if(val & MII_STAT_ANEG_CMPL) + { + duplex = LM_MEDIUM_HALF_DUPLEX; + DbgMessage(pdev, INFORM, "serdes autoneg to half duplex.\n"); + } + else + { + DbgMessage(pdev, INFORM, "serdes autoneg to full duplex.\n"); + } + } + + /* Set up pre-emphasis for a backplane application. */ + if(pdev->hw_info.nvm_hw_config & SHARED_HW_CFG_BACKPLANE_APP) + { + restarted_autoneg = set_5708_serdes_pre_emphasis( + pdev, + pdev->params.serdes_pre_emphasis); + + if(restarted_autoneg) + { + speed = LM_MEDIUM_SPEED_UNKNOWN; + duplex = LM_MEDIUM_FULL_DUPLEX; + link = LM_STATUS_LINK_DOWN; + } + } + } + else + { + /* Determine the forced link settings. */ + if(val & MII_CTRL_MANUAL_FORCE_2500) + { + DbgMessage(pdev, INFORM, "serdes forced to 2.5gb.\n"); + speed = LM_MEDIUM_SPEED_2500MBPS; + } + else if(val & MII_CTRL_MANUAL_SPD1) + { + DbgMessage(pdev, INFORM, "serdes forced to 1gb.\n"); + speed = LM_MEDIUM_SPEED_1000MBPS; + } + else if(val & MII_CTRL_MANUAL_SPD0) + { + DbgMessage(pdev, INFORM, "serdes forced to 100mb.\n"); + speed = LM_MEDIUM_SPEED_100MBPS; + } + else + { + DbgMessage(pdev, INFORM, "serdes forced to 10mb.\n"); + speed = LM_MEDIUM_SPEED_10MBPS; + } + + if(val & MII_CTRL_DUPLEX_MODE) + { + DbgMessage(pdev, INFORM, "serdes forced to full duplex.\n"); + duplex = LM_MEDIUM_FULL_DUPLEX; + } + else + { + DbgMessage(pdev, INFORM, "serdes forced to half duplex.\n"); + duplex = LM_MEDIUM_HALF_DUPLEX; + } + } + + *medium = LM_MEDIUM_TYPE_FIBER | speed | duplex; + + return link; +} /* get_5708_serdes_link */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +get_5709_serdes_link( + lm_device_t *pdev, + lm_medium_t *medium) +{ + lm_medium_t duplex = LM_MEDIUM_FULL_DUPLEX; + lm_medium_t speed = LM_MEDIUM_SPEED_UNKNOWN; + lm_status_t link = LM_STATUS_LINK_UNKNOWN; + u32_t mac_status; + u32_t val; + + *medium = LM_MEDIUM_TYPE_FIBER | + LM_MEDIUM_SPEED_UNKNOWN | + LM_MEDIUM_FULL_DUPLEX; + + pdev->vars.cable_is_attached = FALSE; + + /* select gp_status block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0x8120); + + /* get status. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x1b, &val); + (void) lm_mread(pdev, pdev->params.phy_addr, 0x1b, &val); /* is this needed? */ + + /* sometimes when we get a link event, mii register 0x1b does not + * reflect the current link status but mac_status does reflect the + * correct link status. */ + REG_RD(pdev, emac.emac_status, &mac_status); + + /* link down. */ + if((val & 0x4) == 0 && (mac_status & EMAC_STATUS_LINK) == 0) + { + return LM_STATUS_LINK_DOWN; + } + + link = LM_STATUS_LINK_ACTIVE; + pdev->vars.cable_is_attached = TRUE; + + /* select combo ieee0 block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0xffe0); + + /* phy_ctrl register. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x10, &val); + + if(val & 0x1000) + { + /* select gp_status block. */ + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1f, 0x8120); + + /* get status. */ + (void) lm_mread(pdev, pdev->params.phy_addr, 0x1b, &val); + + /* duplex mode. */ + if(val & 0x8) + { + duplex = LM_MEDIUM_FULL_DUPLEX; + } + else + { + duplex = LM_MEDIUM_HALF_DUPLEX; + } + + /* Determine autoneg speed. */ + val = (val >> 8) & 0x3f; + if(val == 0) + { + speed = LM_MEDIUM_SPEED_10MBPS; + } + else if(val == 1) + { + speed = LM_MEDIUM_SPEED_100MBPS; + } + else if(val == 2 || val == 13) + { + speed = LM_MEDIUM_SPEED_1000MBPS; + } + else if(val == 3) + { + speed = LM_MEDIUM_SPEED_2500MBPS; + } + else + { + DbgBreakMsg("unknown link speed status.\n"); + } + } + else + { + /* get forced duplex mode. */ + if(val & 0x100) + { + duplex = LM_MEDIUM_FULL_DUPLEX; + } + else + { + duplex = LM_MEDIUM_HALF_DUPLEX; + } + + /* get forced speed. */ + if(val & 0x20) + { + speed = LM_MEDIUM_SPEED_2500MBPS; + } + else if((val & 0x2040) == 0) + { + speed = LM_MEDIUM_SPEED_10MBPS; + } + else if((val & 0x2040) == 0x2000) + { + speed = LM_MEDIUM_SPEED_100MBPS; + } + else if((val & 0x2040) == 0x40) + { + speed = LM_MEDIUM_SPEED_1000MBPS; + } + else + { + DbgBreakMsg("unknown speed.\n"); + } + } + + *medium = LM_MEDIUM_TYPE_FIBER | speed | duplex; + + return link; +} /* get_5709_serdes_link */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +get_5706_serdes_link( + lm_device_t *pdev, + lm_medium_t *medium) +{ + lm_status_t link; + u32_t phy_status; + u32_t remote_adv; + u32_t local_adv; + u32_t phy_ctrl; + u32_t val; + + *medium = LM_MEDIUM_TYPE_FIBER; + + phy_status = mii_get_serdes_link_status(pdev); + + if(phy_status & PHY_STATUS_LINK_PASS) + { + DbgMessage(pdev, INFORM, "serdes link up.\n"); + + link = LM_STATUS_LINK_ACTIVE; + *medium |= LM_MEDIUM_SPEED_1000MBPS; + + /* Determine duplex mode. Link is present also means + * autoneg is done. */ + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_CTRL_REG, &phy_ctrl); + if(phy_ctrl & PHY_CTRL_AUTO_NEG_ENABLE) + { + (void) lm_mread( + pdev, + pdev->params.phy_addr, + PHY_AN_AD_REG, + &local_adv); + (void) lm_mread( + pdev, + pdev->params.phy_addr, + PHY_LINK_PARTNER_ABILITY_REG, + &remote_adv); + + val = local_adv & remote_adv; + if(val & PHY_AN_AD_1000X_FULL_DUPLEX) + { + DbgMessage(pdev, INFORM, "serdes autoneg to full duplex.\n"); + + *medium |= LM_MEDIUM_FULL_DUPLEX; + } + else + { + DbgMessage(pdev, INFORM, "serdes autoneg to half duplex.\n"); + + *medium |= LM_MEDIUM_HALF_DUPLEX; + } + + pdev->vars.serdes_fallback_status = SERDES_FALLBACK_NONE; + } + else + { + if(phy_ctrl & PHY_CTRL_FULL_DUPLEX_MODE) + { + DbgMessage(pdev, INFORM, "serdes forced to full duplex.\n"); + + *medium |= LM_MEDIUM_FULL_DUPLEX; + } + else + { + DbgMessage(pdev, INFORM, "serdes forced to half duplex.\n"); + + *medium |= LM_MEDIUM_HALF_DUPLEX; + } + + if(pdev->vars.serdes_fallback_select) + { + pdev->vars.serdes_fallback_status = SERDES_FALLBACK_1G; + } + } + } + else + { + DbgMessage(pdev, INFORM, "serdes link down.\n"); + + /* This routine is called only when the link is down. */ + link = serdes_fallback(pdev, pdev->vars.serdes_fallback_select); + } + + /* cq#30504 - restore the tx driver current so we can get link. */ + if(pdev->vars.bcm5706s_tx_drv_cur) + { + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x17, 0x0f03); + + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + 0x15, + pdev->vars.bcm5706s_tx_drv_cur); + + pdev->vars.bcm5706s_tx_drv_cur = 0; + } + + pdev->vars.cable_is_attached = TRUE; + + if(link == LM_STATUS_LINK_DOWN) + { + (void) lm_mwrite(pdev, pdev->params.phy_addr, 0x1c, 0x7c00); + (void) lm_mread(pdev, pdev->params.phy_addr, 0x1c, &val); + if(!(val & 0x10)) + { + pdev->vars.cable_is_attached = FALSE; + } + } + + return link; +} /* get_5706_serdes_link */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +get_remote_phy_link( + lm_device_t *pdev, + lm_medium_t *medium) +{ + u32_t remote_phy_link; + lm_medium_t duplex; + lm_medium_t speed; + lm_status_t link; + + DbgBreakIf(pdev->params.enable_remote_phy == FALSE); + + *medium = LM_MEDIUM_TYPE_FIBER | + LM_MEDIUM_SPEED_UNKNOWN | + LM_MEDIUM_FULL_DUPLEX; + + pdev->vars.cable_is_attached = FALSE; + + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, drv_fw_mb.link_status), + &remote_phy_link); + + pdev->vars.rphy_status = 0; + + if((remote_phy_link & NETLINK_GET_LINK_STATUS_SERDES_LINK) == 0) + { + pdev->vars.rphy_status |= RPHY_STATUS_ACTIVE; + } + + if((remote_phy_link & NETLINK_GET_LINK_STATUS_NO_MEDIA_DETECTED) == 0) + { + pdev->vars.rphy_status |= RPHY_STATUS_MODULE_PRESENT; + } + + if((remote_phy_link & NETLINK_GET_LINK_STATUS_LINK_UP) == 0) + { + return LM_STATUS_LINK_DOWN; + } + + link = LM_STATUS_LINK_ACTIVE; + pdev->vars.cable_is_attached = TRUE; + + switch(remote_phy_link & NETLINK_GET_LINK_STATUS_SPEED_MASK) + { + case NETLINK_GET_LINK_STATUS_10HALF: + speed = LM_MEDIUM_SPEED_10MBPS; + duplex = LM_MEDIUM_HALF_DUPLEX; + break; + + case NETLINK_GET_LINK_STATUS_10FULL: + speed = LM_MEDIUM_SPEED_10MBPS; + duplex = LM_MEDIUM_FULL_DUPLEX; + break; + + case NETLINK_GET_LINK_STATUS_100HALF: + speed = LM_MEDIUM_SPEED_100MBPS; + duplex = LM_MEDIUM_HALF_DUPLEX; + break; + + case NETLINK_GET_LINK_STATUS_100FULL: + speed = LM_MEDIUM_SPEED_100MBPS; + duplex = LM_MEDIUM_FULL_DUPLEX; + break; + + case NETLINK_GET_LINK_STATUS_1000HALF: + speed = LM_MEDIUM_SPEED_1000MBPS; + duplex = LM_MEDIUM_HALF_DUPLEX; + break; + + case NETLINK_GET_LINK_STATUS_1000FULL: + speed = LM_MEDIUM_SPEED_1000MBPS; + duplex = LM_MEDIUM_FULL_DUPLEX; + break; + + case NETLINK_GET_LINK_STATUS_2500HALF: + speed = LM_MEDIUM_SPEED_2500MBPS; + duplex = LM_MEDIUM_HALF_DUPLEX; + break; + + case NETLINK_GET_LINK_STATUS_2500FULL: + speed = LM_MEDIUM_SPEED_2500MBPS; + duplex = LM_MEDIUM_FULL_DUPLEX; + break; + + default: + speed = LM_MEDIUM_SPEED_UNKNOWN; + duplex = LM_MEDIUM_FULL_DUPLEX; + break; + } + + *medium = LM_MEDIUM_TYPE_FIBER | speed | duplex; + + return link; +} /* get_remote_phy_link */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_init_mac_link( + lm_device_t *pdev) +{ + lm_status_t lm_status; + lm_medium_t medium; + lm_status_t link; + u32_t val, phy_ctrl, phy_status; + + if(pdev->params.enable_remote_phy) + { + link = get_remote_phy_link(pdev, &medium); + init_mac_link(pdev, link, medium, pdev->params.flow_ctrl_cap); + + return LM_STATUS_SUCCESS; + } + + switch(GET_MEDIUM_TYPE(pdev->vars.medium)) + { + case LM_MEDIUM_TYPE_UTP: + link = get_copper_phy_link(pdev, &medium); + init_mac_link(pdev, link, medium, pdev->params.flow_ctrl_cap); + + lm_status = LM_STATUS_SUCCESS; + break; + + case LM_MEDIUM_TYPE_FIBER: + DbgBreakIf(CHIP_NUM(pdev) != CHIP_NUM_5706 && + CHIP_NUM(pdev) != CHIP_NUM_5708 && + CHIP_NUM(pdev) != CHIP_NUM_5709); + + if(CHIP_NUM(pdev) == CHIP_NUM_5706) + { + link = get_5706_serdes_link(pdev, &medium); + } + else if(CHIP_NUM(pdev) == CHIP_NUM_5708) + { + link = get_5708_serdes_link(pdev, &medium); + } + else + { + link = get_5709_serdes_link(pdev, &medium); + } + + init_mac_link(pdev, link, medium, pdev->params.flow_ctrl_cap); + + lm_status = LM_STATUS_SUCCESS; + break; + + case LM_MEDIUM_TYPE_PHY_LOOPBACK: + case LM_MEDIUM_TYPE_MAC_LOOPBACK: + lm_status = init_loopback_mac_link( + pdev, + pdev->params.req_medium, + pdev->params.flow_ctrl_cap); + break; + + case LM_MEDIUM_TYPE_NULL: + init_mac_link( + pdev, + LM_STATUS_LINK_ACTIVE, + LM_MEDIUM_TYPE_NULL | + LM_MEDIUM_SPEED_1000MBPS | + LM_MEDIUM_FULL_DUPLEX, + pdev->params.flow_ctrl_cap); + + lm_status = LM_STATUS_SUCCESS; + break; + + default: + lm_status = LM_STATUS_UNKNOWN_MEDIUM; + break; + } + + /* Report the currnet link status to the management firmware. */ + val = 0; + + if(pdev->vars.link_status == LM_STATUS_LINK_ACTIVE) + { + val |= NETLINK_GET_LINK_STATUS_LINK_UP; + + if(lm_get_medium(pdev) == LM_MEDIUM_TYPE_FIBER) + { + val |= NETLINK_GET_LINK_STATUS_SERDES_LINK; + } + } + + switch(GET_MEDIUM_SPEED(pdev->vars.medium)) + { + case LM_MEDIUM_SPEED_10MBPS: + if(GET_MEDIUM_DUPLEX(pdev->vars.medium) == LM_MEDIUM_FULL_DUPLEX) + { + val |= NETLINK_GET_LINK_STATUS_10FULL; + } + else + { + val |= NETLINK_GET_LINK_STATUS_10HALF; + } + break; + + case LM_MEDIUM_SPEED_100MBPS: + if(GET_MEDIUM_DUPLEX(pdev->vars.medium) == LM_MEDIUM_FULL_DUPLEX) + { + val |= NETLINK_GET_LINK_STATUS_100FULL; + } + else + { + val |= NETLINK_GET_LINK_STATUS_100HALF; + } + break; + + case LM_MEDIUM_SPEED_1000MBPS: + if(GET_MEDIUM_DUPLEX(pdev->vars.medium) == LM_MEDIUM_FULL_DUPLEX) + { + val |= NETLINK_GET_LINK_STATUS_1000FULL; + } + else + { + val |= NETLINK_GET_LINK_STATUS_1000HALF; + } + break; + + case LM_MEDIUM_SPEED_2500MBPS: + if(GET_MEDIUM_DUPLEX(pdev->vars.medium) == LM_MEDIUM_FULL_DUPLEX) + { + val |= NETLINK_GET_LINK_STATUS_2500FULL; + } + else + { + val |= NETLINK_GET_LINK_STATUS_2500HALF; + } + break; + } + + // read PHY_CTRL_REG to see if auto-negotiation is enabled/completed + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_CTRL_REG, &phy_ctrl); + + if(phy_ctrl & PHY_CTRL_AUTO_NEG_ENABLE) + { + val |= NETLINK_GET_LINK_STATUS_AN_ENABLED; + (void) lm_mread(pdev, pdev->params.phy_addr, PHY_STATUS_REG, &phy_status); + if(phy_status & PHY_STATUS_AUTO_NEG_COMPLETE) + { + val |= NETLINK_GET_LINK_STATUS_AN_COMPLETE; + // Following bits are valid for copper (i.e. SerDes flag == 0) + if ((val & NETLINK_GET_LINK_STATUS_SERDES_LINK) == 0) + { + u32_t remote_phy_ad; + (void) lm_mread( + pdev, + pdev->params.phy_addr, + PHY_1000BASET_STATUS_REG, + &remote_phy_ad); + + if(remote_phy_ad & PHY_LINK_PARTNER_1000BASET_FULL) + val |= NETLINK_GET_LINK_STATUS_PARTNER_AD_1000FULL; + if(remote_phy_ad & PHY_LINK_PARTNER_1000BASET_HALF) + val |= NETLINK_GET_LINK_STATUS_PARTNER_AD_1000HALF; + + (void) lm_mread( + pdev, + pdev->params.phy_addr, + PHY_LINK_PARTNER_ABILITY_REG, + &remote_phy_ad); + if (remote_phy_ad & PHY_LINK_PARTNER_10BASET_HALF) + val |= NETLINK_GET_LINK_STATUS_PARTNER_AD_10HALF; + if (remote_phy_ad & PHY_LINK_PARTNER_10BASET_FULL) + val |= NETLINK_GET_LINK_STATUS_PARTNER_AD_10FULL; + if (remote_phy_ad & PHY_LINK_PARTNER_100BASETX_HALF) + val |= NETLINK_GET_LINK_STATUS_PARTNER_AD_100HALF; + if (remote_phy_ad & PHY_LINK_PARTNER_100BASETX_FULL) + val |= NETLINK_GET_LINK_STATUS_PARTNER_AD_100FULL; + if (remote_phy_ad & PHY_LINK_PARTNER_PAUSE_CAPABLE) + val |= NETLINK_GET_LINK_STATUS_PARTNER_SYM_PAUSE_CAP; + if (remote_phy_ad & PHY_LINK_PARTNER_ASYM_PAUSE) + val |= NETLINK_GET_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP; + // Read PHY_AN_EXPANSION_REG to see if Link partner support auto + // negotiation + (void) lm_mread( + pdev, + pdev->params.phy_addr, + PHY_AN_EXPANSION_REG, + &remote_phy_ad); + // If Link partner does not support auto negotiation, we assume + // parallel detection was used to get link. + if ((remote_phy_ad & PHY_LINK_PARTNER_AUTONEG_ABILITY) == 0) + val |= NETLINK_GET_LINK_STATUS_PARALLEL_DET; + } + } + } + if(pdev->vars.flow_control & LM_FLOW_CONTROL_TRANSMIT_PAUSE) + { + val |= NETLINK_GET_LINK_STATUS_TX_FC_ENABLED; + } + if(pdev->vars.flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) + { + val |= NETLINK_GET_LINK_STATUS_RX_FC_ENABLED; + } + // Following bits are not supported yet + // NETLINK_GET_LINK_STATUS_NO_MEDIA_DETECTED; + // NETLINK_GET_LINK_STATUS_CABLESENSE; + // NETLINK_GET_LINK_STATUS_SW_TIMER_EVENT; + REG_WR_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, drv_fw_mb.link_status), + val); + + return lm_status; +} /* lm_init_mac_link */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_service_phy_int( + lm_device_t *pdev, + u32_t force_service_int) +{ + u32_t deasserted_attns; + u32_t asserted_attns; + u32_t link_chng; + u32_t val; + + link_chng = FALSE; + + if(pdev->params.link_chng_mode == LINK_CHNG_MODE_USE_STATUS_REG) + { + REG_RD(pdev, emac.emac_status, &val); + if(pdev->params.phy_int_mode == PHY_INT_MODE_MI_INTERRUPT) + { + if(val & EMAC_STATUS_MI_INT) + { + link_chng = TRUE; + } + } + else if(val & EMAC_STATUS_LINK_CHANGE) + { + link_chng = TRUE; + } + } + else + { + link_chng = FALSE; + + GET_ATTN_CHNG_BITS(pdev, &asserted_attns, &deasserted_attns); + + asserted_attns &= STATUS_ATTN_BITS_LINK_STATE; + deasserted_attns &= STATUS_ATTN_BITS_LINK_STATE; + + if(asserted_attns) + { + link_chng = TRUE; + + REG_WR( + pdev, + pci_config.pcicfg_status_bit_set_cmd, + asserted_attns); + } + else if(deasserted_attns) + { + link_chng = TRUE; + + REG_WR( + pdev, + pci_config.pcicfg_status_bit_clear_cmd, + deasserted_attns); + } + } + + if(link_chng || force_service_int || pdev->params.enable_remote_phy) + { + (void) lm_init_mac_link(pdev); + + mm_indicate_link(pdev, pdev->vars.link_status, pdev->vars.medium); + } +} /* lm_service_phy_int */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_medium_t +lm_get_medium( + lm_device_t *pdev) +{ + u32_t decode; + u32_t val; + + if(CHIP_REV(pdev) == CHIP_REV_IKOS) + { + return LM_MEDIUM_TYPE_NULL; + } + + if(CHIP_REV(pdev) == CHIP_REV_FPGA) + { + return LM_MEDIUM_TYPE_UTP; + } + + if(CHIP_NUM(pdev) == CHIP_NUM_5706 || CHIP_NUM(pdev) == CHIP_NUM_5708) + { + if(CHIP_BOND_ID(pdev) & CHIP_BOND_ID_SERDES_BIT) + { + return LM_MEDIUM_TYPE_FIBER; + } + + return LM_MEDIUM_TYPE_UTP; + } + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + REG_RD(pdev, misc.misc_dual_media_ctrl, &val); + + if((val & MISC_DUAL_MEDIA_CTRL_BOND_ID) == + MISC_DUAL_MEDIA_CTRL_BOND_ID_C) + { + return LM_MEDIUM_TYPE_UTP; + } + + if((val & MISC_DUAL_MEDIA_CTRL_BOND_ID) == + MISC_DUAL_MEDIA_CTRL_BOND_ID_S) + { + return LM_MEDIUM_TYPE_FIBER; + } + + /* mac to phy/serdes decode. + * swap strap mac0 mac1 + * ==== ===== ==== ==== + * 0 000 phy0 phy1 + * 0 001 phy0 ser0 + * 0 010 phy0 ser1 + * 0 110 ser0 phy0 + * 0 101 ser0 phy1 + * 0 100 ser0 ser1 + * + * 1 000 phy1 phy0 + * 1 001 phy1 ser1 + * 1 010 phy1 ser0 + * 1 110 ser1 phy1 + * 1 101 ser1 phy0 + * 1 100 ser1 ser0 */ + if(val & MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) + { + decode = (val & MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; + + if(val & MISC_DUAL_MEDIA_CTRL_PORT_SWAP) + { + decode |= 0x8; + } + } + else + { + decode = (val & MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; + + if(val & MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN) + { + decode |= 0x8; + } + } + + decode |= pdev->hw_info.mac_id << 4; + + /* mac:4, swap:3, strap:2-0. */ + switch(decode) + { + case 0x00: /* 00000 - mac0, phy0 */ + case 0x01: /* 00001 - mac0, phy0 */ + case 0x02: /* 00010 - mac0, phy0 */ + case 0x08: /* 01000 - mac0, phy1 */ + case 0x09: /* 01001 - mac0, phy1 */ + case 0x0a: /* 01010 - mac0, phy1 */ + case 0x10: /* 10000 - mac1, phy1 */ + case 0x15: /* 10101 - mac1, phy1 */ + case 0x16: /* 10110 - mac1, phy0 */ + case 0x18: /* 11000 - mac1, phy0 */ + case 0x1d: /* 11101 - mac1, phy0 */ + case 0x1e: /* 11110 - mac1, phy1 */ + return LM_MEDIUM_TYPE_UTP; + + case 0x04: /* 00100 - mac0, ser0 */ + case 0x05: /* 00101 - mac0, ser0 */ + case 0x06: /* 00110 - mac0, ser0 */ + case 0x0c: /* 01100 - mac0, ser1 */ + case 0x0d: /* 01101 - mac0, ser1 */ + case 0x0e: /* 01110 - mac0, ser1 */ + case 0x11: /* 10001 - mac1, ser0 */ + case 0x12: /* 10010 - mac1, ser1 */ + case 0x14: /* 10100 - mac1, ser1 */ + case 0x19: /* 11001 - mac1, ser1 */ + case 0x1a: /* 11010 - mac1, ser0 */ + case 0x1c: /* 11100 - mac1, ser0 */ + return LM_MEDIUM_TYPE_FIBER; + } + } + + return LM_MEDIUM_TYPE_NULL; +} /* lm_get_medium */ diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c new file mode 100644 index 0000000000..83b39d4a12 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c @@ -0,0 +1,2567 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "lm5706.h" + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +u8_t +fw_reset_sync( + lm_device_t *pdev, + lm_reason_t reason, + u32_t msg_data, + u32_t fw_ack_timeout_us) /* timeout in microseconds. */ +{ + u32_t cnt; + u32_t val; + + /* Skip handshake for 5709 for emulation */ + if (CHIP_ID(pdev) == CHIP_ID_5709_IKOS) + { + return TRUE; + } + + /* If we timed out, inform the firmware that this is the case. */ + if(pdev->vars.fw_timed_out) + { + return TRUE; + } + + pdev->vars.fw_wr_seq++; + msg_data |= (pdev->vars.fw_wr_seq & DRV_MSG_SEQ); + + switch(reason) + { + case LM_REASON_DRIVER_RESET: + msg_data |= DRV_MSG_CODE_RESET; + break; + + case LM_REASON_DRIVER_UNLOAD: + msg_data |= DRV_MSG_CODE_UNLOAD; + break; + + case LM_REASON_DRIVER_UNLOAD_POWER_DOWN: + msg_data |= DRV_MSG_CODE_UNLOAD_LNK_DN; + break; + + case LM_REASON_DRIVER_SHUTDOWN: + msg_data |= DRV_MSG_CODE_SHUTDOWN; + break; + + case LM_REASON_WOL_SUSPEND: + msg_data |= DRV_MSG_CODE_SUSPEND_WOL; + break; + + case LM_REASON_NO_WOL_SUSPEND: + msg_data |= DRV_MSG_CODE_SUSPEND_NO_WOL; + break; + + case LM_REASON_DIAG: + msg_data |= DRV_MSG_CODE_DIAG; + break; + + default: + DbgBreakMsg("invalid reason code.\n"); + break; + } + + REG_WR_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, drv_fw_mb.drv_mb), + msg_data); + + val = 0; + + /* wait for an acknowledgement. */ + for(cnt = 0; cnt < fw_ack_timeout_us/5; cnt++) + { + mm_wait(pdev, 5); + + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, drv_fw_mb.fw_mb), + &val); + if((val & FW_MSG_ACK) == (msg_data & DRV_MSG_SEQ)) + { + break; + } + } + + if((val & FW_MSG_ACK) != (msg_data & DRV_MSG_SEQ)) + { + if((msg_data & DRV_MSG_DATA) != DRV_MSG_DATA_WAIT0) + { + msg_data &= ~DRV_MSG_CODE; + msg_data |= DRV_MSG_CODE_FW_TIMEOUT; + + REG_WR_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, drv_fw_mb.drv_mb), + msg_data); + + pdev->vars.fw_timed_out = TRUE; + pdev->fw_timed_out_cnt++; + + DbgMessage(pdev, WARN, "firmware timed out.\n"); + } + + return TRUE; + } + + return FALSE; +} /* fw_reset_sync */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_context_5706_a0_wa( + lm_device_t *pdev) +{ + u8_t vcid_to_pcid[96]; + u32_t vcid_addr; + u32_t pcid_addr; + u32_t offset; + u32_t vcid; + + /* In A0 silicon, certain context memory region is not accessible + * due to address decoding problem. The bad context memory is identify + * by its pcid having Bit 3 set. This table provides a mapping between + * the virtual context id to the usable physical context id. */ + vcid_to_pcid[0x00] = 0x00; vcid_to_pcid[0x01] = 0x01; + vcid_to_pcid[0x02] = 0x02; vcid_to_pcid[0x03] = 0x03; + vcid_to_pcid[0x04] = 0x04; vcid_to_pcid[0x05] = 0x05; + vcid_to_pcid[0x06] = 0x06; vcid_to_pcid[0x07] = 0x07; + vcid_to_pcid[0x08] = 0x60; vcid_to_pcid[0x09] = 0x61; /* bad entries. */ + vcid_to_pcid[0x0a] = 0x62; vcid_to_pcid[0x0b] = 0x63; /* bad entries. */ + vcid_to_pcid[0x0c] = 0x64; vcid_to_pcid[0x0d] = 0x65; /* bad entries. */ + vcid_to_pcid[0x0e] = 0x66; vcid_to_pcid[0x0f] = 0x67; /* bad entries. */ + vcid_to_pcid[0x10] = 0x10; vcid_to_pcid[0x11] = 0x11; + vcid_to_pcid[0x12] = 0x12; vcid_to_pcid[0x13] = 0x13; + vcid_to_pcid[0x14] = 0x14; vcid_to_pcid[0x15] = 0x15; + vcid_to_pcid[0x16] = 0x16; vcid_to_pcid[0x17] = 0x17; + vcid_to_pcid[0x18] = 0x70; vcid_to_pcid[0x19] = 0x71; /* bad entries. */ + vcid_to_pcid[0x1a] = 0x72; vcid_to_pcid[0x1b] = 0x73; /* bad entries. */ + vcid_to_pcid[0x1c] = 0x74; vcid_to_pcid[0x1d] = 0x75; /* bad entries. */ + vcid_to_pcid[0x1e] = 0x76; vcid_to_pcid[0x1f] = 0x77; /* bad entries. */ + vcid_to_pcid[0x20] = 0x20; vcid_to_pcid[0x21] = 0x21; + vcid_to_pcid[0x22] = 0x22; vcid_to_pcid[0x23] = 0x23; + vcid_to_pcid[0x24] = 0x24; vcid_to_pcid[0x25] = 0x25; + vcid_to_pcid[0x26] = 0x26; vcid_to_pcid[0x27] = 0x27; + vcid_to_pcid[0x28] = 0x80; vcid_to_pcid[0x29] = 0x81; /* bad entries. */ + vcid_to_pcid[0x2a] = 0x82; vcid_to_pcid[0x2b] = 0x83; /* bad entries. */ + vcid_to_pcid[0x2c] = 0x84; vcid_to_pcid[0x2d] = 0x85; /* bad entries. */ + vcid_to_pcid[0x2e] = 0x86; vcid_to_pcid[0x2f] = 0x87; /* bad entries. */ + vcid_to_pcid[0x30] = 0x30; vcid_to_pcid[0x31] = 0x31; + vcid_to_pcid[0x32] = 0x32; vcid_to_pcid[0x33] = 0x33; + vcid_to_pcid[0x34] = 0x34; vcid_to_pcid[0x35] = 0x35; + vcid_to_pcid[0x36] = 0x36; vcid_to_pcid[0x37] = 0x37; + vcid_to_pcid[0x38] = 0x90; vcid_to_pcid[0x39] = 0x91; /* bad entries. */ + vcid_to_pcid[0x3a] = 0x92; vcid_to_pcid[0x3b] = 0x93; /* bad entries. */ + vcid_to_pcid[0x3c] = 0x94; vcid_to_pcid[0x3d] = 0x95; /* bad entries. */ + vcid_to_pcid[0x3e] = 0x96; vcid_to_pcid[0x3f] = 0x97; /* bad entries. */ + vcid_to_pcid[0x40] = 0x40; vcid_to_pcid[0x41] = 0x41; + vcid_to_pcid[0x42] = 0x42; vcid_to_pcid[0x43] = 0x43; + vcid_to_pcid[0x44] = 0x44; vcid_to_pcid[0x45] = 0x45; + vcid_to_pcid[0x46] = 0x46; vcid_to_pcid[0x47] = 0x47; + vcid_to_pcid[0x48] = 0xa0; vcid_to_pcid[0x49] = 0xa1; /* bad entries. */ + vcid_to_pcid[0x4a] = 0xa2; vcid_to_pcid[0x4b] = 0xa3; /* bad entries. */ + vcid_to_pcid[0x4c] = 0xa4; vcid_to_pcid[0x4d] = 0xa5; /* bad entries. */ + vcid_to_pcid[0x4e] = 0xa6; vcid_to_pcid[0x4f] = 0xa7; /* bad entries. */ + vcid_to_pcid[0x50] = 0x50; vcid_to_pcid[0x51] = 0x51; + vcid_to_pcid[0x52] = 0x52; vcid_to_pcid[0x53] = 0x53; + vcid_to_pcid[0x54] = 0x54; vcid_to_pcid[0x55] = 0x55; + vcid_to_pcid[0x56] = 0x56; vcid_to_pcid[0x57] = 0x57; + vcid_to_pcid[0x58] = 0xb0; vcid_to_pcid[0x59] = 0xb1; /* bad entries. */ + vcid_to_pcid[0x5a] = 0xb2; vcid_to_pcid[0x5b] = 0xb3; /* bad entries. */ + vcid_to_pcid[0x5c] = 0xb4; vcid_to_pcid[0x5d] = 0xb5; /* bad entries. */ + vcid_to_pcid[0x5e] = 0xb6; vcid_to_pcid[0x5f] = 0xb7; /* bad entries. */ + + vcid = sizeof(vcid_to_pcid); + while(vcid) + { + vcid--; + + vcid_addr = GET_PCID_ADDR(vcid); + pcid_addr = GET_PCID_ADDR(vcid_to_pcid[vcid]); + + /* There maybe some residuals in the context that may cause + * receive problem later. The problem intermittently occurs + * when we are resetting the chip while there are incoming + * traffic and some other firmware is running. To prevent this + * problem from occuring we need to zero out context first + * before initializing the virtual to physical mapping. We + * arbitrarily use a virtual context address 0x00 to map to a + * physical context one at a time then zero them out. + * + * First map the physical context to virtual context 0 then + * zero out the context. */ + REG_WR(pdev, context.ctx_virt_addr, 0x00); + REG_WR(pdev, context.ctx_page_tbl, pcid_addr); + + /* Zero out the context. */ + for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) + { + CTX_WR(pdev, 0x00, offset, 0); + } + + /* Now initalize the correct mapping in which the virtual + * context to the correspondinding physical context. */ + REG_WR(pdev, context.ctx_virt_addr, vcid_addr); + REG_WR(pdev, context.ctx_page_tbl, pcid_addr); + } +} /* init_context_5706_a0_wa */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_context_5706( + lm_device_t *pdev) +{ + u32_t vcid_addr; + u32_t offset; + + vcid_addr = GET_CID_ADDR(96); /* This corresponds to 48 context. */ + + while(vcid_addr) + { + vcid_addr -= PHY_CTX_SIZE; + + /* There maybe some residuals in the context that may cause + * receive problem later. The problem intermittently occurs + * when we are resetting the chip while there are incoming + * traffic and some other firmware is running. To prevent this + * problem from occuring we need to zero out context first + * before initializing the virtual to physical mapping. We + * arbitrarily use a virtual context address 0x00 to map to a + * physical context one at a time then zero them out. + * + * First map the physical context to virtual context 0 then + * zero out the context. */ + REG_WR(pdev, context.ctx_virt_addr, 0x00); + REG_WR(pdev, context.ctx_page_tbl, vcid_addr); + + /* Zero out the context. */ + for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) + { + CTX_WR(pdev, 0x00, offset, 0); + } + + /* Now initalize the correct mapping in which the virtual + * context to the correspondinding physical context. */ + REG_WR(pdev, context.ctx_virt_addr, vcid_addr); + REG_WR(pdev, context.ctx_page_tbl, vcid_addr); + } +} /* init_context_5706 */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_context_5709( + lm_device_t *pdev) +{ + lm_address_t mem_phy; + u8_t *mem_virt; + u32_t mem_size; + u32_t page_idx; + u32_t idx; + u32_t cnt; + u32_t val; + + DbgBreakIf(CHIP_NUM(pdev) != CHIP_NUM_5709); + + val = 0x3001; + val |= (LM_PAGE_BITS - 8) << 16; + REG_WR(pdev, context.ctx_command, val); + + page_idx = 0; + + for(idx = 0; idx < NUM_CTX_MBLKS; idx++) + { + mem_virt = pdev->vars.ctx_mem[idx].start; + mem_phy = pdev->vars.ctx_mem[idx].start_phy; + mem_size = pdev->vars.ctx_mem[idx].size; + + DbgBreakIf(mem_phy.as_u32.low & LM_PAGE_MASK); + DbgBreakIf(mem_size & LM_PAGE_MASK); + + while(mem_size) + { + for(cnt = 0; cnt < LM_PAGE_SIZE; cnt += 4) + { + ((u32_t *) mem_virt)[cnt/4] = 0; + } + + REG_WR( + pdev, + context.ctx_host_page_tbl_data0, + mem_phy.as_u32.low | CTX_HOST_PAGE_TBL_DATA0_VALID); + REG_WR( + pdev, + context.ctx_host_page_tbl_data1, + mem_phy.as_u32.high); + REG_WR( + pdev, + context.ctx_host_page_tbl_ctrl, + page_idx | CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); + + for(cnt = 0; cnt < 100; cnt++) + { + REG_RD(pdev, context.ctx_host_page_tbl_ctrl, &val); + + if(!(val & CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ)) + { + break; + } + + mm_wait(pdev, 5); + } + + DbgBreakIf(val & CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); + + mem_virt += LM_PAGE_SIZE; + LM_INC64(&mem_phy, LM_PAGE_SIZE); + mem_size -= LM_PAGE_SIZE; + + page_idx++; + } + } +} /* init_context_5709 */ + + + +/******************************************************************************* + * Description: + * This workaround must be applied right after a CORE clock reset + * and before enable other blocks which may try to allocate mbufs. + * + * Return: + ******************************************************************************/ +STATIC void +alloc_bad_rbuf_5706_a0_wa( + lm_device_t *pdev) +{ + u16_t good_mbuf[512]; + u32_t good_mbuf_cnt; + u32_t val; + + REG_WR( + pdev, + misc.misc_enable_set_bits, + MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE); + + good_mbuf_cnt = 0; + + /* Allocate a bunch of mbufs and save the good ones in an array. */ + REG_RD_IND(pdev, OFFSETOF(reg_space_t, rbuf.rbuf_status1), &val); + while(val & RBUF_STATUS1_FREE_COUNT) + { + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, rbuf.rbuf_command), + RBUF_COMMAND_ALLOC_REQ_TE); + + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, rbuf.rbuf_fw_buf_alloc), + &val); + val &= RBUF_FW_BUF_ALLOC_VALUE; + + /* The addresses with Bit 9 set are bad memory blocks. */ + if(!(val & (1 << 9))) + { + DbgBreakIf(good_mbuf_cnt >= sizeof(good_mbuf)/sizeof(u16_t)); + + good_mbuf[good_mbuf_cnt] = (u16_t) val; + good_mbuf_cnt++; + } + + REG_RD_IND(pdev, OFFSETOF(reg_space_t, rbuf.rbuf_status1), &val); + } + + /* Free the good ones back to the mbuf pool thus discardining + * all the bad ones. */ + while(good_mbuf_cnt) + { + good_mbuf_cnt--; + + val = good_mbuf[good_mbuf_cnt]; + val = (val << 9) | val | 1; + + REG_WR_IND(pdev, OFFSETOF(reg_space_t, rbuf.rbuf_fw_buf_free), val); + } +} /* alloc_bad_rbuf_5706_a0_wa */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_chip_reset( + lm_device_t *pdev, + lm_reason_t reason) +{ + u32_t val; + u32_t idx; + + DbgMessage(pdev, VERBOSE, "+++ lm_chip_reset\n"); + pdev->chip_reset_cnt++; + + /* acquiesce the bus before a reset. */ + if(CHIP_NUM(pdev) == CHIP_NUM_5706 || CHIP_NUM(pdev) == CHIP_NUM_5708) + { + REG_WR( + pdev, + misc.misc_enable_clr_bits, + MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | + MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | + MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE); + mm_wait(pdev, 5); + } + else + { + if(CHIP_ID(pdev) == CHIP_ID_5709_A0) + { + /* Disable bus_master. */ + REG_RD_OFFSET( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_command), + &val); + val &= ~PCICFG_COMMAND_BUS_MASTER; + REG_WR_OFFSET( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_command), + val); + } + else + { + /* Disable DMA activities. */ + REG_RD(pdev, misc.misc_new_core_ctl, &val); + val &= ~(1 << 16); + REG_WR(pdev, misc.misc_new_core_ctl, val); + } + + /* wait until there is no pending transaction. */ + for(idx = 0; idx < 1000; idx++) + { + REG_RD_OFFSET( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_device_control), + &val); + if((val & (PCICFG_DEVICE_STATUS_NO_PEND << 16)) == 0) + { + break; + } + + mm_wait(pdev, 5); + } + } + + /* Enable or disable remote phy. */ + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, drv_fw_cap_mb.fw_cap_mb), + &val); + + if((val & CAPABILITY_SIGNATURE_MASK) == FW_CAP_SIGNATURE) + { + val = DRV_ACK_CAP_SIGNATURE; + + if(pdev->params.enable_remote_phy) + { + if (LM_REASON_DIAG != reason) + { + val |= FW_CAP_REMOTE_PHY_CAPABLE; + } + else + { + val &= ~FW_CAP_REMOTE_PHY_CAPABLE; + } + } + + REG_WR_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, drv_fw_cap_mb.drv_ack_cap_mb), + val); + } + + /* Wait for the firmware to tell us it is ok to issue a reason. */ + (void) fw_reset_sync(pdev, reason, DRV_MSG_DATA_WAIT0, FW_ACK_TIME_OUT_MS*1000); + + /* Deposit a driver reset signature so the firmware knows + * that this is a soft reset. */ + REG_WR_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, drv_fw_mb.drv_reset_signature), + DRV_RESET_SIGNATURE); + + /* Force the driver to wait for the acknowledgement from + * the firmware. */ + pdev->vars.fw_timed_out = FALSE; + + /* Do a dummy read to force the chip to complete all current + * transaction before we issue a reset. This is a workaround + * for A0. If there is any pending transactions when a reset + * occur, the chip will lock up. There must be one last read + * before a core clock reset. */ + REG_RD(pdev, misc.misc_id, &val); + + /* Chip reset. */ + if(CHIP_NUM(pdev) == CHIP_NUM_5706 || CHIP_NUM(pdev) == CHIP_NUM_5708) + { + REG_WR( + pdev, + pci_config.pcicfg_misc_config, + PCICFG_MISC_CONFIG_CORE_RST_REQ | + PCICFG_MISC_CONFIG_REG_WINDOW_ENA | + PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); + + /* Wait for the firmware to configure for PLL bypass. This is a + * 5706 A0 workaround. Without the wait the system will lock up + * on the first register access in PCI-X mode and may intermittently + * do the same in PCI mode. */ + if(CHIP_ID(pdev) == CHIP_ID_5706_A0 || CHIP_ID(pdev) == CHIP_ID_5706_A1) + { + /* 15ms is how long for the first stage of bootcode to load + * and set up the PLL bypass. */ + for(idx = 0; idx < 1000; idx++) + { + mm_wait(pdev, 15); + } + } + + /* Reset takes at approximate 3ms on the FPGA which is 100 times + * slower than the real chip. IKOS is 10 times slower than the FPGA. */ + for(idx = 0; idx < 5000; idx++) + { + REG_RD(pdev, pci_config.pcicfg_misc_config, &val); + + mm_wait(pdev, 10); + + if((val & ( + PCICFG_MISC_CONFIG_CORE_RST_REQ | + PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) + { + break; + } + } + + DbgBreakIf(val & ( + PCICFG_MISC_CONFIG_CORE_RST_REQ | + PCICFG_MISC_CONFIG_CORE_RST_BSY)); + } + else + { + REG_WR(pdev, misc.misc_command, MISC_COMMAND_SW_RESET); + + /* Flush the previous write and wait at least 500 nsec */ + REG_RD( pdev, misc.misc_command, &val); + mm_wait(pdev, 1); + + /* Reset takes at approximate 3ms on the FPGA which is 100 times + * slower than the real chip. IKOS is 10 times slower than the FPGA. */ + for(idx = 0; idx < 5000; idx++) + { + REG_RD(pdev, misc.misc_command, &val); + + mm_wait(pdev, 10); + + if((val & MISC_COMMAND_SW_RESET) == 0) + { + break; + } + } + + DbgBreakIf(val & MISC_COMMAND_SW_RESET); + + REG_WR( + pdev, + pci_config.pcicfg_misc_config, + PCICFG_MISC_CONFIG_REG_WINDOW_ENA | + PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); + + if(CHIP_ID(pdev) == CHIP_ID_5709_A0) + { + REG_RD_OFFSET( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_command), + &val); + val |= PCICFG_COMMAND_BUS_MASTER; + REG_WR_OFFSET( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_command), + val); + + /* cq#28345. */ + REG_RD(pdev, tsch.tsch_ctx_access_cfg, &val); + val &= ~TSCH_CTX_ACCESS_CFG_L5_TCMD_PREFETCH_SIZE; + REG_WR(pdev, tsch.tsch_ctx_access_cfg, val); + } + else + { + if((reason == LM_REASON_DRIVER_RESET) || (reason == LM_REASON_DIAG)) + { + /* Enable DMA activities. */ + REG_RD(pdev, misc.misc_new_core_ctl, &val); + val |= (1 << 16); + REG_WR(pdev, misc.misc_new_core_ctl, val); + } + } + + if(CHIP_ID(pdev) == CHIP_ID_5709_A0 || + CHIP_ID(pdev) == CHIP_ID_5709_B0 || + CHIP_ID(pdev) == CHIP_ID_5709_B1 || + CHIP_ID(pdev) == CHIP_ID_5709_B2 || + CHIP_ID(pdev) == CHIP_ID_5709_A1) + { + REG_RD(pdev, mq.mq_config, &val); + REG_WR(pdev, mq.mq_config, val | MQ_CONFIG_HALT_DIS); + } + } + + DbgMessage1(pdev, INFORM, "Reset done, idx = %d\n", idx); + + /* Wait for the firmware to finish its initialization. */ + (void) fw_reset_sync(pdev, reason, DRV_MSG_DATA_WAIT1, FW_ACK_TIME_OUT_MS*1000); + + /* Make sure byte swapping is properly configured. */ + REG_RD(pdev, pci.pci_swap_diag0, &val); + + DbgBreakIf(val != 0x01020304); + + /* The emac block will lock up if the power_down_mode is enabled. + * + * This is now done by the bootcode. + * + * lm_mread(pdev, PHY_CTRL_REG, &val); + * if(val & PHY_CTRL_LOWER_POWER_MODE) + * { + * val &= ~PHY_CTRL_LOWER_POWER_MODE; + * lm_mwrite(pdev, PHY_CTRL_REG, val); + * } */ + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + /* make sure the MSI-X setting is preserved */ + REG_WR(pdev, + pci.pci_grc_window_addr, + (pdev->hw_info.shmem_base & ~0x7fff) | + PCI_GRC_WINDOW_ADDR_SEP_WIN); + + REG_WR(pdev, + pci.pci_grc_window1_addr, + (pdev->hw_info.shmem_base & ~0x7fff) + 0x6000 /*0x16e000 */); + + REG_WR(pdev, + pci.pci_grc_window2_addr, + MSIX_TABLE_ADDR /*MSIX vector addr */); + REG_WR(pdev, + pci.pci_grc_window3_addr, + MSIX_PBA_ADDR /*MSIX PBA addr */); + REG_WR(pdev, pci.pci_msix_tbl_off_bir, PCI_GRC_WINDOW2_BASE); + REG_WR(pdev, pci.pci_msix_pba_off_bit, PCI_GRC_WINDOW3_BASE); + if(pdev->params.ena_large_grc_timeout) + { + /* this workaround cause IBM minnow to reboot randomly */ + /* set large GRC timeout in MSIX mode */ + REG_RD(pdev, misc.misc_eco_hw_ctl, &val); + val |= MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN; + REG_WR(pdev, misc.misc_eco_hw_ctl, val); + } + else + { + REG_RD(pdev, misc.misc_eco_hw_ctl, &val); + val &= ~MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN; + REG_WR(pdev, misc.misc_eco_hw_ctl, val); + } + } + else + { + /* Default 32k window. */ + REG_WR(pdev, pci.pci_grc_window_addr, pdev->hw_info.shmem_base & ~0x7fff); + } + + /* 5706A0 workaround. */ + if(CHIP_ID(pdev) == CHIP_ID_5706_A0) + { + /* Adjust the voltage regular to two steps lower. The default + * of this register is 0x0000000e. */ + REG_WR(pdev, misc.misc_vreg_control, 0x000000fa); + + /* Remove bad rbuf memory from the free pool. */ + alloc_bad_rbuf_5706_a0_wa(pdev); + } + + REG_WR( + pdev, + timer.timer_sw_tmr_reload_value1, + pdev->params.tmr_reload_value1); + + (void) lm_set_mac_addr(pdev, 0x0, pdev->params.mac_addr); + + val = pdev->params.mac_addr[0] + + (pdev->params.mac_addr[1] << 8) + + (pdev->params.mac_addr[2] << 16) + + pdev->params.mac_addr[3] + + (pdev->params.mac_addr[4] << 8) + + (pdev->params.mac_addr[5] << 16); + REG_WR(pdev, emac.emac_backoff_seed, val); + + (void) lm_set_rx_mask( + pdev, + RX_FILTER_USER_IDX0, + pdev->rx_info.mask[RX_FILTER_USER_IDX0]); + + /* The firmware relies on the driver to issue a periodic pulse to + * determine when to go enter an OS absent mode. During debugging + * we may not want the firmware to go into this mode. */ + if(pdev->params.test_mode & TEST_MODE_DRIVER_PULSE_ALWAYS_ALIVE) + { + pdev->vars.drv_pulse_wr_seq++; + + val = pdev->vars.drv_pulse_wr_seq | DRV_PULSE_ALWAYS_ALIVE; + + REG_WR_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, drv_fw_mb.drv_pulse_mb), + val); + } +} /* lm_chip_reset */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_setup_bd_chain_ring( + u8_t *mem_virt, + lm_address_t mem_phy, + u32_t page_cnt) +{ + lm_address_t start_mem_phy; + u8_t *start_mem_virt; + tx_bd_next_t *next_ptr; + u32_t idx; + + DbgBreakIf( + ((u32_t) PTR_SUB(mem_virt, 0) & LM_PAGE_MASK) != + (mem_phy.as_u32.low & LM_PAGE_MASK)); + + start_mem_phy = mem_phy; + start_mem_virt = mem_virt; + + for(idx = 0; idx < page_cnt-1; idx++) + { + /* Increment mem_phy to the next page. */ + LM_INC64(&mem_phy, LM_PAGE_SIZE); + + next_ptr = &((tx_bd_next_t *) mem_virt)[MAX_BD_PER_PAGE]; + + /* Initialize the physical address of the next bd chain. */ + next_ptr->tx_bd_next_paddr_hi = mem_phy.as_u32.high; + next_ptr->tx_bd_next_paddr_lo = mem_phy.as_u32.low; + + /* Initialize the virtual address of the next bd chain. */ + *((u8_t **) next_ptr->tx_bd_next_reserved) = mem_virt + LM_PAGE_SIZE; + + /* Move to the next bd chain. */ + mem_virt += LM_PAGE_SIZE; + } + + next_ptr = &((tx_bd_next_t *) mem_virt)[MAX_BD_PER_PAGE]; + + next_ptr->tx_bd_next_paddr_hi = start_mem_phy.as_u32.high; + next_ptr->tx_bd_next_paddr_lo = start_mem_phy.as_u32.low; + *((u8_t **) next_ptr->tx_bd_next_reserved) = start_mem_virt; +} /* lm_setup_bd_chain_ring */ + + + +#ifndef EXCLUDE_KQE_SUPPORT +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +setup_page_table( + void *page_table, + u32_t page_cnt, + lm_address_t page_base_phy) +{ + u32_t *page_entry; + + page_entry = (u32_t *) page_table; + while(page_cnt) + { + /* Each entry needs to be in big endian format. */ + *page_entry = page_base_phy.as_u32.high; + page_entry++; + *page_entry = page_base_phy.as_u32.low; + page_entry++; + + LM_INC64(&page_base_phy, LM_PAGE_SIZE); + + page_cnt--; + } +} /* setup_page_table */ +#endif + + +#if INCLUDE_OFLD_SUPPORT +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +l4_reset_setup( + lm_device_t *pdev) +{ + u32_t val; + + lm_setup_bd_chain_ring( + (u8_t *) pdev->ofld.gen_chain.bd_chain_virt, + pdev->ofld.gen_chain.bd_chain_phy, + pdev->params.gen_bd_page_cnt); + + pdev->ofld.gen_chain.prod_idx = 0; + pdev->ofld.gen_chain.prod_bseq = 0; + pdev->ofld.gen_chain.prod_bd = pdev->ofld.gen_chain.bd_chain_virt; + + /* Don't count the last bd of a BD page. A full BD chain must + * have at least one empty entry. */ + pdev->ofld.gen_chain.bd_left = pdev->params.gen_bd_page_cnt * + MAX_BD_PER_PAGE - 1; + + DbgMessage2(pdev, INFORMrs, "gen_chain %p, bd_left %d\n", + pdev->ofld.gen_chain.bd_chain_virt, + pdev->ofld.gen_chain.bd_left); + + /* Initialize the type, size, bd_pre_read. */ + val = L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE << 24; + val |= (((sizeof(l2_bd_chain_context_t) + 0x1f) & ~0x1f) / 0x20) << 16; + val |= 0x2 << 8; + CTX_WR( + pdev, + pdev->ofld.gen_chain.cid_addr, + WORD_ALIGNED_OFFSETOF(l2_bd_chain_context_t, l2ctx_ctx_type), + val); + + val = pdev->ofld.gen_chain.bd_chain_phy.as_u32.high; + CTX_WR( + pdev, + pdev->ofld.gen_chain.cid_addr, + WORD_ALIGNED_OFFSETOF(l2_bd_chain_context_t, l2ctx_nx_bdhaddr_hi), + val); + + val = pdev->ofld.gen_chain.bd_chain_phy.as_u32.low; + CTX_WR( + pdev, + pdev->ofld.gen_chain.cid_addr, + WORD_ALIGNED_OFFSETOF(l2_bd_chain_context_t, l2ctx_nx_bdhaddr_lo), + val); + + /* Set up the hcopy chain. */ + if(pdev->params.hcopy_desc_cnt) + { + lm_setup_bd_chain_ring( + (u8_t *) pdev->ofld.hcopy_chain.bd_chain_virt, + pdev->ofld.hcopy_chain.bd_chain_phy, + pdev->params.hcopy_bd_page_cnt); + + pdev->ofld.hcopy_chain.prod_bd = + pdev->ofld.hcopy_chain.bd_chain_virt; + pdev->ofld.hcopy_chain.prod_idx = 0; + pdev->ofld.hcopy_chain.con_idx = 0; + pdev->ofld.hcopy_chain.prod_bseq = 0; + + /* Don't count the last bd of a BD page. A full BD chain must + * have at least one empty entry. */ + pdev->ofld.hcopy_chain.bd_left = pdev->params.hcopy_bd_page_cnt * + MAX_BD_PER_PAGE - 1; + + val = L4CTX_TYPE_TYPE_L2 << 24; + val |= (((sizeof(l4_context_t) + 0x1f) & ~0x1f) / 0x20) << 16; + CTX_WR( + pdev, + pdev->ofld.hcopy_chain.cid_addr, + WORD_ALIGNED_OFFSETOF(l4_context_t, l4ctx_ctx_type), + val); + + val = (CCELL_CMD_TYPE_TYPE_L2 | ((LM_PAGE_BITS-8) << 4)) << 24; + val |= 8 << 16; + CTX_WR( + pdev, + pdev->ofld.hcopy_chain.cid_addr, + WORD_ALIGNED_OFFSETOF(l4_context_t, l4ctx_cmd), + val); + + val = pdev->ofld.hcopy_chain.bd_chain_phy.as_u32.high; + CTX_WR( + pdev, + pdev->ofld.hcopy_chain.cid_addr, + WORD_ALIGNED_OFFSETOF(l4_context_t, l4ctx_cmd) + + WORD_ALIGNED_OFFSETOF(tcp_context_cmd_cell_te_t, + ccell_tbdr_bhaddr.hi), + val); + + val = pdev->ofld.hcopy_chain.bd_chain_phy.as_u32.low; + CTX_WR( + pdev, + pdev->ofld.hcopy_chain.cid_addr, + WORD_ALIGNED_OFFSETOF(l4_context_t, l4ctx_cmd) + + WORD_ALIGNED_OFFSETOF(tcp_context_cmd_cell_te_t, + ccell_tbdr_bhaddr.lo), + val); + } + + /* Setup statistics mapping. */ + REG_WR( + pdev, + hc.hc_stat_gen_sel_0, + HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0_TE | /* 0 - inseg */ + (HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1_TE << 8) | /* 1 - inerr */ + (HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2_TE << 16) | /* 2 - inrecv */ + (HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3_TE << 24)); /* 3 - inhdrerr */ + + REG_WR( + pdev, + hc.hc_stat_gen_sel_1, + HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4_TE | /* 4 - indiscard */ + (HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5_TE << 8) | /* 5 - indeliver */ + (HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0_TE << 16) | /* 6 - outseg */ + (HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1_TE << 24)); /* 7 - retrans */ + + REG_WR( + pdev, + hc.hc_stat_gen_sel_2, + HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2_TE | /* 8 - outreset */ + (HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3_TE << 8) | /* 9 - outreq */ + (HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4_TE << 16) | /* 10 - outdiscrd */ + (HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5_TE << 24)); /* 11 - outnorte */ + + /* set enable_iscsi_fast_response. */ + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(enable_fast_iscsi_response), + pdev->params.enable_fir); +} /* l4_reset_setup */ +#endif + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_l2txq( + lm_device_t *pdev) +{ + lm_tx_chain_t *txq; + u32_t bd_page_cnt; + u32_t offset; + u32_t idx; + u32_t val; + + for(idx = 0; idx < sizeof(lm_tx_stats_t)/sizeof(u32_t); idx++) + { + ((u32_t *) &pdev->tx_info.stats)[idx] = 0; + } + + for(idx = 0; idx < pdev->tx_info.num_txq; idx++) + { + txq = &pdev->tx_info.chain[idx]; + + bd_page_cnt = pdev->params.l2_tx_bd_page_cnt[txq->idx]; + + txq->prod_idx = 0; + txq->con_idx = 0; + txq->prod_bseq = 0; + txq->prod_bd = txq->bd_chain_virt; + txq->bd_left = bd_page_cnt * MAX_BD_PER_PAGE - 1; + + if(bd_page_cnt == 0) + { + continue; + } + + lm_setup_bd_chain_ring( + (u8_t *) txq->bd_chain_virt, + txq->bd_chain_phy, + bd_page_cnt); + +#ifndef L2_ONLY + val = (L4CTX_TYPE_TYPE_L2 << 24) | + (((sizeof(l4_context_t) + 0x1f) & ~0x1f) / 0x20) << 16; +#else + // This is equivalent as above, but some constants/structures are not + // defined for Solaris + val = (0x10 << 24) | + (((80 * sizeof(u32_t) + 0x1f) & ~0x1f) / 0x20) << 16; +#endif + + if (CHIP_NUM(pdev) == CHIP_NUM_5709) + { + offset = 0x80; + } + else + { + // offset = WORD_ALIGNED_OFFSETOF(l4_context_t, l4ctx_ctx_type); + offset = 0; + } + + CTX_WR(pdev, txq->cid_addr, offset, val); + + if (CHIP_NUM(pdev) == CHIP_NUM_5709) + { + offset = 0x240; + } + else + { + // offset = WORD_ALIGNED_OFFSETOF(l4_context_t, l4ctx_cmd); + offset = 34*sizeof(u32_t); + } + + val = (CCELL_CMD_TYPE_TYPE_L2 | ((LM_PAGE_BITS-8) << 4)) << 24; + val |= 8 << 16; + CTX_WR(pdev, txq->cid_addr, offset, val); + + val = txq->bd_chain_phy.as_u32.high; + CTX_WR( + pdev, + txq->cid_addr, + offset + WORD_ALIGNED_OFFSETOF( + tcp_context_cmd_cell_te_t, ccell_tbdr_bhaddr.hi), + val); + + val = txq->bd_chain_phy.as_u32.low; + CTX_WR( + pdev, + txq->cid_addr, + offset + WORD_ALIGNED_OFFSETOF( + tcp_context_cmd_cell_te_t, ccell_tbdr_bhaddr.lo), + val); + + } +} /* init_l2txq */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_l2rxq( + lm_device_t *pdev) +{ + lm_rx_chain_t *rxq; + u32_t bd_page_cnt; + u32_t idx; + u32_t val; + + for(idx = 0; idx < sizeof(lm_rx_stats_t)/sizeof(u32_t); idx++) + { + ((u32_t *) &pdev->rx_info.stats)[idx] = 0; + } + + for(idx = 0; idx < pdev->rx_info.num_rxq; idx++) + { + rxq = &pdev->rx_info.chain[idx]; + + bd_page_cnt = pdev->params.l2_rx_bd_page_cnt[rxq->idx]; + + rxq->prod_idx = 0; + rxq->con_idx = 0; + rxq->prod_bseq = 0; + rxq->prod_bd = rxq->bd_chain_virt; + rxq->bd_left = bd_page_cnt * MAX_BD_PER_PAGE - 1; + + if(bd_page_cnt == 0) + { + continue; + } + + lm_setup_bd_chain_ring( + (u8_t *) rxq->bd_chain_virt, + rxq->bd_chain_phy, + bd_page_cnt); + + val = L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE << 24; + val |= (((sizeof(l2_bd_chain_context_t) + 0x1f) & ~0x1f) / 0x20) << 16; + val |= 0x02 << 8; + CTX_WR( + pdev, + rxq->cid_addr, + WORD_ALIGNED_OFFSETOF(l2_bd_chain_context_t, l2ctx_ctx_type), + val); + + val = rxq->bd_chain_phy.as_u32.high; + CTX_WR( + pdev, + rxq->cid_addr, + WORD_ALIGNED_OFFSETOF(l2_bd_chain_context_t, l2ctx_nx_bdhaddr_hi), + val); + + val = rxq->bd_chain_phy.as_u32.low; + CTX_WR( + pdev, + rxq->cid_addr, + WORD_ALIGNED_OFFSETOF(l2_bd_chain_context_t, l2ctx_nx_bdhaddr_lo), + val); + + // In case we are coming out from hibernation, we need to restore + // previous MTU setting. Otherwise, we would initialize max packet + // length to default (i.e. initial power-up) + CTX_WR( + pdev, + rxq->cid_addr, + WORD_ALIGNED_OFFSETOF(l2_bd_chain_context_t, l2ctx_max_pkt_len), + rxq->max_pkt_len ? + rxq->max_pkt_len: + pdev->params.mtu + 4); // + 4 L2CRC + + + } +} /* init_l2rxq */ + + + +#ifndef EXCLUDE_KQE_SUPPORT +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_kq( + lm_device_t *pdev) +{ + lm_kq_info_t *kq; + u32_t page_cnt; + u32_t val; + + kq = &pdev->kq_info; + + /* initialize kwq. */ + page_cnt = pdev->params.kwq_page_cnt; + if(page_cnt) + { + kq->kwq_cid_addr = GET_CID_ADDR(KWQ_CID); + kq->kwqe_left = (LM_PAGE_SIZE/sizeof(kwqe_t)) * page_cnt - 1; + kq->kwq_last_qe = kq->kwq_virt + kq->kwqe_left; + + setup_page_table(kq->kwq_pgtbl_virt, page_cnt, kq->kwq_phy); + + kq->kwq_prod_idx = 0; + kq->kwq_con_idx = 0; + kq->kwq_prod_qe = kq->kwq_virt; + kq->kwq_con_qe = kq->kwq_virt; + kq->kwqe_left = (LM_PAGE_SIZE/sizeof(kwqe_t)) * page_cnt - 1; + + val = KRNLQ_TYPE_TYPE_KRNLQ << 24; + val |= (((sizeof(krnlq_context_t) + 0x1f) & ~0x1f) / 0x20) << 16; + val |= LM_PAGE_BITS-8; + val |= KRNLQ_FLAGS_QE_SELF_SEQ; + CTX_WR( + pdev, + kq->kwq_cid_addr, + WORD_ALIGNED_OFFSETOF(krnlq_context_t, krnlq_type), + val); + + val = (LM_PAGE_SIZE/sizeof(kwqe_t) - 1) << 16; + CTX_WR( + pdev, + kq->kwq_cid_addr, + WORD_ALIGNED_OFFSETOF(krnlq_context_t, krnlq_qe_self_seq_max), + val); + + val = (LM_PAGE_SIZE/sizeof(kwqe_t)) << 16; + val |= pdev->params.kwq_page_cnt; + CTX_WR( + pdev, + kq->kwq_cid_addr, + WORD_ALIGNED_OFFSETOF(krnlq_context_t, krnlq_pgtbl_npages), + val); + + val = kq->kwq_pgtbl_phy.as_u32.high; + CTX_WR( + pdev, + kq->kwq_cid_addr, + WORD_ALIGNED_OFFSETOF(krnlq_context_t, krnlq_pgtbl_haddr_hi), + val); + + val = kq->kwq_pgtbl_phy.as_u32.low; + CTX_WR( + pdev, + kq->kwq_cid_addr, + WORD_ALIGNED_OFFSETOF(krnlq_context_t, krnlq_pgtbl_haddr_lo), + val); + } + + /* initialize kcq. */ + page_cnt = pdev->params.kcq_page_cnt; + if(page_cnt) + { + kq->kcq_cid_addr = GET_CID_ADDR(KCQ_CID); + kq->kcq_last_qe = kq->kcq_virt + + (LM_PAGE_SIZE/sizeof(kcqe_t)) * page_cnt - 1; + + setup_page_table(kq->kcq_pgtbl_virt, page_cnt, kq->kcq_phy); + + kq->kcq_con_idx = 0; + kq->history_kcq_con_idx = 0; + kq->kcq_con_qe = kq->kcq_virt; + kq->history_kcq_con_qe = kq->kcq_virt; + + val = KRNLQ_TYPE_TYPE_KRNLQ << 24; + val |= (((sizeof(krnlq_context_t) + 0x1f) & ~0x1f) / 0x20) << 16; + val |= LM_PAGE_BITS-8; + val |= KRNLQ_FLAGS_QE_SELF_SEQ; + CTX_WR( + pdev, + kq->kcq_cid_addr, + WORD_ALIGNED_OFFSETOF(krnlq_context_t, krnlq_type), + val); + + val = (LM_PAGE_SIZE/sizeof(kwqe_t) - 1) << 16; + CTX_WR( + pdev, + kq->kcq_cid_addr, + WORD_ALIGNED_OFFSETOF(krnlq_context_t, krnlq_qe_self_seq_max), + val); + + val = (LM_PAGE_SIZE/sizeof(kcqe_t)) << 16; + val |= pdev->params.kcq_page_cnt; + CTX_WR( + pdev, + kq->kcq_cid_addr, + WORD_ALIGNED_OFFSETOF(krnlq_context_t, krnlq_pgtbl_npages), + val); + + val = kq->kcq_pgtbl_phy.as_u32.high; + CTX_WR( + pdev, + kq->kcq_cid_addr, + WORD_ALIGNED_OFFSETOF(krnlq_context_t, krnlq_pgtbl_haddr_hi), + val); + + val = kq->kcq_pgtbl_phy.as_u32.low; + CTX_WR( + pdev, + kq->kcq_cid_addr, + WORD_ALIGNED_OFFSETOF(krnlq_context_t, krnlq_pgtbl_haddr_lo), + val); + } +} /* init_kq */ +#endif /* EXCLUDE_KQE_SUPPORT */ + +/******************************************************************************* + * Description: Determines the flow control, MAC, and CU trip values + * + * xoff = processing_q_delay + propagation_delay + response_delay + + * propagation_delay for return path + drop_margin_delay + * xon = xoff + (mtu/mbuf_size) + * + * MAC_drop = drop_margin_low*mtu/mbuf_size + * MAC_keep = drop_margin_high*mtu/mbuf_size + * + * CU_drop = (drop_margin_low+1)*mtu/mbuf_size + * CU_keep = (drop_margin_high)*mtu/mbuf_size + * + * processing_q_delay = ((mtu+20)/(64+20))+1) + * propagation_delay = 1 + * response_time = 2 (quanta) + * mbuf_size = 128 + * response_delay = (response_time*512)/(mbuf_size*8) + (mtu/mbuf_size) + * drop_margin_low = 0.5 + * drop_margin_high = 2.5 + * drop_margin_mid = 1.5 + * drop_margin_delay = (mtu*drop_margin_mid/mbuf_size) + * + * Table: + * + * Return: Flow control, MAC, and CU trip values + ******************************************************************************/ +typedef enum +{ + TRIP_FLOW = 0, + TRIP_MAC = 1, + TRIP_CU = 2 +} trip_type_t; + +STATIC void +get_trip_val( + trip_type_t type, + u32_t mtu, + u32_t *val, + u8_t enable_cu_rate_limiter, + u8_t mbuf_cnt_adj) +{ +#define NONJF_MTU_SIZE 1500 +#define MTU_STEP 500 + + const u32_t trip_tbl[3][2] = { + /* Base value, Increment */ + { 0x00410036, 0x00140010 }, /* XOFF/XON setting */ + { 0x001e0006, 0x000a0002 }, /* MAC drop/keep trip setting */ + { 0x005e0052, 0x000a0006 } /* CU drop/keep trip setting */ + }; + + const u32_t isolate_rbuf_trip_tbl[3][2] = { + /* Base value, Increment */ + { 0x0089007e, 0x00140010 }, /* XOFF/XON setting */ + { 0x0066004e, 0x000a0002 }, /* MAC drop/keep trip setting */ + { 0x0066004e, 0x000a0006 } /* CU drop/keep trip setting */ + }; + + if(type > TRIP_CU) + type = 0; /* Crash prevention */ + + *val = 0; + while(mtu > NONJF_MTU_SIZE + MTU_STEP) + { + if(enable_cu_rate_limiter) + *val += isolate_rbuf_trip_tbl[type][1]; + else + *val += trip_tbl[type][1]; + + mtu -= MTU_STEP; + } + if(enable_cu_rate_limiter) + *val = *val + (isolate_rbuf_trip_tbl[type][0] - (mbuf_cnt_adj<<16 | mbuf_cnt_adj)); + else + *val = *val + trip_tbl[type][0]; + +} /* get_trip_val */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +zero_out_sb( + lm_device_t *pdev, + u32_t *sb_ptr) +{ + u32_t sb_size; + u32_t offset; + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + sb_size = sizeof(status_blk_combined_t); + } + else + { + sb_size = sizeof(status_block_t); + } + + offset = 0; + + while(offset < sb_size) + { + *sb_ptr = 0; + sb_ptr++; + offset += sizeof(u32_t); + } +} /* zero_out_sb */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +reduce_ftq_depth( + lm_device_t *pdev) +{ + DbgBreakIf(CHIP_REV(pdev) != CHIP_REV_IKOS && + CHIP_REV(pdev) != CHIP_REV_FPGA); + + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, com.com_comxq_ftq_ctl), + 2 << 12); + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, com.com_comtq_ftq_ctl), + 2 << 12); + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, com.com_comq_ftq_ctl), + 2 << 12); + + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, cp.cp_cpq_ftq_ctl), + 4 << 12); + + REG_WR(pdev, csch.csch_ch_ftq_ctl, 8 << 12); + + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, mcp.mcp_mcpq_ftq_ctl), + 32 << 12); + + REG_WR(pdev, rdma.rdma_ftq_ctl, 2 << 12); + + REG_WR(pdev, rlup.rlup_ftq_ctl, 8 << 12); + + REG_WR(pdev, rv2p.rv2p_pftq_ctl, 2 << 12); + REG_WR(pdev, rv2p.rv2p_tftq_ctl, 2 << 12); + REG_WR(pdev, rv2p.rv2p_mftq_ctl, 4 << 12); + + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, rxp.rxp_cftq_ctl), + 8 << 12); + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, rxp.rxp_ftq_ctl), + 8 << 12); + + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, tas.tas_ftq_ctl), + 16 << 12); + + REG_WR(pdev, tbdr.tbdr_ftq_ctl, 2 << 12); + + REG_WR(pdev, tdma.tdma_ftq_ctl, 2 << 12); + + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, tpat.tpat_ftq_ctl), + 16 << 12); + + REG_WR(pdev, tsch.tsch_ftq_ctl, 2 << 12); + + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, txp.txp_ftq_ctl), + 2 << 12); +} /* reduce_ftq_depth */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_5709_for_msix( + lm_device_t *pdev) +{ + u32_t val; + + DbgBreakIf(CHIP_NUM(pdev) != CHIP_NUM_5709); + + REG_WR(pdev, + pci.pci_grc_window_addr, + (pdev->hw_info.shmem_base & ~0x7fff) | + PCI_GRC_WINDOW_ADDR_SEP_WIN); + + REG_WR(pdev, + pci.pci_grc_window1_addr, + (pdev->hw_info.shmem_base & ~0x7fff) + 0x6000 /*0x16e000 */); + + REG_RD(pdev, pci_config.pcicfg_msix_control, &val); + switch(pdev->vars.interrupt_mode) + { + case IRQ_MODE_MSIX_BASED: + /* enable all msix vectors */ + REG_WR(pdev, + hc.hc_msix_bit_vector, + HC_MSIX_BIT_VECTOR_VAL); + break; + + case IRQ_MODE_MSI_BASED: + /* enable 16 messages so hardware will + * generate maximum of 9 messages + */ + REG_RD(pdev, + pci_config.pcicfg_msi_control, + &val); + val &= PCICFG_MSI_CONTROL_MENA; + val |= PCICFG_MSI_CONTROL_MENA_16; + REG_WR(pdev, + pci_config.pcicfg_msi_control, + (u16_t)val); + break; + + case IRQ_MODE_SIMD: + /* tell the chip that we are in single isr/multiple dpc mode */ + if(val & PCICFG_MSIX_CONTROL_MSIX_ENABLE) + { + u32_t idx, addr_l, addr_h, vec_data; + + REG_WR(pdev, + hc.hc_msix_bit_vector, + HC_MSIX_BIT_VECTOR_VAL); + + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, hc1.hc1_msix_vector0_addr_l), + &addr_l); + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, hc1.hc1_msix_vector0_addr_h), + &addr_h); + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, hc1.hc1_msix_vector0_data), + &vec_data); + for(idx = 1; idx < 9; idx++) + { + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, + hc1.hc1_msix_vector0_addr_l) + + idx*4*sizeof(u32_t), + addr_l); + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, + hc1.hc1_msix_vector0_addr_h) + + idx*4*sizeof(u32_t), + addr_h); + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, + hc1.hc1_msix_vector0_data) + + idx*4*sizeof(u32_t), + vec_data); + } + } + else + { + REG_RD(pdev, + pci_config.pcicfg_msi_control, + &val); + val &= ~PCICFG_MSI_CONTROL_MENA; + REG_WR(pdev, + pci_config.pcicfg_msi_control, + (u16_t)val); + } + break; + + case IRQ_MODE_LINE_BASED: + /* do nothing */ + break; + + default: + DbgBreakMsg("Unknown interrupt mode\n"); + break; + } + + REG_WR(pdev, + pci.pci_grc_window2_addr, + MSIX_TABLE_ADDR /*MSIX vector addr */); + REG_WR(pdev, + pci.pci_grc_window3_addr, + MSIX_PBA_ADDR /*MSIX PBA addr */); + REG_WR(pdev, pci.pci_msix_tbl_off_bir, PCI_GRC_WINDOW2_BASE); + REG_WR(pdev, pci.pci_msix_pba_off_bit, PCI_GRC_WINDOW3_BASE); +} /* init_5709_for_msix */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_hc( + lm_device_t *pdev) +{ + u32_t val; + + /* Set HC timer mode. */ + REG_RD(pdev, hc.hc_config, &val); + val &= ~(HC_CONFIG_RX_TMR_MODE | HC_CONFIG_TX_TMR_MODE | + HC_CONFIG_COM_TMR_MODE | HC_CONFIG_CMD_TMR_MODE); + + if(pdev->params.hc_timer_mode & HC_RX_TIMER_MODE) + { + val |= HC_CONFIG_RX_TMR_MODE; + } + + if(pdev->params.hc_timer_mode & HC_TX_TIMER_MODE) + { + val |= HC_CONFIG_TX_TMR_MODE; + } + + if(pdev->params.hc_timer_mode & HC_COM_TIMER_MODE) + { + val |= HC_CONFIG_COM_TMR_MODE; + } + + if(pdev->params.hc_timer_mode & HC_CMD_TIMER_MODE) + { + val |= HC_CONFIG_CMD_TMR_MODE; + } + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + val &= ~HC_CONFIG_SET_MASK_AT_RD; + //if(pdev->vars.interrupt_mode > IRQ_MODE_SIMD) + //{ + // val |= HC_CONFIG_ONE_SHOT; + //} + } + + REG_WR(pdev, hc.hc_config, val); + + /* Enable timer abort a attention which is used to request + * the driver to write a driver pulse to the firmware. */ + REG_RD(pdev, hc.hc_attn_bits_enable, &val); + val |= STATUS_ATTN_BITS_TIMER_ABORT; + REG_WR(pdev, hc.hc_attn_bits_enable, val); + + /* Set HC parameters. */ + REG_WR(pdev, hc.hc_status_addr_l, pdev->vars.status_phy.as_u32.low); + REG_WR(pdev, hc.hc_status_addr_h, pdev->vars.status_phy.as_u32.high); + + REG_WR(pdev, hc.hc_statistics_addr_l, pdev->vars.stats_phy.as_u32.low); + REG_WR(pdev, hc.hc_statistics_addr_h, pdev->vars.stats_phy.as_u32.high); + + REG_WR( + pdev, + hc.hc_tx_quick_cons_trip, + (pdev->params.tx_quick_cons_trip_int << 16) | + pdev->params.tx_quick_cons_trip); + REG_WR( + pdev, + hc.hc_rx_quick_cons_trip, + (pdev->params.rx_quick_cons_trip_int << 16) | + pdev->params.rx_quick_cons_trip); + REG_WR( + pdev, + hc.hc_comp_prod_trip, + (pdev->params.comp_prod_trip_int << 16) | + pdev->params.comp_prod_trip); + REG_WR( + pdev, + hc.hc_tx_ticks, + (pdev->params.tx_ticks_int << 16) | + pdev->params.tx_ticks); + REG_WR( + pdev, + hc.hc_rx_ticks, + (pdev->params.rx_ticks_int << 16) | + pdev->params.rx_ticks); + REG_WR( + pdev, + hc.hc_com_ticks, + (pdev->params.com_ticks_int << 16) | + pdev->params.com_ticks); + REG_WR( + pdev, hc.hc_cmd_ticks, + (pdev->params.cmd_ticks_int << 16) | + pdev->params.cmd_ticks); + + val = pdev->params.stats_ticks; + if(CHIP_REV(pdev) == CHIP_REV_IKOS) + { + val = val / 1000; + if(val < 0x100) + { + val = 0x100; + } + } + REG_WR(pdev, hc.hc_stats_ticks, val); + + REG_WR(pdev, hc.hc_stat_collect_ticks, 0xbb8); /* 3ms */ + REG_WR(pdev, hc.hc_command, HC_COMMAND_CLR_STAT_NOW); +} /* init_hc */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_hc_for_5709( + lm_device_t *pdev) +{ + DbgBreakIf(CHIP_NUM(pdev) != CHIP_NUM_5709); + + init_hc(pdev); + + REG_WR(pdev, hc.hc_tx_quick_cons_trip_1, pdev->params.psb_tx_cons_trip); + REG_WR(pdev, hc.hc_tx_ticks_1, pdev->params.psb_tx_ticks); + REG_WR(pdev, hc.hc_rx_quick_cons_trip_1, pdev->params.psb_rx_cons_trip); + REG_WR(pdev, hc.hc_rx_ticks_1, pdev->params.psb_rx_ticks); + REG_WR(pdev, hc.hc_comp_prod_trip_1, pdev->params.psb_comp_prod_trip); + REG_WR(pdev, hc.hc_com_ticks_1, pdev->params.psb_com_ticks); + REG_WR(pdev, hc.hc_cmd_ticks_1, pdev->params.psb_cmd_ticks); + REG_WR(pdev, hc.hc_periodic_ticks_1, pdev->params.psb_period_ticks); + //if(pdev->vars.interrupt_mode > IRQ_MODE_SIMD) + //{ + // REG_RD(pdev, hc.hc_sb_config_1, &val); + // val |= HC_SB_CONFIG_1_ONE_SHOT; + // REG_WR(pdev, hc.hc_sb_config_1, val); + //} + + REG_WR(pdev, hc.hc_tx_quick_cons_trip_2, pdev->params.psb_tx_cons_trip); + REG_WR(pdev, hc.hc_tx_ticks_2, pdev->params.psb_tx_ticks); + REG_WR(pdev, hc.hc_rx_quick_cons_trip_2, pdev->params.psb_rx_cons_trip); + REG_WR(pdev, hc.hc_rx_ticks_2, pdev->params.psb_rx_ticks); + REG_WR(pdev, hc.hc_comp_prod_trip_2, pdev->params.psb_comp_prod_trip); + REG_WR(pdev, hc.hc_com_ticks_2, pdev->params.psb_com_ticks); + REG_WR(pdev, hc.hc_cmd_ticks_2, pdev->params.psb_cmd_ticks); + REG_WR(pdev, hc.hc_periodic_ticks_2, pdev->params.psb_period_ticks); + //if(pdev->vars.interrupt_mode > IRQ_MODE_SIMD) + //{ + // REG_RD(pdev, hc.hc_sb_config_2, &val); + // val |= HC_SB_CONFIG_2_ONE_SHOT; + // REG_WR(pdev, hc.hc_sb_config_2, val); + //} + + REG_WR(pdev, hc.hc_tx_quick_cons_trip_3, pdev->params.psb_tx_cons_trip); + REG_WR(pdev, hc.hc_tx_ticks_3, pdev->params.psb_tx_ticks); + REG_WR(pdev, hc.hc_rx_quick_cons_trip_3, pdev->params.psb_rx_cons_trip); + REG_WR(pdev, hc.hc_rx_ticks_3, pdev->params.psb_rx_ticks); + REG_WR(pdev, hc.hc_comp_prod_trip_3, pdev->params.psb_comp_prod_trip); + REG_WR(pdev, hc.hc_com_ticks_3, pdev->params.psb_com_ticks); + REG_WR(pdev, hc.hc_cmd_ticks_3, pdev->params.psb_cmd_ticks); + REG_WR(pdev, hc.hc_periodic_ticks_3, pdev->params.psb_period_ticks); + //if(pdev->vars.interrupt_mode > IRQ_MODE_SIMD) + //{ + // REG_RD(pdev, hc.hc_sb_config_3, &val); + // val |= HC_SB_CONFIG_3_ONE_SHOT; + // REG_WR(pdev, hc.hc_sb_config_3, val); + //} + + REG_WR(pdev, hc.hc_tx_quick_cons_trip_4, pdev->params.psb_tx_cons_trip); + REG_WR(pdev, hc.hc_tx_ticks_4, pdev->params.psb_tx_ticks); + REG_WR(pdev, hc.hc_rx_quick_cons_trip_4, pdev->params.psb_rx_cons_trip); + REG_WR(pdev, hc.hc_rx_ticks_4, pdev->params.psb_rx_ticks); + REG_WR(pdev, hc.hc_comp_prod_trip_4, pdev->params.psb_comp_prod_trip); + REG_WR(pdev, hc.hc_com_ticks_4, pdev->params.psb_com_ticks); + REG_WR(pdev, hc.hc_cmd_ticks_4, pdev->params.psb_cmd_ticks); + REG_WR(pdev, hc.hc_periodic_ticks_4, pdev->params.psb_period_ticks); + //if(pdev->vars.interrupt_mode > IRQ_MODE_SIMD) + //{ + // REG_RD(pdev, hc.hc_sb_config_4, &val); + // val |= HC_SB_CONFIG_4_ONE_SHOT; + // REG_WR(pdev, hc.hc_sb_config_4, val); + //} + + REG_WR(pdev, hc.hc_tx_quick_cons_trip_5, pdev->params.psb_tx_cons_trip); + REG_WR(pdev, hc.hc_tx_ticks_5, pdev->params.psb_tx_ticks); + REG_WR(pdev, hc.hc_rx_quick_cons_trip_5, pdev->params.psb_rx_cons_trip); + REG_WR(pdev, hc.hc_rx_ticks_5, pdev->params.psb_rx_ticks); + REG_WR(pdev, hc.hc_comp_prod_trip_5, pdev->params.psb_comp_prod_trip); + REG_WR(pdev, hc.hc_com_ticks_5, pdev->params.psb_com_ticks); + REG_WR(pdev, hc.hc_cmd_ticks_5, pdev->params.psb_cmd_ticks); + REG_WR(pdev, hc.hc_periodic_ticks_5, pdev->params.psb_period_ticks); + //if(pdev->vars.interrupt_mode > IRQ_MODE_SIMD) + //{ + // REG_RD(pdev, hc.hc_sb_config_5, &val); + // val |= HC_SB_CONFIG_5_ONE_SHOT; + // REG_WR(pdev, hc.hc_sb_config_5, val); + //} + + REG_WR(pdev, hc.hc_tx_quick_cons_trip_6, pdev->params.psb_tx_cons_trip); + REG_WR(pdev, hc.hc_tx_ticks_6, pdev->params.psb_tx_ticks); + REG_WR(pdev, hc.hc_rx_quick_cons_trip_6, pdev->params.psb_rx_cons_trip); + REG_WR(pdev, hc.hc_rx_ticks_6, pdev->params.psb_rx_ticks); + REG_WR(pdev, hc.hc_comp_prod_trip_6, pdev->params.psb_comp_prod_trip); + REG_WR(pdev, hc.hc_com_ticks_6, pdev->params.psb_com_ticks); + REG_WR(pdev, hc.hc_cmd_ticks_6, pdev->params.psb_cmd_ticks); + REG_WR(pdev, hc.hc_periodic_ticks_6, pdev->params.psb_period_ticks); + //if(pdev->vars.interrupt_mode > IRQ_MODE_SIMD) + //{ + // REG_RD(pdev, hc.hc_sb_config_6, &val); + // val |= HC_SB_CONFIG_6_ONE_SHOT; + // REG_WR(pdev, hc.hc_sb_config_6, val); + //} + + REG_WR(pdev, hc.hc_tx_quick_cons_trip_7, pdev->params.psb_tx_cons_trip); + REG_WR(pdev, hc.hc_tx_ticks_7, pdev->params.psb_tx_ticks); + REG_WR(pdev, hc.hc_rx_quick_cons_trip_7, pdev->params.psb_rx_cons_trip); + REG_WR(pdev, hc.hc_rx_ticks_7, pdev->params.psb_rx_ticks); + REG_WR(pdev, hc.hc_comp_prod_trip_7, pdev->params.psb_comp_prod_trip); + REG_WR(pdev, hc.hc_com_ticks_7, pdev->params.psb_com_ticks); + REG_WR(pdev, hc.hc_cmd_ticks_7, pdev->params.psb_cmd_ticks); + REG_WR(pdev, hc.hc_periodic_ticks_7, pdev->params.psb_period_ticks); + //if(pdev->vars.interrupt_mode > IRQ_MODE_SIMD) + //{ + // REG_RD(pdev, hc.hc_sb_config_7, &val); + // val |= HC_SB_CONFIG_7_ONE_SHOT; + // REG_WR(pdev, hc.hc_sb_config_7, val); + //} + + REG_WR(pdev, hc.hc_tx_quick_cons_trip_8, pdev->params.psb_tx_cons_trip); + REG_WR(pdev, hc.hc_tx_ticks_8, pdev->params.psb_tx_ticks); + REG_WR(pdev, hc.hc_rx_quick_cons_trip_8, pdev->params.psb_rx_cons_trip); + REG_WR(pdev, hc.hc_rx_ticks_8, pdev->params.psb_rx_ticks); + REG_WR(pdev, hc.hc_comp_prod_trip_8, pdev->params.psb_comp_prod_trip); + REG_WR(pdev, hc.hc_com_ticks_8, pdev->params.psb_com_ticks); + REG_WR(pdev, hc.hc_cmd_ticks_8, pdev->params.psb_cmd_ticks); + REG_WR(pdev, hc.hc_periodic_ticks_8, pdev->params.psb_period_ticks); + //if(pdev->vars.interrupt_mode > IRQ_MODE_SIMD) + //{ + // REG_RD(pdev, hc.hc_sb_config_8, &val); + // val |= HC_SB_CONFIG_8_ONE_SHOT; + // REG_WR(pdev, hc.hc_sb_config_8, val); + //} +} /* init_hc_for_5709 */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +init_hc_for_57728( + lm_device_t *pdev) +{ + init_hc(pdev); + init_hc_for_5709(pdev); + + #if X1V_havhavhav + REG_WR(pdev, hc.hc_sb_haddr_0_lo, pdev->vars.status_phy.as_u32.low); + REG_WR(pdev, hc.hc_sb_haddr_0_hi, pdev->vars.status_phy.as_u32.high); + + REG_WR(pdev, hc.hc_sb_select_0_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 0); + REG_WR(pdev, hc.hc_sb_select_1_config, + ENABLE | fid == 1 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 7); + REG_WR(pdev, hc.hc_sb_select_2_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 2); + REG_WR(pdev, hc.hc_sb_select_3_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 3); + REG_WR(pdev, hc.hc_sb_select_4_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 4); + REG_WR(pdev, hc.hc_sb_select_5_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 5); + REG_WR(pdev, hc.hc_sb_select_6_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 6); + REG_WR(pdev, hc.hc_sb_select_7_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 7); + REG_WR(pdev, hc.hc_sb_select_8_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 8); + REG_WR(pdev, hc.hc_sb_select_8_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 9); + REG_WR(pdev, hc.hc_sb_select_8_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 10); + REG_WR(pdev, hc.hc_sb_select_8_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 11); + REG_WR(pdev, hc.hc_sb_select_8_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 12); + REG_WR(pdev, hc.hc_sb_select_8_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 13); + REG_WR(pdev, hc.hc_sb_select_8_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 14); + REG_WR(pdev, hc.hc_sb_select_8_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 15); + REG_WR(pdev, hc.hc_sb_select_8_config, + ENABLE | fid == 7 | param-sel = 0 | haddr_sel = 0 | + haddr_idx_sel = 16); + #endif +} /* init_hc_for_57728 */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ + +// Refer to TetonII Register spec, setting bits in krl_???_mask1 and +// krl_???_mask2 will cause the corresponding engine (CP or RV2P) to be +// activated when any word enabled by this mask is written. Mask1 is +// for first 128 bytes and mask2 is for second 128 bytes. +// Each bit in the mask correspond to a 32 bit word in the kernal area. +// e.g. Writing 0x2000 to the mask2 means activating the engine +// when context location 0xB4 is being written +// (i.e. (0xB4 - 128)/sizeof(u32_t) = bit 13 +#define KNL_L4_MASK(field) \ + (1<<(OFFSETOF(l4_context_t, l4ctx_l4_bd_chain_##field) & ~0x80)/sizeof(u32_t)) + +#define KNL_L5_MASK(field) \ + (1<<(OFFSETOF(l5_context_t, l5ctx_##field) & ~0x80)/sizeof(u32_t)) + +lm_status_t +lm_reset_setup( + lm_device_t *pdev, + u32_t reset_reason) +{ + u32_t val; + u8_t mbuf_adj = 0; + + lm_chip_reset(pdev, reset_reason); + + /* Teton family of chips does not support PCI-X relax ordering. */ + if(pdev->hw_info.bus_mode == BUS_MODE_PCIX) + { + REG_RD_OFFSET( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_pcix_cap_id), + &val); + val &= ~(PCICFG_PCIX_COMMAND_RELAX_ORDER << 16); + REG_WR_OFFSET( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_pcix_cap_id), + val); + } + + /* 5709 devices have interrupts enabled by default + * after a hardware reset. Disable them. + */ + lm_disable_int(pdev); + + /* The linkready signal going to the MAC is qualified by a port + * mode of GMII or MII. When the port mode is NONE, the linkready + * signal is always deasserted when when link is active. Thus for + * us to get a link change event, we need to set the port mode to + * something other than NONE. This logic may change in future + * version of the chip. + * + * Also when the port mode is set NONE, the register read/write + * to the emac block (0x1408) will cause the TETON-II FPGA to + * lock up. This is not seen with the original TETON FPGA. */ + REG_WR(pdev, emac.emac_mode, EMAC_MODE_EXT_LINK_POL | EMAC_MODE_PORT_GMII); + + /* Setup DMA configuration. The swap settings are what the device will + * will do, not the net result you want. This is because there could + * be swapping by intermediary devices (pci bridges). */ + val = DMA_CONFIG_DATA_BYTE_SWAP_TE | + DMA_CONFIG_DATA_WORD_SWAP_TE | + DMA_CONFIG_CNTL_WORD_SWAP_TE | +#ifdef BIG_ENDIAN + DMA_CONFIG_CNTL_BYTE_SWAP_TE | +#endif + (pdev->params.num_rchans & 0xf) << 12 | + (pdev->params.num_wchans & 0xf) << 16; + + /* Workaround for data corruption on Intel 840/860 chipset. */ + if(pdev->params.ping_pong_dma) + { + val |= DMA_CONFIG_CNTL_PING_PONG_DMA_TE; + } + + /* Apply workaround to avoid race condition in DMA completion + * and write to DMA buffer memory. This configuration should be + * enabled on all versions of 5706. */ + val |= (0x2<<20) | (1<<11); + + /* Enable delayed completion. */ + if(pdev->hw_info.bus_mode == BUS_MODE_PCIX && + pdev->hw_info.bus_speed == BUS_SPEED_133_MHZ && + CHIP_ID(pdev) != CHIP_ID_5706_A0) + { + val |= 1 << 23; + } + + /* Configure the clock ratio in the FPGA mode. */ + if(CHIP_REV(pdev) == CHIP_REV_FPGA) + { + val |= 0x100; + } + + REG_WR(pdev, dma.dma_config, val); + + if(pdev->params.one_tdma) + { + REG_RD(pdev, tdma.tdma_config, &val); + val |= TDMA_CONFIG_ONE_DMA; + REG_WR(pdev, tdma.tdma_config, val); + } + + if(CHIP_REV(pdev) == CHIP_REV_FPGA) + { + REG_RD(pdev, pci.pci_config_2, &val); + val &= ~0x02000000; + REG_WR(pdev, pci.pci_config_2, val); + } + + /* We need to enable the context block so we can initialize context + * memory. + * + * We also need to enable HC so it can record the link state and the + * first status block update we get will reflect the current state. + * + * We need to enable RV2P in order to download the firmwares for + * its two processors. */ + REG_WR( + pdev, + misc.misc_enable_set_bits, + MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | + MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | + MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE | + MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); + + /* Initialize context mapping and zero out the quick contexts. The + * context block must have already been enabled. */ + if(CHIP_ID(pdev) == CHIP_ID_5706_A0) + { + init_context_5706_a0_wa(pdev); + } + else if(CHIP_NUM(pdev) == CHIP_NUM_5706 || CHIP_NUM(pdev) == CHIP_NUM_5708) + { + init_context_5706(pdev); + } + else if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + init_context_5709(pdev); + #if 0 + /* Temporary L4 fix. */ + // if(CHIP_ID(pdev) == CHIP_ID_5709_IKOS || + // CHIP_ID(pdev) == CHIP_ID_5709_FPGA) + { + REG_WR(pdev, mq.mq_map_l4_0, 0x8001c1b9); + } + #endif + + REG_WR(pdev, mq.mq_map_l4_0, 0x80010db9); + REG_WR(pdev, mq.mq_map_l4_4, 0x82810eb2); + REG_WR(pdev, mq.mq_map_l4_5, 0x8f0113b4); + } + else + { + DbgBreakIf(1); + } + + if(pdev->params.test_mode & TEST_MODE_XDIAG_ISCSI) + { + lm_init_cpus(pdev, CPU_RV2P_1 | CPU_RV2P_2); /* other CPUs are loaded through TCL */ + } + else + { + lm_init_cpus(pdev, CPU_ALL); + } + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+ + RXP_HSI_OFFSETOFF(hw_filter_ctx_offset), + &pdev->vars.hw_filter_ctx_offset); + + init_5709_for_msix(pdev); + } + + lm_nvram_init(pdev, FALSE); + + /* tcp_syn_dos_defense - let the firmware route all the packets with + * TCP SYN bit set to rx chain #1. */ + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(tcp_syn_dos_defense), + pdev->params.enable_syn_rcvq); + + REG_RD(pdev, mq.mq_config, &val); + val &= ~MQ_CONFIG_KNL_BYP_BLK_SIZE; + switch((LM_PAGE_BITS - 8) << 4) + { + case MQ_CONFIG_KNL_BYP_BLK_SIZE_256: + val |= MQ_CONFIG_KNL_BYP_BLK_SIZE_256; + break; + + case MQ_CONFIG_KNL_BYP_BLK_SIZE_512: + val |= MQ_CONFIG_KNL_BYP_BLK_SIZE_512; + break; + + case MQ_CONFIG_KNL_BYP_BLK_SIZE_1K: + val |= MQ_CONFIG_KNL_BYP_BLK_SIZE_1K; + break; + + case MQ_CONFIG_KNL_BYP_BLK_SIZE_2K: + val |= MQ_CONFIG_KNL_BYP_BLK_SIZE_2K; + break; + + case MQ_CONFIG_KNL_BYP_BLK_SIZE_4K: + val |= MQ_CONFIG_KNL_BYP_BLK_SIZE_4K; + break; + + default: + DbgBreakMsg("Not supported page size.\n"); + break; + } + + if(pdev->params.bin_mq_mode) + { + DbgBreakIf(CHIP_NUM(pdev) != CHIP_NUM_5709); + + val |= MQ_CONFIG_BIN_MQ_MODE; + } + + REG_WR(pdev, mq.mq_config, val); + + /* Configure the end of the kernel mailboxq window and the start of the + * kernel bypass mailboxq. */ + val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); + REG_WR(pdev, mq.mq_knl_byp_wind_start, val); + REG_WR(pdev, mq.mq_knl_wind_end, val); + + /* Configure page size. */ + REG_RD(pdev, tbdr.tbdr_config, &val); + val &= ~TBDR_CONFIG_PAGE_SIZE; + val |= (LM_PAGE_BITS - 8) << 24 | 0x40; + REG_WR(pdev, tbdr.tbdr_config, val); + + /* Program the MTU. Also include 4 bytes for CRC32. */ + val = pdev->params.mtu+4; + if(pdev->params.mtu > MAX_ETHERNET_PACKET_SIZE) + { + val |= EMAC_RX_MTU_SIZE_JUMBO_ENA; + } + REG_WR(pdev, emac.emac_rx_mtu_size, val); + + if(pdev->vars.enable_cu_rate_limiter) + { + if(pdev->vars.cu_mbuf_cnt > 0x48) + { + /* only allow cu mbuf cluster cnt up to 0x48 to accomodate jumbo + * frame size of 9018 ( note: each mbuf cluster is 128 bytes) */ + pdev->vars.cu_mbuf_cnt = 0x48; + } + + if(pdev->vars.cu_mbuf_cnt == 0) + { + /* chip default use 8k cu mbuf */ + mbuf_adj = 0x48 - 0x40; + } + else + { + mbuf_adj = 0x48 - pdev->vars.cu_mbuf_cnt; + } + } + /* Added flow control trip setup, JF or non-JF */ + get_trip_val( + TRIP_FLOW, + pdev->params.mtu, + &val, + pdev->vars.enable_cu_rate_limiter, + mbuf_adj); + + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, rbuf.rbuf_config), + val); + + get_trip_val( + TRIP_MAC, + pdev->params.mtu, + &val, + pdev->vars.enable_cu_rate_limiter, + mbuf_adj); + + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, rbuf.rbuf_config2), + val); + + if(!pdev->vars.enable_cu_rate_limiter) + { + get_trip_val(TRIP_CU, pdev->params.mtu, &val, 0, 0); + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, rbuf.rbuf_config3), + val); + } + else + { + /* isolate catchup traffic rbuf from normal traffic */ + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, rbuf.rbuf_command), + &val); + val |= RBUF_COMMAND_CU_ISOLATE_XI; + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, rbuf.rbuf_command), + val); + + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, rbuf.rbuf_config3), + 0); + if(pdev->vars.cu_mbuf_cnt) + { + val = pdev->vars.cu_mbuf_cnt; + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, rbuf.rbuf_cu_buffer_size), + val); + } + else + { + /* get default cu_mbuf_cnt from chip */ + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, rbuf.rbuf_cu_buffer_size), + &val); + } + /*account for initial MBUF allocated by the RPC*/ + val -= 1; + val *= 128; + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_cu_buf_size), + val); + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(cu_rate_limiter_enable), + 1); + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, txp.txp_scratch[0])+TXP_HSI_OFFSETOFF(cu_rate_limiter_enable), + 1); + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(cu_rate_limiter_enable), + 1); + } + + /* Set up how to generate a link change interrupt. */ + if(pdev->params.phy_int_mode == PHY_INT_MODE_MI_INTERRUPT) + { + REG_WR(pdev, emac.emac_attention_ena, EMAC_ATTENTION_ENA_MI_INT); + } + else if(pdev->params.phy_int_mode == PHY_INT_MODE_LINK_READY) + { + REG_WR(pdev, emac.emac_attention_ena, EMAC_ATTENTION_ENA_LINK); + } + else if(pdev->params.phy_int_mode == PHY_INT_MODE_AUTO_POLLING) + { + REG_WR(pdev, emac.emac_attention_ena, EMAC_ATTENTION_ENA_LINK); + + REG_RD(pdev, emac.emac_mdio_mode, &val); + val |= EMAC_MDIO_MODE_AUTO_POLL; + REG_WR(pdev, emac.emac_mdio_mode, val); + } + else + { + DbgBreakMsg("Invalid phy_int_mode.\n"); + } + + zero_out_sb(pdev, (u32_t *) pdev->vars.status_virt); + + if(CHIP_NUM(pdev) == CHIP_NUM_5706 || + CHIP_NUM(pdev) == CHIP_NUM_5708) + { + init_hc(pdev); + } + else if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + init_hc_for_5709(pdev); + } + else if(CHIP_NUM(pdev) == CHIP_NUM_57728) + { + init_hc_for_57728(pdev); + } + else + { + DbgBreakMsg("### Invalid chip number.\n"); + } + + if(CHIP_REV(pdev) == CHIP_REV_IKOS || CHIP_REV(pdev) == CHIP_REV_FPGA) + { + reduce_ftq_depth(pdev); + } + + init_l2txq(pdev); + init_l2rxq(pdev); + + #ifndef EXCLUDE_KQE_SUPPORT + init_kq(pdev); + #endif + + #if INCLUDE_OFLD_SUPPORT + l4_reset_setup(pdev); + #endif + + /* Enable Commnad Scheduler notification when we write to the + * host producer index of the kernel contexts. */ + REG_WR(pdev, mq.mq_knl_cmd_mask1, KNL_L5_MASK(sq_pidx)); + + /* Enable Command Scheduler notification when we write to either + * the Send Queue or Receive Queue producer indexes of the kernel + * bypass contexts. */ + REG_WR(pdev, mq.mq_knl_byp_cmd_mask1, KNL_L5_MASK(cq_cidx)| + KNL_L5_MASK(sq_pidx)| + KNL_L5_MASK(rq_pidx)); + REG_WR(pdev, mq.mq_knl_byp_write_mask1, KNL_L5_MASK(cq_cidx)| + KNL_L5_MASK(sq_pidx)| + KNL_L5_MASK(rq_pidx)); + + /* Use kernel mailbox for L5 context (iSCSI and rdma). */ + REG_WR(pdev, mq.mq_knl_cmd_mask1, KNL_L5_MASK(cq_cidx)| + KNL_L5_MASK(sq_pidx)| + KNL_L5_MASK(rq_pidx)); + REG_WR(pdev, mq.mq_knl_write_mask1, KNL_L5_MASK(cq_cidx)| + KNL_L5_MASK(sq_pidx)| + KNL_L5_MASK(rq_pidx)); +#ifndef L2_ONLY + if(CHIP_NUM(pdev) != CHIP_NUM_5709) + { + /* Notify CP when the driver post an application buffer. (i.e. writing to host_bseq) */ + REG_WR(pdev, mq.mq_knl_cmd_mask2, KNL_L4_MASK(host_bseq)); + } + else // CHIP_NUM_5709 + { + /* Notify RV2P when the driver post an application buffer. (i.e. writing to host_bseq) */ + REG_WR(pdev, mq.mq_knl_rx_v2p_mask2, KNL_L4_MASK(host_bseq)); + } +#endif + #ifndef EXCLUDE_KQE_SUPPORT + /* fw_doorbell - These two processors polls the doorbell for a non zero + * value before running. This must be done after setting up the kernel + * queue contexts. */ + if(pdev->params.kcq_page_cnt) + { + REG_WR_IND(pdev, OFFSETOF(reg_space_t, cp.cp_scratch[0])+CP_HSI_OFFSETOFF(fw_doorbell), 1); + REG_WR_IND(pdev, OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(fw_doorbell), 1); + + mm_wait(pdev, 5); + } + #endif + + /* get information from firmware-configured mq.mq_config2. */ + if(pdev->params.bin_mq_mode) + { + REG_RD(pdev, mq.mq_config2, &val); + + pdev->hw_info.first_l4_l5_bin = (u16_t) (val & MQ_CONFIG2_FIRST_L4L5); + pdev->hw_info.bin_size = (u8_t) (val & MQ_CONFIG2_CONT_SZ) >> 3; + } + + /* Configure page size and start the RV2P processors. */ + val = (LM_PAGE_BITS - 8) << 24; + REG_WR(pdev, rv2p.rv2p_config, val); + + /* Setup the MAC for the current link settings. The HC should be already + * enabled. We need to enable it so it is aware of the current link + * state and link acknowledgement (via the call below). The first + * status block update we get will reflect the current link state. */ + lm_service_phy_int(pdev, TRUE); + + return LM_STATUS_SUCCESS; +} /* lm_reset_setup */ + + + +#if INCLUDE_OFLD_SUPPORT +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +enable_alt_catchup( + lm_device_t *pdev) +{ + l4_kwqe_enable_alt_catchup_t *alt_catchup_kwqe; + kwqe_t *prod_qe; + u16_t prod_idx; + + pdev->kq_info.kwqe_left -= 1; + + prod_qe = pdev->kq_info.kwq_prod_qe; + prod_idx = pdev->kq_info.kwq_prod_idx; + + alt_catchup_kwqe = (l4_kwqe_enable_alt_catchup_t *) prod_qe; + alt_catchup_kwqe->tcp_hdr_flags = TCP_HDR_FLAGS_LAYER_MASK_L4; + alt_catchup_kwqe->tcp_hdr_opcode = TCP_HDR_OPCODE_VALUE_ENABLE_ALT_CATCHUP; + + /* Advance to the next KWQE. */ + if(prod_qe == pdev->kq_info.kwq_last_qe) + { + prod_qe = pdev->kq_info.kwq_virt; + } + else + { + prod_qe++; + } + prod_idx++; + + pdev->kq_info.kwq_prod_qe = prod_qe; + pdev->kq_info.kwq_prod_idx = prod_idx; + + /* catchup_override - use cid 0x30 (catchup2) instead of tx1 for catcup. */ + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, tpat.tpat_scratch[0])+TPAT_HSI_OFFSETOFF(catchup_overide), + 1); + + MBQ_WR16( + pdev, + GET_CID(pdev->kq_info.kwq_cid_addr), + OFFSETOF(krnlq_context_t, krnlq_host_qidx), + prod_idx); +} /* enable_alt_catchup */ +#endif + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_reset_run( + lm_device_t *pdev) +{ + u32_t max_loop_cnt; + u32_t idx; + + /* Enable all the state machines including the processors. We could use + * REG_WR(pdev, misc.misc_command, MISC_COMMAND_ENABLE_ALL) this write + * but for now we don't want to enable the timer block yet. This + * needs to be done by the firmware. */ + REG_WR(pdev, misc.misc_enable_set_bits, 0x15ffffff); + + /* Allow the firmware to run. How long is the delay? */ + max_loop_cnt = 1000; + if(CHIP_REV(pdev) == CHIP_REV_IKOS) + { + max_loop_cnt = 25000; + } + + for(idx = 0; idx < max_loop_cnt; idx++) + { + mm_wait(pdev, 10); + } + + #if INCLUDE_OFLD_SUPPORT + /* 'tx4' (cid 30/31) for catcup. */ + if(pdev->tx_info.cu_idx != TX_CHAIN_IDX1) + { + enable_alt_catchup(pdev); + } + #endif + + /* Force the first status block update so we can acknowledge the initial + * link status and service an link change since we last call + * lm_service_phy_int. If we need to do this here so that we don't have + * to service a link change event when later we receive a status + * block update. */ + REG_WR(pdev, hc.hc_command, HC_COMMAND_COAL_NOW_WO_INT); + + /* Wait for the status block. In the IKOS environment we need to + * wait this long. This delay may be reduced significantly when running + * on the real chip. */ + mm_wait(pdev, 20); + if(CHIP_REV(pdev) == CHIP_REV_IKOS) + { + for(idx = 0; idx < 100; idx++) + { + mm_wait(pdev, 10); + } + } + + /* Setup the MAC for the current link settings and acknowledge the + * current link state if necessary. */ + lm_service_phy_int(pdev, FALSE); + + /* Ensure the status block in host memory reflect the current link + * state and link acknowledgement. */ + REG_WR(pdev, hc.hc_command, HC_COMMAND_COAL_NOW); + + return LM_STATUS_SUCCESS; +} /* lm_reset_run */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_reset( + lm_device_t *pdev, + u32_t reset_reason) +{ + lm_status_t status; + + status = lm_reset_setup(pdev, reset_reason); + if(status == LM_STATUS_SUCCESS) + { + status = lm_reset_run(pdev); + } + + return status; +} /* lm_reset */ diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c new file mode 100644 index 0000000000..56b52b7e85 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c @@ -0,0 +1,5736 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "lm5706.h" +#if !defined(LINUX) && !defined(SOLARIS) +#include "string.h" // needed by some OS for memset +#pragma warning(disable:28718) +#endif + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_abort( + lm_device_t *pdev, + u32_t abort_op, + u32_t idx) +{ + if(abort_op == ABORT_OP_RX_CHAIN) + { + lm_recv_abort(pdev, idx); + } + else if(abort_op == ABORT_OP_TX_CHAIN) + { + lm_send_abort(pdev, idx); + } + else + { + DbgBreakMsg("Invalid abort.\n"); + } +} /* lm_abort */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC char * +val_to_decimal_string( + char *str_buf, + u32_t buf_size, + u32_t val) +{ + u32_t digit; + + if(buf_size == 0) + { + return str_buf; + } + + digit = val % 10; + val = val / 10; + + if(val) + { + buf_size--; + str_buf = val_to_decimal_string(str_buf, buf_size, val); + } + + *str_buf = '0' + digit; + + str_buf++; + + return str_buf; +} /* val_to_decimal_string */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u32_t +build_ver_string( + char *str_buf, + u32_t buf_size, + u8_t major_ver, + u8_t minor_ver, + u8_t rel_num, + u8_t fix_num) +{ + char *p; + + if(buf_size == 0) + { + return 0; + } + + p = str_buf; + + if(buf_size - (p - str_buf) > 1) + { + *p = 'v'; + p++; + } + + if(buf_size - (p - str_buf) > 1) + { + p = val_to_decimal_string( + p, + buf_size - (u32_t) PTR_SUB(p, str_buf), + major_ver); + } + + if(buf_size - (p - str_buf) > 1) + { + *p = '.'; + p++; + } + + if(buf_size - (u32_t) PTR_SUB(p, str_buf) > 1) + { + p = val_to_decimal_string( + p, + buf_size - (u32_t) PTR_SUB(p, str_buf), + minor_ver); + } + + if(buf_size - (u32_t) PTR_SUB(p, str_buf) > 1) + { + *p = '.'; + p++; + } + + if(buf_size - (u32_t) PTR_SUB(p, str_buf) > 1) + { + p = val_to_decimal_string( + p, + buf_size - (u32_t) PTR_SUB(p, str_buf), + rel_num); + } + + if(buf_size - (u32_t) PTR_SUB(p, str_buf) > 1) + { + *p = '.'; + p++; + } + + if(buf_size - (u32_t) PTR_SUB(p, str_buf) > 1) + { + p = val_to_decimal_string( + p, + buf_size - (u32_t) PTR_SUB(p, str_buf), + fix_num); + } + + if(buf_size - (u32_t) PTR_SUB(p, str_buf) > 1) + { + *p = '.'; + p++; + } + + if(buf_size - (u32_t) PTR_SUB(p, str_buf) > 1) + { + #if DBG + *p = 'd'; + #else + *p = 'r'; + #endif + + p++; + } + + if(buf_size - (u32_t) PTR_SUB(p, str_buf) > 1) + { + #if DBG + *p = 'b'; + #else + *p = 't'; + #endif + + p++; + } + + if(buf_size - (u32_t) PTR_SUB(p, str_buf) > 1) + { + #if DBG + *p = 'g'; + #else + *p = 'l'; + #endif + + p++; + } + + *p = 0; + p++; + + return (u32_t) PTR_SUB(p, str_buf); +} /* build_ver_string */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +get_max_conns( + lm_device_t *pdev, + u32_t *max_toe_conn, + u32_t *max_iscsi_conn, + u32_t *max_iscsi_pending_tasks) +{ + u32_t max_lic_conn; + u32_t max_res_conn; + u32_t res_flags; + + /* get resource reservation flag. */ + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, + dev_info.port_feature_config.resource.res_cfg), + &res_flags); + + /* get max_lic_conn for toe. */ + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, fw_lic_key.max_toe_conn), + &max_lic_conn); + + max_lic_conn &= 0xffff; + + if(max_lic_conn) + { + max_lic_conn ^= FW_ENCODE_16BIT_PATTERN; + + if(max_lic_conn == 0xffff) + { + max_lic_conn = 1024; + } + } + + /* get max_res_conn for toe. */ + if(res_flags & RES_RES_CFG_VALID) + { + if(res_flags & RES_RES_CFG_L2) + { + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, + dev_info.port_feature_config.resource.conn_resource1), + &max_res_conn); + /* + * if(max_res_conn == 0 || !(res_flags & RES_RES_CFG_FCFS_DISABLED)) + * CQ#42214 HH, SK and HYF all agreed on removing the test + * for max_res_conn == 0 + */ + if (!(res_flags & RES_RES_CFG_FCFS_DISABLED)) + { + max_res_conn = 1024; + } + } + else + { + max_res_conn = 0; + } + } + else + { + max_res_conn = 1024; + } + + *max_toe_conn = (max_lic_conn < max_res_conn) ? max_lic_conn: max_res_conn; + + /* get iscsi pending tasks. */ + if((res_flags & RES_RES_CFG_VALID) && (res_flags & RES_RES_CFG_ISCSI)) + { + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, + dev_info.port_feature_config.resource.conn_resource3), + max_iscsi_pending_tasks); + + *max_iscsi_pending_tasks &= RES_CONN_ISCSI_PTASK_MASK; + + if(*max_iscsi_pending_tasks == 0 || *max_iscsi_pending_tasks > 128) + { + *max_iscsi_pending_tasks = 128; + } + } + else + { + *max_iscsi_pending_tasks = 128; + *max_iscsi_conn = 0; + } + + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, fw_lic_key.max_iscsi_trgt_conn), + &max_lic_conn); + + if(max_lic_conn) + { + max_lic_conn ^= FW_ENCODE_32BIT_PATTERN; + max_lic_conn >>= 16; + } + + *max_iscsi_conn = max_lic_conn; + + /* no license information. */ + if(*max_toe_conn == 0) + { + if(pdev->hw_info.svid == 0x103c) /* HP device. */ + { + *max_toe_conn = 1024; + } + else if(CHIP_REV(pdev) == CHIP_REV_IKOS || + CHIP_REV(pdev) == CHIP_REV_FPGA) + { + *max_toe_conn = 32; + } + } + + /* cq#39856 - iSCSI Device Disappears from System after reboot. */ + if(*max_iscsi_conn == 0) + { + if(pdev->hw_info.svid == 0x103c) /* HP device. */ + { + *max_iscsi_conn = 1024; + } + else if(CHIP_REV(pdev) == CHIP_REV_IKOS || + CHIP_REV(pdev) == CHIP_REV_FPGA) + { + *max_iscsi_conn = 32; + } + } +} /* get_max_conns */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_get_dev_info( + lm_device_t *pdev) +{ + typedef struct _param_entry_t + { + /* Ideally, we want to save the address of the parameter here. + * However, some compiler will not allow us to dynamically + * initialize the pointer to a parameter in the table below. + * As an alternative, we will save the offset to the parameter + * from pdev device structure. */ + u32_t offset; + + /* Parameter default value. */ + u32_t asic_default; + u32_t fpga_ikos_default; + + /* Limit checking is diabled if min and max are zeros. */ + u32_t min; + u32_t max; + } param_entry_t; + + #define _OFFSET(_name) (OFFSETOF(lm_device_t, params._name)) + #define PARAM_VAL(_pdev, _entry) \ + (*((u32_t *) ((u8_t *) (_pdev) + (_entry)->offset))) + #define SET_PARAM_VAL(_pdev, _entry, _val) \ + *((u32_t *) ((u8_t *) (_pdev) + (_entry)->offset)) = (_val) + + static param_entry_t param_list[] = + { + /* asic fpga/ikos + offset default default min max */ + { _OFFSET(mtu), 1500, 1500, 1500, 9018 }, + { _OFFSET(l2_rx_desc_cnt[0]), 200, 150, 0, 0 }, + { _OFFSET(l2_rx_desc_cnt[1]), 0, 0, 0, 0 }, + { _OFFSET(l2_rx_desc_cnt[2]), 0, 0, 0, 0 }, + { _OFFSET(l2_rx_desc_cnt[3]), 0, 0, 0, 0 }, + { _OFFSET(l2_rx_desc_cnt[4]), 0, 0, 0, 0 }, + { _OFFSET(l2_rx_desc_cnt[5]), 0, 0, 0, 0 }, + { _OFFSET(l2_rx_desc_cnt[6]), 0, 0, 0, 0 }, + { _OFFSET(l2_rx_desc_cnt[7]), 0, 0, 0, 0 }, + { _OFFSET(l2_rx_desc_cnt[8]), 0, 0, 0, 0 }, + { _OFFSET(l2_rx_desc_cnt[9]), 0, 0, 0, 0 }, + { _OFFSET(l2_rx_desc_cnt[10]), 0, 0, 0, 0 }, + { _OFFSET(l2_rx_desc_cnt[11]), 0, 0, 0, 0 }, + #if 0 + { _OFFSET(l2_rx_desc_cnt[12]), 0, 0, 0, 0 }, + { _OFFSET(l2_rx_desc_cnt[13]), 0, 0, 0, 0 }, + { _OFFSET(l2_rx_desc_cnt[14]), 0, 0, 0, 0 }, + { _OFFSET(l2_rx_desc_cnt[15]), 0, 0, 0, 0 }, + #endif + + /* The maximum page count is chosen to prevent us from having + * more than 32767 pending entries at any one time. */ + { _OFFSET(l2_tx_bd_page_cnt[0]), 2, 2, 1, 127 }, + { _OFFSET(l2_tx_bd_page_cnt[1]), 1, 1, 1, 127 }, + { _OFFSET(l2_tx_bd_page_cnt[2]), 1, 1, 1, 127 }, + { _OFFSET(l2_tx_bd_page_cnt[3]), 1, 1, 1, 127 }, + { _OFFSET(l2_tx_bd_page_cnt[4]), 1, 1, 1, 127 }, + { _OFFSET(l2_tx_bd_page_cnt[5]), 1, 1, 1, 127 }, + { _OFFSET(l2_tx_bd_page_cnt[6]), 1, 1, 1, 127 }, + { _OFFSET(l2_tx_bd_page_cnt[7]), 1, 1, 1, 127 }, + { _OFFSET(l2_tx_bd_page_cnt[8]), 1, 1, 1, 127 }, + { _OFFSET(l2_tx_bd_page_cnt[9]), 1, 1, 1, 127 }, + { _OFFSET(l2_tx_bd_page_cnt[10]), 1, 1, 1, 127 }, + { _OFFSET(l2_tx_bd_page_cnt[11]), 1, 1, 1, 127 }, + + { _OFFSET(l2_rx_bd_page_cnt[0]), 2, 2, 1, 127 }, + { _OFFSET(l2_rx_bd_page_cnt[1]), 1, 1, 1, 127 }, + { _OFFSET(l2_rx_bd_page_cnt[2]), 1, 1, 1, 127 }, + { _OFFSET(l2_rx_bd_page_cnt[3]), 1, 1, 1, 127 }, + { _OFFSET(l2_rx_bd_page_cnt[4]), 1, 1, 1, 127 }, + { _OFFSET(l2_rx_bd_page_cnt[5]), 1, 1, 1, 127 }, + { _OFFSET(l2_rx_bd_page_cnt[6]), 1, 1, 1, 127 }, + { _OFFSET(l2_rx_bd_page_cnt[7]), 1, 1, 1, 127 }, + { _OFFSET(l2_rx_bd_page_cnt[8]), 1, 1, 1, 127 }, + { _OFFSET(l2_rx_bd_page_cnt[9]), 1, 1, 1, 127 }, + { _OFFSET(l2_rx_bd_page_cnt[10]), 1, 1, 1, 127 }, + { _OFFSET(l2_rx_bd_page_cnt[11]), 1, 1, 1, 127 }, + #if 0 + { _OFFSET(l2_rx_bd_page_cnt[12]), 1, 1, 1, 127 }, + { _OFFSET(l2_rx_bd_page_cnt[13]), 1, 1, 1, 127 }, + { _OFFSET(l2_rx_bd_page_cnt[14]), 1, 1, 1, 127 }, + { _OFFSET(l2_rx_bd_page_cnt[15]), 1, 1, 1, 127 }, + #endif + + { _OFFSET(l4_tx_bd_page_cnt), 1, 1, 1, 255 }, + { _OFFSET(limit_l4_tx_bd_cnt), 0, 0, 0, 0 }, + { _OFFSET(l4_rx_bd_page_cnt), 1, 1, 1, 255 }, + { _OFFSET(limit_l4_rx_bd_cnt), 0, 0, 0, 0 }, + + #ifndef EXCLUDE_KQE_SUPPORT + #if INCLUDE_OFLD_SUPPORT + { _OFFSET(kwq_page_cnt), 4, 2, 1, 255 }, + { _OFFSET(kcq_page_cnt), 32, 32, 1, 255 }, + { _OFFSET(kcq_history_size), 0x80, 0x80, 0, 0 }, + #else + /* Kernel queues are used when RSS or TCP offload is enabled. + * When RSS is enabled, the upper module should modify the + * default settings for these parameters. */ + { _OFFSET(kwq_page_cnt), 0, 0, 0, 0 }, + { _OFFSET(kcq_page_cnt), 0, 0, 0, 0 }, + { _OFFSET(kcq_history_size), 0, 0, 0, 0 }, + #endif + + /* Connection kcqe/kwqe history. */ + { _OFFSET(con_kcqe_history_size), 0, 0, 0, 0 }, + { _OFFSET(con_kwqe_history_size), 0, 0, 0, 0 }, + #endif + + { _OFFSET(gen_bd_page_cnt), 2, 2, 1, 127 }, + { _OFFSET(max_gen_buf_cnt), 0x8000, 0x8000, 0, 0 }, + { _OFFSET(gen_buf_per_alloc), 0x4, 0x4, 0, 0 }, + + { _OFFSET(copy_buffered_data), 0, 0, 0, 0 }, + { _OFFSET(rcv_buffer_offset), 0x38, 0x38, 0, 0 }, + { _OFFSET(enable_syn_rcvq), 0, 0, 0, 0 }, + + { _OFFSET(hcopy_desc_cnt), 0, 0, 0, 0 }, + { _OFFSET(hcopy_bd_page_cnt), 2, 2, 1, 127 }, + { _OFFSET(buffered_kcqe_cnt), 0x80, 0x80, 0, 0 }, + + { _OFFSET(deferred_kcqe_cnt), 0x100, 0x100, 0, 0 }, + + { _OFFSET(test_mode), 0x60, 0x60, 0, 0 }, + { _OFFSET(ofld_cap), 0, 0, 0, 0 }, + { _OFFSET(wol_cap), 0, 0, 0, 0 }, + { _OFFSET(flow_ctrl_cap), 0, 0, 0, 0 }, + { _OFFSET(req_medium), 0, 0, 0, 0xfffff }, + { _OFFSET(selective_autoneg), 0, 0, 0, 0 }, + { _OFFSET(wire_speed), 1, 0, 0, 0 }, + { _OFFSET(phy_addr), 1, 0, 0, 0 }, + { _OFFSET(phy_int_mode), 2, 2, 0, 0 }, + { _OFFSET(link_chng_mode), 2, 2, 0, 0 }, + + { _OFFSET(hc_timer_mode), 0, 0, 0, 0 }, + { _OFFSET(ind_comp_limit), 200, 100, 0, 0 }, + { _OFFSET(tx_quick_cons_trip_int), 3, 10, 0, 0 }, + { _OFFSET(tx_quick_cons_trip), 3, 30, 0, 0 }, + { _OFFSET(tx_ticks_int), 30, 10, 0, 0 }, + { _OFFSET(tx_ticks), 60, 200, 0, 0 }, + { _OFFSET(rx_quick_cons_trip_int), 1, 3, 0, 0 }, + { _OFFSET(rx_quick_cons_trip), 2, 1, 0, 0 }, + { _OFFSET(rx_ticks_int), 15, 5, 0, 0 }, + { _OFFSET(rx_ticks), 45, 1, 0, 0 }, + { _OFFSET(comp_prod_trip_int), 2, 3, 0, 0 }, + { _OFFSET(comp_prod_trip), 4, 1, 0, 0 }, + { _OFFSET(com_ticks_int), 64, 5, 0, 0 }, + { _OFFSET(com_ticks), 220, 1, 0, 0 }, + { _OFFSET(cmd_ticks_int), 64, 5, 0, 0 }, + { _OFFSET(cmd_ticks), 220, 1, 0, 0 }, + { _OFFSET(stats_ticks), 1000000, 1000000, 0, 0 }, + + /* Xinan per-processor HC configuration. */ + { _OFFSET(psb_tx_cons_trip), 0x100010,0x100010,0, 0 }, + { _OFFSET(psb_tx_ticks), 0x100040,0x100040,0, 0 }, + { _OFFSET(psb_rx_cons_trip), 0x100010,0x100010,0, 0 }, + { _OFFSET(psb_rx_ticks), 0x80020, 0x80020, 0, 0 }, + { _OFFSET(psb_comp_prod_trip), 0x80008, 0x80008, 0, 0 }, + { _OFFSET(psb_com_ticks), 0x400040,0x400040,0, 0 }, + { _OFFSET(psb_cmd_ticks), 0x400040,0x400040,0, 0 }, + { _OFFSET(psb_period_ticks), 0, 0, 0, 0 }, + + { _OFFSET(enable_fir), 1, 1, 0, 0 }, + { _OFFSET(num_rchans), 5, 5, 0, 0 }, + { _OFFSET(num_wchans), 3, 3, 0, 0 }, + + /* One some system, with one_tdma disabled, we will get data + * corruption. Currently this looks like a chipset bug. The + * chip group will continue to look into this. So for now, we + * will enable one_tdma for all chip revisions. */ + { _OFFSET(one_tdma), 0, 0, 0, 0 }, + + { _OFFSET(ping_pong_dma), 0, 0, 0, 0 }, + { _OFFSET(tmr_reload_value1), 0x6c627970, 0, 0, 0 }, + { _OFFSET(keep_vlan_tag), 0, 0, 0, 0 }, + + { _OFFSET(enable_remote_phy), 0, 0, 0, 0 }, + { _OFFSET(rphy_req_medium), 0, 0, 0, 0 }, + { _OFFSET(rphy_flow_ctrl_cap), 0, 0, 0, 0 }, + { _OFFSET(rphy_selective_autoneg), 0, 0, 0, 0 }, + { _OFFSET(rphy_wire_speed), 1, 0, 0, 0 }, + + { _OFFSET(bin_mq_mode), 0, 0, 0, 0 }, + { _OFFSET(validate_l4_data), 0, 0, 0, 0 }, + { _OFFSET(disable_pcie_nfr), 0, 0, 0, 0 }, + { _OFFSET(fw_flow_control), 0, 0, 0, 0 }, + { _OFFSET(fw_flow_control_wait), 0xffff, 0xffff, 0, 0xffff }, + { _OFFSET(ena_large_grc_timeout), 0, 0, 0, 0 }, + { _OFFSET(flow_control_reporting_mode), 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0 } + }; + + lm_status_t lm_status; + param_entry_t *param; + u32_t val; + + DbgMessage(pdev, INFORMi, "### lm_get_dev_info\n"); + + /* Get PCI device and vendor id. */ + lm_status = mm_read_pci( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_vendor_id), + &val); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + pdev->hw_info.vid = (u16_t) val; + DbgMessage1(pdev, INFORMi, "vid 0x%x\n", pdev->hw_info.vid); + + pdev->hw_info.did = (u16_t) (val >> 16); + DbgMessage1(pdev, INFORMi, "did 0x%x\n", pdev->hw_info.did); + + /* Get subsystem and subvendor id. */ + lm_status = mm_read_pci( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_subsystem_vendor_id), + &val); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + pdev->hw_info.svid = (u16_t) val; + DbgMessage1(pdev, INFORMi, "svid 0x%x\n", pdev->hw_info.svid); + + pdev->hw_info.ssid = (u16_t) (val >> 16); + DbgMessage1(pdev, INFORMi, "ssid 0x%x\n", pdev->hw_info.ssid); + + /* Get IRQ, and interrupt pin. */ + lm_status = mm_read_pci( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_int_line), + &val); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + pdev->hw_info.irq = (u8_t) val; + DbgMessage1(pdev, INFORMi, "IRQ 0x%x\n", pdev->hw_info.irq); + + pdev->hw_info.int_pin = (u8_t) (val >> 8); + DbgMessage1(pdev, INFORMi, "Int pin 0x%x\n", pdev->hw_info.int_pin); + + /* Get cache line size. */ + lm_status = mm_read_pci( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_cache_line_size), + &val); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + pdev->hw_info.cache_line_size = (u8_t) val; + DbgMessage1(pdev, INFORMi, "Cache line size 0x%x\n", (u8_t) val); + + pdev->hw_info.latency_timer = (u8_t) (val >> 8); + DbgMessage1(pdev, INFORMi, "Latency timer 0x%x\n", (u8_t) (val >> 8)); + + /* Get PCI revision id. */ + lm_status = mm_read_pci( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_class_code), + &val); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + pdev->hw_info.rev_id = (u8_t) val; + DbgMessage1(pdev, INFORMi, "Revision id 0x%x\n", pdev->hw_info.rev_id); + + /* Get the base address. */ + lm_status = mm_read_pci( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_bar_1), + &val); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + +#ifndef CONFIG_PPC64 + pdev->hw_info.mem_base.as_u32.low = val & 0xfffffff0; +#endif + + DbgMessage1(pdev, INFORMi, "Mem base low 0x%x\n", pdev->hw_info.mem_base.as_u32.low); + + val = 0; + + lm_status = mm_read_pci( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_bar_2), + &val); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + +#ifndef CONFIG_PPC64 + pdev->hw_info.mem_base.as_u32.high = val; +#endif + + DbgMessage1(pdev, INFORMi, "Mem base high 0x%x\n", + pdev->hw_info.mem_base.as_u32.high); + + /* Enable PCI bus master. This is supposed to be enabled by the + * BIOS, however, BIOS on older systems may not set this bit. */ + lm_status = mm_read_pci( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_command), + &val); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + /* Error out if memory map is NOT enabled. This could occur if the + * BIOS is not able to reserve an address range for the device. */ + if(!(val & PCICFG_COMMAND_MEM_SPACE)) + { + DbgBreakMsg("MEM_SPACE not enabled.\n"); + + return LM_STATUS_FAILURE; + } + + val |= PCICFG_COMMAND_BUS_MASTER; + + lm_status = mm_write_pci( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_command), + val); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + /* Configure byte swap and enable write to the reg_window registers. */ + val = PCICFG_MISC_CONFIG_REG_WINDOW_ENA | + PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; + lm_status = mm_write_pci( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_misc_config), + val); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + /* Get the bar size at register 0x408 via PCI configuration indirect. */ + lm_status = mm_write_pci( + pdev, + OFFSETOF(pci_config_t, pcicfg_reg_window_address), + OFFSETOF(reg_space_t, pci.pci_config_2)); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + lm_status = mm_read_pci( + pdev, + OFFSETOF(pci_config_t, pcicfg_reg_window), + &val); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + val &= PCI_CONFIG_2_BAR1_SIZE; + if(val == PCI_CONFIG_2_BAR1_SIZE_DISABLED || + val > PCI_CONFIG_2_BAR1_SIZE_1G) + { + DbgBreakMsg("Invalid bar size.\n"); + + return LM_STATUS_FAILURE; + } + + pdev->hw_info.bar_size = 1 << (val+15); + DbgMessage1(pdev, INFORM, "bar_size 0x%x\n", pdev->hw_info.bar_size); + + /* Map memory base to system address space. */ + pdev->vars.regview = (reg_space_t *) mm_map_io_base( + pdev, + pdev->hw_info.mem_base, + pdev->hw_info.bar_size); + if(pdev->vars.regview == NULL) + { + return LM_STATUS_FAILURE; + } + DbgMessage1(pdev, INFORMi, "Mapped base %p\n", pdev->vars.regview); + + #if DBG + /* Make sure byte swapping is properly configured. */ + REG_RD(pdev, pci.pci_swap_diag0, &val); + + DbgBreakIf(val != 0x1020304); + #endif + + /* Get the chip revision id and number. */ + REG_RD(pdev, misc.misc_id, &pdev->hw_info.chip_id); + DbgMessage1(pdev, INFORMi, "chip id 0x%x\n", pdev->hw_info.chip_id); + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + pdev->hw_info.bus_mode = BUS_MODE_PCIE; + } + else + { + /* Get bus information. */ + REG_RD(pdev, pci_config.pcicfg_misc_status, &val); + + if(val & PCICFG_MISC_STATUS_32BIT_DET) + { + pdev->hw_info.bus_width = BUS_WIDTH_32_BIT; + DbgMessage(pdev, INFORM, "32bit bus width.\n"); + } + else + { + pdev->hw_info.bus_width = BUS_WIDTH_64_BIT; + DbgMessage(pdev, INFORM, "64bit bus width.\n"); + } + + if(val & PCICFG_MISC_STATUS_PCIX_DET) + { + pdev->hw_info.bus_mode = BUS_MODE_PCIX; + DbgMessage(pdev, INFORM, "PCIX bus detected.\n"); + + REG_RD(pdev, pci_config.pcicfg_pci_clock_control_bits, &val); + switch(val & PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET) + { + case PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: + pdev->hw_info.bus_speed = BUS_SPEED_133_MHZ; + DbgMessage(pdev, INFORM, "Bus speed is 133Mhz.\n"); + break; + + case PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: + pdev->hw_info.bus_speed = BUS_SPEED_100_MHZ; + DbgMessage(pdev, INFORM, "Bus speed is 100Mhz.\n"); + break; + + case PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: + case PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: + pdev->hw_info.bus_speed = BUS_SPEED_66_MHZ; + DbgMessage(pdev, INFORM, "Bus speed is 66Mhz.\n"); + break; + + case PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: + case PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: + pdev->hw_info.bus_speed = BUS_SPEED_50_MHZ; + DbgMessage(pdev, INFORM, "Bus speed is 50Mhz.\n"); + break; + + case PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET: + case PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: + case PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: + default: + pdev->hw_info.bus_speed = BUS_SPEED_33_MHZ; + DbgMessage(pdev, INFORM, "Bus speed is 33Mhz.\n"); + break; + } + } + else + { + pdev->hw_info.bus_mode = BUS_MODE_PCI; + DbgMessage(pdev, INFORM, "Conventional PCI bus detected.\n"); + + if(val & PCICFG_MISC_STATUS_M66EN) + { + pdev->hw_info.bus_speed = BUS_SPEED_66_MHZ; + DbgMessage(pdev, INFORM, "Bus speed is 66Mhz.\n"); + } + else + { + pdev->hw_info.bus_speed = BUS_SPEED_33_MHZ; + DbgMessage(pdev, INFORM, "Bus speed is 33Mhz.\n"); + } + } + } + + if(CHIP_ID(pdev) == CHIP_ID_5706_A0 || CHIP_ID(pdev) == CHIP_ID_5706_A1) + { + REG_RD_OFFSET( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_command), + &val); + + /* 5706A0 may falsely detect SERR and PERR. */ + if(CHIP_ID(pdev) == CHIP_ID_5706_A0) + { + val &= ~(PCICFG_COMMAND_SERR_ENA | PCICFG_COMMAND_PERR_ENA); + } + + /* 5706A1 PCI 64-bit. */ + else if(pdev->hw_info.bus_mode == BUS_MODE_PCI && + pdev->hw_info.bus_width == BUS_WIDTH_64_BIT) + { + /* E4_5706A1_577: PERR IS INCORRECTLY GENERATED IN PCI 64-BIT. + Description: If the data on the upper AD and CBE busses + do not match the parity of PAR64 during a 32-bit target + access, a parity error is incorrectly generated. This + happens only after a 64-bit master DMA operation has been + done by the chip. + Scope: All PCI 64-bit systems. + Impact: Ability to indicate a real parity error is lost. + Workaround: Driver needs to clear PERR_EN. */ + val &= ~PCICFG_COMMAND_PERR_ENA; + } + + REG_WR_OFFSET( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_command), + val); + } + else if(CHIP_ID(pdev) == CHIP_ID_5708_A0) + { + /* 5708A0 errata. */ + REG_RD_OFFSET( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_command), + &val); + + val &= ~(PCICFG_COMMAND_SERR_ENA | PCICFG_COMMAND_PERR_ENA); + + REG_WR_OFFSET( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_command), + val); + } + + /* Get the EPB info. */ + if(CHIP_NUM(pdev) == CHIP_NUM_5708) + { + REG_RD_IND(pdev, 0x240000+0x18, &val); + pdev->hw_info.pcie_bus_num = (u8_t) val; + + REG_RD_IND(pdev, 0x240000+0x6c, &val); + pdev->hw_info.pcie_max_width = (u8_t) ((val & 0x3f0) >> 4); + + switch(val & 0xf) + { + case 1: + pdev->hw_info.pcie_max_speed = PCIE_SPEED_2_5_G; + break; + + default: + pdev->hw_info.pcie_max_speed = 0; + break; + } + + REG_RD_IND(pdev, 0x240000+0x70, &val); + pdev->hw_info.pcie_width = (u8_t) ((val & 0x3f00000) >> 20); + + switch(val & 0xf0000) + { + case 0x10000: + pdev->hw_info.pcie_speed = PCIE_SPEED_2_5_G; + break; + + default: + pdev->hw_info.pcie_speed = 0; + break; + } + } + else if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + REG_RD(pdev, pci_config.pcicfg_link_capability, &val); + pdev->hw_info.pcie_max_width = + (u8_t) ((val & PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH) >> 4); + switch (val & PCICFG_LINK_CAPABILITY_MAX_LINK_SPEED) + { + case PCICFG_LINK_CAPABILITY_MAX_LINK_SPEED_5: + pdev->hw_info.pcie_max_speed = PCIE_SPEED_5_G; + break; + case PCICFG_LINK_CAPABILITY_MAX_LINK_SPEED_2_5: + pdev->hw_info.pcie_max_speed = PCIE_SPEED_2_5_G; + break; + default: + pdev->hw_info.pcie_max_speed = 0; + break; + } + + REG_RD(pdev, pci_config.pcicfg_link_status, &val); + pdev->hw_info.pcie_width = + (u8_t) ((val & PCICFG_LINK_STATUS_NEG_LINK_WIDTH) >> 4); + switch (val & PCICFG_LINK_STATUS_SPEED) + { + case PCICFG_LINK_CAPABILITY_MAX_LINK_SPEED_5: + pdev->hw_info.pcie_speed = PCIE_SPEED_5_G; + break; + case PCICFG_LINK_CAPABILITY_MAX_LINK_SPEED_2_5: + pdev->hw_info.pcie_speed = PCIE_SPEED_2_5_G; + break; + default: + pdev->hw_info.pcie_speed = 0; + break; + } + + REG_RD_IND(pdev, OFFSETOF(reg_space_t, mcp.mcp_toe_id), &val); + if(val & MCP_TOE_ID_FUNCTION_ID) + { + pdev->hw_info.mac_id = 1; + } + } + + /* Get firmware share memory base address. */ + REG_RD_IND( + pdev, + MCP_SCRATCHPAD_START + OFFSETOF(shm_hdr_t, shm_hdr_signature), + &val); + if((val & SHM_ADDR_SIGN_MASK) == SHM_ADDR_SIGNATURE) + { + REG_RD_IND( + pdev, + MCP_SCRATCHPAD_START + + OFFSETOF(shm_hdr_t, shm_addr[pdev->hw_info.mac_id]), + &pdev->hw_info.shmem_base); + } + else + { + /* Pre v1.3.2 bootcode. */ + pdev->hw_info.shmem_base = HOST_VIEW_SHMEM_BASE; + } + + /* Get the hw config word. */ + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, dev_info.shared_hw_config.config), + &val); + pdev->hw_info.nvm_hw_config = val; + + get_max_conns( + pdev, + &pdev->hw_info.max_toe_conn, + &pdev->hw_info.max_iscsi_conn, + &pdev->hw_info.max_iscsi_pending_tasks); + + /* Get the permanent MAC address. */ + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, dev_info.port_hw_config.mac_upper), + &val); + pdev->hw_info.mac_addr[0] = (u8_t) (val >> 8); + pdev->hw_info.mac_addr[1] = (u8_t) val; + + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, dev_info.port_hw_config.mac_lower), + &val); + + pdev->hw_info.mac_addr[2] = (u8_t) (val >> 24); + pdev->hw_info.mac_addr[3] = (u8_t) (val >> 16); + pdev->hw_info.mac_addr[4] = (u8_t) (val >> 8); + pdev->hw_info.mac_addr[5] = (u8_t) val; + + /* Get iSCSI MAC address. */ + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF( + shmem_region_t, + dev_info.port_hw_config.iscsi_mac_upper), + &val); + pdev->hw_info.iscsi_mac_addr[0] = (u8_t) (val >> 8); + pdev->hw_info.iscsi_mac_addr[1] = (u8_t) val; + + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF( + shmem_region_t, + dev_info.port_hw_config.iscsi_mac_lower), + &val); + pdev->hw_info.iscsi_mac_addr[2] = (u8_t) (val >> 24); + pdev->hw_info.iscsi_mac_addr[3] = (u8_t) (val >> 16); + pdev->hw_info.iscsi_mac_addr[4] = (u8_t) (val >> 8); + pdev->hw_info.iscsi_mac_addr[5] = (u8_t) val; + + DbgMessage6(pdev, INFORM, "mac addr: %02x %02x %02x %02x %02x %02x\n", + pdev->hw_info.mac_addr[0], + pdev->hw_info.mac_addr[1], + pdev->hw_info.mac_addr[2], + pdev->hw_info.mac_addr[3], + pdev->hw_info.mac_addr[4], + pdev->hw_info.mac_addr[5]); + + DbgBreakIf(LM_DRIVER_MAJOR_VER > 255); + DbgBreakIf(LM_DRIVER_MINOR_VER > 255); + DbgBreakIf(LM_DRIVER_REL_NUM > 255); + DbgBreakIf(LM_DRIVER_FIX_NUM > 255); + + pdev->ver_num = + (LM_DRIVER_MAJOR_VER << 24) | + (LM_DRIVER_MINOR_VER << 16) | + (LM_DRIVER_REL_NUM << 8) | + LM_DRIVER_FIX_NUM; + + (void) build_ver_string( + (char *)pdev->ver_str, + sizeof(pdev->ver_str), + LM_DRIVER_MAJOR_VER, + LM_DRIVER_MINOR_VER, + LM_DRIVER_REL_NUM, + LM_DRIVER_FIX_NUM); + + pdev->params.mac_addr[0] = pdev->hw_info.mac_addr[0]; + pdev->params.mac_addr[1] = pdev->hw_info.mac_addr[1]; + pdev->params.mac_addr[2] = pdev->hw_info.mac_addr[2]; + pdev->params.mac_addr[3] = pdev->hw_info.mac_addr[3]; + pdev->params.mac_addr[4] = pdev->hw_info.mac_addr[4]; + pdev->params.mac_addr[5] = pdev->hw_info.mac_addr[5]; + + /* Initialize the default parameters. */ + param = param_list; + while(param->offset) + { + if(CHIP_REV(pdev) == CHIP_REV_FPGA || CHIP_REV(pdev) == CHIP_REV_IKOS) + { + SET_PARAM_VAL(pdev, param, param->fpga_ikos_default); + } + else + { + SET_PARAM_VAL(pdev, param, param->asic_default); + } + + param++; + } + + if(CHIP_REV(pdev) == CHIP_REV_FPGA || CHIP_REV(pdev) == CHIP_REV_IKOS) + { + pdev->params.test_mode |= TEST_MODE_INIT_GEN_BUF_DATA; + pdev->params.test_mode |= TEST_MODE_SAVE_DUMMY_DMA_DATA; + pdev->params.test_mode |= TEST_MODE_IGNORE_SHMEM_SIGNATURE; + pdev->params.test_mode |= TEST_MODE_DRIVER_PULSE_ALWAYS_ALIVE; + } + + /* Some chipsets are not capabable of handling multiple + * read requests. Currently we will get data corrupt on + * Intel 840/860 chipset when one_tdma is not enabled. */ + if(pdev->hw_info.bus_mode == BUS_MODE_PCI) + { + if((CHIP_NUM(pdev)==CHIP_NUM_5706 || CHIP_NUM(pdev)==CHIP_NUM_5708) && + (CHIP_REV(pdev)==CHIP_REV_FPGA || CHIP_REV(pdev)==CHIP_REV_IKOS)) + { + pdev->params.ping_pong_dma = FALSE; + } + else + { + pdev->params.ping_pong_dma = TRUE; + } + } + else + { + pdev->params.ping_pong_dma = FALSE; + } + + /* Get the pre-emphasis. */ + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, dev_info.port_hw_config.config), + &pdev->params.serdes_pre_emphasis); + pdev->params.serdes_pre_emphasis &= PORT_HW_CFG_SERDES_TXCTL3_MASK; + + /* This should be fixed in A1. */ + if(CHIP_ID(pdev) == CHIP_ID_5706_A0) + { + if(pdev->hw_info.bus_mode == BUS_MODE_PCIX && + pdev->hw_info.bus_speed == BUS_SPEED_133_MHZ) + { + pdev->params.num_rchans = 1; + } + } + + #if defined(DBG) && !defined(EXCLUDE_KQE_SUPPORT) + pdev->params.con_kcqe_history_size = 256; + pdev->params.con_kwqe_history_size = 256; + #endif + + if(CHIP_NUM(pdev) == CHIP_NUM_5708 || CHIP_NUM(pdev) == CHIP_NUM_5709) + { + if(lm_get_medium(pdev) == LM_MEDIUM_TYPE_FIBER) + { + pdev->params.phy_addr = 2; + } + } + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + pdev->params.bin_mq_mode = TRUE; + } + + DbgBreakIf(NUM_RX_CHAIN != NUM_TX_CHAIN); + + pdev->rx_info.num_rxq = NUM_RX_CHAIN; + pdev->tx_info.num_txq = NUM_TX_CHAIN; + pdev->tx_info.cu_idx = TX_CHAIN_IDX1; + + /* see if remote phy is enabled. */ + if(CHIP_REV(pdev) != CHIP_REV_IKOS) + { + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, + dev_info.port_feature_config.config), + &val); + if(val & PORT_FEATURE_RPHY_ENABLED) + { + pdev->params.enable_remote_phy = 1; + } + } + + if (CHIP_NUM(pdev) == CHIP_NUM_5706 || + CHIP_NUM(pdev) == CHIP_NUM_5708) + { + // Due to slower speed of RV2P in Teton, we need to limit max + // number of BD per each end bit. Otherwise, Appscan in RV2P + // would spend excessive time scanning for end bit. + pdev->params.limit_l4_rx_bd_cnt = 110; + } + + /* Override the defaults with user configurations. */ + lm_status = mm_get_user_config(pdev); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + /* Make sure share memory is initialized by the firmware. If not + * fail initialization. The check here is a little late as we + * have already read some share memory info above. This is ok. */ + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, dev_info.signature), + &val); + if((val & DEV_INFO_SIGNATURE_MASK) != DEV_INFO_SIGNATURE) + { + if(!(pdev->params.test_mode & TEST_MODE_IGNORE_SHMEM_SIGNATURE)) + { + DbgBreakMsg("Shmem signature not present.\n"); + + return LM_STATUS_BAD_SIGNATURE; + } + + pdev->hw_info.mac_addr[0] = 0x00; + pdev->hw_info.mac_addr[1] = 0x10; + pdev->hw_info.mac_addr[2] = 0x18; + pdev->hw_info.mac_addr[3] = 0xff; + pdev->hw_info.mac_addr[4] = 0xff; + pdev->hw_info.mac_addr[5] = 0xff; + + pdev->hw_info.iscsi_mac_addr[0] = 0x00; + pdev->hw_info.iscsi_mac_addr[1] = 0x10; + pdev->hw_info.iscsi_mac_addr[2] = 0x18; + pdev->hw_info.iscsi_mac_addr[3] = 0xff; + pdev->hw_info.iscsi_mac_addr[4] = 0xff; + pdev->hw_info.iscsi_mac_addr[5] = 0xfe; + } + + /* Make sure the parameter values are within range. */ + param = param_list; + while(param->offset) + { + if(param->min != 0 || param->max != 0) + { + if(PARAM_VAL(pdev, param) < param->min || + PARAM_VAL(pdev, param) > param->max) + { + if(CHIP_REV(pdev) == CHIP_REV_FPGA || + CHIP_REV(pdev) == CHIP_REV_IKOS) + { + SET_PARAM_VAL(pdev, param, param->fpga_ikos_default); + } + else + { + SET_PARAM_VAL(pdev, param, param->asic_default); + } + } + } + + param++; + } + + /* params.mtu read from the registry does not include the MAC header + * size. We need to add the header here. */ + /* + * get_vbd_params does this aleady + * pdev->params.mtu += ETHERNET_PACKET_HEADER_SIZE; + */ + + #ifndef EXCLUDE_KQE_SUPPORT + /* The size of the kcq histroy. This is the number entries that will + * not be over written by the chip. */ + if(pdev->params.kcq_history_size > (LM_PAGE_SIZE/sizeof(kcqe_t)) * + pdev->params.kcq_page_cnt - 1) + { + pdev->params.kcq_history_size = ((LM_PAGE_SIZE/sizeof(kcqe_t)) * + pdev->params.kcq_page_cnt) / 2; + } + #endif + + /* XXX: Exception for Xinan, need a permanent fix. */ + if (CHIP_NUM(pdev) == CHIP_NUM_5709) + { + pdev->params.rcv_buffer_offset = 0; + } + + /* Check for a valid mac address. */ + if((pdev->params.mac_addr[0] == 0 && + pdev->params.mac_addr[1] == 0 && + pdev->params.mac_addr[2] == 0 && + pdev->params.mac_addr[3] == 0 && + pdev->params.mac_addr[4] == 0 && + pdev->params.mac_addr[5] == 0) || (pdev->params.mac_addr[0] & 1)) + { + DbgMessage(pdev, WARN, "invalid LAA.\n"); + + pdev->params.mac_addr[0] = pdev->hw_info.mac_addr[0]; + pdev->params.mac_addr[1] = pdev->hw_info.mac_addr[1]; + pdev->params.mac_addr[2] = pdev->hw_info.mac_addr[2]; + pdev->params.mac_addr[3] = pdev->hw_info.mac_addr[3]; + pdev->params.mac_addr[4] = pdev->hw_info.mac_addr[4]; + pdev->params.mac_addr[5] = pdev->hw_info.mac_addr[5]; + } + + /* There is a bug in HC that will cause it to stop updating the + * status block. This has been shown on some system with L4 traffic + * goinging. To workaround this, the trip points and interrupt trip + * points must be the same and the statistics DMA must be disabled. */ + if(CHIP_ID(pdev) == CHIP_ID_5706_A0) + { + pdev->params.tx_quick_cons_trip_int = pdev->params.tx_quick_cons_trip; + pdev->params.tx_ticks_int = pdev->params.tx_ticks; + pdev->params.rx_quick_cons_trip_int = pdev->params.rx_quick_cons_trip; + pdev->params.rx_ticks_int = pdev->params.rx_ticks; + pdev->params.comp_prod_trip_int = pdev->params.comp_prod_trip; + pdev->params.com_ticks_int = pdev->params.com_ticks; + pdev->params.cmd_ticks_int = pdev->params.cmd_ticks; + pdev->params.stats_ticks = 0; + } + + /* enable_syn_rcvd will direct all tcp segments with syn bit to rxq 1. */ + if(pdev->params.enable_syn_rcvq && + NUM_RX_CHAIN > 1 && + pdev->params.l2_rx_desc_cnt[1] == 0) + { + pdev->params.l2_rx_desc_cnt[1] = 60; + } + + /* Timer mode is broken is 5706_A0 and 5706_A1. */ + if(CHIP_ID(pdev) == CHIP_ID_5706_A0 || CHIP_ID(pdev) == CHIP_ID_5706_A1) + { + pdev->params.hc_timer_mode = HC_COLLECT_MODE; + } + + /* Get the current fw_wr_seq. */ + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + OFFSETOF(shmem_region_t, drv_fw_mb.fw_mb), + &val); + pdev->vars.fw_wr_seq = val & DRV_MSG_SEQ; + + /* see if firmware is remote phy capable. */ + if(pdev->params.enable_remote_phy) + { + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, drv_fw_cap_mb.fw_cap_mb), + &val); + if((val & CAPABILITY_SIGNATURE_MASK) != FW_CAP_SIGNATURE || + (val & FW_CAP_REMOTE_PHY_CAPABLE) == 0) + { + pdev->params.enable_remote_phy = 0; + } + } + + return LM_STATUS_SUCCESS; +} /* lm_get_dev_info */ + + + +#ifndef EXCLUDE_KQE_SUPPORT +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +init_kwq_resc( + lm_device_t *pdev) +{ + u32_t mem_size; + + if(pdev->params.kwq_page_cnt == 0) + { + return LM_STATUS_SUCCESS; + } + + /* Allocate memory for the page table which does not need to be + * page aligned. However the size must be multiple of page size. + * + * When initialized, the page table will point to the pages + * used for the kernel work queue. */ + mem_size = pdev->params.kwq_page_cnt * sizeof(lm_address_t); + mem_size = (mem_size + LM_PAGE_MASK) & ~LM_PAGE_MASK; + + pdev->kq_info.kwq_pgtbl_virt = mm_alloc_phys_mem( + pdev, + mem_size, + &pdev->kq_info.kwq_pgtbl_phy, + PHYS_MEM_TYPE_NONCACHED, + NULL); + if(pdev->kq_info.kwq_pgtbl_virt == NULL) + { + return LM_STATUS_RESOURCE; + } + + DbgBreakIf(pdev->kq_info.kwq_pgtbl_phy.as_u32.low & CACHE_LINE_SIZE_MASK); + + /* Allocate memory for the kernel work queue. Here we allocate + * a physically continuous block of memory and then initialize the + * page table to pointer to the pages in this block. + * + * The kernel work queue is used by the driver similiar to a + * circular ring. + * + * The memory block must be page aligned. */ + mem_size = LM_PAGE_SIZE * pdev->params.kwq_page_cnt; + pdev->kq_info.kwq_virt = (kwqe_t *) mm_alloc_phys_mem( + pdev, + mem_size, + &pdev->kq_info.kwq_phy, + PHYS_MEM_TYPE_NONCACHED, + NULL); + if(pdev->kq_info.kwq_virt == NULL) + { + return LM_STATUS_RESOURCE; + } + + DbgBreakIf(pdev->kq_info.kwq_phy.as_u32.low & CACHE_LINE_SIZE_MASK); + DbgBreakIf(((u8_t *) pdev->kq_info.kwq_virt - (u8_t *) 0) & LM_PAGE_MASK); + + return LM_STATUS_SUCCESS; +} /* init_kwq_resc */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +init_kcq_resc( + lm_device_t *pdev) +{ + + u32_t mem_size; + + if(pdev->params.kcq_page_cnt == 0) + { + return LM_STATUS_SUCCESS; + } + + /* Allocate memory for the page table which does not need to be + * page aligned. However the size must be multiple of page size. + * + * When initialized, the page table will point to the pages + * used for the kernel completion queue. */ + mem_size = pdev->params.kcq_page_cnt * sizeof(lm_address_t); + mem_size = (mem_size + LM_PAGE_MASK) & ~LM_PAGE_MASK; + + pdev->kq_info.kcq_pgtbl_virt = mm_alloc_phys_mem( + pdev, + mem_size, + &pdev->kq_info.kcq_pgtbl_phy, + PHYS_MEM_TYPE_NONCACHED, + NULL); + if(pdev->kq_info.kcq_pgtbl_virt == NULL) + { + return LM_STATUS_RESOURCE; + } + + DbgBreakIf(pdev->kq_info.kcq_pgtbl_phy.as_u32.low & CACHE_LINE_SIZE_MASK); + + /* Allocate memory for the kernel completion queue. Here we allocate + * a physically continuous block of memory and then initialize the + * page table to pointer to the pages in this block. + * + * The kernel completion queue is used by the driver similiar to a + * circular ring. + * + * The memory block must be page aligned. */ + mem_size = LM_PAGE_SIZE * pdev->params.kcq_page_cnt; + + pdev->kq_info.kcq_virt = (kcqe_t *) mm_alloc_phys_mem( + pdev, + mem_size, + &pdev->kq_info.kcq_phy, + PHYS_MEM_TYPE_NONCACHED, + NULL); + if(pdev->kq_info.kcq_virt == NULL) + { + return LM_STATUS_RESOURCE; + } + + DbgBreakIf(pdev->kq_info.kcq_phy.as_u32.low & CACHE_LINE_SIZE_MASK); + DbgBreakIf(((u8_t *) pdev->kq_info.kcq_virt - (u8_t *) 0) & LM_PAGE_MASK); + + return LM_STATUS_SUCCESS; +} /* init_kcq_resc */ +#endif /* EXCLUDE_KQE_SUPPORT */ + + + +#if INCLUDE_OFLD_SUPPORT +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +init_ofld_resc( + lm_device_t *pdev) +{ + lm_offload_info_t *ofld; + u32_t mem_size; + u32_t idx; + + ofld = &pdev->ofld; + ofld->pdev = pdev; + ofld->pg_cid_hnd_info.max_pending_pg_oflds = 16; + ofld->pg_cid_hnd_info.pending_pg_ofld_cnt = 0; + + s_list_init(&ofld->active_req_list, NULL, NULL, 0); + s_list_init(&ofld->upload_req_list, NULL, NULL, 0); + + for(idx = 0; idx < STATE_BLOCK_CNT; idx++) + { + d_list_init(&ofld->state_blks[idx].tcp_list, NULL, NULL, 0); + d_list_init(&ofld->state_blks[idx].path_list, NULL, NULL, 0); + d_list_init(&ofld->state_blks[idx].neigh_list, NULL, NULL, 0); + + ofld->state_blks[idx].max_conn = 0xffffffff; + + ofld->state_blks[idx].state_block_idx = idx; + ofld->state_blks[idx].ofld = ofld; + + ofld->state_blks[idx].params.ticks_per_second = 100; + ofld->state_blks[idx].params.ack_frequency = 2; + ofld->state_blks[idx].params.delayed_ack_ticks = 20; + ofld->state_blks[idx].params.max_retx = 10; + ofld->state_blks[idx].params.doubt_reachability_retx = 8; + ofld->state_blks[idx].params.sws_prevention_ticks = 10; + ofld->state_blks[idx].params.dup_ack_threshold = 3; + ofld->state_blks[idx].params.push_ticks = 20; + ofld->state_blks[idx].params.nce_stale_ticks = 20; + ofld->state_blks[idx].params.starting_ip_id = 0x8000; + } + + /* Allocate memory for the generic buffer chain. */ + mem_size = LM_PAGE_SIZE * pdev->params.gen_bd_page_cnt; + ofld->gen_chain.bd_chain_virt = (rx_bd_t *) mm_alloc_phys_mem( + pdev, + mem_size, + &ofld->gen_chain.bd_chain_phy, + PHYS_MEM_TYPE_UNSPECIFIED, + NULL); + if(ofld->gen_chain.bd_chain_virt == NULL) + { + return LM_STATUS_RESOURCE; + } + + DbgBreakIf(ofld->gen_chain.bd_chain_phy.as_u32.low & CACHE_LINE_SIZE_MASK); + + ofld->gen_chain.cid_addr = GET_CID_ADDR(GEN_CHAIN_CID); + + s_list_init(&ofld->gen_chain.block_list, NULL, NULL, 0); + s_list_init(&ofld->gen_chain.free_gen_buf_list, NULL, NULL, 0); + s_list_init(&ofld->gen_chain.active_gen_buf_list, NULL, NULL, 0); + + /* Allocate memory for the hcopy chain. */ + if(pdev->params.hcopy_desc_cnt) + { + mem_size = LM_PAGE_SIZE * pdev->params.hcopy_bd_page_cnt; + ofld->hcopy_chain.bd_chain_virt =(tx_bd_t *) mm_alloc_phys_mem( + pdev, + mem_size, + &ofld->hcopy_chain.bd_chain_phy, + PHYS_MEM_TYPE_UNSPECIFIED, + NULL); + if(ofld->hcopy_chain.bd_chain_virt == NULL) + { + return LM_STATUS_RESOURCE; + } + + DbgBreakIf(ofld->hcopy_chain.bd_chain_phy.as_u32.low & + CACHE_LINE_SIZE_MASK); + + ofld->hcopy_chain.cid_addr = GET_CID_ADDR(HCOPY_CID); + ofld->hcopy_chain.hw_con_idx_ptr = + &pdev->vars.status_virt->deflt.status_rx_quick_consumer_index15; + + s_list_init(&ofld->hcopy_chain.pending_descq, NULL, NULL, 0); + s_list_init(&ofld->hcopy_chain.active_descq, NULL, NULL, 0); + } + + ofld->cid_to_state = (lm_state_header_t **) mm_alloc_mem( + pdev, + sizeof(lm_state_header_t *) * MAX_CID, + NULL); + if(ofld->cid_to_state == NULL) + { + return LM_STATUS_RESOURCE; + } + + return LM_STATUS_SUCCESS; +} /* init_ofld_resc */ +#endif /* INCLUDE_OFLD_SUPPORT */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC volatile u16_t * +sblk_tx_con_idx_ptr( + lm_device_t *pdev, + lm_tx_chain_t *txq) +{ + volatile status_blk_combined_t *sblk; + volatile u16_t *idx_ptr; + + sblk = pdev->vars.status_virt; + + if(CHIP_NUM(pdev) == CHIP_NUM_5706 || CHIP_NUM(pdev) == CHIP_NUM_5708) + { + switch(txq->idx) + { + case TX_CHAIN_IDX0: + idx_ptr = &sblk->deflt.status_tx_quick_consumer_index0; + break; + + case TX_CHAIN_IDX1: + idx_ptr = &sblk->deflt.status_tx_quick_consumer_index1; + break; + + case TX_CHAIN_IDX2: + idx_ptr = &sblk->deflt.status_tx_quick_consumer_index2; + break; + + case TX_CHAIN_IDX3: + idx_ptr = &sblk->deflt.status_tx_quick_consumer_index3; + break; + + default: + idx_ptr = NULL; + + DbgBreakIf(txq->idx != pdev->tx_info.cu_idx); + + if(txq->idx == pdev->tx_info.cu_idx) + { + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index14; + } + break; + } + } + else + { + switch(txq->idx) + { + case TX_CHAIN_IDX0: + idx_ptr = &sblk->deflt.status_tx_quick_consumer_index0; + break; + + case TX_CHAIN_IDX1: + idx_ptr = &sblk->deflt.status_tx_quick_consumer_index1; + break; + + case TX_CHAIN_IDX2: + idx_ptr = &sblk->deflt.status_tx_quick_consumer_index2; + break; + + case TX_CHAIN_IDX3: + idx_ptr = &sblk->deflt.status_tx_quick_consumer_index3; + break; + + case TX_CHAIN_IDX4: + idx_ptr = &sblk->proc[0].status_pcpu_tx_quick_consumer_index; + break; + + case TX_CHAIN_IDX5: + idx_ptr = &sblk->proc[1].status_pcpu_tx_quick_consumer_index; + break; + + case TX_CHAIN_IDX6: + idx_ptr = &sblk->proc[2].status_pcpu_tx_quick_consumer_index; + break; + + case TX_CHAIN_IDX7: + idx_ptr = &sblk->proc[3].status_pcpu_tx_quick_consumer_index; + break; + + case TX_CHAIN_IDX8: + idx_ptr = &sblk->proc[4].status_pcpu_tx_quick_consumer_index; + break; + + case TX_CHAIN_IDX9: + idx_ptr = &sblk->proc[5].status_pcpu_tx_quick_consumer_index; + break; + + case TX_CHAIN_IDX10: + idx_ptr = &sblk->proc[6].status_pcpu_tx_quick_consumer_index; + break; + + case TX_CHAIN_IDX11: + idx_ptr = &sblk->proc[7].status_pcpu_tx_quick_consumer_index; + break; + + default: + DbgBreakMsg("invalid xinan tx index.\n"); + idx_ptr = NULL; + break; + } + } + + return idx_ptr; +} /* sblk_tx_con_idx_ptr */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +init_l2tx_resc( + lm_device_t *pdev) +{ + lm_tx_chain_t *txq; + u32_t bd_page_cnt; + u32_t mem_size; + u32_t idx; + u32_t num_tx_chains; + +#if defined(LM_NON_LEGACY_MODE_SUPPORT) + num_tx_chains = MAX_TX_CHAIN; + if(CHIP_NUM(pdev) == CHIP_NUM_5706 || CHIP_NUM(pdev) == CHIP_NUM_5708) + { + num_tx_chains = pdev->tx_info.num_txq; + } +#else + DbgBreakIf(pdev->tx_info.num_txq > MAX_TX_CHAIN); + for(idx = pdev->tx_info.num_txq; idx < MAX_TX_CHAIN; idx++) + { + pdev->params.l2_tx_bd_page_cnt[idx] = 0; + } + num_tx_chains = pdev->tx_info.num_txq; +#endif + for(idx = 0; idx < num_tx_chains; idx++) + { + txq = &pdev->tx_info.chain[idx]; + txq->idx = idx; + txq->cid_addr = GET_CID_ADDR(L2TX_CID_BASE + 2 * txq->idx); + + s_list_init(&txq->active_descq, NULL, NULL, 0); + + if(CHIP_NUM(pdev) == CHIP_NUM_5706 || CHIP_NUM(pdev) == CHIP_NUM_5708) + { + DbgBreakIf(idx > 4); + + if(txq->idx == pdev->tx_info.cu_idx && txq->idx != TX_CHAIN_IDX1) + { + DbgBreakIf(idx != 4); + txq->cid_addr = GET_CID_ADDR(30); + } + } + else if(txq->idx >= 4) + { + DbgBreakIf(idx > 11); + + /* Xinan has to use tx1 for catchup because catchup2 uses + * status_rx_quick_consumer_index14 for completion. This + * status block index is not available on Xinan. */ + DbgBreakIf(pdev->tx_info.cu_idx != TX_CHAIN_IDX1); + + if(txq->idx >= 4) + { + txq->cid_addr = GET_CID_ADDR(L2TX_TSS_CID_BASE + txq->idx - 4); + } + } + + bd_page_cnt = pdev->params.l2_tx_bd_page_cnt[txq->idx]; + if(bd_page_cnt) + { + mem_size = LM_PAGE_SIZE * bd_page_cnt; + + txq->bd_chain_virt = (tx_bd_t *) mm_alloc_phys_mem( + pdev, + mem_size, + &txq->bd_chain_phy, + PHYS_MEM_TYPE_NONCACHED, + NULL); + if(txq->bd_chain_virt == NULL) + { + return LM_STATUS_RESOURCE; + } + + DbgBreakIf(txq->bd_chain_phy.as_u32.low & CACHE_LINE_SIZE_MASK); + } + + txq->hw_con_idx_ptr = sblk_tx_con_idx_ptr(pdev, txq); + } + + return LM_STATUS_SUCCESS; +} /* init_l2tx_resc */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC volatile u16_t * +sblk_rx_con_idx_ptr( + lm_device_t *pdev, + lm_rx_chain_t *rxq) +{ + volatile status_blk_combined_t *sblk; + volatile u16_t *idx_ptr; + + sblk = pdev->vars.status_virt; + + if(CHIP_NUM(pdev) == CHIP_NUM_5706 || CHIP_NUM(pdev) == CHIP_NUM_5708) + { + switch(rxq->idx) + { + case RX_CHAIN_IDX0: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index0; + break; + + case RX_CHAIN_IDX1: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index1; + break; + + case RX_CHAIN_IDX2: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index2; + break; + + case RX_CHAIN_IDX3: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index3; + break; + + case RX_CHAIN_IDX4: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index4; + break; + + case RX_CHAIN_IDX5: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index5; + break; + + case RX_CHAIN_IDX6: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index6; + break; + + case RX_CHAIN_IDX7: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index7; + break; + + case RX_CHAIN_IDX8: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index8; + break; + + case RX_CHAIN_IDX9: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index9; + break; + + case RX_CHAIN_IDX10: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index10; + break; + + case RX_CHAIN_IDX11: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index11; + break; + + case RX_CHAIN_IDX12: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index12; + break; + + case RX_CHAIN_IDX13: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index13; + break; + + case RX_CHAIN_IDX14: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index14; + break; + + case RX_CHAIN_IDX15: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index15; + break; + + default: + DbgBreakMsg("invalid teton rx index.\n"); + idx_ptr = NULL; + break; + } + } + else + { + switch(rxq->idx) + { + case RX_CHAIN_IDX0: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index0; + break; + + case RX_CHAIN_IDX1: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index1; + break; + + case RX_CHAIN_IDX2: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index2; + break; + + case RX_CHAIN_IDX3: + idx_ptr = &sblk->deflt.status_rx_quick_consumer_index3; + break; + + case RX_CHAIN_IDX4: + idx_ptr = &sblk->proc[0].status_pcpu_rx_quick_consumer_index; + break; + + case RX_CHAIN_IDX5: + idx_ptr = &sblk->proc[1].status_pcpu_rx_quick_consumer_index; + break; + + case RX_CHAIN_IDX6: + idx_ptr = &sblk->proc[2].status_pcpu_rx_quick_consumer_index; + break; + + case RX_CHAIN_IDX7: + idx_ptr = &sblk->proc[3].status_pcpu_rx_quick_consumer_index; + break; + + case RX_CHAIN_IDX8: + idx_ptr = &sblk->proc[4].status_pcpu_rx_quick_consumer_index; + break; + + case RX_CHAIN_IDX9: + idx_ptr = &sblk->proc[5].status_pcpu_rx_quick_consumer_index; + break; + + case RX_CHAIN_IDX10: + idx_ptr = &sblk->proc[6].status_pcpu_rx_quick_consumer_index; + break; + + case RX_CHAIN_IDX11: + idx_ptr = &sblk->proc[7].status_pcpu_rx_quick_consumer_index; + break; + + default: + DbgBreakMsg("invalid xinan rx index.\n"); + idx_ptr = NULL; + break; + } + } + + return idx_ptr; +} /* sblk_rx_con_idx_ptr */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +alloc_l2rx_desc( + lm_device_t *pdev, + lm_rx_chain_t *rxq) +{ + u32_t bd_page_cnt; + lm_packet_t *pkt; + u32_t desc_size; + u32_t desc_cnt; + u8_t *mem_virt; + u32_t mem_size; + u32_t idx; + + bd_page_cnt = pdev->params.l2_rx_bd_page_cnt[rxq->idx]; + desc_cnt = pdev->params.l2_rx_desc_cnt[rxq->idx]; + + if(bd_page_cnt == 0 || desc_cnt == 0) + { + pdev->params.l2_rx_bd_page_cnt[rxq->idx] = 0; + pdev->params.l2_rx_desc_cnt[rxq->idx] = 0; + + return LM_STATUS_SUCCESS; + } + + mem_size = LM_PAGE_SIZE * bd_page_cnt; + + rxq->bd_chain_virt = (rx_bd_t *) mm_alloc_phys_mem( + pdev, + mem_size, + &rxq->bd_chain_phy, + PHYS_MEM_TYPE_NONCACHED, + NULL); + if(rxq->bd_chain_virt == NULL) + { + return LM_STATUS_RESOURCE; + } + + DbgBreakIf(rxq->bd_chain_phy.as_u32.low & CACHE_LINE_SIZE_MASK); + +#ifndef LM_NON_LEGACY_MODE_SUPPORT + desc_size = mm_desc_size(pdev, DESC_TYPE_L2RX_PACKET) + SIZEOF_SIG; + mem_size = desc_size * desc_cnt; + + mem_virt = (u8_t *) mm_alloc_mem(pdev, mem_size, NULL); + if(mem_virt == NULL) + { + return LM_STATUS_RESOURCE; + } + + for(idx = 0; idx < desc_cnt; idx++) + { + pkt = (lm_packet_t *) (mem_virt + SIZEOF_SIG); + mem_virt += desc_size; + mem_size -= desc_size; + + SIG(pkt) = L2PACKET_RX_SIG; + // full packet needs to hold mtu + 4-byte CRC32 + pkt->u1.rx.buf_size = pdev->params.mtu + 4; + pkt->u1.rx.buf_size += L2RX_FRAME_HDR_LEN; + pkt->u1.rx.buf_size += pdev->params.rcv_buffer_offset; + pkt->u1.rx.buf_size += CACHE_LINE_SIZE_MASK + 1; + pkt->u1.rx.buf_size &= ~CACHE_LINE_SIZE_MASK; + + s_list_push_tail(&rxq->free_descq, &pkt->link); + } + + DbgBreakIf(mem_size); + DbgBreakIf(s_list_entry_cnt(&rxq->free_descq) != desc_cnt); +#endif + return LM_STATUS_SUCCESS; +} /* alloc_l2rx_desc */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +init_l2rx_resc( + lm_device_t *pdev) +{ + lm_status_t lm_status; + lm_rx_chain_t *rxq; + u32_t idx; + +#ifndef LM_NON_LEGACY_MODE_SUPPORT + DbgBreakIf(pdev->rx_info.num_rxq > MAX_RX_CHAIN); + + for(idx = pdev->rx_info.num_rxq; idx < MAX_RX_CHAIN; idx++) + { + pdev->params.l2_rx_desc_cnt[idx] = 0; + pdev->params.l2_rx_bd_page_cnt[idx] = 0; + } +#endif + for(idx = 0; idx < pdev->rx_info.num_rxq ; idx++) + { + rxq = &pdev->rx_info.chain[idx]; + rxq->idx = idx; + rxq->cid_addr = GET_CID_ADDR(L2RX_CID_BASE + rxq->idx); + + s_list_init(&rxq->free_descq, NULL, NULL, 0); + s_list_init(&rxq->active_descq, NULL, NULL, 0); + + lm_status = alloc_l2rx_desc(pdev, rxq); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + rxq->hw_con_idx_ptr = sblk_rx_con_idx_ptr(pdev, rxq); + } + + return LM_STATUS_SUCCESS; +} /* init_l2rx_resc */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_status_t +init_context_resc_5709( + lm_device_t *pdev) +{ + phy_mem_block_t *ctx_mem; + u32_t page_align_delta; + lm_address_t mem_phy; + u32_t ctx_in_mblk; + u32_t mem_size; + u8_t *mem_virt; + u32_t ctx_cnt; + + DbgBreakIf(CHIP_NUM(pdev) != CHIP_NUM_5709); + DbgBreakIf(CTX_MBLK_SIZE & LM_PAGE_MASK); + DbgBreakIf(MAX_CTX > 16 * 1024); + DbgBreakIf(MAX_CTX * ONE_CTX_SIZE / CTX_MBLK_SIZE != NUM_CTX_MBLKS); + DbgBreakIf((MAX_CTX * ONE_CTX_SIZE) % CTX_MBLK_SIZE); + + ctx_mem = &pdev->vars.ctx_mem[0]; + ctx_cnt = 0; + + while(ctx_cnt < MAX_CTX) + { + ctx_in_mblk = CTX_MBLK_SIZE / ONE_CTX_SIZE; + if(ctx_cnt + ctx_in_mblk > MAX_CTX) + { + ctx_in_mblk = MAX_CTX - ctx_cnt; + } + + mem_size = ctx_in_mblk * ONE_CTX_SIZE; + + mem_virt = (u8_t *) mm_alloc_phys_mem( + pdev, + mem_size + LM_PAGE_MASK, + &mem_phy, + PHYS_MEM_TYPE_NONCACHED, + NULL); + if(mem_virt == NULL) + { + return LM_STATUS_RESOURCE; + } + + page_align_delta = mem_phy.as_u32.low & LM_PAGE_MASK; + if(page_align_delta) + { + page_align_delta = LM_PAGE_SIZE - page_align_delta; + } + + mem_virt += page_align_delta; + LM_INC64(&mem_phy, page_align_delta); + + ctx_mem->start_phy = mem_phy; + ctx_mem->start = mem_virt; + ctx_mem->size = mem_size; + ctx_mem++; + + ctx_cnt += mem_size / ONE_CTX_SIZE; + } + + return LM_STATUS_SUCCESS; +} /* init_context_resc_5709 */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_init_resc( + lm_device_t *pdev) +{ + lm_status_t lm_status; + lm_address_t mem_phy; + u8_t *mem_virt; + u32_t mem_size; + + #ifndef EXCLUDE_KQE_SUPPORT + lm_status = init_kwq_resc(pdev); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + lm_status = init_kcq_resc(pdev); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + #endif + + #if INCLUDE_OFLD_SUPPORT + lm_status = init_ofld_resc(pdev); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + #endif + + DbgBreakIf(sizeof(status_blk_combined_t) > STATUS_BLOCK_BUFFER_SIZE); + DbgBreakIf(sizeof(statistics_block_t) > CHIP_STATS_BUFFER_SIZE); + + mem_size = STATUS_BLOCK_BUFFER_SIZE + + #ifndef EXCLUDE_RSS_SUPPORT + RSS_INDIRECTION_TABLE_SIZE + + RSS_LOOKUP_TABLE_WA + + #endif + CHIP_STATS_BUFFER_SIZE; + + mem_virt = mm_alloc_phys_mem( + pdev, + mem_size, + &mem_phy, + PHYS_MEM_TYPE_NONCACHED, + NULL); + if(mem_virt == NULL) + { + return LM_STATUS_RESOURCE; + } + + DbgBreakIf(mem_phy.as_u32.low & CACHE_LINE_SIZE_MASK); + + pdev->vars.status_virt = (status_blk_combined_t *) mem_virt; + pdev->vars.status_phy = mem_phy; + mem_virt += STATUS_BLOCK_BUFFER_SIZE; + LM_INC64(&mem_phy, STATUS_BLOCK_BUFFER_SIZE); + + pdev->vars.stats_virt = (statistics_block_t *) mem_virt; + pdev->vars.stats_phy = mem_phy; + mem_virt += CHIP_STATS_BUFFER_SIZE; + LM_INC64(&mem_phy, CHIP_STATS_BUFFER_SIZE); + + #ifndef EXCLUDE_RSS_SUPPORT + pdev->rx_info.rss_ind_table_virt = mem_virt; + pdev->rx_info.rss_ind_table_phy = mem_phy; + #endif + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + lm_status = init_context_resc_5709(pdev); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + } + + lm_status = init_l2tx_resc(pdev); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + lm_status = init_l2rx_resc(pdev); + if(lm_status != LM_STATUS_SUCCESS) + { + return lm_status; + } + + lm_clear_nwuf(pdev); + + return LM_STATUS_SUCCESS; +} /* lm_init_resc */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u32_t +compute_crc32( + u8_t *buf, + u32_t buf_size) +{ + u32_t reg; + u32_t tmp; + u32_t j; + u32_t k; + + reg = 0xffffffff; + + for(j = 0; j < buf_size; j++) + { + reg ^= buf[j]; + + for(k = 0; k < 8; k++) + { + tmp = reg & 0x01; + + reg >>= 1; + + if(tmp) + { + reg ^= 0xedb88320; + } + } + } + + return ~reg; +} /* compute_crc32 */ + + + +#define NUM_MC_HASH_REGISTERS 8 +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +set_mc_hash_reg( + lm_device_t *pdev, + lm_mc_table_t *mc_table) +{ + u32_t hash_reg[NUM_MC_HASH_REGISTERS]; + u32_t reg_idx; + u32_t bit_pos; + u32_t idx; + u32_t crc32; + + /* Program the MC hash registers. + * The MAC hash registers are used to help discard unwanted + * multicast packets as they are received from the external + * media. The destination address is fed into the normal CRC + * algorithm in order to generate a hash function. The most + * significant bits of the CRC are then used without any inversion + * in reverse order to index into a hash table which is comprised + * of these MAC hash registers. If the CRC is calculated by + * shifting right then the rightmost bits of the CRC can be + * directly used with no additional inversion or bit swapping + * required. All four MAC hash registers are used such that + * register 1 bit-32 is the most significant hash table entry + * and register 8 bit-0 is the least significant hash table entry. + * This follows the normal big-endian ordering used throughout + * Teton. Since there are 256 hash table entries, 8-bits are + * used from the CRC. The hash registers are ignored if the + * receive MAC is in promiscuous mode. */ + for(idx = 0; idx < NUM_MC_HASH_REGISTERS; idx++) + { + hash_reg[idx] = 0; + } + + for(idx = 0; idx < mc_table->entry_cnt; idx++) + { + crc32 = compute_crc32( + mc_table->addr_arr[idx].mc_addr, + ETHERNET_ADDRESS_SIZE); + + /* The most significant 7 bits of the CRC32 (no inversion), + * are used to index into one of the possible 128 bit positions. */ + bit_pos = ~crc32 & 0xff; + + reg_idx = (bit_pos & 0xe0) >> 5; + + bit_pos &= 0x1f; + + hash_reg[reg_idx] |= (1 << bit_pos); + } + + for(idx = 0; idx < NUM_MC_HASH_REGISTERS; idx++) + { + REG_WR(pdev, emac.emac_multicast_hash[idx], hash_reg[idx]); + } +} /* set_mc_hash_reg */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_set_rx_mask( + lm_device_t *pdev, + u32_t user_idx, + lm_rx_mask_t rx_mask) +{ + u32_t combined_rx_mask; + u32_t invalid_rx_mask; + u32_t sort_mode; + u32_t rx_mode; + u32_t val; + u32_t idx; + + if(user_idx >= MAX_RX_FILTER_USER_CNT) + { + DbgBreakMsg("invalid user index.\n"); + + return LM_STATUS_FAILURE; + } + + combined_rx_mask = rx_mask; + for(idx = 0; idx < MAX_RX_FILTER_USER_CNT; idx++) + { + if(idx != user_idx) + { + combined_rx_mask |= pdev->rx_info.mask[idx]; + } + } + + /* Set up the rx_mode register. */ + invalid_rx_mask = combined_rx_mask; + REG_RD(pdev, emac.emac_rx_mode, &rx_mode); + + if(invalid_rx_mask & LM_RX_MASK_ACCEPT_UNICAST) + { + invalid_rx_mask &= ~LM_RX_MASK_ACCEPT_UNICAST; + } + + if(invalid_rx_mask & LM_RX_MASK_ACCEPT_MULTICAST) + { + invalid_rx_mask &= ~LM_RX_MASK_ACCEPT_MULTICAST; + } + + if(invalid_rx_mask & LM_RX_MASK_ACCEPT_ALL_MULTICAST) + { + invalid_rx_mask &= ~LM_RX_MASK_ACCEPT_ALL_MULTICAST; + } + + rx_mode &= ~EMAC_RX_MODE_FILT_BROADCAST; + if(invalid_rx_mask & LM_RX_MASK_ACCEPT_BROADCAST) + { + invalid_rx_mask &= ~LM_RX_MASK_ACCEPT_BROADCAST; + } + else + { + rx_mode |= EMAC_RX_MODE_FILT_BROADCAST; + } + + rx_mode &= ~(EMAC_RX_MODE_ACCEPT_RUNTS | EMAC_RX_MODE_ACCEPT_OVERSIZE); + if(invalid_rx_mask & LM_RX_MASK_ACCEPT_ERROR_PACKET) + { + invalid_rx_mask &= ~LM_RX_MASK_ACCEPT_ERROR_PACKET; + rx_mode |= EMAC_RX_MODE_ACCEPT_RUNTS | + EMAC_RX_MODE_ACCEPT_OVERSIZE | + EMAC_RX_MODE_NO_CRC_CHK; + } + + rx_mode &= ~EMAC_RX_MODE_PROMISCUOUS; + if(invalid_rx_mask & LM_RX_MASK_PROMISCUOUS_MODE) + { + invalid_rx_mask &= ~LM_RX_MASK_PROMISCUOUS_MODE; + rx_mode |= EMAC_RX_MODE_PROMISCUOUS; + } + + if(invalid_rx_mask) + { + DbgBreakMsg("Unknown rx_mask.\n"); + + return LM_STATUS_FAILURE; + } + + if(combined_rx_mask & LM_RX_MASK_ACCEPT_ALL_MULTICAST) + { + for(idx = 0; idx < NUM_MC_HASH_REGISTERS; idx++) + { + REG_WR(pdev, emac.emac_multicast_hash[idx], 0xffffffff); + } + } + else if(combined_rx_mask & LM_RX_MASK_ACCEPT_MULTICAST) + { + set_mc_hash_reg(pdev, &pdev->mc_table); + } + else + { + for(idx = 0; idx < NUM_MC_HASH_REGISTERS; idx++) + { + REG_WR(pdev, emac.emac_multicast_hash[idx], 0); + } + } + + pdev->rx_info.mask[user_idx] = rx_mask; + + val = rx_mode | EMAC_RX_MODE_SORT_MODE; + if(pdev->params.keep_vlan_tag) + { + val |= EMAC_RX_MODE_KEEP_VLAN_TAG; + } + REG_WR(pdev, emac.emac_rx_mode, val); + + /* Set up the sort_mode register. */ + sort_mode = 0; + + if(rx_mask & LM_RX_MASK_ACCEPT_UNICAST) + { + sort_mode |= 1 << user_idx; + } + + if(rx_mask & LM_RX_MASK_ACCEPT_MULTICAST) + { + sort_mode |= RPM_SORT_USER0_MC_HSH_EN; + } + + if(rx_mask & LM_RX_MASK_ACCEPT_ALL_MULTICAST) + { + sort_mode |= RPM_SORT_USER0_MC_EN; + } + + if(rx_mask & LM_RX_MASK_ACCEPT_BROADCAST) + { + sort_mode |= RPM_SORT_USER0_BC_EN; + } + + if(rx_mask & LM_RX_MASK_PROMISCUOUS_MODE) + { + sort_mode |= RPM_SORT_USER0_PROM_EN | RPM_SORT_USER0_PROM_VLAN; + } + + switch(user_idx) + { + case RX_FILTER_USER_IDX0: + REG_RD(pdev, rpm.rpm_sort_user0, &val); + + REG_WR(pdev, rpm.rpm_sort_user0, 0x00000000); + REG_WR(pdev, rpm.rpm_sort_user0, sort_mode); + + val &= 0xffff; + val &= ~(1 << user_idx); + + sort_mode |= val | RPM_SORT_USER0_ENA; + REG_WR(pdev, rpm.rpm_sort_user0, sort_mode); + break; + + case RX_FILTER_USER_IDX1: + REG_RD(pdev, rpm.rpm_sort_user1, &val); + + REG_WR(pdev, rpm.rpm_sort_user1, 0x00000000); + REG_WR(pdev, rpm.rpm_sort_user1, sort_mode); + + val &= 0xffff; + val &= ~(1 << user_idx); + + sort_mode |= val | RPM_SORT_USER0_ENA; + REG_WR(pdev, rpm.rpm_sort_user1, sort_mode); + break; + + case RX_FILTER_USER_IDX2: + REG_RD(pdev, rpm.rpm_sort_user2, &val); + + REG_WR(pdev, rpm.rpm_sort_user2, 0x00000000); + REG_WR(pdev, rpm.rpm_sort_user2, sort_mode); + + val &= 0xffff; + val &= ~(1 << user_idx); + + sort_mode |= val | RPM_SORT_USER0_ENA; + REG_WR(pdev, rpm.rpm_sort_user2, sort_mode); + break; + + case RX_FILTER_USER_IDX3: + REG_RD(pdev, rpm.rpm_sort_user3, &val); + + REG_WR(pdev, rpm.rpm_sort_user3, 0x00000000); + REG_WR(pdev, rpm.rpm_sort_user3, sort_mode); + + val &= 0xffff; + val &= ~(1 << user_idx); + + sort_mode |= val | RPM_SORT_USER0_ENA; + REG_WR(pdev, rpm.rpm_sort_user3, sort_mode); + break; + + default: + DbgBreakMsg("invalid user idx.\n"); + + break; + } + + /* Set rx_flood for L2. */ + REG_RD_IND(pdev, 0xe0024, &val); + val &= ~(1 << user_idx); + + if(rx_mask & (LM_RX_MASK_ACCEPT_MULTICAST | + LM_RX_MASK_ACCEPT_ALL_MULTICAST | + LM_RX_MASK_ACCEPT_BROADCAST | + LM_RX_MASK_PROMISCUOUS_MODE)) + { + val |= (1 << user_idx); + } + + REG_WR_IND(pdev, 0xe0024, val); + + return LM_STATUS_SUCCESS; +} /* lm_set_rx_mask */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_add_mc( + lm_device_t *pdev, + u8_t *mc_addr) +{ + lm_mc_entry_t *mc_entry; + u32_t cnt; + + DbgMessage(pdev, VERBOSE, "### lm_add_mc\n"); + + for(cnt = 0; cnt < pdev->mc_table.entry_cnt; cnt++) + { + mc_entry = &pdev->mc_table.addr_arr[cnt]; + + if(IS_ETH_ADDRESS_EQUAL(mc_entry->mc_addr, mc_addr)) + { + mc_entry->ref_cnt++; + + return LM_STATUS_SUCCESS; + } + } + + if(pdev->mc_table.entry_cnt >= LM_MAX_MC_TABLE_SIZE) + { + DbgBreakMsg("No entry in MC table\n"); + + return LM_STATUS_FAILURE; + } + + mc_entry = &pdev->mc_table.addr_arr[pdev->mc_table.entry_cnt]; + pdev->mc_table.entry_cnt++; + + mc_entry->ref_cnt = 1; + + COPY_ETH_ADDRESS(mc_addr, mc_entry->mc_addr); + + (void) lm_set_rx_mask( + pdev, + RX_FILTER_USER_IDX0, + pdev->rx_info.mask[RX_FILTER_USER_IDX0] | LM_RX_MASK_ACCEPT_MULTICAST); + + return LM_STATUS_SUCCESS; +} /* lm_add_mc */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_del_mc( + lm_device_t *pdev, + u8_t *mc_addr) +{ + lm_mc_entry_t *mc_entry; + u32_t cnt; + + for(cnt = 0; cnt < pdev->mc_table.entry_cnt; cnt++) + { + mc_entry = &pdev->mc_table.addr_arr[cnt]; + + if(IS_ETH_ADDRESS_EQUAL(mc_entry->mc_addr, mc_addr)) + { + mc_entry->ref_cnt--; + + /* No more instance left, remove the address from the table. + * Move the last entry in the table to the deleted slot. */ + if(mc_entry->ref_cnt == 0) + { + if(pdev->mc_table.entry_cnt > 1) + { + *mc_entry = pdev->mc_table.addr_arr[pdev->mc_table.entry_cnt-1]; + } + + pdev->mc_table.entry_cnt--; + + /* Update the receive mask if the table is empty. */ + if(pdev->mc_table.entry_cnt == 0) + { + pdev->rx_info.mask[RX_FILTER_USER_IDX0] &= + ~LM_RX_MASK_ACCEPT_MULTICAST; + } + + (void) lm_set_rx_mask( + pdev, + RX_FILTER_USER_IDX0, + pdev->rx_info.mask[RX_FILTER_USER_IDX0]); + } + + return LM_STATUS_SUCCESS; + } + } + + DbgBreakMsg("Mc address not in the table\n"); + + return LM_STATUS_FAILURE; +} /* lm_del_mc */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_clear_mc(lm_device_t *pdev) +{ + DbgMessage(pdev, VERBOSE, "### lm_clear_mc\n"); + + pdev->mc_table.entry_cnt = 0; + + (void) lm_set_rx_mask( + pdev, + RX_FILTER_USER_IDX0, + pdev->rx_info.mask[RX_FILTER_USER_IDX0] & ~LM_RX_MASK_ACCEPT_MULTICAST); +} /* lm_clear_mc */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_get_stats( + lm_device_t *pdev, + lm_stats_t stats_type, + u64_t *stats_cnt) +{ + volatile statistics_block_t *sb; + lm_status_t lm_status; + lm_u64_t *stats; + u32_t reg_val; + u32_t val; + + // + // The fix of CQ#29454 caused CQ#30307 - + // Bacs: Bogus counters on 5708 under statistics tab + // So far, Windows never see CQ#29454 problem. + // Remove the fix right now + // + + /* CQ#29454 - statistics corruption. */ + //REG_RD(pdev, hc.hc_stats_ticks, &val); + //REG_WR(pdev, hc.hc_stats_ticks, 0); + + REG_WR(pdev, hc.hc_command, HC_COMMAND_STATS_NOW); + REG_RD(pdev, hc.hc_command, ®_val); + mm_wait(pdev, 5); + + lm_status = LM_STATUS_SUCCESS; + sb = pdev->vars.stats_virt; + stats = (lm_u64_t *) stats_cnt; + + switch(stats_type) + { + case LM_STATS_FRAMES_XMITTED_OK: + stats->as_u32.low = sb->stat_IfHCOutUcastPkts_lo; + stats->as_u32.high = sb->stat_IfHCOutUcastPkts_hi; + + LM_INC64(stats, sb->stat_IfHCOutMulticastPkts_lo); + stats->as_u32.high += sb->stat_IfHCOutMulticastPkts_hi; + + LM_INC64(stats, sb->stat_IfHCOutBroadcastPkts_lo); + stats->as_u32.high += sb->stat_IfHCOutBroadcastPkts_hi; + break; + + case LM_STATS_FRAMES_RECEIVED_OK: + stats->as_u32.low = sb->stat_IfHCInUcastPkts_lo; + stats->as_u32.high = sb->stat_IfHCInUcastPkts_hi; + + LM_INC64(stats, sb->stat_IfHCInMulticastPkts_lo); + stats->as_u32.high += sb->stat_IfHCInMulticastPkts_hi; + + LM_INC64(stats, sb->stat_IfHCInBroadcastPkts_lo); + stats->as_u32.high += sb->stat_IfHCInBroadcastPkts_hi; + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, + com.com_scratch[0])+ + COM_HSI_OFFSETOFF(com_l2_iscsi_no_buffer), + &val); + if((stats->as_u32.high == 0 && stats->as_u32.low) && + (stats->as_u32.low < val)) + { + /* due to asynchrous nature of reading the counters + * from status block and reading the counters from + * chip scratchpad mem, it is possible that the values + * are out of syn */ + stats->as_u32.low = 0; + } + else + { + LM_DEC64(stats, val); + } + + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, + com.com_scratch[0])+ + COM_HSI_OFFSETOFF(com_l2_no_buffer), + &val); + if((stats->as_u32.high == 0 && stats->as_u32.low) && + (stats->as_u32.low < val)) + { + /* due to asynchrous nature of reading the counters + * from status block and reading the counters from + * chip scratchpad mem, it is possible that the values + * are out of syn */ + stats->as_u32.low = 0; + } + else + { + LM_DEC64(stats, val); + } + break; + + case LM_STATS_ERRORED_RECEIVE_CNT: + stats->as_u32.low = pdev->rx_info.stats.err; + stats->as_u32.high = 0; + break; + + case LM_STATS_RCV_CRC_ERROR: + stats->as_u32.low = sb->stat_Dot3StatsFCSErrors; + stats->as_u32.high = 0; + break; + + case LM_STATS_ALIGNMENT_ERROR: + stats->as_u32.low = sb->stat_Dot3StatsAlignmentErrors; + stats->as_u32.high = 0; + break; + + case LM_STATS_SINGLE_COLLISION_FRAMES: + stats->as_u32.low = sb->stat_Dot3StatsSingleCollisionFrames; + stats->as_u32.high = 0; + break; + + case LM_STATS_MULTIPLE_COLLISION_FRAMES: + stats->as_u32.low = sb->stat_Dot3StatsMultipleCollisionFrames; + stats->as_u32.high = 0; + break; + + case LM_STATS_FRAMES_DEFERRED: + stats->as_u32.low = sb->stat_Dot3StatsDeferredTransmissions; + stats->as_u32.high = 0; + break; + + case LM_STATS_MAX_COLLISIONS: + stats->as_u32.low = sb->stat_Dot3StatsExcessiveCollisions; + break; + + case LM_STATS_UNICAST_FRAMES_XMIT: + stats->as_u32.low = sb->stat_IfHCOutUcastPkts_lo; + stats->as_u32.high = sb->stat_IfHCOutUcastPkts_hi; + break; + + case LM_STATS_MULTICAST_FRAMES_XMIT: + stats->as_u32.low = sb->stat_IfHCOutMulticastPkts_lo; + stats->as_u32.high = sb->stat_IfHCOutMulticastPkts_hi; + break; + + case LM_STATS_BROADCAST_FRAMES_XMIT: + stats->as_u32.low = sb->stat_IfHCOutBroadcastPkts_lo; + stats->as_u32.high = sb->stat_IfHCOutBroadcastPkts_hi; + break; + + case LM_STATS_UNICAST_FRAMES_RCV: + stats->as_u32.low = sb->stat_IfHCInUcastPkts_lo; + stats->as_u32.high = sb->stat_IfHCInUcastPkts_hi; + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, + com.com_scratch[0])+ + COM_HSI_OFFSETOFF(com_unicast_no_buffer), + &val); + if((stats->as_u32.high == 0 && stats->as_u32.low) && + (stats->as_u32.low < val)) + { + /* due to asynchrous nature of reading the counters + * from status block and reading the counters from + * chip scratchpad mem, it is possible that the values + * are out of syn */ + stats->as_u32.low = 0; + } + else + { + LM_DEC64(stats, val); + } + break; + + case LM_STATS_MULTICAST_FRAMES_RCV: + stats->as_u32.low = sb->stat_IfHCInMulticastPkts_lo; + stats->as_u32.high = sb->stat_IfHCInMulticastPkts_hi; + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, + com.com_scratch[0])+ + COM_HSI_OFFSETOFF(com_mcast_no_buffer), + &val); + + if((stats->as_u32.high == 0 && stats->as_u32.low) && + (stats->as_u32.low < val)) + { + /* due to asynchrous nature of reading the counters + * from status block and reading the counters from + * chip scratchpad mem, it is possible that the values + * are out of syn */ + stats->as_u32.low = 0; + } + else + { + LM_DEC64(stats, val); + } + break; + + case LM_STATS_BROADCAST_FRAMES_RCV: + stats->as_u32.low = sb->stat_IfHCInBroadcastPkts_lo; + stats->as_u32.high = sb->stat_IfHCInBroadcastPkts_hi; + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, + com.com_scratch[0])+ + COM_HSI_OFFSETOFF(com_bcast_no_buffer), + &val); + if((stats->as_u32.high == 0 && stats->as_u32.low) && + (stats->as_u32.low < val)) + { + /* due to asynchrous nature of reading the counters + * from status block and reading the counters from + * chip scratchpad mem, it is possible that the values + * are out of syn */ + stats->as_u32.low = 0; + } + else + { + LM_DEC64(stats, val); + } + break; + + case LM_STATS_ERRORED_TRANSMIT_CNT: + case LM_STATS_RCV_OVERRUN: + case LM_STATS_XMIT_UNDERRUN: + /* These counters are always zero. */ + stats->as_u32.low = 0; + stats->as_u32.high = 0; + break; + + case LM_STATS_RCV_NO_BUFFER_DROP: + /* com_no_buffer */ + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_unicast_no_buffer), + &val); + stats->as_u32.low = val; + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_mcast_no_buffer), + &val); + stats->as_u32.low += val; + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_bcast_no_buffer), + &val); + stats->as_u32.low += val; + + stats->as_u32.high = 0; + break; + + case LM_STATS_BYTES_RCV: + stats->as_u32.low = sb->stat_IfHCInOctets_lo; + stats->as_u32.high = sb->stat_IfHCInOctets_hi; + break; + + case LM_STATS_BYTES_XMIT: + stats->as_u32.low = sb->stat_IfHCOutOctets_lo; + stats->as_u32.high = sb->stat_IfHCOutOctets_hi; + break; + + case LM_STATS_IF_IN_DISCARDS: + /* com_no_buffer */ + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_unicast_no_buffer), + &val); + stats->as_u32.low = val; + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_mcast_no_buffer), + &val); + stats->as_u32.low += val; + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_bcast_no_buffer), + &val); + stats->as_u32.low += val; + stats->as_u32.low += sb->stat_Dot3StatsFCSErrors; + + stats->as_u32.high = 0; + break; + + case LM_STATS_XMIT_DISCARDS: + case LM_STATS_IF_IN_ERRORS: + case LM_STATS_IF_OUT_ERRORS: + stats->as_u32.low = 0; + stats->as_u32.high = 0; + break; + + case LM_STATS_DIRECTED_BYTES_RCV: + /* rxp_unicast_bytes_rcvd */ + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(rxp_unicast_bytes_rcvd)+4, + &stats->as_u32.low); + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(rxp_unicast_bytes_rcvd), + &stats->as_u32.high); + break; + + case LM_STATS_MULTICAST_BYTES_RCV: + /* rxp_multicast_bytes_rcvd */ + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(rxp_multicast_bytes_rcvd)+4, + &stats->as_u32.low); + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(rxp_multicast_bytes_rcvd), + &stats->as_u32.high); + break; + + case LM_STATS_BROADCAST_BYTES_RCV: + /* rxp_broadcast_bytes_rcvd */ + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(rxp_broadcast_bytes_rcvd)+4, + &stats->as_u32.low); + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+RXP_HSI_OFFSETOFF(rxp_broadcast_bytes_rcvd), + &stats->as_u32.high); + break; + + case LM_STATS_DIRECTED_BYTES_XMIT: + /* unicast_bytes_xmit_lo */ + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, tpat.tpat_scratch[0])+TPAT_HSI_OFFSETOFF(unicast_bytes_xmit)+4, + &stats->as_u32.low); + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, tpat.tpat_scratch[0])+TPAT_HSI_OFFSETOFF(unicast_bytes_xmit), + &stats->as_u32.high); + break; + + case LM_STATS_MULTICAST_BYTES_XMIT: + /* multicast_bytes_xmit */ + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, tpat.tpat_scratch[0])+TPAT_HSI_OFFSETOFF(multicast_bytes_xmit)+4, + &stats->as_u32.low); + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, tpat.tpat_scratch[0])+TPAT_HSI_OFFSETOFF(multicast_bytes_xmit), + &stats->as_u32.high); + break; + + case LM_STATS_BROADCAST_BYTES_XMIT: + /* broadcast_bytes_xmit */ + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, tpat.tpat_scratch[0])+TPAT_HSI_OFFSETOFF(broadcast_bytes_xmit)+4, + &stats->as_u32.low); + REG_RD_IND( + pdev, + OFFSETOF(reg_space_t, tpat.tpat_scratch[0])+TPAT_HSI_OFFSETOFF(broadcast_bytes_xmit), + &stats->as_u32.high); + break; + + default: + stats->as_u32.low = 0; + stats->as_u32.high = 0; + + lm_status = LM_STATUS_INVALID_PARAMETER; + break; + } + + //REG_WR(pdev, hc.hc_stats_ticks, val); + + return lm_status; +} /* lm_get_stats */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC lm_nwuf_t * +find_nwuf( + lm_nwuf_list_t *nwuf_list, + u32_t mask_size, + u8_t *byte_mask, + u8_t *pattern, + u32_t max_nwuf_cnt) +{ + lm_nwuf_t *nwuf; + u8_t found; + u32_t idx; + u32_t j; + u32_t k; + + for(idx = 0; idx < max_nwuf_cnt; idx++) + { + nwuf = &nwuf_list->nwuf_arr[idx]; + + if((nwuf->size&0xffff) != mask_size) + { + continue; + } + + found = TRUE; + for(j = 0; j < mask_size && found == TRUE; j++) + { + if(nwuf->mask[j] != byte_mask[j]) + { + found = FALSE; + break; + } + + for(k = 0; k < 8; k++) + { + if((byte_mask[j] & (1 << k)) && + (nwuf->pattern[j*8 + k] != pattern[j*8 + k])) + { + found = FALSE; + break; + } + } + } + + if(found) + { + return nwuf; + } + } + + return NULL; +} /* find_nwuf */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_add_nwuf( + lm_device_t *pdev, + u32_t pattern_size, + u32_t mask_size, + u8_t *byte_mask, + u8_t *pattern) +{ + lm_nwuf_t *nwuf; + u32_t idx; +/* + u32_t i; +*/ + u32_t j; + u32_t k; + u32_t l; + u32_t combind_size; + u32_t max_nwuf_cnt; + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + max_nwuf_cnt = LM_MAX_NWUF_CNT_5709; + } + else + { + max_nwuf_cnt = LM_MAX_NWUF_CNT; + } + + combind_size = (pattern_size<<16) & 0xffff0000; + combind_size |= mask_size; + pattern_size &= 0xffff; + mask_size &= 0xffff; + + + //DbgBreakIf(mask_size == 0xc &&pattern_size == 0x4a); + + + if(mask_size == 0 || mask_size > LM_NWUF_PATTERN_MASK_SIZE) + { + DbgBreakMsg("Invalid byte mask size\n"); + + return LM_STATUS_FAILURE; + } + + /* If this is a duplicate entry, we are done. */ + nwuf = find_nwuf( + &pdev->nwuf_list, + mask_size, + byte_mask, pattern, + max_nwuf_cnt); + + if(nwuf) + { + DbgMessage(pdev, INFORM, "Duplicated nwuf entry.\n"); + + return LM_STATUS_EXISTING_OBJECT; + } + + /* Find an empty slot. */ + nwuf = NULL; + for(idx = 0; idx < max_nwuf_cnt; idx++) + { + if(pdev->nwuf_list.nwuf_arr[idx].size == 0) + { + nwuf = &pdev->nwuf_list.nwuf_arr[idx]; + break; + } + } + + /* + * LHDBG_PRINT(("%p Adding NWUF[%d], mask size: %d, pattern size: %d\n", + pdev,idx,mask_size,pattern_size)); + LHDBG_PRINT(("mask array:\n")); + + for (i=0;i<mask_size;i++) + { + if (0 == i%16) LH_PRINTK(("\n")); + LH_PRINTK(("%02x ", byte_mask[i])); + } + LH_PRINTK(("\npattern:\n")); + + for (i=0;i<mask_size;i++) + { + for (j=0;j<8;j++) + { + if (0 == (i*8+j)%16) + { + LH_PRINTK(("\n")); + } + if (byte_mask[i] & 1<<j) + { + LH_PRINTK(("[%02x] ",pattern[i*8+j])); + } + else + { + if (pattern_size && i*8+j>=pattern_size) + { + LH_PRINTK(("-%02x- ",pattern[i*8+j])); + } + else + { + LH_PRINTK((" %02x ",pattern[i*8+j])); + } + + } + } + } + LH_PRINTK(("\n")); +*/ + + if(nwuf == NULL) + { + DbgMessage(pdev, WARN, "Cannot add Nwuf, exceeded maximum.\n"); + + return LM_STATUS_RESOURCE; + } + + pdev->nwuf_list.cnt++; + + /* Save nwuf data. */ + nwuf->size = mask_size; + + if (pattern_size) + { + nwuf->size = combind_size; + goto _handle_win7_pattern; + } + + for(j = 0; j < mask_size; j++) + { + nwuf->mask[j] = byte_mask[j]; + + for(k = 0; k < 8; k++) + { + if(byte_mask[j] & (1 << k)) + { + nwuf->pattern[j*8 + k] = pattern[j*8 + k]; + } + else + { + nwuf->pattern[j*8 + k] = 0; + } + } + } + + /* The byte patterns immediately following the byte that is enabled + * for comparision need to be set to 0xff. This will help facilitate + * the programming of pattern onto the chip. The end of the pattern is + * indicated by the first 0xff byte that is not enabled for comparision. */ + if(byte_mask[mask_size-1]) + { + k = 8; + while(k) + { + k--; + if(byte_mask[mask_size-1] & (1 << k)) + { + break; + } + + nwuf->pattern[(mask_size-1)*8 + k] = 0xff; + } + } + + /* Set the rest of the pattern to 0xff. */ + for(j = mask_size; j < LM_NWUF_PATTERN_MASK_SIZE; j++) + { + nwuf->mask[j] = 0; + + for(k = 0; k < 8; k++) + { + nwuf->pattern[j*8 + k] = 0xff; + } + } +/* + LHDBG_PRINT(("Dumping pattern before return\n")); + for (i=0;i<128;i++) + { + if (i!=0 && i%16==0) + { + LH_PRINTK(("\n")); + } + + LH_PRINTK(("%02x ",nwuf->pattern[i])); + + } + LH_PRINTK(("\nEnd of add_nwuf\n")); +*/ + return LM_STATUS_SUCCESS; +_handle_win7_pattern: + /* + * this is new for win7 + */ + l=0; + + /*for lxdiag build*/ +#ifdef LINUX + { + u8_t idx; + for (idx=0; idx< LM_NWUF_PATTERN_MASK_SIZE; idx++) + nwuf->mask[idx] = 0; + } +#else + memset(nwuf->mask,0,LM_NWUF_PATTERN_MASK_SIZE); +#endif + + for(j = 0; j < mask_size ; j++) + { + nwuf->mask[j] = byte_mask[j]; + + for(k = 0; k < 8 ; k++) + { + if ( l<pattern_size ) + { + if(byte_mask[j] & (1 << k)) + { + nwuf->pattern[j*8 + k] = pattern[j*8 + k]; + } + else + { + nwuf->pattern[j*8 + k] = 0; + } + } + else + { + nwuf->pattern[j*8 + k] = 0xff; + } + l++; + } + } +/* + LHDBG_PRINT(("Dumping pattern before return\n")); + for (i=0;i<128;i++) + { + if (i!=0 && i%16==0) + { + LH_PRINTK(("\n")); + } + + LH_PRINTK(("%02x ",nwuf->pattern[i])); + + } + LH_PRINTK(("\nEnd of add_nwuf\n")); +*/ + return LM_STATUS_SUCCESS; +} /* lm_add_nwuf */ + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_del_nwuf( + lm_device_t *pdev, + u32_t mask_size, + u8_t *byte_mask, + u8_t *pattern) +{ + lm_nwuf_t *nwuf; + u32_t k; + u32_t max_nwuf_cnt; + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + max_nwuf_cnt = LM_MAX_NWUF_CNT_5709; + } + else + { + max_nwuf_cnt = LM_MAX_NWUF_CNT; + } + + mask_size &= 0xffff; + if(mask_size == 0 || mask_size > LM_NWUF_PATTERN_MASK_SIZE) + { + DbgBreakMsg("Invalid byte mask size\n"); + + return LM_STATUS_FAILURE; + } + + /* Look for a matching pattern. */ + nwuf = find_nwuf( + &pdev->nwuf_list, + mask_size, + byte_mask, + pattern, + max_nwuf_cnt); + + if(nwuf == NULL) + { + return LM_STATUS_OBJECT_NOT_FOUND; + } + + nwuf->size = 0; + + for(k = 0; k < LM_NWUF_PATTERN_MASK_SIZE; k++) + { + nwuf->mask[k] = 0; + } + + for(k = 0; k < LM_NWUF_PATTERN_SIZE; k++) + { + nwuf->pattern[k] = 0xff; + } + + pdev->nwuf_list.cnt--; + + return LM_STATUS_SUCCESS; +} /* lm_del_nwuf */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_clear_nwuf( + lm_device_t *pdev) +{ + u32_t j; + u32_t k; + u32_t max_nwuf_cnt; + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + max_nwuf_cnt = LM_MAX_NWUF_CNT_5709; + } + else + { + max_nwuf_cnt = LM_MAX_NWUF_CNT; + } + + for(j = 0; j < max_nwuf_cnt; j++) + { + pdev->nwuf_list.nwuf_arr[j].size = 0; + + for(k = 0; k < LM_NWUF_PATTERN_MASK_SIZE; k++) + { + pdev->nwuf_list.nwuf_arr[j].mask[k] = 0; + } + + for(k = 0; k < LM_NWUF_PATTERN_SIZE; k++) + { + pdev->nwuf_list.nwuf_arr[j].pattern[k] = 0xff; + } + } + + pdev->nwuf_list.cnt = 0; +} /* lm_clear_nwuf */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u32_t +init_nwuf_5709( + lm_device_t *pdev, + lm_nwuf_list_t *nwuf_list) +{ + lm_nwuf_t *nwuf; + u16_t prev_val; + u32_t nwuf_len; + u32_t nwuf_cnt; + u32_t offset; + u8_t mask; + u32_t val; + u32_t idx; + u8_t bit; + u16_t pattern_size; + u32_t nwuf_size[LM_MAX_NWUF_CNT_5709]; + + DbgBreakIf(CHIP_NUM(pdev) != CHIP_NUM_5709); + DbgBreakIf(LM_NWUF_PATTERN_SIZE > 128); + DbgBreakIf(LM_MAX_NWUF_CNT_5709 > 8); + + REG_WR(pdev, rpm.rpm_acpi_byte_enable_ctrl, RPM_ACPI_BYTE_ENABLE_CTRL_INIT); + + for(idx = 0; idx < LM_MAX_NWUF_CNT_5709; idx++) + { + nwuf = &nwuf_list->nwuf_arr[idx]; + nwuf_size[idx] = nwuf->size; + } + for(idx = 0; idx < 1000; idx++) + { + mm_wait(pdev, 5); + + REG_RD(pdev, rpm.rpm_acpi_byte_enable_ctrl, &val); + if((val & RPM_ACPI_BYTE_ENABLE_CTRL_INIT) == 0) + { + break; + } + } + DbgBreakIf(val & RPM_ACPI_BYTE_ENABLE_CTRL_INIT); + + val = 0; + for(idx = 0; idx < 4; idx++) + { + nwuf = &nwuf_list->nwuf_arr[idx]; + pattern_size = nwuf->size >>16; + nwuf->size &= 0xffff; + + DbgBreakIf(nwuf->size > LM_NWUF_PATTERN_MASK_SIZE); + + if(nwuf->size == 0) + { + continue; + } + if (pattern_size) + { + val |= (pattern_size) << ((3 - idx) * 8); + } + else + { + val |= (nwuf->size * 8) << ((3 - idx) * 8); + } + } + REG_WR(pdev, rpm.rpm_acpi_pattern_len0, val); + + val = 0; + for(idx = 4; idx < LM_MAX_NWUF_CNT_5709; idx++) + { + nwuf = &nwuf_list->nwuf_arr[idx]; + pattern_size = nwuf->size >>16; + nwuf->size &= 0xffff; + + DbgBreakIf(nwuf->size > LM_NWUF_PATTERN_MASK_SIZE); + + if(nwuf->size == 0) + { + continue; + } + + if (pattern_size) + { + val |= (pattern_size) << ((7 - idx) * 8); + } + else + { + val |= (nwuf->size * 8) << ((7 - idx) * 8); + } + + // old code val |= (nwuf->size * 8) << ((7 - idx) * 8); + } + REG_WR(pdev, rpm.rpm_acpi_pattern_len1, val); + + for(offset = 0; offset < LM_NWUF_PATTERN_SIZE; offset++) + { + val = 0; + + for(idx = 0; idx < LM_MAX_NWUF_CNT_5709; idx++) + { + nwuf = &nwuf_list->nwuf_arr[idx]; + pattern_size = nwuf_size[idx]>>16; + + if(nwuf->size == 0 || offset > nwuf->size * 8) + { + continue; + } + + mask = nwuf->mask[offset/8]; + bit = offset % 8; + + if(mask & (1 << bit)) + { + val |= 1 << idx; + } + } + + REG_WR(pdev, rpm.rpm_acpi_data, val); + + /* Perform the Write to the byte enable memory, The actual pattern + * byte enables start from byte address 2. the first two bytes of + * a packet are always 0 and inserted by EMAC to align the IP header + * to 4-byte boudary. */ + REG_WR( + pdev, + rpm.rpm_acpi_byte_enable_ctrl, + RPM_ACPI_BYTE_ENABLE_CTRL_WR | offset); + REG_RD(pdev, rpm.rpm_acpi_byte_enable_ctrl, &val); + DbgBreakIf(val & RPM_ACPI_BYTE_ENABLE_CTRL_WR); + } + + nwuf_cnt = 0; + + for(idx = 0; idx < LM_MAX_NWUF_CNT_5709; idx++) + { + REG_WR( + pdev, + rpm.rpm_acpi_pattern_ctrl, + RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR|idx); + REG_RD(pdev, rpm.rpm_acpi_pattern_ctrl, &val); + DbgBreakIf(val & RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR); + + nwuf = &nwuf_list->nwuf_arr[idx]; + if(nwuf->size == 0) + { + continue; + } + pattern_size = nwuf_size[idx]>>16; + + /* The CRC calculation is done on 64-bit data. So the length of the + * pattern over which CRC needs to be calculated needs to be padded + * by 0 to 7 bytes to make it 8 byte aligned. */ + + if (pattern_size) + { + nwuf_len = pattern_size; + } + else + { + nwuf_len = (nwuf->size * 8); + } + nwuf_len += 2; /* 2-byte padding. */ + nwuf_len = (nwuf_len + 3) & ~3; + + prev_val = 0; + + for(offset = 0; offset < nwuf_len; offset += 4) + { + val = 0; + + for(bit = 0; bit < 4; bit++) + { + if (pattern_size) + { + if(offset < pattern_size) + { + mask = nwuf->mask[offset/8]; + } + else + { + mask = 0; + } + } + else + { + if(offset < nwuf->size * 8) + { + mask = nwuf->mask[offset/8]; + } + else + { + mask = 0; + } + } + if(mask & (1 << (bit + (offset % 8)))) + { + val |= nwuf->pattern[offset+bit] << ((3 - bit) * 8); + } + } + + REG_WR(pdev, rpm.rpm_acpi_data, (prev_val << 16) | (val >> 16)); + prev_val = (u16_t) val; + + REG_WR( + pdev, + rpm.rpm_acpi_pattern_ctrl, + RPM_ACPI_PATTERN_CTRL_WR | idx); + REG_RD(pdev, rpm.rpm_acpi_pattern_ctrl, &val); + DbgBreakIf(val & RPM_ACPI_PATTERN_CTRL_WR); + } + + nwuf_cnt++; + } + for(idx = 0; idx < LM_MAX_NWUF_CNT_5709; idx++) + { + nwuf = &nwuf_list->nwuf_arr[idx]; + nwuf->size = nwuf_size[idx]; + } + + return nwuf_cnt; +} /* init_nwuf_5709 */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u32_t +init_nwuf_5706( + lm_device_t *pdev, + lm_nwuf_list_t *nwuf_list) +{ + typedef union _acpi_wol_pat_t + { + #if defined(LITTLE_ENDIAN) + struct _acpi_wol_pat_as_u8_t + { + u8_t pat[7]; + u8_t ena; + } as_u8; + + struct _acpi_wol_pat_as_u32_t + { + u32_t low; + u32_t high; + } as_u32; + #elif defined(BIG_ENDIAN) + struct _acpi_wol_pat_as_u8_t + { + u8_t ena; + u8_t pat[7]; + } as_u8; + + struct _acpi_wol_pat_as_u32_t + { + u32_t high; + u32_t low; + } as_u32; + #endif + } acpi_wol_pat_t; + + u32_t filler_pattern_idx; + acpi_wol_pat_t wol_pat; + u32_t pattern_cnt; + u8_t val; + u32_t j; + u32_t k; + u8_t idx; + u32_t nwuf_size[LM_MAX_NWUF_CNT]; + lm_nwuf_t *nwuf; + + /* + * 06/08 doesn't seem to have pattern size like those of 09 + */ + for(idx = 0; idx < LM_MAX_NWUF_CNT; idx++) + { + nwuf = &nwuf_list->nwuf_arr[idx]; + nwuf_size[idx] = nwuf->size; + nwuf->size &= 0xffff; + } + + DbgBreakIf(LM_NWUF_PATTERN_SIZE > 128); + DbgBreakIf(LM_MAX_NWUF_CNT > 7); + DbgBreakIf(CHIP_NUM(pdev) != CHIP_NUM_5706 && + CHIP_NUM(pdev) != CHIP_NUM_5708); + + /* If a pattern is not present, we will fill the pattern buffer + * with the pattern with this index. The pattern buffer cannot + * have an empty pattern otherwise we will get a false detection. */ + filler_pattern_idx = 0; + + /* Find out the number of patterns. */ + pattern_cnt = 0; + for(k = 0; k < LM_MAX_NWUF_CNT; k++) + { + if(nwuf_list->nwuf_arr[k].size) + { + pattern_cnt++; + filler_pattern_idx = k; + } + } + + /* Program the pattern. */ + for(j = 0; j < LM_NWUF_PATTERN_SIZE; j++) + { + wol_pat.as_u32.low = 0x0; + wol_pat.as_u32.high = 0x0; + + /* Build the enable bits. */ + wol_pat.as_u8.ena = 0; + for(k = 0; k < LM_MAX_NWUF_CNT; k++) + { + if(nwuf_list->nwuf_arr[k].size == 0) + { + val = nwuf_list->nwuf_arr[filler_pattern_idx].mask[j/8]; + } + else if((j/8) >= nwuf_list->nwuf_arr[k].size) + { + val = 0; + } + else + { + val = nwuf_list->nwuf_arr[k].mask[j/8]; + } + + /* Determine if a byte is enabled for comparision. */ + if(val & (1 << (j % 8))) + { + wol_pat.as_u8.ena |= 1 << k; + } + } + + DbgMessage1(pdev, VERBOSE, "%02x: ", j); + + /* Enter the byte of each pattern that will be used for comparison. */ + for(k = 0; k < LM_MAX_NWUF_CNT; k++) + { + /* Check to see if we are at the end of the pattern. 0xff + * will terminate the pattern. If there is no pattern present + * we cannot terminate with 0xff. */ + if(nwuf_list->nwuf_arr[k].size == 0) + { + val = nwuf_list->nwuf_arr[filler_pattern_idx].pattern[j]; + DbgMessage(pdev, VERBOSE, "xx "); + } + else if((j/8) >= nwuf_list->nwuf_arr[k].size) + { + val = 0xff; + DbgMessage(pdev, VERBOSE, "ff "); + } + else + { + val = nwuf_list->nwuf_arr[k].pattern[j]; + DbgMessage1(pdev, VERBOSE, "%02x ", val); + } + + /* Format of the ACPI_WOL pattern from low address to high on a + * little endian system: + * pat0_6 pat0_5 pat0_4 pat0_3 pat0_2 pat0_1 pat0_0 ena0 + * + * on a big endian system: + * ena0 pat0_0 pat0_1 pat0_2 pat0_3 pat0_4 pat0_5 pat0_6 */ + #if defined(LITTLE_ENDIAN) + wol_pat.as_u8.pat[6-k] = val; + #elif defined(BIG_ENDIAN) + wol_pat.as_u8.pat[k] = val; + #endif + } + + DbgMessage2(pdev, VERBOSE, " %08x %08x\n", + wol_pat.as_u32.high, wol_pat.as_u32.low); + + /* Swap the even 64-bit word with the odd 64-bit word. This is + * they way it works. Don't ask why. So the values written + * to the header buffer looks as follows: + * 0x0000: ena1 pat1_0 pat1_1 pat1_2 + * 0x0004: pat1_3 pat1_4 pat1_5 pat1_6 + * 0x0008: ena0 pat0_0 pat0_1 pat0_2 + * 0x000c: pat0_3 pat0_4 pat0_5 pat0_6 + * 0x0010: ena3 pat3_0 pat3_1 pat3_2 + * 0x0014: pat3_3 pat3_4 pat3_5 pat3_6 + * 0x0018: ena2 pat2_0 pat2_1 pat2_2 + * 0x001c: pat2_3 pat2_4 pat2_5 pat2_6 */ + if(j % 2) + { + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, tas.tas_thbuf[(j-1) * 2]), + wol_pat.as_u32.high); + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, tas.tas_thbuf[(j-1) * 2 + 1]), + wol_pat.as_u32.low); + } + else + { + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, tas.tas_thbuf[(j+1) * 2]), + wol_pat.as_u32.high); + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, tas.tas_thbuf[(j+1) * 2 + 1]), + wol_pat.as_u32.low); + } + } + + for(idx = 0; idx < LM_MAX_NWUF_CNT; idx++) + { + nwuf = &nwuf_list->nwuf_arr[idx]; + nwuf->size = nwuf_size[idx]; + } + + return pattern_cnt; +} /* init_nwuf_5706 */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u32_t +init_nwuf( + lm_device_t *pdev, + lm_nwuf_list_t *nwuf_list) +{ + u32_t nwuf_cnt; + + if(CHIP_NUM(pdev) == CHIP_NUM_5706 || CHIP_NUM(pdev) == CHIP_NUM_5708) + { + nwuf_cnt = init_nwuf_5706(pdev, nwuf_list); + } + else + { + nwuf_cnt = init_nwuf_5709(pdev, nwuf_list); + } + + return nwuf_cnt; +} /* init_nwuf */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +set_d0_power_state( + lm_device_t *pdev, + u8_t set_pci_pm) +{ + u32_t val; + u32_t idx; + + /* This step should be done by the OS or the caller. Windows is + * already doing this. */ + if(set_pci_pm) + { + /* Set the device to D0 state. If a device is already in D3 state, + * we will not be able to read the PCICFG_PM_CSR register using the + * PCI memory command, we need to use config access here. */ + (void) mm_read_pci( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_pm_csr), + &val); + + /* Set the device to D0 state. This may be already done by the OS. */ + val &= ~PCICFG_PM_CSR_STATE; + val |= PCICFG_PM_CSR_STATE_D0 | PCICFG_PM_CSR_PME_STATUS; + + (void) mm_write_pci( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_pm_csr), + val); + } + + /* With 5706_A1, the chip gets a reset coming out of D3. Wait + * for the boot to code finish running before we continue. Without + * this wait, we could run into lockup or the PHY may not work. */ + if(CHIP_ID(pdev) == CHIP_ID_5706_A1) + { + for(idx = 0; idx < 1000; idx++) + { + mm_wait(pdev, 15); + } + } + + /* Clear the ACPI_RCVD and MPKT_RCVD bits and disable magic packet. */ + REG_RD(pdev, emac.emac_mode, &val); + val |= EMAC_MODE_MPKT_RCVD | EMAC_MODE_ACPI_RCVD; + val &= ~EMAC_MODE_MPKT; + REG_WR(pdev, emac.emac_mode, val); + + /* Disable interesting packet detection. */ + REG_RD(pdev, rpm.rpm_config, &val); + val &= ~RPM_CONFIG_ACPI_ENA; + REG_WR(pdev, rpm.rpm_config, val); +} /* set_d0_power_state */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC void +set_d3_power_state( + lm_device_t *pdev, + lm_wake_up_mode_t wake_up_mode, + u8_t set_pci_pm) +{ + u32_t fw_timed_out; + u32_t reset_reason; + u32_t gpio_pin; + u32_t val; + u32_t cnt; + + /* Set up magic and interesting packet detection. */ + if(wake_up_mode & (LM_WAKE_UP_MODE_MAGIC_PACKET | LM_WAKE_UP_MODE_NWUF)) + { + /* Enable magic packet detection. */ + REG_RD(pdev, emac.emac_mode, &val); + if(wake_up_mode & LM_WAKE_UP_MODE_MAGIC_PACKET) + { + val |= EMAC_MODE_MPKT; + } + else + { + val &= ~EMAC_MODE_MPKT; + } + + /* Enable port mode. */ + val &= ~EMAC_MODE_PORT; + if(CHIP_REV(pdev) == CHIP_REV_FPGA || CHIP_REV(pdev) == CHIP_REV_IKOS) + { + /* IKOS or FPGA always run in GMII mode even if its actual + * link speed is 10mb or 100mb. */ + val |= EMAC_MODE_PORT_GMII; + } + else + { + val |= EMAC_MODE_PORT_MII; + } + val |= EMAC_MODE_MPKT_RCVD | EMAC_MODE_ACPI_RCVD; + + REG_WR(pdev, emac.emac_mode, val); + + /* Set up the receive mask. */ + (void) lm_set_rx_mask( + pdev, + RX_FILTER_USER_IDX0, + LM_RX_MASK_ACCEPT_UNICAST | + LM_RX_MASK_ACCEPT_ALL_MULTICAST | + LM_RX_MASK_ACCEPT_BROADCAST); + + /* The first four address slots are use for magic packet detection. + * we need to initialize all four address slots. */ + for(cnt = 0; cnt < 4; cnt++) + { + (void) lm_set_mac_addr(pdev, cnt, pdev->params.mac_addr); + } + + /* Need to enable EMAC and RPM for WOL. */ + REG_WR( + pdev, + misc.misc_enable_set_bits, + MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE | + MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE | + MISC_ENABLE_SET_BITS_EMAC_ENABLE); + + /* Enable interesting packet detection. This must be done after + * the necessary blocks are enabled, otherwise we may wake-up on + * a bogus first packet. Need to document this in prm. */ + REG_RD(pdev, rpm.rpm_config, &val); + if(wake_up_mode & LM_WAKE_UP_MODE_NWUF) + { + REG_WR(pdev, rpm.rpm_config, val & ~RPM_CONFIG_ACPI_ENA); + + /* Also need to be documented in the prm - to prevent a false + * detection, we need to disable ACP_EN if there is no pattern + * programmed. There is no way of preventing false detection + * by intializing the pattern buffer a certain way. */ + if(init_nwuf(pdev, &pdev->nwuf_list)) + { + val |= RPM_CONFIG_ACPI_ENA; + } + else + { + val &= ~RPM_CONFIG_ACPI_ENA; + } + } + else + { + val &= ~RPM_CONFIG_ACPI_ENA; + } + REG_WR(pdev, rpm.rpm_config, val); + + /* xinan requires rbuf to be enabled. enabling it for teton + * does not hurt. */ + REG_WR( + pdev, + misc.misc_enable_set_bits, + MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE); + + reset_reason = LM_REASON_WOL_SUSPEND; + } + else + { + reset_reason = LM_REASON_NO_WOL_SUSPEND; + } + + /* Allow the firmware to make any final changes to the chip before + * we go into D3 mode. The timeout period is longer because the + * firwmare could take more time to download management firmware + * which occurs during this stage of the reset. */ + fw_timed_out = fw_reset_sync( + pdev, + reset_reason, + DRV_MSG_DATA_WAIT3, + FW_ACK_TIME_OUT_MS*1000 * 3); + + /* If the firmware is not running, we have to switch to vaux power, + * otherwise let the firmware do it. */ + if(fw_timed_out) + { + /* Power down the PHY. */ + if(pdev->params.enable_remote_phy == FALSE) + { + if(CHIP_REV(pdev) != CHIP_REV_FPGA && + CHIP_REV(pdev) != CHIP_REV_IKOS) + { + (void) lm_mwrite( + pdev, + pdev->params.phy_addr, + 0x1c, + 0xa821); + } + } + + /* Minimum core clock for a particular link. + * 10Mb core_clk = 6.25Mhz + * 100Mb core_clk = 12Mhz + * 1Gb core_clk = 100Mhz (use PLL) + * + * The driver is configured to autoneg to 10/100Mb for WOL mode. So + * the core clock needs to be configured to 12Mhz. */ + REG_RD(pdev, misc.misc_clock_control_bits, &val); + val &= ~(MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE | + MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT | + MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_TE); + + /* Select the 12.5m alt clock. */ + REG_WR( + pdev, + misc.misc_clock_control_bits, + MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12_TE | val); + + /* Switch to the alt clock. */ + REG_WR( + pdev, + misc.misc_clock_control_bits, + MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12_TE | + MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT | + val); + + /* Disable core clock to non-wol blocks. */ + REG_WR( + pdev, + misc.misc_clock_control_bits, + MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12_TE | + MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT | + MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE | + val); + + gpio_pin = 1 << 2; /* GPIO 2 */ + + /* Switch to vaux power by bring GPIO2 to low. */ + REG_RD(pdev, misc.misc_spio, &val); + val &= ~(gpio_pin << 24); /* use this gpio as output. */ + val |= gpio_pin << 16; /* clear the gpio. */ + REG_WR(pdev, misc.misc_spio, val); + + /* This step should be done by the OS or the caller. Windows is + * already doing this. */ + if(set_pci_pm) + { + /* Set the device to D3 state. */ + REG_RD_OFFSET( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_pm_csr), + &val); + + val &= ~PCICFG_PM_CSR_STATE; + val |= PCICFG_PM_CSR_STATE_D3_HOT; + + REG_WR_OFFSET( + pdev, + OFFSETOF(reg_space_t, pci_config.pcicfg_pm_csr), + val); + } + } +} /* set_d3_power_state */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_set_power_state( + lm_device_t *pdev, + lm_power_state_t power_state, + lm_wake_up_mode_t wake_up_mode, /* Valid when power_state is D3. */ + u8_t set_pci_pm) +{ + if(power_state == LM_POWER_STATE_D0) + { + set_d0_power_state(pdev, set_pci_pm); + } + else + { + set_d3_power_state(pdev, wake_up_mode, set_pci_pm); + } +} /* lm_set_power_state */ + + + +#ifndef EXCLUDE_KQE_SUPPORT +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +u32_t +lm_submit_kernel_wqes( + lm_device_t *pdev, + kwqe_t *wqes[], + u32_t num_wqes) +{ + kwqe_t *prod_qe; + u16_t prod_idx; + u32_t qe_cnt; + + if(num_wqes > pdev->kq_info.kwqe_left) + { + pdev->kq_info.no_kwq_bd_left++; + + return 0; + } + + pdev->kq_info.kwqe_left -= num_wqes; + + prod_qe = pdev->kq_info.kwq_prod_qe; + prod_idx = pdev->kq_info.kwq_prod_idx; + + qe_cnt = num_wqes; + while(qe_cnt) + { + *prod_qe = *(*wqes); + + if(prod_qe == pdev->kq_info.kwq_last_qe) + { + prod_qe = pdev->kq_info.kwq_virt; + } + else + { + prod_qe++; + } + + wqes++; + prod_idx++; + qe_cnt--; + } + + pdev->kq_info.kwq_prod_qe = prod_qe; + pdev->kq_info.kwq_prod_idx = prod_idx; + + MBQ_WR16( + pdev, + GET_CID(pdev->kq_info.kwq_cid_addr), + OFFSETOF(krnlq_context_t, krnlq_host_qidx), + prod_idx); + + return num_wqes; +} /* lm_submit_kernel_wqes */ +#endif /* EXCLUDE_KQE_SUPPORT */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_interrupt_status_t +lm_get_interrupt_status( + lm_device_t *pdev) +{ + lm_interrupt_status_t intr_status; + u32_t deasserted_attns; + u32_t asserted_attns; + lm_rx_chain_t *rxq; + lm_tx_chain_t *txq; + u16_t hw_con_idx; + u32_t val; + u32_t idx; + + intr_status = LM_NO_EVENT_ACTIVE; + + /* Determine link change status. */ + if(pdev->params.link_chng_mode == LINK_CHNG_MODE_USE_STATUS_REG) + { + REG_RD(pdev, emac.emac_status, &val); + if(pdev->params.phy_int_mode == PHY_INT_MODE_MI_INTERRUPT) + { + if(val & EMAC_STATUS_MI_INT) + { + intr_status |= LM_PHY_EVENT_ACTIVE; + } + } + else if(val & EMAC_STATUS_LINK_CHANGE) + { + intr_status |= LM_PHY_EVENT_ACTIVE; + } + + GET_ATTN_CHNG_BITS(pdev, &asserted_attns, &deasserted_attns); + } + else + { + GET_ATTN_CHNG_BITS(pdev, &asserted_attns, &deasserted_attns); + + if(asserted_attns & STATUS_ATTN_BITS_LINK_STATE) + { + intr_status |= LM_PHY_EVENT_ACTIVE; + } + else if(deasserted_attns & STATUS_ATTN_BITS_LINK_STATE) + { + intr_status |= LM_PHY_EVENT_ACTIVE; + } + } + + /* Get driver pulse event. MCP uses the TIMER_ABORT attention to + * signal to the driver to write a driver pulse to the firmware. */ + if((asserted_attns & STATUS_ATTN_BITS_TIMER_ABORT) || + (deasserted_attns & STATUS_ATTN_BITS_TIMER_ABORT)) + { + if(pdev->params.enable_remote_phy) + { + REG_RD_IND( + pdev, + pdev->hw_info.shmem_base + + OFFSETOF(shmem_region_t, fw_evt_mb.fw_evt_code_mb), + &val); + + if(val == 0) + { + intr_status |= LM_KNOCK_KNOCK_EVENT; + } + else if(val == FW_EVT_CODE_LINK_STATUS_CHANGE_EVENT) + { + intr_status |= LM_PHY_EVENT_ACTIVE; + } + else + { + DbgBreakMsg("not a valid fw event.\n"); + } + } + else + { + intr_status |= LM_KNOCK_KNOCK_EVENT; + } + + if(asserted_attns & STATUS_ATTN_BITS_TIMER_ABORT) + { + REG_WR( + pdev, + pci_config.pcicfg_status_bit_set_cmd, + asserted_attns & STATUS_ATTN_BITS_TIMER_ABORT); + } + else + { + REG_WR( + pdev, + pci_config.pcicfg_status_bit_clear_cmd, + deasserted_attns & STATUS_ATTN_BITS_TIMER_ABORT); + } + } + + /* get l2 tx events. */ + for(idx = 0; idx < pdev->tx_info.num_txq; idx++) + { + txq = &pdev->tx_info.chain[idx]; + + hw_con_idx = *txq->hw_con_idx_ptr; + if((hw_con_idx & MAX_BD_PER_PAGE) == MAX_BD_PER_PAGE) + { + hw_con_idx++; + } + + if(hw_con_idx != txq->con_idx) + { + intr_status |= LM_TX0_EVENT_ACTIVE << txq->idx; + } + } + + /* get l2 rx events. */ + for(idx = 0; idx < pdev->rx_info.num_rxq; idx++) + { + rxq = &pdev->rx_info.chain[idx]; + + hw_con_idx = *rxq->hw_con_idx_ptr; + if((hw_con_idx & MAX_BD_PER_PAGE) == MAX_BD_PER_PAGE) + { + hw_con_idx++; + } + + if(hw_con_idx != rxq->con_idx) + { + intr_status |= LM_RX0_EVENT_ACTIVE << rxq->idx; + } + } + + #ifndef EXCLUDE_KQE_SUPPORT + if(CHIP_NUM(pdev) == CHIP_NUM_5706 || CHIP_NUM(pdev) == CHIP_NUM_5708) + { + /* HC install problem: as a workaround, rx_quick_consumer_index15 + * is high jacked for use as cmd_con_idx. The original cmd_con_idx + * is not used. */ + if(pdev->kq_info.kwq_con_idx != + pdev->vars.status_virt->deflt.status_rx_quick_consumer_index15) + { + intr_status |= LM_KWQ_EVENT_ACTIVE; + } + } + else + { + if(pdev->kq_info.kwq_con_idx != + pdev->vars.status_virt->deflt.status_cmd_consumer_index) + { + intr_status |= LM_KWQ_EVENT_ACTIVE; + } + } + + if(pdev->kq_info.kcq_con_idx != + pdev->vars.status_virt->deflt.status_completion_producer_index) + { + intr_status |= LM_KCQ_EVENT_ACTIVE; + } + #endif + + #if INCLUDE_OFLD_SUPPORT + else if(pdev->params.hcopy_desc_cnt) + { + if(pdev->ofld.hcopy_chain.con_idx != + *(pdev->ofld.hcopy_chain.hw_con_idx_ptr)) + { + intr_status |= LM_KCQ_EVENT_ACTIVE; + } + } + #endif + + return intr_status; +} /* lm_get_interrupt_status */ + + + +#ifndef EXCLUDE_KQE_SUPPORT +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_ack_completed_wqes( + lm_device_t *pdev) +{ + u16_t new_con_idx; + kwqe_t *con_qe; + u16_t num_wqes; + u16_t con_idx; + + /* HC install problem: as a workaround, rx_quick_consumer_index15 + * is high jacked for use as cmd_con_idx. The original cmd_con_idx + * is not used. */ + if(CHIP_NUM(pdev) == CHIP_NUM_5706 || CHIP_NUM(pdev) == CHIP_NUM_5708) + { + new_con_idx = + pdev->vars.status_virt->deflt.status_rx_quick_consumer_index15; + } + else + { + new_con_idx = pdev->vars.status_virt->deflt.status_cmd_consumer_index; + } + + num_wqes = (u16_t) S16_SUB(new_con_idx, pdev->kq_info.kwq_con_idx); + pdev->kq_info.kwqe_left += num_wqes; + + con_idx = new_con_idx; + con_qe = pdev->kq_info.kwq_con_qe + num_wqes; + + /* Check for con_qe wrap around. */ + if((u8_t *) con_qe > (u8_t *) pdev->kq_info.kwq_last_qe) + { + con_qe = (kwqe_t *) ((u8_t *) pdev->kq_info.kwq_virt + + ((u8_t *) con_qe - (u8_t *) pdev->kq_info.kwq_last_qe)); + con_qe--; + } + + pdev->kq_info.kwq_con_idx = con_idx; + pdev->kq_info.kwq_con_qe = con_qe; + + /* Make sure the con_qe and con_idx are consistent. */ + DbgBreakIf(((((u8_t *) con_qe - (u8_t *) pdev->kq_info.kwq_virt) / + sizeof(kwqe_t)) & 0x7f) != (con_idx & 0x7f)); + + #if DBG + /* Make sure all the kwqes are accounted for. */ + if(S16_SUB(pdev->kq_info.kwq_prod_idx, con_idx) >= 0) + { + num_wqes = pdev->kq_info.kwqe_left + + (u32_t) S16_SUB(pdev->kq_info.kwq_prod_idx, con_idx); + } + else + { + num_wqes = pdev->kq_info.kwqe_left + 0x10000 - con_idx + + pdev->kq_info.kwq_prod_idx; + } + + DbgBreakIf(num_wqes != (LM_PAGE_SIZE/sizeof(kwqe_t)) * + pdev->params.kwq_page_cnt - 1); + #endif +} /* lm_ack_completed_wqes */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +u32_t +lm_get_kernel_cqes( + lm_device_t *pdev, + kcqe_t *cqe_ptr[], + u32_t ptr_cnt) +{ + kcqe_t *con_qe; + u16_t prod_idx; + u32_t num_cqes; + u16_t con_idx; + + DbgMessage(pdev, VERBOSEint, "### lm_get_kernel_cqes\n"); + + con_idx = pdev->kq_info.kcq_con_idx; + con_qe = pdev->kq_info.kcq_con_qe; + + DbgBreakIf(((((u8_t *) con_qe - (u8_t *) pdev->kq_info.kcq_virt) / + sizeof(kcqe_t)) & 0x7f) != (con_idx & 0x7f)); + + num_cqes = 0; + prod_idx = pdev->vars.status_virt->deflt.status_completion_producer_index; + + while(con_idx != prod_idx && num_cqes != ptr_cnt) + { + *cqe_ptr = con_qe; + cqe_ptr++; + num_cqes++; + con_idx++; + + if(con_qe == pdev->kq_info.kcq_last_qe) + { + con_qe = pdev->kq_info.kcq_virt; + } + else + { + con_qe++; + } + + prod_idx = + pdev->vars.status_virt->deflt.status_completion_producer_index; + } + + /* Make sure the last entry in the array does not have the 'next' + * bit set. We want to ensure the array contains all the cqes + * for a completion. + * + * This piece of code also takes care of the case where a completion + * spans multiple kcqes and not all the kcqes have been dma'd to + * the host. For example, if a completion consists of A, B, C, and D + * kcqes. The status block may tell us A and B have been dma'd. In + * this case, we don't want to return kcqes A and B in the array. */ + cqe_ptr--; + while(num_cqes && ((*cqe_ptr)->kcqe_flags & KCQE_FLAGS_NEXT)) + { + num_cqes--; + cqe_ptr--; + } + + DbgBreakIf(num_cqes == 0); + + return num_cqes; +} /* lm_get_kernel_cqes */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +u8_t +lm_ack_kernel_cqes( + lm_device_t *pdev, + u32_t num_cqes) +{ + kcqe_t *con_qe; + u16_t prod_idx; + u16_t con_idx; + + DbgMessage(pdev, VERBOSEint, "### lm_ack_kernel_cqes\n"); + + con_idx = pdev->kq_info.kcq_con_idx; + + if(num_cqes) + { + /* Advance the consumer index and the con_qe pointer */ + con_idx += (u16_t) num_cqes; + con_qe = pdev->kq_info.kcq_con_qe + num_cqes; + + /* Check for con_qe wrap around. */ + if((u8_t *) con_qe > (u8_t *) pdev->kq_info.kcq_last_qe) + { + con_qe = (kcqe_t *) ((u8_t *) pdev->kq_info.kcq_virt + + ((u8_t *) con_qe - (u8_t *) pdev->kq_info.kcq_last_qe)); + con_qe--; + } + + pdev->kq_info.kcq_con_idx = con_idx; + pdev->kq_info.kcq_con_qe = con_qe; + + /* Don't acknowledge the last 'kcq_history_size' entries so the + * chip will not over write them with new entries. We are doing + * this to have a history of the kcq entries for debugging. */ + if(pdev->params.kcq_history_size) + { + /* The con_idx should always be ahead of history_kcq_con_idx. */ + DbgBreakIf(S16_SUB(con_idx, pdev->kq_info.history_kcq_con_idx) < 0); + + /* Number of entries between con_idx and history_kcq_con_idx. */ + num_cqes = (u32_t) S16_SUB( + con_idx, + pdev->kq_info.history_kcq_con_idx); + + /* Don't advance the consumer index if the number of history + * entries is less than 'kcq_history_size'. */ + if(num_cqes >= pdev->params.kcq_history_size) + { + /* Make sure we will have at most kcq_history_size entires. */ + num_cqes -= pdev->params.kcq_history_size; + + DbgBreakIf(num_cqes > pdev->params.kcq_history_size); + + /* Advance the consumer index and the con_qe pointer */ + pdev->kq_info.history_kcq_con_idx += (u16_t) num_cqes; + con_qe = pdev->kq_info.history_kcq_con_qe + num_cqes; + + /* Check for con_qe wrap around. */ + if((u8_t *) con_qe > (u8_t *) pdev->kq_info.kcq_last_qe) + { + con_qe = (kcqe_t *) ((u8_t *) pdev->kq_info.kcq_virt + + ((u8_t *) con_qe - + (u8_t *) pdev->kq_info.kcq_last_qe)); + con_qe--; + } + pdev->kq_info.history_kcq_con_qe = con_qe; + + MBQ_WR16( + pdev, + GET_CID(pdev->kq_info.kcq_cid_addr), + OFFSETOF(krnlq_context_t, krnlq_host_qidx), + pdev->kq_info.history_kcq_con_idx); + } + } + else + { + MBQ_WR16( + pdev, + GET_CID(pdev->kq_info.kcq_cid_addr), + OFFSETOF(krnlq_context_t, krnlq_host_qidx), + con_idx); + } + } + + prod_idx = pdev->vars.status_virt->deflt.status_completion_producer_index; + + DbgBreakIf(S16_SUB(prod_idx, con_idx) < 0); + + return con_idx != prod_idx; +} /* lm_ack_kernel_cqes */ +#endif /* EXCLUDE_KQE_SUPPORT */ + + + +#ifndef EXCLUDE_RSS_SUPPORT +#if RSS_LOOKUP_TABLE_WA +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +u64_t +rss_f64( + u8_t* key, + u8_t s, + u8_t e + ) +{ + u64_t f; + + for( f=0; s<=e; ++s ) + { + f = (f << 8); + f |= key[s]; + } + + return f; +} + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +u32_t +rss_hash_byte( + u8_t* key, + u8_t byte, + u8_t s, + u8_t e, + u32_t rst + ) +{ + u8_t i; + u64_t key_msb; + + key_msb = rss_f64(key, s,e); + + for( i=0x80; i!=0; i>>=1 ) + { + if( i & byte ) + { + u32_t k; + + k = (u32_t)(key_msb >> 32); + rst ^= k; + } + key_msb = (key_msb << 1); + } + + return rst; +} + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +rss_gen_one_table( + u8_t* key, + u8_t s, + u8_t e, + u32_t* gtbl + ) +{ + u32_t i; + + for( i = 0; i < 256; ++i ) + { + gtbl[i] = rss_hash_byte( key, (u8_t)i, s, e, 0 ); + } +} + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +rss_gen_tables( + u8_t* key, + u32_t* tables + ) +{ + u8_t t; + + for( t = 0; t < 12; ++t ) + { + rss_gen_one_table( key, t, (u8_t)(t+7), tables ); + tables += 256; + } +} +#endif + + +#ifndef LM_NON_LEGACY_MODE_SUPPORT +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_enable_rss( + lm_device_t *pdev, + lm_rss_hash_t hash_type, + u8_t *indirection_table, + u32_t table_size, + u8_t *hash_key, + u32_t key_size) +{ + l2_kwqe_rss_table_update_t *rss_update; + u8_t rss_key[RSS_HASH_KEY_SIZE]; + lm_address_t rss_table_phy; + u8_t *rss_table_virt; + kwqe_t *prod_qe; + u16_t prod_idx; + u32_t idx; + u32_t val; + + if(pdev->kq_info.kwqe_left < 2) + { + pdev->kq_info.no_kwq_bd_left++; + return LM_STATUS_RESOURCE; + } + + pdev->kq_info.kwqe_left -= 2; + + DbgBreakIf(key_size > RSS_HASH_KEY_SIZE); + + /* Initialize the rss key array. */ + if(key_size > RSS_HASH_KEY_SIZE) + { + key_size = RSS_HASH_KEY_SIZE; + } + + for(idx = 0; idx < key_size; idx++) + { + rss_key[idx] = hash_key[idx]; + } + + for(idx = key_size; idx < RSS_HASH_KEY_SIZE; idx++) + { + rss_key[idx] = 0; + } + + DbgBreakIf(table_size > RSS_INDIRECTION_TABLE_SIZE); + + if(table_size > RSS_INDIRECTION_TABLE_SIZE) + { + table_size = RSS_INDIRECTION_TABLE_SIZE; + } + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + REG_RD(pdev, rlup.rlup_rss_config, &val); + val &= ~RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI; + val &= ~RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI; + REG_WR(pdev, rlup.rlup_rss_config, val); + + val = (rss_key[0] << 24) | + (rss_key[1] << 16) | + (rss_key[2] << 8) | + rss_key[3]; + REG_WR(pdev, rlup.rlup_rss_key1, val); + + val = (rss_key[4] << 24) | + (rss_key[5] << 16) | + (rss_key[6] << 8) | + rss_key[7]; + REG_WR(pdev, rlup.rlup_rss_key2, val); + + val = (rss_key[8] << 24) | + (rss_key[9] << 16) | + (rss_key[10] << 8) | + rss_key[11]; + REG_WR(pdev, rlup.rlup_rss_key3, val); + + val = (rss_key[12] << 24) | + (rss_key[13] << 16) | + (rss_key[14] << 8) | + rss_key[15]; + REG_WR(pdev, rlup.rlup_rss_key4, val); + + val = (rss_key[16] << 24) | + (rss_key[17] << 16) | + (rss_key[18] << 8) | + rss_key[19]; + REG_WR(pdev, rlup.rlup_ipv6_rss_key5, val); + + val = (rss_key[20] << 24) | + (rss_key[21] << 16) | + (rss_key[22] << 8) | + rss_key[23]; + REG_WR(pdev, rlup.rlup_ipv6_rss_key6, val); + + val = (rss_key[24] << 24) | + (rss_key[25] << 16) | + (rss_key[26] << 8) | + rss_key[27]; + REG_WR(pdev, rlup.rlup_ipv6_rss_key7, val); + + val = (rss_key[28] << 24) | + (rss_key[29] << 16) | + (rss_key[30] << 8) | + rss_key[31]; + REG_WR(pdev, rlup.rlup_ipv6_rss_key8, val); + + val = (rss_key[32] << 24) | + (rss_key[33] << 16) | + (rss_key[34] << 8) | + rss_key[35]; + REG_WR(pdev, rlup.rlup_ipv6_rss_key9, val); + + val = (rss_key[36] << 24) | + (rss_key[37] << 16) | + (rss_key[38] << 8) | + rss_key[39]; + REG_WR(pdev, rlup.rlup_ipv6_rss_key10, val); + } + + rss_table_virt = pdev->rx_info.rss_ind_table_virt; + rss_table_phy = pdev->rx_info.rss_ind_table_phy; + + for(idx = 0; idx < table_size; idx++) + { + rss_table_virt[idx] = indirection_table[idx]; + } + + prod_qe = pdev->kq_info.kwq_prod_qe; + prod_idx = pdev->kq_info.kwq_prod_idx; + + /* Initialize the RSS update KWQE. */ + rss_update = (l2_kwqe_rss_table_update_t *) prod_qe; + + rss_update->rss_flags = L2_KWQE_FLAGS_LAYER_MASK_L2; + rss_update->rss_opcode = L2_KWQE_OPCODE_VALUE_UPDATE_RSS; + + rss_update->rss_table_size = (u16_t) table_size; + rss_update->rss_table_haddr_lo = rss_table_phy.as_u32.low; + rss_update->rss_table_haddr_hi = rss_table_phy.as_u32.high; + rss_update->rss_host_opaque = 0; + rss_update->rss_hash_type = hash_type; + + #if RSS_LOOKUP_TABLE_WA + rss_table_virt += RSS_INDIRECTION_TABLE_SIZE; + LM_INC64(&rss_table_phy, RSS_INDIRECTION_TABLE_SIZE); + + rss_update->rss_lookup_table_lo = rss_table_phy.as_u32.low; + rss_update->rss_lookup_table_hi = rss_table_phy.as_u32.high; + + rss_gen_tables(rss_key, (u32_t *) rss_table_virt); + #endif + + /* Advance to the next KWQE. */ + if(prod_qe == pdev->kq_info.kwq_last_qe) + { + prod_qe = pdev->kq_info.kwq_virt; + } + else + { + prod_qe++; + } + prod_idx++; + + /* Initialize the RSS enable KWQE. */ + rss_update = (l2_kwqe_rss_table_update_t *) prod_qe; + + rss_update->rss_flags = L2_KWQE_FLAGS_LAYER_MASK_L2; + rss_update->rss_opcode = L2_KWQE_OPCODE_VALUE_ENABLE_RSS; + rss_update->rss_host_opaque = 0; + rss_update->rss_hash_type = hash_type; + + /* Advance to the next KWQE. */ + if(prod_qe == pdev->kq_info.kwq_last_qe) + { + prod_qe = pdev->kq_info.kwq_virt; + } + else + { + prod_qe++; + } + prod_idx++; + + pdev->kq_info.kwq_prod_qe = prod_qe; + pdev->kq_info.kwq_prod_idx = prod_idx; + + MBQ_WR16( + pdev, + GET_CID(pdev->kq_info.kwq_cid_addr), + OFFSETOF(krnlq_context_t, krnlq_host_qidx), + prod_idx); + + return LM_STATUS_SUCCESS; +} /* lm_enable_rss */ +#else /* LM_LEAGCY_MODE_SUPPORT */ +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_enable_rss( + lm_device_t *pdev, + lm_rss_hash_t hash_type, + PROCESSOR_NUMBER *indirection_table, + u32_t table_size, + u8_t *hash_key, + u32_t key_size, + u8_t *cpu_tbl, + u8_t *rss_qidx_tbl) +{ + l2_kwqe_rss_table_update_t *rss_update; + u8_t rss_key[RSS_HASH_KEY_SIZE]; + lm_address_t rss_table_phy; + u8_t *rss_table_virt; + kwqe_t *prod_qe; + u16_t prod_idx; + u32_t idx; + u32_t val; + + if(pdev->kq_info.kwqe_left < 2) + { + pdev->kq_info.no_kwq_bd_left++; + return LM_STATUS_RESOURCE; + } + + pdev->kq_info.kwqe_left -= 2; + + DbgBreakIf(key_size > RSS_HASH_KEY_SIZE); + + /* Initialize the rss key array. */ + if(key_size > RSS_HASH_KEY_SIZE) + { + key_size = RSS_HASH_KEY_SIZE; + } + + for(idx = 0; idx < key_size; idx++) + { + rss_key[idx] = hash_key[idx]; + } + + for(idx = key_size; idx < RSS_HASH_KEY_SIZE; idx++) + { + rss_key[idx] = 0; + } + + DbgBreakIf(table_size > RSS_INDIRECTION_TABLE_SIZE); + + if(table_size > RSS_INDIRECTION_TABLE_SIZE) + { + table_size = RSS_INDIRECTION_TABLE_SIZE; + } + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + REG_RD(pdev, rlup.rlup_rss_config, &val); + val &= ~RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI; + val &= ~RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI; + REG_WR(pdev, rlup.rlup_rss_config, val); + + val = (rss_key[0] << 24) | + (rss_key[1] << 16) | + (rss_key[2] << 8) | + rss_key[3]; + REG_WR(pdev, rlup.rlup_rss_key1, val); + + val = (rss_key[4] << 24) | + (rss_key[5] << 16) | + (rss_key[6] << 8) | + rss_key[7]; + REG_WR(pdev, rlup.rlup_rss_key2, val); + + val = (rss_key[8] << 24) | + (rss_key[9] << 16) | + (rss_key[10] << 8) | + rss_key[11]; + REG_WR(pdev, rlup.rlup_rss_key3, val); + + val = (rss_key[12] << 24) | + (rss_key[13] << 16) | + (rss_key[14] << 8) | + rss_key[15]; + REG_WR(pdev, rlup.rlup_rss_key4, val); + + val = (rss_key[16] << 24) | + (rss_key[17] << 16) | + (rss_key[18] << 8) | + rss_key[19]; + REG_WR(pdev, rlup.rlup_ipv6_rss_key5, val); + + val = (rss_key[20] << 24) | + (rss_key[21] << 16) | + (rss_key[22] << 8) | + rss_key[23]; + REG_WR(pdev, rlup.rlup_ipv6_rss_key6, val); + + val = (rss_key[24] << 24) | + (rss_key[25] << 16) | + (rss_key[26] << 8) | + rss_key[27]; + REG_WR(pdev, rlup.rlup_ipv6_rss_key7, val); + + val = (rss_key[28] << 24) | + (rss_key[29] << 16) | + (rss_key[30] << 8) | + rss_key[31]; + REG_WR(pdev, rlup.rlup_ipv6_rss_key8, val); + + val = (rss_key[32] << 24) | + (rss_key[33] << 16) | + (rss_key[34] << 8) | + rss_key[35]; + REG_WR(pdev, rlup.rlup_ipv6_rss_key9, val); + + val = (rss_key[36] << 24) | + (rss_key[37] << 16) | + (rss_key[38] << 8) | + rss_key[39]; + REG_WR(pdev, rlup.rlup_ipv6_rss_key10, val); + } + + rss_table_virt = pdev->rx_info.rss_ind_table_virt; + rss_table_phy = pdev->rx_info.rss_ind_table_phy; + + pdev->rx_info.rss_tbl_size = table_size; + if(!cpu_tbl) /* indirection table already had queue idx? */ + { + for(idx = 0; idx < table_size; idx++) + rss_table_virt[idx] = indirection_table[idx].Number; + } + else + { + /* map the cpu num in the indirection table to queue idx + * according to the cpu table passed down from the um, then + * rebuilt the table with queue idx*/ + u8_t *rss_cpu_tbl = &cpu_tbl[1]; + + for(idx = 0; idx < table_size; idx++) + { + for(val = 0; val < cpu_tbl[0]; val++) + { + if(indirection_table[idx].Number == rss_cpu_tbl[val]) + { + if(pdev->vars.interrupt_mode == IRQ_MODE_MSIX_BASED || + pdev->vars.interrupt_mode == IRQ_MODE_MSI_BASED) + { + rss_table_virt[idx] = rss_qidx_tbl[rss_cpu_tbl[val] + 1]; + } + else + { + rss_table_virt[idx] = (u8_t)val; + } + break; + } + } + } + } + + prod_qe = pdev->kq_info.kwq_prod_qe; + prod_idx = pdev->kq_info.kwq_prod_idx; + + /* Initialize the RSS update KWQE. */ + rss_update = (l2_kwqe_rss_table_update_t *) prod_qe; + + rss_update->rss_flags = L2_KWQE_FLAGS_LAYER_MASK_L2; + rss_update->rss_opcode = L2_KWQE_OPCODE_VALUE_UPDATE_RSS; + + rss_update->rss_table_size = (u16_t) table_size; + rss_update->rss_table_haddr_lo = rss_table_phy.as_u32.low; + rss_update->rss_table_haddr_hi = rss_table_phy.as_u32.high; + rss_update->rss_host_opaque = 0; + rss_update->rss_hash_type = hash_type; + + #if RSS_LOOKUP_TABLE_WA + rss_table_virt += RSS_INDIRECTION_TABLE_SIZE; + LM_INC64(&rss_table_phy, RSS_INDIRECTION_TABLE_SIZE); + + rss_update->rss_lookup_table_lo = rss_table_phy.as_u32.low; + rss_update->rss_lookup_table_hi = rss_table_phy.as_u32.high; + + rss_gen_tables(rss_key, (u32_t *) rss_table_virt); + #endif + + /* Advance to the next KWQE. */ + if(prod_qe == pdev->kq_info.kwq_last_qe) + { + prod_qe = pdev->kq_info.kwq_virt; + } + else + { + prod_qe++; + } + prod_idx++; + + /* Initialize the RSS enable KWQE. */ + rss_update = (l2_kwqe_rss_table_update_t *) prod_qe; + + rss_update->rss_flags = L2_KWQE_FLAGS_LAYER_MASK_L2; + rss_update->rss_opcode = L2_KWQE_OPCODE_VALUE_ENABLE_RSS; + rss_update->rss_host_opaque = 0; + rss_update->rss_hash_type = hash_type; + + /* Advance to the next KWQE. */ + if(prod_qe == pdev->kq_info.kwq_last_qe) + { + prod_qe = pdev->kq_info.kwq_virt; + } + else + { + prod_qe++; + } + prod_idx++; + + pdev->kq_info.kwq_prod_qe = prod_qe; + pdev->kq_info.kwq_prod_idx = prod_idx; + + MBQ_WR16( + pdev, + GET_CID(pdev->kq_info.kwq_cid_addr), + OFFSETOF(krnlq_context_t, krnlq_host_qidx), + prod_idx); + + return LM_STATUS_SUCCESS; +} /* lm_enable_rss */ +#endif /* LM_NON_LEGACY_MODE_SUPPORT */ + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_disable_rss( + lm_device_t *pdev) +{ + l2_kwqe_rss_table_update_t *rss_update; + kwqe_t *prod_qe; + u16_t prod_idx; + u32_t val; + + if(pdev->kq_info.kwqe_left < 1) + { + pdev->kq_info.no_kwq_bd_left++; + return LM_STATUS_RESOURCE; + } + + pdev->kq_info.kwqe_left -= 1; + + if(CHIP_NUM(pdev) == CHIP_NUM_5709) + { + REG_RD(pdev, rlup.rlup_rss_config, &val); + val &= ~RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI; + val &= ~RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI; + REG_WR(pdev, rlup.rlup_rss_config, val); + } + + prod_qe = pdev->kq_info.kwq_prod_qe; + prod_idx = pdev->kq_info.kwq_prod_idx; + + /* Initialize the RSS enable KWQE. */ + rss_update = (l2_kwqe_rss_table_update_t *) prod_qe; + + rss_update->rss_flags = L2_KWQE_FLAGS_LAYER_MASK_L2; + rss_update->rss_opcode = L2_KWQE_OPCODE_VALUE_DISABLE_RSS; + + /* Advance to the next KWQE. */ + if(prod_qe == pdev->kq_info.kwq_last_qe) + { + prod_qe = pdev->kq_info.kwq_virt; + } + else + { + prod_qe++; + } + prod_idx++; + + pdev->kq_info.kwq_prod_qe = prod_qe; + pdev->kq_info.kwq_prod_idx = prod_idx; + + MBQ_WR16( + pdev, + GET_CID(pdev->kq_info.kwq_cid_addr), + OFFSETOF(krnlq_context_t, krnlq_host_qidx), + prod_idx); + + return LM_STATUS_SUCCESS; +} /* lm_disable_rss */ +#endif /* EXCLUDE_RSS_SUPPORT */ + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void lm_set_pcie_nfe_report(lm_device_t *pdev) +{ + if(CHIP_NUM(pdev) == CHIP_NUM_5709 && + pdev->params.disable_pcie_nfr) + { + u16_t pci_devctl; + REG_RD(pdev,pci_config.pcicfg_device_control,&pci_devctl); + pci_devctl &= ~PCICFG_DEVICE_CONTROL_NON_FATAL_REP_ENA; + REG_WR(pdev,pci_config.pcicfg_device_control,pci_devctl); + } +} + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void lm_clear_coalescing_ticks(lm_device_t *pdev) +{ + pdev->params.tx_quick_cons_trip = 1; + pdev->params.tx_quick_cons_trip_int = 1; + pdev->params.rx_quick_cons_trip = 1; + pdev->params.rx_quick_cons_trip_int = 1; + pdev->params.comp_prod_trip = 1; + pdev->params.comp_prod_trip_int = 1; + + pdev->params.tx_ticks = 0; + pdev->params.tx_ticks_int = 0; + pdev->params.com_ticks = 0; + pdev->params.com_ticks_int = 0; + pdev->params.cmd_ticks = 0; + pdev->params.cmd_ticks_int = 0; + pdev->params.rx_ticks = 0; + pdev->params.rx_ticks_int = 0; + pdev->params.stats_ticks = 0; + + /* Xinan per-processor HC configuration. */ + pdev->params.psb_tx_cons_trip = 0x10001; + pdev->params.psb_rx_cons_trip = 0x10001; + pdev->params.psb_comp_prod_trip = 0x10001; + + pdev->params.psb_tx_ticks = 0; + pdev->params.psb_rx_ticks = 0; + pdev->params.psb_com_ticks = 0; + pdev->params.psb_cmd_ticks = 0; + pdev->params.psb_period_ticks = 0; +} + +u8_t lm_is_mmio_ok(lm_device_t *pdev) +{ + u32_t val; + REG_RD(pdev, pci_config.pcicfg_vendor_id, &val); + if (0xffffffff == val) + { + return FALSE; + } + else + { + return TRUE; + } +} + +#if defined(LM_NON_LEGACY_MODE_SUPPORT) +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_create_q_group( + lm_device_t *pdev, + u32_t q_group_id, + u32_t lookahead_sz + ) +{ + u32_t val; + lm_rx_chain_t *rxq; + + rxq = &pdev->rx_info.chain[q_group_id]; + rxq->vmq_lookahead_size = lookahead_sz; + + val = lookahead_sz << 16; + CTX_WR( + pdev, + rxq->cid_addr, + WORD_ALIGNED_OFFSETOF(l2_bd_chain_context_t, + l2ctx_vmq_lookahead_sz), + val); +} + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_destroy_q_group( + lm_device_t *pdev, + u32_t q_group_id, + u32_t num_queues + ) +{ + u32_t num_kwqes_needed; + kwqe_t *prod_qe; + u16_t prod_idx; + l2_kwqe_vm_free_rx_queue_t *kwqe_free_rxq; + + num_kwqes_needed = num_queues; + + if(pdev->kq_info.kwqe_left < num_kwqes_needed) + { + DbgMessage(pdev, WARN, "No more KWQE left.\n"); + + pdev->kq_info.no_kwq_bd_left++; + + return LM_STATUS_RESOURCE; + } + + prod_qe = pdev->kq_info.kwq_prod_qe; + prod_idx = pdev->kq_info.kwq_prod_idx; + + kwqe_free_rxq = (l2_kwqe_vm_free_rx_queue_t *) prod_qe; + + if(q_group_id <= RX_CHAIN_IDX3) + { + if(q_group_id == RX_CHAIN_IDX0) + { + u8_t idx; + /* default queue may have more than 1 queue pairs */ + for(idx = 0; idx < num_queues; idx++) + { + kwqe_free_rxq->flags = L2_KWQE_FLAGS_LAYER_MASK_L2; + kwqe_free_rxq->queue_type = L2_NORMAL_QUEUE; + + if(idx == 0) + kwqe_free_rxq->qid = (u8_t)q_group_id; + else + { + kwqe_free_rxq->qid = idx + 3; + } + + kwqe_free_rxq->opcode = L2_KWQE_OPCODE_VALUE_VM_FREE_RX_QUEUE; + + /* Advance to the next KWQE. */ + if(prod_qe == pdev->kq_info.kwq_last_qe) + { + prod_qe = pdev->kq_info.kwq_virt; + } + else + { + prod_qe++; + } + prod_idx++; + + pdev->kq_info.kwqe_left -= 1; + kwqe_free_rxq = (l2_kwqe_vm_free_rx_queue_t *) prod_qe; + } + pdev->kq_info.kwq_prod_qe = prod_qe; + pdev->kq_info.kwq_prod_idx = prod_idx; + + MBQ_WR16( + pdev, + GET_CID(pdev->kq_info.kwq_cid_addr), + OFFSETOF(krnlq_context_t, krnlq_host_qidx), + prod_idx); + + return LM_STATUS_SUCCESS; + } + else + { + kwqe_free_rxq->queue_type = L2_NORMAL_QUEUE; + kwqe_free_rxq->qid = (u8_t)q_group_id; + pdev->kq_info.kwqe_left -= 1; +#if INCLUDE_OFLD_SUPPORT + if(q_group_id == RX_CHAIN_IDX2 && + !s_list_is_empty(&pdev->rx_info.chain[RX_CHAIN_IDX1].active_descq)) + { + kwqe_free_rxq->flags = L2_KWQE_FLAGS_LAYER_MASK_L2; + kwqe_free_rxq->opcode = L2_KWQE_OPCODE_VALUE_VM_FREE_RX_QUEUE; + + /* Advance to the next KWQE. */ + if(prod_qe == pdev->kq_info.kwq_last_qe) + { + prod_qe = pdev->kq_info.kwq_virt; + } + else + { + prod_qe++; + } + prod_idx++; + + /* flush the catchup RX queue too */ + kwqe_free_rxq = (l2_kwqe_vm_free_rx_queue_t *) prod_qe; + kwqe_free_rxq->queue_type = L2_NORMAL_QUEUE; + kwqe_free_rxq->qid = (u8_t)RX_CHAIN_IDX1; + pdev->kq_info.kwqe_left -= 1; + } +#endif + } + } + else + { + kwqe_free_rxq->queue_type = L2_VM_QUEUE; + kwqe_free_rxq->qid = (u8_t)q_group_id; + pdev->kq_info.kwqe_left -= 1; + } + kwqe_free_rxq->flags = L2_KWQE_FLAGS_LAYER_MASK_L2; + kwqe_free_rxq->opcode = L2_KWQE_OPCODE_VALUE_VM_FREE_RX_QUEUE; + + /* Advance to the next KWQE. */ + if(prod_qe == pdev->kq_info.kwq_last_qe) + { + prod_qe = pdev->kq_info.kwq_virt; + } + else + { + prod_qe++; + } + prod_idx++; + + pdev->kq_info.kwq_prod_qe = prod_qe; + pdev->kq_info.kwq_prod_idx = prod_idx; + + MBQ_WR16( + pdev, + GET_CID(pdev->kq_info.kwq_cid_addr), + OFFSETOF(krnlq_context_t, krnlq_host_qidx), + prod_idx); + + return LM_STATUS_SUCCESS; +} + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +VOID +lm_update_defq_filter_ctx( + lm_device_t *pdev, + u8_t valid + ) +{ + u32_t ctx_offset = pdev->vars.hw_filter_ctx_offset; + u32_t val = 0; + + if(valid) + val |= L2_VM_FILTER_MAC << 16; + + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, rxp.rxp_scratch[0])+ctx_offset, + val); +} + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_chng_q_group_filter( + lm_device_t *pdev, + u32_t q_group_id, + u8_t *dest_mac, + u16_t *vlan_ptr, + u32_t filter_id + ) +{ + kwqe_t *prod_qe; + u16_t prod_idx; + + if(pdev->kq_info.kwqe_left < 1) + { + DbgMessage(pdev, WARN, "No more KWQE left.\n"); + + pdev->kq_info.no_kwq_bd_left++; + + return LM_STATUS_RESOURCE; + } + + prod_qe = pdev->kq_info.kwq_prod_qe; + prod_idx = pdev->kq_info.kwq_prod_idx; + + pdev->kq_info.kwqe_left -= 1; + if(dest_mac == NULL && vlan_ptr == NULL) + { + /* clear filter operation */ + l2_kwqe_vm_remove_rx_filter_t * kwqe_remove_rx_filter = + (l2_kwqe_vm_remove_rx_filter_t *) prod_qe; + kwqe_remove_rx_filter->flags = L2_KWQE_FLAGS_LAYER_MASK_L2; + kwqe_remove_rx_filter->qid = (u8_t)q_group_id; + kwqe_remove_rx_filter->filter_id = (u8_t)filter_id; + kwqe_remove_rx_filter->opcode = L2_KWQE_OPCODE_VALUE_VM_REMOVE_RX_FILTER; + } + else + { + /* set filter operation */ + l2_kwqe_vm_set_rx_filter_t * kwqe_set_rx_filter = + (l2_kwqe_vm_set_rx_filter_t *) prod_qe; + + kwqe_set_rx_filter->flags = L2_KWQE_FLAGS_LAYER_MASK_L2; + kwqe_set_rx_filter->qid = (u8_t)q_group_id; + kwqe_set_rx_filter->filter_id = (u8_t)filter_id; + if(vlan_ptr) + { + kwqe_set_rx_filter->vlan = *vlan_ptr; + kwqe_set_rx_filter->filter_type = L2_VM_FILTER_MAC_VLAN; + } + else + { + kwqe_set_rx_filter->filter_type = L2_VM_FILTER_MAC; + } + kwqe_set_rx_filter->opcode = L2_KWQE_OPCODE_VALUE_VM_SET_RX_FILTER; + } + + /* Advance to the next KWQE. */ + if(prod_qe == pdev->kq_info.kwq_last_qe) + { + prod_qe = pdev->kq_info.kwq_virt; + } + else + { + prod_qe++; + } + prod_idx++; + + pdev->kq_info.kwq_prod_qe = prod_qe; + pdev->kq_info.kwq_prod_idx = prod_idx; + + MBQ_WR16( + pdev, + GET_CID(pdev->kq_info.kwq_cid_addr), + OFFSETOF(krnlq_context_t, krnlq_host_qidx), + prod_idx); + return LM_STATUS_PENDING; +} + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +u32_t +lm_service_l2_kcqes( + struct _lm_device_t *pdev, + kcqe_t *cqe_ptr[], + u32_t num_cqes) +{ + u32_t cqe_serviced_cnt; + u32_t cqe_cnt; + u8_t success; + kcqe_t *kcqe; + lm_status_t lm_status; + + cqe_serviced_cnt = 0; + while(num_cqes) + { + /* Determine the number of cqes for a completion. Some + * completions span several cqes. */ + cqe_cnt = 0; + while(cqe_ptr[cqe_cnt]->kcqe_flags & KCQE_FLAGS_NEXT) + { + cqe_cnt++; + } + cqe_cnt++; + + DbgBreakIf(cqe_cnt > num_cqes); + + kcqe = *cqe_ptr; + + DbgBreakIf((kcqe->kcqe_flags & KCQE_FLAGS_LAYER_MASK) != + KCQE_FLAGS_LAYER_MASK_L2); + + switch(kcqe->kcqe_opcode) + { + case L2_KCQE_OPCODE_VALUE_VM_FREE_RX_QUEUE: + /* initiate rx buffer abort */ + { + l2_kcqe_vm_free_rx_queue_t *kcqe_free_rxq; + + kcqe_free_rxq = (l2_kcqe_vm_free_rx_queue_t *)kcqe; + mm_q_grp_abort_rx_request( + pdev, + kcqe_free_rxq->qid); + } + break; + + case L2_KCQE_OPCODE_VALUE_VM_SET_RX_FILTER: + case L2_KCQE_OPCODE_VALUE_VM_REMOVE_RX_FILTER: + { + l2_kcqe_vm_set_rx_filter_t *kcqe_filter; + + kcqe_filter = (l2_kcqe_vm_set_rx_filter_t *)kcqe; + if(kcqe_filter->status == SC_SUCCESS) + { + lm_status = LM_STATUS_SUCCESS; + } + else + { + lm_status = LM_STATUS_FAILURE; + } + mm_comp_l2_filter_chng_req( + pdev, + lm_status, + kcqe_filter->qid); + } + break; + + case L2_KCQE_OPCODE_VALUE_VM_ALLOC_RX_QUEUE: + case L2_KCQE_OPCODE_VALUE_RX_PACKET: + case L2_KCQE_OPCODE_VALUE_ENABLE_RSS: + case L2_KCQE_OPCODE_VALUE_DISABLE_RSS: + case L2_KCQE_OPCODE_VALUE_UPDATE_RSS: + case L2_KCQE_OPCODE_VALUE_FLUSH_BD_CHAIN: + /* no need to do anything in the driver */ + break; + + default: + DbgBreakMsg("invalid l2 kcqe.\n"); + break; + } + + cqe_ptr += cqe_cnt; + num_cqes -= cqe_cnt; + cqe_serviced_cnt += cqe_cnt; + } + + return cqe_serviced_cnt; +} +#endif /* LM_NON_LEGACY_MODE_SUPPORT */ diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_recv.c b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_recv.c new file mode 100644 index 0000000000..01d7da010d --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_recv.c @@ -0,0 +1,994 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "lm5706.h" +#include <sys/crc32.h> + +/* + * When using "crc32" or "crc16" these initial CRC values must be given to + * the respective function the first time it is called. The function can + * then be called with the return value from the last call of the function + * to generate a running CRC over multiple data blocks. + * When the last data block has been processed using the "crc32" algorithm + * the CRC value should be inverted to produce the final CRC value: + * e.g. CRC = ~CRC + */ + +#define startCRC32 (0xFFFFFFFF) /* CRC initialised to all 1s */ + +/* + * For the CRC-32 residual to be calculated correctly requires that the CRC + * value is in memory little-endian due to the byte read, bit-ordering + * nature of the algorithm. + */ +#define CRC32residual (0xDEBB20E3) /* good CRC-32 residual */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +static void +post_bd_buffer( + lm_rx_chain_t *rxq, + u64_t phy_addr, + u32_t bd_len) +{ + rx_bd_t *prod_bd; + rx_bd_t *cur_bd; + u16_t prod_idx; + + + prod_bd = rxq->prod_bd; + prod_idx = rxq->prod_idx; + + cur_bd = prod_bd; + + prod_bd++; + prod_idx++; + + /* Check for the last bd on this BD page. */ + if((prod_idx & MAX_BD_PER_PAGE) == MAX_BD_PER_PAGE) + { + prod_idx++; + prod_bd = *((rx_bd_t **) ((tx_bd_next_t *) + prod_bd)->tx_bd_next_reserved); + } + + cur_bd->rx_bd_haddr_lo = ((lm_u64_t *)&phy_addr)->as_u32.low; + cur_bd->rx_bd_haddr_hi = ((lm_u64_t *)&phy_addr)->as_u32.high; + cur_bd->rx_bd_len = bd_len; + cur_bd->rx_bd_flags = (RX_BD_FLAGS_END | RX_BD_FLAGS_START); + + rxq->bd_left--; + rxq->prod_idx = prod_idx; + rxq->prod_bd = prod_bd; + +} /* post_bd_buffer */ + +#ifndef LM_NON_LEGACY_MODE_SUPPORT +u32_t +lm_post_buffers( + lm_device_t *pdev, + u32_t chain_idx, + lm_packet_t *packet) /* optional. */ +{ + lm_rx_chain_t *rxq; + u32_t pkt_queued; + rx_bd_t *cur_bd; + u16_t cur_idx; + + rxq = &pdev->rx_info.chain[chain_idx]; + + pkt_queued = 0; + + /* Make sure we have a bd left for posting a receive buffer. */ + if(packet) + { + DbgBreakIf(SIG(packet) != L2PACKET_RX_SIG); + + if(rxq->bd_left == 0) + { + s_list_push_tail(&rxq->free_descq, &packet->link); + packet = NULL; + } + } + else if(rxq->bd_left) + { + packet = (lm_packet_t *) s_list_pop_head(&rxq->free_descq); + } + + while(packet) + { + cur_bd = rxq->prod_bd; + cur_idx = rxq->prod_idx; + #if DBG + ((u32_t *) packet->u1.rx.mem_virt)[0] = 0; + ((u32_t *) packet->u1.rx.mem_virt)[1] = 0; + ((u32_t *) packet->u1.rx.mem_virt)[2] = 0; + ((u32_t *) packet->u1.rx.mem_virt)[3] = 0; + + packet->u1.rx.dbg_bd = cur_bd; + + DbgBreakIf(SIG(packet) != L2PACKET_RX_SIG); + #endif + post_bd_buffer( + rxq, + packet->u1.rx.mem_phy.as_u64, + packet->u1.rx.buf_size); + rxq->prod_bseq += packet->u1.rx.buf_size; + packet->u1.rx.next_bd_idx = rxq->prod_idx; + + /* Tag this bd for debugging. The last nibble is the chain cid. */ + if(pdev->params.test_mode & TEST_MODE_RX_BD_TAGGING) + { + cur_bd->rx_bd_flags |= (u16_t)cur_idx << 4; // put bd idx at the 12 msb of flags + + cur_bd->unused_0 = (u16_t) (rxq->cid_addr); + } + else + { + cur_bd->unused_0 = 0; + } + // Move on to next packet + s_list_push_tail(&rxq->active_descq, &packet->link); + pkt_queued++; + + if(rxq->bd_left == 0) + { + break; + } + + packet = (lm_packet_t *) s_list_pop_head(&rxq->free_descq); + } + + + if(pkt_queued) + { + MBQ_WR16( + pdev, + GET_CID(rxq->cid_addr), + OFFSETOF(l2_bd_chain_context_t, l2ctx_host_bdidx), + rxq->prod_idx); + + MBQ_WR32( + pdev, + GET_CID(rxq->cid_addr), + OFFSETOF(l2_bd_chain_context_t, l2ctx_host_bseq), + rxq->prod_bseq); + } + + return pkt_queued; +} /* lm_post_buffers */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u32_t +get_packets_rcvd( + struct _lm_device_t *pdev, + lm_rx_chain_t *rxq, + u16_t hw_con_idx, + s_list_t *rcvd_list) +{ + l2_fhdr_t *rx_hdr; + lm_packet_t *pkt; + u32_t byte_cnt; + u32_t pkt_cnt; + + pkt_cnt = 0; + byte_cnt = 0; + + /* The consumer index may stop at the end of a page boundary. + * In this case, we need to advance the next to the next one. */ + if((hw_con_idx & MAX_BD_PER_PAGE) == MAX_BD_PER_PAGE) + { + hw_con_idx++; + } + + while(rxq->con_idx != hw_con_idx) + { + DbgBreakIf(S16_SUB(hw_con_idx, rxq->con_idx) <= 0); + + pkt = (lm_packet_t *) s_list_pop_head(&rxq->active_descq); + + DbgBreakIf(pkt == NULL); + DbgBreakIf(SIG(pkt) != L2PACKET_RX_SIG); + + mm_flush_cache( + pdev, + pkt->u1.rx.mem_virt, + pkt->u1.rx.mem_phy, + pkt->u1.rx.buf_size, + FLUSH_CACHE_AFTER_DMA_WRITE); + + rxq->bd_left++; + + /* Advance the rxq->con_idx to the start bd_idx of the next packet. */ + rxq->con_idx = pkt->u1.rx.next_bd_idx; + + rx_hdr = (l2_fhdr_t *) pkt->u1.rx.mem_virt; + pkt->status = LM_STATUS_SUCCESS; + pkt->size = rx_hdr->l2_fhdr_pkt_len - 4 /* CRC32 */; + pkt->u1.rx.flags = 0; + + DbgBreakIf( + (rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_L2_VLAN_TAG) && + pdev->params.keep_vlan_tag && + (pkt->size < MIN_ETHERNET_PACKET_SIZE || + pkt->size > pdev->params.mtu+4)); + DbgBreakIf( + (rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_L2_VLAN_TAG) && + pdev->params.keep_vlan_tag == 0 && + (pkt->size < MIN_ETHERNET_PACKET_SIZE-4 || + pkt->size > pdev->params.mtu)); + DbgBreakIf( + (rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_L2_VLAN_TAG) == 0 && + (pkt->size < MIN_ETHERNET_PACKET_SIZE || + pkt->size > pdev->params.mtu)); + + if(rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_RSS_HASH) + { + pkt->u1.rx.flags |= LM_RX_FLAG_VALID_HASH_VALUE; + pkt->u1.rx.hash_value = rx_hdr->l2_fhdr_hash; + } + + if(rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_L2_VLAN_TAG) + { + pkt->u1.rx.flags |= LM_RX_FLAG_VALID_VLAN_TAG; + pkt->u1.rx.vlan_tag = rx_hdr->l2_fhdr_vlan_tag; + } + + if(rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_IP_DATAGRAM) + { + if(rx_hdr->l2_fhdr_errors & 0x40) + { + pkt->u1.rx.flags |= LM_RX_FLAG_IS_IPV6_DATAGRAM; + } + else + { + pkt->u1.rx.flags |= LM_RX_FLAG_IS_IPV4_DATAGRAM; + } + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_IP_BAD_XSUM) + { + pkt->u1.rx.ip_cksum = rx_hdr->l2_fhdr_ip_xsum; + } + else + { + pkt->u1.rx.ip_cksum = 0xffff; + } + } + + if(rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_TCP_SEGMENT) + { + pkt->u1.rx.flags |= LM_RX_FLAG_IS_TCP_SEGMENT; + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_TCP_BAD_XSUM) + { + pkt->u1.rx.tcp_or_udp_cksum = rx_hdr->l2_fhdr_tcp_udp_xsum; + } + else + { + pkt->u1.rx.tcp_or_udp_cksum = 0xffff; + } + } + else if(rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_UDP_DATAGRAM) + { + pkt->u1.rx.flags |= LM_RX_FLAG_IS_UDP_DATAGRAM; + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_UDP_BAD_XSUM) + { + pkt->u1.rx.tcp_or_udp_cksum = rx_hdr->l2_fhdr_tcp_udp_xsum; + } + else + { + pkt->u1.rx.tcp_or_udp_cksum = 0xffff; + } + } + + if((rx_hdr->l2_fhdr_errors & ( + L2_FHDR_ERRORS_BAD_CRC | + L2_FHDR_ERRORS_PHY_DECODE | + L2_FHDR_ERRORS_ALIGNMENT | + L2_FHDR_ERRORS_TOO_SHORT | + L2_FHDR_ERRORS_GIANT_FRAME)) == 0) + { + if(pdev->params.test_mode & TEST_MODE_VERIFY_RX_CRC) + { + uint32_t crc; + // Offset for CRC depends if there is lookahead buffer + // since L2 frame header could be in lookahead buffer + CRC32(crc, (u8_t *)(pkt->u1.rx.mem_virt + L2RX_FRAME_HDR_LEN), + rx_hdr->l2_fhdr_pkt_len, startCRC32, crc32_table); + if (crc != CRC32residual) + { + TRIGGER(pdev, TEST_MODE_VERIFY_RX_CRC); + + DbgBreakMsg("Bad CRC32 in rx packet.\n"); + + pkt->status = LM_STATUS_FAILURE; + } + } + } + else + { + if(!(pdev->rx_info.mask[rxq->idx] & LM_RX_MASK_ACCEPT_ERROR_PACKET)) + { + pkt->status = LM_STATUS_FAILURE; + } + + pdev->rx_info.stats.err++; + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_BAD_CRC) + { + pdev->rx_info.stats.crc++; + } + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_PHY_DECODE) + { + pdev->rx_info.stats.phy_err++; + } + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_ALIGNMENT) + { + pdev->rx_info.stats.alignment++; + } + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_TOO_SHORT) + { + pdev->rx_info.stats.short_packet++; + } + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_GIANT_FRAME) + { + pdev->rx_info.stats.giant_packet++; + } + + DbgBreakIf( + rx_hdr->l2_fhdr_errors & ~(L2_FHDR_ERRORS_BAD_CRC | + L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | + L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)); + } + + pkt_cnt++; + byte_cnt += pkt->size; + + s_list_push_tail(rcvd_list, &pkt->link); + } + + return pkt_cnt; +} /* get_packets_rcvd */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +u32_t +lm_get_packets_rcvd( + struct _lm_device_t *pdev, + u32_t qidx, + u32_t con_idx, + s_list_t *rcvd_list) +{ + lm_rx_chain_t *rxq; + u16_t hw_con_idx; + u32_t pkts_added; + u32_t pkt_cnt; + + rxq = &pdev->rx_info.chain[qidx]; + + if(con_idx) + { + hw_con_idx = con_idx & 0xffff; + + pkt_cnt = get_packets_rcvd(pdev, rxq, hw_con_idx, rcvd_list); + } + else + { + pkt_cnt = 0; + + for(; ;) + { + hw_con_idx = *rxq->hw_con_idx_ptr; + + pkts_added = get_packets_rcvd(pdev, rxq, hw_con_idx, rcvd_list); + if(pkts_added == 0) + { + break; + } + + pkt_cnt += pkts_added; + } + } + + return pkt_cnt; +} /* lm_get_packets_rcvd */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_service_rx_int( + lm_device_t *pdev, + u32_t chain_idx) +{ + lm_packet_t *pkt_arr[MAX_PACKETS_PER_INDICATION]; + lm_packet_t **pkt_arr_ptr; + s_list_t rcvd_list; + lm_packet_t *pkt; + u32_t pkt_cnt; + + s_list_init(&rcvd_list, NULL, NULL, 0); + + (void) lm_get_packets_rcvd(pdev, chain_idx, 0, &rcvd_list); + + while(!s_list_is_empty(&rcvd_list)) + { + pkt_arr_ptr = pkt_arr; + + for(pkt_cnt = 0; pkt_cnt < MAX_PACKETS_PER_INDICATION; pkt_cnt++) + { + pkt = (lm_packet_t *) s_list_pop_head(&rcvd_list); + if(pkt == NULL) + { + break; + } + + *pkt_arr_ptr = pkt; + pkt_arr_ptr++; + } + + mm_indicate_rx(pdev, chain_idx, pkt_arr, pkt_cnt); + } +} /* lm_service_rx_int */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_recv_abort( + struct _lm_device_t *pdev, + u32_t idx) +{ + lm_rx_chain_t *rxq; + lm_packet_t *pkt; + + DbgBreakIf(idx >= pdev->rx_info.num_rxq); + + rxq = &pdev->rx_info.chain[idx]; + + for(; ;) + { + pkt = (lm_packet_t *) s_list_pop_head(&rxq->active_descq); + if(pkt == NULL) + { + break; + } + + pkt->status = LM_STATUS_ABORTED; + rxq->bd_left++; + pdev->rx_info.stats.aborted++; + + s_list_push_tail(&rxq->free_descq, &pkt->link); + } +} /* lm_recv_abort */ +#else /* LM_NON_LEGACY_MODE_SUPPORT */ +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +u32_t +lm_post_buffers( + lm_device_t *pdev, + u32_t chain_idx, + lm_packet_t *packet, + lm_frag_list_t *frags) +{ + lm_rx_chain_t *rxq; + u32_t pkt_queued; + rx_bd_t *cur_bd; + u16_t cur_idx; + lm_pkt_rx_info_t *pkt_info; + lm_address_t mem_phy; + + rxq = &pdev->rx_info.chain[chain_idx]; + + pkt_queued = 0; + + /* Make sure we have a bd left for posting a receive buffer. */ + if(packet) + { + if(rxq->vmq_lookahead_size && rxq->bd_left < 2) + { + return pkt_queued; + } + else if(rxq->bd_left == 0) + { + return pkt_queued; + } + + pkt_info = packet->u1.rx.rx_pkt_info; + + cur_bd = rxq->prod_bd; + cur_idx = rxq->prod_idx; + #if DBG + ((u32_t *) pkt_info->mem_virt)[0] = 0; + ((u32_t *) pkt_info->mem_virt)[1] = 0; + ((u32_t *) pkt_info->mem_virt)[2] = 0; + ((u32_t *) pkt_info->mem_virt)[3] = 0; + packet->u1.rx.dbg_bd = cur_bd; + packet->u1.rx.dbg_bd1 = NULL; + #endif + if (rxq->vmq_lookahead_size) + { + // Break down 2 BDs for lookahead header support + // We cannot allow odd number of BDs + // The first BD must at least fit the L2 frame header + DbgBreakIf(frags->cnt != 2); + DbgBreakIf(frags->frag_arr[0].size < rxq->vmq_lookahead_size); + + post_bd_buffer( + rxq, + frags->frag_arr[0].addr.as_u64, + frags->frag_arr[0].size); + cur_bd->rx_bd_flags |= RX_BD_FLAGS_HEADERSPLIT; + rxq->prod_bseq += frags->frag_arr[0].size; + + #if DBG + packet->u1.rx.dbg_bd1 = rxq->prod_bd; + #endif + post_bd_buffer( + rxq, + frags->frag_arr[1].addr.as_u64, + frags->frag_arr[1].size); + rxq->prod_bseq += frags->frag_arr[1].size; + } + else + { + DbgBreakIf(frags->cnt != 1); + post_bd_buffer( + rxq, + frags->frag_arr[0].addr.as_u64, + frags->frag_arr[0].size); + rxq->prod_bseq += frags->frag_arr[0].size; + if(pdev->params.test_mode & TEST_MODE_RX_BD_TAGGING) + { + // put bd idx at the 12 msb of flags + cur_bd->rx_bd_flags |= (u16_t)cur_idx << 4; + } + } + + packet->u1.rx.next_bd_idx = rxq->prod_idx; + /* Tag this bd for debugging. The last nibble is the chain cid. */ + if(pdev->params.test_mode & TEST_MODE_RX_BD_TAGGING) + { + cur_bd->unused_0 = (u16_t) (rxq->cid_addr); + } + else + { + cur_bd->unused_0 = 0; + } + + // Move on to next packet + s_list_push_tail(&rxq->active_descq, &packet->link); + pkt_queued++; + } + + return pkt_queued; +} /* lm_post_buffers */ + +/******************************************************************************* + * DescriptionX_BD_FLAGS_HEADERSPLIT + * + * Return: + ******************************************************************************/ +void +lm_post_rx_bd( + lm_device_t *pdev, + lm_rx_chain_t *rxq + ) +{ + MBQ_WR16( + pdev, + GET_CID(rxq->cid_addr), + OFFSETOF(l2_bd_chain_context_t, l2ctx_host_bdidx), + rxq->prod_idx); + + MBQ_WR32( + pdev, + GET_CID(rxq->cid_addr), + OFFSETOF(l2_bd_chain_context_t, l2ctx_host_bseq), + rxq->prod_bseq); +} + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u32_t +get_packets_rcvd( + struct _lm_device_t *pdev, + lm_rx_chain_t *rxq, + u16_t hw_con_idx, + s_list_t *rcvd_list) +{ + l2_fhdr_t *rx_hdr; + lm_packet_t *pkt; + u32_t byte_cnt; + u32_t pkt_cnt; + lm_pkt_rx_info_t *pkt_info; + u8_t l2_abort_packet = FALSE; + + pkt_cnt = 0; + byte_cnt = 0; + + /* The consumer index may stop at the end of a page boundary. + * In this case, we need to advance the next to the next one. */ + if((hw_con_idx & MAX_BD_PER_PAGE) == MAX_BD_PER_PAGE) + { + hw_con_idx++; + } + + while(rxq->con_idx != hw_con_idx) + { + DbgBreakIf(S16_SUB(hw_con_idx, rxq->con_idx) <= 0); + + pkt = (lm_packet_t *) s_list_pop_head(&rxq->active_descq); + + DbgBreakIf(pkt == NULL); + if(!pkt) + { + DbgBreakIf(!s_list_is_empty(&rxq->active_descq)); + break; + } + pkt_info = pkt->u1.rx.rx_pkt_info; + + //mm_flush_cache( + // pdev, + // pkt_info->mem_virt, + // pkt->sgl->Elements[0].Address, + // pkt_info->size, + // FLUSH_CACHE_AFTER_DMA_WRITE); + + // In case of Lookahead header support, each packet was split to 2 BDs + rxq->bd_left += rxq->vmq_lookahead_size? 2 : 1; + + /* Advance the rxq->con_idx to the start bd_idx of the next packet. */ + rxq->con_idx = pkt->u1.rx.next_bd_idx; + + rx_hdr = (l2_fhdr_t *) pkt_info->mem_virt; + if(l2_abort_packet == FALSE && + rx_hdr->l2_fhdr_pkt_len == 0) + { + DbgBreakIf(!(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_ABORT_PKT)); + // Set upon the first BD detecting L2_FHDR_ERRORS_ABORT_PKT + l2_abort_packet = TRUE; + } + + if(l2_abort_packet) + { + pkt->status = LM_STATUS_ABORTED; + pkt_info->size = 0; + pdev->rx_info.stats.aborted++; + } + else + { + pkt->status = LM_STATUS_SUCCESS; + pkt_info->size = rx_hdr->l2_fhdr_pkt_len - 4 /* CRC32 */; + pkt_info->flags = 0; + + DbgBreakIf( + (rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_L2_VLAN_TAG) && + pdev->params.keep_vlan_tag && + (pkt_info->size < MIN_ETHERNET_PACKET_SIZE || + pkt_info->size > pdev->params.mtu+4)); + DbgBreakIf( + (rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_L2_VLAN_TAG) && + pdev->params.keep_vlan_tag == 0 && + (pkt_info->size < MIN_ETHERNET_PACKET_SIZE-4 || + pkt_info->size > pdev->params.mtu)); + DbgBreakIf( + (rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_L2_VLAN_TAG) == 0 && + (pkt_info->size < MIN_ETHERNET_PACKET_SIZE || + pkt_info->size > pdev->params.mtu)); + + if(rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_RSS_HASH) + { + pkt_info->flags |= LM_RX_FLAG_VALID_HASH_VALUE; + pkt->u1.rx.hash_value = rx_hdr->l2_fhdr_hash; + } + + if(rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_L2_VLAN_TAG) + { + pkt_info->flags |= LM_RX_FLAG_VALID_VLAN_TAG; + pkt_info->vlan_tag = rx_hdr->l2_fhdr_vlan_tag; + } + + if(rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_IP_DATAGRAM) + { + if(rx_hdr->l2_fhdr_errors & 0x40) + { + pkt_info->flags |= LM_RX_FLAG_IS_IPV6_DATAGRAM; + } + else + { + pkt_info->flags |= LM_RX_FLAG_IS_IPV4_DATAGRAM; + } + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_IP_BAD_XSUM) + { + pkt_info->flags |= LM_RX_FLAG_IP_CKSUM_IS_BAD; + } + else + { + pkt_info->flags |= LM_RX_FLAG_IP_CKSUM_IS_GOOD; + } + } + + if(rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_TCP_SEGMENT) + { + pkt_info->flags |= LM_RX_FLAG_IS_TCP_SEGMENT; + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_TCP_BAD_XSUM) + { + pkt_info->flags |= LM_RX_FLAG_TCP_CKSUM_IS_BAD; + } + else + { + pkt_info->flags |= LM_RX_FLAG_TCP_CKSUM_IS_GOOD; + } + } + else if(rx_hdr->l2_fhdr_status & L2_FHDR_STATUS_UDP_DATAGRAM) + { + pkt_info->flags |= LM_RX_FLAG_IS_UDP_DATAGRAM; + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_UDP_BAD_XSUM) + { + pkt_info->flags |= LM_RX_FLAG_UDP_CKSUM_IS_BAD; + } + else + { + pkt_info->flags |= LM_RX_FLAG_UDP_CKSUM_IS_GOOD; + } + } + + if((rx_hdr->l2_fhdr_errors & ( + L2_FHDR_ERRORS_BAD_CRC | + L2_FHDR_ERRORS_PHY_DECODE | + L2_FHDR_ERRORS_ALIGNMENT | + L2_FHDR_ERRORS_TOO_SHORT | + L2_FHDR_ERRORS_GIANT_FRAME)) == 0) + { + if(pdev->params.test_mode & TEST_MODE_VERIFY_RX_CRC) + { + uint32_t crc; + // Offset for CRC depends if there is lookahead buffer + // since L2 frame header could be in lookahead buffer + CRC32(crc, (u8_t *)pkt_info->mem_virt + L2RX_FRAME_HDR_LEN, + rx_hdr->l2_fhdr_pkt_len, startCRC32, crc32_table); + if (crc != CRC32residual) + { + TRIGGER(pdev, TEST_MODE_VERIFY_RX_CRC); + + DbgBreakMsg("Bad CRC32 in rx packet.\n"); + + pkt->status = LM_STATUS_FAILURE; + } + } + } + else + { + if(!(pdev->rx_info.mask[rxq->idx] & LM_RX_MASK_ACCEPT_ERROR_PACKET)) + { + pkt->status = LM_STATUS_FAILURE; + } + + pdev->rx_info.stats.err++; + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_BAD_CRC) + { + pdev->rx_info.stats.crc++; + } + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_PHY_DECODE) + { + pdev->rx_info.stats.phy_err++; + } + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_ALIGNMENT) + { + pdev->rx_info.stats.alignment++; + } + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_TOO_SHORT) + { + pdev->rx_info.stats.short_packet++; + } + + if(rx_hdr->l2_fhdr_errors & L2_FHDR_ERRORS_GIANT_FRAME) + { + pdev->rx_info.stats.giant_packet++; + } + + DbgBreakIf( + rx_hdr->l2_fhdr_errors & ~(L2_FHDR_ERRORS_BAD_CRC | + L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | + L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)); + } + } + pkt_cnt++; + byte_cnt += pkt_info->size; + + s_list_push_tail(rcvd_list, &pkt->link); + } + + return pkt_cnt; +} /* get_packets_rcvd */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +u32_t +lm_get_packets_rcvd( + struct _lm_device_t *pdev, + u32_t qidx, + u32_t con_idx, + s_list_t *rcvd_list) +{ + lm_rx_chain_t *rxq; + u16_t hw_con_idx; + u32_t pkts_added; + u32_t pkt_cnt; + + rxq = &pdev->rx_info.chain[qidx]; + + if(con_idx) + { + hw_con_idx = con_idx & 0xffff; + + pkt_cnt = get_packets_rcvd(pdev, rxq, hw_con_idx, rcvd_list); + } + else + { + pkt_cnt = 0; + + for(; ;) + { + hw_con_idx = *rxq->hw_con_idx_ptr; + + pkts_added = get_packets_rcvd(pdev, rxq, hw_con_idx, rcvd_list); + if(pkts_added == 0) + { + break; + } + + pkt_cnt += pkts_added; + } + } + + return pkt_cnt; +} /* lm_get_packets_rcvd */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_service_rx_int( + lm_device_t *pdev, + u32_t chain_idx) +{ + lm_packet_t *pkt_arr[MAX_PACKETS_PER_INDICATION]; + lm_packet_t **pkt_arr_ptr; + s_list_t rcvd_list; + lm_packet_t *pkt; + u32_t pkt_cnt; + + s_list_init(&rcvd_list, NULL, NULL, 0); + + lm_get_packets_rcvd(pdev, chain_idx, 0, &rcvd_list); + + while(!s_list_is_empty(&rcvd_list)) + { + pkt_arr_ptr = pkt_arr; + + for(pkt_cnt = 0; pkt_cnt < MAX_PACKETS_PER_INDICATION; pkt_cnt++) + { + pkt = (lm_packet_t *) s_list_pop_head(&rcvd_list); + if(pkt == NULL) + { + break; + } + + *pkt_arr_ptr = pkt; + pkt_arr_ptr++; + } + + mm_indicate_rx(pdev, chain_idx, pkt_arr, pkt_cnt, TRUE); + } +} /* lm_service_rx_int */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_recv_abort( + struct _lm_device_t *pdev, + u32_t idx) +{ + lm_rx_chain_t *rxq; + lm_packet_t *pkt; + lm_packet_t *pkt_arr[MAX_PACKETS_PER_INDICATION]; + lm_packet_t **pkt_arr_ptr; + u32_t pkt_cnt; + + rxq = &pdev->rx_info.chain[idx]; + + while(!s_list_is_empty(&rxq->active_descq)) + { + pkt_arr_ptr = pkt_arr; + + for(pkt_cnt = 0; pkt_cnt < MAX_PACKETS_PER_INDICATION; pkt_cnt++) + { + pkt = (lm_packet_t *) s_list_pop_head(&rxq->active_descq); + if(pkt == NULL) + { + break; + } + + pkt->status = LM_STATUS_ABORTED; + // In case of Lookahead header support, each packet was split to 2 BDs + rxq->bd_left += rxq->vmq_lookahead_size? 2 : 1; + pdev->rx_info.stats.aborted++; + + *pkt_arr_ptr = pkt; + pkt_arr_ptr++; + } + + mm_indicate_rx(pdev, idx, pkt_arr, pkt_cnt, FALSE); + } +} /* lm_recv_abort */ + +#endif /*LM_NON_LEGACY_MODE_SUPPORT*/ diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_send.c b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_send.c new file mode 100644 index 0000000000..cc793890e4 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_send.c @@ -0,0 +1,869 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "lm5706.h" + + +#ifndef LM_NON_LEGACY_MODE_SUPPORT +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_send_packet( + lm_device_t *pdev, + u32_t chain_idx, + lm_packet_t *packet, + lm_frag_list_t *frags) +{ + u16_t lso_bd_reserved; + u16_t ipv6_ext_len; + lm_tx_chain_t *txq; + tx_bd_t *start_bd; + tx_bd_t *last_bd; + tx_bd_t *prod_bd; + lm_frag_t *frag; + u16_t prod_idx; + u32_t flags; + u32_t cnt; + + txq = &pdev->tx_info.chain[chain_idx]; + + if(packet == NULL) + { + // hardcode offset in case of L2_ONLY (e.g Solaris) + u32_t cmd_offset = 34*sizeof(u32_t); // == OFFSETOF(l4_context_t, l4ctx_cmd) + MBQ_WR16( + pdev, + GET_CID(txq->cid_addr), + cmd_offset + + OFFSETOF(tcp_context_cmd_cell_te_t, ccell_tx_host_bidx), + txq->prod_idx); + MBQ_WR32( + pdev, + GET_CID(txq->cid_addr), + cmd_offset + + OFFSETOF(tcp_context_cmd_cell_te_t, ccell_tx_host_bseq), + txq->prod_bseq); + + return LM_STATUS_SUCCESS; + } + + #if DBG + if(frags->cnt == 0) + { + DbgBreakMsg("zero frag_cnt\n"); + + return LM_STATUS_INVALID_PARAMETER; + } + + packet->u1.tx.dbg_start_bd = txq->prod_bd; + packet->u1.tx.dbg_start_bd_idx = txq->prod_idx; + packet->u1.tx.dbg_frag_cnt = (u16_t) frags->cnt; + #endif + + last_bd = NULL; + + if(frags->cnt > txq->bd_left) + { + /* The caller should have done this check before calling this + * routine. */ + DbgBreakMsg("No tx bd left.\n"); + + return LM_STATUS_RESOURCE; + } + + txq->bd_left -= (u16_t) frags->cnt; + + packet->size = 0; + flags = 0; + + if(packet->u1.tx.flags & LM_TX_FLAG_INSERT_VLAN_TAG) + { + flags |= TX_BD_FLAGS_VLAN_TAG; + } + + if((packet->u1.tx.flags & LM_TX_FLAG_TCP_LSO_FRAME) == 0) + { + if(packet->u1.tx.flags & LM_TX_FLAG_COMPUTE_IP_CKSUM) + { + flags |= TX_BD_FLAGS_IP_CKSUM; + LM_INC64(&pdev->tx_info.stats.ip_cso_frames, 1); + } + + if(packet->u1.tx.flags & LM_TX_FLAG_COMPUTE_TCP_UDP_CKSUM) + { + flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; + if(packet->u1.tx.flags & LM_TX_FLAG_IPV6_PACKET) + { + LM_INC64(&pdev->tx_info.stats.ipv6_tcp_udp_cso_frames, 1); + } + else + { + LM_INC64(&pdev->tx_info.stats.ipv4_tcp_udp_cso_frames, 1); + } + } + } + + if(packet->u1.tx.flags & LM_TX_FLAG_DONT_COMPUTE_CRC) + { + flags |= TX_BD_FLAGS_DONT_GEN_CRC; + } + + if(packet->u1.tx.flags & LM_TX_FLAG_TCP_LSO_FRAME) + { + if(packet->u1.tx.flags & LM_TX_FLAG_IPV6_PACKET) + { + /* TCP option length - bottom 4 bits of TX_BD_FLAGS_SW_OPTION_WORD + * in term of the number of 4-byte words. + * IP header length - bits 1-2 of bd flag, the upper 2 bits of + * tx_bd_reserved, and the upper 1 bit of + * TX_BD_FLAGS_SW_OPTION_WORD will be used for IPV6 extension + * header length in term of 8-btye words. + * TX_BD_FLAGS_SW_FLAGS bit will be used to indicate IPV6 LSO. */ + flags |= TX_BD_FLAGS_SW_FLAGS; + + if(packet->u1.tx.flags & LM_TX_FLAG_TCP_LSO_SNAP_FRAME) + { + flags |= TX_BD_FLAGS_SW_SNAP; + } + + DbgBreakIf(packet->u1.tx.lso_tcp_hdr_len < 20 || + packet->u1.tx.lso_tcp_hdr_len > 84 || + packet->u1.tx.lso_tcp_hdr_len % 4); + + /* tcp option length in term of number of 32-bit word. 4 bits + * are used for the number of words. */ + flags |= (packet->u1.tx.lso_tcp_hdr_len - 20) << 6; + + DbgBreakIf(packet->u1.tx.lso_ip_hdr_len < 20 || + packet->u1.tx.lso_ip_hdr_len > 296 || + (packet->u1.tx.lso_ip_hdr_len - 40) % 8); + + /* ipv6 extension header length. 6 bits are used for the number + * of 64-bit words. */ + ipv6_ext_len = packet->u1.tx.lso_ip_hdr_len - 40; + + DbgBreakIf(ipv6_ext_len & 0x7); + + /* ext_len in number of 8-byte words. */ + ipv6_ext_len >>= 3; + + flags |= (ipv6_ext_len & 0x3) << 1; /* bit 1-0 */ + + lso_bd_reserved = packet->u1.tx.lso_mss; + lso_bd_reserved |= (ipv6_ext_len & 0xc) << 12; /* bit 3-2 */ + + flags |= (ipv6_ext_len & 0x10) << 8; /* bit 4 */ + + DbgBreakIf(ipv6_ext_len >> 5); /* bit 5 & high are invalid. */ + + LM_INC64(&pdev->tx_info.stats.ipv6_lso_frames, 1); + } + else + { + flags |= TX_BD_FLAGS_SW_LSO; + if(packet->u1.tx.flags & LM_TX_FLAG_TCP_LSO_SNAP_FRAME) + { + flags |= TX_BD_FLAGS_SW_SNAP; + } + + DbgBreakIf(packet->u1.tx.lso_ip_hdr_len + + packet->u1.tx.lso_tcp_hdr_len > 120); + + /* The size of IP and TCP options in term of 32-bit words. */ + flags |= (packet->u1.tx.lso_ip_hdr_len + + packet->u1.tx.lso_tcp_hdr_len - 40) << 6; + + lso_bd_reserved = packet->u1.tx.lso_mss; + + LM_INC64(&pdev->tx_info.stats.ipv4_lso_frames, 1); + } + } + else + { + lso_bd_reserved = 0; + } + + start_bd = txq->prod_bd; + frag = frags->frag_arr; + + /* Get the pointer to the current BD and its index. */ + prod_idx = txq->prod_idx; + prod_bd = txq->prod_bd; + + /* This is the number of times we cross a BD page boundary for this + * packet. This and the bd_used value will give us the total number + * of BD slots needed to send this packet which is used to determine + * if a packet has been sent. We only need this because unlike L2 + * completion, LSO completion does not end at a request boundary. + * For example, if we had an LSO request that spans BD#100-120. We + * could get a transmit consumer index of 115. */ + packet->u1.tx.span_pages = 0; + + /* Initialize the bd's of this packet. */ + for(cnt = 0; cnt < frags->cnt; cnt++) + { + DbgBreakIf(frag->size >= 0x10000 || frag->size == 0); + + prod_bd->tx_bd_haddr_lo = frag->addr.as_u32.low; + prod_bd->tx_bd_haddr_hi = frag->addr.as_u32.high; + prod_bd->tx_bd_nbytes = (u16_t) frag->size; + prod_bd->tx_bd_vlan_tag = packet->u1.tx.vlan_tag; + prod_bd->tx_bd_flags = (u16_t) flags; + + if(packet->u1.tx.flags & LM_TX_FLAG_TCP_LSO_FRAME) + { + prod_bd->tx_bd_reserved = lso_bd_reserved; + } + else if(pdev->params.test_mode & TEST_MODE_TX_BD_TAGGING) + { + prod_bd->tx_bd_reserved = prod_idx & 0x0fff; + prod_bd->tx_bd_reserved |= (u16_t) (GET_CID(txq->cid_addr) << 12); + } + + packet->size += frag->size; + + last_bd = prod_bd; + frag++; + + /* Advance to the next BD. */ + prod_bd++; + prod_idx++; + if((prod_idx & MAX_BD_PER_PAGE) == MAX_BD_PER_PAGE) + { + /* Only increment span_pages when this BDs for this request + * cross a page boundary. */ + if(cnt+1 < frags->cnt) + { + packet->u1.tx.span_pages++; + } + + prod_idx++; + prod_bd = *((tx_bd_t **) ((tx_bd_next_t *) + prod_bd)->tx_bd_next_reserved); + } + } + + /* Set the bd flags of the first and last BDs. */ + flags |= TX_BD_FLAGS_END; + if(packet->u1.tx.flags & LM_TX_FLAG_COAL_NOW) + { + flags |= TX_BD_FLAGS_COAL_NOW; + } + + last_bd->tx_bd_flags |= (u16_t) flags; + start_bd->tx_bd_flags |= TX_BD_FLAGS_START; + + #if INCLUDE_OFLD_SUPPORT + /* We need to do the padding for the catchup path. */ + if(chain_idx == pdev->tx_info.cu_idx && + packet->size < MIN_ETHERNET_PACKET_SIZE) + { + last_bd->tx_bd_nbytes += + (u16_t) (MIN_ETHERNET_PACKET_SIZE - packet->size); + packet->size = MIN_ETHERNET_PACKET_SIZE; + } + #endif + + /* Save the number of BDs used. Later we need to add this value back + * to txq->bd_left when the packet is sent. */ + packet->u1.tx.bd_used = (u16_t) frags->cnt; + + packet->u1.tx.next_bd_idx = prod_idx; + + txq->prod_bd = prod_bd; + txq->prod_idx = prod_idx; + txq->prod_bseq += packet->size; +#if (DBG) + if (chain_idx == pdev->tx_info.cu_idx) + { + DbgBreakIf(packet->size > pdev->params.mtu + 4); + } + else + { + DbgBreakIf(packet->size > pdev->params.mtu && + (flags & (TX_BD_FLAGS_SW_LSO | TX_BD_FLAGS_SW_FLAGS)) == 0); + } +#endif + s_list_push_tail(&txq->active_descq, &packet->link); + + if(!(packet->u1.tx.flags & LM_TX_FLAG_SKIP_MBQ_WRITE)) + { + // hardcode offset in case of L2_ONLY (e.g Solaris) + u32_t cmd_offset = 34*sizeof(u32_t); // == OFFSETOF(l4_context_t, l4ctx_cmd) + MBQ_WR16( + pdev, + GET_CID(txq->cid_addr), + cmd_offset + + OFFSETOF(tcp_context_cmd_cell_te_t, ccell_tx_host_bidx), + txq->prod_idx); + MBQ_WR32( + pdev, + GET_CID(txq->cid_addr), + cmd_offset + + OFFSETOF(tcp_context_cmd_cell_te_t, ccell_tx_host_bseq), + txq->prod_bseq); + } + + return LM_STATUS_SUCCESS; +} /* lm_send_packet */ +#else +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +lm_status_t +lm_send_packet( + lm_device_t *pdev, + u32_t chain_idx, + lm_packet_t *packet, + lm_frag_list_t *frags) +{ + u16_t lso_bd_reserved; + u16_t ipv6_ext_len; + lm_tx_chain_t *txq; + tx_bd_t *start_bd; + tx_bd_t *last_bd; + tx_bd_t *prod_bd; + lm_frag_t *frag; + u16_t prod_idx; + u32_t flags; + u32_t cnt; + lm_pkt_tx_info_t *pkt_info; + + txq = &pdev->tx_info.chain[chain_idx]; + + if(packet == NULL) + { + // hardcode offset in case of L2_ONLY (e.g Solaris) + u32_t cmd_offset = 34*sizeof(u32_t); // == OFFSETOF(l4_context_t, l4ctx_cmd) + MBQ_WR16( + pdev, + GET_CID(txq->cid_addr), + cmd_offset + + OFFSETOF(tcp_context_cmd_cell_te_t, ccell_tx_host_bidx), + txq->prod_idx); + if(pdev->vars.enable_cu_rate_limiter && + txq->idx == TX_CHAIN_IDX1) + { + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_cu_host_bseq), + txq->prod_bseq); + } + else + { + MBQ_WR32( + pdev, + GET_CID(txq->cid_addr), + cmd_offset + + OFFSETOF(tcp_context_cmd_cell_te_t, ccell_tx_host_bseq), + txq->prod_bseq); + } + + return LM_STATUS_SUCCESS; + } + + #if DBG + if(frags->cnt == 0) + { + DbgBreakMsg("zero frag_cnt\n"); + + return LM_STATUS_INVALID_PARAMETER; + } + + packet->u1.tx.dbg_start_bd = txq->prod_bd; + packet->u1.tx.dbg_start_bd_idx = txq->prod_idx; + packet->u1.tx.dbg_frag_cnt = (u16_t) frags->cnt; + #endif + + last_bd = NULL; + + if(frags->cnt > txq->bd_left) + { + /* The caller should have done this check before calling this + * routine. */ + DbgBreakMsg("No tx bd left.\n"); + + return LM_STATUS_RESOURCE; + } + + txq->bd_left -= (u16_t) frags->cnt; + + pkt_info = packet->u1.tx.tx_pkt_info; + packet->u1.tx.size = 0; + flags = 0; + + if(pkt_info->flags & LM_TX_FLAG_INSERT_VLAN_TAG) + { + flags |= TX_BD_FLAGS_VLAN_TAG; + } + + if((pkt_info->flags & LM_TX_FLAG_TCP_LSO_FRAME) == 0) + { + if(pkt_info->flags & LM_TX_FLAG_COMPUTE_IP_CKSUM) + { + flags |= TX_BD_FLAGS_IP_CKSUM; + LM_INC64(&pdev->tx_info.stats.ip_cso_frames, 1); + } + + if(pkt_info->flags & LM_TX_FLAG_COMPUTE_TCP_UDP_CKSUM) + { + flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; + if(pkt_info->flags & LM_TX_FLAG_IPV6_PACKET) + { + LM_INC64(&pdev->tx_info.stats.ipv6_tcp_udp_cso_frames, 1); + } + else + { + LM_INC64(&pdev->tx_info.stats.ipv4_tcp_udp_cso_frames, 1); + } + } + } + + if(pkt_info->flags & LM_TX_FLAG_DONT_COMPUTE_CRC) + { + flags |= TX_BD_FLAGS_DONT_GEN_CRC; + } + + if(pkt_info->flags & LM_TX_FLAG_TCP_LSO_FRAME) + { + if(pkt_info->flags & LM_TX_FLAG_IPV6_PACKET) + { + /* TCP option length - bottom 4 bits of TX_BD_FLAGS_SW_OPTION_WORD + * in term of the number of 4-byte words. + * IP header length - bits 1-2 of bd flag, the upper 2 bits of + * tx_bd_reserved, and the upper 1 bit of + * TX_BD_FLAGS_SW_OPTION_WORD will be used for IPV6 extension + * header length in term of 8-btye words. + * TX_BD_FLAGS_SW_FLAGS bit will be used to indicate IPV6 LSO. */ + flags |= TX_BD_FLAGS_SW_FLAGS; + + if(pkt_info->flags & LM_TX_FLAG_TCP_LSO_SNAP_FRAME) + { + flags |= TX_BD_FLAGS_SW_SNAP; + } + + DbgBreakIf(pkt_info->lso_tcp_hdr_len < 20 || + pkt_info->lso_tcp_hdr_len > 84 || + pkt_info->lso_tcp_hdr_len % 4); + + /* tcp option length in term of number of 32-bit word. 4 bits + * are used for the number of words. */ + flags |= (pkt_info->lso_tcp_hdr_len - 20) << 6; + + DbgBreakIf(pkt_info->lso_ip_hdr_len < 20 || + pkt_info->lso_ip_hdr_len > 296 || + (pkt_info->lso_ip_hdr_len - 40) % 8); + + /* ipv6 extension header length. 6 bits are used for the number + * of 64-bit words. */ + ipv6_ext_len = pkt_info->lso_ip_hdr_len - 40; + + DbgBreakIf(ipv6_ext_len & 0x7); + + /* ext_len in number of 8-byte words. */ + ipv6_ext_len >>= 3; + + flags |= (ipv6_ext_len & 0x3) << 1; /* bit 1-0 */ + + lso_bd_reserved = pkt_info->lso_mss; + lso_bd_reserved |= (ipv6_ext_len & 0xc) << 12; /* bit 3-2 */ + + flags |= (ipv6_ext_len & 0x10) << 8; /* bit 4 */ + + DbgBreakIf(ipv6_ext_len >> 5); /* bit 5 & high are invalid. */ + + LM_INC64(&pdev->tx_info.stats.ipv6_lso_frames, 1); + } + else + { + flags |= TX_BD_FLAGS_SW_LSO; + if(pkt_info->flags & LM_TX_FLAG_TCP_LSO_SNAP_FRAME) + { + flags |= TX_BD_FLAGS_SW_SNAP; + } + + DbgBreakIf(pkt_info->lso_ip_hdr_len + + pkt_info->lso_tcp_hdr_len > 120); + + /* The size of IP and TCP options in term of 32-bit words. */ + flags |= (pkt_info->lso_ip_hdr_len + + pkt_info->lso_tcp_hdr_len - 40) << 6; + + lso_bd_reserved = pkt_info->lso_mss; + + LM_INC64(&pdev->tx_info.stats.ipv4_lso_frames, 1); + } + } + else + { + lso_bd_reserved = 0; + } + + start_bd = txq->prod_bd; + frag = frags->frag_arr; + + /* Get the pointer to the current BD and its index. */ + prod_idx = txq->prod_idx; + prod_bd = txq->prod_bd; + + /* This is the number of times we cross a BD page boundary for this + * packet. This and the bd_used value will give us the total number + * of BD slots needed to send this packet which is used to determine + * if a packet has been sent. We only need this because unlike L2 + * completion, LSO completion does not end at a request boundary. + * For example, if we had an LSO request that spans BD#100-120. We + * could get a transmit consumer index of 115. */ + packet->u1.tx.span_pages = 0; + + /* Initialize the bd's of this packet. */ + for(cnt = 0; cnt < frags->cnt; cnt++) + { + DbgBreakIf(frag->size >= 0x10000 || frag->size == 0); + + prod_bd->tx_bd_haddr_lo = frag->addr.as_u32.low; + prod_bd->tx_bd_haddr_hi = frag->addr.as_u32.high; + prod_bd->tx_bd_nbytes = (u16_t) frag->size; + prod_bd->tx_bd_vlan_tag = pkt_info->vlan_tag; + prod_bd->tx_bd_flags = (u16_t) flags; + + if(pkt_info->flags & LM_TX_FLAG_TCP_LSO_FRAME) + { + prod_bd->tx_bd_reserved = lso_bd_reserved; + } + else if(pdev->params.test_mode & TEST_MODE_TX_BD_TAGGING) + { + prod_bd->tx_bd_reserved = prod_idx & 0x0fff; + prod_bd->tx_bd_reserved |= (u16_t) (GET_CID(txq->cid_addr) << 12); + } + + packet->u1.tx.size += frag->size; + + last_bd = prod_bd; + frag++; + + /* Advance to the next BD. */ + prod_bd++; + prod_idx++; + if((prod_idx & MAX_BD_PER_PAGE) == MAX_BD_PER_PAGE) + { + /* Only increment span_pages when this BDs for this request + * cross a page boundary. */ + if(cnt+1 < frags->cnt) + { + packet->u1.tx.span_pages++; + } + + prod_idx++; + prod_bd = *((tx_bd_t **) ((tx_bd_next_t *) + prod_bd)->tx_bd_next_reserved); + } + } + + /* Set the bd flags of the first and last BDs. */ + flags |= TX_BD_FLAGS_END; + if(pkt_info->flags & LM_TX_FLAG_COAL_NOW) + { + flags |= TX_BD_FLAGS_COAL_NOW; + } + + last_bd->tx_bd_flags |= (u16_t) flags; + start_bd->tx_bd_flags |= TX_BD_FLAGS_START; + + #if INCLUDE_OFLD_SUPPORT + /* We need to do the padding for the catchup path. */ + if(chain_idx == pdev->tx_info.cu_idx && + packet->u1.tx.size < MIN_ETHERNET_PACKET_SIZE) + { + last_bd->tx_bd_nbytes += + (u16_t) (MIN_ETHERNET_PACKET_SIZE - packet->u1.tx.size); + packet->u1.tx.size = MIN_ETHERNET_PACKET_SIZE; + } + #endif + + /* Save the number of BDs used. Later we need to add this value back + * to txq->bd_left when the packet is sent. */ + packet->u1.tx.bd_used = (u16_t) frags->cnt; + + packet->u1.tx.next_bd_idx = prod_idx; + + txq->prod_bd = prod_bd; + txq->prod_idx = prod_idx; + txq->prod_bseq += packet->u1.tx.size; +#if (DBG) + if (chain_idx == pdev->tx_info.cu_idx) + { + DbgBreakIf(packet->u1.tx.size > pdev->params.mtu + 4); + } + else + { + DbgBreakIf(packet->u1.tx.size > pdev->params.mtu && + (flags & (TX_BD_FLAGS_SW_LSO | TX_BD_FLAGS_SW_FLAGS)) == 0); + } +#endif + s_list_push_tail(&txq->active_descq, &packet->link); + + if(!(pkt_info->flags & LM_TX_FLAG_SKIP_MBQ_WRITE)) + { + // hardcode offset in case of L2_ONLY (e.g Solaris) + u32_t cmd_offset = 34*sizeof(u32_t); // == OFFSETOF(l4_context_t, l4ctx_cmd) + MBQ_WR16( + pdev, + GET_CID(txq->cid_addr), + cmd_offset + + OFFSETOF(tcp_context_cmd_cell_te_t, ccell_tx_host_bidx), + txq->prod_idx); + if(pdev->vars.enable_cu_rate_limiter && + txq->idx == TX_CHAIN_IDX1) + { + REG_WR_IND( + pdev, + OFFSETOF(reg_space_t, com.com_scratch[0])+COM_HSI_OFFSETOFF(com_cu_host_bseq), + txq->prod_bseq); + } + else + { + MBQ_WR32( + pdev, + GET_CID(txq->cid_addr), + cmd_offset + + OFFSETOF(tcp_context_cmd_cell_te_t, ccell_tx_host_bseq), + txq->prod_bseq); + } + } + + return LM_STATUS_SUCCESS; +} /* lm_send_packet */ +#endif /* LM_NON_LEGACY_MODE_SUPPORT */ + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +STATIC u32_t +get_packets_sent( + struct _lm_device_t *pdev, + lm_tx_chain_t *txq, + u16_t hw_con_idx, + s_list_t *sent_list) +{ + lm_packet_t *pkt; + u32_t pkt_cnt; + + /* The consumer index may stop at the end of a page boundary. + * In this case, we need to advance the next to the next one. */ + if((hw_con_idx & MAX_BD_PER_PAGE) == MAX_BD_PER_PAGE) + { + hw_con_idx++; + } + + pkt_cnt = 0; + + while(txq->con_idx != hw_con_idx) + { + DbgBreakIf(S16_SUB(hw_con_idx, txq->con_idx) <= 0); + + pkt = (lm_packet_t *) s_list_peek_head(&txq->active_descq); + + DbgBreakIf(pkt == NULL); + + if(!pkt) + { + DbgBreakIf(!s_list_is_empty(&txq->active_descq)); + break; + } + /* LSO requests may not complete at the request boundary. + * + * if(pkt->u1.tx.flags & LM_TX_FLAG_TCP_LSO_FRAME) */ + { + if((u16_t) S16_SUB(hw_con_idx, txq->con_idx) < + pkt->u1.tx.bd_used + pkt->u1.tx.span_pages) + { + break; + } + } + + #if DBG + DbgBreakIf(pkt->u1.tx.dbg_start_bd_idx != txq->con_idx); + + /* Make sure hw_con_idx ends at an l2 packet boundary. For LSO, + * request, hw_con_idx may not end at the request boundary. */ + while(pkt) + { + if(S16_SUB(hw_con_idx, pkt->u1.tx.next_bd_idx) <= 0) + { + break; + } + + pkt = (lm_packet_t *) s_list_next_entry(&pkt->link); + } + + DbgBreakIf(pkt == NULL); + + /* catchup workaround. + * DbgBreakIf( + * !(pkt->u1.tx.flags & LM_TX_FLAG_TCP_LSO_FRAME) && + * (hw_con_idx != pkt->u1.tx.next_bd_idx)); */ + #endif + + pkt = (lm_packet_t *) s_list_pop_head(&txq->active_descq); + + /* Advance the txq->con_idx to the start bd_idx of the next packet. */ + txq->con_idx = pkt->u1.tx.next_bd_idx; + + pkt->status = LM_STATUS_SUCCESS; + + txq->bd_left += pkt->u1.tx.bd_used; + + s_list_push_tail(sent_list, &pkt->link); + + pkt_cnt++; + } + + return pkt_cnt; +} /* get_packets_sent */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +u32_t +lm_get_packets_sent( + struct _lm_device_t *pdev, + u32_t qidx, + u32_t con_idx, + s_list_t *sent_list) +{ + lm_tx_chain_t *txq; + u16_t hw_con_idx; + u32_t pkts_added; + u32_t pkt_cnt; + + txq = &pdev->tx_info.chain[qidx]; + + if(con_idx) + { + hw_con_idx = con_idx & 0xffff; + + pkt_cnt = get_packets_sent(pdev, txq, hw_con_idx, sent_list); + } + else + { + pkt_cnt = 0; + + for(; ;) + { + hw_con_idx = *txq->hw_con_idx_ptr; + + pkts_added = get_packets_sent(pdev, txq, hw_con_idx, sent_list); + if(pkts_added == 0) + { + break; + } + + pkt_cnt += pkts_added; + } + } + + return pkt_cnt; +} /* lm_get_packets_sent */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_service_tx_int( + lm_device_t *pdev, + u32_t chain_idx) +{ + lm_packet_t *pkt_arr[MAX_PACKETS_PER_INDICATION]; + lm_packet_t **pkt_arr_ptr; + s_list_t sent_list; + lm_packet_t *pkt; + u32_t pkt_cnt; + + s_list_init(&sent_list, NULL, NULL, 0); + + (void) lm_get_packets_sent(pdev, chain_idx, 0, &sent_list); + + while(!s_list_is_empty(&sent_list)) + { + pkt_arr_ptr = pkt_arr; + + for(pkt_cnt = 0; pkt_cnt < MAX_PACKETS_PER_INDICATION; pkt_cnt++) + { + pkt = (lm_packet_t *) s_list_pop_head(&sent_list); + if(pkt == NULL) + { + break; + } + + *pkt_arr_ptr = pkt; + pkt_arr_ptr++; + } + + mm_indicate_tx(pdev, chain_idx, pkt_arr, pkt_cnt); + } +} /* lm_service_tx_int */ + + + +/******************************************************************************* + * Description: + * + * Return: + ******************************************************************************/ +void +lm_send_abort( + struct _lm_device_t *pdev, + u32_t idx) +{ + lm_tx_chain_t *txq; + lm_packet_t *pkt; + + DbgBreakIf(idx >= pdev->tx_info.num_txq); + + txq = &pdev->tx_info.chain[idx]; + + for(; ;) + { + pkt = (lm_packet_t *) s_list_pop_head(&txq->active_descq); + if(pkt == NULL) + { + break; + } + + pkt->status = LM_STATUS_ABORTED; + pdev->tx_info.stats.aborted++; + txq->bd_left += pkt->u1.tx.bd_used; + + mm_indicate_tx(pdev, idx, &pkt, 1); + } + + DbgBreakIf(txq->bd_left != + pdev->params.l2_tx_bd_page_cnt[txq->idx] * MAX_BD_PER_PAGE - 1); +} /* lm_send_abort */ diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/comfw.h b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/comfw.h new file mode 100644 index 0000000000..bdf6c8f35c --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/comfw.h @@ -0,0 +1,2014 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* 4.0.4 */ +#include "bcmtype.h" +int COM_b06FwReleaseMajor = 0x1; +int COM_b06FwReleaseMinor = 0x0; +int COM_b06FwReleaseFix = 0x0; +u32_t COM_b06FwStartAddr = 0x08000118; +u32_t COM_b06FwTextAddr = 0x08000000; +int COM_b06FwTextLen = 0x7a78; +u32_t COM_b06FwDataAddr = 0x00000000; +int COM_b06FwDataLen = 0x0; +u32_t COM_b06FwRodataAddr = 0x08007a78; +int COM_b06FwRodataLen = 0xdc; +u32_t COM_b06FwBssAddr = 0x08007bb8; +int COM_b06FwBssLen = 0xc4; +u32_t COM_b06FwSbssAddr = 0x08007b80; +int COM_b06FwSbssLen = 0x38; +u32_t COM_b06FwSDataAddr = 0x00000000; +int COM_b06FwSDataLen = 0x0; +u32_t COM_b06FwText[(0x7a78/4) + 1] = { +0xa000046, +0x0, 0x0, 0xd, 0x636f6d36, +0x2e322e33, 0x0, 0x6020302, 0x0, +0x3, 0xc8, 0x32, 0x3, +0x0, 0x0, 0x0, 0x0, +0x0, 0x10, 0x136, 0xea60, +0x5, 0x0, 0x0, 0x0, +0x8, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x2, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x10, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 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0x1440005c, 0x8fbf0010, +0x8ca20108, 0xe21023, 0x18400058, 0x0, +0x8c830054, 0x9482003c, 0x6a1823, 0x3042ffff, +0x31843, 0x21040, 0x43102a, 0x10400005, +0x0, 0x8c820054, 0x4a1023, 0xa001d75, +0x21043, 0x9482003c, 0x3042ffff, 0x21040, +0xad020064, 0x9502003c, 0x8d040064, 0x9503003c, +0x3042ffff, 0x21040, 0x822021, 0x3063ffff, +0x831821, 0x1431021, 0xad02005c, 0x8d020054, +0xaca20108, 0x24020002, 0xa1020084, 0xe001b4b, +0x8f440100, 0x10400035, 0x8fbf0010, 0x8f430100, +0x8f4201f8, 0x440fffe, 0x24020002, 0xa001db7, +0x0, 0xad07004c, 0x8ca20108, 0xe21023, +0x18400002, 0x24e2fffc, 0xaca20108, 0x30c20001, +0x1040000a, 0x0, 0x8d020050, 0xe21023, +0x4410004, 0x1002021, 0x8d020054, 0x14e20003, +0x0, 0xa001dae, 0x24060005, 0x8d020054, +0x14e2001a, 0x8fbf0010, 0x3c020800, 0x8c4200d8, +0x30420020, 0x1040000a, 0x24020001, 0x91030078, +0x91020083, 0x14430006, 0x24020001, 0x1002021, +0x24060004, 0x8fbf0010, 0xa001c58, 0x27bd0018, +0xa1000084, 0xa5020014, 0x8f430100, 0x8f4201f8, +0x440fffe, 0x24020002, 0xaf4301c0, 0xa34201c4, +0x3c021000, 0xaf4201f8, 0x8fbf0010, 0x3e00008, +0x27bd0018, 0x8faa0010, 0x8c820050, 0x804021, +0x30c600ff, 0x4a1023, 0xa04821, 0x18400007, +0xe01821, 0x24020001, 0xa0800084, 0xa0a00112, +0xa4820014, 0xa001d29, 0xafaa0010, 0xa0800081, +0xad07004c, 0x8ca20108, 0xe21023, 0x18400002, +0x24e2fffc, 0xaca20108, 0x30c20001, 0x10400008, +0x0, 0x8d020050, 0x621023, 0x4410013, +0x24060005, 0x8d020054, 0x10620010, 0x0, +0x8d020054, 0x14620011, 0x0, 0x3c020800, +0x8c4200d8, 0x30420020, 0x1040000a, 0x24020001, +0x91030078, 0x91020083, 0x14430006, 0x24020001, +0x1002021, 0x1202821, 0x24060004, 0xa001c58, +0x0, 0xa1000084, 0xa5020014, 0x3e00008, +0x0, 0x27bdffe0, 0xafbf0018, 0x27420100, +0x9046000a, 0x8c480014, 0x8c8b004c, 0x90820084, +0x30c900ff, 0x1681823, 0x304a00ff, 0x1c60001a, +0x2d460006, 0x24020001, 0x1421004, 0x10c00016, +0x30430003, 0x1203021, 0x1003821, 0x14600007, +0x304c000c, 0x15800009, 0x30420030, 0x1440000b, +0x8fbf0018, 0xa001e18, 0x0, 0xe001d29, +0xafab0010, 0xa001e18, 0x8fbf0018, 0xe001c9e, +0xafab0010, 0xa001e18, 0x8fbf0018, 0xafab0010, +0xe001dbe, 0xafaa0014, 0x8fbf0018, 0x3e00008, +0x27bd0020, 0x24020003, 0xa0820084, 0x8c820054, +0x3e00008, 0xaca20108, 0x3c020008, 0x3421821, +0x90620081, 0x24060043, 0x3c076019, 0x24420001, +0xa0620081, 0x90630081, 0x3c020800, 0x8c4200c0, +0x306300ff, 0x14620010, 0x2403ff80, 0x3c020800, +0x8c4200e0, 0x821021, 0x431024, 0xaf420024, +0x3c020800, 0x8c4200e0, 0x3c03000a, 0x821021, +0x3042007f, 0x3421021, 0x431021, 0x944500d4, +0xa001755, 0x30a5ffff, 0x3e00008, 0x0, +0x27bdffe0, 0xafbf0018, 0xafb10014, 0xafb00010, +0x8f420180, 0x808021, 0xa08821, 0xe001e1f, +0x402021, 0xa2000084, 0x8e020054, 0x8fbf0018, +0x8fb00010, 0xae220108, 0x8fb10014, 0x3e00008, +0x27bd0020, 0x27bdffe0, 0x3c020008, 0xafb00010, +0xafbf0018, 0xafb10014, 0x3428021, 0x8f510140, +0x92030084, 0x8e040050, 0x8e02004c, 0x14820040, +0x306600ff, 0x3c020800, 0x8c4200e0, 0x2403ff80, +0x2221021, 0x431024, 0xaf420024, 0x3c020800, +0x8c4200e0, 0x9744007c, 0x92050081, 0x2221021, +0x3042007f, 0x3421821, 0x3c02000a, 0x621821, +0x14a0000b, 0x3084ffff, 0x24020005, 0x54c20014, +0x248205dc, 0x90620112, 0x24420001, 0xa0620112, +0x24020c80, 0xaf420024, 0xa001e77, 0x24020005, +0xa0600112, 0x24020005, 0x14c20009, 0x248205dc, +0x92020081, 0x2c420007, 0x50400005, 0x24820a00, +0x92030081, 0x24020014, 0x621004, 0x821021, +0x3044ffff, 0xa6040014, 0xe001e1f, 0x2202021, +0x9602003c, 0x8e03004c, 0x2202021, 0x3042ffff, +0x21040, 0x621821, 0xe00022b, 0xae03005c, +0x9202007d, 0x2202021, 0x34420040, 0xe000234, +0xa202007d, 0x8f4201f8, 0x440fffe, 0x24020002, +0xaf5101c0, 0xa34201c4, 0x3c021000, 0xaf4201f8, +0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x3e00008, +0x27bd0020, 0x0 }; +u32_t COM_b06FwData[(0x0/4) + 1] = { 0x0 }; +u32_t COM_b06FwRodata[(0xdc/4) + 1] = { +0x80024d4, 0x80024d4, 0x80025a4, +0x80025a4, 0x80024dc, 0x80024e4, 0x80025a4, +0x80024ec, 0x80024f4, 0x8002508, 0x8002560, +0x8002588, 0x800256c, 0x8002644, 0x800289c, +0x8002920, 0x8002974, 0x8002a9c, 0x8002d68, +0x8002d70, 0x8002d28, 0x8002d70, 0x8002d74, +0x8002d70, 0x8002d40, 0x8002d70, 0x8002d68, +0x8002d70, 0x8002d68, 0x8003e90, 0x8003eb0, +0x8003eb0, 0x8003eb0, 0x8003eb0, 0x8003eb0, +0x8003de8, 0x8003eb0, 0x8003e2c, 0x8003eb0, +0x8003d98, 0x8003eb0, 0x8003eb0, 0x8003eb0, +0x8003dac, 0x8003e10, 0x8003e20, 0x8003fa4, +0x8003e20, 0x8003fa4, 0x8003e20, 0x8003e20, +0x8003e20, 0x8003e18, 0x8003e20, 0x8003e78, +0x0 }; +u32_t COM_b06FwBss[(0xc4/4) + 1] = { 0x0 }; +u32_t COM_b06FwSbss[(0x38/4) + 1] = { 0x0 }; +u32_t COM_b06FwSdata[(0x0/4) + 1] = { 0x0 }; diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/cpfw.h b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/cpfw.h new file mode 100644 index 0000000000..901678a7e9 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/cpfw.h @@ -0,0 +1,1575 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* 4.0.4 */ +#include "bcmtype.h" +int CP_b06FwReleaseMajor = 0x1; +int CP_b06FwReleaseMinor = 0x0; +int CP_b06FwReleaseFix = 0x0; +u32_t CP_b06FwStartAddr = 0x080000a0; +u32_t CP_b06FwTextAddr = 0x08000000; +int CP_b06FwTextLen = 0x5e64; +u32_t CP_b06FwDataAddr = 0x08005f60; +int CP_b06FwDataLen = 0x84; +u32_t CP_b06FwRodataAddr = 0x08005e64; +int CP_b06FwRodataLen = 0xd8; +u32_t CP_b06FwBssAddr = 0x080060d8; +int CP_b06FwBssLen = 0x5d8; +u32_t CP_b06FwSbssAddr = 0x08005fe4; +int CP_b06FwSbssLen = 0xf1; +u32_t CP_b06FwSDataAddr = 0x00000000; +int CP_b06FwSDataLen = 0x0; +u32_t CP_b06FwText[(0x5e64/4) + 1] = { +0xa000028, +0x0, 0x0, 0xd, 0x6370362e, +0x322e3300, 0x0, 0x6020304, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x20, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x1, 0x2b, 0x0, +0x4, 0x30d40, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x10000003, 0x0, 0xd, 0xd, +0x3c020800, 0x24425fe4, 0x3c030800, 0x246366b0, +0xac400000, 0x43202b, 0x1480fffd, 0x24420004, +0x3c1d0800, 0x37bd7ffc, 0x3a0f021, 0x3c100800, +0x261000a0, 0x3c1c0800, 0x279c5fe4, 0xe0001bf, +0x0, 0xd, 0x27bdffe8, 0x3c096018, +0xafbf0014, 0xafb00010, 0x8d2c5000, 0x240dff7f, +0x24080031, 0x18d5824, 0x356a380c, 0x24070c00, +0x3c1a8000, 0xad2a5000, 0x3c04800a, 0xaf480008, +0x3c1b8008, 0xaf470024, 0xe000b09, 0xaf840010, +0xe000acc, 0x0, 0xe000a19, 0x0, +0xe001446, 0x0, 0x3c046016, 0x8c850000, +0x3c06ffff, 0x3c025353, 0xa61824, 0x10620065, +0x34907c00, 0x960201f2, 0xa780002c, 0x10400003, +0xa78000cc, 0x38581e1e, 0xa798002c, 0x960201f8, +0x10400004, 0x978500cc, 0x38591e1e, 0xa79900cc, +0x978500cc, 0x2cbf0067, 0x17e00002, 0xa38000ce, +0x24050066, 0x9784002c, 0x2c820401, 0x50400001, +0x24040400, 0x3c086000, 0x8d070438, 0x2406103c, +0x30e3ffff, 0x50660047, 0x24050066, 0x8e0300f0, +0xa784002c, 0x30640001, 0x1480000f, 0xa78500cc, +0x938700ce, 0x10e00004, 0x978800cc, 0xa78000cc, +0xa780002c, 0x978800cc, 0x8fbf0014, 0x8fb00010, +0xa7800034, 0xa78000e6, 0x3c010800, 0xac280080, +0x3e00008, 0x27bd0018, 0x461fff2, 0x938700ce, +0x96040102, 0x248affe0, 0x2d4901e1, 0x51200001, +0x24040080, 0xe001449, 0x0, 0x8e0400f0, +0x308b0004, 0x51600007, 0xa780002c, 0x9785002c, +0x960300fa, 0xa3602b, 0x55800001, 0xa01821, +0xa783002c, 0x308d0008, 0x51a00007, 0xa78000cc, +0x960300fc, 0x978400cc, 0x83702b, 0x55c00001, +0x801821, 0xa78300cc, 0x9783002c, 0x978200cc, +0x24050040, 0x623021, 0xe000e9e, 0x30c4ffff, +0x9784002c, 0x24050140, 0xe000e9e, 0x408021, +0x978400cc, 0x978500d6, 0xe000e9e, 0x2028021, +0x202f821, 0x27f91800, 0x3c180006, 0x319782b, +0x11e0ffc4, 0x938700ce, 0xa780002c, 0xa00007d, +0xa78000cc, 0x24100400, 0xa78500cc, 0xa00007d, +0xa790002c, 0x8c8f0004, 0x3c0e6000, 0xa00005e, +0x1ee8021, 0x8f860010, 0x3089ffff, 0x93940, +0x8cc30010, 0x3c080050, 0xe82025, 0xaf430038, +0x8cc50014, 0x27420400, 0xaf82001c, 0xaf45003c, +0xaf440030, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x8f4b0000, 0x316a0020, 0x1140fffd, +0x0, 0x3e00008, 0x0, 0x8f840010, +0x948a001a, 0x8c870024, 0x3149ffff, 0x940c0, +0xe83021, 0xaf46003c, 0x8c850024, 0x8f43003c, +0xa31023, 0x18400029, 0x0, 0x8c8b0020, +0x25620001, 0x3c0d0050, 0x35ac0008, 0xaf420038, +0xaf4c0030, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x8f4f0000, 0x31ee0020, 0x11c0fffd, +0x0, 0x8f4a0400, 0x3c080020, 0xac8a0010, +0x8f490404, 0xac890014, 0xaf480030, 0x0, +0x94860018, 0x9487001c, 0xc71821, 0xa4830018, +0x9485001a, 0x24a20001, 0xa482001a, 0x9498001a, +0x9499001e, 0x13380003, 0x0, 0x3e00008, +0x0, 0x3e00008, 0xa480001a, 0x8c820020, +0xa0000ef, 0x3c0d0050, 0xa0000e0, 0x0, +0x3c030800, 0x8c630020, 0x8f820018, 0x27bdffe8, +0x10620008, 0xafbf0010, 0xe000117, 0xaf830018, +0x3c030800, 0x8c630020, 0x24040001, 0x10640004, +0x8f890010, 0x8fbf0010, 0x3e00008, 0x27bd0018, +0x8fbf0010, 0x3c076012, 0xa520000a, 0x9528000a, +0x34e50010, 0x27bd0018, 0x3106ffff, 0x3e00008, +0xaca60090, 0x3c020800, 0x8c420020, 0x27bdffc8, +0xafbf0034, 0xafbe0030, 0xafb7002c, 0xafb60028, +0xafb50024, 0xafb40020, 0xafb3001c, 0xafb20018, +0xafb10014, 0x10400050, 0xafb00010, 0x8f840010, +0x94860006, 0x9483000a, 0xc32823, 0x30b6ffff, +0x12c0004a, 0x8fbf0034, 0x94890018, 0x948a000a, +0x12a4023, 0x3102ffff, 0x2c2382b, 0x14e00002, +0x2c02021, 0x402021, 0x2c8c0005, 0x15800002, +0x80a021, 0x24140004, 0xe0000c6, 0x2802021, +0x8f870010, 0x2809821, 0xaf800014, 0x94ed000a, +0x2808821, 0x1280004e, 0x31b2ffff, 0x3c177000, +0x3c154000, 0x3c1e6000, 0x8f8f001c, 0x8dee0000, +0x1d71824, 0x50750050, 0x2202021, 0x2a3802b, +0x16000035, 0x3c182000, 0x50780047, 0x2202021, +0x24100001, 0x8f830014, 0x14600039, 0x2915823, +0x230f823, 0x250c821, 0x33f1ffff, 0x1620ffee, +0x3332ffff, 0x8f870010, 0x3c110020, 0xaf510030, +0x0, 0x94e6000a, 0x3c1e6012, 0x37d50010, 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0xaca8005c, +0x8ccc0010, 0x34e80010, 0xacac000c, 0x8ccb000c, +0xacab0008, 0x94aa0014, 0x3c020800, 0x8c420044, +0x25490001, 0xa4a90014, 0x94a40014, 0x3083ffff, +0x10620017, 0x8f8400d0, 0x3c0a0800, 0x8d4a0040, +0xa4aa0012, 0x8cce0018, 0xac8e0024, 0x8ccd0014, +0xac8d0020, 0x8cc70018, 0xac87002c, 0x8ccc0014, +0x24060001, 0xac8c0028, 0x8d0b00bc, 0x5166001a, +0x8d0200b4, 0x8d0200b8, 0xa482003a, 0x948f003a, +0xa48f003c, 0x948800d4, 0x3e00008, 0x3102ffff, +0x3c090800, 0x8d290024, 0xa4a00014, 0x8f8400d0, +0xa4a90012, 0x8cce0018, 0xac8e0024, 0x8ccd0014, +0xac8d0020, 0x8cc70018, 0xac87002c, 0x8ccc0014, +0x24060001, 0xac8c0028, 0x8d0b00bc, 0x5566ffea, +0x8d0200b8, 0x8d0200b4, 0xa482003a, 0x948f003a, +0xa48f003c, 0x948800d4, 0x3e00008, 0x3102ffff, +0x8f86001c, 0x3c0c0800, 0x8d8c0050, 0x240bff80, +0x8ccd0008, 0x3c03000c, 0xd51c0, 0x18a4021, +0x10b4824, 0xaf8a00e8, 0xaf490028, 0x90c70007, +0x3105007f, 0xba1021, 0x432821, 0x30e40004, +0x10800039, 0xaf8500d0, 0x90cf0007, 0x31ee0008, +0x11c00038, 0x0, 0x8cd9000c, 0x8cc40014, +0x324c02b, 0x13000030, 0x0, 0x8cc2000c, +0xaca20064, 0x8ccd0018, 0x2402fff8, 0xacad0068, +0x8ccc0010, 0xacac0080, 0x8ccb000c, 0xacab0084, +0x8cca001c, 0xacaa007c, 0x90a900bc, 0x1224024, +0xa0a800bc, 0x90c30007, 0x30670008, 0x10e00004, +0x8f8500d0, 0x90af00bc, 0x35ee0001, 0xa0ae00bc, +0x90d90007, 0x33380001, 0x13000008, 0x8f8300d0, +0x8f8700d0, 0x24040034, 0x90e800bc, 0x35030002, +0xa0e300bc, 0x8f8300d0, 0xac6400c0, 0x90c90007, +0x31260002, 0x10c00005, 0x0, 0x906a00bc, +0x35420004, 0xa06200bc, 0x8f8300d0, 0x90650113, +0x30ad003f, 0xa06d0113, 0x8f8c00d0, 0x958b00d4, +0x3e00008, 0x3162ffff, 0x8cc20014, 0xa0014f9, +0x0, 0xa0014fa, 0xaca00064, 0x27bdffd8, +0xafb00010, 0x8f90001c, 0xafbf0024, 0xafb40020, +0xafb20018, 0xafb10014, 0xafb3001c, 0x9613000e, +0x3c07600a, 0x3c146006, 0x3264ffff, 0x36930010, +0xe001449, 0x34f40410, 0x8f8400d4, 0x3c11600e, +0xe000b8f, 0x36310010, 0x920e0015, 0x3c070800, +0x8ce70060, 0x3c126012, 0x31cd000f, 0xa38d00f0, +0x8e0e0004, 0x8e0d0008, 0x96080012, 0x961f0010, +0x9619001a, 0x9618001e, 0x960f001c, 0x310cffff, +0x33ebffff, 0x332affff, 0x3309ffff, 0x31e6ffff, +0x3c010800, 0xac2b0040, 0x3c010800, 0xac2c0024, +0x3c010800, 0xac2a0044, 0xae293178, 0xae26317c, +0x92020015, 0x96030016, 0x36520010, 0x304400ff, +0x3065ffff, 0x3c060800, 0x8cc60064, 0xae243188, +0xae4500b4, 0x92080014, 0x96190018, 0x241f0001, +0x11fc004, 0x332fffff, 0x3c050800, 0x8ca50058, +0xae5800b8, 0xae4f00bc, 0x920c0014, 0xaf8e00d8, +0xaf8d00dc, 0x318b00ff, 0xae4b00c0, 0x920a0015, +0xae670048, 0xae66004c, 0x314900ff, 0xae4900c8, +0xae65007c, 0x3c030800, 0x8c630050, 0x3c040800, +0x8c84004c, 0x3c080800, 0x8d080054, 0x3c020800, +0x8c42005c, 0x8fbf0024, 0xae630080, 0x8fb00010, +0xae830074, 0x8fb3001c, 0xae22319c, 0xae4200dc, +0xae2731a0, 0xae2631a4, 0xae24318c, 0xae233190, +0xae283194, 0xae253198, 0xae870050, 0xae860054, +0xae850070, 0x8fb10014, 0xae4700e0, 0xae4600e4, +0xae4400cc, 0xae4300d0, 0xae4800d4, 0xae4500d8, +0x8fb40020, 0x8fb20018, 0x3e00008, 0x27bd0028, +0x27bdffe0, 0xafb10014, 0xafbf0018, 0x24110001, +0xe000a39, 0xafb00010, 0x10510005, 0x978400e6, +0x978300cc, 0x83102b, 0x14400008, 0x8f8500d4, +0x24070002, 0x8fbf0018, 0x8fb10014, 0x8fb00010, +0xe01021, 0x3e00008, 0x27bd0020, 0xe000e6e, +0x24040005, 0xaf8200e8, 0x1040fff6, 0x24070002, +0xe000a3d, 0x8f90001c, 0x979f00e6, 0x8f9900e8, +0x8f8d00c8, 0x27ef0001, 0x240e0050, 0xaf590020, +0xa78f00e6, 0xa1ae0000, 0x3c0c0800, 0x8d8c0064, +0x8f8600c8, 0x240a8000, 0xc5e00, 0xaccb0074, +0xa4c00006, 0x94c9000a, 0x241fff80, 0x3c0d000c, +0x12ac024, 0xa4d8000a, 0x90c8000a, 0x24182000, +0x11f1825, 0xa0c3000a, 0x8f8700c8, 0xa0e00078, +0x8f8500c8, 0x3821, 0xa0a00083, 0x3c020800, +0x8c420050, 0x8f8400e8, 0x447821, 0x1ffc824, +0xaf590028, 0x960b0002, 0x31ee007f, 0x1da6021, +0x18d3021, 0xa4cb00d4, 0x960a0002, 0xaf8600d0, +0x3c0e0004, 0x25492401, 0xa4c900e6, 0x8e080004, +0xacc80004, 0x8e030008, 0xacc30000, 0xa4c00010, +0xa4c00014, 0xa0c000d0, 0x8f8500d0, 0x2403ffbf, +0xa0a000d1, 0x3c040800, 0x8c840064, 0x8f8200d0, +0xa04400d2, 0x8e1f000c, 0x8f8a00d0, 0x978f00e4, +0xad5f001c, 0x8e190010, 0x24100030, 0xad590018, +0xa5400030, 0xa5510054, 0xa5510056, 0xa54f0016, +0xad4e0068, 0xad580080, 0xad580084, 0x914d0062, +0x31ac000f, 0x358b0010, 0xa14b0062, 0x8f8600d0, +0x90c90063, 0x3128007f, 0xa0c80063, 0x8f8400d0, +0x2406ffff, 0x90850063, 0xa31024, 0xa0820063, +0x8f9100d0, 0xe01021, 0x923f00bc, 0x37f90001, +0xa23900bc, 0x8f8a00d0, 0x938f00f0, 0xad580064, +0xad5000c0, 0x914e00d3, 0xf6900, 0x31cc000f, +0x18d5825, 0xa14b00d3, 0x8f8500d0, 0x8f8900dc, +0xaca900e8, 0x8f8800d8, 0x8fbf0018, 0x8fb10014, +0x8fb00010, 0x27bd0020, 0xaca800ec, 0xa4a600d6, +0xa4a000e0, 0xa4a000e2, 0x3e00008, 0x0, +0x27bdffe0, 0xafb00010, 0x8f90001c, 0xafb10014, +0xafbf0018, 0x8e190004, 0x3c180800, 0x8f180050, +0x240fff80, 0x1989c0, 0x2387021, 0x31cd007f, +0x1cf6024, 0x1ba5021, 0x3c0b000c, 0xaf4c0028, +0x14b4021, 0x950900d4, 0x950400d6, 0x8e070004, +0x3131ffff, 0xaf8800d0, 0xe000b07, 0x721c0, +0x8e060004, 0x8f8300c8, 0x629c0, 0xaf450020, +0x9064003e, 0x30820040, 0x14400006, 0x8f8400d0, +0x341fffff, 0x948300d6, 0x3062ffff, 0x145f0004, +0x0, 0x948400d6, 0xe000a9c, 0x3084ffff, +0x8e050004, 0x2203021, 0x8fbf0018, 0x8fb10014, +0x8fb00010, 0x24040022, 0x3821, 0x529c0, +0xa001470, 0x27bd0020, 0x27bdffe0, 0xafb10014, +0x3091ffff, 0xafb00010, 0xafbf0018, 0x1220001d, +0x8021, 0x8f86001c, 0x8cc50000, 0x24030006, +0x53f02, 0x51402, 0x30e40007, 0x14830015, +0x304500ff, 0x2ca80006, 0x1100004d, 0x55880, +0x3c0c0800, 0x258c5f24, 0x16c5021, 0x8d490000, +0x1200008, 0x0, 0x8f8e00ec, 0x240d0001, +0x11cd0059, 0x0, 0x260b0001, 0x3170ffff, +0x24ca0020, 0x211202b, 0x1403021, 0x1480ffe6, +0xaf8a001c, 0x2001021, 0x8fbf0018, 0x8fb10014, +0x8fb00010, 0x3e00008, 0x27bd0020, 0x938700ce, +0x14e00038, 0x24040014, 0xe00152c, 0x0, +0x8f86001c, 0x24020001, 0xa001673, 0xaf8200ec, +0x8f8900ec, 0x24080002, 0x1128003b, 0x24040013, +0x2821, 0x3021, 0x24070001, 0xe001470, +0x0, 0xa001673, 0x8f86001c, 0x8f8700ec, +0x24050002, 0x14e5fff6, 0x24040012, 0xe0014dd, +0x0, 0x8f8500e8, 0x403021, 0x24040012, +0xe001470, 0x3821, 0xa001673, 0x8f86001c, +0x8f8300ec, 0x241f0003, 0x147fffd0, 0x260b0001, +0xe00148f, 0x0, 0x8f8500e8, 0x403021, +0x24020002, 0x24040010, 0x3821, 0xaf8200ec, +0xe001470, 0x0, 0xa001673, 0x8f86001c, +0x8f8f00ec, 0x24060002, 0x11e6000b, 0x0, +0x24040010, 0x2821, 0x3021, 0xa001690, +0x24070001, 0x2821, 0xe001470, 0x3021, +0xa001673, 0x8f86001c, 0xe001599, 0x0, +0x14400012, 0x8f99001c, 0x8f86001c, 0x24020003, +0xa001673, 0xaf8200ec, 0xe001625, 0x0, +0xa001673, 0x8f86001c, 0xe00147f, 0x0, +0x24020002, 0x24040014, 0x2821, 0x3021, +0x3821, 0xa0016ad, 0xaf8200ec, 0x403821, +0x24040010, 0x97380002, 0x2821, 0xe001470, +0x3306ffff, 0xa001673, 0x8f86001c, 0x8f8400c8, +0x3c077fff, 0x34e6ffff, 0x8c850074, 0x24020001, +0xa61824, 0xac830074, 0x3e00008, 0xa0820005, +0x10a00036, 0x2ca20080, 0x274a0400, 0x3c0b0005, +0x24090080, 0x10400007, 0x24080080, 0x30a6000f, +0xc54021, 0x2d030081, 0x14600002, 0xa04821, +0x24080080, 0xaf4b0030, 0x0, 0x0, +0x0, 0x11000009, 0x3821, 0x1403021, +0x8c8d0000, 0x24e70004, 0xe8602b, 0xaccd0000, +0x24840004, 0x1580fffa, 0x24c60004, 0x0, +0x0, 0x0, 0x3c0e0006, 0x10e3825, +0xaf470030, 0x0, 0x0, 0x0, +0x8f4f0000, 0x31e80010, 0x1100fffd, 0x0, +0x8f42003c, 0x8f43003c, 0x49c821, 0x323c02b, +0x13000004, 0x0, 0x8f4c0038, 0x25860001, +0xaf460038, 0x8f47003c, 0xa92823, 0xe96821, +0xaf4d003c, 0x14a0ffce, 0x2ca20080, 0x3e00008, +0x0, 0x27bdffd0, 0x3c020002, 0xafb10014, +0x3c11000c, 0xaf450038, 0xafb3001c, 0xaf46003c, +0x809821, 0xaf420030, 0x24050088, 0xaf440028, +0x3512021, 0xafbf0028, 0xafb50024, 0xafb40020, +0xafb20018, 0xe0016e5, 0xafb00010, 0x3c1f0800, +0x8fff004c, 0x3c180800, 0x8f180064, 0x2410ff80, +0x3f3a821, 0x32b9007f, 0x2b07824, 0x18a0c0, +0x33a7021, 0x189140, 0x1d12021, 0xaf4f0028, +0xe0016e5, 0x2542821, 0x3c0d0800, 0x8dad0050, +0x24050120, 0x1b35821, 0x316c007f, 0x1705024, +0x19a4821, 0x1312021, 0xe0016e5, 0xaf4a0028, +0x3c080800, 0x8d080054, 0x3c050800, 0x8ca50064, +0x1133821, 0x30e6007f, 0xf01824, 0xda2021, +0x912021, 0xaf430028, 0xe0016e5, 0x52940, +0x3c020800, 0x8c420058, 0x3c100800, 0x8e100060, +0x1200001c, 0x538821, 0x2415ff80, 0xa001768, +0x3c14000c, 0x3226007f, 0x2351824, 0xda2021, +0x2402821, 0xaf430028, 0x942021, 0xe0016e5, +0x2610ffc0, 0x1200000f, 0x2328821, 0x2e050041, +0x10a0fff4, 0x24121000, 0x3226007f, 0x109180, +0x2351824, 0xda2021, 0x2402821, 0xaf430028, +0x942021, 0xe0016e5, 0x8021, 0x1600fff3, +0x2328821, 0x3c0b0800, 0x8d6b005c, 0x240aff80, +0x24050002, 0x1734021, 0x10a4824, 0xaf490028, +0x3c040800, 0x94840062, 0x3110007f, 0x21a8821, +0x3c07000c, 0xe000e9e, 0x2279821, 0x402821, +0x2602021, 0x8fbf0028, 0x8fb50024, 0x8fb40020, +0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, +0xa0016e5, 0x27bd0030, 0x8f83001c, 0x8c620004, +0x10400003, 0x0, 0x3e00008, 0x0, +0x8c640010, 0x8c650008, 0xa00171e, 0x8c66000c, +0x0 }; +u32_t CP_b06FwData[(0x84/4) + 1] = { +0x0, +0x1b, 0xf, 0xa, 0x8, +0x6, 0x5, 0x5, 0x4, +0x4, 0x3, 0x3, 0x3, +0x3, 0x3, 0x2, 0x2, +0x2, 0x2, 0x2, 0x2, +0x2, 0x2, 0x2, 0x2, +0x2, 0x2, 0x2, 0x2, +0x2, 0x1, 0x1, 0x1, +0x0 }; +u32_t CP_b06FwRodata[(0xd8/4) + 1] = { +0x8001390, +0x8001370, 0x800134c, 0x8001200, 0x8001180, +0x8001104, 0x80010d4, 0x8001080, 0x8001864, +0x80017ec, 0x8001080, 0x8001080, 0x8001824, +0x800175c, 0x800175c, 0x8001080, 0x80017b0, +0x8001774, 0x8001080, 0x8001030, 0x8001080, +0x8001080, 0x8001700, 0x8001080, 0x8001080, +0x8001080, 0x8001080, 0x8001080, 0x8001080, +0x8001080, 0x8001080, 0x8001080, 0x8001080, +0x800165c, 0x8001080, 0x800162c, 0x8001490, +0x80010f8, 0x8001080, 0x800107c, 0x8001458, +0x80015c4, 0x80035e4, 0x80035ec, 0x80035b4, +0x80035c0, 0x80035cc, 0x80035d8, 0x8005ac4, +0x8005a84, 0x8005a50, 0x8005a24, 0x8005a00, +0x80059bc, 0x0 }; +u32_t CP_b06FwBss[(0x5d8/4) + 1] = { 0x0 }; +u32_t CP_b06FwSbss[(0xf1/4) + 1] = { 0x0 }; +u32_t CP_b06FwSdata[(0x0/4) + 1] = { 0x0 }; diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/lm.h b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/lm.h new file mode 100644 index 0000000000..d0a359ca59 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/lm.h @@ -0,0 +1,610 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _LM_H +#define _LM_H + +#include "lm_defs.h" +#include "listq.h" + + + +/******************************************************************************* + * Constants. + ******************************************************************************/ + +#define BAD_DEFAULT_VALUE 0xffffffff + +#define ETHERNET_ADDRESS_SIZE 6 +#define ETHERNET_PACKET_HEADER_SIZE 14 +#define MIN_ETHERNET_PACKET_SIZE 60 +#define MAX_ETHERNET_PACKET_SIZE 1514 +#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 /* A nice even number. */ +#define MIN_JMBO_ETHERNET_PACKET_SIZE 2014 +#define MAX_JMBO_ETHERNET_PACKET_SIZE 9014 + + + +/******************************************************************************* + * Forward definition. + ******************************************************************************/ + +/* Main device structure. */ +/* typedef struct _lm_device_t lm_device_t; */ +struct _lm_device_t; + +/* Packet descriptor for sending/receiving packets. */ +/* typedef struct _lm_packet_t lm_packet_t; */ +struct _lm_packet_t; + + + +/******************************************************************************* + * Mutlicast address table. + ******************************************************************************/ + +#ifndef LM_MAX_MC_TABLE_SIZE +#define LM_MAX_MC_TABLE_SIZE 64 +#endif + +typedef struct _lm_mc_entry_t +{ + u8_t mc_addr[ETHERNET_ADDRESS_SIZE]; + u16_t ref_cnt; +} lm_mc_entry_t; + +typedef struct _lm_mc_table_t +{ + u32_t entry_cnt; + lm_mc_entry_t addr_arr[LM_MAX_MC_TABLE_SIZE]; +} lm_mc_table_t; + + + +/******************************************************************************* + * Network wake-up frame. + ******************************************************************************/ + +#ifndef LM_NWUF_PATTERN_SIZE +#define LM_NWUF_PATTERN_SIZE 128 +#endif +#define LM_NWUF_PATTERN_MASK_SIZE (LM_NWUF_PATTERN_SIZE/8) + +/* Wake-up frame pattern. */ +typedef struct _lm_nwuf_pattern_t +{ + u32_t size; /* Mask size. */ + u8_t mask[LM_NWUF_PATTERN_MASK_SIZE]; + u8_t pattern[LM_NWUF_PATTERN_SIZE]; +} lm_nwuf_t; + + +#ifndef LM_MAX_NWUF_CNT +#define LM_MAX_NWUF_CNT 7 +#endif + +#ifndef LM_MAX_NWUF_CNT_5709 +#define LM_MAX_NWUF_CNT_5709 8 +#endif + +typedef struct _lm_nwuf_list_t +{ + lm_nwuf_t nwuf_arr[LM_MAX_NWUF_CNT_5709]; + u32_t cnt; +} lm_nwuf_list_t; + + + +/******************************************************************************* + * Interrupts. + ******************************************************************************/ + +#define LM_NO_EVENT_ACTIVE 0x00000000 + +#define LM_TX0_EVENT_BIT 0 + +#define LM_TX0_EVENT_ACTIVE (1UL<<0) +#define LM_TX1_EVENT_ACTIVE (1UL<<1) +#define LM_TX2_EVENT_ACTIVE (1UL<<2) +#define LM_TX3_EVENT_ACTIVE (1UL<<3) +#define LM_TX4_EVENT_ACTIVE (1UL<<4) +#define LM_TX5_EVENT_ACTIVE (1UL<<5) +#define LM_TX6_EVENT_ACTIVE (1UL<<6) +#define LM_TX7_EVENT_ACTIVE (1UL<<7) +#define LM_TX8_EVENT_ACTIVE (1UL<<8) +#define LM_TX9_EVENT_ACTIVE (1UL<<9) +#define LM_TX10_EVENT_ACTIVE (1UL<<10) +#define LM_TX11_EVENT_ACTIVE (1UL<<11) + +#define LM_TX_EVENT_MASK 0xfffUL + +#define LM_RX0_EVENT_BIT 16 + +#define LM_RX0_EVENT_ACTIVE (1UL<<16) +#define LM_RX1_EVENT_ACTIVE (1UL<<17) +#define LM_RX2_EVENT_ACTIVE (1UL<<18) +#define LM_RX3_EVENT_ACTIVE (1UL<<19) +#define LM_RX4_EVENT_ACTIVE (1UL<<20) +#define LM_RX5_EVENT_ACTIVE (1UL<<21) +#define LM_RX6_EVENT_ACTIVE (1UL<<22) +#define LM_RX7_EVENT_ACTIVE (1UL<<23) +#define LM_RX8_EVENT_ACTIVE (1UL<<24) +#define LM_RX9_EVENT_ACTIVE (1UL<<25) +#define LM_RX10_EVENT_ACTIVE (1UL<<26) +#define LM_RX11_EVENT_ACTIVE (1UL<<27) + +#define LM_RX_EVENT_MASK 0xfff0000UL + +#define LM_PHY_CONFIG_CHANGED (1UL<<13) +#define LM_KWQ_EVENT_ACTIVE (1UL<<14) +#define LM_KCQ_EVENT_ACTIVE (1UL<<15) +#define LM_PHY_EVENT_ACTIVE (1UL<<30) +#define LM_KNOCK_KNOCK_EVENT (1UL<<31) + +typedef u32_t lm_interrupt_status_t; + + + +/******************************************************************************* + * Function prototypes. + ******************************************************************************/ + +/* Description: + * 1. Retrieves the adapter information, such as IRQ, BAR, chip + * IDs, MAC address, etc. + * 2. Maps the BAR to system address space so hardware registers are + * accessible. + * 3. Initializes the default parameters in 'pdev'. + * 4. Reads user configurations. + * 5. Resets the transceiver. + * This routine calls the following mm routines: + * mm_map_io_base, mm_get_user_config. */ +lm_status_t +lm_get_dev_info( + struct _lm_device_t *pdev); + +/* Description: + * This routine is called during driver initialization. It is responsible + * for allocating memory resources needed by the driver. Packet + * descriptors are allocated here and put into various queues. OS + * independent initialization of packets descriptors are done here and + * finished up in mm_init_packet_desc. + * This routine calls the following mm routines: + * mm_alloc_mem, mm_alloc_phys_mem, and mm_init_packet_desc. */ +lm_status_t +lm_init_resc( + struct _lm_device_t *pdev); + +/* Description: + * This routine is responsible for stopping the hardware from running, + * cleaning up various request queues, aborting transmit requests, and + * reclaiming all the receive buffers. + * This routine calls the following mm routines: + * mm_indicate_tx, mm_free_rx_buf. */ +void +lm_abort( + struct _lm_device_t *pdev, + u32_t abort_op, + u32_t idx); +#define ABORT_OP_RX_CHAIN 1 +#define ABORT_OP_TX_CHAIN 2 + +void +lm_recv_abort( + struct _lm_device_t *pdev, + u32_t idx); + +void +lm_send_abort( + struct _lm_device_t *pdev, + u32_t idx); + +/* Description: + * This routine is called to initialize the first stage of reset which + * only initializes all the device configurations; however states machines + * if any, are not enabled yet. */ +lm_status_t +lm_reset_setup( + struct _lm_device_t *pdev, + u32_t reset_reason); + +/* Description: + * This routine finishes up the final stage of reset. Various state + * machines are enabled here. Upon exit, interrupt will not yet enabled + * and receive buffers are not queued. However, the chip is initialized + * and is ready to send and receive packets. + * receive buffers are not queued. */ +lm_status_t +lm_reset_run( + struct _lm_device_t *pdev); + +/* Description: + * The main function of this routine is to reset and initialize the + * hardware. Upon exit, interrupt generation is not enable; however, + * the hardware is ready to accept transmit requests and receive receive + * packets. 'lm_abort' must be called prior to calling 'lm_reset'. + * This routine is a wrapper for lm_reset_setup and lm_reset_run. */ +lm_status_t +lm_reset( + struct _lm_device_t *pdev, + u32_t reset_reason); + +/* Description: + * The main responsibility of this routine is to gracefully restore the + * chip to its initial power-on state. */ +void +lm_chip_reset( + struct _lm_device_t *pdev, + lm_reason_t reason); + +/* Description: + * This routine post the indicate buffer or receive buffers in the + * free buffer pool. If 'packet' is null, all buffers in the free poll + * will be posted; otherwise, only the 'packet' will be posted. */ +#if defined(LM_NON_LEGACY_MODE_SUPPORT) +u32_t +lm_post_buffers( + struct _lm_device_t *pdev, + u32_t chain_idx, + struct _lm_packet_t *packet, + lm_frag_list_t *frags); +#else +u32_t +lm_post_buffers( + struct _lm_device_t *pdev, + u32_t chain_idx, + struct _lm_packet_t *packet); +#endif +/* Description: + * This routine sends the given packet. Resources required to send this + * must have already been reserved. The upper moduel is resposible for + * any necessary queueing. */ +lm_status_t +lm_send_packet( + struct _lm_device_t *pdev, + u32_t chain_idx, + struct _lm_packet_t *packet, + lm_frag_list_t *frags); + +/* Description: + * This routine is called to get all pending interrupts. */ +lm_interrupt_status_t +lm_get_interrupt_status( + struct _lm_device_t *pdev); + +/* Description: + * This routine is called to service receive interrupts. + * This routine calls the following mm routines: + * mm_indicate_rx */ +void +lm_service_rx_int( + struct _lm_device_t *pdev, + u32_t chain_idx); + +u32_t +lm_get_packets_rcvd( + struct _lm_device_t *pdev, + u32_t qidx, + u32_t con_idx, + s_list_t *rcvd_list); + + +/* Description: + * This routine is called to service transmit complete interrupts. + * This routine calls the following mm routines: + * mm_indicate_tx, mm_complete_tx. */ +void +lm_service_tx_int( + struct _lm_device_t *pdev, + u32_t chain_idx); + +u32_t +lm_get_packets_sent( + struct _lm_device_t *pdev, + u32_t qidx, + u32_t con_idx, + s_list_t *sent_list); + + +/* Description: + * This routine is called to service PHY interrupt. + * This routine calls the following mm routines: + * mm_indicate_link */ +void +lm_service_phy_int( + struct _lm_device_t *pdev, + u32_t force_service_int); + +/* Description: + * This routine is called to mask out interrupt from the hardware. */ +void +lm_disable_int( + struct _lm_device_t *pdev); + +/* Description: + * This routine is called to enable interrupt generation. */ +void +lm_enable_int( + struct _lm_device_t *pdev); + +/* Description: + * This routine is called to set the receive filter. */ +lm_status_t +lm_set_rx_mask( + struct _lm_device_t *pdev, + u32_t user_idx, + lm_rx_mask_t rx_mask); + +/* Description: + * This routine is called to add a multicast address to the multicast + * address table. Multicast filtering is enabled independently via + * lm_set_rx_mask call. */ +lm_status_t +lm_add_mc( + struct _lm_device_t *pdev, + u8_t *mc_addr); + +/* Description: + * This routine is called to remove a multicast address from the multicast + * address table. Multicast filtering is enabled independently via + * lm_set_rx_mask call. */ +lm_status_t +lm_del_mc( + struct _lm_device_t *pdev, + u8_t *mc_addr); + +/* Description: + * This routine is called to remove all multicast addresses from the + * multicast address table. Multicast filtering is enabled independently + * via lm_set_rx_mask call. */ +void +lm_clear_mc( + struct _lm_device_t *pdev); + +/* Description: + * This routine is called to set the current MAC address. The 'addr_idx' + * allows the caller to set multiple MAC addresses if the hardware is + * capable of filtering multiple unicast addresses. */ +lm_status_t +lm_set_mac_addr( + struct _lm_device_t *pdev, + u32_t addr_idx, /* zero based address index. */ + u8_t *mac_addr); + +/* Description: + * This routine is called to retrieve statistics. */ +lm_status_t +lm_get_stats( + struct _lm_device_t *pdev, + lm_stats_t stats_type, + u64_t *stats_cnt); + +/* Description: + * This routine is called to add a wake-up pattern to the main list that + * contains all the wake-up frame. */ +lm_status_t +lm_add_nwuf( + struct _lm_device_t *pdev, + u32_t byte_pattern_size, + u32_t byte_mask_size, + u8_t *byte_mask, + u8_t *byte_pattern); + +/* Description: + * This routine is called to remove the wake-up pattern from the main list + * that contains all the wake-up frame. */ +lm_status_t +lm_del_nwuf( + struct _lm_device_t *pdev, + u32_t byte_mask_size, + u8_t *byte_mask, + u8_t *byte_pattern); + +/* Description: + * Delete all the NWUF entries. */ +void +lm_clear_nwuf( + struct _lm_device_t *pdev); + + +/* Description: + * This routine is called to set up the device power state. */ +void +lm_set_power_state( + struct _lm_device_t *pdev, + lm_power_state_t power_state, + lm_wake_up_mode_t wake_up_mode, /* Valid when power_state is D3. */ + u8_t set_pci_pm); + +/* Description: + * This routine is called to initialize the PHY based one 'media_type' + * setting. 'wait_for_link_timeout' specifies how long to poll for + * link before returning. */ +lm_status_t +lm_init_phy( + struct _lm_device_t *pdev, + lm_medium_t req_medium, + lm_flow_control_t flow_control, + u32_t selective_autoneg, + u32_t wire_speed, + u32_t wait_for_link_timeout); + +u8_t lm_is_mmio_ok(struct _lm_device_t *pdev); + +#if INCLUDE_OFLD_SUPPORT +void +lm_get_ooo_pkts_rcvd( + struct _lm_device_t *pdev, + struct _lm_rx_chain_t *rxq, + u32_t con_idx, + s_list_t *rx_done_list); +#endif + +/******************************************************************************* + * OS dependent functions called by the 'lm' routines. + ******************************************************************************/ + +/* Busy delay for the specified microseconds. */ +void +mm_wait( + struct _lm_device_t *pdev, + u32_t delay_us); + +/* This routine is called to read a PCI configuration register. The register + * must be 32-bit aligned. */ +lm_status_t +mm_read_pci( + struct _lm_device_t *pdev, + u32_t pci_reg, + u32_t *reg_value); + +/* This routine is called to write a PCI configuration register. The + * register must be 32-bit aligned. */ +lm_status_t +mm_write_pci( + struct _lm_device_t *pdev, + u32_t pci_reg, + u32_t reg_value); + +/* This routine is called to map the base address of the device registers + * to system address space so that registers are accessible. The base + * address will be unmapped when the driver unloads. */ +void * +mm_map_io_base( + struct _lm_device_t *pdev, + lm_address_t base_addr, + u32_t size); + +/* This routine is called to read driver configuration. It is called from + * lm_get_dev_info. */ +lm_status_t +mm_get_user_config( + struct _lm_device_t *pdev); + +/* This routine returns the size of a packet descriptor. */ +u32_t +mm_desc_size( + struct _lm_device_t *pdev, + u32_t desc_type); +#define DESC_TYPE_L2TX_PACKET 0 +#define DESC_TYPE_L2RX_PACKET 1 + +/* This routine is responsible for allocating system memory and keeping track + * of it. The memory will be freed later when the driver unloads. This + * routine is called during driver initialization. */ +void * +mm_alloc_mem( + struct _lm_device_t *pdev, + u32_t mem_size, + void *resc_list); + +/* This routine is responsible for physical memory and keeping track + * of it. The memory will be freed later when the driver unloads. */ +void * +mm_alloc_phys_mem( + struct _lm_device_t *pdev, + u32_t mem_size, + lm_address_t *phys_mem, + u8_t mem_type, + void *resc_list); +#define PHYS_MEM_TYPE_UNSPECIFIED 0 +#define PHYS_MEM_TYPE_NONCACHED 1 + + +/* This routine flushes a memory block from caches of all processors. */ +//#if defined(_X86_) || defined(_AMD64_) +#define mm_flush_cache(_pdev, _mem_virt, _mem_phy, _mem_size, _flush_type) +//#else +//void +//mm_flush_cache( +// struct _lm_device_t *pdev, +// u8_t *mem_virt, +// lm_address_t mem_phy, +// u32_t mem_size, +// u8_t flush_type); +//#define FLUSH_CACHE_BEFORE_DMA_READ 0 +//#define FLUSH_CACHE_AFTER_DMA_WRITE 1 +//#endif + + +/* This routine is called to indicate completion of a transmit request. + * If 'packet' is not NULL, all the packets in the completion queue will be + * indicated. Otherwise, only 'packet' will be indicated. */ +void +mm_indicate_tx( + struct _lm_device_t *pdev, + u32_t chain_idx, + struct _lm_packet_t *packet_arr[], + u32_t num_packets); + +/* This routine is called to indicate received packets. If 'packet' is not + * NULL, all the packets in the received queue will be indicated. Otherwise, + * only 'packet' will be indicated. */ +#if defined(LM_NON_LEGACY_MODE_SUPPORT) +void +mm_indicate_rx( + struct _lm_device_t *pdev, + u32_t chain_idx, + struct _lm_packet_t *packet_arr[], + u32_t num_packets, + u8_t ind_as_resc); +#else +void +mm_indicate_rx( + struct _lm_device_t *pdev, + u32_t chain_idx, + struct _lm_packet_t *packet_arr[], + u32_t num_packets); +#endif + +#if INCLUDE_OFLD_SUPPORT +void +mm_return_ooo_pkts( + struct _lm_device_t *pdev, + u32_t qidx, + s_list_t *rcvd_list, + u32_t l2pkt_type + ); +#endif + +/* lm_service_phy_int calls this routine to indicate the current link. */ +void +mm_indicate_link( + struct _lm_device_t *pdev, + lm_status_t link, + lm_medium_t medium); + +/* indirect register access lock. */ +void +mm_acquire_ind_reg_lock( + struct _lm_device_t *pdev); + +void +mm_release_ind_reg_lock( + struct _lm_device_t *pdev); + +void +mm_comp_l2_filter_chng_req( + struct _lm_device_t *pdev, + lm_status_t lm_status, + u32_t q_grp_id); + +void +mm_q_grp_abort_rx_request( + struct _lm_device_t *pdev, + u32_t qidx); + + +#endif /* _LM_H */ + diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/lm5706.h b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/lm5706.h new file mode 100644 index 0000000000..bf87f56571 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/lm5706.h @@ -0,0 +1,1700 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _LM5706_H +#define _LM5706_H + + +#include "bcmtype.h" +#include "debug.h" +#include "5706_reg.h" +#include "l2_defs.h" +#include "l5_defs.h" +#ifndef EXCLUDE_KQE_SUPPORT +#include "l4_kqe.h" +#endif +#ifndef L2_ONLY +#include "status_code.h" +#endif +#include "shmem.h" +#include "lm_desc.h" +#include "listq.h" +#include "lm.h" +#include "mm.h" +#ifndef L2_ONLY +#include "toe_ctx.h" +#endif +#ifdef UEFI +#include "5706_efi.h" +#endif +#ifdef SOLARIS +#include <sys/ddi.h> +#include <sys/sunddi.h> +#endif + +#ifdef LINUX /*lediag*/ +#include "../../mpd_driver_hybrid/pal2.h" +#endif + +typedef struct fw_version +{ + u8_t name[11]; + u8_t namez; + u32_t version; +} fw_version_t; + +#ifndef PRIVATE_HSI_HEADER +#include "rxp_hsi.h" +#include "com_hsi.h" +#include "cp_hsi.h" +#include "txp_hsi.h" +#include "tpat_hsi.h" +#else +#include "hsi.h" +#endif + +/******************************************************************************* + * Constants. + ******************************************************************************/ + +#define MAX_TX_CHAIN 12 +#define MAX_RX_CHAIN 12 +#define FIRST_RSS_RXQ 4 + +#ifndef NUM_RX_CHAIN +#define NUM_RX_CHAIN 1 +#endif + +#ifndef NUM_TX_CHAIN +#define NUM_TX_CHAIN 1 +#endif + +#if NUM_TX_CHAIN > MAX_TX_CHAIN +#error Exceeded maximum number of tx chains. +#endif + +#if NUM_RX_CHAIN > MAX_RX_CHAIN +#error Exceeded maximum number of rx chains. +#endif + +/* Number of bits must be 10 to 25. */ +#ifndef LM_PAGE_BITS +#define LM_PAGE_BITS 12 /* 4K page. */ +#endif + +#define LM_PAGE_SIZE (1 << LM_PAGE_BITS) +#define LM_PAGE_MASK (LM_PAGE_SIZE - 1) + + +#ifndef CACHE_LINE_SIZE_MASK +#define CACHE_LINE_SIZE_MASK 0x3f +#endif + + +/* Number of packets per indication in calls to mm_indicate_rx/tx. */ +#ifndef MAX_PACKETS_PER_INDICATION +#define MAX_PACKETS_PER_INDICATION 50 +#endif + + +#ifndef MAX_FRAG_CNT +#define MAX_FRAG_CNT 33 +#endif + +/* The maximum is actually 0xffff which can be described by a BD. */ +#define MAX_FRAGMENT_SIZE 0xf000 + + +/* Context size. */ +#define CTX_SHIFT 7 +#define CTX_SIZE (1 << CTX_SHIFT) +#define CTX_MASK (CTX_SIZE - 1) +#define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) +#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) + +#define PHY_CTX_SHIFT 6 +#define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) +#define PHY_CTX_MASK (PHY_CTX_SIZE - 1) +#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) +#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) + +#define MB_KERNEL_CTX_SHIFT 8 +#define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) +#define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) +/* #define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) */ +#define MB_GET_CID_ADDR(_p, _c) lm_mb_get_cid_addr(_p, _c) + +#define MAX_CID_CNT 0x4000 +#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) +#define INVALID_CID_ADDR 0xffffffff + + +/* The size of the GRC window that appears in 32k-64k. */ +#define GRC_WINDOW_BASE 0x8000 +#define GRC_WINDOW_SIZE 0x8000 + + +/* L2 rx frame header size. */ +#define L2RX_FRAME_HDR_LEN (sizeof(l2_fhdr_t)+2) + + +/* The number of bd's per page including the last bd which is used as + * a pointer to the next bd page. */ +#define BD_PER_PAGE (LM_PAGE_SIZE/sizeof(tx_bd_t)) + +/* The number of useable bd's per page. This number does not include + * the last bd at the end of the page. */ +#define MAX_BD_PER_PAGE ((u32_t) (BD_PER_PAGE-1)) + + +/* Buffer size of the statistics block. */ +#define CHIP_STATS_BUFFER_SIZE ((sizeof(statistics_block_t) + \ + CACHE_LINE_SIZE_MASK) & \ + ~CACHE_LINE_SIZE_MASK) + +/* Buffer size of the status block. */ +#define STATUS_BLOCK_BUFFER_SIZE ((sizeof(status_blk_combined_t) + \ + CACHE_LINE_SIZE_MASK) & \ + ~CACHE_LINE_SIZE_MASK) + + +#define RSS_INDIRECTION_TABLE_SIZE 0x80 /* Maximum indirection table. */ +#define RSS_HASH_KEY_SIZE 0x40 /* Maximum key size. */ +#ifndef RSS_LOOKUP_TABLE_WA +#define RSS_LOOKUP_TABLE_WA (4*12*256) /* 0 to disable workaround. */ +#endif + + +/* Quick context assigments. */ +#define L2RX_CID_BASE 0 /* 0-15 */ +#define L2TX_CID_BASE 16 /* 16-23 */ +#define KWQ_CID 24 +#define KCQ_CID 25 +#define HCOPY_CID 26 /* 26-27 */ +#define GEN_CHAIN_CID 29 + +/* Xinan definitions. */ +#define L2TX_TSS_CID_BASE 32 /* 32-43 */ + +/* MSIX definitions. */ +#define IRQ_MODE_UNKNOWN 0 +#define IRQ_MODE_LINE_BASED 1 +#define IRQ_MODE_SIMD 2 +#define IRQ_MODE_MSI_BASED 3 +#define IRQ_MODE_MSIX_BASED 4 +#define MAX_MSIX_HW_VEC 9 +#define PCI_GRC_WINDOW2_BASE 0xc000 +#define PCI_GRC_WINDOW3_BASE 0xe000 +#define MSIX_TABLE_ADDR 0x318000 +#define MSIX_PBA_ADDR 0x31c000 + +/******************************************************************************* + * Macros. + ******************************************************************************/ + +/* These macros have been moved to bcmtype.h. */ +#if 0 +/* Signed subtraction macros with no sign extending. */ +#define S64_SUB(_a, _b) ((s64_t) ((s64_t) (_a) - (s64_t) (_b))) +#define u64_SUB(_a, _b) ((u64_t) ((s64_t) (_a) - (s64_t) (_b))) +#define S32_SUB(_a, _b) ((s32_t) ((s32_t) (_a) - (s32_t) (_b))) +#define uS32_SUB(_a, _b) ((u32_t) ((s32_t) (_a) - (s32_t) (_b))) +#define S16_SUB(_a, _b) ((s16_t) ((s16_t) (_a) - (s16_t) (_b))) +#define u16_SUB(_a, _b) ((u16_t) ((s16_t) (_a) - (s16_t) (_b))) +#define PTR_SUB(_a, _b) ((u8_t *) (_a) - (u8_t *) (_b)) +#endif + +#ifndef OFFSETOF +#define OFFSETOF(_s, _m) ((u32_t) PTR_SUB(&((_s *) 0)->_m, (u8_t *) 0)) +#endif +#define WORD_ALIGNED_OFFSETOF(_s, _m) (OFFSETOF(_s, _m) & ~0x03) + + +/* STATIC void + * get_attn_chng_bits( + * lm_device_t *pdev, + * u32_t *asserted_attns, + * u32_t *deasserted_attns); */ +#define GET_ATTN_CHNG_BITS(_pdev, _asserted_attns_ptr, _deasserted_attns_ptr) \ + { \ + u32_t attn_chng; \ + u32_t attn_bits; \ + u32_t attn_ack; \ + \ + attn_bits = (_pdev)->vars.status_virt->deflt.status_attn_bits; \ + attn_ack = (_pdev)->vars.status_virt->deflt.status_attn_bits_ack; \ + \ + attn_chng = attn_bits ^ attn_ack; \ + \ + *(_asserted_attns_ptr) = attn_bits & attn_chng; \ + *(_deasserted_attns_ptr) = ~attn_bits & attn_chng; \ + } + + + +/******************************************************************************* + * Statistics. + ******************************************************************************/ + +typedef struct _lm_tx_statistics_t +{ + lm_u64_t ipv4_lso_frames; + lm_u64_t ipv6_lso_frames; + lm_u64_t ip_cso_frames; + lm_u64_t ipv4_tcp_udp_cso_frames; + lm_u64_t ipv6_tcp_udp_cso_frames; + u32_t aborted; + u32_t no_bd; + u32_t no_desc; + u32_t no_coalesce_buf; + u32_t no_map_reg; +} lm_tx_stats_t; + + +typedef struct _lm_rx_statistics_t +{ + u32_t aborted; + u32_t err; + u32_t crc; + u32_t phy_err; + u32_t alignment; + u32_t short_packet; + u32_t giant_packet; +} lm_rx_stats_t; + + + +/******************************************************************************* + * Packet descriptor. + ******************************************************************************/ +#if defined(LM_NON_LEGACY_MODE_SUPPORT) +typedef struct _lm_packet_t +{ + /* Must be the first entry in this structure. */ + s_list_entry_t link; + + lm_status_t status; + + union _lm_pkt_info_t + { + struct _tx_pkt_info_t + { + lm_pkt_tx_info_t *tx_pkt_info; + u16_t next_bd_idx; + u16_t bd_used; + u8_t span_pages; + u8_t pad; + u16_t pad1; + u32_t size; + #if DBG + tx_bd_t *dbg_start_bd; + u16_t dbg_start_bd_idx; + u16_t dbg_frag_cnt; + #endif + } tx; + + struct _rx_pkt_info_t + { + lm_pkt_rx_info_t *rx_pkt_info; + u16_t next_bd_idx; + u16_t pad; + u32_t hash_value; /* RSS hash value. */ + #if DBG + rx_bd_t *dbg_bd; + rx_bd_t *dbg_bd1; /* when vmq header split is enabled */ + #endif + } rx; + } u1; +} lm_packet_t; +#else +typedef struct _lm_packet_t +{ + /* Must be the first entry in this structure. */ + s_list_entry_t link; + + lm_status_t status; + u32_t size; + + union _lm_pkt_info_t + { + struct _lm_tx_pkt_info_t + { + lm_tx_flag_t flags; + + u16_t vlan_tag; + u16_t next_bd_idx; + u16_t bd_used; + u8_t span_pages; + u8_t _pad; + + u16_t lso_mss; + u16_t _pad2; + + u16_t lso_ip_hdr_len; + u16_t lso_tcp_hdr_len; + + #if DBG + tx_bd_t *dbg_start_bd; + u16_t dbg_start_bd_idx; + u16_t dbg_frag_cnt; + #endif + } tx; + + struct _lm_rx_pkt_info_t + { + lm_rx_flag_t flags; + + u16_t vlan_tag; + u16_t ip_cksum; + u16_t tcp_or_udp_cksum; + u16_t next_bd_idx; + + u8_t *mem_virt; + lm_address_t mem_phy; + u32_t buf_size; + + u32_t hash_value; /* RSS hash value. */ + + #if DBG + rx_bd_t *dbg_bd; + #endif + } rx; + } u1; +} lm_packet_t; +#endif + +DECLARE_FRAG_LIST_BUFFER_TYPE(lm_packet_frag_list_t, MAX_FRAG_CNT); + + + +/******************************************************************************* + * Configurable parameters for the hardware dependent module. + ******************************************************************************/ + +typedef struct _lm_params_t +{ + /* This value is used by the upper module to inform the protocol + * of the maximum transmit/receive packet size. Packet size + * ranges from 1514-9014 bytes. This value does not include CRC32 and + * VLAN tag. */ + u32_t mtu; + /* Current node address. The MAC address is initially set to the + * hardware address. This entry can be modified to allow the driver + * to override the default MAC address. The new MAC address takes + * effect after a driver reset. */ + u8_t mac_addr[8]; + + u32_t l2_rx_desc_cnt[MAX_RX_CHAIN]; + u32_t l2_tx_bd_page_cnt[MAX_TX_CHAIN]; + u32_t l2_rx_bd_page_cnt[MAX_RX_CHAIN]; + + u32_t l4_tx_bd_page_cnt; + u32_t limit_l4_tx_bd_cnt; + u32_t l4_rx_bd_page_cnt; + u32_t limit_l4_rx_bd_cnt; + + #ifndef EXCLUDE_KQE_SUPPORT + u32_t kwq_page_cnt; + u32_t kcq_page_cnt; + u32_t kcq_history_size; + u32_t con_kcqe_history_size; + u32_t con_kwqe_history_size; + #endif + + u32_t gen_bd_page_cnt; + u32_t max_gen_buf_cnt; + u32_t gen_buf_per_alloc; + + /* This parameter controls whether the buffered data (generic buffers) + * should be copied to a staging buffer for indication. */ + u32_t copy_buffered_data; + + /* All the L2 receive buffers start at a cache line size aligned + * address. This value determines the location of the L2 frame header + * from the beginning of the receive buffer. The value must be a + * multiple of 4. */ + u32_t rcv_buffer_offset; + + /* Enable a separate receive queue for receiving packets with + * TCP SYN bit set. */ + u32_t enable_syn_rcvq; + + /* Buffer of hcopy descriptor to allocate for a connection. When + * this value is 0, hcopy is disabled. */ + u32_t hcopy_desc_cnt; + + /* Number of pages used for the hcopy bd chain. */ + u32_t hcopy_bd_page_cnt; + + /* This parameter is only valid when enable_hcopy is enabled. + * When enable_hcopy is enabled, a given connection will not + * be able to process subsequent kcqe's after the copy_gen kcqe + * until the hcopy request (for the copy_gen) has completed. + * The subsequent kcqe's will be copied to a per-connection kcq + * buffer. The parameter controls the size of this buffer. */ + u32_t buffered_kcqe_cnt; + + /* Size of the deferred kcqe queue. */ + u32_t deferred_kcqe_cnt; + + /* Various test/debug modes. Any validation failure will cause the + * driver to write to misc.swap_diag0 with the corresponding flag. + * The intention is to trigger the bus analyzer. */ + u32_t test_mode; + #define TEST_MODE_DISABLED 0x00 + #define TEST_MODE_OBSOLETE_0 0x01 /* was TEST_MODE_IKOS */ + #define TEST_MODE_OBSOLETE_1 0x02 /* was TEST_MODE_FPGA */ + #define TEST_MODE_VERIFY_RX_CRC 0x10 + #define TEST_MODE_RX_BD_TAGGING 0x20 + #define TEST_MODE_TX_BD_TAGGING 0x40 + #define TEST_MODE_LOG_REG_ACCESS 0x80 + #define TEST_MODE_SAVE_DUMMY_DMA_DATA 0x0100 + #define TEST_MODE_INIT_GEN_BUF_DATA 0x0200 + #define TEST_MODE_DRIVER_PULSE_ALWAYS_ALIVE 0x0400 + #define TEST_MODE_IGNORE_SHMEM_SIGNATURE 0x0800 + #define TEST_MODE_XDIAG_ISCSI 0x1000 + + lm_offload_t ofld_cap; + lm_wake_up_mode_t wol_cap; + lm_flow_control_t flow_ctrl_cap; + lm_medium_t req_medium; + + u32_t selective_autoneg; + #define SELECTIVE_AUTONEG_OFF 0 + #define SELECTIVE_AUTONEG_SINGLE_SPEED 1 + #define SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS 2 + + u32_t wire_speed; /* Not valid on SERDES. */ + u32_t phy_addr; /* PHY address. */ + + /* Ways for the MAC to determine a link change. */ + u32_t phy_int_mode; + #define PHY_INT_MODE_AUTO 0 + #define PHY_INT_MODE_MI_INTERRUPT 1 + #define PHY_INT_MODE_LINK_READY 2 + #define PHY_INT_MODE_AUTO_POLLING 3 + + /* Ways for the driver to get the link change event. */ + u32_t link_chng_mode; + #define LINK_CHNG_MODE_AUTO 0 + #define LINK_CHNG_MODE_USE_STATUS_REG 1 + #define LINK_CHNG_MODE_USE_STATUS_BLOCK 2 + + /* Coalescing paramers. */ + u32_t hc_timer_mode; + #define HC_COLLECT_MODE 0x0000 + #define HC_RX_TIMER_MODE 0x0001 + #define HC_TX_TIMER_MODE 0x0002 + #define HC_COM_TIMER_MODE 0x0004 + #define HC_CMD_TIMER_MODE 0x0008 + #define HC_TIMER_MODE 0x000f + + u32_t ind_comp_limit; + u32_t tx_quick_cons_trip; + u32_t tx_quick_cons_trip_int; + u32_t rx_quick_cons_trip; + u32_t rx_quick_cons_trip_int; + u32_t comp_prod_trip; + u32_t comp_prod_trip_int; + u32_t tx_ticks; + u32_t tx_ticks_int; + u32_t com_ticks; + u32_t com_ticks_int; + u32_t cmd_ticks; + u32_t cmd_ticks_int; + u32_t rx_ticks; + u32_t rx_ticks_int; + u32_t stats_ticks; + + /* Xinan per-processor HC configuration. */ + u32_t psb_tx_cons_trip; + u32_t psb_tx_ticks; + u32_t psb_rx_cons_trip; + u32_t psb_rx_ticks; + u32_t psb_comp_prod_trip; + u32_t psb_com_ticks; + u32_t psb_cmd_ticks; + u32_t psb_period_ticks; + + u32_t enable_fir; + u32_t num_rchans; + u32_t num_wchans; + u32_t one_tdma; + u32_t ping_pong_dma; + u32_t serdes_pre_emphasis; + u32_t tmr_reload_value1; + + u32_t keep_vlan_tag; + + u32_t enable_remote_phy; + u32_t rphy_req_medium; + u32_t rphy_flow_ctrl_cap; + u32_t rphy_selective_autoneg; + u32_t rphy_wire_speed; + + u32_t bin_mq_mode; + u32_t validate_l4_data; + + /* disable PCIe non-FATAL error reporting */ + u32_t disable_pcie_nfr; + + // setting for L2 flow control 0 for disable 1 for enable: + u32_t fw_flow_control; + // This parameter dictates how long to wait before dropping L2 packet + // due to insufficient posted buffers + // 0 mean no waiting before dropping, 0xFFFF means maximum wait + u32_t fw_flow_control_wait; + // 8 lsb represents watermark for flow control, 0 is disable + u32_t fw_flow_control_watermarks; + + u32_t ena_large_grc_timeout; + + /* 0 causes the driver to report the current flow control configuration. + * 1 causes the driver to report the flow control autoneg result. */ + u32_t flow_control_reporting_mode; +} lm_params_t; + + + +/******************************************************************************* + * Device NVM info -- The native strapping does not support the new parts, the + * software needs to reconfigure for them. + ******************************************************************************/ + +typedef struct _flash_spec_t +{ + u32_t buffered; + u32_t shift_bits; + u32_t page_size; + u32_t addr_mask; + u32_t total_size; +} flash_spec_t; + + +/******************************************************************************* + * Device info. + ******************************************************************************/ + +typedef struct _lm_hardware_info_t +{ + /* PCI info. */ + u16_t vid; + u16_t did; + u16_t ssid; + u16_t svid; + + u8_t irq; + u8_t int_pin; + u8_t latency_timer; + u8_t cache_line_size; + u8_t rev_id; + u8_t _pad[3]; + + u8_t mac_id; /* 5709 function 0 or 1. */ + u8_t bin_size; /* 5709 bin size in term of context pages. */ + u16_t first_l4_l5_bin; /* 5709 first bin. */ + + lm_address_t mem_base; + u32_t bar_size; + + /* Device info. */ + u32_t phy_id; /* (phy_reg2 << 16) | phy_reg3 */ + u8_t mac_addr[8]; /* Hardware MAC address. */ + u8_t iscsi_mac_addr[8]; /* Hardware MAC address for iSCSI. */ + + u32_t shmem_base; /* Firmware share memory base addr. */ + + u32_t chip_id; /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ + #define CHIP_NUM(_p) (((_p)->hw_info.chip_id) & 0xffff0000) + #define CHIP_NUM_5706 0x57060000 + #define CHIP_NUM_5708 0x57080000 + #define CHIP_NUM_5709 0x57090000 + #define CHIP_NUM_57728 0x00000000 + + #define CHIP_REV(_p) (((_p)->hw_info.chip_id) & 0x0000f000) + #define CHIP_REV_Ax 0x00000000 + #define CHIP_REV_Bx 0x00001000 + #define CHIP_REV_Cx 0x00002000 + #define CHIP_REV_FPGA 0x0000f000 + #define CHIP_REV_IKOS 0x0000e000 + + #define CHIP_METAL(_p) (((_p)->hw_info.chip_id) & 0x00000ff0) + #define CHIP_BONDING(_p) (((_p)->hw_info.chip_id) & 0x0000000f) + + #define CHIP_ID(_p) (((_p)->hw_info.chip_id) & 0xfffffff0) + #define CHIP_ID_5706_A0 0x57060000 + #define CHIP_ID_5706_A1 0x57060010 + #define CHIP_ID_5706_FPGA 0x5706f000 + #define CHIP_ID_5706_IKOS 0x5706e000 + #define CHIP_ID_5708_A0 0x57080000 + #define CHIP_ID_5708_B0 0x57081000 + #define CHIP_ID_5708_B1 0x57081010 + #define CHIP_ID_5708_FPGA 0x5708f000 + #define CHIP_ID_5708_IKOS 0x5708e000 + #define CHIP_ID_5709_A0 0x57090000 + #define CHIP_ID_5709_A1 0x57090010 + #define CHIP_ID_5709_B0 0x57091000 + #define CHIP_ID_5709_B1 0x57091010 + #define CHIP_ID_5709_B2 0x57091020 + #define CHIP_ID_5709_FPGA 0x5709f000 + #define CHIP_ID_5709_IKOS 0x5709e000 + + #define CHIP_BOND_ID(_p) (((_p)->hw_info.chip_id) & 0xf) + + /* A serdes chip will have the first bit of the bond id set. */ + #define CHIP_BOND_ID_SERDES_BIT 0x01 + + /* HW config from nvram. */ + u32_t nvm_hw_config; + + u32_t max_toe_conn; + u32_t max_iscsi_conn; + u32_t max_iscsi_pending_tasks; + + /* Bus info. */ + u8_t bus_mode; + #define BUS_MODE_PCI 0 + #define BUS_MODE_PCIX 1 + #define BUS_MODE_PCIE 2 + + u8_t bus_width; + #define BUS_WIDTH_32_BIT 32 + #define BUS_WIDTH_64_BIT 64 + + u16_t bus_speed; + #define BUS_SPEED_33_MHZ 33 + #define BUS_SPEED_50_MHZ 50 + #define BUS_SPEED_66_MHZ 66 + #define BUS_SPEED_100_MHZ 100 + #define BUS_SPEED_133_MHZ 133 + + /* EPB info. Only valid for 5708. */ + u8_t pcie_bus_num; + + u8_t pcie_max_width; + u8_t pcie_width; + #define PCIE_WIDTH_1 1 + #define PCIE_WIDTH_2 2 + #define PCIE_WIDTH_4 4 + #define PCIE_WIDTH_8 8 + #define PCIE_WIDTH_16 16 + #define PCIE_WIDTH_32 32 + + u8_t _unused_; + + u16_t pcie_max_speed; + u16_t pcie_speed; + #define PCIE_SPEED_2_5_G 25 + #define PCIE_SPEED_5_G 50 + + /* Flash info. */ + flash_spec_t flash_spec; +} lm_hardware_info_t; + + + +/******************************************************************************* + * Device state variables. + ******************************************************************************/ + +typedef struct _phy_mem_block_t +{ + lm_address_t start_phy; + u8_t *start; + u32_t size; +} phy_mem_block_t; + + +typedef struct _lm_variables_t +{ +#ifdef SOLARIS + ddi_acc_handle_t dmaRegAccHandle; +#endif + volatile reg_space_t *regview; + + volatile status_blk_combined_t *status_virt; + lm_address_t status_phy; + + lm_status_t link_status; + lm_medium_t medium; + lm_flow_control_t flow_control; + + /* remote phy status. */ + u8_t rphy_status; + #define RPHY_STATUS_ACTIVE 0x01 + #define RPHY_STATUS_MODULE_PRESENT 0x02 + + u8_t enable_cu_rate_limiter; + + u16_t bcm5706s_tx_drv_cur; + + volatile statistics_block_t *stats_virt; + lm_address_t stats_phy; + + u16_t fw_wr_seq; + u8_t fw_timed_out; + + /* Serdes autonegotiation fallback. For a serdes medium, + * if we cannot get link via autonegotiation, we'll force + * the speed to get link. */ + u8_t serdes_fallback_select; + u8_t serdes_fallback_status; + #define SERDES_FALLBACK_NONE 0 + #define SERDES_FALLBACK_1G 1 + #define SERDES_FALLBACK_2_5G 2 + + /* This flag is set if the cable is attached when there + * is no link. The upper module could check this flag to + * determine if there is a need to wait for link. */ + u8_t cable_is_attached; + + /* Write sequence for driver pulse. */ + u16_t drv_pulse_wr_seq; + + /* 5708 pre-emphasis. */ + u32_t serdes_pre_emphasis; + + u32_t interrupt_mode; + + u32_t cu_mbuf_cnt; /*5709 only */ + + u32_t hw_filter_ctx_offset; + /* 5709 backing store context memory. */ + #ifndef MAX_CTX + #define MAX_CTX (16 * 1024) + #endif + #define ONE_CTX_SIZE 0x80 + #define NUM_CTX_MBLKS 16 + #define CTX_MBLK_SIZE (128 * 1024) + phy_mem_block_t ctx_mem[NUM_CTX_MBLKS]; +} lm_variables_t; + + + +/******************************************************************************* + * Transmit info. + ******************************************************************************/ + +typedef struct _lm_tx_chain_t +{ + u32_t idx; + #define TX_CHAIN_IDX0 0 + #define TX_CHAIN_IDX1 1 + #define TX_CHAIN_IDX2 2 + #define TX_CHAIN_IDX3 3 + #define TX_CHAIN_IDX4 4 + #define TX_CHAIN_IDX5 5 + #define TX_CHAIN_IDX6 6 + #define TX_CHAIN_IDX7 7 + #define TX_CHAIN_IDX8 8 + #define TX_CHAIN_IDX9 9 + #define TX_CHAIN_IDX10 10 + #define TX_CHAIN_IDX11 11 + + u8_t cpu_num; + u8_t cpu_num_valid; + u16_t reserve2; + /* This is a contiguous memory block of params.l2_tx_bd_page_cnt pages + * used for L2 tx_bd chain. The BD chain is arranged as a circular + * chain where the last BD entry of a page points to the next page, + * and the last BD entry of the last page points to the first. */ + tx_bd_t *bd_chain_virt; + lm_address_t bd_chain_phy; + + u32_t cid_addr; + u16_t prod_idx; + u16_t con_idx; + tx_bd_t *prod_bd; + u32_t prod_bseq; + volatile u16_t *hw_con_idx_ptr; + u16_t bd_left; + + s_list_t active_descq; +} lm_tx_chain_t; + + +typedef struct _lm_tx_info_t +{ + lm_tx_chain_t chain[MAX_TX_CHAIN]; + + u32_t num_txq; + u32_t cu_idx; + + lm_tx_stats_t stats; +} lm_tx_info_t; + + + +/******************************************************************************* + * Receive info. + ******************************************************************************/ + +typedef struct _lm_rx_chain_t +{ + u32_t idx; + #define RX_CHAIN_IDX0 0 + #define RX_CHAIN_IDX1 1 + #define RX_CHAIN_IDX2 2 + #define RX_CHAIN_IDX3 3 + #define RX_CHAIN_IDX4 4 + #define RX_CHAIN_IDX5 5 + #define RX_CHAIN_IDX6 6 + #define RX_CHAIN_IDX7 7 + #define RX_CHAIN_IDX8 8 + #define RX_CHAIN_IDX9 9 + #define RX_CHAIN_IDX10 10 + #define RX_CHAIN_IDX11 11 + #define RX_CHAIN_IDX12 12 + #define RX_CHAIN_IDX13 13 + #define RX_CHAIN_IDX14 14 + #define RX_CHAIN_IDX15 15 + + u8_t cpu_num; /* place holder for cpu affinity(msix) */ + u8_t cpu_num_valid; + u16_t max_pkt_len; + /* This is a contiguous memory block of params.l2_rx_bd_page_cnt pages + * used for rx completion. The BD chain is arranged as a circular + * chain where the last BD entry of a page points to the next page, + * and the last BD entry of the last page points to the first. */ + rx_bd_t *bd_chain_virt; + lm_address_t bd_chain_phy; + + u32_t cid_addr; + u16_t prod_idx; + u16_t con_idx; + u16_t hw_con_idx; + u16_t _pad; + + rx_bd_t *prod_bd; + u32_t prod_bseq; + volatile u16_t *hw_con_idx_ptr; + u16_t bd_left; + + u32_t vmq_lookahead_size; + s_list_t free_descq; /* legacy mode variable */ + s_list_t active_descq; +} lm_rx_chain_t; + + +typedef struct _lm_rx_info_t +{ + lm_rx_chain_t chain[MAX_RX_CHAIN]; + + u32_t num_rxq; + + #define RX_FILTER_USER_IDX0 0 + #define RX_FILTER_USER_IDX1 1 + #define RX_FILTER_USER_IDX2 2 + #define RX_FILTER_USER_IDX3 3 + #define MAX_RX_FILTER_USER_CNT 4 + lm_rx_mask_t mask[MAX_RX_FILTER_USER_CNT]; + + lm_rx_stats_t stats; + + #ifndef EXCLUDE_RSS_SUPPORT + u32_t rss_tbl_size; + u8_t *rss_ind_table_virt; + lm_address_t rss_ind_table_phy; + #endif +} lm_rx_info_t; + + + +#ifndef EXCLUDE_KQE_SUPPORT +/******************************************************************************* + * Kernel work and completion queue info. + ******************************************************************************/ + +typedef struct _lm_kq_info_t +{ + u32_t kwq_cid_addr; + u32_t kcq_cid_addr; + + kwqe_t *kwq_virt; + kwqe_t *kwq_prod_qe; + kwqe_t *kwq_con_qe; + kwqe_t *kwq_last_qe; + u16_t kwq_prod_idx; + u16_t kwq_con_idx; + u32_t kwqe_left; + + kcqe_t *kcq_virt; + kcqe_t *kcq_con_qe; + kcqe_t *kcq_last_qe; + u16_t kcq_con_idx; + u16_t history_kcq_con_idx; + kcqe_t *history_kcq_con_qe; + + void *kwq_pgtbl_virt; + lm_address_t kwq_pgtbl_phy; + lm_address_t kwq_phy; + + void *kcq_pgtbl_virt; + lm_address_t kcq_pgtbl_phy; + lm_address_t kcq_phy; + + /* Statistics. */ + u32_t no_kwq_bd_left; +} lm_kq_info_t; +#endif /* EXCLUDE_KQE_SUPPORT */ + + + +/******************************************************************************* + * Include the l4 offload header file. + ******************************************************************************/ + +#if INCLUDE_OFLD_SUPPORT +#include "lm_ofld.h" +#else +/* This structure is only used as a placed holder and it is not referenced. */ +typedef struct _lm_offload_info_t +{ + void *unused; +} lm_offload_info_t; +#endif + + + +/******************************************************************************* + * Main device block. + ******************************************************************************/ + +typedef enum +{ + OS_TYPE_UNKNOWN = 0, + OS_TYPE_W2K = 1, + OS_TYPE_WXP = 2, + OS_TYPE_W2K3 = 3, + OS_TYPE_VISTA = 4, + OS_TYPE_W2K8 = 5, + OS_TYPE_WIN7 = 6, + OS_TYPE_WIN8 = 7, +} lm_os_type_t; + + +typedef struct _lm_device_t +{ + d_list_entry_t link; /* Link for the device list. */ + + u32_t ver_num; /* major:8 minor:8 rel:8 fix:8 */ + u8_t ver_str[32]; /* null terminated version string. */ + + lm_os_type_t os_type; + + lm_variables_t vars; + lm_tx_info_t tx_info; + lm_rx_info_t rx_info; + #ifndef EXCLUDE_KQE_SUPPORT + lm_kq_info_t kq_info; + #endif + lm_offload_info_t ofld; + lm_hardware_info_t hw_info; + lm_params_t params; + lm_mc_table_t mc_table; + lm_nwuf_list_t nwuf_list; + + #ifdef UEFI + EFI_PCI_IO_PROTOCOL *PciIoFuncs; + #endif + + /* Statistics. */ + u32_t chip_reset_cnt; + u32_t fw_timed_out_cnt; +} lm_device_t; + + + +/******************************************************************************* + * Functions exported between file modules. + ******************************************************************************/ + +lm_status_t +lm_mwrite( + lm_device_t *pdev, + u32_t phy_addr, + u32_t phy_reg, + u32_t val); + +lm_status_t +lm_mread( + lm_device_t *pdev, + u32_t phy_addr, + u32_t phy_reg, + u32_t *ret_val); + +u32_t +lm_nvram_query( + lm_device_t *pdev, + u8_t reset_flash_block, + u8_t no_hw_mod); + +void +lm_nvram_init( + lm_device_t *pdev, + u8_t reset_flash_block); + +lm_status_t +lm_nvram_read( + lm_device_t *pdev, + u32_t offset, + u32_t *ret_buf, + u32_t buf_size); /* Must be a multiple of 4. */ + +lm_status_t +lm_nvram_write( + lm_device_t *pdev, + u32_t offset, + u32_t *data_buf, + u32_t buf_size); /* Must be a multiple of 4. */ + +void +lm_init_cpus( + lm_device_t *pdev, + u32_t cpu_mask); +#define CPU_RV2P_1 0x00000001 +#define CPU_RV2P_2 0x00000002 +#define CPU_RXP 0x00000004 +#define CPU_TXP 0x00000008 +#define CPU_TPAT 0x00000010 +#define CPU_COM 0x00000020 +#define CPU_CP 0x00000040 +#define CPU_ALL 0xffffffff + +void +lm_reg_rd_ind( + lm_device_t *pdev, + u32_t offset, + u32_t *ret); + +void +lm_reg_wr_ind( + lm_device_t *pdev, + u32_t offset, + u32_t val); + +void +lm_ctx_wr( + lm_device_t *pdev, + u32_t cid_addr, + u32_t offset, + u32_t val); + +u32_t +lm_ctx_rd( + lm_device_t *pdev, + u32_t cid_addr, + u32_t offset); + +void +lm_setup_bd_chain_ring( + u8_t *mem_virt, + lm_address_t mem_phy, + u32_t page_cnt); + +lm_status_t +lm_init_remote_phy( + lm_device_t *pdev, + lm_link_settings_t *local_link, + lm_link_settings_t *rphy_link); + +lm_status_t +lm_init_mac_link( + lm_device_t *pdev); + +#ifndef EXCLUDE_KQE_SUPPORT +u32_t +lm_submit_kernel_wqes( + lm_device_t *pdev, + kwqe_t *wqes[], + u32_t num_wqes); + +u32_t +lm_get_kernel_cqes( + lm_device_t *pdev, + kcqe_t *cqe_ptr[], + u32_t ptr_cnt); + +u8_t +lm_ack_kernel_cqes( + lm_device_t *pdev, + u32_t num_cqes); + +void +lm_ack_completed_wqes( + lm_device_t *pdev); +#endif /* EXCLUDE_KQE_SUPPORT */ + +u8_t +fw_reset_sync( + lm_device_t *pdev, + lm_reason_t reason, + u32_t msg_data, + u32_t fw_ack_timeout_us); /* timeout in microseconds. */ + +void +lm_reg_rd_blk( + lm_device_t *pdev, + u32_t reg_offset, + u32_t *buf_ptr, + u32_t u32t_cnt); + +void +lm_reg_rd_blk_ind( + lm_device_t *pdev, + u32_t reg_offset, + u32_t *buf_ptr, + u32_t u32t_cnt); + +void +lm_reg_wr_blk( + lm_device_t *pdev, + u32_t reg_offset, + u32_t *data_ptr, + u32_t u32t_cnt); + +void +lm_reg_wr_blk_ind( + lm_device_t *pdev, + u32_t reg_offset, + u32_t *data_ptr, + u32_t u32t_cnt); + +lm_status_t +lm_submit_fw_cmd( + lm_device_t *pdev, + u32_t drv_msg); + +lm_status_t +lm_last_fw_cmd_status( + lm_device_t *pdev); + +#ifndef EXCLUDE_RSS_SUPPORT + +#if defined(LM_NON_LEGACY_MODE_SUPPORT) +lm_status_t +lm_enable_rss( + lm_device_t *pdev, + lm_rss_hash_t hash_type, + PROCESSOR_NUMBER *indirection_table, + u32_t table_size, + u8_t *hash_key, + u32_t key_size, + u8_t *cpu_tbl, + u8_t *rss_qidx_tbl); +#else +lm_status_t +lm_enable_rss( + lm_device_t *pdev, + lm_rss_hash_t hash_type, + u8_t *indirection_table, + u32_t table_size, + u8_t *hash_key, + u32_t key_size); +#endif + +lm_status_t +lm_disable_rss( + lm_device_t *pdev); +#endif /* EXCLUDE_RSS_SUPPORT */ + +lm_medium_t +lm_get_medium( + lm_device_t *pdev); + +u32_t +lm_mb_get_cid_addr( + lm_device_t *pdev, + u32_t cid); + +u32_t +lm_mb_get_bypass_addr( + lm_device_t *pdev, + u32_t cid); + +void +lm_set_pcie_nfe_report( + lm_device_t *pdev); + +void +lm_clear_coalescing_ticks( + lm_device_t *pdev); + +void +lm_post_rx_bd( + lm_device_t *pdev, + lm_rx_chain_t *rxq + ); + +void +lm_create_q_group( + lm_device_t *pdev, + u32_t q_group_id, + u32_t lookahead_sz + ); + +lm_status_t +lm_destroy_q_group( + lm_device_t *pdev, + u32_t q_group_id, + u32_t num_queues + ); + +void +lm_update_defq_filter_ctx( + lm_device_t *pdev, + u8_t valid + ); + +lm_status_t +lm_chng_q_group_filter( + lm_device_t *pdev, + u32_t q_group_id, + u8_t *dest_mac, + u16_t *vlan_ptr, + u32_t filter_id + ); + +#ifndef EXCLUDE_KQE_SUPPORT +u32_t +lm_service_l2_kcqes( + struct _lm_device_t *pdev, + kcqe_t *cqe_ptr[], + u32_t num_cqes); +#endif + +/******************************************************************************* + * Register access macros. + ******************************************************************************/ + +#if DBG && LOG_REG_ACCESS + +#define LOG_REG_RD(_pdev, _offset, _val) \ + if((_pdev)->params.test_mode & TEST_MODE_LOG_REG_ACCESS) \ + { \ + DbgMessage2(_pdev, INFORM, "rd 0x%04x = 0x%08x\n", _offset, _val); \ + } + +#define LOG_REG_WR(_pdev, _offset, _val) \ + if((_pdev)->params.test_mode & TEST_MODE_LOG_REG_ACCESS) \ + { \ + DbgMessage2(_pdev, INFORM, "wr 0x%04x 0x%08x\n", _offset, _val); \ + } + +#define LOG_MBQ_WR32(_pdev, _cid, _offset, _val) \ + if((_pdev)->params.test_mode & TEST_MODE_LOG_REG_ACCESS) \ + { \ + DbgMessage3(_pdev, INFORM, "mbq_wr32 (0x%04x,0x%02x) = 0x%08x\n", \ + _cid, _offset, _val); \ + } + +#define LOG_MBQ_WR32(_pdev, _cid, _offset, _val) \ + if((_pdev)->params.test_mode & TEST_MODE_LOG_REG_ACCESS) \ + { \ + DbgMessage3(_pdev, INFORM, "mbq_wr32 (0x%04x,0x%02x) = 0x%08x\n", \ + _cid, _offset, _val); \ + } + +#define LOG_MBQ_WR16(_pdev, _cid, _offset, _val) \ + if((_pdev)->params.test_mode & TEST_MODE_LOG_REG_ACCESS) \ + { \ + DbgMessage3(_pdev, INFORM, "mbq_wr16 (0x%04x,0x%02x) = 0x%04x\n", \ + _cid, _offset, _val); \ + } + +#define LOG_MBQ_WR8(_pdev, _cid, _offset, _val) \ + if((_pdev)->params.test_mode & TEST_MODE_LOG_REG_ACCESS) \ + { \ + DbgMessage3(_pdev, INFORM, "mbq_wr8 (0x%04x,0x%02x) = 0x%02x\n", \ + _cid, _offset, _val); \ + } + +#else +#define LOG_REG_RD(_pdev, _offset, _val) +#define LOG_REG_WR(_pdev, _offset, _val) +#define LOG_MBQ_WR32(_pdev, _cid, _offset, _val) +#define LOG_MBQ_WR16(_pdev, _cid, _offset, _val) +#define LOG_MBQ_WR8(_pdev, _cid, _offset, _val) +#endif + +/* Indirect register access. */ +#define REG_RD_IND(_pdev, _offset, _ret) lm_reg_rd_ind(_pdev, _offset, _ret) +#define REG_WR_IND(_pdev, _offset, _val) lm_reg_wr_ind(_pdev, _offset, _val) + +#ifdef CONFIG_PPC64 + +/* Register access via register name. */ +#define REG_RD(_pdev, _name, _ret) \ + mm_read_barrier(); \ + *(_ret) = pal_readl(&((_pdev)->vars.regview->_name)); \ + LOG_REG_RD( \ + _pdev, \ + OFFSETOF(reg_space_t, _name), \ + (_pdev)->vars.regview->_name) + +#define REG_WR(_pdev, _name, _val) \ + LOG_REG_WR(_pdev, OFFSETOF(reg_space_t, _name), _val); \ + pal_writel((_val), &((_pdev)->vars.regview->_name)); \ + mm_write_barrier() + + +/* Register access via register offset. */ +#define REG_RD_OFFSET(_pdev, _offset, _ret) \ + mm_read_barrier(); \ + *(_ret) = pal_readl((volatile u32_t *) ((u8_t *) (_pdev)->vars.regview + (_offset))); \ + LOG_REG_RD( \ + _pdev, \ + _offset, \ + *((volatile u32_t *) ((u8_t *) (_pdev)->vars.regview + (_offset)))) + +#define REG_WR_OFFSET(_pdev, _offset, _val) \ + LOG_REG_WR(_pdev, _offset, _val); \ + pal_writel((_val), (volatile u32_t *) ((u8_t *) (_pdev)->vars.regview + (_offset))); \ + mm_write_barrier() + + +/* Context write via mailbox queue. */ +#define MBQ_WR32(_pdev, _cid, _offset, _val) \ + LOG_MBQ_WR32(_pdev, _cid, _offset, _val); \ + pal_writel((_val), (volatile u32_t *) ((u8_t *) (_pdev)->vars.regview + \ + MB_GET_CID_ADDR(_pdev, _cid) + (_offset))); \ + mm_write_barrier(); \ + if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ + { \ + mm_wait(_pdev, 1); \ + } + +#define MBQ_WR16(_pdev, _cid, _offset, _val) \ + LOG_MBQ_WR16(_pdev, _cid, _offset, _val); \ + pal_writew((_val), (volatile u16_t *) ((u8_t *) (_pdev)->vars.regview + \ + MB_GET_CID_ADDR(_pdev, _cid) + (_offset))); \ + mm_write_barrier(); \ + if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ + { \ + mm_wait(_pdev, 1); \ + } + +#define MBQ_WR8(_pdev, _cid, _offset, _val) \ + LOG_MBQ_WR8(_pdev, _cid, _offset, _val); \ + pal_writeb((_val), (volatile u8_t *) ((u8_t *) (_pdev)->vars.regview + \ + MB_GET_CID_ADDR(_pdev, _cid) + (_offset))); \ + mm_write_barrier(); \ + if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ + { \ + mm_wait(_pdev, 1); \ + } + +#else /* CONFIG_PPC64 */ + +#ifdef SOLARIS + +/* Register access via register name. */ +#define REG_RD(_pdev, _name, _ret) \ + mm_read_barrier(); \ + if ((OFFSETOF(reg_space_t, _name) % 4) == 0) \ + { \ + *(_ret) = \ + ddi_get32((_pdev)->vars.dmaRegAccHandle, \ + (u32_t *)&(_pdev)->vars.regview->_name); \ + } \ + else \ + { \ + *(_ret) = \ + ddi_get16((_pdev)->vars.dmaRegAccHandle, \ + (u16_t *)&(_pdev)->vars.regview->_name); \ + } \ + LOG_REG_RD(_pdev, OFFSETOF(reg_space_t, _name), *(_ret)) + +#define REG_WR(_pdev, _name, _val) \ + LOG_REG_WR(_pdev, OFFSETOF(reg_space_t, _name), _val); \ + if ((OFFSETOF(reg_space_t, _name) % 4) == 0) \ + { \ + ddi_put32((_pdev)->vars.dmaRegAccHandle, \ + (u32_t *)&(_pdev)->vars.regview->_name, \ + (_val)); \ + } \ + else \ + { \ + ddi_put16((_pdev)->vars.dmaRegAccHandle, \ + (u16_t *)&(_pdev)->vars.regview->_name, \ + (u16_t)(_val)); \ + } \ + mm_write_barrier() + +/* Register access via register offset. */ +#define REG_RD_OFFSET(_pdev, _offset, _ret) \ + mm_read_barrier(); \ + *(_ret) = ddi_get32((_pdev)->vars.dmaRegAccHandle, \ + (u32_t *)((u8_t *)(_pdev)->vars.regview + (_offset))); \ + LOG_REG_RD(_pdev, _offset, *(_ret)) + +#define REG_WR_OFFSET(_pdev, _offset, _val) \ + LOG_REG_WR(_pdev, _offset, _val); \ + ddi_put32((_pdev)->vars.dmaRegAccHandle, \ + (u32_t *)((u8_t *)(_pdev)->vars.regview + (_offset)), \ + (_val)); \ + mm_write_barrier() + +/* Context write via mailbox queue. */ +#define MBQ_WR32(_pdev, _cid, _offset, _val) \ + LOG_MBQ_WR32(_pdev, _cid, _offset, _val); \ + ddi_put32((_pdev)->vars.dmaRegAccHandle, \ + (u32_t *)((u8_t *)(_pdev)->vars.regview + \ + MB_GET_CID_ADDR(_pdev, _cid) + (_offset)), \ + (_val)); \ + mm_write_barrier(); \ + if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ + { \ + mm_wait(_pdev, 1); \ + } + +#define MBQ_WR16(_pdev, _cid, _offset, _val) \ + LOG_MBQ_WR16(_pdev, _cid, _offset, _val); \ + ddi_put16((_pdev)->vars.dmaRegAccHandle, \ + (u16_t *)((u8_t *)(_pdev)->vars.regview + \ + MB_GET_CID_ADDR(_pdev, _cid) + (_offset)), \ + (u16_t)(_val)); \ + mm_write_barrier(); \ + if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ + { \ + mm_wait(_pdev, 1); \ + } + +#define MBQ_WR8(_pdev, _cid, _offset, _val) \ + LOG_MBQ_WR8(_pdev, _cid, _offset, _val); \ + ddi_put8((_pdev)->vars.dmaRegAccHandle, \ + (u8_t *)((u8_t *)(_pdev)->vars.regview + \ + MB_GET_CID_ADDR(_pdev, _cid) + (_offset)), \ + (u8_t)(_val)); \ + mm_write_barrier(); \ + if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ + { \ + mm_wait(_pdev, 1); \ + } + +#elif !defined(UEFI) + +/* Register access via register name. */ +#define REG_RD(_pdev, _name, _ret) \ + mm_read_barrier(); \ + *(_ret) = ((_pdev)->vars.regview->_name); \ + LOG_REG_RD( \ + _pdev, \ + OFFSETOF(reg_space_t, _name), \ + (_pdev)->vars.regview->_name) + +#define REG_WR(_pdev, _name, _val) \ + LOG_REG_WR(_pdev, OFFSETOF(reg_space_t, _name), _val); \ + (_pdev)->vars.regview->_name = (_val); \ + mm_write_barrier() + + +/* Register access via register offset. */ +#define REG_RD_OFFSET(_pdev, _offset, _ret) \ + mm_read_barrier(); \ + *(_ret) = *((volatile u32_t *) ((u8_t *) (_pdev)->vars.regview+(_offset)));\ + LOG_REG_RD( \ + _pdev, \ + _offset, \ + *((volatile u32_t *) ((u8_t *) (_pdev)->vars.regview + (_offset)))) + +#define REG_WR_OFFSET(_pdev, _offset, _val) \ + LOG_REG_WR(_pdev, _offset, _val); \ + *((volatile u32_t *) ((u8_t *) (_pdev)->vars.regview+(_offset)))=(_val); \ + mm_write_barrier() + + +/* Context write via mailbox queue. */ +#define MBQ_WR32(_pdev, _cid, _offset, _val) \ + LOG_MBQ_WR32(_pdev, _cid, _offset, _val); \ + *((volatile u32_t *) (((u8_t *) (_pdev)->vars.regview) + \ + MB_GET_CID_ADDR(_pdev, _cid) + (_offset))) = (_val); \ + mm_write_barrier(); \ + if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ + { \ + mm_wait(_pdev, 1); \ + } + +#define MBQ_WR16(_pdev, _cid, _offset, _val) \ + LOG_MBQ_WR16(_pdev, _cid, _offset, _val); \ + *((volatile u16_t *) (((u8_t *) (_pdev)->vars.regview) + \ + MB_GET_CID_ADDR(_pdev, _cid) + (_offset))) = (u16_t) (_val); \ + mm_write_barrier(); \ + if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ + { \ + mm_wait(_pdev, 1); \ + } + +#define MBQ_WR8(_pdev, _cid, _offset, _val) \ + LOG_MBQ_WR8(_pdev, _cid, _offset, _val); \ + *((volatile u8_t *) (((u8_t *) (_pdev)->vars.regview) + \ + MB_GET_CID_ADDR(_pdev, _cid) + (_offset))) = (u8_t) (_val); \ + mm_write_barrier(); \ + if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ + { \ + mm_wait(_pdev, 1); \ + } + +#else //UEFI + +/* Register access via register name. */ +#define REG_RD(_pdev, _name, _ret) \ + if ((OFFSETOF(reg_space_t, _name) % 4) == 0) \ + { \ + (_pdev)->PciIoFuncs->Mem.Read( \ + (_pdev)->PciIoFuncs, \ + EfiPciIoWidthUint32, \ + 0, \ + (UINT64)(OFFSETOF(reg_space_t, _name)), \ + 1, \ + _ret); \ + } \ + else \ + { \ + (_pdev)->PciIoFuncs->Mem.Read( \ + (_pdev)->PciIoFuncs, \ + EfiPciIoWidthUint16, \ + 0, \ + (UINT64)(OFFSETOF(reg_space_t, _name)), \ + 1, \ + _ret); \ + } + +#define REG_WR(_pdev, _name, _val) \ + if ((OFFSETOF(reg_space_t, _name) % 4) == 0) \ + { \ + { \ + u32_t w_val; \ + w_val = _val; \ + (_pdev)->PciIoFuncs->Mem.Write( \ + (_pdev)->PciIoFuncs, \ + EfiPciIoWidthUint32, \ + 0, \ + (UINT64)(OFFSETOF(reg_space_t, _name)), \ + 1, \ + &w_val); \ + } \ + } \ + else \ + { \ + { \ + u16_t w_val; \ + w_val = (u16_t)_val; \ + (_pdev)->PciIoFuncs->Mem.Write( \ + (_pdev)->PciIoFuncs, \ + EfiPciIoWidthUint16, \ + 0, \ + (UINT64)(OFFSETOF(reg_space_t, _name)), \ + 1, \ + &w_val); \ + } \ + } + + +/* Register access via register offset. */ +#define REG_RD_OFFSET(_pdev, _offset, _ret) \ + (_pdev)->PciIoFuncs->Mem.Read( \ + (_pdev)->PciIoFuncs, \ + EfiPciIoWidthUint32, \ + 0, \ + (UINT64)(_offset), \ + 1, \ + _ret) + +#define REG_WR_OFFSET(_pdev, _offset, _val) \ + { \ + u32_t w_val; \ + w_val = _val; \ + (_pdev)->PciIoFuncs->Mem.Write( \ + (_pdev)->PciIoFuncs, \ + EfiPciIoWidthUint32, \ + 0, \ + (UINT64)(_offset), \ + 1, \ + &w_val); \ + } + + +/* Context write via mailbox queue. */ +#define MBQ_WR32(_pdev, _cid, _offset, _val) \ + { \ + u32_t w_val; \ + w_val = _val; \ + (_pdev)->PciIoFuncs->Mem.Write( \ + (_pdev)->PciIoFuncs, \ + EfiPciIoWidthUint32, \ + 0, \ + (UINT64)(MB_GET_CID_ADDR(_pdev, _cid) + (_offset)), \ + 1, \ + &w_val); \ + if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ + { \ + mm_wait(_pdev, 1); \ + } \ + } + +#define MBQ_WR16(_pdev, _cid, _offset, _val) \ + { \ + u16_t w_val; \ + w_val = _val; \ + (_pdev)->PciIoFuncs->Mem.Write( \ + (_pdev)->PciIoFuncs, \ + EfiPciIoWidthUint16, \ + 0, \ + (UINT64)(MB_GET_CID_ADDR(_pdev, _cid) + (_offset)), \ + 1, \ + &w_val); \ + if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ + { \ + mm_wait(_pdev, 1); \ + } \ + } + +#define MBQ_WR8(_pdev, _cid, _offset, _val) \ + { \ + u8_t w_val; \ + w_val = _val; \ + (_pdev)->PciIoFuncs->Mem.Write( \ + (_pdev)->PciIoFuncs, \ + EfiPciIoWidthUint8, \ + 0, \ + (UINT64)(MB_GET_CID_ADDR(_pdev, _cid) + (_offset)), \ + 1, \ + &w_val); \ + if(CHIP_REV(_pdev) == CHIP_REV_IKOS) \ + { \ + mm_wait(_pdev, 1); \ + } \ + } + +#endif //!UEFI + +#endif /* CONFIG_PPC64 */ + +/* Indirect context access. Unlike the MBQ_WR, these macros will not + * trigger a chip event. */ +#define CTX_WR(_pdev, _cid_addr, _offset, _val) \ + lm_ctx_wr(_pdev, _cid_addr, _offset, _val) + +#define CTX_RD(_pdev, _cid_addr, _offset) \ + lm_ctx_rd(_pdev, _cid_addr, _offset) + + +/* Away to trigger the bus analyzer. */ +#define TRIGGER(_pdev, _val) REG_WR(_pdev, misc.misc_id, _val) + + + +#endif /* _LM5706_H */ + diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/rv2p_p1.h b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/rv2p_p1.h new file mode 100644 index 0000000000..5d7b556cf4 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/rv2p_p1.h @@ -0,0 +1,497 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __rv2p_proc1_h__ +#define __rv2p_proc1_h__ +#include "bcmtype.h" + +u32_t rv2p_proc1[] = { + 0x00000010, 0xb1800006, + 0x0000001f, 0x01060201, + 0x00000008, 0x05000000, + 0x00000018, 0x00020000, + 0x00000008, 0x050000ff, + 0x00000018, 0x00020000, + 0x00000008, 0xac000001, + 0x00000008, 0x07800000, + 0x0000000c, 0x2f800001, + 0x00000000, 0x2b000000, + 0x00000000, 0x2b800000, + 0x00000010, 0x91e10002, + 0x00000008, 0xac000001, + 0x00000010, 0x203f0058, + 0x00000010, 0x213f0003, + 0x00000010, 0x20bf0032, + 0x00000018, 0x8000fffd, + 0x00000008, 0x03800800, + 0x00000010, 0xb6380e01, + 0x00000010, 0xb1b8b00d, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c380000, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000006e, + 0x00000018, 0x80000145, + 0x00000008, 0x02000002, + 0x0000000f, 0x42e0001c, + 0x00000010, 0x91840a11, + 0x00000010, 0x2c62000b, + 0x00000018, 0x8000001b, + 0x00000008, 0x02000002, + 0x0000000f, 0x42e0001c, + 0x00000010, 0x91840a16, + 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800108, + 0x00000018, 0x80000074, + 0x00000018, 0x80000012, + 0x00000008, 0xb1000001, + 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800001, + 0x00000018, 0x80000061, + 0x0000000b, 0x2fdf0002, + 0x0000000c, 0x1f800002, + 0x00000000, 0x2c070000, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000ffd9, + 0x0000000b, 0x2fdf0002, + 0x0000000c, 0x1f800000, + 0x00000000, 0x2c070000, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000ffd4, + 0x0000000c, 0x1f800002, + 0x00000018, 0x8000ffd2, + 0x00000010, 0x0ce70002, + 0x00000010, 0x2ce20046, + 0x0000000c, 0x29800002, + 0x0000000c, 0x1f800002, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000005, + 0x00000018, 0x8000ffcb, + 0x00000008, 0x02240042, + 0x00000018, 0x00040000, + 0x00000018, 0x80000000, + 0x00000018, 0x8000001b, + 0x00000018, 0x80000060, + 0x00000018, 0x800000a0, + 0x00000018, 0x800000da, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000121, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x800000f0, + 0x00000018, 0x80000000, + 0x00000018, 0x80000120, + 0x00000018, 0x8000014a, + 0x00000018, 0x80000117, + 0x00000018, 0x8000016d, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000002, + 0x00000008, 0x07800000, + 0x00000018, 0x8000ffa7, + 0x00000008, 0x03800100, + 0x00000010, 0xb73c0e00, + 0x00000010, 0xb1bcb00a, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c3c0000, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000001a, + 0x00000018, 0x800000f1, + 0x00000010, 0x2c6201c4, + 0x00000018, 0x80000006, + 0x00000008, 0x2c8000b1, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x00000018, 0x80000026, + 0x0000000c, 0x29800000, + 0x0000000c, 0x1f800000, + 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, + 0x00000010, 0x2e670005, + 0x00000010, 0x0ce20004, + 0x00000018, 0x80000005, + 0x00000008, 0x2a000011, + 0x00000018, 0x80000002, + 0x00000008, 0x2a000006, + 0x00000018, 0x8000ff8b, + 0x0000000c, 0x71620019, + 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800001, + 0x00000018, 0x00020000, + 0x00000018, 0x00020000, + 0x00000000, 0x06820000, + 0x00000010, 0xb18f0004, + 0x00000010, 0xb18f1403, + 0x00000008, 0x2a000001, + 0x00000010, 0x91d40000, + 0x00000000, 0x07801400, + 0x00000018, 0x000d0000, + 0x00000000, 0x05020000, + 0x00000010, 0x91de0000, + 0x00000018, 0x000a0000, + 0x00000000, 0x06820000, + 0x00000010, 0x91de0000, + 0x00000009, 0x0561ffff, + 0x00000010, 0x918a0002, + 0x00000008, 0x30e1ffff, + 0x00000018, 0x8000ff6e, + 0x00000001, 0x05611400, + 0x00000010, 0x918a0002, + 0x00000008, 0xb0e10001, + 0x00000018, 0x000d0000, + 0x00000000, 0x06820000, + 0x00000010, 0x91de0000, + 0x00000009, 0x0562ffff, + 0x00000010, 0x918a0002, + 0x00000008, 0x3162ffff, + 0x00000018, 0x8000ff64, + 0x00000001, 0x05621400, + 0x00000010, 0x918a0002, + 0x00000008, 0xb1620001, + 0x00000018, 0x000d0000, + 0x00000010, 0xb1a0b013, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000ffdb, + 0x00000008, 0x2d80011c, + 0x00000010, 0x001f0000, + 0x00000018, 0x8000ffe2, + 0x0000000f, 0x47600008, + 0x0000000f, 0x060e0001, + 0x00000000, 0x0f580000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0d610000, + 0x00000018, 0x80000015, + 0x0000000f, 0x47600008, + 0x0000000b, 0x2fdf0002, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d80011c, + 0x0000000f, 0x060e0001, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f580000, + 0x00000018, 0x8000ffd0, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0d610000, + 0x00000000, 0x02620000, + 0x00000000, 0x02e00000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x30050000, + 0x00000000, 0x31040000, + 0x00000000, 0x309a0000, + 0x00000010, 0x0060000c, + 0x00000010, 0x21a2000b, + 0x00000010, 0xb1a6000a, + 0x00000008, 0x05160001, + 0x00000010, 0xba9a1403, + 0x00000000, 0x03000000, + 0x00000018, 0x80000006, + 0x00000018, 0x8000ff2f, + 0x00000010, 0xb6061404, + 0x00000008, 0x03060001, + 0x00000008, 0x2a000001, + 0x00000018, 0x8000ff34, + 0x00000000, 0x0c961800, + 0x00000009, 0x0c99ffff, + 0x00000004, 0xcc993400, + 0x00000010, 0xba992c02, + 0x00000008, 0x0f800000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x29520001, + 0x0000000c, 0x29520000, + 0x00000008, 0x22800002, + 0x00000008, 0x02000003, + 0x0000000c, 0x1f800001, + 0x00000000, 0x2adf0000, + 0x00000000, 0x2a000800, + 0x00000018, 0x8000ff26, + 0x00000010, 0xb1a0b016, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000ff9c, + 0x00000018, 0x80000073, + 0x0000000f, 0x47600008, + 0x00000000, 0x060e0000, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f580000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000000, 0x0b670000, + 0x00000000, 0x0d620000, + 0x00000000, 0x0ce71800, + 0x00000009, 0x0c99ffff, + 0x00000004, 0xcc993400, + 0x00000010, 0xba992c20, + 0x00000008, 0x0f800000, + 0x00000018, 0x8000001e, + 0x0000000f, 0x47600008, + 0x0000000b, 0x2fdf0002, + 0x00000008, 0x2c8000b1, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d80012b, + 0x0000000f, 0x060e0001, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f580000, + 0x00000018, 0x8000ff96, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000000, 0x0b670000, + 0x00000000, 0x0d620000, + 0x00000000, 0x02630000, + 0x0000000f, 0x47620010, + 0x00000000, 0x0ce71800, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x31840000, + 0x00000000, 0x311a0000, + 0x0000000b, 0xc20000ff, + 0x00000002, 0x42040000, + 0x00000001, 0x31620800, + 0x0000000f, 0x020e0010, + 0x00000002, 0x31620800, + 0x00000009, 0x0c99ffff, + 0x00000004, 0xcc993400, + 0x00000010, 0xba992c02, + 0x00000008, 0x0f800000, + 0x00000010, 0x2ce20168, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x0000000c, 0x61420006, + 0x00000008, 0x22000008, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000004, + 0x00000018, 0x8000feeb, + 0x00000010, 0x91a0b009, + 0x00000008, 0x2c8000b1, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x00000018, 0x8000ff75, + 0x00000018, 0x8000000f, + 0x00000008, 0xac000001, + 0x00000018, 0x8000000b, + 0x00000000, 0x0380b000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c004000, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000ff58, + 0x00000018, 0x8000002f, + 0x00000018, 0x80000005, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c000e00, + 0x00000008, 0x2a000007, + 0x00000018, 0x8000fed6, + 0x00000000, 0x06820000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000010, 0x0ce70007, + 0x00000009, 0x0562ffff, + 0x00000010, 0xba6c1405, + 0x00000000, 0x2adf0000, + 0x00000000, 0x21000000, + 0x00000008, 0x2a000005, + 0x00000010, 0x91d40000, + 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, + 0x0000000c, 0x31620018, + 0x00000008, 0x2d800001, + 0x00000018, 0x8000ff4a, + 0x00000018, 0x000d0000, + 0x00000010, 0xb1a0b00d, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c200000, + 0x00000010, 0x91d40000, + 0x00000018, 0x80000014, + 0x00000010, 0x2c620002, + 0x00000018, 0x8000000b, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c070000, + 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000feb9, + 0x00000008, 0x2c8000b1, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x00000018, 0x8000ff44, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000a, + 0x00000008, 0x07800000, + 0x00000018, 0x8000fead, + 0x00000000, 0x06820000, + 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800150, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d800105, + 0x00000009, 0x0562ffff, + 0x00000010, 0x918a0002, + 0x00000008, 0x3162ffff, + 0x00000018, 0x8000fe99, + 0x00000001, 0x05621400, + 0x00000010, 0x918a0002, + 0x00000008, 0xb1620001, + 0x00000010, 0x91de0000, + 0x00000018, 0x000d0000, + 0x00000010, 0x91d40000, + 0x00000008, 0x050000aa, + 0x00000018, 0x8000ff14, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000009, + 0x00000018, 0x8000fe94, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000ff0d, + 0x00000010, 0x91a0b002, + 0x00000010, 0xb1e66207, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c310000, + 0x00000009, 0x2cb1007f, + 0x00000008, 0x2cd90000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d80010d, + 0x00000010, 0xb1a80006, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c200000, + 0x00000000, 0x2ca70000, + 0x00000008, 0x2d000010, + 0x00000008, 0x2d800108, + 0x00000018, 0x8000ff05, + 0x00000010, 0xb1a60010, + 0x00000010, 0x001f0000, + 0x0000000f, 0x0f300007, + 0x00000000, 0x0a600000, + 0x00000000, 0x0ae10000, + 0x0000000f, 0x4b620008, + 0x00000009, 0x0b1600ff, + 0x00000000, 0x0d620000, + 0x00000009, 0x0d1a00ff, + 0x00000010, 0x07300003, + 0x0000000c, 0x0d1a0008, + 0x0000000c, 0x0b160008, + 0x0000000f, 0x4ce30018, + 0x00000000, 0x0c992c00, + 0x00000004, 0xcc993400, + 0x00000008, 0x0f800000, + 0x0000000c, 0x29800001, + 0x00000000, 0x33310000, + 0x00000008, 0x22000016, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000c, + 0x00000010, 0x009f0000, + 0x00000000, 0x2c200000, + 0x0000000c, 0x1f800001, + 0x00000018, 0x8000fe69, + 0x00000010, 0x91d40000, + 0x00000008, 0x050000aa, + 0x00000018, 0x8000fee2, + 0x0000000f, 0x47220008, + 0x00000009, 0x070e000f, + 0x00000008, 0x070e0008, + 0x00000008, 0x02800001, + 0x00000007, 0x02851c00, + 0x00000008, 0x82850001, + 0x00000000, 0x02854c00, + 0x00000007, 0x42851c00, + 0x00000003, 0xc3aa5200, + 0x00000000, 0x03b10e00, + 0x00000007, 0x4b071c00, + 0x0000000f, 0x0f300007, + 0x0000000f, 0x0a960003, + 0x00000000, 0x0a955c00, + 0x00000000, 0x4a005a00, + 0x00000000, 0x0c960a00, + 0x00000009, 0x0c99ffff, + 0x00000008, 0x0d00ffff, + 0x00000010, 0xba992c02, + 0x00000008, 0x0f800005, + 0x00000010, 0xb1a80008, + 0x00000010, 0x205f0000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, + 0x00000000, 0x2ca70000, + 0x00000008, 0x2d000010, + 0x00000008, 0x2d800108, + 0x00000018, 0x8000fecd, + 0x0000000c, 0x29800001, + 0x00000010, 0x001f0000, + 0x0000000c, 0x1f800001, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000d, + 0x00000018, 0x8000fe44, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000febd, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000007, + 0x00000018, 0x8000fe3d, +}; +/* Calling this macro prior to loading will change value of POST_WAIT_TIMEOUT (default = 0x0)*/ +#define RV2P_PROC1_POST_WAIT_TIMEOUT_LOC 5 +#define RV2P_PROC1_CHG_POST_WAIT_TIMEOUT(value) {\ + rv2p_proc1[RV2P_PROC1_POST_WAIT_TIMEOUT_LOC] = (rv2p_proc1[RV2P_PROC1_POST_WAIT_TIMEOUT_LOC] & ~0xFFFF) | (value);\ +} + +/* Calling this macro prior to loading will change value of MAX_BD_PAGE (default = 0xff)*/ +#define RV2P_PROC1_MAX_BD_PAGE_LOC 9 +#define RV2P_PROC1_CHG_MAX_BD_PAGE(value) {\ + rv2p_proc1[RV2P_PROC1_MAX_BD_PAGE_LOC] = (rv2p_proc1[RV2P_PROC1_MAX_BD_PAGE_LOC] & ~0xFFFF) | (value);\ +} + +#endif /* __rv2p_proc1.h__ */ + diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/rv2p_p2.h b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/rv2p_p2.h new file mode 100644 index 0000000000..4c09c995dd --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/rv2p_p2.h @@ -0,0 +1,917 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __rv2p_proc2_h__ +#define __rv2p_proc2_h__ +#include "bcmtype.h" + +u32_t rv2p_proc2[] = { + 0x00000010, 0xb1800006, + 0x0000001f, 0x01060201, + 0x00000008, 0x050000ff, + 0x00000018, 0x00020000, + 0x00000008, 0x05000001, + 0x00000018, 0x00020000, + 0x00000000, 0x2a000000, + 0x00000010, 0xb1d40000, + 0x00000010, 0x91de0000, + 0x00000010, 0x20530000, + 0x00000010, 0x001f0000, + 0x00000000, 0x2f80aa00, + 0x0000000c, 0x29800001, + 0x00000008, 0x02540010, + 0x00000000, 0x2c400000, + 0x00000000, 0x0f400000, + 0x00000018, 0x00040000, + 0x00000018, 0x80000011, + 0x00000018, 0x80000012, + 0x00000018, 0x80000038, + 0x00000018, 0x80000069, + 0x00000018, 0x80000187, + 0x00000018, 0x800001ca, + 0x00000018, 0x800002af, + 0x00000018, 0x80000000, + 0x00000018, 0x800002c8, + 0x00000018, 0x8000017c, + 0x00000018, 0x80000000, + 0x00000018, 0x800002cc, + 0x00000018, 0x8000031a, + 0x00000018, 0x8000005b, + 0x00000018, 0x8000005b, + 0x00000018, 0x8000005c, + 0x00000018, 0x8000019b, + 0x00000000, 0x2a000000, + 0x00000018, 0x8000ffe4, + 0x00000000, 0x2a000000, + 0x0000000c, 0x29800000, + 0x00000018, 0x8000ffe1, + 0x00000018, 0x00020000, + 0x00000000, 0x05020000, + 0x00000010, 0xb99a2c21, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d000006, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d610000, + 0x00000018, 0x000a0000, + 0x00000000, 0x05020000, + 0x00000010, 0xb99a2c16, + 0x00000010, 0x205f0000, + 0x00000000, 0x09d80000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c8000b2, + 0x00000008, 0x2d00000a, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d620000, + 0x00000000, 0x2c130000, + 0x00000018, 0x000a0000, + 0x00000000, 0x05020000, + 0x00000010, 0xb99a2c09, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d00006a, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d7a0000, + 0x00000018, 0x000a0000, + 0x00000000, 0x2a000000, + 0x00000008, 0x22000001, + 0x00000000, 0x0d610000, + 0x00000010, 0x21c20025, + 0x00000010, 0xb1c60002, + 0x00000010, 0x2342002c, + 0x00000009, 0x0b66ffff, + 0x00000010, 0xba9a2c21, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000000, 0x0c000000, + 0x00000000, 0x0b800000, + 0x00000008, 0x0cc60012, + 0x00000018, 0x8000ffd0, + 0x00000008, 0x0f800003, + 0x00000000, 0x00000000, + 0x00000010, 0x009f0000, + 0x00000010, 0x919b3200, + 0x00000008, 0x27110012, + 0x00000000, 0x66900000, + 0x00000010, 0xb1980003, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800004, + 0x00000008, 0x22000003, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d00000c, + 0x00000010, 0x009f0000, + 0x00000010, 0x91c60005, + 0x00000010, 0x001f0000, + 0x00000010, 0xba9a2c03, + 0x00000008, 0x0f800004, + 0x00000018, 0x8000fffd, + 0x00000000, 0x25960000, + 0x0000000c, 0x29800000, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000005, 0x73662c00, + 0x00000000, 0x31e32e00, + 0x00000008, 0x2d800010, + 0x00000018, 0x8000ff95, + 0x00000000, 0x23000000, + 0x00000009, 0x25e6ffff, + 0x00000008, 0x2200000b, + 0x0000000c, 0x69520000, + 0x0000000c, 0x29800000, + 0x00000018, 0x8000ff8f, + 0x00000018, 0x8000ff8e, + 0x00000000, 0x2a000000, + 0x00000018, 0x8000ff8c, + 0x00000018, 0x80000000, + 0x00000000, 0x02700000, + 0x00000000, 0x0d620000, + 0x00000000, 0xbc630800, + 0x00000000, 0x2a000000, + 0x00000009, 0x076000ff, + 0x0000000f, 0x2c0e0007, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d00006a, + 0x00000008, 0x2d800116, + 0x0000000c, 0x61420001, + 0x00000000, 0x05780000, + 0x00000010, 0x0ce70002, + 0x00000003, 0x85721400, + 0x00000000, 0x3c8a0000, + 0x00000000, 0x02d08c00, + 0x00000000, 0x23000000, + 0x00000004, 0x826da000, + 0x00000000, 0x8304a000, + 0x00000000, 0x22c50c00, + 0x00000010, 0x91ed0802, + 0x00000003, 0xbcf80a00, + 0x00000010, 0x0d67000a, + 0x00000010, 0x24c20007, + 0x00000010, 0x01c20008, + 0x0000000c, 0x61420003, + 0x00000010, 0xb96f0856, + 0x00000010, 0xb7ef0a03, + 0x0000000c, 0x21420003, + 0x00000018, 0x80000003, + 0x00000018, 0x80000047, + 0x00000018, 0x80000051, + 0x00000004, 0x83790800, + 0x00000004, 0x83860a00, + 0x00000000, 0x83870c00, + 0x00000010, 0x91de0000, + 0x00000009, 0x057affff, + 0x00000010, 0x918a0002, + 0x00000008, 0x3d7affff, + 0x00000018, 0x8000ff5f, + 0x00000001, 0x057a1400, + 0x00000010, 0x918a0002, + 0x00000008, 0xbd7a0001, + 0x00000000, 0x037c0000, + 0x00000000, 0x837b0c00, + 0x00000001, 0x83060e00, + 0x00000000, 0x83870c00, + 0x00000000, 0x82850e00, + 0x00000010, 0xb186000e, + 0x0000000f, 0x47610018, + 0x00000000, 0x068e0000, + 0x0000000f, 0x47670010, + 0x0000000f, 0x45620010, + 0x00000000, 0x870e1400, + 0x00000010, 0xb70e1a08, + 0x00000010, 0x0ce70006, + 0x00000010, 0x0ce70003, + 0x00000000, 0x056d0000, + 0x00000018, 0x80000215, + 0x00000000, 0x37ed0000, + 0x0000000c, 0x73e7001a, + 0x00000003, 0x82f90a00, + 0x00000004, 0x82840a00, + 0x00000010, 0xb1840a31, + 0x00000010, 0x2d67000a, + 0x00000010, 0xb96d0804, + 0x00000004, 0xb6ed0a00, + 0x00000000, 0x37ed0000, + 0x00000018, 0x80000030, + 0x00000000, 0x37040000, + 0x00000000, 0x37850000, + 0x0000000c, 0x33e7001a, + 0x00000018, 0x80000217, + 0x00000018, 0x8000002b, + 0x00000010, 0xb96d0810, + 0x0000000c, 0x21420007, + 0x00000004, 0xb6ed0a00, + 0x00000000, 0x036d0000, + 0x00000004, 0xb76e0c00, + 0x00000010, 0x91ee0c25, + 0x00000004, 0xb6ef0c00, + 0x0000000c, 0x21420008, + 0x0000000c, 0x73e7001a, + 0x00000000, 0x37ed0000, + 0x00000010, 0x0ce70002, + 0x0000000c, 0x21420006, + 0x00000010, 0x0ee70003, + 0x0000000c, 0x21420002, + 0x0000000c, 0x73e7001d, + 0x00000018, 0x8000001b, + 0x00000010, 0xb7ee0a06, + 0x00000010, 0xb96f0815, + 0x00000003, 0xb76e0800, + 0x00000004, 0xb7ef0a00, + 0x00000018, 0x80000201, + 0x00000018, 0x80000015, + 0x00000018, 0x80000005, + 0x0000000c, 0x33e7001a, + 0x00000000, 0x37040000, + 0x00000000, 0x37850000, + 0x00000018, 0x80000010, + 0x00000000, 0x06020000, + 0x0000000c, 0x73e7001d, + 0x00000010, 0x0ce70003, + 0x00000000, 0x056d0000, + 0x00000018, 0x800001e6, + 0x0000000c, 0x73e7001a, + 0x00000000, 0x37ed0000, + 0x00000000, 0x056d0000, + 0x00000003, 0xb8f11400, + 0x00000018, 0x800001f1, + 0x00000018, 0x000c0000, + 0x00000000, 0x02840000, + 0x0000000c, 0x21420001, + 0x0000000c, 0x61420000, + 0x00000000, 0x25020000, + 0x00000000, 0x286d0000, + 0x0000000f, 0x65ed0010, + 0x00000009, 0x266dffff, + 0x00000000, 0x23000000, + 0x00000010, 0xb1840a44, + 0x00000010, 0x01420002, + 0x00000004, 0xb8f10a00, + 0x00000003, 0x83790a00, + 0x00000010, 0xb8040c40, + 0x00000010, 0xb7e6080a, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0c68ffff, + 0x00000009, 0x0b67ffff, + 0x00000000, 0x0be60000, + 0x00000000, 0x0c840000, + 0x00000010, 0xb197320c, + 0x00000008, 0x0f800002, + 0x00000018, 0x8000000a, + 0x00000000, 0x0a6a0000, + 0x00000000, 0x0aeb0000, + 0x00000000, 0x0c000000, + 0x00000009, 0x0b6cffff, + 0x00000000, 0x0be90000, + 0x00000000, 0x0c840000, + 0x00000010, 0xb1973203, + 0x00000008, 0x0f800002, + 0x00000000, 0x00000000, + 0x00000010, 0x001f0000, + 0x00000000, 0x0c860000, + 0x00000000, 0x06980000, + 0x00000018, 0x8000ff24, + 0x00000008, 0x0f800003, + 0x0000000f, 0x63ef0010, + 0x00000000, 0x246f0000, + 0x00000010, 0x009f0000, + 0x00000010, 0xb1973213, + 0x00000018, 0x8000ff1e, + 0x00000000, 0x231b0000, + 0x00000000, 0x28840000, + 0x00000000, 0x02043600, + 0x00000003, 0x8384a000, + 0x0000000f, 0x65870010, + 0x00000009, 0x2607ffff, + 0x00000000, 0x27111a00, + 0x00000000, 0x66900000, + 0x0000000c, 0x29520000, + 0x00000000, 0x24c60000, + 0x0000000c, 0x29800000, + 0x00000000, 0x06980000, + 0x00000010, 0x20530000, + 0x00000000, 0x22c58c00, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800003, + 0x00000018, 0x8000ffed, + 0x00000000, 0x02043600, + 0x00000000, 0x231b0000, + 0x00000000, 0x03840000, + 0x00000010, 0x91870a03, + 0x00000000, 0x03d00000, + 0x0000000c, 0x21420001, + 0x00000003, 0x8387a000, + 0x0000000f, 0x65870010, + 0x00000009, 0x2607ffff, + 0x00000000, 0x27111a00, + 0x00000000, 0x66900000, + 0x0000000c, 0x29520000, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000005, 0x73e72c00, + 0x00000005, 0x74683000, + 0x00000000, 0x33170000, + 0x00000018, 0x800000b9, + 0x00000010, 0x91c60006, + 0x00000008, 0x07000004, + 0x00000010, 0xb1c41c04, + 0x00000010, 0x21c20003, + 0x00000010, 0x91840a10, + 0x00000000, 0x28840000, + 0x00000010, 0x01c20009, + 0x00000000, 0x05580000, + 0x00000000, 0x2c400000, + 0x00000008, 0x2c8000c4, + 0x00000008, 0x2d00001c, + 0x00000008, 0x2d800020, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x2c0a0000, + 0x00000000, 0x24c60000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x0000000c, 0x61420003, + 0x00000000, 0x22c58c00, + 0x00000010, 0xb1840a29, + 0x0000000c, 0x21420006, + 0x00000010, 0x0ce70020, + 0x0000000f, 0x43680010, + 0x00000000, 0x03f30c00, + 0x00000003, 0xb9720800, + 0x00000010, 0x91870820, + 0x0000000f, 0x46ec0010, + 0x00000010, 0xb68d0c1e, + 0x00000000, 0x838d0c00, + 0x0000000f, 0x63ef0010, + 0x00000000, 0x246f0000, + 0x00000000, 0xa3050800, + 0x00000001, 0xa3460e00, + 0x00000000, 0x28840000, + 0x00000000, 0x02048c00, + 0x00000008, 0x22000008, + 0x00000000, 0x03840000, + 0x00000010, 0x91870a03, + 0x00000000, 0x03d00000, + 0x0000000c, 0x21420001, + 0x00000003, 0x8387a000, + 0x0000000f, 0x65870010, + 0x00000009, 0x2607ffff, + 0x00000000, 0x27750c00, + 0x00000000, 0x66f40000, + 0x0000000c, 0x29000000, + 0x00000000, 0x24c60000, + 0x0000000c, 0x29800000, + 0x00000000, 0x03068c00, + 0x00000003, 0xf4680c00, + 0x00000010, 0x20530000, + 0x00000000, 0x22c58c00, + 0x00000018, 0x8000ffdf, + 0x00000000, 0x39040000, + 0x0000000c, 0x33e70019, + 0x00000008, 0x22000006, + 0x00000018, 0x80000119, + 0x0000000f, 0x65680010, + 0x00000008, 0x22000007, + 0x00000018, 0x80000116, + 0x00000010, 0x0ce70005, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d000070, + 0x00000008, 0x2d800010, + 0x00000000, 0x00000000, + 0x00000010, 0x205f0000, + 0x00000018, 0x80000100, + 0x00000018, 0x8000000d, + 0x00000018, 0x8000fe89, + 0x00000000, 0x06800400, + 0x00000018, 0x8000000a, + 0x00000000, 0x05440000, + 0x00000003, 0xc50aa400, + 0x00000008, 0x22000012, + 0x00000008, 0x29000000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000009, 0x220affff, + 0x0000000f, 0x690a0010, + 0x00000018, 0x000d0000, + 0x00000000, 0x05020000, + 0x00000000, 0x2c400000, + 0x00000008, 0x2c8000b8, + 0x00000008, 0x2d000010, + 0x00000008, 0x2d800048, + 0x00000010, 0x0ce20006, + 0x00000010, 0x205f0000, + 0x0000000c, 0x71620019, + 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800001, + 0x00000018, 0x000a0000, + 0x00000000, 0x2a000000, + 0x00000018, 0x800000e5, + 0x00000008, 0x2c8000c4, + 0x00000008, 0x2d00001c, + 0x00000008, 0x2d800001, + 0x00000018, 0x8000fe6c, + 0x00000000, 0x02700000, + 0x00000000, 0x0d620000, + 0x00000000, 0xbc630800, + 0x00000000, 0x2a000000, + 0x00000000, 0x0f400000, + 0x0000000c, 0x73e7001b, + 0x00000010, 0x0ce7000c, + 0x00000000, 0x286d0000, + 0x0000000f, 0x65ed0010, + 0x00000009, 0x266dffff, + 0x00000018, 0x8000004b, + 0x00000008, 0x02000004, + 0x00000010, 0x91c40803, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000018, 0x800000d1, + 0x00000018, 0x8000ffde, + 0x00000018, 0x80000005, + 0x00000008, 0x2c8000c4, + 0x00000008, 0x2d00001c, + 0x00000008, 0x2d800001, + 0x00000000, 0x00000000, + 0x00000010, 0x205f0000, + 0x00000008, 0x2c800048, + 0x00000008, 0x2d000064, + 0x00000008, 0x2d800104, + 0x00000000, 0x27f80000, + 0x00000010, 0x91de0000, + 0x00000010, 0xb8799e03, + 0x00000008, 0x2200000d, + 0x0000000c, 0x29800000, + 0x00000018, 0x8000fe4c, + 0x00000000, 0x02700000, + 0x00000000, 0x0d620000, + 0x00000000, 0xbc630800, + 0x00000000, 0x2a000000, + 0x00000010, 0x2ce70030, + 0x00000010, 0x2d67002f, + 0x00000000, 0x286d0000, + 0x0000000f, 0x65ed0010, + 0x00000009, 0x266dffff, + 0x00000000, 0x0f400000, + 0x00000008, 0x22000004, + 0x00000000, 0x28e90000, + 0x00000008, 0x2500dead, + 0x00000010, 0xb1f8a227, + 0x0000000c, 0x29800000, + 0x00000000, 0x0a6a0000, + 0x00000000, 0x0aeb0000, + 0x00000009, 0x0b6cffff, + 0x00000000, 0x0c000000, + 0x00000000, 0x0be90000, + 0x00000000, 0x0ce90000, + 0x0000000c, 0x09800002, + 0x00000008, 0x0f800004, + 0x00000000, 0x00000000, + 0x00000010, 0x009f0000, + 0x00000000, 0x83973200, + 0x00000000, 0x38700e00, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000005, 0x73e72c00, + 0x00000005, 0x74680000, + 0x00000000, 0x35140000, + 0x00000000, 0x35950000, + 0x00000005, 0x766c2c00, + 0x00000018, 0x8000ffac, + 0x00000018, 0x8000fe28, + 0x00000000, 0x02700000, + 0x00000000, 0x0d620000, + 0x00000000, 0xbc630800, + 0x00000000, 0x2a000000, + 0x00000000, 0x286d0000, + 0x0000000f, 0x65ed0010, + 0x00000009, 0x266dffff, + 0x00000000, 0x0f400000, + 0x00000010, 0x0e670008, + 0x0000000c, 0x73e7001c, + 0x00000004, 0xb8f1a000, + 0x00000018, 0x80000006, + 0x00000008, 0x02000004, + 0x00000010, 0x91c40802, + 0x0000000c, 0x29800000, + 0x00000018, 0x8000ff9b, + 0x00000018, 0x8000fe17, + 0x00000000, 0x06820000, + 0x00000010, 0x001f0000, + 0x00000010, 0x0ce70031, + 0x00000000, 0x03720000, + 0x00000000, 0x0cf80000, + 0x00000003, 0x8ced3200, + 0x00000000, 0xa8190c00, + 0x00000010, 0xb872322c, + 0x00000000, 0x03ca0000, + 0x0000000f, 0x65680010, + 0x00000000, 0x0bcf0000, + 0x00000000, 0x27f20000, + 0x00000000, 0x28ed0000, + 0x00000004, 0xb9723200, + 0x00000010, 0x0d670004, + 0x00000000, 0x056d0000, + 0x00000010, 0x91f21402, + 0x00000000, 0x396e0000, + 0x00000000, 0x03720000, + 0x00000003, 0xbcf80c00, + 0x00000000, 0x03440000, + 0x00000008, 0x22000010, + 0x00000010, 0xb7ef3204, + 0x0000000c, 0x21420004, + 0x0000000c, 0x73e70019, + 0x00000000, 0x3cf80000, + 0x00000000, 0x07520000, + 0x00000000, 0x29000000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000000, 0x22060000, + 0x0000000c, 0x61420004, + 0x00000000, 0x25070000, + 0x00000000, 0x27970000, + 0x00000000, 0x28940000, + 0x00000000, 0x290e0000, + 0x00000010, 0x0ce7000f, + 0x00000010, 0xb873320e, + 0x0000000f, 0x436c0010, + 0x00000000, 0x03f30000, + 0x00000000, 0x83990e00, + 0x00000001, 0x83860e00, + 0x00000000, 0x83060e00, + 0x00000003, 0xf66c0c00, + 0x00000000, 0x39f30e00, + 0x00000000, 0x3af50e00, + 0x00000000, 0x7a740000, + 0x0000000f, 0x43680010, + 0x00000001, 0x83860e00, + 0x00000000, 0x83060e00, + 0x00000003, 0xf4680c00, + 0x00000000, 0x286d0000, + 0x0000000f, 0x63ef0010, + 0x00000000, 0x246f0000, + 0x00000010, 0xb1e9a054, + 0x00000000, 0x03690000, + 0x00000010, 0xb1f80c52, + 0x00000000, 0x0a6a0000, + 0x00000000, 0x0aeb0000, + 0x00000009, 0x0b6cffff, + 0x00000000, 0x0c000000, + 0x00000000, 0x0be90000, + 0x00000003, 0x8cf8a000, + 0x0000000c, 0x09800002, + 0x00000010, 0x009f0000, + 0x00000010, 0xb817320a, + 0x00000000, 0x35140000, + 0x00000000, 0x35950000, + 0x00000005, 0x766c2c00, + 0x00000000, 0x34970000, + 0x00000004, 0xb8f12e00, + 0x00000010, 0x001f0000, + 0x00000018, 0x8000fdfa, + 0x00000008, 0x0f800004, + 0x00000018, 0x8000fff6, + 0x00000000, 0x03e90000, + 0x00000010, 0xb8f8a017, + 0x00000010, 0x20130016, + 0x00000010, 0xb1f10e15, + 0x00000000, 0x83973200, + 0x00000000, 0x38700e00, + 0x00000000, 0xbc780e00, + 0x00000000, 0x3cf80000, + 0x00000000, 0x37d00000, + 0x0000000c, 0x73e7001a, + 0x00000003, 0xb8f1a000, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000005, 0x73e72c00, + 0x00000000, 0x33190000, + 0x00000005, 0x74680000, + 0x00000010, 0x0ce70009, + 0x00000000, 0x07520000, + 0x00000000, 0x396d0000, + 0x00000010, 0x0ce70003, + 0x00000000, 0x056d0000, + 0x00000018, 0x8000007a, + 0x00000000, 0x290e0000, + 0x00000018, 0x80000002, + 0x00000010, 0x91973206, + 0x00000000, 0x35140000, + 0x00000000, 0x35950000, + 0x00000005, 0x766c2c00, + 0x00000000, 0x34990000, + 0x00000004, 0xb8f13200, + 0x00000000, 0x83690c00, + 0x00000010, 0xb1860013, + 0x00000000, 0x28e90000, + 0x00000008, 0x22000004, + 0x00000008, 0x25002345, + 0x00000000, 0x03690000, + 0x00000010, 0xb8660c07, + 0x00000009, 0x036cffff, + 0x00000000, 0x326a0000, + 0x00000000, 0x32eb0000, + 0x00000005, 0x73e70c00, + 0x00000000, 0x33690000, + 0x00000005, 0x74680000, + 0x0000000c, 0x73e7001c, + 0x00000000, 0x03690000, + 0x00000010, 0xb1f80c12, + 0x00000010, 0xb1d00c11, + 0x0000000c, 0x21420005, + 0x0000000c, 0x33e7001c, + 0x00000018, 0x8000000e, + 0x00000010, 0x2e67000d, + 0x00000000, 0x03690000, + 0x00000010, 0xb1f80c0b, + 0x00000010, 0xb1d00c0a, + 0x00000000, 0x03440000, + 0x00000008, 0x2200000c, + 0x00000000, 0x07520000, + 0x00000000, 0x29000000, + 0x0000000c, 0x29800000, + 0x0000000c, 0x33e7001c, + 0x00000010, 0x20530000, + 0x00000000, 0x22060000, + 0x00000000, 0x290e0000, + 0x00000018, 0x000d0000, + 0x00000000, 0x06820000, + 0x00000010, 0x2de7000d, + 0x00000010, 0x0ce7000c, + 0x00000000, 0x27f20000, + 0x00000010, 0xb96d9e0a, + 0x00000000, 0xa86d9e00, + 0x00000018, 0x8000fd82, + 0x00000010, 0xb7501407, + 0x00000008, 0x2200000f, + 0x0000000f, 0x65680010, + 0x00000000, 0x29000000, + 0x0000000c, 0x29800000, + 0x0000000c, 0x33e7001b, + 0x00000010, 0x20530000, + 0x00000018, 0x000d0000, + 0x00000000, 0x39840000, + 0x00000000, 0x28f30000, + 0x00000000, 0x031e0000, + 0x00000009, 0x076000ff, + 0x00000010, 0x001f0000, + 0x0000000f, 0x0f0e0007, + 0x00000000, 0x83850800, + 0x00000000, 0x0a7d0000, + 0x00000000, 0x0afe0000, + 0x00000000, 0x0b7f0000, + 0x00000000, 0x0d7a0000, + 0x00000000, 0x0c000000, + 0x00000000, 0x0bfc0000, + 0x00000000, 0x0c970e00, + 0x00000018, 0x8000fda7, + 0x00000008, 0x0f800003, + 0x0000000f, 0x47670010, + 0x00000008, 0x070e0001, + 0x0000000b, 0xc50000ff, + 0x00000002, 0x450a0000, + 0x00000001, 0x33e71400, + 0x0000000f, 0x050e0010, + 0x00000002, 0x33e71400, + 0x00000010, 0x009f0000, + 0x00000000, 0x02043600, + 0x00000000, 0x231b0000, + 0x00000000, 0x23ff0000, + 0x00000000, 0x241b0000, + 0x00000000, 0x03840000, + 0x00000010, 0x91870a03, + 0x00000000, 0x03d00000, + 0x0000000c, 0x21420001, + 0x00000003, 0x8387a000, + 0x0000000f, 0x65870010, + 0x00000009, 0x2607ffff, + 0x00000000, 0x27110000, + 0x00000000, 0x26900000, + 0x0000000c, 0x29000000, + 0x0000000f, 0x64e70010, + 0x00000009, 0x24c900ff, + 0x0000000c, 0x29800000, + 0x00000003, 0xf4683600, + 0x00000000, 0x3a100000, + 0x00000000, 0x3a910000, + 0x00000003, 0xf66c2400, + 0x00000010, 0xb1923605, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800004, + 0x00000000, 0x00000000, + 0x00000010, 0x009f0000, + 0x00000000, 0x3e170000, + 0x00000000, 0x3e940000, + 0x00000000, 0x3f150000, + 0x00000000, 0x3f960000, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f060000, + 0x00000010, 0x20530000, + 0x00000000, 0x22c53600, + 0x00000018, 0x8000fe88, + 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f008000, + 0x00000008, 0x0f800007, + 0x00000018, 0x8000001b, + 0x00000000, 0x280a0000, + 0x00000000, 0x05020000, + 0x00000008, 0x22000009, + 0x00000000, 0x29000000, + 0x0000000f, 0x65680010, + 0x00000000, 0x248a0000, + 0x00000003, 0xf66c9400, + 0x00000010, 0xb972a004, + 0x0000000c, 0x73e70019, + 0x0000000c, 0x21420004, + 0x00000000, 0x3cf80000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000008, 0x22000008, + 0x0000000c, 0x61420004, + 0x00000018, 0x000a0000, + 0x00000000, 0x05020000, + 0x0000000c, 0x61420000, + 0x00000010, 0x01420003, + 0x0000000c, 0x33e7001d, + 0x0000000c, 0x61420002, + 0x00000018, 0x000a0000, + 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, + 0x0000000f, 0x0f470007, + 0x00000008, 0x0f800008, + 0x0000000c, 0x29800000, + 0x00000010, 0x009f0000, + 0x00000018, 0x8000fd20, + 0x00000000, 0x33510000, + 0x00000000, 0x2a000000, + 0x00000010, 0xb1c60023, + 0x0000000f, 0x0f500007, + 0x00000000, 0x0a600000, + 0x00000000, 0x0ae10000, + 0x0000000f, 0x4b620008, + 0x00000009, 0x0b1600ff, + 0x0000000f, 0x4c620010, + 0x00000000, 0x0d620000, + 0x00000009, 0x0d1a00ff, + 0x00000010, 0x07500003, + 0x0000000c, 0x0d1a0008, + 0x0000000c, 0x0b160008, + 0x00000000, 0x0cc60000, + 0x00000000, 0x0b800000, + 0x00000000, 0x06980000, + 0x00000008, 0x0f800003, + 0x00000010, 0x06c20004, + 0x0000000c, 0x29000002, + 0x00000010, 0x26420002, + 0x0000000c, 0x29520003, + 0x00000008, 0x22000001, + 0x00000010, 0x009f0000, + 0x00000000, 0x231b0000, + 0x00000000, 0x27111a00, + 0x00000000, 0x66900000, + 0x0000000c, 0x29520000, + 0x00000010, 0xb1973209, + 0x0000000c, 0x29800000, + 0x00000000, 0x06980000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520003, + 0x00000000, 0x22c58c00, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800003, + 0x00000018, 0x8000fff3, + 0x00000010, 0xb1c80013, + 0x00000010, 0xb1c60003, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520000, + 0x0000000c, 0x29520003, + 0x00000010, 0x06c20002, + 0x0000000c, 0x29520002, + 0x00000000, 0x22c58c00, + 0x00000000, 0x27650000, + 0x00000000, 0x26e40000, + 0x00000008, 0x22000016, + 0x00000010, 0xb1c60003, + 0x00000000, 0x23480000, + 0x00000010, 0xb1800005, + 0x00000000, 0x23480000, + 0x0000000c, 0x29800000, + 0x0000000f, 0x0f500007, + 0x00000018, 0x80000012, + 0x00000008, 0x22000016, + 0x0000000c, 0x29800000, + 0x00000000, 0x30140000, + 0x00000000, 0x30950000, + 0x00000010, 0x07500003, + 0x00000009, 0x0b1600ff, + 0x00000009, 0x0d1a00ff, + 0x0000000f, 0x31160008, + 0x00000000, 0x31623400, + 0x00000003, 0xf1623000, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c510000, + 0x00000009, 0x2cd1007f, + 0x00000008, 0x2cd90000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d80000c, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000010, 0x05c20004, + 0x00000008, 0x0f800007, + 0x00000000, 0x33000000, + 0x00000010, 0x009f0000, + 0x00000018, 0x8000fcd1, + 0x00000000, 0x2a000000, + 0x0000000f, 0x0f500007, + 0x00000010, 0xb1c6002d, + 0x0000000f, 0x47420008, + 0x00000009, 0x070e000f, + 0x00000008, 0x070e0008, + 0x00000010, 0x001f0000, + 0x00000008, 0x09000001, + 0x00000007, 0x09121c00, + 0x00000003, 0xcbca9200, + 0x00000000, 0x0b97a200, + 0x00000007, 0x42171c00, + 0x00000000, 0x0b040000, + 0x0000000f, 0x0a840003, + 0x00000000, 0x0a959c00, + 0x00000000, 0x4a009a00, + 0x00000008, 0x82120001, + 0x00000001, 0x0c170800, + 0x00000000, 0x0c978c00, + 0x00000000, 0x02180000, + 0x00000008, 0x0d00ffff, + 0x00000008, 0x0f800006, + 0x0000000c, 0x29000000, + 0x00000010, 0x06c20004, + 0x0000000c, 0x29520002, + 0x00000010, 0x26420002, + 0x0000000c, 0x29520003, + 0x00000008, 0x22000001, + 0x00000010, 0x009f0000, + 0x00000010, 0xb197320c, + 0x00000000, 0x231b0000, + 0x00000000, 0x27110800, + 0x00000000, 0x66900000, + 0x0000000c, 0x29800000, + 0x00000000, 0x02180000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520003, + 0x00000000, 0x22c53600, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800006, + 0x00000018, 0x8000fff4, + 0x00000000, 0x231b0000, + 0x00000000, 0x27110800, + 0x00000000, 0x66900000, + 0x00000010, 0xb1c8000b, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520000, + 0x0000000c, 0x29520003, + 0x00000010, 0x06c20002, + 0x0000000c, 0x29520002, + 0x00000000, 0x22c58c00, + 0x00000000, 0x27650000, + 0x00000000, 0x26e40000, + 0x00000000, 0x23480000, + 0x00000008, 0x22000017, + 0x0000000c, 0x29800000, + 0x00000010, 0x001f0000, + 0x00000018, 0x8000fc96, +}; +/* Calling this macro prior to loading will change value of MAX_BD_PAGE (default = 0xff)*/ +#define RV2P_PROC2_MAX_BD_PAGE_LOC 5 +#define RV2P_PROC2_CHG_MAX_BD_PAGE(value) {\ + rv2p_proc2[RV2P_PROC2_MAX_BD_PAGE_LOC] = (rv2p_proc2[RV2P_PROC2_MAX_BD_PAGE_LOC] & ~0xFFFF) | (value);\ +} + +/* Calling this macro prior to loading will change value of GEN_IND_SIZE (default = 0x1)*/ +#define RV2P_PROC2_GEN_IND_SIZE_LOC 9 +#define RV2P_PROC2_CHG_GEN_IND_SIZE(value) {\ + rv2p_proc2[RV2P_PROC2_GEN_IND_SIZE_LOC] = (rv2p_proc2[RV2P_PROC2_GEN_IND_SIZE_LOC] & ~0xFFFF) | (value);\ +} + +#endif /* __rv2p_proc2.h__ */ + diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/rxpfw.h b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/rxpfw.h new file mode 100644 index 0000000000..27532be322 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/rxpfw.h @@ -0,0 +1,1970 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* 4.0.4 */ +#include "bcmtype.h" +int RXP_b06FwReleaseMajor = 0x1; +int RXP_b06FwReleaseMinor = 0x0; +int RXP_b06FwReleaseFix = 0x0; +u32_t RXP_b06FwStartAddr = 0x08003210; +u32_t RXP_b06FwTextAddr = 0x08000000; +int RXP_b06FwTextLen = 0x7874; +u32_t RXP_b06FwDataAddr = 0x00000000; +int RXP_b06FwDataLen = 0x0; +u32_t RXP_b06FwRodataAddr = 0x08007874; +int RXP_b06FwRodataLen = 0x24; +u32_t RXP_b06FwBssAddr = 0x08007918; +int RXP_b06FwBssLen = 0x478; +u32_t RXP_b06FwSbssAddr = 0x080078c0; +int RXP_b06FwSbssLen = 0x54; +u32_t RXP_b06FwSDataAddr = 0x00000000; +int RXP_b06FwSDataLen = 0x0; +u32_t RXP_b06FwText[(0x7874/4) + 1] = { +0xa000c84, +0x0, 0x0, 0xd, 0x72787036, +0x2e322e33, 0x0, 0x6020303, 0x0, +0x1, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 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0xa001cb4, +0x30c60001, 0x2402021, 0xa001cb3, 0x24050001, +0x2402021, 0x2821, 0x24060001, 0xe0017a7, +0x0, 0x97820042, 0x1440fd04, 0x8f84001c, +0x8e430020, 0x30620004, 0x10400012, 0x8f840044, +0x2402fffb, 0x621024, 0xae420020, 0x27430180, +0x8f4201b8, 0x440fffe, 0x8f820050, 0xac620000, +0x8f420124, 0xac620004, 0x24026083, 0xa4620008, +0x24020002, 0xa062000b, 0x3c021000, 0xaf4201b8, +0x8f840044, 0x8f83001c, 0x8fbf0034, 0x8fb60030, +0x8fb5002c, 0x8fb40028, 0x8fb30024, 0x8fb20020, +0x8fb1001c, 0x8fb00018, 0x24020001, 0x27bd0038, +0x3e00008, 0xac6400c0, 0x30a500ff, 0x24030001, +0x24a90001, 0x69102b, 0x1040000c, 0x4021, +0x240a0001, 0xa31023, 0x4a3804, 0x24630001, +0x30820001, 0x69302b, 0x10400002, 0x42042, +0x1074025, 0x54c0fff8, 0xa31023, 0x3e00008, +0x1001021, 0x3c020800, 0x24426628, 0x3c010800, +0xac227950, 0x3c020800, 0x2442588c, 0x3c010800, +0xac227954, 0x24020006, 0x27bdffe0, 0x3c010800, +0xa0227958, 0x3c021edc, 0xafb20018, 0xafb10014, +0xafbf001c, 0xafb00010, 0x34526f41, 0x8821, +0x24050008, 0xe001cdb, 0x2202021, 0x118080, +0x3c070800, 0x24e7795c, 0x21600, 0x2071821, +0xac620000, 0x2821, 0x24a20001, 0x3045ffff, +0x8c620000, 0x2ca60008, 0x4410002, 0x22040, +0x922026, 0x14c0fff8, 0xac640000, 0x2078021, +0x8e040000, 0xe001cdb, 0x24050020, 0x26230001, +0x3071ffff, 0x2e230100, 0x1460ffe5, 0xae020000, +0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, +0x3e00008, 0x27bd0020, 0x27bdffd8, 0xafb3001c, +0xafb20018, 0xafbf0020, 0xafb10014, 0xafb00010, +0x8f510140, 0x8f480148, 0x89402, 0x324300ff, +0x311300ff, 0x8f4201b8, 0x440fffe, 0x27500180, +0xae110000, 0x8f420144, 0xae020004, 0x24020002, +0xa6120008, 0xa202000b, 0x24020014, 0xae130024, +0x10620025, 0x28620015, 0x10400008, 0x24020015, +0x24020010, 0x10620030, 0x24020012, 0x10620009, +0x8fbf0020, 0xa001e16, 0x8fb3001c, 0x10620070, +0x24020022, 0x10620037, 0x8fbf0020, 0xa001e16, +0x8fb3001c, 0x3c020800, 0x8c4231a0, 0x2403ff80, +0x2221021, 0x431024, 0xaf420024, 0x3c020800, +0x8c4231a0, 0x2221021, 0x3042007f, 0x3421821, +0x3c02000a, 0x621821, 0x166000bc, 0xaf83001c, +0x90620062, 0x3042000f, 0x34420030, 0xa0620062, +0xa001e15, 0x8fbf0020, 0x3c046000, 0x8c832c08, +0x3c02f003, 0x3442ffff, 0x621824, 0xac832c08, +0x3c020800, 0x8c4231a0, 0x8c832c08, 0x24420074, +0x21082, 0x21480, 0x621825, 0xac832c08, +0xa001e15, 0x8fbf0020, 0x3c020800, 0x8c4231a0, +0x2403ff80, 0x2221021, 0x431024, 0xaf420024, +0x3c020800, 0x8c4231a0, 0x3c03000a, 0x2221021, +0x3042007f, 0x3421021, 0x431021, 0xa001e14, +0xaf82001c, 0x3c020800, 0x8c4231a0, 0x2405ff80, +0x2221021, 0x451024, 0xaf420024, 0x3c020800, +0x8c4231a0, 0x2221021, 0x3042007f, 0x3421821, +0x3c02000a, 0x621821, 0x90620063, 0xa21024, +0x304200ff, 0x10400085, 0xaf83001c, 0x24620088, +0x94430012, 0x3c020800, 0x8c4231a8, 0x30633fff, +0x31980, 0x2221021, 0x431021, 0x3043007f, +0x3432021, 0x451024, 0x3c03000c, 0x832021, +0xaf420028, 0x9082000d, 0xa21024, 0x304200ff, +0x10400072, 0xaf84002c, 0x9082000d, 0x30420010, +0x1440006f, 0x8fbf0020, 0xe001729, 0x0, +0x8f4201b8, 0x440fffe, 0x0, 0xae110000, +0x8f420144, 0xae020004, 0x24020002, 0xa6120008, +0xa202000b, 0xae130024, 0xa001e15, 0x8fbf0020, +0x2406ff80, 0x2261024, 0xaf420020, 0x3c020800, +0x8c4231a0, 0x31043fff, 0x42180, 0x2221021, +0x461024, 0xaf420024, 0x3c030800, 0x8c6331a8, +0x3c020800, 0x8c4231a0, 0x3227007f, 0x2231821, +0x2221021, 0x641821, 0x3042007f, 0x3064007f, +0x3422821, 0x3c02000a, 0x661824, 0xa22821, +0x3442021, 0x3c02000c, 0x822021, 0xaf430028, +0x3c020008, 0x3471821, 0x629021, 0xaf85001c, +0xaf84002c, 0xe001729, 0x1008021, 0x8f4201b8, +0x440fffe, 0x8f82002c, 0x8f84001c, 0x27450180, +0x9042000d, 0xacb10000, 0xa4b00006, 0x21600, +0x21603, 0x21027, 0x237c2, 0x14c00016, +0x24820088, 0x94420012, 0x32033fff, 0x30423fff, +0x14430012, 0x24026082, 0x90830063, 0x2402ff80, +0x431024, 0x304200ff, 0x5040000c, 0x24026082, +0x90820062, 0x3042000f, 0x34420040, 0xa0820062, +0x24026084, 0xa4a20008, 0x2402000d, 0xa0a20005, +0xa001dff, 0x3c022700, 0x24026082, 0xa4a20008, +0xa0a00005, 0x3c022700, 0x61c00, 0x621825, +0x24020002, 0xa0a2000b, 0xaca30010, 0xaca00014, +0xaca00024, 0xaca00028, 0xaca0002c, 0x8e42004c, +0x8f84002c, 0xaca20018, 0x9083000d, 0x2402ff80, +0x431024, 0x304200ff, 0x10400005, 0x8fbf0020, +0x9082000d, 0x3042007f, 0xa082000d, 0x8fbf0020, +0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, +0x3c021000, 0x27bd0028, 0x3e00008, 0xaf4201b8, +0x0 }; +u32_t RXP_b06FwData[(0x0/4) + 1] = { 0x0 }; +u32_t RXP_b06FwRodata[(0x24/4) + 1] = { +0x8004c74, 0x8004b74, 0x8004c24, +0x8004c3c, 0x8004c54, 0x8004c6c, 0x8004c9c, +0x8004c9c, 0x8004b7c, 0x0 }; +u32_t RXP_b06FwBss[(0x478/4) + 1] = { 0x0 }; +u32_t RXP_b06FwSbss[(0x54/4) + 1] = { 0x0 }; +u32_t RXP_b06FwSdata[(0x0/4) + 1] = { 0x0 }; diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/tpatfw.h b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/tpatfw.h new file mode 100644 index 0000000000..0d6bd3ca1d --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/tpatfw.h @@ -0,0 +1,421 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* 4.0.4 */ +#include "bcmtype.h" +int TPAT_b06FwReleaseMajor = 0x1; +int TPAT_b06FwReleaseMinor = 0x0; +int TPAT_b06FwReleaseFix = 0x0; +u32_t TPAT_b06FwStartAddr = 0x08000490; +u32_t TPAT_b06FwTextAddr = 0x08000400; +int TPAT_b06FwTextLen = 0x17d4; +u32_t TPAT_b06FwDataAddr = 0x00000000; +int TPAT_b06FwDataLen = 0x0; +u32_t TPAT_b06FwRodataAddr = 0x00000000; +int TPAT_b06FwRodataLen = 0x0; +u32_t TPAT_b06FwBssAddr = 0x08001c44; +int TPAT_b06FwBssLen = 0x450; +u32_t TPAT_b06FwSbssAddr = 0x08001c00; +int TPAT_b06FwSbssLen = 0x44; +u32_t TPAT_b06FwSDataAddr = 0x00000000; +int TPAT_b06FwSDataLen = 0x0; +u32_t TPAT_b06FwText[(0x17d4/4) + 1] = { +0xa000124, +0x0, 0x0, 0xd, 0x74706136, +0x2e322e33, 0x0, 0x6020301, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x10000003, 0x0, 0xd, 0xd, +0x3c020800, 0x24421c00, 0x3c030800, 0x24632094, +0xac400000, 0x43202b, 0x1480fffd, 0x24420004, +0x3c1d0800, 0x37bd2ffc, 0x3a0f021, 0x3c100800, +0x26100490, 0x3c1c0800, 0x279c1c00, 0xe00015c, +0x0, 0xd, 0x3084ffff, 0x30820007, +0x8f850018, 0x10400002, 0x24830007, 0x3064fff8, +0x853021, 0x30c41fff, 0x3441821, 0x247b4000, +0xaf85001c, 0xaf840018, 0x3e00008, 0xaf440084, +0x3084ffff, 0x30820007, 0x8f850020, 0x8f860028, +0x10400002, 0x24830007, 0x3064fff8, 0x852021, +0x86182b, 0x14600002, 0xaf850024, 0x862023, +0x3442821, 0x34068000, 0xaf840020, 0xaf440080, +0xa62021, 0x3e00008, 0xaf840038, 0x27bdffd8, +0xafb3001c, 0xafb20018, 0xafb00010, 0xafbf0024, +0xafb40020, 0xafb10014, 0x3c086008, 0x8d145000, +0x2418ff7f, 0x3c1a8000, 0x2989824, 0x3672380c, +0xad125000, 0x8f510008, 0x3c07601c, 0x3c086000, +0x36300001, 0xaf500008, 0xaf800018, 0xaf400080, +0xaf400084, 0x8ce60008, 0x8d0f0808, 0x3c076016, +0x8cec0000, 0x31eefff0, 0x39ca0010, 0x3c0dffff, +0x340b8000, 0x3c030080, 0x34b4821, 0x2d440001, +0x18d2824, 0x3c025353, 0x3c010800, 0xac230420, +0xaf890038, 0xaf860028, 0xaf840010, 0x275b4000, +0x14a20003, 0x34e37c00, 0x8cf90004, 0x3281821, +0x8c7f007c, 0x8c650078, 0x3c028000, 0x3c0b0800, +0x8d6b048c, 0x3c0a0800, 0x8d4a0488, 0x34520070, +0xaf85003c, 0xaf9f0040, 0x3c130800, 0x26731c44, +0x240a021, 0x8e480000, 0x8f460000, 0x38c30001, +0x30640001, 0x10800017, 0xaf880034, 0x2804821, +0x8d2f0000, 0x3c050800, 0x8ca5045c, 0x3c180800, +0x8f180458, 0x1e81023, 0xa28021, 0xc821, +0x202402b, 0x3198821, 0x2283821, 0x3c010800, +0xac30045c, 0x3c010800, 0xac270458, 0x8f4e0000, +0x39cd0001, 0x31ac0001, 0x1580ffed, 0x1e04021, +0xaf8f0034, 0x8e510000, 0x3c070800, 0x8ce7045c, +0x3c0d0800, 0x8dad0458, 0x2288023, 0xf06021, +0x7021, 0x190302b, 0x1ae1821, 0x662021, +0x3c010800, 0xac2c045c, 0x3c010800, 0xac240458, +0x8f460108, 0x8f470100, 0x30c92000, 0xaf860000, +0xaf87000c, 0x1120000a, 0xc04021, 0x3c180800, +0x8f18042c, 0x27080001, 0x3c010800, 0xac28042c, +0x3c184000, 0xaf580138, 0xa000196, 0x0, +0x97490104, 0x2821, 0x1455021, 0x3122ffff, +0x1625821, 0x162f82b, 0x15f5021, 0x30d90200, +0x3c010800, 0xac2b048c, 0x3c010800, 0xac2a0488, +0x17200015, 0x24040f00, 0x10e40013, 0x0, +0x24080d00, 0x10e8023b, 0x30cd0006, 0x11a0ffe9, +0x3c184000, 0x936e0000, 0x24090010, 0x31c400f0, +0x10890271, 0x24020070, 0x108202e5, 0x8f880014, +0x250f0001, 0xaf8f0014, 0x3c184000, 0xaf580138, +0xa000196, 0x0, 0x974c0104, 0x1180ffd9, +0x3c184000, 0x30c34000, 0x146000a1, 0x0, +0x8f460178, 0x4c0fffe, 0x8f870038, 0x24100800, +0x240f0008, 0x8ce30008, 0xaf500178, 0xa74f0140, +0xa7400142, 0x974e0104, 0x8f860000, 0x31c9ffff, +0x30cd0001, 0x11a002e1, 0x1204021, 0x2531fffe, +0x24180002, 0xa7580146, 0x3228ffff, 0xa7510148, +0x3c190800, 0x8f39043c, 0x172002d0, 0x8f8c000c, +0x30df0020, 0x17e00002, 0x24040009, 0x24040001, +0x30c20c00, 0x24050400, 0x50450001, 0x34840004, +0xa744014a, 0x3c110800, 0x8e310420, 0x3c180048, +0x3c100001, 0x2381825, 0x30cf0002, 0x702825, +0x11e00004, 0x1821, 0x3c190100, 0xb92825, +0x24030001, 0x30df0004, 0x53e00005, 0xaf830008, +0x3c060010, 0xa62825, 0x24030001, 0xaf830008, +0xaf451000, 0x0, 0x0, 0x0, +0x0, 0x8f830008, 0x10600023, 0x0, +0x8f451000, 0x4a1fffe, 0x0, 0x1060001e, +0x0, 0x8f441000, 0x3c0c0020, 0x8c1024, +0x10400019, 0x8f8e0000, 0x31cd0002, 0x11a00016, +0x0, 0x974f1014, 0x15e00013, 0x0, +0x97591008, 0x3338ffff, 0x27110006, 0x111882, +0x33080, 0xc72821, 0x32300001, 0x32230003, +0x1200032c, 0x8ca20000, 0xd, 0xc7f821, +0xafe20000, 0x3c050800, 0x8ca50430, 0x24a60001, +0x3c010800, 0xac260430, 0x8f6d0000, 0x3402ffff, +0xaf8d0004, 0x8cec0000, 0x118202a6, 0x2021, +0x8ced0000, 0x31ac0100, 0x1180028a, 0x0, +0x3c020800, 0x8c420474, 0x3c030800, 0x8c63044c, +0x3c1f0800, 0x8fff0470, 0x3c180800, 0x8f180448, +0x483821, 0x688021, 0xe8282b, 0x3e43021, +0x208402b, 0x3048821, 0xc57021, 0x2287821, +0x3c010800, 0xac30044c, 0x3c010800, 0xac2f0448, +0x3c010800, 0xac270474, 0x3c010800, 0xac2e0470, +0x8f840018, 0x1203021, 0x31290007, 0x249f0008, +0x33f91fff, 0x3594021, 0xaf84001c, 0xaf990018, +0x251b4000, 0xaf590084, 0x11200003, 0x8f830020, +0x24c20007, 0x3046fff8, 0x8f840028, 0xc32821, +0xa4302b, 0x14c00002, 0xaf830024, 0xa42823, +0x3456021, 0x340d8000, 0x18d1021, 0x3c0f1000, +0xaf850020, 0xaf820038, 0xaf450080, 0xaf4f0178, +0x8f880014, 0x250f0001, 0xa0001ef, 0xaf8f0014, +0x8f620008, 0x8f670000, 0x24050030, 0x77602, +0x31c300f0, 0x106500a7, 0x240f0040, 0x546fff4c, +0x8f880014, 0x8f4b0178, 0x560fffe, 0x0, +0x30ca0200, 0x15400003, 0x61282, 0xd, +0x61282, 0x304d0003, 0xd4900, 0x12d1821, +0x38080, 0x20d4021, 0x86080, 0x1938021, +0x8e1f0000, 0x17e00002, 0x0, 0xd, +0x8f6e0004, 0x5c202bd, 0x92070006, 0x920e0005, +0x92020004, 0x3c090001, 0xe1880, 0x70f821, +0x8fed0018, 0x27710008, 0x24480005, 0x1a96021, +0x83082, 0xafec0018, 0x2202021, 0xe00059e, +0x26050014, 0x920a0006, 0x8f790004, 0x3c0b7fff, +0xa2080, 0x917821, 0x8df80004, 0x3566ffff, +0x3262824, 0x3053821, 0xade70004, 0x920e0005, +0x920d0004, 0x960c0008, 0xe1080, 0x51c821, +0x8f230000, 0x97490104, 0x3c07ffff, 0x675824, +0x3128ffff, 0x10df821, 0x3ec5023, 0x3144ffff, +0x1643025, 0xaf260000, 0x92030007, 0x24180001, +0x10780275, 0x240f0003, 0x106f0285, 0x0, +0x8e050010, 0x2419000a, 0xa7590140, 0xa7450142, +0x92180004, 0x8f860000, 0x240f0001, 0xa7580144, +0xa7400146, 0x97470104, 0x30d10002, 0x3c050041, +0xa7470148, 0x1821, 0xa74f014a, 0x12200003, +0x30cb0004, 0x3c050141, 0x24030001, 0x51600005, +0xaf830008, 0x3c060010, 0xa62825, 0x24030001, +0xaf830008, 0xaf451000, 0x0, 0x0, +0x0, 0x0, 0x8f8a0008, 0x11400004, +0x0, 0x8f441000, 0x481fffe, 0x0, +0x8f6b0000, 0x92080004, 0x3c110800, 0x8e310444, +0xaf8b0004, 0x97590104, 0x311800ff, 0x3c0e0800, +0x8dce0440, 0x3325ffff, 0x3053821, 0x2276021, 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0x27bd0030, 0x10a0ff70, 0x0, +0x24a5fffc, 0xa0005ec, 0x24090004, 0x8cd10000, +0xaf511018, 0x8f530178, 0x660ff7a, 0x2404000a, +0xa000601, 0x0, 0xa7c821, 0x8f880038, +0x8f4e101c, 0x19c082, 0x187880, 0x1e82021, +0xac8e0000, 0xe2c02, 0xc02021, 0xe0005b3, +0x31c6ffff, 0x23b2821, 0x8cad0000, 0x25400, +0x403021, 0xafad0010, 0x8fac0010, 0x318bffff, +0xafab0010, 0x8fa20010, 0x1424825, 0xafa90010, +0x8fa70010, 0xa000631, 0xaca70000, 0x8f8f0040, +0x148fffc9, 0x0, 0x97420104, 0x960b0002, +0x3c050800, 0x8ca5046c, 0x3049ffff, 0x316affff, +0x3c110800, 0x8e310468, 0x12a3821, 0x24f2fffe, +0xb24021, 0x12ffc3, 0x112c82b, 0x23fc021, +0x3192021, 0x3c010800, 0xac28046c, 0x3c010800, +0xac240468, 0xa00066b, 0x0, 0xa4102b, +0x10400009, 0x24030001, 0x52840, 0xa4102b, +0x4a00003, 0x31840, 0x5440fffc, 0x52840, +0x10600007, 0x0, 0x85302b, 0x14c00002, +0x31842, 0x852023, 0x1460fffb, 0x52842, +0x3e00008, 0x801021, 0x8f85002c, 0x27bdffe8, +0x53027, 0x2cc30001, 0x2ca40002, 0x831025, +0x10400003, 0xafbf0010, 0x2405007f, 0xaf85002c, +0x52827, 0x30a5ffff, 0xe000592, 0x240426f5, +0x8f830030, 0x240402bd, 0x403021, 0x83382b, +0x10e00009, 0x24050001, 0x42040, 0x83102b, +0x4800003, 0x52840, 0x5440fffc, 0x42040, +0x10a00008, 0xc35021, 0x64402b, 0x15000002, +0x52842, 0x641823, 0x14a0fffb, 0x42042, +0xc35021, 0x8fbf0010, 0xa4c02, 0x312200ff, +0x27bd0018, 0xaf8a002c, 0x3e00008, 0xaf890030, +0x0 }; +u32_t TPAT_b06FwData[(0x0/4) + 1] = { 0x0 }; +u32_t TPAT_b06FwRodata[(0x0/4) + 1] = { 0x0 }; +u32_t TPAT_b06FwBss[(0x450/4) + 1] = { 0x0 }; +u32_t TPAT_b06FwSbss[(0x44/4) + 1] = { 0x0 }; +u32_t TPAT_b06FwSdata[(0x0/4) + 1] = { 0x0 }; diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/txpfw.h b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/txpfw.h new file mode 100644 index 0000000000..0344325941 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/txpfw.h @@ -0,0 +1,1318 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* 4.0.4 */ +#include "bcmtype.h" +int TXP_b06FwReleaseMajor = 0x1; +int TXP_b06FwReleaseMinor = 0x0; +int TXP_b06FwReleaseFix = 0x0; +u32_t TXP_b06FwStartAddr = 0x080000a8; +u32_t TXP_b06FwTextAddr = 0x08000000; +int TXP_b06FwTextLen = 0x4fe8; +u32_t TXP_b06FwDataAddr = 0x00000000; +int TXP_b06FwDataLen = 0x0; +u32_t TXP_b06FwRodataAddr = 0x00000000; +int TXP_b06FwRodataLen = 0x0; +u32_t TXP_b06FwBssAddr = 0x08005088; +int TXP_b06FwBssLen = 0x1ac; +u32_t TXP_b06FwSbssAddr = 0x08005000; +int TXP_b06FwSbssLen = 0x88; +u32_t TXP_b06FwSDataAddr = 0x00000000; +int TXP_b06FwSDataLen = 0x0; +u32_t TXP_b06FwText[(0x4fe8/4) + 1] = { +0xa00002a, +0x0, 0x0, 0xd, 0x74787036, +0x2e322e33, 0x0, 0x6020300, 0x0, +0x136, 0xea60, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x16, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x1388, 0x0, 0x5dc, +0x0, 0x0, 0x10000003, 0x0, +0xd, 0xd, 0x3c020800, 0x24425000, +0x3c030800, 0x24635234, 0xac400000, 0x43202b, +0x1480fffd, 0x24420004, 0x3c1d0800, 0x37bd7ffc, +0x3a0f021, 0x3c100800, 0x261000a8, 0x3c1c0800, +0x279c5000, 0xe0008f1, 0x0, 0xd, +0xaf440e00, 0x8f430000, 0x30620008, 0x1040fffd, +0x0, 0x97450e08, 0xa785005c, 0x8f440e04, +0xaf840054, 0x3e00008, 0x0, 0xd, +0x3e00008, 0x0, 0x3c0d000a, 0x27bdffe8, +0x34d6021, 0x3c040800, 0x24845088, 0x2405000c, +0x3021, 0xafbf0010, 0xe0006b7, 0xaf8c0000, +0x3c0b6000, 0x8d6a149c, 0x8fbf0010, 0x3c050800, +0x24a505d0, 0x3149ffff, 0x3c060800, 0x24c60130, +0x2524ffee, 0x3c080800, 0x250801f8, 0x3c070800, +0x24e7039c, 0x3c020800, 0x24420604, 0x3c030800, +0x24630614, 0x3c010800, 0xac2850b8, 0x3c010800, +0xac2750bc, 0x3c010800, 0xac2250d0, 0x3c010800, +0xac2350d4, 0x3c010800, 0xac2550d8, 0x3c010800, +0xac2650e0, 0x3c010800, 0xac2400a0, 0x3c010800, +0xac2550c0, 0x3c010800, 0xac2650c8, 0x3e00008, +0x27bd0018, 0x8f860060, 0x3c050800, 0x8ca55098, +0x90c7003e, 0x8f44096c, 0x93430923, 0x30e20004, +0x10400009, 0x306800ff, 0x3c0d6000, 0x8dac5404, +0x3c0a0800, 0x8d4a0060, 0x318b003f, 0x14b482b, +0x1520001c, 0x41842, 0x3c030800, 0x8c635088, +0x3c040800, 0x8c84508c, 0x64102b, 0x54400001, +0x602021, 0xa4182b, 0x54600001, 0xa02021, +0x31050002, 0x10a0000b, 0x0, 0x8cc70124, +0x8f880008, 0x1071023, 0x10800006, 0x441821, +0x4400019, 0x284a0002, 0x5540003a, 0x240b0001, +0xd, 0x3c010800, 0xac245090, 0x3e00008, +0x1021, 0xa3202b, 0x54800001, 0xa01821, +0x3c070800, 0x8ce7508c, 0xe3702b, 0x11c00006, +0x0, 0x8cd80050, 0x8cd9004c, 0x3197823, +0x1de0ffe3, 0x2021, 0x3c030800, 0x8c635088, +0xa000093, 0xe02021, 0x1860ffea, 0x0, +0x24090001, 0x10690002, 0x0, 0xd, +0x90cd003f, 0x2dac000c, 0x11800005, 0x2484ffff, +0x90cf003f, 0x2dee0007, 0x11c0001a, 0x24030010, +0x90d90118, 0x24060003, 0x333800ff, 0x13060015, +0x24030010, 0x3c080800, 0x8d0850b4, 0x3c030800, +0x8c635088, 0x25050001, 0x3c010800, 0xac2550b4, +0x1060ffd0, 0x0, 0x2467ffff, 0x3c010800, +0xac275088, 0x3c010800, 0xac245090, 0x3e00008, +0x1021, 0x148bffe1, 0x0, 0xa0000c1, +0x0, 0x24020001, 0x3c010800, 0xa0235096, +0xa0000ce, 0xaf82001c, 0x8f45096c, 0x3c030800, +0x8c635098, 0x52042, 0x64102b, 0x14400003, +0x604021, 0x8f46096c, 0x64042, 0x8f860060, +0x240d0010, 0x90cb003e, 0x8cc90050, 0x8f8c0054, +0x9787005c, 0x3c010800, 0xa02d5094, 0x3c010800, +0xac2c5090, 0x30ea0040, 0x11400005, 0x316700ff, +0x978f005c, 0x31ee1000, 0x11c0003f, 0x0, +0x8f830064, 0x8c620024, 0x8f840054, 0x8c790008, +0x44c021, 0x13380038, 0x0, 0x30eb0004, +0x1160000f, 0x0, 0x8f870054, 0x10e80046, +0x0, 0x8f8f0054, 0x1e8702b, 0x11c00008, +0x3c036000, 0x8c645404, 0x3c190800, 0x8f390060, +0x3082003f, 0x322c02b, 0x17000044, 0x0, +0x90c2011a, 0x24180002, 0x305900ff, 0x13380029, +0x0, 0x90cc011a, 0x240b0001, 0x318700ff, +0x10eb0005, 0x0, 0x8f890054, 0x128682b, +0x15a0000c, 0x0, 0x90c50122, 0x2403fffd, +0x24040006, 0xa31024, 0xa0c20122, 0x8f860054, +0x54c00001, 0x2021, 0x801821, 0x3e00008, +0x601021, 0x3c0f0800, 0x91ef5094, 0x31ee0008, +0x15c0fff1, 0x0, 0x3c010800, 0xac205090, +0x90d90122, 0x24030006, 0x601021, 0x37380002, +0x3e00008, 0xa0d80122, 0x3c0a0800, 0x914a5094, +0x35450008, 0x3c010800, 0xa0255094, 0xa000109, +0x30eb0004, 0x8f830054, 0x68202b, 0x50800006, +0x24080001, 0x8cca000c, 0x31450001, 0x10a0ffd1, +0x0, 0x24080001, 0xacc8000c, 0xa0c0011a, +0xa000127, 0x8f860060, 0x974c0e14, 0x974d0e10, +0x15acffb8, 0x0, 0x90c90122, 0x35220008, +0xa0c20122, 0xa000119, 0x8f860060, 0x8cca004c, +0x12a2823, 0x18a0ffba, 0x0, 0x90c70122, +0x30eb0008, 0x1560000b, 0x0, 0x978e005c, +0x31c90080, 0x1120ffb2, 0x8f8f001c, 0x15e0ffb0, +0x24030006, 0x3c010800, 0xac205090, 0x3e00008, +0x601021, 0x90cc0122, 0x240dfff7, 0x18d1024, +0xa0c20122, 0xa000119, 0x8f860060, 0x3c0a0800, +0x914a5095, 0x3c090800, 0x952950a2, 0x3c051100, +0xa3c00, 0x25280002, 0xe83025, 0xc51825, +0x24820008, 0xac830000, 0x3e00008, 0xac800004, +0x3c010800, 0xac205090, 0x3e00008, 0x24020001, +0x24020010, 0x3c010800, 0xa0225094, 0x3c010800, +0xac205090, 0x3e00008, 0x24020004, 0x8f840058, +0x3c058000, 0x34a20001, 0x821825, 0x3e00008, +0xaf430020, 0x8f830058, 0x3c088000, 0x35070070, +0x8ce50000, 0x833025, 0x3c029000, 0xc22025, +0xaf850050, 0xaf440020, 0x8f490020, 0x520fffe, +0x3c038000, 0x34620070, 0x8c450000, 0x8f860050, +0x3c190800, 0x8f39007c, 0x3c0e0800, 0x8dce0078, +0xa62023, 0x3245821, 0x7821, 0x164682b, +0x1cf6021, 0x18d5021, 0x3c010800, 0xac2b007c, +0x3c010800, 0xac2a0078, 0x3e00008, 0x0, +0xa000192, 0x24040001, 0x8f830060, 0x27bdffe0, +0xafb10014, 0xafb00010, 0xafbf0018, 0x808821, +0x8c64000c, 0x30820001, 0x14400007, 0x8021, +0x2001021, 0x8fbf0018, 0x8fb10014, 0x8fb00010, +0x3e00008, 0x27bd0020, 0xe0001b1, 0x0, +0x8f850060, 0x8ca7000c, 0x30e60001, 0x10c00022, +0x0, 0x16200028, 0x0, 0x90a80081, +0x15000011, 0x0, 0x94aa006a, 0x3149ffff, +0x91880, 0x50600001, 0x24030001, 0x94ad0068, +0x3c060800, 0x8cc60024, 0x31acffff, 0x1832021, +0x86582b, 0x55600001, 0xc02021, 0xaca40028, +0xa0001e0, 0x0, 0x8ca40028, 0x3c030800, +0x8c630028, 0x64702b, 0x55c00001, 0x602021, +0x8f580074, 0x801021, 0x28840, 0x2387821, +0x24100001, 0xacaf000c, 0xe00018c, 0x0, +0x2001021, 0x8fbf0018, 0x8fb10014, 0x8fb00010, +0x3e00008, 0x27bd0020, 0x3c020800, 0x8c420098, +0x8f580074, 0x24100001, 0x28840, 0x2387821, +0xa0001eb, 0xacaf000c, 0x27bdffd8, 0xafbf0024, +0xafb40020, 0xafb3001c, 0xafb20018, 0xafb10014, +0xafb00010, 0x24070040, 0xaf400810, 0xaf470814, +0x8f870060, 0x8f430944, 0x8f440950, 0x8f450954, +0x8f46095c, 0x90e80000, 0x24020020, 0xaf830004, +0x310300ff, 0xaf840008, 0xaf85000c, 0x10620010, +0xaf860010, 0x24090050, 0x106902cf, 0x8fbf0024, +0x3c0b0800, 0x8d6b0030, 0x256a0001, 0x3c010800, +0xac2a0030, 0x8fb40020, 0x8fb3001c, 0x8fb20018, +0x8fb10014, 0x8fb00010, 0x3e00008, 0x27bd0028, +0x24110088, 0xaf510818, 0x24100800, 0xaf500178, +0x8f430988, 0x8f4509a0, 0x8f4f0104, 0x8f4e09a4, +0x3c010800, 0xac2550b0, 0x974d093c, 0x1ee2023, +0x3c010800, 0xac2e50b4, 0x31acffff, 0x3c010800, +0xac2c5098, 0x3c010800, 0xa0205097, 0x3c140800, +0x269450b8, 0x4800393, 0x0, 0x3c010800, +0xac245088, 0x8f860008, 0x8f820058, 0xaf80001c, +0x3c010800, 0xac2650a8, 0xaf420080, 0x3c1f0800, +0x8fff50b4, 0xaf450e10, 0x9351010b, 0xaf5f0e18, +0x93590905, 0x33380008, 0x17000328, 0x322b0002, +0x156003d9, 0x0, 0x934a0108, 0x31490010, +0x11200030, 0x0, 0x90e2007f, 0x90ff007e, +0x90f80080, 0x305900ff, 0x90ed007a, 0x1f9600, +0x199c00, 0x331000ff, 0x2537025, 0x107a00, +0x1cf6025, 0x31ab00ff, 0x18b2025, 0x8f460178, +0x4c0fffe, 0x24070052, 0x3c090800, 0x8d2950b4, +0x3c0a0800, 0x8d4a50b0, 0x24037000, 0x3c081000, +0xaf4a0144, 0xaf490148, 0xaf44014c, 0xa3470152, +0xa7400158, 0xaf430154, 0xaf480178, 0x3c040800, +0x8c840034, 0x24850001, 0x3c010800, 0xac250034, +0x12200307, 0x0, 0x3c0b0800, 0x8d6b5088, +0x11600008, 0x8f870060, 0x3c0d0800, 0x8dad0038, +0x3c010800, 0xac205088, 0x25ac0001, 0x3c010800, +0xac2c0038, 0x9350093f, 0x240e0012, 0x320f00ff, +0x11ee03cb, 0x32320028, 0x90e20023, 0x2fe00, +0x1fce03, 0x72003c2, 0x0, 0x9344093f, +0x24060010, 0x308500ff, 0x10a603bd, 0x0, +0x97480908, 0x110003df, 0x0, 0x97500908, +0x320fffff, 0xf71c0, 0xaf4e0024, 0x974d0908, +0x3c0a0080, 0x35490003, 0x31acffff, 0xc59c0, +0xaf4b080c, 0xaf49081c, 0x974709ec, 0x8f4309a4, +0xa7870014, 0x3c010800, 0xac2350ac, 0x93480934, +0x93440937, 0x310200ff, 0x308500ff, 0x53080, +0xc2c021, 0x3c010800, 0xa438509e, 0x935f09d8, +0x33f900ff, 0x3199821, 0x3c010800, 0xa43350a0, +0x935209d8, 0x93500934, 0x324e00ff, 0x320f00ff, +0x1cf6821, 0x25ac0010, 0x3c010800, 0xa42c509c, +0x24130006, 0x32320028, 0x3c010800, 0xac3350a4, +0x3c010800, 0xa0205096, 0xa780005c, 0x16400259, +0x9821, 0x8f990008, 0x8f9f0010, 0x8f580958, +0x3f91823, 0x4600266, 0x3192023, 0x4800264, +0x64302b, 0x10c0026a, 0x0, 0x3c010800, +0xac23508c, 0x8e900000, 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0x30980003, 0x17000002, +0x981823, 0x2483fffc, 0x3c010800, 0xac2351d4, +0xa00119e, 0x0, 0xa75824, 0xa0011c6, +0x1671826, 0x3c010800, 0xa42d51f2, 0xa00122e, +0x0, 0x3c010800, 0xac2051d4, 0xa0011d9, +0x24030042, 0x8f830030, 0x14600007, 0x1021, +0x8f880044, 0x24050005, 0x91060000, 0x30c400ff, +0x10850003, 0x0, 0x3e00008, 0x0, +0x910a0018, 0x314900ff, 0x939c2, 0x14e0fffa, +0x8f85003c, 0x3c040800, 0x948451dc, 0x3c030800, +0x8c6351f4, 0x3c190800, 0x8f3951d4, 0x3c0f0800, +0x95ef51f2, 0x64c021, 0x8cad0054, 0x3197021, +0x1cf6021, 0x18d5823, 0x1960001d, 0x0, +0x910e001c, 0x8f8c004c, 0x974b0e10, 0x31cd00ff, +0x8d850004, 0x16d3023, 0x8d880000, 0x30ceffff, +0xe5100, 0xaac821, 0x3821, 0x1072021, +0x32a182b, 0x83c021, 0xad990004, 0xad980000, +0x918f000a, 0x1cf6821, 0xa18d000a, 0x8f88004c, +0x974b0e12, 0xa50b0008, 0x950a0038, 0x25490001, +0xa5090038, 0x9107000d, 0x34e60008, 0xa106000d, +0x3e00008, 0x0, 0x27bdffe0, 0x93870024, +0x8f8f0044, 0x8fad0014, 0x3c0e7fff, 0x8f89002c, +0x35c8ffff, 0xafbf001c, 0xafb00018, 0x1a81824, +0x91ea000d, 0x717c0, 0x3c1fbfff, 0x625825, +0x2d2e0001, 0x8f900038, 0x37f9ffff, 0x3c180800, +0x8f1851f4, 0x3c0f0800, 0x95ef51ea, 0x1796824, +0xe4780, 0x3c07efff, 0x3c05f0ff, 0x1a81825, +0x31490020, 0x34e2ffff, 0x34acffff, 0x3105823, +0x27a50010, 0x24060002, 0x25ea0002, 0x621824, +0x808021, 0x15200002, 0x4021, 0x8f480e1c, +0xa7aa0012, 0x5600037, 0x24070000, 0x30ff00ff, +0x1fcf00, 0x8f8b003c, 0x793825, 0xafa70014, +0x916f0085, 0x3c080800, 0x910851f1, 0x3c18dfff, +0x31ee00c0, 0x370affff, 0xe182b, 0x3c1f0800, +0x97ff51e4, 0xea6824, 0xa3a80011, 0x31740, +0x1a24825, 0x8fb90010, 0xafa90014, 0x3c0a0800, +0x914a51f3, 0xa7bf0016, 0x8fa80014, 0x32cc024, +0x3c0b0100, 0x3c0f0fff, 0x30b1825, 0x31470003, +0x35eeffff, 0x10c6824, 0x71600, 0x6ef824, +0x3c097000, 0x1a2c825, 0x3e95825, 0xafb90014, +0xafab0010, 0xe0006ad, 0xa3a00015, 0x8f8c0044, +0x26020008, 0x9186000d, 0x30c40020, 0x10800006, +0x8fbf001c, 0x3c050800, 0x94a551e0, 0x24b0ffff, +0x3c010800, 0xa43051e0, 0x8fb00018, 0x3e00008, +0x27bd0020, 0x8f980034, 0x118502b, 0x5540ffc7, +0x24070001, 0xa0012b1, 0x30ff00ff, 0x93820024, +0x27bdffe0, 0xafbf0018, 0x1040000f, 0x805021, +0x8f880044, 0x240b0005, 0x8f890028, 0x91070000, +0x8f840040, 0x1002821, 0x30e3003f, 0x8f86004c, +0x106b0008, 0x3821, 0xafa90010, 0xe000a4d, +0xafaa0014, 0xa3800024, 0x8fbf0018, 0x3e00008, +0x27bd0020, 0x8d190018, 0x3c0f0800, 0x8def51d4, +0x8f980030, 0x3c027fff, 0x8d080014, 0x345fffff, +0x33f6824, 0x1f87021, 0x1ae6023, 0x1883821, +0xafa90010, 0xe000a4d, 0xafaa0014, 0xa0012ff, +0xa3800024, 0x8f870044, 0x3c050800, 0x94a551f2, +0x3c020800, 0x8c4251ec, 0x90e6000d, 0x52400, +0x30c30020, 0x1060002c, 0x444025, 0x8f85003c, +0x6021, 0x240b0001, 0x90a30085, 0x4821, +0x240a0001, 0x3c0f8000, 0x35ee0070, 0x8dc70000, +0xaf870050, 0x8f580178, 0x700fffe, 0x3c038000, +0x34790070, 0x8f380000, 0x3c050800, 0x8ca50074, +0x3c0d0800, 0x8dad0070, 0x3077823, 0xaf3821, +0x1021, 0xef302b, 0x1a22021, 0x861821, +0x3c010800, 0xac270074, 0x3c010800, 0xac230070, +0xaf4b0148, 0x3c190800, 0x8f3951f4, 0xa7490144, +0xa74a0146, 0xaf59014c, 0x3c0b0800, 0x916b51f1, +0xa34b0152, 0xaf480154, 0x3c081000, 0xa74c0158, +0x3e00008, 0xaf480178, 0x8f4b0e1c, 0x3c0a0800, +0x8d4a51d4, 0x97490e16, 0x974d0e14, 0x1456021, +0x312affff, 0xa001322, 0x31a9ffff, 0x8f830044, +0x9064000d, 0x30820020, 0x10400029, 0x0, +0x4821, 0x5021, 0x4021, 0x3c078000, +0x34eb0070, 0x8d670000, 0xaf870050, 0x8f4c0178, +0x580fffe, 0x3c0d8000, 0x35ac0070, 0x8d8b0000, +0x3c050800, 0x8ca50074, 0x3c040800, 0x8c840070, +0x1673023, 0xa67821, 0x1021, 0x1e6c82b, +0x82c021, 0x3197021, 0x3c010800, 0xac2f0074, +0x3c010800, 0xac2e0070, 0xaf490148, 0x3c0d0800, +0x8dad51f4, 0xa7480144, 0x24090040, 0xa74a0146, +0x3c081000, 0x240aff91, 0xaf4d014c, 0xa34a0152, +0xaf490154, 0xa7400158, 0x3e00008, 0xaf480178, +0x8f490e18, 0x97460e12, 0x97450e10, 0x30caffff, +0xa001358, 0x30a8ffff, 0x8f830044, 0x27bdfff8, +0x9064000d, 0x30820020, 0x1040003a, 0x0, +0x240b0001, 0x4821, 0x240a0001, 0x3c088000, +0x35070070, 0x8ce30000, 0xaf830050, 0x8f4c0178, +0x580fffe, 0x3c0e8000, 0x3c040800, 0x90845230, +0x35c70070, 0x8cec0000, 0x3c050800, 0x8ca50074, +0xa3a40003, 0x3c190800, 0x8f390070, 0x8fad0000, +0x1833023, 0xa63821, 0x1021, 0x3227821, +0xe6c02b, 0x1f86021, 0x1ae4025, 0xafa80000, +0x3c010800, 0xac270074, 0x3c010800, 0xac2c0070, +0x9346010a, 0x3c040800, 0x90845231, 0xa3a00002, +0xa3a60001, 0x8fa30000, 0x3c0580ff, 0x3099007f, +0x34a2ffff, 0x627824, 0x19c600, 0x1f87025, +0x240d3000, 0xaf4e014c, 0x27bd0008, 0xaf4d0154, +0xa7400158, 0xaf4b0148, 0xa7490144, 0xa74a0146, +0x3c091000, 0x240aff80, 0xa34a0152, 0x3e00008, +0xaf490178, 0x8f4b0e18, 0x97460e12, 0x97450e10, +0x30caffff, 0xa00138c, 0x30a9ffff, 0x8f85003c, +0x24020080, 0x90a40085, 0x308300c0, 0x10620005, +0x8f860040, 0x8f880028, 0x8f87002c, 0xacc800c8, +0xacc700c4, 0x3e00008, 0x0, 0x3c0a0800, +0x254a4d40, 0x3c090800, 0x25294e0c, 0x3c080800, +0x250841c0, 0x3c070800, 0x24e74f20, 0x3c060800, +0x24c64bb0, 0x3c050800, 0x24a54928, 0x3c040800, +0x24844550, 0x3c030800, 0x24634c48, 0x3c020800, +0x24424a1c, 0x3c010800, 0xac2a51b0, 0x3c010800, +0xac2951ac, 0x3c010800, 0xac2851a8, 0x3c010800, +0xac2751b4, 0x3c010800, 0xac2651c4, 0x3c010800, +0xac2551bc, 0x3c010800, 0xac2451b8, 0x3c010800, +0xac2351c8, 0x3c010800, 0xac2251c0, 0x3e00008, +0x0, 0x0 }; +u32_t TXP_b06FwData[(0x0/4) + 1] = { 0x0 }; +u32_t TXP_b06FwRodata[(0x0/4) + 1] = { 0x0 }; +u32_t TXP_b06FwBss[(0x1ac/4) + 1] = { 0x0 }; +u32_t TXP_b06FwSbss[(0x88/4) + 1] = { 0x0 }; +u32_t TXP_b06FwSdata[(0x0/4) + 1] = { 0x0 }; diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/xi90_rv2p_p1.h b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/xi90_rv2p_p1.h new file mode 100644 index 0000000000..ade6484c7c --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/xi90_rv2p_p1.h @@ -0,0 +1,508 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __xi90_rv2p_proc1_h__ +#define __xi90_rv2p_proc1_h__ +#include "bcmtype.h" + +u32_t xi90_rv2p_proc1[] = { + 0x00000010, 0xb1800006, + 0x0000001f, 0x03060201, + 0x00000008, 0x05000000, + 0x00000018, 0x00020000, + 0x00000008, 0x050000ff, + 0x00000018, 0x00020000, + 0x00000008, 0xac000001, + 0x00000008, 0x07800000, + 0x0000000c, 0x2f800001, + 0x00000000, 0x2b000000, + 0x00000000, 0x2b800000, + 0x00000010, 0x91e10002, + 0x00000008, 0xac000001, + 0x00000010, 0x203f0058, + 0x00000010, 0x213f0003, + 0x00000010, 0x20bf0032, + 0x00000018, 0x8000fffd, + 0x00000008, 0x03800800, + 0x00000010, 0xb6380e01, + 0x00000010, 0xb1b8b00d, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c380000, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x80000081, + 0x00000018, 0x8000014b, + 0x00000008, 0x02000002, + 0x0000000f, 0x42e0001c, + 0x00000010, 0x91840a11, + 0x00000010, 0x2c62000b, + 0x00000018, 0x8000001b, + 0x00000008, 0x02000002, + 0x0000000f, 0x42e0001c, + 0x00000010, 0x91840a16, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800108, + 0x00000018, 0x80000087, + 0x00000018, 0x80000012, + 0x00000008, 0xb1000001, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800001, + 0x00000018, 0x80000074, + 0x0000000b, 0x2fdf0002, + 0x0000000c, 0x1f800002, + 0x00000000, 0x2c070000, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000ffd9, + 0x0000000b, 0x2fdf0002, + 0x0000000c, 0x1f800000, + 0x00000000, 0x2c070000, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000ffd4, + 0x0000000c, 0x1f800002, + 0x00000018, 0x8000ffd2, + 0x00000010, 0x0ce70002, + 0x00000010, 0x2ce20046, + 0x0000000c, 0x29800002, + 0x0000000c, 0x1f800002, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000005, + 0x00000018, 0x8000ffcb, + 0x00000008, 0x02240042, + 0x00000018, 0x00040000, + 0x00000018, 0x80000000, + 0x00000018, 0x8000001b, + 0x00000018, 0x80000073, + 0x00000018, 0x800000af, + 0x00000018, 0x800000e0, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x8000012c, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x800000f6, + 0x00000018, 0x80000000, + 0x00000018, 0x8000012b, + 0x00000018, 0x80000155, + 0x00000018, 0x80000122, + 0x00000018, 0x80000178, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000002, + 0x00000008, 0x07800000, + 0x00000018, 0x8000ffa7, + 0x00000008, 0x03800100, + 0x00000010, 0xb73c0e00, + 0x00000010, 0xb1bcb00a, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c3c0000, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000002d, + 0x00000018, 0x800000f7, + 0x00000010, 0x2c6201c4, + 0x00000018, 0x80000006, + 0x00000008, 0x2c80010d, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x00000018, 0x80000039, + 0x0000000c, 0x29800000, + 0x0000000c, 0x1f800000, + 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, + 0x00000010, 0x2e670005, + 0x00000010, 0x0ce20004, + 0x00000018, 0x80000005, + 0x00000008, 0x2a000011, + 0x00000018, 0x80000002, + 0x00000008, 0x2a000006, + 0x00000018, 0x8000ff8b, + 0x0000000c, 0x71620019, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800001, + 0x00000018, 0x00020000, + 0x00000000, 0x02020000, + 0x00000000, 0x029a0000, + 0x00000000, 0x060c2c00, + 0x00000004, 0xc60c3400, + 0x00000010, 0x001f0000, + 0x00000010, 0xba8c2c0c, + 0x00000008, 0x06960004, + 0x00000009, 0x068dfffc, + 0x00000004, 0xcd051a00, + 0x00000004, 0xcc9a1800, + 0x00000010, 0x20d70000, + 0x0000000c, 0x2b560000, + 0x00000000, 0x00000000, + 0x00000000, 0x00000000, + 0x00000010, 0x20d70000, + 0x00000008, 0x0f800001, + 0x00000010, 0xb18001f4, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6b560000, + 0x00000018, 0x00040000, + 0x00000000, 0x06820000, + 0x00000010, 0xb18f0004, + 0x00000010, 0xb18f1403, + 0x00000008, 0x2a000001, + 0x00000010, 0x91d40000, + 0x00000000, 0x07801400, + 0x00000018, 0x000d0000, + 0x00000000, 0x05020000, + 0x00000010, 0x91de0000, + 0x00000018, 0x000a0000, + 0x00000000, 0x06820000, + 0x00000010, 0x91de0000, + 0x00000009, 0x0561ffff, + 0x00000010, 0x918a0002, + 0x00000008, 0x30e1ffff, + 0x00000018, 0x8000ff5b, + 0x00000001, 0x05611400, + 0x00000010, 0x918a0002, + 0x00000008, 0xb0e10001, + 0x00000018, 0x000d0000, + 0x00000000, 0x06820000, + 0x00000010, 0x91de0000, + 0x00000009, 0x0562ffff, + 0x00000010, 0x918a0002, + 0x00000008, 0x3162ffff, + 0x00000018, 0x8000ff51, + 0x00000001, 0x05621400, + 0x00000010, 0x918a0002, + 0x00000008, 0xb1620001, + 0x00000018, 0x000d0000, + 0x00000010, 0xb1a0b013, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000ffdb, + 0x00000008, 0x2d80011c, + 0x00000010, 0x001f0000, + 0x00000018, 0x8000ffe2, + 0x0000000f, 0x47600008, + 0x0000000f, 0x060e0001, + 0x00000000, 0x0f580000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0d610000, + 0x00000018, 0x80000015, + 0x0000000f, 0x47600008, + 0x0000000b, 0x2fdf0002, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d80011c, + 0x0000000f, 0x060e0001, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f580000, + 0x00000018, 0x8000ffd0, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0d610000, + 0x00000000, 0x02620000, + 0x00000000, 0x02e00000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x30050000, + 0x00000000, 0x31040000, + 0x00000000, 0x309a0000, + 0x00000010, 0x0060000c, + 0x00000010, 0x21a2000b, + 0x00000010, 0xb1a6000a, + 0x00000008, 0x05160001, + 0x00000010, 0xba9a1403, + 0x00000000, 0x03000000, + 0x00000018, 0x80000006, + 0x00000018, 0x8000ff1c, + 0x00000010, 0xb6061404, + 0x00000008, 0x03060001, + 0x00000008, 0x2a000001, + 0x00000018, 0x8000ff21, + 0x00000018, 0x8000ff9b, + 0x0000000c, 0x29800001, + 0x0000000c, 0x29520001, + 0x0000000c, 0x29520000, + 0x00000008, 0x22800002, + 0x00000008, 0x02000003, + 0x0000000c, 0x1f800001, + 0x00000000, 0x2adf0000, + 0x00000000, 0x2a000800, + 0x00000018, 0x8000ff17, + 0x00000010, 0xb1a0b011, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000ffa0, + 0x00000018, 0x8000006a, + 0x0000000f, 0x47600008, + 0x00000000, 0x060e0000, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f580000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000000, 0x0b670000, + 0x00000000, 0x0d620000, + 0x00000018, 0x80000019, + 0x0000000f, 0x47600008, + 0x0000000b, 0x2fdf0002, + 0x00000008, 0x2c80010d, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d80012b, + 0x0000000f, 0x060e0001, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f580000, + 0x00000018, 0x8000ff9f, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000000, 0x0b670000, + 0x00000000, 0x0d620000, + 0x00000000, 0x02630000, + 0x0000000f, 0x47620010, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x31840000, + 0x00000000, 0x311a0000, + 0x0000000b, 0xc20000ff, + 0x00000002, 0x42040000, + 0x00000001, 0x31620800, + 0x0000000f, 0x020e0010, + 0x00000002, 0x31620800, + 0x00000018, 0x8000ff68, + 0x00000010, 0x2ce20162, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x0000000c, 0x61420006, + 0x00000008, 0x22000008, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000004, + 0x00000018, 0x8000fee5, + 0x00000010, 0x91a0b009, + 0x00000008, 0x2c80010d, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x00000018, 0x8000ff82, + 0x00000018, 0x8000000f, + 0x00000008, 0xac000001, + 0x00000018, 0x8000000b, + 0x00000000, 0x0380b000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c004000, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000ff65, + 0x00000018, 0x8000002f, + 0x00000018, 0x80000005, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c000e00, + 0x00000008, 0x2a000007, + 0x00000018, 0x8000fed0, + 0x00000000, 0x06820000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000010, 0x0ce70007, + 0x00000009, 0x0562ffff, + 0x00000010, 0xba6c1405, + 0x00000000, 0x2adf0000, + 0x00000000, 0x21000000, + 0x00000008, 0x2a000005, + 0x00000010, 0x91d40000, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x0000000c, 0x31620018, + 0x00000008, 0x2d800001, + 0x00000018, 0x8000ff57, + 0x00000018, 0x000d0000, + 0x00000010, 0xb1a0b00d, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c200000, + 0x00000010, 0x91d40000, + 0x00000018, 0x80000014, + 0x00000010, 0x2c620002, + 0x00000018, 0x8000000b, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c070000, + 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000feb3, + 0x00000008, 0x2c80010d, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x00000018, 0x8000ff51, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000a, + 0x00000008, 0x07800000, + 0x00000018, 0x8000fea7, + 0x00000000, 0x06820000, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800134, + 0x00000000, 0x00000000, + 0x00000010, 0x205f0000, + 0x00000008, 0x2c800140, + 0x00000008, 0x2d00003c, + 0x00000008, 0x2d80011c, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000008, 0x2c800080, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d800105, + 0x00000009, 0x0562ffff, + 0x00000010, 0x918a0002, + 0x00000008, 0x3162ffff, + 0x00000018, 0x8000fe8e, + 0x00000001, 0x05621400, + 0x00000010, 0x918a0002, + 0x00000008, 0xb1620001, + 0x00000010, 0x91de0000, + 0x00000018, 0x000d0000, + 0x00000010, 0x91d40000, + 0x00000008, 0x050000aa, + 0x00000018, 0x8000ff1c, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000009, + 0x00000018, 0x8000fe89, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000ff15, + 0x00000010, 0x91a0b002, + 0x00000010, 0xb1e66207, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c310000, + 0x00000009, 0x2cb1007f, + 0x00000008, 0x2cd90000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d80010d, + 0x00000010, 0xb1a80006, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c200000, + 0x00000000, 0x2ca70000, + 0x00000008, 0x2d000010, + 0x00000008, 0x2d800108, + 0x00000018, 0x8000ff0d, + 0x00000010, 0xb1a60010, + 0x00000010, 0x001f0000, + 0x0000000f, 0x0f300007, + 0x00000000, 0x0a600000, + 0x00000000, 0x0ae10000, + 0x0000000f, 0x4b620008, + 0x00000009, 0x0b1600ff, + 0x00000000, 0x0d620000, + 0x00000009, 0x0d1a00ff, + 0x00000010, 0x07300003, + 0x0000000c, 0x0d1a0008, + 0x0000000c, 0x0b160008, + 0x0000000f, 0x4ce30018, + 0x00000000, 0x0c992c00, + 0x00000004, 0xcc993400, + 0x00000008, 0x0f800000, + 0x0000000c, 0x29800001, + 0x00000000, 0x33310000, + 0x00000008, 0x22000016, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000c, + 0x00000010, 0x009f0000, + 0x00000000, 0x2c200000, + 0x0000000c, 0x1f800001, + 0x00000018, 0x8000fe5e, + 0x00000010, 0x91d40000, + 0x00000008, 0x050000aa, + 0x00000018, 0x8000feea, + 0x0000000f, 0x47220008, + 0x00000009, 0x070e000f, + 0x00000008, 0x070e0008, + 0x00000008, 0x02800001, + 0x00000007, 0x02851c00, + 0x00000008, 0x82850001, + 0x00000000, 0x02854c00, + 0x00000007, 0x42851c00, + 0x00000003, 0xc3aa5200, + 0x00000000, 0x03b10e00, + 0x00000007, 0x4b071c00, + 0x0000000f, 0x0f300007, + 0x0000000f, 0x0a960003, + 0x00000000, 0x0a955c00, + 0x00000000, 0x4a005a00, + 0x00000000, 0x0c960a00, + 0x00000009, 0x0c99ffff, + 0x00000008, 0x0d00ffff, + 0x00000010, 0xba992c02, + 0x00000008, 0x0f800005, + 0x00000010, 0xb1a80008, + 0x00000010, 0x205f0000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, + 0x00000000, 0x2ca70000, + 0x00000008, 0x2d000010, + 0x00000008, 0x2d800108, + 0x00000018, 0x8000fed5, + 0x0000000c, 0x29800001, + 0x00000010, 0x001f0000, + 0x0000000c, 0x1f800001, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000d, + 0x00000018, 0x8000fe39, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000fec5, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000007, + 0x00000018, 0x8000fe32, +}; +/* Calling this macro prior to loading will change value of POST_WAIT_TIMEOUT (default = 0x0)*/ +#define XI90_RV2P_PROC1_POST_WAIT_TIMEOUT_LOC 5 +#define XI90_RV2P_PROC1_CHG_POST_WAIT_TIMEOUT(value) {\ + xi90_rv2p_proc1[XI90_RV2P_PROC1_POST_WAIT_TIMEOUT_LOC] = (xi90_rv2p_proc1[XI90_RV2P_PROC1_POST_WAIT_TIMEOUT_LOC] & ~0xFFFF) | (value);\ +} + +/* Calling this macro prior to loading will change value of MAX_BD_PAGE (default = 0xff)*/ +#define XI90_RV2P_PROC1_MAX_BD_PAGE_LOC 9 +#define XI90_RV2P_PROC1_CHG_MAX_BD_PAGE(value) {\ + xi90_rv2p_proc1[XI90_RV2P_PROC1_MAX_BD_PAGE_LOC] = (xi90_rv2p_proc1[XI90_RV2P_PROC1_MAX_BD_PAGE_LOC] & ~0xFFFF) | (value);\ +} + +#endif /* __xi90_rv2p_proc1.h__ */ + diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/xi90_rv2p_p2.h b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/xi90_rv2p_p2.h new file mode 100644 index 0000000000..b84a9601ce --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/xi90_rv2p_p2.h @@ -0,0 +1,1024 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __xi90_rv2p_proc2_h__ +#define __xi90_rv2p_proc2_h__ +#include "bcmtype.h" + +u32_t xi90_rv2p_proc2[] = { + 0x00000010, 0xb1800006, + 0x0000001f, 0x03060201, + 0x00000008, 0x050000ff, + 0x00000018, 0x00020000, + 0x00000008, 0x05000001, + 0x00000018, 0x00020000, + 0x00000000, 0x2a000000, + 0x00000010, 0xb1d40000, + 0x00000010, 0x91de0000, + 0x00000010, 0x20530000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x2f80aa00, + 0x0000000c, 0x29800001, + 0x00000008, 0x02540012, + 0x00000000, 0x2c400000, + 0x00000000, 0x0f400000, + 0x00000009, 0x2952003f, + 0x00000018, 0x00040000, + 0x00000018, 0x80000011, + 0x00000018, 0x80000012, + 0x00000018, 0x80000047, + 0x00000018, 0x800000b4, + 0x00000018, 0x800001dd, + 0x00000018, 0x80000220, + 0x00000018, 0x8000030f, + 0x00000018, 0x80000000, + 0x00000018, 0x80000329, + 0x00000018, 0x800001d2, + 0x00000018, 0x80000000, + 0x00000018, 0x8000032f, + 0x00000018, 0x80000380, + 0x00000018, 0x8000006e, + 0x00000018, 0x8000006e, + 0x00000018, 0x8000006f, + 0x00000018, 0x800001f1, + 0x00000000, 0x2a000000, + 0x00000018, 0x8000ffe2, + 0x00000000, 0x2a000000, + 0x0000000c, 0x29800000, + 0x00000018, 0x8000ffdf, + 0x00000000, 0x03820000, + 0x00000018, 0x8000ffd8, + 0x00000001, 0x0c161400, + 0x00000000, 0x8c181400, + 0x00000010, 0x91980003, + 0x00000008, 0x0c960002, + 0x00000010, 0xb1800003, + 0x00000008, 0x0c960001, + 0x00000000, 0x0c000000, + 0x00000000, 0x0d190000, + 0x00000008, 0x0f800001, + 0x00000000, 0x00000000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000010, 0x011301f3, + 0x00000018, 0x00070000, + 0x00000000, 0x05020000, + 0x00000010, 0xb99a2c21, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d000006, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d610000, + 0x00000018, 0x000a0000, + 0x00000000, 0x05020000, + 0x00000010, 0xb99a2c16, + 0x00000010, 0x205f0000, + 0x00000000, 0x09d80000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c80010e, + 0x00000008, 0x2d00000a, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d620000, + 0x00000000, 0x2c130000, + 0x00000018, 0x000a0000, + 0x00000000, 0x05020000, + 0x00000010, 0xb99a2c09, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d00006a, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d7a0000, + 0x00000018, 0x000a0000, + 0x00000000, 0x2a000000, + 0x00000008, 0x22000001, + 0x00000000, 0x0d610000, + 0x00000010, 0x21c20029, + 0x00000010, 0xb1c60002, + 0x00000010, 0x23420030, + 0x00000009, 0x0b66ffff, + 0x00000010, 0xba9a2c25, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000000, 0x0c000000, + 0x00000000, 0x0b800000, + 0x00000008, 0x0cc60012, + 0x00000018, 0x8000ffd0, + 0x00000008, 0x0f800003, + 0x00000000, 0x00000000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000010, 0x919b3200, + 0x00000008, 0x27110012, + 0x00000000, 0x66900000, + 0x00000010, 0xb1980004, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000008, 0x0f800004, + 0x00000008, 0x22000003, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d00000c, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000010, 0x91c60006, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000010, 0xba9a2c03, + 0x00000008, 0x0f800004, + 0x00000018, 0x8000fffc, + 0x00000000, 0x25960000, + 0x0000000c, 0x29800000, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000005, 0x73662c00, + 0x00000000, 0x31e32e00, + 0x00000008, 0x2d800010, + 0x00000018, 0x8000ff80, + 0x00000000, 0x23000000, + 0x00000009, 0x25e6ffff, + 0x00000008, 0x2200000b, + 0x0000000c, 0x69520000, + 0x0000000c, 0x29800000, + 0x00000018, 0x8000ff7a, + 0x00000018, 0x8000ff79, + 0x00000000, 0x2a000000, + 0x00000018, 0x8000ff77, + 0x00000008, 0x06660001, + 0x00000010, 0xba9a19f6, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0c000000, + 0x00000000, 0x0b800000, + 0x00000008, 0x0cc60012, + 0x00000018, 0x8000ffa0, + 0x00000008, 0x0f800003, + 0x00000000, 0x00000000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000008, 0x27110012, + 0x00000000, 0x66900000, + 0x00000010, 0x919b3200, + 0x00000010, 0x02930000, + 0x00000010, 0xb1980003, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000008, 0x0f800004, + 0x0000000c, 0x29800000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000010, 0xba9a2c00, + 0x00000000, 0x31e32e00, + 0x00000000, 0x0b800000, + 0x00000000, 0x8ccc8c00, + 0x00000010, 0xb5cc8c02, + 0x00000008, 0x0c800001, + 0x00000018, 0x8000ff8a, + 0x00000008, 0x0f800003, + 0x00000010, 0x20530000, + 0x0000000c, 0x69520001, + 0x00000000, 0x22c58c00, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x27110000, + 0x00000000, 0x26900000, + 0x00000000, 0x231b0000, + 0x00000010, 0xb1980003, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000008, 0x0f800004, + 0x00000008, 0x22000003, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d00000c, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x25960000, + 0x0000000c, 0x29800000, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000005, 0x73662c00, + 0x00000000, 0x31e32e00, + 0x00000008, 0x2d800010, + 0x00000018, 0x8000ff3e, + 0x00000000, 0x02700000, + 0x00000000, 0x0d620000, + 0x00000000, 0xbc630800, + 0x00000000, 0x2a000000, + 0x00000009, 0x076000ff, + 0x0000000f, 0x2c0e0007, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d00006a, + 0x00000008, 0x2d800116, + 0x0000000c, 0x61420001, + 0x00000000, 0x05780000, + 0x00000010, 0x0ce70002, + 0x00000003, 0x85721400, + 0x00000000, 0x3c8a0000, + 0x00000000, 0x02d08c00, + 0x00000000, 0x23000000, + 0x00000004, 0x826da000, + 0x00000000, 0x8304a000, + 0x00000000, 0x22c50c00, + 0x00000010, 0x91ed0802, + 0x00000003, 0xbcf80a00, + 0x00000010, 0x0d67000a, + 0x00000010, 0x24c20007, + 0x00000010, 0x01c20008, + 0x0000000c, 0x61420003, + 0x00000010, 0xb96f0856, + 0x00000010, 0xb7ef0a03, + 0x0000000c, 0x21420003, + 0x00000018, 0x80000003, + 0x00000018, 0x80000047, + 0x00000018, 0x80000051, + 0x00000004, 0x83790800, + 0x00000004, 0x83860a00, + 0x00000000, 0x83870c00, + 0x00000010, 0x91de0000, + 0x00000009, 0x057affff, + 0x00000010, 0x918a0002, + 0x00000008, 0x3d7affff, + 0x00000018, 0x8000ff12, + 0x00000001, 0x057a1400, + 0x00000010, 0x918a0002, + 0x00000008, 0xbd7a0001, + 0x00000000, 0x037c0000, + 0x00000000, 0x837b0c00, + 0x00000001, 0x83060e00, + 0x00000000, 0x83870c00, + 0x00000000, 0x82850e00, + 0x00000010, 0xb186000e, + 0x0000000f, 0x47610018, + 0x00000000, 0x068e0000, + 0x0000000f, 0x47670010, + 0x0000000f, 0x45620010, + 0x00000000, 0x870e1400, + 0x00000010, 0xb70e1a08, + 0x00000010, 0x0ce70006, + 0x00000010, 0x0ce70003, + 0x00000000, 0x056d0000, + 0x00000018, 0x8000022b, + 0x00000000, 0x37ed0000, + 0x0000000c, 0x73e7001a, + 0x00000003, 0x82f90a00, + 0x00000004, 0x82840a00, + 0x00000010, 0xb1840a31, + 0x00000010, 0x2d67000a, + 0x00000010, 0xb96d0804, + 0x00000004, 0xb6ed0a00, + 0x00000000, 0x37ed0000, + 0x00000018, 0x80000030, + 0x00000000, 0x37040000, + 0x00000000, 0x37850000, + 0x0000000c, 0x33e7001a, + 0x00000018, 0x8000022d, + 0x00000018, 0x8000002b, + 0x00000010, 0xb96d0810, + 0x0000000c, 0x21420007, + 0x00000004, 0xb6ed0a00, + 0x00000000, 0x036d0000, + 0x00000004, 0xb76e0c00, + 0x00000010, 0x91ee0c25, + 0x00000004, 0xb6ef0c00, + 0x0000000c, 0x21420008, + 0x0000000c, 0x73e7001a, + 0x00000000, 0x37ed0000, + 0x00000010, 0x0ce70002, + 0x0000000c, 0x21420006, + 0x00000010, 0x0ee70003, + 0x0000000c, 0x21420002, + 0x0000000c, 0x73e7001d, + 0x00000018, 0x8000001b, + 0x00000010, 0xb7ee0a06, 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0x00000003, 0xf66c2400, + 0x00000010, 0xb1923607, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000008, 0x0f800004, + 0x00000000, 0x00000000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x3e170000, + 0x00000000, 0x3e940000, + 0x00000000, 0x3f150000, + 0x00000000, 0x3f960000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x0f060000, + 0x00000010, 0x20530000, + 0x00000000, 0x22c53600, + 0x00000018, 0x8000fe79, + 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x0f008000, + 0x00000008, 0x0f800007, + 0x00000018, 0x8000001c, + 0x00000000, 0x280a0000, + 0x00000000, 0x05020000, + 0x00000008, 0x22000009, + 0x00000000, 0x29000000, + 0x0000000f, 0x65680010, + 0x00000000, 0x248a0000, + 0x00000003, 0xf66c9400, + 0x00000010, 0xb972a004, + 0x0000000c, 0x73e70019, + 0x0000000c, 0x21420004, + 0x00000000, 0x3cf80000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000008, 0x22000008, + 0x0000000c, 0x61420004, + 0x00000018, 0x000a0000, + 0x00000000, 0x05020000, + 0x0000000c, 0x61420000, + 0x00000010, 0x01420003, + 0x0000000c, 0x33e7001d, + 0x0000000c, 0x61420002, + 0x00000018, 0x000a0000, + 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x0000000f, 0x0f470007, + 0x00000008, 0x0f800008, + 0x0000000c, 0x29800000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000018, 0x8000fcbb, + 0x00000000, 0x33510000, + 0x00000000, 0x2a000000, + 0x00000010, 0xb1c60025, + 0x0000000f, 0x0f500007, + 0x00000000, 0x0a600000, + 0x00000000, 0x0ae10000, + 0x0000000f, 0x4b620008, + 0x00000009, 0x0b1600ff, + 0x0000000f, 0x4c620010, + 0x00000000, 0x0d620000, + 0x00000009, 0x0d1a00ff, + 0x00000010, 0x07500003, + 0x0000000c, 0x0d1a0008, + 0x0000000c, 0x0b160008, + 0x00000000, 0x0cc60000, + 0x00000000, 0x0b800000, + 0x00000000, 0x06980000, + 0x00000008, 0x0f800003, + 0x00000010, 0x06c20004, + 0x0000000c, 0x29000002, + 0x00000010, 0x26420002, + 0x0000000c, 0x29520003, + 0x00000008, 0x22000001, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x231b0000, + 0x00000000, 0x27111a00, + 0x00000000, 0x66900000, + 0x0000000c, 0x29520000, + 0x00000010, 0xb197320a, + 0x0000000c, 0x29800000, + 0x00000000, 0x06980000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520003, + 0x00000000, 0x22c58c00, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000008, 0x0f800003, + 0x00000018, 0x8000fff1, + 0x00000010, 0xb1c80013, + 0x00000010, 0xb1c60003, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520000, + 0x0000000c, 0x29520003, + 0x00000010, 0x06c20002, + 0x0000000c, 0x29520002, + 0x00000000, 0x22c58c00, + 0x00000000, 0x27650000, + 0x00000000, 0x26e40000, + 0x00000008, 0x22000016, + 0x00000010, 0xb1c60003, + 0x00000000, 0x23480000, + 0x00000010, 0xb1800005, + 0x00000000, 0x23480000, + 0x0000000c, 0x29800000, + 0x0000000f, 0x0f500007, + 0x00000018, 0x80000012, + 0x00000008, 0x22000016, + 0x0000000c, 0x29800000, + 0x00000000, 0x30140000, + 0x00000000, 0x30950000, + 0x00000010, 0x07500003, + 0x00000009, 0x0b1600ff, + 0x00000009, 0x0d1a00ff, + 0x0000000f, 0x31160008, + 0x00000000, 0x31623400, + 0x00000003, 0xf1623000, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c510000, + 0x00000009, 0x2cd1007f, + 0x00000008, 0x2cd90000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d80000c, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000010, 0x05c20005, + 0x00000008, 0x0f800007, + 0x00000000, 0x33000000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000018, 0x8000fc69, + 0x00000000, 0x2a000000, + 0x0000000f, 0x0f500007, + 0x00000010, 0xb1c60030, + 0x0000000f, 0x47420008, + 0x00000009, 0x070e000f, + 0x00000008, 0x070e0008, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000008, 0x09000001, + 0x00000007, 0x09121c00, + 0x00000003, 0xcbca9200, + 0x00000000, 0x0b97a200, + 0x00000007, 0x42171c00, + 0x00000000, 0x0b040000, + 0x0000000f, 0x0a840003, + 0x00000000, 0x0a959c00, + 0x00000000, 0x4a009a00, + 0x00000008, 0x82120001, + 0x00000001, 0x0c170800, + 0x00000000, 0x0c978c00, + 0x00000000, 0x02180000, + 0x00000008, 0x0d00ffff, + 0x00000008, 0x0f800006, + 0x0000000c, 0x29000000, + 0x00000010, 0x06c20004, + 0x0000000c, 0x29520002, + 0x00000010, 0x26420002, + 0x0000000c, 0x29520003, + 0x00000008, 0x22000001, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000010, 0xb197320d, + 0x00000000, 0x231b0000, + 0x00000000, 0x27110800, + 0x00000000, 0x66900000, + 0x0000000c, 0x29800000, + 0x00000000, 0x02180000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520003, + 0x00000000, 0x22c53600, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000008, 0x0f800006, + 0x00000018, 0x8000fff2, + 0x00000000, 0x231b0000, + 0x00000000, 0x27110800, + 0x00000000, 0x66900000, + 0x00000010, 0xb1c8000b, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520000, + 0x0000000c, 0x29520003, + 0x00000010, 0x06c20002, + 0x0000000c, 0x29520002, + 0x00000000, 0x22c58c00, + 0x00000000, 0x27650000, + 0x00000000, 0x26e40000, + 0x00000000, 0x23480000, + 0x00000008, 0x22000017, + 0x0000000c, 0x29800000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000018, 0x8000fc2a, +}; +/* Calling this macro prior to loading will change value of MAX_BD_PAGE (default = 0xff)*/ +#define XI90_RV2P_PROC2_MAX_BD_PAGE_LOC 5 +#define XI90_RV2P_PROC2_CHG_MAX_BD_PAGE(value) {\ + xi90_rv2p_proc2[XI90_RV2P_PROC2_MAX_BD_PAGE_LOC] = (xi90_rv2p_proc2[XI90_RV2P_PROC2_MAX_BD_PAGE_LOC] & ~0xFFFF) | (value);\ +} + +/* Calling this macro prior to loading will change value of GEN_IND_SIZE (default = 0x1)*/ +#define XI90_RV2P_PROC2_GEN_IND_SIZE_LOC 9 +#define XI90_RV2P_PROC2_CHG_GEN_IND_SIZE(value) {\ + xi90_rv2p_proc2[XI90_RV2P_PROC2_GEN_IND_SIZE_LOC] = (xi90_rv2p_proc2[XI90_RV2P_PROC2_GEN_IND_SIZE_LOC] & ~0xFFFF) | (value);\ +} + +#endif /* __xi90_rv2p_proc2.h__ */ + diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/xi_rv2p_p1.h b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/xi_rv2p_p1.h new file mode 100644 index 0000000000..d403c6bc25 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/xi_rv2p_p1.h @@ -0,0 +1,502 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __xi_rv2p_proc1_h__ +#define __xi_rv2p_proc1_h__ +#include "bcmtype.h" + +u32_t xi_rv2p_proc1[] = { + 0x00000010, 0xb1800006, + 0x0000001f, 0x05060201, + 0x00000008, 0x05000000, + 0x00000018, 0x00020000, + 0x00000008, 0x050000ff, + 0x00000018, 0x00020000, + 0x00000008, 0xac000001, + 0x00000008, 0x07800000, + 0x0000000c, 0x2f800001, + 0x00000000, 0x2b000000, + 0x00000000, 0x2b800000, + 0x00000010, 0x91e10002, + 0x00000008, 0xac000001, + 0x00000010, 0x203f0058, + 0x00000010, 0x213f0003, + 0x00000010, 0x20bf0032, + 0x00000018, 0x8000fffd, + 0x00000008, 0x03800800, + 0x00000010, 0xb6380e01, + 0x00000010, 0xb1b8b00d, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c380000, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000006e, + 0x00000018, 0x80000145, + 0x00000008, 0x02000002, + 0x0000000f, 0x42e0001c, + 0x00000010, 0x91840a11, + 0x00000010, 0x2c62000b, + 0x00000018, 0x8000001b, + 0x00000008, 0x02000002, + 0x0000000f, 0x42e0001c, + 0x00000010, 0x91840a16, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800108, + 0x00000018, 0x80000074, + 0x00000018, 0x80000012, + 0x00000008, 0xb1000001, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800001, + 0x00000018, 0x80000061, + 0x0000000b, 0x2fdf0002, + 0x0000000c, 0x1f800002, + 0x00000000, 0x2c070000, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000ffd9, + 0x0000000b, 0x2fdf0002, + 0x0000000c, 0x1f800000, + 0x00000000, 0x2c070000, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000ffd4, + 0x0000000c, 0x1f800002, + 0x00000018, 0x8000ffd2, + 0x00000010, 0x0ce70002, + 0x00000010, 0x2ce20046, + 0x0000000c, 0x29800002, + 0x0000000c, 0x1f800002, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000005, + 0x00000018, 0x8000ffcb, + 0x00000008, 0x02240042, + 0x00000018, 0x00040000, + 0x00000018, 0x80000000, + 0x00000018, 0x8000001b, + 0x00000018, 0x80000060, + 0x00000018, 0x800000a0, + 0x00000018, 0x800000da, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000126, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x800000f0, + 0x00000018, 0x80000000, + 0x00000018, 0x80000125, + 0x00000018, 0x8000014f, + 0x00000018, 0x8000011c, + 0x00000018, 0x80000172, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000002, + 0x00000008, 0x07800000, + 0x00000018, 0x8000ffa7, + 0x00000008, 0x03800100, + 0x00000010, 0xb73c0e00, + 0x00000010, 0xb1bcb00a, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c3c0000, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000001a, + 0x00000018, 0x800000f1, + 0x00000010, 0x2c6201c4, + 0x00000018, 0x80000006, + 0x00000008, 0x2c80010d, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x00000018, 0x80000026, + 0x0000000c, 0x29800000, + 0x0000000c, 0x1f800000, + 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, + 0x00000010, 0x2e670005, + 0x00000010, 0x0ce20004, + 0x00000018, 0x80000005, + 0x00000008, 0x2a000011, + 0x00000018, 0x80000002, + 0x00000008, 0x2a000006, + 0x00000018, 0x8000ff8b, + 0x0000000c, 0x71620019, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800001, + 0x00000018, 0x00020000, + 0x00000018, 0x00020000, + 0x00000000, 0x06820000, + 0x00000010, 0xb18f0004, + 0x00000010, 0xb18f1403, + 0x00000008, 0x2a000001, + 0x00000010, 0x91d40000, + 0x00000000, 0x07801400, + 0x00000018, 0x000d0000, + 0x00000000, 0x05020000, + 0x00000010, 0x91de0000, + 0x00000018, 0x000a0000, + 0x00000000, 0x06820000, + 0x00000010, 0x91de0000, + 0x00000009, 0x0561ffff, + 0x00000010, 0x918a0002, + 0x00000008, 0x30e1ffff, + 0x00000018, 0x8000ff6e, + 0x00000001, 0x05611400, + 0x00000010, 0x918a0002, + 0x00000008, 0xb0e10001, + 0x00000018, 0x000d0000, + 0x00000000, 0x06820000, + 0x00000010, 0x91de0000, + 0x00000009, 0x0562ffff, + 0x00000010, 0x918a0002, + 0x00000008, 0x3162ffff, + 0x00000018, 0x8000ff64, + 0x00000001, 0x05621400, + 0x00000010, 0x918a0002, + 0x00000008, 0xb1620001, + 0x00000018, 0x000d0000, + 0x00000010, 0xb1a0b013, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000ffdb, + 0x00000008, 0x2d80011c, + 0x00000010, 0x001f0000, + 0x00000018, 0x8000ffe2, + 0x0000000f, 0x47600008, + 0x0000000f, 0x060e0001, + 0x00000000, 0x0f580000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0d610000, + 0x00000018, 0x80000015, + 0x0000000f, 0x47600008, + 0x0000000b, 0x2fdf0002, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d80011c, + 0x0000000f, 0x060e0001, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f580000, + 0x00000018, 0x8000ffd0, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0d610000, + 0x00000000, 0x02620000, + 0x00000000, 0x02e00000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x30050000, + 0x00000000, 0x31040000, + 0x00000000, 0x309a0000, + 0x00000010, 0x0060000c, + 0x00000010, 0x21a2000b, + 0x00000010, 0xb1a6000a, + 0x00000008, 0x05160001, + 0x00000010, 0xba9a1403, + 0x00000000, 0x03000000, + 0x00000018, 0x80000006, + 0x00000018, 0x8000ff2f, + 0x00000010, 0xb6061404, + 0x00000008, 0x03060001, + 0x00000008, 0x2a000001, + 0x00000018, 0x8000ff34, + 0x00000000, 0x0c961800, + 0x00000009, 0x0c99ffff, + 0x00000004, 0xcc993400, + 0x00000010, 0xba992c02, + 0x00000008, 0x0f800000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x29520001, + 0x0000000c, 0x29520000, + 0x00000008, 0x22800002, + 0x00000008, 0x02000003, + 0x0000000c, 0x1f800001, + 0x00000000, 0x2adf0000, + 0x00000000, 0x2a000800, + 0x00000018, 0x8000ff26, + 0x00000010, 0xb1a0b016, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000ff9c, + 0x00000018, 0x80000073, + 0x0000000f, 0x47600008, + 0x00000000, 0x060e0000, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f580000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000000, 0x0b670000, + 0x00000000, 0x0d620000, + 0x00000000, 0x0ce71800, + 0x00000009, 0x0c99ffff, + 0x00000004, 0xcc993400, + 0x00000010, 0xba992c20, + 0x00000008, 0x0f800000, + 0x00000018, 0x8000001e, + 0x0000000f, 0x47600008, + 0x0000000b, 0x2fdf0002, + 0x00000008, 0x2c80010d, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d80012b, + 0x0000000f, 0x060e0001, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f580000, + 0x00000018, 0x8000ff96, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000000, 0x0b670000, + 0x00000000, 0x0d620000, + 0x00000000, 0x02630000, + 0x0000000f, 0x47620010, + 0x00000000, 0x0ce71800, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x31840000, + 0x00000000, 0x311a0000, + 0x0000000b, 0xc20000ff, + 0x00000002, 0x42040000, + 0x00000001, 0x31620800, + 0x0000000f, 0x020e0010, + 0x00000002, 0x31620800, + 0x00000009, 0x0c99ffff, + 0x00000004, 0xcc993400, + 0x00000010, 0xba992c02, + 0x00000008, 0x0f800000, + 0x00000010, 0x2ce20168, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x0000000c, 0x61420006, + 0x00000008, 0x22000008, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000004, + 0x00000018, 0x8000feeb, + 0x00000010, 0x91a0b009, + 0x00000008, 0x2c80010d, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x00000018, 0x8000ff75, + 0x00000018, 0x8000000f, + 0x00000008, 0xac000001, + 0x00000018, 0x8000000b, + 0x00000000, 0x0380b000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c004000, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000ff58, + 0x00000018, 0x8000002f, + 0x00000018, 0x80000005, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c000e00, + 0x00000008, 0x2a000007, + 0x00000018, 0x8000fed6, + 0x00000000, 0x06820000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000010, 0x0ce70007, + 0x00000009, 0x0562ffff, + 0x00000010, 0xba6c1405, + 0x00000000, 0x2adf0000, + 0x00000000, 0x21000000, + 0x00000008, 0x2a000005, + 0x00000010, 0x91d40000, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x0000000c, 0x31620018, + 0x00000008, 0x2d800001, + 0x00000018, 0x8000ff4a, + 0x00000018, 0x000d0000, + 0x00000010, 0xb1a0b00d, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c200000, + 0x00000010, 0x91d40000, + 0x00000018, 0x80000014, + 0x00000010, 0x2c620002, + 0x00000018, 0x8000000b, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c070000, + 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000feb9, + 0x00000008, 0x2c80010d, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x00000018, 0x8000ff44, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000a, + 0x00000008, 0x07800000, + 0x00000018, 0x8000fead, + 0x00000000, 0x06820000, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800134, + 0x00000000, 0x00000000, + 0x00000010, 0x205f0000, + 0x00000008, 0x2c800140, + 0x00000008, 0x2d00003c, + 0x00000008, 0x2d80011c, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000008, 0x2c800080, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d800105, + 0x00000009, 0x0562ffff, + 0x00000010, 0x918a0002, + 0x00000008, 0x3162ffff, + 0x00000018, 0x8000fe94, + 0x00000001, 0x05621400, + 0x00000010, 0x918a0002, + 0x00000008, 0xb1620001, + 0x00000010, 0x91de0000, + 0x00000018, 0x000d0000, + 0x00000010, 0x91d40000, + 0x00000008, 0x050000aa, + 0x00000018, 0x8000ff0f, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000009, + 0x00000018, 0x8000fe8f, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000ff08, + 0x00000010, 0x91a0b002, + 0x00000010, 0xb1e66207, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c310000, + 0x00000009, 0x2cb1007f, + 0x00000008, 0x2cd90000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d80010d, + 0x00000010, 0xb1a80006, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c200000, + 0x00000000, 0x2ca70000, + 0x00000008, 0x2d000010, + 0x00000008, 0x2d800108, + 0x00000018, 0x8000ff00, + 0x00000010, 0xb1a60010, + 0x00000010, 0x001f0000, + 0x0000000f, 0x0f300007, + 0x00000000, 0x0a600000, + 0x00000000, 0x0ae10000, + 0x0000000f, 0x4b620008, + 0x00000009, 0x0b1600ff, + 0x00000000, 0x0d620000, + 0x00000009, 0x0d1a00ff, + 0x00000010, 0x07300003, + 0x0000000c, 0x0d1a0008, + 0x0000000c, 0x0b160008, + 0x0000000f, 0x4ce30018, + 0x00000000, 0x0c992c00, + 0x00000004, 0xcc993400, + 0x00000008, 0x0f800000, + 0x0000000c, 0x29800001, + 0x00000000, 0x33310000, + 0x00000008, 0x22000016, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000c, + 0x00000010, 0x009f0000, + 0x00000000, 0x2c200000, + 0x0000000c, 0x1f800001, + 0x00000018, 0x8000fe64, + 0x00000010, 0x91d40000, + 0x00000008, 0x050000aa, + 0x00000018, 0x8000fedd, + 0x0000000f, 0x47220008, + 0x00000009, 0x070e000f, + 0x00000008, 0x070e0008, + 0x00000008, 0x02800001, + 0x00000007, 0x02851c00, + 0x00000008, 0x82850001, + 0x00000000, 0x02854c00, + 0x00000007, 0x42851c00, + 0x00000003, 0xc3aa5200, + 0x00000000, 0x03b10e00, + 0x00000007, 0x4b071c00, + 0x0000000f, 0x0f300007, + 0x0000000f, 0x0a960003, + 0x00000000, 0x0a955c00, + 0x00000000, 0x4a005a00, + 0x00000000, 0x0c960a00, + 0x00000009, 0x0c99ffff, + 0x00000008, 0x0d00ffff, + 0x00000010, 0xba992c02, + 0x00000008, 0x0f800005, + 0x00000010, 0xb1a80008, + 0x00000010, 0x205f0000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, + 0x00000000, 0x2ca70000, + 0x00000008, 0x2d000010, + 0x00000008, 0x2d800108, + 0x00000018, 0x8000fec8, + 0x0000000c, 0x29800001, + 0x00000010, 0x001f0000, + 0x0000000c, 0x1f800001, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000d, + 0x00000018, 0x8000fe3f, + 0x00000010, 0x91d40000, + 0x00000008, 0x05000055, + 0x00000018, 0x8000feb8, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000007, + 0x00000018, 0x8000fe38, +}; +/* Calling this macro prior to loading will change value of POST_WAIT_TIMEOUT (default = 0x0)*/ +#define XI_RV2P_PROC1_POST_WAIT_TIMEOUT_LOC 5 +#define XI_RV2P_PROC1_CHG_POST_WAIT_TIMEOUT(value) {\ + xi_rv2p_proc1[XI_RV2P_PROC1_POST_WAIT_TIMEOUT_LOC] = (xi_rv2p_proc1[XI_RV2P_PROC1_POST_WAIT_TIMEOUT_LOC] & ~0xFFFF) | (value);\ +} + +/* Calling this macro prior to loading will change value of MAX_BD_PAGE (default = 0xff)*/ +#define XI_RV2P_PROC1_MAX_BD_PAGE_LOC 9 +#define XI_RV2P_PROC1_CHG_MAX_BD_PAGE(value) {\ + xi_rv2p_proc1[XI_RV2P_PROC1_MAX_BD_PAGE_LOC] = (xi_rv2p_proc1[XI_RV2P_PROC1_MAX_BD_PAGE_LOC] & ~0xFFFF) | (value);\ +} + +#endif /* __xi_rv2p_proc1.h__ */ + diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/xi_rv2p_p2.h b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/xi_rv2p_p2.h new file mode 100644 index 0000000000..5c31f18d5a --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/xi_rv2p_p2.h @@ -0,0 +1,975 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __xi_rv2p_proc2_h__ +#define __xi_rv2p_proc2_h__ +#include "bcmtype.h" + +u32_t xi_rv2p_proc2[] = { + 0x00000010, 0xb1800006, + 0x0000001f, 0x05060201, + 0x00000008, 0x050000ff, + 0x00000018, 0x00020000, + 0x00000008, 0x05000001, + 0x00000018, 0x00020000, + 0x00000000, 0x2a000000, + 0x00000010, 0xb1d40000, + 0x00000010, 0x91de0000, + 0x00000010, 0x20530000, + 0x00000010, 0x001f0000, + 0x00000000, 0x2f80aa00, + 0x0000000c, 0x29800001, + 0x00000008, 0x02540011, + 0x00000000, 0x2c400000, + 0x00000000, 0x0f400000, + 0x00000009, 0x2952003f, + 0x00000018, 0x00040000, + 0x00000018, 0x80000011, + 0x00000018, 0x80000012, + 0x00000018, 0x80000038, + 0x00000018, 0x8000009b, + 0x00000018, 0x800001c1, + 0x00000018, 0x80000204, + 0x00000018, 0x800002e9, + 0x00000018, 0x80000000, + 0x00000018, 0x80000302, + 0x00000018, 0x800001b6, + 0x00000018, 0x80000000, + 0x00000018, 0x80000306, + 0x00000018, 0x80000354, + 0x00000018, 0x8000005b, + 0x00000018, 0x8000005b, + 0x00000018, 0x8000005c, + 0x00000018, 0x800001d5, + 0x00000000, 0x2a000000, + 0x00000018, 0x8000ffe3, + 0x00000000, 0x2a000000, + 0x0000000c, 0x29800000, + 0x00000018, 0x8000ffe0, + 0x00000018, 0x00020000, + 0x00000000, 0x05020000, + 0x00000010, 0xb99a2c21, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d000006, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d610000, + 0x00000018, 0x000a0000, + 0x00000000, 0x05020000, + 0x00000010, 0xb99a2c16, + 0x00000010, 0x205f0000, + 0x00000000, 0x09d80000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c80010e, + 0x00000008, 0x2d00000a, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d620000, + 0x00000000, 0x2c130000, + 0x00000018, 0x000a0000, + 0x00000000, 0x05020000, + 0x00000010, 0xb99a2c09, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d00006a, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d7a0000, + 0x00000018, 0x000a0000, + 0x00000000, 0x2a000000, + 0x00000008, 0x22000001, + 0x00000000, 0x0d610000, + 0x00000010, 0x21c20025, + 0x00000010, 0xb1c60002, + 0x00000010, 0x2342002c, + 0x00000009, 0x0b66ffff, + 0x00000010, 0xba9a2c21, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000000, 0x0c000000, + 0x00000000, 0x0b800000, + 0x00000008, 0x0cc60012, + 0x00000018, 0x8000ffd0, + 0x00000008, 0x0f800003, + 0x00000000, 0x00000000, + 0x00000010, 0x009f0000, + 0x00000010, 0x919b3200, + 0x00000008, 0x27110012, + 0x00000000, 0x66900000, + 0x00000010, 0xb1980003, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800004, + 0x00000008, 0x22000003, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d00000c, + 0x00000010, 0x009f0000, + 0x00000010, 0x91c60005, + 0x00000010, 0x001f0000, + 0x00000010, 0xba9a2c03, + 0x00000008, 0x0f800004, + 0x00000018, 0x8000fffd, + 0x00000000, 0x25960000, + 0x0000000c, 0x29800000, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000005, 0x73662c00, + 0x00000000, 0x31e32e00, + 0x00000008, 0x2d800010, + 0x00000018, 0x8000ff94, + 0x00000000, 0x23000000, + 0x00000009, 0x25e6ffff, + 0x00000008, 0x2200000b, + 0x0000000c, 0x69520000, + 0x0000000c, 0x29800000, + 0x00000018, 0x8000ff8e, + 0x00000018, 0x8000ff8d, + 0x00000000, 0x2a000000, + 0x00000018, 0x8000ff8b, + 0x00000008, 0x06660001, + 0x00000010, 0xba9a19f6, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0c000000, + 0x00000000, 0x0b800000, + 0x00000008, 0x0cc60012, + 0x00000018, 0x8000ffa4, + 0x00000008, 0x0f800003, + 0x00000000, 0x00000000, + 0x00000010, 0x009f0000, + 0x00000008, 0x27110012, + 0x00000000, 0x66900000, + 0x00000010, 0x919b3200, + 0x00000010, 0x02930000, + 0x00000010, 0xb1980003, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800004, + 0x0000000c, 0x29800000, + 0x00000010, 0x001f0000, + 0x00000010, 0xba9a2c00, + 0x00000000, 0x31e32e00, + 0x00000000, 0x0b800000, + 0x00000000, 0x8ccc8c00, + 0x00000010, 0xb5cc8c02, + 0x00000008, 0x0c800001, + 0x00000018, 0x8000ff91, + 0x00000008, 0x0f800003, + 0x00000010, 0x20530000, + 0x0000000c, 0x69520001, + 0x00000000, 0x22c58c00, + 0x00000010, 0x009f0000, + 0x00000000, 0x27110000, + 0x00000000, 0x26900000, + 0x00000000, 0x231b0000, + 0x00000010, 0xb1980003, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800004, + 0x00000008, 0x22000003, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d00000c, + 0x00000010, 0x009f0000, + 0x00000000, 0x25960000, + 0x0000000c, 0x29800000, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000005, 0x73662c00, + 0x00000000, 0x31e32e00, + 0x00000008, 0x2d800010, + 0x00000018, 0x8000ff58, + 0x00000000, 0x02700000, + 0x00000000, 0x0d620000, + 0x00000000, 0xbc630800, + 0x00000000, 0x2a000000, + 0x00000009, 0x076000ff, + 0x0000000f, 0x2c0e0007, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d00006a, + 0x00000008, 0x2d800116, + 0x0000000c, 0x61420001, + 0x00000000, 0x05780000, + 0x00000010, 0x0ce70002, + 0x00000003, 0x85721400, + 0x00000000, 0x3c8a0000, + 0x00000000, 0x02d08c00, + 0x00000000, 0x23000000, + 0x00000004, 0x826da000, + 0x00000000, 0x8304a000, + 0x00000000, 0x22c50c00, + 0x00000010, 0x91ed0802, + 0x00000003, 0xbcf80a00, + 0x00000010, 0x0d67000a, + 0x00000010, 0x24c20007, + 0x00000010, 0x01c20008, + 0x0000000c, 0x61420003, + 0x00000010, 0xb96f0856, + 0x00000010, 0xb7ef0a03, + 0x0000000c, 0x21420003, + 0x00000018, 0x80000003, + 0x00000018, 0x80000047, + 0x00000018, 0x80000051, + 0x00000004, 0x83790800, + 0x00000004, 0x83860a00, + 0x00000000, 0x83870c00, + 0x00000010, 0x91de0000, + 0x00000009, 0x057affff, + 0x00000010, 0x918a0002, + 0x00000008, 0x3d7affff, + 0x00000018, 0x8000ff2c, + 0x00000001, 0x057a1400, + 0x00000010, 0x918a0002, + 0x00000008, 0xbd7a0001, + 0x00000000, 0x037c0000, + 0x00000000, 0x837b0c00, + 0x00000001, 0x83060e00, + 0x00000000, 0x83870c00, + 0x00000000, 0x82850e00, + 0x00000010, 0xb186000e, + 0x0000000f, 0x47610018, + 0x00000000, 0x068e0000, + 0x0000000f, 0x47670010, + 0x0000000f, 0x45620010, + 0x00000000, 0x870e1400, + 0x00000010, 0xb70e1a08, + 0x00000010, 0x0ce70006, + 0x00000010, 0x0ce70003, + 0x00000000, 0x056d0000, + 0x00000018, 0x8000021d, + 0x00000000, 0x37ed0000, + 0x0000000c, 0x73e7001a, + 0x00000003, 0x82f90a00, + 0x00000004, 0x82840a00, + 0x00000010, 0xb1840a31, + 0x00000010, 0x2d67000a, + 0x00000010, 0xb96d0804, + 0x00000004, 0xb6ed0a00, + 0x00000000, 0x37ed0000, + 0x00000018, 0x80000030, + 0x00000000, 0x37040000, + 0x00000000, 0x37850000, + 0x0000000c, 0x33e7001a, + 0x00000018, 0x8000021f, + 0x00000018, 0x8000002b, + 0x00000010, 0xb96d0810, + 0x0000000c, 0x21420007, + 0x00000004, 0xb6ed0a00, + 0x00000000, 0x036d0000, + 0x00000004, 0xb76e0c00, + 0x00000010, 0x91ee0c25, + 0x00000004, 0xb6ef0c00, + 0x0000000c, 0x21420008, + 0x0000000c, 0x73e7001a, + 0x00000000, 0x37ed0000, + 0x00000010, 0x0ce70002, + 0x0000000c, 0x21420006, + 0x00000010, 0x0ee70003, + 0x0000000c, 0x21420002, + 0x0000000c, 0x73e7001d, + 0x00000018, 0x8000001b, + 0x00000010, 0xb7ee0a06, + 0x00000010, 0xb96f0815, + 0x00000003, 0xb76e0800, + 0x00000004, 0xb7ef0a00, + 0x00000018, 0x80000209, + 0x00000018, 0x80000015, + 0x00000018, 0x80000005, + 0x0000000c, 0x33e7001a, + 0x00000000, 0x37040000, + 0x00000000, 0x37850000, + 0x00000018, 0x80000010, + 0x00000000, 0x06020000, + 0x0000000c, 0x73e7001d, + 0x00000010, 0x0ce70003, + 0x00000000, 0x056d0000, + 0x00000018, 0x800001ee, + 0x0000000c, 0x73e7001a, + 0x00000000, 0x37ed0000, + 0x00000000, 0x056d0000, + 0x00000003, 0xb8f11400, + 0x00000018, 0x800001f9, + 0x00000018, 0x000c0000, + 0x00000000, 0x02840000, + 0x0000000c, 0x21420001, + 0x0000000c, 0x61420000, + 0x00000000, 0x25020000, + 0x00000000, 0x286d0000, + 0x0000000f, 0x65ed0010, + 0x00000009, 0x266dffff, + 0x00000000, 0x23000000, + 0x00000010, 0xb1840a47, + 0x00000010, 0x01420002, + 0x00000004, 0xb8f10a00, + 0x00000003, 0x83790a00, + 0x00000010, 0xb8040c43, + 0x00000010, 0xb7e6080a, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0c68ffff, + 0x00000009, 0x0b67ffff, + 0x00000000, 0x0be60000, + 0x00000000, 0x0c840000, + 0x00000010, 0xb197320c, + 0x00000008, 0x0f800002, + 0x00000018, 0x8000000a, + 0x00000000, 0x0a6a0000, + 0x00000000, 0x0aeb0000, + 0x00000000, 0x0c000000, + 0x00000009, 0x0b6cffff, + 0x00000000, 0x0be90000, + 0x00000000, 0x0c840000, + 0x00000010, 0xb1973203, + 0x00000008, 0x0f800002, + 0x00000000, 0x00000000, + 0x00000010, 0x001f0000, + 0x00000000, 0x0c860000, + 0x00000000, 0x06980000, + 0x00000018, 0x8000fef2, + 0x00000008, 0x0f800003, + 0x0000000f, 0x63ef0010, + 0x00000000, 0x246f0000, + 0x00000010, 0x009f0000, + 0x00000010, 0xb1973214, + 0x00000018, 0x8000feec, + 0x00000000, 0x231b0000, + 0x00000000, 0x28840000, + 0x00000000, 0x02043600, + 0x00000003, 0x8384a000, + 0x0000000f, 0x65870010, + 0x00000009, 0x2607ffff, + 0x00000000, 0x27111a00, + 0x00000000, 0x66900000, + 0x0000000c, 0x29520000, + 0x00000000, 0x24c60000, + 0x0000000c, 0x29800000, + 0x00000000, 0x06980000, + 0x00000010, 0x20530000, + 0x0000000c, 0x69520004, + 0x00000000, 0x22c58c00, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800003, + 0x00000018, 0x8000ffec, + 0x00000000, 0x02043600, + 0x00000000, 0x231b0000, + 0x00000000, 0x03840000, + 0x00000010, 0x91870a03, + 0x00000000, 0x03d00000, + 0x0000000c, 0x21420001, + 0x00000003, 0x8387a000, + 0x0000000f, 0x65870010, + 0x00000009, 0x2607ffff, + 0x00000000, 0x27111a00, + 0x00000000, 0x66900000, + 0x0000000c, 0x29520000, + 0x00000010, 0x03520002, + 0x0000000c, 0x69520006, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000005, 0x73e72c00, + 0x00000005, 0x74683000, + 0x00000000, 0x33170000, + 0x00000018, 0x800000be, + 0x00000010, 0x91c60006, + 0x00000008, 0x07000004, + 0x00000010, 0xb1c41c04, + 0x00000010, 0x21c20003, + 0x00000010, 0x91840a10, + 0x00000000, 0x28840000, + 0x00000010, 0x01c20009, + 0x00000000, 0x05580000, + 0x00000000, 0x2c400000, + 0x00000008, 0x2c800120, + 0x00000008, 0x2d00001c, + 0x00000008, 0x2d800020, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x2c0a0000, + 0x00000000, 0x24c60000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x0000000c, 0x61420003, + 0x00000000, 0x22c58c00, + 0x00000010, 0xb1840a29, + 0x0000000c, 0x21420006, + 0x00000010, 0x0ce70020, + 0x0000000f, 0x43680010, + 0x00000000, 0x03f30c00, + 0x00000003, 0xb9720800, + 0x00000010, 0x91870820, + 0x0000000f, 0x46ec0010, + 0x00000010, 0xb68d0c1e, + 0x00000000, 0x838d0c00, + 0x0000000f, 0x63ef0010, + 0x00000000, 0x246f0000, + 0x00000000, 0xa3050800, + 0x00000001, 0xa3460e00, + 0x00000000, 0x28840000, + 0x00000000, 0x02048c00, + 0x00000008, 0x22000008, + 0x00000000, 0x03840000, + 0x00000010, 0x91870a03, + 0x00000000, 0x03d00000, + 0x0000000c, 0x21420001, + 0x00000003, 0x8387a000, + 0x0000000f, 0x65870010, + 0x00000009, 0x2607ffff, + 0x00000000, 0x27750c00, + 0x00000000, 0x66f40000, + 0x0000000c, 0x29000000, + 0x00000000, 0x24c60000, + 0x0000000c, 0x29800000, + 0x00000000, 0x03068c00, + 0x00000003, 0xf4680c00, + 0x00000010, 0x20530000, + 0x00000000, 0x22c58c00, + 0x00000018, 0x8000ffdf, + 0x00000000, 0x39040000, + 0x0000000c, 0x33e70019, + 0x00000008, 0x22000006, + 0x00000018, 0x8000011e, + 0x0000000f, 0x65680010, + 0x00000008, 0x22000007, + 0x00000018, 0x8000011b, + 0x00000010, 0x0ce70005, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d000070, + 0x00000008, 0x2d800010, + 0x00000000, 0x00000000, + 0x00000010, 0x205f0000, + 0x00000018, 0x80000105, + 0x00000018, 0x8000000d, + 0x00000018, 0x8000fe53, + 0x00000000, 0x06800400, + 0x00000018, 0x8000000a, + 0x00000000, 0x05440000, + 0x00000003, 0xc50aa400, + 0x00000008, 0x22000012, + 0x00000008, 0x29000000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000009, 0x220affff, + 0x0000000f, 0x690a0010, + 0x00000018, 0x000d0000, + 0x00000000, 0x05020000, + 0x00000000, 0x2c400000, + 0x00000008, 0x2c800114, + 0x00000008, 0x2d000010, + 0x00000008, 0x2d80002c, + 0x00000000, 0x00000000, + 0x00000010, 0x205f0000, + 0x00000008, 0x2c800140, + 0x00000008, 0x2d00003c, + 0x00000008, 0x2d80001c, + 0x00000010, 0x0ce20006, + 0x00000010, 0x205f0000, + 0x0000000c, 0x71620019, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800001, + 0x00000018, 0x000a0000, + 0x00000000, 0x2a000000, + 0x00000018, 0x800000e5, + 0x00000008, 0x2c800120, + 0x00000008, 0x2d00001c, + 0x00000008, 0x2d800001, + 0x00000018, 0x8000fe31, + 0x00000000, 0x02700000, + 0x00000000, 0x0d620000, + 0x00000000, 0xbc630800, + 0x00000000, 0x2a000000, + 0x00000000, 0x0f400000, + 0x0000000c, 0x73e7001b, + 0x00000010, 0x0ce7000c, + 0x00000000, 0x286d0000, + 0x0000000f, 0x65ed0010, + 0x00000009, 0x266dffff, + 0x00000018, 0x8000004b, + 0x00000008, 0x02000004, + 0x00000010, 0x91c40803, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000018, 0x800000d1, + 0x00000018, 0x8000ffd9, + 0x00000018, 0x80000005, + 0x00000008, 0x2c800120, + 0x00000008, 0x2d00001c, + 0x00000008, 0x2d800001, + 0x00000000, 0x00000000, + 0x00000010, 0x205f0000, + 0x00000008, 0x2c8000b8, + 0x00000008, 0x2d000064, + 0x00000008, 0x2d800104, + 0x00000000, 0x27f80000, + 0x00000010, 0x91de0000, + 0x00000010, 0xb8799e03, + 0x00000008, 0x2200000d, + 0x0000000c, 0x29800000, + 0x00000018, 0x8000fe11, + 0x00000000, 0x02700000, + 0x00000000, 0x0d620000, + 0x00000000, 0xbc630800, + 0x00000000, 0x2a000000, + 0x00000010, 0x2ce70030, + 0x00000010, 0x2d67002f, + 0x00000000, 0x286d0000, + 0x0000000f, 0x65ed0010, + 0x00000009, 0x266dffff, + 0x00000000, 0x0f400000, + 0x00000008, 0x22000004, + 0x00000000, 0x28e90000, + 0x00000008, 0x2500dead, + 0x00000010, 0xb1f8a227, + 0x0000000c, 0x29800000, + 0x00000000, 0x0a6a0000, + 0x00000000, 0x0aeb0000, + 0x00000009, 0x0b6cffff, + 0x00000000, 0x0c000000, + 0x00000000, 0x0be90000, + 0x00000000, 0x0ce90000, + 0x0000000c, 0x09800002, + 0x00000008, 0x0f800004, + 0x00000000, 0x00000000, + 0x00000010, 0x009f0000, + 0x00000000, 0x83973200, + 0x00000000, 0x38700e00, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000005, 0x73e72c00, + 0x00000005, 0x74680000, + 0x00000000, 0x35140000, + 0x00000000, 0x35950000, + 0x00000005, 0x766c2c00, + 0x00000018, 0x8000ffa7, + 0x00000018, 0x8000fded, + 0x00000000, 0x02700000, + 0x00000000, 0x0d620000, + 0x00000000, 0xbc630800, + 0x00000000, 0x2a000000, + 0x00000000, 0x286d0000, + 0x0000000f, 0x65ed0010, + 0x00000009, 0x266dffff, + 0x00000000, 0x0f400000, + 0x00000010, 0x0e670008, + 0x0000000c, 0x73e7001c, + 0x00000004, 0xb8f1a000, + 0x00000018, 0x80000006, + 0x00000008, 0x02000004, + 0x00000010, 0x91c40802, + 0x0000000c, 0x29800000, + 0x00000018, 0x8000ff96, + 0x00000018, 0x8000fddc, + 0x00000000, 0x06820000, + 0x00000010, 0x001f0000, + 0x00000010, 0x0ce70031, + 0x00000000, 0x03720000, + 0x00000000, 0x0cf80000, + 0x00000003, 0x8ced3200, + 0x00000000, 0xa8190c00, + 0x00000010, 0xb872322c, + 0x00000000, 0x03ca0000, + 0x0000000f, 0x65680010, + 0x00000000, 0x0bcf0000, + 0x00000000, 0x27f20000, + 0x00000000, 0x28ed0000, + 0x00000004, 0xb9723200, + 0x00000010, 0x0d670004, + 0x00000000, 0x056d0000, + 0x00000010, 0x91f21402, + 0x00000000, 0x396e0000, + 0x00000000, 0x03720000, + 0x00000003, 0xbcf80c00, + 0x00000000, 0x03440000, + 0x00000008, 0x22000010, + 0x00000010, 0xb7ef3204, + 0x0000000c, 0x21420004, + 0x0000000c, 0x73e70019, + 0x00000000, 0x3cf80000, + 0x00000000, 0x07520000, + 0x00000000, 0x29000000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000000, 0x22060000, + 0x0000000c, 0x61420004, + 0x00000000, 0x25070000, + 0x00000000, 0x27970000, + 0x00000000, 0x28940000, + 0x00000000, 0x290e0000, + 0x00000010, 0x0ce7000f, + 0x00000010, 0xb873320e, + 0x0000000f, 0x436c0010, + 0x00000000, 0x03f30000, + 0x00000000, 0x83990e00, + 0x00000001, 0x83860e00, + 0x00000000, 0x83060e00, + 0x00000003, 0xf66c0c00, + 0x00000000, 0x39f30e00, + 0x00000000, 0x3af50e00, + 0x00000000, 0x7a740000, + 0x0000000f, 0x43680010, + 0x00000001, 0x83860e00, + 0x00000000, 0x83060e00, + 0x00000003, 0xf4680c00, + 0x00000000, 0x286d0000, + 0x0000000f, 0x63ef0010, + 0x00000000, 0x246f0000, + 0x00000010, 0xb1e9a054, + 0x00000000, 0x03690000, + 0x00000010, 0xb1f80c52, + 0x00000000, 0x0a6a0000, + 0x00000000, 0x0aeb0000, + 0x00000009, 0x0b6cffff, + 0x00000000, 0x0c000000, + 0x00000000, 0x0be90000, + 0x00000003, 0x8cf8a000, + 0x0000000c, 0x09800002, + 0x00000010, 0x009f0000, + 0x00000010, 0xb817320a, + 0x00000000, 0x35140000, + 0x00000000, 0x35950000, + 0x00000005, 0x766c2c00, + 0x00000000, 0x34970000, + 0x00000004, 0xb8f12e00, + 0x00000010, 0x001f0000, + 0x00000018, 0x8000fdc0, + 0x00000008, 0x0f800004, + 0x00000018, 0x8000fff6, + 0x00000000, 0x03e90000, + 0x00000010, 0xb8f8a017, + 0x00000010, 0x20130016, + 0x00000010, 0xb1f10e15, + 0x00000000, 0x83973200, + 0x00000000, 0x38700e00, + 0x00000000, 0xbc780e00, + 0x00000000, 0x3cf80000, + 0x00000000, 0x37d00000, + 0x0000000c, 0x73e7001a, + 0x00000003, 0xb8f1a000, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000005, 0x73e72c00, + 0x00000000, 0x33190000, + 0x00000005, 0x74680000, + 0x00000010, 0x0ce70009, + 0x00000000, 0x07520000, + 0x00000000, 0x396d0000, + 0x00000010, 0x0ce70003, + 0x00000000, 0x056d0000, + 0x00000018, 0x8000007a, + 0x00000000, 0x290e0000, + 0x00000018, 0x80000002, + 0x00000010, 0x91973206, + 0x00000000, 0x35140000, + 0x00000000, 0x35950000, + 0x00000005, 0x766c2c00, + 0x00000000, 0x34990000, + 0x00000004, 0xb8f13200, + 0x00000000, 0x83690c00, + 0x00000010, 0xb1860013, + 0x00000000, 0x28e90000, + 0x00000008, 0x22000004, + 0x00000008, 0x25002345, + 0x00000000, 0x03690000, + 0x00000010, 0xb8660c07, + 0x00000009, 0x036cffff, + 0x00000000, 0x326a0000, + 0x00000000, 0x32eb0000, + 0x00000005, 0x73e70c00, + 0x00000000, 0x33690000, + 0x00000005, 0x74680000, + 0x0000000c, 0x73e7001c, + 0x00000000, 0x03690000, + 0x00000010, 0xb1f80c12, + 0x00000010, 0xb1d00c11, + 0x0000000c, 0x21420005, + 0x0000000c, 0x33e7001c, + 0x00000018, 0x8000000e, + 0x00000010, 0x2e67000d, + 0x00000000, 0x03690000, + 0x00000010, 0xb1f80c0b, + 0x00000010, 0xb1d00c0a, + 0x00000000, 0x03440000, + 0x00000008, 0x2200000c, + 0x00000000, 0x07520000, + 0x00000000, 0x29000000, + 0x0000000c, 0x29800000, + 0x0000000c, 0x33e7001c, + 0x00000010, 0x20530000, + 0x00000000, 0x22060000, + 0x00000000, 0x290e0000, + 0x00000018, 0x000d0000, + 0x00000000, 0x06820000, + 0x00000010, 0x2de7000d, + 0x00000010, 0x0ce7000c, + 0x00000000, 0x27f20000, + 0x00000010, 0xb96d9e0a, + 0x00000000, 0xa86d9e00, + 0x00000018, 0x8000fd47, + 0x00000010, 0xb7501407, + 0x00000008, 0x2200000f, + 0x0000000f, 0x65680010, + 0x00000000, 0x29000000, + 0x0000000c, 0x29800000, + 0x0000000c, 0x33e7001b, + 0x00000010, 0x20530000, + 0x00000018, 0x000d0000, + 0x00000000, 0x39840000, + 0x00000000, 0x28f30000, + 0x00000000, 0x031e0000, + 0x00000009, 0x076000ff, + 0x00000010, 0x001f0000, + 0x0000000f, 0x0f0e0007, + 0x00000000, 0x83850800, + 0x00000000, 0x0a7d0000, + 0x00000000, 0x0afe0000, + 0x00000000, 0x0b7f0000, + 0x00000000, 0x0d7a0000, + 0x00000000, 0x0c000000, + 0x00000000, 0x0bfc0000, + 0x00000000, 0x0c970e00, + 0x00000018, 0x8000fd6d, + 0x00000008, 0x0f800003, + 0x0000000f, 0x47670010, + 0x00000008, 0x070e0001, + 0x0000000b, 0xc50000ff, + 0x00000002, 0x450a0000, + 0x00000001, 0x33e71400, + 0x0000000f, 0x050e0010, + 0x00000002, 0x33e71400, + 0x00000010, 0x009f0000, + 0x00000000, 0x02043600, + 0x00000000, 0x231b0000, + 0x00000000, 0x23ff0000, + 0x00000000, 0x241b0000, + 0x00000000, 0x03840000, + 0x00000010, 0x91870a03, + 0x00000000, 0x03d00000, + 0x0000000c, 0x21420001, + 0x00000003, 0x8387a000, + 0x0000000f, 0x65870010, + 0x00000009, 0x2607ffff, + 0x00000000, 0x27110000, + 0x00000000, 0x26900000, + 0x0000000c, 0x29000000, + 0x0000000f, 0x64e70010, + 0x00000009, 0x24c900ff, + 0x0000000c, 0x29800000, + 0x00000003, 0xf4683600, + 0x00000000, 0x3a100000, + 0x00000000, 0x3a910000, + 0x00000003, 0xf66c2400, + 0x00000010, 0xb1923605, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800004, + 0x00000000, 0x00000000, + 0x00000010, 0x009f0000, + 0x00000000, 0x3e170000, + 0x00000000, 0x3e940000, + 0x00000000, 0x3f150000, + 0x00000000, 0x3f960000, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f060000, + 0x00000010, 0x20530000, + 0x00000000, 0x22c53600, + 0x00000018, 0x8000fe83, + 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f008000, + 0x00000008, 0x0f800007, + 0x00000018, 0x8000001b, + 0x00000000, 0x280a0000, + 0x00000000, 0x05020000, + 0x00000008, 0x22000009, + 0x00000000, 0x29000000, + 0x0000000f, 0x65680010, + 0x00000000, 0x248a0000, + 0x00000003, 0xf66c9400, + 0x00000010, 0xb972a004, + 0x0000000c, 0x73e70019, + 0x0000000c, 0x21420004, + 0x00000000, 0x3cf80000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000008, 0x22000008, + 0x0000000c, 0x61420004, + 0x00000018, 0x000a0000, + 0x00000000, 0x05020000, + 0x0000000c, 0x61420000, + 0x00000010, 0x01420003, + 0x0000000c, 0x33e7001d, + 0x0000000c, 0x61420002, + 0x00000018, 0x000a0000, + 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, + 0x0000000f, 0x0f470007, + 0x00000008, 0x0f800008, + 0x0000000c, 0x29800000, + 0x00000010, 0x009f0000, + 0x00000018, 0x8000fce5, + 0x00000000, 0x33510000, + 0x00000000, 0x2a000000, + 0x00000010, 0xb1c60023, + 0x0000000f, 0x0f500007, + 0x00000000, 0x0a600000, + 0x00000000, 0x0ae10000, + 0x0000000f, 0x4b620008, + 0x00000009, 0x0b1600ff, + 0x0000000f, 0x4c620010, + 0x00000000, 0x0d620000, + 0x00000009, 0x0d1a00ff, + 0x00000010, 0x07500003, + 0x0000000c, 0x0d1a0008, + 0x0000000c, 0x0b160008, + 0x00000000, 0x0cc60000, + 0x00000000, 0x0b800000, + 0x00000000, 0x06980000, + 0x00000008, 0x0f800003, + 0x00000010, 0x06c20004, + 0x0000000c, 0x29000002, + 0x00000010, 0x26420002, + 0x0000000c, 0x29520003, + 0x00000008, 0x22000001, + 0x00000010, 0x009f0000, + 0x00000000, 0x231b0000, + 0x00000000, 0x27111a00, + 0x00000000, 0x66900000, + 0x0000000c, 0x29520000, + 0x00000010, 0xb1973209, + 0x0000000c, 0x29800000, + 0x00000000, 0x06980000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520003, + 0x00000000, 0x22c58c00, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800003, + 0x00000018, 0x8000fff3, + 0x00000010, 0xb1c80013, + 0x00000010, 0xb1c60003, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520000, + 0x0000000c, 0x29520003, + 0x00000010, 0x06c20002, + 0x0000000c, 0x29520002, + 0x00000000, 0x22c58c00, + 0x00000000, 0x27650000, + 0x00000000, 0x26e40000, + 0x00000008, 0x22000016, + 0x00000010, 0xb1c60003, + 0x00000000, 0x23480000, + 0x00000010, 0xb1800005, + 0x00000000, 0x23480000, + 0x0000000c, 0x29800000, + 0x0000000f, 0x0f500007, + 0x00000018, 0x80000012, + 0x00000008, 0x22000016, + 0x0000000c, 0x29800000, + 0x00000000, 0x30140000, + 0x00000000, 0x30950000, + 0x00000010, 0x07500003, + 0x00000009, 0x0b1600ff, + 0x00000009, 0x0d1a00ff, + 0x0000000f, 0x31160008, + 0x00000000, 0x31623400, + 0x00000003, 0xf1623000, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c510000, + 0x00000009, 0x2cd1007f, + 0x00000008, 0x2cd90000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d80000c, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000010, 0x05c20004, + 0x00000008, 0x0f800007, + 0x00000000, 0x33000000, + 0x00000010, 0x009f0000, + 0x00000018, 0x8000fc96, + 0x00000000, 0x2a000000, + 0x0000000f, 0x0f500007, + 0x00000010, 0xb1c6002d, + 0x0000000f, 0x47420008, + 0x00000009, 0x070e000f, + 0x00000008, 0x070e0008, + 0x00000010, 0x001f0000, + 0x00000008, 0x09000001, + 0x00000007, 0x09121c00, + 0x00000003, 0xcbca9200, + 0x00000000, 0x0b97a200, + 0x00000007, 0x42171c00, + 0x00000000, 0x0b040000, + 0x0000000f, 0x0a840003, + 0x00000000, 0x0a959c00, + 0x00000000, 0x4a009a00, + 0x00000008, 0x82120001, + 0x00000001, 0x0c170800, + 0x00000000, 0x0c978c00, + 0x00000000, 0x02180000, + 0x00000008, 0x0d00ffff, + 0x00000008, 0x0f800006, + 0x0000000c, 0x29000000, + 0x00000010, 0x06c20004, + 0x0000000c, 0x29520002, + 0x00000010, 0x26420002, + 0x0000000c, 0x29520003, + 0x00000008, 0x22000001, + 0x00000010, 0x009f0000, + 0x00000010, 0xb197320c, + 0x00000000, 0x231b0000, + 0x00000000, 0x27110800, + 0x00000000, 0x66900000, + 0x0000000c, 0x29800000, + 0x00000000, 0x02180000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520003, + 0x00000000, 0x22c53600, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800006, + 0x00000018, 0x8000fff4, + 0x00000000, 0x231b0000, + 0x00000000, 0x27110800, + 0x00000000, 0x66900000, + 0x00000010, 0xb1c8000b, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520000, + 0x0000000c, 0x29520003, + 0x00000010, 0x06c20002, + 0x0000000c, 0x29520002, + 0x00000000, 0x22c58c00, + 0x00000000, 0x27650000, + 0x00000000, 0x26e40000, + 0x00000000, 0x23480000, + 0x00000008, 0x22000017, + 0x0000000c, 0x29800000, + 0x00000010, 0x001f0000, + 0x00000018, 0x8000fc5b, +}; +/* Calling this macro prior to loading will change value of MAX_BD_PAGE (default = 0xff)*/ +#define XI_RV2P_PROC2_MAX_BD_PAGE_LOC 5 +#define XI_RV2P_PROC2_CHG_MAX_BD_PAGE(value) {\ + xi_rv2p_proc2[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = (xi_rv2p_proc2[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] & ~0xFFFF) | (value);\ +} + +/* Calling this macro prior to loading will change value of GEN_IND_SIZE (default = 0x1)*/ +#define XI_RV2P_PROC2_GEN_IND_SIZE_LOC 9 +#define XI_RV2P_PROC2_CHG_GEN_IND_SIZE(value) {\ + xi_rv2p_proc2[XI_RV2P_PROC2_GEN_IND_SIZE_LOC] = (xi_rv2p_proc2[XI_RV2P_PROC2_GEN_IND_SIZE_LOC] & ~0xFFFF) | (value);\ +} + +#endif /* __xi_rv2p_proc2.h__ */ + diff --git a/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/xinanfw.h b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/xinanfw.h new file mode 100644 index 0000000000..02a82dbcf9 --- /dev/null +++ b/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/xinanfw.h @@ -0,0 +1,8227 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* 4.0.4 */ +#include "bcmtype.h" +int TXP_b09FwReleaseMajor = 0x1; +int TXP_b09FwReleaseMinor = 0x0; +int TXP_b09FwReleaseFix = 0x0; +u32_t TXP_b09FwStartAddr = 0x080000a8; +u32_t TXP_b09FwTextAddr = 0x08000000; +int TXP_b09FwTextLen = 0x53e0; +u32_t TXP_b09FwDataAddr = 0x00000000; +int TXP_b09FwDataLen = 0x0; +u32_t TXP_b09FwRodataAddr = 0x080053e0; +int TXP_b09FwRodataLen = 0x30; +u32_t TXP_b09FwBssAddr = 0x080054d0; +int TXP_b09FwBssLen = 0x2ac; +u32_t TXP_b09FwSbssAddr = 0x08005448; +int TXP_b09FwSbssLen = 0x88; +u32_t TXP_b09FwSDataAddr = 0x00000000; +int TXP_b09FwSDataLen = 0x0; +u32_t TXP_b09FwText[(0x53e0/4) + 1] = { +0xa00002a, +0x0, 0x0, 0xd, 0x74787036, +0x2e322e36, 0x0, 0x6020600, 0x0, +0x136, 0xea60, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x16, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x1388, 0x0, 0x5dc, +0x0, 0x0, 0x10000003, 0x0, +0xd, 0xd, 0x3c020800, 0x24425448, +0x3c030800, 0x2463577c, 0xac400000, 0x43202b, +0x1480fffd, 0x24420004, 0x3c1d0800, 0x37bd7ffc, +0x3a0f021, 0x3c100800, 0x261000a8, 0x3c1c0800, +0x279c5448, 0xe000aa0, 0x0, 0xd, +0x27bdffb4, 0xafa10000, 0xafa20004, 0xafa30008, +0xafa4000c, 0xafa50010, 0xafa60014, 0xafa70018, +0xafa8001c, 0xafa90020, 0xafaa0024, 0xafab0028, +0xafac002c, 0xafad0030, 0xafae0034, 0xafaf0038, +0xafb8003c, 0xafb90040, 0xafbc0044, 0xafbf0048, +0xe000c29, 0x0, 0x8fbf0048, 0x8fbc0044, +0x8fb90040, 0x8fb8003c, 0x8faf0038, 0x8fae0034, +0x8fad0030, 0x8fac002c, 0x8fab0028, 0x8faa0024, +0x8fa90020, 0x8fa8001c, 0x8fa70018, 0x8fa60014, +0x8fa50010, 0x8fa4000c, 0x8fa30008, 0x8fa20004, +0x8fa10000, 0x27bd004c, 0x3c1b6004, 0x8f7a5030, +0x377b5028, 0x3400008, 0xaf7a0000, 0x3c038000, +0x34620e00, 0xac440000, 0x3c038000, 0x8c650000, +0x30a40008, 0x1080fffd, 0x34670e00, 0x94e80008, +0xa7880064, 0x8ce60004, 0xaf86005c, 0x3e00008, +0x0, 0xd, 0x3e00008, 0x0, +0x27bdffe8, 0x3c040800, 0x248454d0, 0x2405000c, +0x3021, 0x3c0c800e, 0xafbf0010, 0xe0006bc, +0xaf8c0000, 0x3c0b6000, 0x8d6a149c, 0x8fbf0010, +0x3c050800, 0x24a50710, 0x3149ffff, 0x3c060800, +0x24c601f8, 0x2524ffee, 0x3c080800, 0x25080354, +0x3c070800, 0x24e70508, 0x3c020800, 0x24420744, +0x3c030800, 0x24630754, 0x3c010800, 0xac285500, +0x3c010800, 0xac275504, 0x3c010800, 0xac225518, +0x3c010800, 0xac23551c, 0x3c010800, 0xac255520, +0x3c010800, 0xac265528, 0x3c010800, 0xac2400a0, +0x3c010800, 0xac255508, 0x3c010800, 0xac265510, +0x3e00008, 0x27bd0018, 0x27bdffe0, 0xafb20018, +0xafb10014, 0xc09021, 0xafbf001c, 0xafb00010, +0x308600ff, 0x3c118000, 0x8e220178, 0x440fffe, +0x36300140, 0x3c090800, 0x8d2954f8, 0x3c080800, +0x8d0854fc, 0xae090004, 0xa02021, 0xae080008, +0xae07000c, 0xa2060012, 0xe0007b8, 0xa6050018, +0x3c041000, 0x32432000, 0xae120014, 0xae240178, +0x10600006, 0x8fbf001c, 0x3c060800, 0x8cc60034, +0x24c50001, 0x3c010800, 0xac250034, 0x8fb20018, +0x8fb10014, 0x8fb00010, 0x3e00008, 0x27bd0020, +0x8f88ff98, 0x8f82ff9c, 0x3c060800, 0x8cc654e0, +0x91070008, 0x8d050048, 0x9044001b, 0x30e30004, +0x10600009, 0x308800ff, 0x3c0d6000, 0x8dac5404, +0x3c0a0800, 0x8d4a0060, 0x318b003f, 0x14b482b, +0x1520001d, 0x51842, 0x3c030800, 0x8c6354d0, +0x3c050800, 0x8ca554d4, 0x65202b, 0x54800001, +0x602821, 0xc5382b, 0x54e00001, 0xc02821, +0x31060002, 0x10c0000c, 0x0, 0x8f84ffa4, +0x8f820008, 0x8c880068, 0x481023, 0x10a00006, +0x451821, 0x440001b, 0x284a0002, 0x5540003c, +0x240b0001, 0xd, 0x3c010800, 0xac2554d8, +0x3e00008, 0x1021, 0xc3282b, 0x54a00001, +0xc01821, 0x3c070800, 0x8ce754d4, 0xe3702b, +0x11c00008, 0x0, 0x8f83ffa4, 0x2821, +0x8c78003c, 0x8c790038, 0x3197823, 0x5de0ffe1, +0x31060002, 0x3c030800, 0x8c6354d0, 0xa0000eb, +0xe02821, 0x1860ffe8, 0x0, 0x24090001, +0x10690002, 0x0, 0xd, 0x908d0009, +0x2dac000c, 0x11800005, 0x24a5ffff, 0x908f0009, +0x2dee0007, 0x11c0001a, 0x24070010, 0x90830071, +0x24180003, 0x307900ff, 0x13380015, 0x24070010, +0x3c020800, 0x8c4254fc, 0x3c030800, 0x8c6354d0, +0x24460001, 0x3c010800, 0xac2654fc, 0x1060ffce, +0x0, 0x2468ffff, 0x3c010800, 0xac2854d0, +0x3c010800, 0xac2554d8, 0x3e00008, 0x1021, +0x14abffe1, 0x0, 0xa00011c, 0x0, +0x24040001, 0x3c010800, 0xa02754de, 0xa000129, +0xaf84001c, 0x8f84ff98, 0x3c050800, 0x8ca554e0, +0x8c860048, 0x61042, 0xa2182b, 0x14600003, +0xa03821, 0x8c880048, 0x83842, 0x90840008, +0x8f8c005c, 0x978b0064, 0x240a0010, 0x3c010800, +0xac2c54d8, 0x31690040, 0x3c010800, 0xa02a54dc, +0x308600ff, 0x11200005, 0x8f880008, 0x978e0064, +0x31cd1000, 0x11a0003a, 0x0, 0x8f830068, +0x8c790024, 0x8f85005c, 0x8c780008, 0x3257821, +0x130f0033, 0x0, 0x30c40004, 0x10800011, +0x8f85ffa8, 0x8f86005c, 0x10c70040, 0x3c0d8000, +0x8f8f005c, 0x1e7702b, 0x11c0000a, 0x8f85ffa8, +0x3c026000, 0x8c435404, 0x3c190800, 0x8f390060, +0x3065003f, 0x325c02b, 0x1700003d, 0x8f84ffa4, +0x8f85ffa8, 0x8f84ffa4, 0x908f0073, 0x24080002, +0x31ee00ff, 0x11c80021, 0x0, 0x90890073, +0x24030001, 0x312400ff, 0x10830005, 0x0, +0x8f8a005c, 0x147302b, 0x14c00008, 0x0, +0xa0a0004c, 0x8f85005c, 0x10a00002, 0x24030006, +0x1821, 0x3e00008, 0x601021, 0x3c0c0800, +0x918c54dc, 0x318b0008, 0x1560fff5, 0x24020006, +0x3c010800, 0xac2054d8, 0x3e00008, 0xa0a3004c, +0x3c090800, 0x912954dc, 0x35220008, 0x3c010800, +0xa02254dc, 0xa000164, 0x30c40004, 0x8f99005c, +0x327c02b, 0x53000006, 0x24070001, 0x8c82000c, +0x30430001, 0x1060ffd9, 0x0, 0x24070001, +0xac87000c, 0xa000185, 0xa0800073, 0x35ac0e00, +0x958a0014, 0x958b0010, 0x156affbd, 0x8f85ffa8, +0x8f84ffa4, 0x24080001, 0xa000177, 0xa0a8004e, +0x8c860038, 0x1064823, 0x1920ffc3, 0x8f85ffa8, +0x90aa004e, 0x1540000b, 0x0, 0x978c0064, +0x318b0080, 0x1160ffbc, 0x8f8d001c, 0x15a0ffba, +0x24020006, 0x3c010800, 0xac2054d8, 0x3e00008, +0x0, 0xa000177, 0xa0a0004e, 0x3c0a0800, +0x914a54dd, 0x3c090800, 0x952954ea, 0x3c051100, +0xa3c00, 0x25280002, 0xe83025, 0xc51825, +0x24820008, 0xac830000, 0x3e00008, 0xac800004, +0x3c010800, 0xac2054d8, 0x3e00008, 0x24020001, +0x24020010, 0x3c010800, 0xa02254dc, 0x3c010800, +0xac2054d8, 0x3e00008, 0x24020004, 0x8f850060, +0x3c048000, 0x34830001, 0xa31025, 0x3e00008, +0xac820020, 0x3c058000, 0x8f830060, 0x34a80070, +0x8d070000, 0x833025, 0x3c029000, 0xc22025, +0xaca40020, 0xaf870058, 0x3c048000, 0x8c890020, +0x520fffe, 0x0, 0x34840070, 0x8c850000, +0x3c180800, 0x8f18007c, 0x3c0d0800, 0x8dad0078, +0xa7c823, 0x3195021, 0x7021, 0x159602b, +0x1ae5821, 0x16c3821, 0x3c010800, 0xac2a007c, +0x3c010800, 0xac270078, 0x3e00008, 0x0, +0xa0001e2, 0x24040001, 0x27bdffe0, 0xafb00010, +0x8f90ffa4, 0xafb20018, 0xafb10014, 0xafbf001c, +0x8e03000c, 0x809021, 0x30620001, 0x14400008, +0x8821, 0x2201021, 0x8fbf001c, 0x8fb20018, +0x8fb10014, 0x8fb00010, 0x3e00008, 0x27bd0020, +0xe000201, 0x0, 0x8e05000c, 0x30a40001, +0x1080001d, 0x0, 0x16400012, 0x0, +0x92060027, 0x14c00021, 0x8f8bffa8, 0x8e070044, +0x71080, 0x50400001, 0x24020001, 0x8e090040, +0x3c040800, 0x8c840024, 0x1221821, 0x64402b, +0x55000001, 0x801821, 0x8f8affa8, 0xa000241, +0xad430040, 0x3c020800, 0x8c420098, 0x3c118000, +0x8e300074, 0x8f8dffa4, 0x27840, 0x1f07021, +0xadae000c, 0x24110001, 0xe0001dc, 0x0, +0x2201021, 0x8fbf001c, 0x8fb20018, 0x8fb10014, +0x8fb00010, 0x3e00008, 0x27bd0020, 0x8d630040, +0x3c040800, 0x8c840028, 0x83602b, 0x55800001, +0x801821, 0xa000230, 0x601021, 0x27bdffc0, +0xafbf003c, 0xafbe0038, 0xafb70034, 0xafb60030, +0xafb5002c, 0xafb40028, 0xafb30024, 0xafb20020, +0xafb1001c, 0xafb00018, 0x3c058000, 0x24080080, +0x240600c0, 0xaca00810, 0xaca80814, 0xaca60818, +0x8f89ff98, 0x8f88ffa4, 0x8f8aff9c, 0x8d2b0050, +0x8d26003c, 0x8d470004, 0x8d24001c, 0x91020000, +0x24030020, 0xaf840010, 0x304400ff, 0xaf8b0004, +0xaf860008, 0x10830014, 0xaf87000c, 0x24050050, +0x1085030d, 0x8fbf003c, 0x3c0c0800, 0x8d8c0030, +0x25890001, 0x3c010800, 0xac290030, 0x8fbe0038, +0x8fb70034, 0x8fb60030, 0x8fb5002c, 0x8fb40028, +0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, +0x3e00008, 0x27bd0040, 0x24130240, 0xacb3081c, +0x24120800, 0xacb20178, 0x34b109c0, 0x8e220008, +0x8e270020, 0x34b00100, 0x8e0f0004, 0x3c010800, +0xac2754f8, 0x8e250024, 0x952e005c, 0x3c170800, +0x26f75500, 0x1e51823, 0x31cdffff, 0x3c010800, +0xac2554fc, 0x3c010800, 0xac2d54e0, 0x3c010800, +0xa02054df, 0x460036b, 0x0, 0x3c010800, +0xac2354d0, 0x8f9e0060, 0x3c108000, 0x36190e00, +0xae1e0080, 0x3c010800, 0xac2654f0, 0xaf270010, +0xaf250018, 0x91380005, 0x36110100, 0xaf80001c, +0x33160008, 0x16c0032a, 0x9234000b, 0x32870002, +0x14e00381, 0x0, 0x92300008, 0x320f0010, +0x15e0035d, 0x8f8affa8, 0x912c0009, 0x24080012, +0x318500ff, 0x10a803a8, 0x8f91ffa8, 0x9230001b, +0x107e00, 0xf7603, 0x5c0039f, 0x0, +0x91330009, 0x24090010, 0x327200ff, 0x1249039a, +0x0, 0x8f88ff9c, 0x9515000c, 0x12a003b1, +0x0, 0x9505000c, 0x3c0c8000, 0x30a6ffff, +0x659c0, 0xad8b002c, 0x9504000c, 0x3c030080, +0x34670003, 0x3082ffff, 0x251c0, 0xad8a080c, +0xad870820, 0x358d0a00, 0x359f09c0, 0x95b9002c, +0x8f9eff98, 0x8ff80024, 0xa7990014, 0xafbe0010, +0x3c010800, 0xac3854f4, 0x91160011, 0x91150012, +0x91b10018, 0x32d200ff, 0x32b300ff, 0x134880, +0x1327021, 0x323000ff, 0x1d07821, 0x3c010800, +0xa42f54e8, 0x3c010800, 0xa42e54e6, 0x91a50018, +0x91060011, 0x359e0e00, 0x30a400ff, 0x30cb00ff, +0x8b1021, 0x244a0010, 0x3c010800, 0xa42a54e4, +0x240c0006, 0x32880028, 0x3c010800, 0xac2c54ec, +0x3c010800, 0xa02054de, 0xa7800064, 0xb021, +0x1500005f, 0x24150008, 0x8f90ff98, 0x8f8e0008, +0x8f8f0010, 0x8e0d0020, 0x1ee1823, 0x460025e, +0x1ae2023, 0x480025c, 0x64882b, 0x12200262, +0x0, 0x3c010800, 0xac2354d4, 0x8ef20000, +0x240f809, 0x0, 0x8f86ffa8, 0x40a821, +0x90c9004c, 0x11200010, 0x8fa20010, 0x3c040800, +0x8c8454e0, 0x3c050800, 0x8ca554d8, 0x8c590048, +0x19c042, 0x98982b, 0x16600004, 0xa4382b, +0x8c5f0048, 0x1f2042, 0xa4382b, 0x14e0026d, +0x8f90ffa4, 0xa0c0004c, 0x3c080800, 0x910854de, +0x32a50001, 0x14a0001e, 0x288a025, 0x3c020800, +0x8c4254d8, 0x10400033, 0x328d0078, 0x3c0cc000, +0xe000070, 0x4c2025, 0x3c160800, 0x8ed600a4, +0x12c0000b, 0x0, 0x97c9000a, 0x97d10010, +0x97ce0014, 0x3125ffff, 0xb18023, 0x107c00, +0xf6c03, 0x19a0030e, 0x31c2ffff, 0xd, +0x8f87005c, 0x3c1f0800, 0x8fff54d8, 0x3e7c82b, +0x13200003, 0x24160001, 0xd, 0x24160001, +0x8ee20004, 0x40f809, 0x0, 0x2a2a825, +0x32a30002, 0x1060002a, 0x8f90ffa4, 0x12c0000e, +0x32ac0004, 0x8f860068, 0x3c080800, 0x8d0854f8, +0x3c050800, 0x8ca554fc, 0xacc80020, 0xacc50024, +0x3c0b0800, 0x8d6b54d8, 0xb202b, 0x45023, +0x2cab024, 0x32ac0004, 0x11800019, 0x8f90ffa4, +0x328d0078, 0x3c170800, 0x26f75518, 0x15a00007, +0x8f90ffa4, 0x328e0005, 0x11c00170, 0x8f850004, +0x8e0f0030, 0x11e50267, 0x8f86ffa8, 0x32990008, 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0x602821, 0x8f840044, 0x12040006, +0x3c0b8008, 0x8d6c006c, 0x2002021, 0xaf910040, +0x25900001, 0xad70006c, 0x8f8d0048, 0x858823, +0xaf910044, 0x1a52023, 0xaf840048, 0x12200002, +0x24070018, 0x24070010, 0x3c188008, 0x37060080, +0x90cf0068, 0x3c010800, 0xa0275738, 0x24070001, +0x31ee00ff, 0x11c70047, 0x0, 0x14800018, +0x2821, 0x3c068000, 0x34d10980, 0x34cd0100, +0x91a60009, 0x8e2c0018, 0x24c40001, 0xc8602, +0x3205007f, 0x308b007f, 0x1165007f, 0x2407ff80, +0x3c198008, 0x37290080, 0xa124004c, 0x3c080800, +0x8d085734, 0x24180002, 0x3c010800, 0xa0385779, +0x350f0008, 0x3c010800, 0xac2f5734, 0x24050010, +0x3c028000, 0x34440a00, 0x9083003c, 0x307f0020, +0x13e00005, 0xa02021, 0x240a0001, 0x3c010800, +0xac2a571c, 0x34a40001, 0x8fbf0018, 0x8fb10014, +0x8fb00010, 0x801021, 0x3e00008, 0x27bd0020, +0x3c010800, 0xa4205724, 0x10a0ff94, 0x2001821, +0xa00123c, 0xc01821, 0xa001233, 0x24030030, +0x3c050800, 0x8ca5571c, 0xb0702b, 0x11c0ffa8, +0x0, 0x3c190800, 0x97395724, 0x325c021, +0x307782b, 0x11e00007, 0x2caa0004, 0x3c036000, +0x8c625404, 0x305f003f, 0x17e0ffe3, 0x24040042, +0x2caa0004, 0x1140ff9a, 0x24040042, 0xa0012a0, +0x8fbf0018, 0x1528ffb9, 0x0, 0x8cca0018, +0x3c1f8000, 0x24020002, 0x15f1825, 0xacc30018, +0x37f90a00, 0xa0c20068, 0x9329003c, 0x24040004, +0xa01021, 0x31280020, 0x3c010800, 0xa0245779, +0x11000002, 0x24050010, 0x24020001, 0x3c010800, +0xac225714, 0xa001296, 0x3c028000, 0x8f880048, +0x8c890060, 0x109282b, 0x14a00002, 0x1008821, +0x8c910060, 0x3c048000, 0x348b0e00, 0x8d640018, +0x240a0001, 0x2202821, 0x2203021, 0xa38a003c, +0xe0010ff, 0x2208021, 0xa001222, 0xaf82004c, +0x45823, 0x12200007, 0x31640003, 0x3c0e8000, +0x35c70980, 0x90ed007c, 0x31ac0004, 0x15800019, +0x248f0004, 0x3c010800, 0xa424573a, 0x3c1f0800, +0x97ff573a, 0x3e5c821, 0xd9c02b, 0x1300ff6b, +0x8f840044, 0x2ca60005, 0x14c0ffa3, 0x24040042, +0x30a20003, 0x14400002, 0xa21823, 0x24a3fffc, +0x3c010800, 0xac23571c, 0x3c010800, 0xa420573a, +0xa001263, 0x602821, 0xc77024, 0xa001289, +0x1c72026, 0x3c010800, 0xa42f573a, 0xa0012f4, +0x0, 0x3c010800, 0xac20571c, 0xa00129f, +0x24040042, 0x8f830048, 0x3c058000, 0x34aa0a00, +0x14600006, 0x1021, 0x91470030, 0x24060005, +0x30e400ff, 0x10860003, 0x0, 0x3e00008, +0x0, 0x914b0048, 0x316900ff, 0x941c2, +0x1500fffa, 0x3c068008, 0x3c040800, 0x94845724, +0x3c030800, 0x8c63573c, 0x3c190800, 0x8f39571c, +0x3c0f0800, 0x95ef573a, 0x64c021, 0x8ccd0004, +0x3197021, 0x1cf6021, 0x34ab0e00, 0x18d2823, +0x18a0001d, 0x0, 0x914f004c, 0x8f8c0054, +0x956d0010, 0x31ee00ff, 0x8d890004, 0x1ae3023, +0x8d8a0000, 0x30ceffff, 0xe2900, 0x125c821, +0x3821, 0x1472021, 0x325182b, 0x83c021, +0xad990004, 0xad980000, 0x918f000a, 0x1cf6821, +0xa18d000a, 0x95650012, 0x8f8a0054, 0xa5450008, +0x954b0038, 0x25690001, 0xa5490038, 0x9148000d, +0x35070008, 0xa147000d, 0x3e00008, 0x0, +0x27bdffd8, 0xafb00018, 0x9388003c, 0x8fb00014, +0x3c0a8000, 0x3c197fff, 0x8f870044, 0x3738ffff, +0xafbf0020, 0xafb1001c, 0x355f0a00, 0x2181824, +0x93eb003c, 0x87fc0, 0x3c02bfff, 0x6f6025, +0x2cf00001, 0x3449ffff, 0x3c1f0800, 0x8fff573c, +0x8f990050, 0x3c180800, 0x97185732, 0x1897824, +0x104780, 0x3c07efff, 0x3c05f0ff, 0x1e81825, +0x3c118000, 0x31690020, 0x34e2ffff, 0x34adffff, +0x362e0980, 0x27a50010, 0x24060002, 0x3f96023, +0x270b0002, 0x354a0e00, 0x621824, 0x808021, +0x15200002, 0x4021, 0x8d48001c, 0xa7ab0012, +0x5800039, 0x24070000, 0x30e800ff, 0x83f00, +0x675825, 0x3c028008, 0xafab0014, 0x344f0080, +0x91ea0068, 0x3c080800, 0x91085739, 0x3c09dfff, +0x352cffff, 0xaf82b, 0x3c020800, 0x9442572c, +0xa3a80011, 0x16cc024, 0x1fcf40, 0x3191825, +0x8fa70010, 0xafa30014, 0x3c0c0800, 0x918c573b, +0xa7a20016, 0x8fab0014, 0xed4824, 0x3c0f0100, +0x3c0a0fff, 0x12fc825, 0x31980003, 0x355fffff, +0x16d4024, 0x3c027000, 0x33f3824, 0x181e00, +0xe24825, 0x1037825, 0xafaf0014, 0xafa90010, +0x91cc007c, 0xe0006b2, 0xa3ac0015, 0x362d0a00, +0x91a6003c, 0x30c40020, 0x10800006, 0x26020008, +0x3c110800, 0x96315728, 0x262effff, 0x3c010800, +0xa42e5728, 0x8fbf0020, 0x8fb1001c, 0x8fb00018, +0x3e00008, 0x27bd0028, 0x8f8b004c, 0x10b502b, +0x5540ffc5, 0x24070001, 0xa001380, 0x30e800ff, +0x9383003c, 0x3c028000, 0x27bdffd8, 0x34480a00, +0x805021, 0xafbf0020, 0x34460ac0, 0x1002821, +0x1060000e, 0x34440980, 0x91070030, 0x240b0005, +0x8f890040, 0x30ec003f, 0x118b000b, 0x3821, +0xafa90010, 0x3c0b8008, 0x8d69006c, 0xafaa0018, +0xe00077a, 0xafa90014, 0xa380003c, 0x8fbf0020, +0x3e00008, 0x27bd0028, 0x8d1f0048, 0x3c180800, +0x8f18571c, 0x8f990048, 0x3c027fff, 0x8d080044, +0x3443ffff, 0xafa90010, 0x3c0b8008, 0x8d69006c, +0x3e37024, 0x3197821, 0x1cf6823, 0x1a83821, +0xafaa0018, 0xe00077a, 0xafa90014, 0xa0013d4, +0xa380003c, 0x3c058000, 0x34a60a00, 0x90c7003c, +0x3c060800, 0x94c6573a, 0x3c020800, 0x8c425734, +0x30e30020, 0x62400, 0x10600032, 0x444825, +0x3c088008, 0x35050080, 0x90a30068, 0x6821, +0x240c0001, 0x5021, 0x240b0001, 0x3c188000, +0x370f0070, 0x8de70000, 0x3c088000, 0xaf870058, +0x8d190178, 0x720fffe, 0x350e0070, 0x8dc60000, +0x3c040800, 0x8c840074, 0x3c190800, 0x8f390070, +0xc71023, 0x822821, 0x3821, 0xa2c02b, +0x3277821, 0x1f87021, 0x35070140, 0x3c010800, +0xac250074, 0x3c010800, 0xac2e0070, 0xacec0008, +0x3c060800, 0x8cc6573c, 0xa4ea0004, 0xa4eb0006, +0xace6000c, 0x3c020800, 0x90425739, 0x3c048008, +0x34830080, 0xa0e20012, 0xace90014, 0xa4ed0018, +0x906c004c, 0x3c091000, 0xa0ec002d, 0x3e00008, +0xad090178, 0x34ad0e00, 0x8dac001c, 0x3c0b0800, +0x8d6b571c, 0x95aa0016, 0x95ae0014, 0x1666821, +0x314bffff, 0xa0013fc, 0x31caffff, 0x3c048000, +0x34830a00, 0x9065003c, 0x30a20020, 0x1040002d, +0x34870e00, 0x6021, 0x5821, 0x5021, +0x3c088000, 0x35090070, 0x8d280000, 0x3c098000, +0xaf880058, 0x8d2d0178, 0x5a0fffe, 0x35380070, +0x8f0f0000, 0x3c070800, 0x8ce70074, 0x3c060800, +0x8cc60070, 0x1e87023, 0xee2821, 0x1021, +0xae202b, 0xc21821, 0x352e0140, 0x352d0100, +0x64c821, 0x91af0009, 0x3c010800, 0xac250074, +0x3c010800, 0xac390070, 0xadcc0008, 0x3c180800, +0x8f18573c, 0xa5ca0004, 0x240cff91, 0xa5cb0006, +0x3c0a1000, 0x240b0040, 0xadd8000c, 0xa1cc0012, +0xadcb0014, 0xa5c00018, 0xa1cf002d, 0x3e00008, +0xad2a0178, 0x8cec0018, 0x94e60012, 0x94e40010, +0x30cbffff, 0xa001439, 0x308affff, 0x3c048000, +0x34830a00, 0x9065003c, 0x30a20020, 0x1040003b, +0x27bdfff8, 0x240d0001, 0x5821, 0x240c0001, +0x3c098000, 0x35280070, 0x8d050000, 0x3c0a8000, +0xaf850058, 0x8d4e0178, 0x5c0fffe, 0x35460100, +0x90c90009, 0x35580070, 0x8f040000, 0xa3a90003, +0x8faf0000, 0x3c090800, 0x8d290074, 0x3c070800, +0x90e75779, 0x1ea7025, 0xafae0000, 0x90c2000a, +0xa3a00002, 0x3c0e0800, 0x8dce0070, 0xa3a20001, +0x8fb90000, 0x854023, 0x3c0380ff, 0x3465ffff, +0x30f8007f, 0x1281821, 0x2021, 0x3253024, +0x183e00, 0x68102b, 0x1c44021, 0x354f0140, +0x1022821, 0xc7c825, 0x24183000, 0x3c010800, +0xac230074, 0x27bd0008, 0x3c010800, 0xac250070, +0xadf9000c, 0xadf80014, 0xa5e00018, 0xaded0008, +0xa5eb0004, 0xa5ec0006, 0x3c0b1000, 0x240cff80, +0xa1ec0012, 0x3e00008, 0xad4b0178, 0x34870e00, +0x8ced0018, 0x94e60012, 0x94e40010, 0x30ccffff, +0xa001471, 0x308bffff, 0x27bdffe0, 0xafb10014, +0x3c118000, 0xafb00010, 0xafbf0018, 0x36380a00, +0x970f0032, 0x36300100, 0xe0010fb, 0x31e43fff, +0x8e0e0000, 0x240dff80, 0x3c042000, 0x1c25821, +0x16d6024, 0xc4940, 0x316a007f, 0x12a4025, +0x1043825, 0x3c048008, 0xae270830, 0x34860080, +0x90c50068, 0x24030002, 0x30a200ff, 0x10430004, +0x8f9f0040, 0x8f990044, 0xac9f0068, 0xac990064, +0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x3e00008, +0x27bd0020, 0x3c0a0800, 0x254a50c0, 0x3c090800, +0x252951a0, 0x3c080800, 0x2508450c, 0x3c070800, +0x24e752bc, 0x3c060800, 0x24c64ef4, 0x3c050800, +0x24a54c48, 0x3c040800, 0x2484484c, 0x3c030800, +0x24634fa8, 0x3c020800, 0x24424d44, 0x3c010800, +0xac2a56f8, 0x3c010800, 0xac2956f4, 0x3c010800, +0xac2856f0, 0x3c010800, 0xac2756fc, 0x3c010800, +0xac26570c, 0x3c010800, 0xac255704, 0x3c010800, +0xac245700, 0x3c010800, 0xac235710, 0x3c010800, +0xac225708, 0x3e00008, 0x0, 0x0 }; +u32_t TXP_b09FwData[(0x0/4) + 1] = { 0x0 }; +u32_t TXP_b09FwRodata[(0x30/4) + 1] = { +0x80000940, +0x80000900, 0x80080100, 0x80080080, 0x80080000, +0x800e0000, 0x80080080, 0x80080000, 0x80000a80, +0x80000a00, 0x80000980, 0x80000900, 0x0 }; +u32_t TXP_b09FwBss[(0x2ac/4) + 1] = { 0x0 }; +u32_t TXP_b09FwSbss[(0x88/4) + 1] = { 0x0 }; +u32_t TXP_b09FwSdata[(0x0/4) + 1] = { 0x0 }; +/* 4.0.4 */ +#include "bcmtype.h" +int TPAT_b09FwReleaseMajor = 0x1; +int TPAT_b09FwReleaseMinor = 0x0; +int TPAT_b09FwReleaseFix = 0x0; +u32_t TPAT_b09FwStartAddr = 0x08000490; +u32_t TPAT_b09FwTextAddr = 0x08000400; +int TPAT_b09FwTextLen = 0x13f0; +u32_t TPAT_b09FwDataAddr = 0x00000000; +int TPAT_b09FwDataLen = 0x0; +u32_t TPAT_b09FwRodataAddr = 0x080017f0; +int TPAT_b09FwRodataLen = 0x4; +u32_t TPAT_b09FwBssAddr = 0x08001860; +int TPAT_b09FwBssLen = 0x12b4; +u32_t TPAT_b09FwSbssAddr = 0x08001820; +int TPAT_b09FwSbssLen = 0x40; +u32_t TPAT_b09FwSDataAddr = 0x00000000; +int TPAT_b09FwSDataLen = 0x0; +u32_t TPAT_b09FwText[(0x13f0/4) + 1] = { +0xa000124, +0x0, 0x0, 0xd, 0x74706136, +0x2e322e36, 0x0, 0x6020601, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x10000003, 0x0, 0xd, 0xd, +0x3c020800, 0x24421820, 0x3c030800, 0x24632b14, +0xac400000, 0x43202b, 0x1480fffd, 0x24420004, +0x3c1d0800, 0x37bd2ffc, 0x3a0f021, 0x3c100800, +0x26100490, 0x3c1c0800, 0x279c1820, 0xe000262, +0x0, 0xd, 0x2402ff80, 0x27bdffe0, +0x821024, 0xafb00010, 0xaf420020, 0xafbf0018, +0xafb10014, 0x93650004, 0x3084007f, 0x3441821, +0x3c020008, 0x621821, 0x30a50020, 0x3608021, +0x3c080111, 0x277b0008, 0x14a00002, 0x2466005c, +0x24660058, 0x92020004, 0x97430104, 0x92040004, +0x3047000f, 0x3063ffff, 0x30840040, 0x672823, +0x10800009, 0x4821, 0x92020005, 0x30420004, +0x10400005, 0x0, 0x10a00003, 0x0, +0x24a5fffc, 0x24090004, 0x92020005, 0x30420004, +0x10400012, 0x0, 0x10a00010, 0x0, +0x96020002, 0xa72021, 0x1044025, 0x2442fffe, +0xa7421016, 0x92030004, 0x2402ff80, 0x431024, +0x304200ff, 0x10400003, 0x3c020400, 0xa000174, +0x1024025, 0x8cc20000, 0xaf421018, 0x8f420178, +0x440fffe, 0x2402000a, 0xa7420140, 0x96020002, +0x24040009, 0x30420007, 0x21023, 0x30420007, +0xa7420142, 0x96020002, 0x2442fffe, 0xa7420144, +0xa7400146, 0x97420104, 0xa7420148, 0x8f420108, +0x30420020, 0x50400001, 0x24040001, 0x92020004, +0x30420010, 0x14400002, 0x34830010, 0x801821, +0xa743014a, 0x0, 0x0, 0x0, +0x0, 0xaf481000, 0x0, 0x0, +0x0, 0x0, 0x8f421000, 0x441fffe, +0x3102ffff, 0x10400007, 0x0, 0x92020004, +0x30420040, 0x14400003, 0x0, 0x8f421018, +0xacc20000, 0x96020006, 0x3042ffff, 0x24420002, +0x21043, 0x21040, 0x3628821, 0x96220000, +0x1120000d, 0x3044ffff, 0xa71021, 0x8f83003c, +0x8f45101c, 0x21082, 0x21080, 0x431021, +0xac450000, 0x30a6ffff, 0xe0005ca, 0x52c02, +0x402021, 0xa6220000, 0x92030004, 0x2402ff80, +0x431024, 0x304200ff, 0x1040001f, 0x0, +0x92020005, 0x30420002, 0x1040001b, 0x0, +0x9742100c, 0x2442fffe, 0xa7421016, 0x0, +0x3c020400, 0x34420030, 0xaf421000, 0x0, +0x0, 0x0, 0x0, 0x8f421000, +0x441fffe, 0x0, 0x9742100c, 0x8f45101c, +0x3042ffff, 0x24420030, 0x21082, 0x21080, +0x5b1021, 0xac450000, 0x30a6ffff, 0xe0005ca, +0x52c02, 0xa6220000, 0x96040002, 0x24840008, +0xe0001e9, 0x3084ffff, 0x97440104, 0xe0001f7, +0x3084ffff, 0x8fbf0018, 0x8fb10014, 0x8fb00010, +0x3c021000, 0x27bd0020, 0x3e00008, 0xaf420178, +0x3084ffff, 0x30820007, 0x8f850024, 0x10400002, +0x24830007, 0x3064fff8, 0xa41021, 0x30421fff, +0x3421821, 0x247b4000, 0xaf850028, 0xaf820024, +0x3e00008, 0xaf420084, 0x3084ffff, 0x3082000f, +0x8f85002c, 0x8f860034, 0x10400002, 0x2483000f, +0x3064fff0, 0xa41021, 0x46182b, 0xaf850030, +0x462023, 0x14600002, 0xaf82002c, 0xaf84002c, +0x8f82002c, 0x34048000, 0x3421821, 0x641821, +0xaf83003c, 0x3e00008, 0xaf420080, 0x8f820014, +0x10400008, 0x8f820004, 0x8f82ffd0, 0x14400005, +0x8f820004, 0x3c02ffbf, 0x3442ffff, 0x822024, +0x8f820004, 0x30430006, 0x24020002, 0x1062000f, +0x3c020101, 0x2c620003, 0x50400005, 0x24020004, +0x1060000f, 0x3c020001, 0xa000230, 0x0, +0x10620005, 0x24020006, 0x1462000c, 0x3c020111, +0xa000229, 0x821025, 0x3c020011, 0x821025, +0xaf421000, 0x24020001, 0xa000230, 0xaf82000c, +0x821025, 0xaf421000, 0xaf80000c, 0x0, +0x0, 0x0, 0x3e00008, 0x0, +0x8f82000c, 0x10400004, 0x0, 0x8f421000, +0x441fffe, 0x0, 0x3e00008, 0x0, +0x8f820010, 0x2443f800, 0x231c2, 0x24c2fff0, +0x2c630301, 0x10600003, 0x21042, 0xa000257, +0xac820000, 0x8f850018, 0xc5102b, 0x1440000b, +0x1821, 0xc51023, 0x24470001, 0x8f82001c, +0xa21021, 0x2442ffff, 0x46102b, 0x54400004, +0x2402ffff, 0xa000257, 0xac870000, 0x2402ffff, +0xa000260, 0xac820000, 0x8c820000, 0x21940, +0x621821, 0x31880, 0x621821, 0x31880, +0x3c020800, 0x24421860, 0x621821, 0x3e00008, +0x601021, 0x27bdffd8, 0xafbf0020, 0xafb1001c, +0xafb00018, 0x3c046008, 0x8c825000, 0x2403ff7f, +0x3c066000, 0x431024, 0x3442380c, 0xac825000, +0x8cc24c1c, 0x3c1a8000, 0x21602, 0x3042000f, +0x10400007, 0xaf82001c, 0x8cc34c1c, 0x3c02001f, +0x3442fc00, 0x621824, 0x319c2, 0xaf830018, +0x8f420008, 0x275b4000, 0x34420001, 0xaf420008, +0xaf800024, 0x3c02601c, 0xaf400080, 0xaf400084, +0x8c450008, 0x8cc30808, 0x34028000, 0x3422021, +0x2402fff0, 0x621824, 0x3c020080, 0x3c010800, +0xac220420, 0x3c025709, 0xaf84003c, 0x14620004, +0xaf850034, 0x24020001, 0xa000292, 0xaf820014, +0xaf800014, 0x3c028000, 0x34440070, 0x8c830000, +0x8f420000, 0x38420001, 0x30420001, 0x10400018, +0xaf830038, 0x804021, 0x603021, 0x8d070000, +0x3c050800, 0x8ca5045c, 0x3c040800, 0x8c840458, +0xe63023, 0x1021, 0xa62821, 0xa6302b, +0x822021, 0x862021, 0x3c010800, 0xac25045c, +0x3c010800, 0xac240458, 0x8f420000, 0x38420001, +0x30420001, 0x1440ffed, 0xe03021, 0xaf870038, +0x3c028000, 0x34420070, 0x8c470000, 0x8f860038, +0x3c050800, 0x8ca5045c, 0x3c040800, 0x8c840458, +0xe63823, 0x1021, 0xa72821, 0x822021, +0x8f820014, 0xa7302b, 0x862021, 0x3c010800, +0xac25045c, 0x3c010800, 0xac240458, 0x10400016, +0x0, 0x97420104, 0x10400005, 0x8f830000, +0x14600007, 0x2462ffff, 0xa0002d4, 0x2c62000a, +0x2c620010, 0x50400004, 0x8f830000, 0x24620001, +0xaf820000, 0x8f830000, 0x2c62000a, 0x14400003, +0x2c620007, 0xa0002db, 0xaf80ffd0, 0x10400002, +0x24020001, 0xaf82ffd0, 0x8f470108, 0x8f480100, +0x30e22000, 0xaf870004, 0x10400008, 0xaf880010, +0x3c020800, 0x8c42042c, 0x24420001, 0x3c010800, +0xac22042c, 0xa0005c6, 0x3c024000, 0x97440104, +0x3c050800, 0x8ca5048c, 0x1021, 0x3083ffff, +0x3c040800, 0x8c840488, 0xa32821, 0xa3302b, +0x822021, 0x862021, 0x30e60200, 0x3c010800, +0xac25048c, 0x3c010800, 0xac240488, 0x14c00003, +0x24020f00, 0x15020260, 0x24020d00, 0x97420104, +0x104002c8, 0x3c024000, 0x30e24000, 0x144000ad, +0x8f82003c, 0x8c440008, 0x8f420178, 0x440fffe, +0x24020800, 0xaf420178, 0x24020008, 0xa7420140, +0xa7400142, 0x97420104, 0x8f840004, 0x3051ffff, +0x30820001, 0x10400007, 0x2208021, 0x2623fffe, +0x24020002, 0x3070ffff, 0xa7420146, 0xa000317, +0xa7430148, 0xa7400146, 0x3c020800, 0x8c42043c, +0x1440000d, 0x8f830010, 0x30820020, 0x14400002, +0x24030009, 0x24030001, 0x602021, 0x8f830010, +0x24020900, 0x50620001, 0x34840004, 0xa744014a, +0xa000332, 0x0, 0x24020f00, 0x14620005, +0x30820020, 0x14400006, 0x2403000d, 0xa000331, +0x24030005, 0x14400002, 0x24030009, 0x24030001, +0xa743014a, 0x3c020800, 0x8c420420, 0x3c040048, +0xe00020c, 0x442025, 0xe000235, 0x0, +0x8f82000c, 0x1040003e, 0x0, 0x8f421000, +0x3c030020, 0x431024, 0x10400039, 0x8f820004, +0x30420002, 0x10400036, 0x0, 0x97421014, +0x14400033, 0x0, 0x97421008, 0x8f88003c, +0x3042ffff, 0x24420006, 0x21882, 0x33880, +0xe83021, 0x30430001, 0x8cc40000, 0x10600004, +0x30420003, 0xd, 0xa000373, 0xe81021, +0x54400010, 0x3084ffff, 0x3c05ffff, 0x852024, +0x851826, 0x3182b, 0x4102b, 0x431024, +0x10400005, 0x0, 0x0, 0xd, +0x0, 0x24000222, 0x8cc20000, 0xa000372, +0x452025, 0x3883ffff, 0x3182b, 0x4102b, +0x431024, 0x10400005, 0x0, 0x0, +0xd, 0x0, 0x2400022b, 0x8cc20000, +0x3444ffff, 0xe81021, 0xac440000, 0x3c020800, +0x8c420430, 0x24420001, 0x3c010800, 0xac220430, +0x8f620000, 0x8f84003c, 0xaf820008, 0x8c830000, +0x3402ffff, 0x1462000f, 0x1021, 0x3c050800, +0x8ca50454, 0x3c040800, 0x8c840450, 0xb02821, +0xb0302b, 0x822021, 0x862021, 0x3c010800, +0xac250454, 0x3c010800, 0xac240450, 0xa0005bc, +0x24040008, 0x8c820000, 0x30420100, 0x1040000f, +0x1021, 0x3c050800, 0x8ca5044c, 0x3c040800, +0x8c840448, 0xb02821, 0xb0302b, 0x822021, +0x862021, 0x3c010800, 0xac25044c, 0x3c010800, +0xac240448, 0xa0005bc, 0x24040008, 0x3c050800, +0x8ca50444, 0x3c040800, 0x8c840440, 0xb02821, +0xb0302b, 0x822021, 0x862021, 0x3c010800, +0xac250444, 0x3c010800, 0xac240440, 0xa0005bc, +0x24040008, 0x8f620008, 0x8f620000, 0x21602, +0x304300f0, 0x24020030, 0x10620005, 0x24020040, +0x106200e0, 0x8f820020, 0xa0005c4, 0x24420001, +0x14c00005, 0x0, 0x0, 0xd, +0x0, 0x24000256, 0x8f420178, 0x440fffe, +0x0, 0xe00023d, 0x27a40010, 0x14400005, +0x408021, 0x0, 0xd, 0x0, +0x2400025d, 0x8e020000, 0x10400005, 0x0, +0x0, 0xd, 0x0, 0x24000260, +0x8f62000c, 0x4430003, 0x24020001, 0xa00046a, +0xae000000, 0xae020000, 0x8f82003c, 0x8c480008, +0xa2000007, 0x8f65000c, 0x8f640004, 0x30a3ffff, +0x42402, 0x852023, 0x308200ff, 0x431021, +0x24420005, 0x23083, 0x2cc20081, 0xa605000a, +0x14400005, 0xa2040004, 0x0, 0xd, +0x0, 0x24000278, 0x8f85003c, 0xe0005e8, +0x26040014, 0x8f620004, 0x8f430108, 0xa6020008, +0x3c021000, 0x621824, 0x10600008, 0x0, +0x97420104, 0x92030007, 0x2442ffec, 0x34630002, +0x3045ffff, 0xa0003ff, 0xa2030007, 0x97420104, +0x2442fff0, 0x3045ffff, 0x96060008, 0x2cc20013, +0x54400005, 0x92030007, 0x92020007, 0x34420001, +0xa2020007, 0x92030007, 0x24020001, 0x10620005, +0x24020003, 0x1062000b, 0x8f82003c, 0xa00041c, +0x30c6ffff, 0x8f82003c, 0x3c04ffff, 0x8c43000c, +0x641824, 0x651825, 0xac43000c, 0xa00041c, +0x30c6ffff, 0x3c04ffff, 0x8c430010, 0x641824, +0x651825, 0xac430010, 0x30c6ffff, 0x24c20002, +0x21083, 0xa2020005, 0x8f83003c, 0x304200ff, +0x21080, 0x432821, 0x8ca80000, 0x8ca20000, +0x24030004, 0x21702, 0x14430012, 0x0, +0x97420104, 0x3c03ffff, 0x1031824, 0x3042ffff, +0x461023, 0x2442fffe, 0x624025, 0xaca80000, +0x92030005, 0x306200ff, 0x21080, 0x501021, +0x90420014, 0x3042000f, 0x431021, 0xa000451, +0xa2020006, 0x8ca40004, 0x97420104, 0x9603000a, +0x3088ffff, 0x3042ffff, 0x461023, 0x2442ffd6, +0x21400, 0x1024025, 0xaca80004, 0x92020007, +0x92040005, 0x24630028, 0x31883, 0x641821, +0x34420004, 0xa2030006, 0xa2020007, 0x8f820004, +0x2403fffb, 0x34420002, 0x431024, 0xaf820004, +0x92030006, 0x8f87003c, 0x31880, 0x701021, +0x8c440020, 0x3c02fff6, 0x3442ffff, 0x824024, +0x671821, 0xae04000c, 0xac68000c, 0x92050006, +0x3c03ff7f, 0x8e02000c, 0x52880, 0xb02021, +0x3463ffff, 0x1033024, 0x94880026, 0xa72821, +0x431024, 0xae02000c, 0xac860020, 0xac880024, +0xaca80010, 0x24020010, 0xa7420140, 0x24020002, +0xa7400142, 0xa7400144, 0xa7420146, 0x97420104, +0x3c040008, 0x2442fffe, 0xa7420148, 0x24020001, +0xe00020c, 0xa742014a, 0x9603000a, 0x92020004, +0x431021, 0x24420002, 0x30420007, 0x21023, +0x30420007, 0xe000235, 0xae020010, 0x8f620000, +0x3c030800, 0x8c630444, 0x24040010, 0xaf820008, +0x97420104, 0x3042ffff, 0x2442fffe, 0x403821, +0x237c3, 0x3c020800, 0x8c420440, 0x671821, +0x67282b, 0x461021, 0x451021, 0x3c010800, +0xac230444, 0x3c010800, 0xac220440, 0xa000551, +0x0, 0x14c00005, 0x0, 0x0, +0xd, 0x0, 0x2400030a, 0x8f420178, +0x440fffe, 0x0, 0xe00023d, 0x27a40014, +0x14400005, 0x408021, 0x0, 0xd, +0x0, 0x24000311, 0x8e020000, 0x54400006, +0x92020007, 0x0, 0xd, 0x0, +0x2400031c, 0x92020007, 0x30420004, 0x10400005, +0x8f820004, 0x2403fffb, 0x34420002, 0x431024, +0xaf820004, 0x8f620004, 0x4430008, 0x92020007, +0x92020006, 0x8e03000c, 0xae000000, 0x21080, +0x501021, 0xac430020, 0x92020007, 0x30420004, +0x54400009, 0x9602000a, 0x92020005, 0x3c030001, +0x21080, 0x501021, 0x8c460018, 0xc33021, +0xac460018, 0x9602000a, 0x92060004, 0x27710008, +0x2202021, 0xc23021, 0x24c60005, 0x26050014, +0xe0005e8, 0x63082, 0x92040006, 0x8f650004, +0x3c027fff, 0x42080, 0x912021, 0x8c830004, +0x3442ffff, 0xa22824, 0x651821, 0xac830004, +0x92020007, 0x92040005, 0x92030004, 0x30420004, +0x10400014, 0x96070008, 0x308400ff, 0x42080, +0x912021, 0x8c860004, 0x97420104, 0x9605000a, +0x306300ff, 0x3042ffff, 0x431021, 0x451021, +0x30e3ffff, 0x431023, 0x2442ffd8, 0x30c6ffff, +0x21400, 0xc23025, 0xac860004, 0xa000505, +0x92030007, 0x308500ff, 0x52880, 0xb12821, +0x8ca40000, 0x97420104, 0x306300ff, 0x3042ffff, +0x431021, 0x471023, 0x3c03ffff, 0x832024, +0x3042ffff, 0x822025, 0xaca40000, 0x92030007, +0x24020001, 0x10620006, 0x0, 0x24020003, +0x10620011, 0x0, 0xa000528, 0x8e030010, +0x97420104, 0x92030004, 0x9605000a, 0x8e24000c, +0x431021, 0x451021, 0x2442fff2, 0x3c03ffff, +0x832024, 0x3042ffff, 0x822025, 0xae24000c, +0xa000528, 0x8e030010, 0x97420104, 0x92030004, +0x9605000a, 0x8e240010, 0x431021, 0x451021, +0x2442ffee, 0x3c03ffff, 0x832024, 0x3042ffff, +0x822025, 0xae240010, 0x8e030010, 0x2402000a, +0xa7420140, 0xa7430142, 0x9603000a, 0x92020004, +0x3c040040, 0x431021, 0xa7420144, 0xa7400146, +0x97420104, 0xa7420148, 0x24020001, 0xe00020c, +0xa742014a, 0xe000235, 0x0, 0x8f620000, +0x92030004, 0x2021, 0xaf820008, 0x97420104, +0x9606000a, 0x3042ffff, 0x621821, 0x602821, +0x3c030800, 0x8c630444, 0x3c020800, 0x8c420440, +0x651821, 0x441021, 0x65382b, 0x471021, +0x3c010800, 0xac230444, 0x3c010800, 0xac220440, +0x92040004, 0x862021, 0x2484000a, 0x3084ffff, +0xe0001e9, 0x0, 0x97440104, 0x3084ffff, +0xe0001f7, 0x0, 0x3c021000, 0xaf420178, +0xa0005c3, 0x8f820020, 0x15020027, 0x30e20006, +0x97420104, 0x10400067, 0x3c024000, 0x30e24000, +0x10400005, 0x0, 0x0, 0xd, +0x0, 0x24000420, 0x8f420178, 0x440fffe, +0x24020800, 0xaf420178, 0x24020008, 0xa7420140, +0xa7400142, 0x8f820004, 0x97430104, 0x30420001, +0x10400007, 0x3070ffff, 0x2603fffe, 0x24020002, +0xa7420146, 0xa7430148, 0xa00057b, 0x2402000d, +0xa7400146, 0x2402000d, 0xa742014a, 0x8f620000, +0x24040008, 0xaf820008, 0xe0001e9, 0x0, +0xa000555, 0x2002021, 0x10400042, 0x3c024000, +0x93620000, 0x304300f0, 0x24020010, 0x10620005, +0x24020070, 0x10620035, 0x0, 0xa0005c3, +0x8f820020, 0x8f620000, 0x97430104, 0x3050ffff, +0x3071ffff, 0x8f420178, 0x440fffe, 0x32020007, +0x21023, 0x30420007, 0x2403000a, 0x2604fffe, +0xa7430140, 0xa7420142, 0xa7440144, 0xa7400146, +0xa7510148, 0x8f420108, 0x30420020, 0x14400002, +0x24030009, 0x24030001, 0xa743014a, 0xe00020c, +0x3c040040, 0xe000235, 0x0, 0x3c070800, +0x8ce70444, 0x2111021, 0x2442fffe, 0x3c060800, +0x8cc60440, 0x401821, 0xe33821, 0x1021, +0x8f650000, 0xe3402b, 0xc23021, 0x26040008, +0xc83021, 0x3084ffff, 0xaf850008, 0x3c010800, +0xac270444, 0x3c010800, 0xac260440, 0xe0001e9, +0x0, 0xa000555, 0x2202021, 0xe00013b, +0x1002021, 0x8f820020, 0x24420001, 0xaf820020, +0x3c024000, 0xaf420138, 0x0, 0xa000293, +0x3c028000, 0x3084ffff, 0x30c6ffff, 0x52c00, +0xa62825, 0x3882ffff, 0x451021, 0x45282b, +0x451021, 0x21c02, 0x3042ffff, 0x431021, +0x21c02, 0x3042ffff, 0x431021, 0x3842ffff, +0x3e00008, 0x3042ffff, 0x3084ffff, 0x30a5ffff, +0x1821, 0x10800007, 0x0, 0x30820001, +0x10400002, 0x42042, 0x651821, 0xa0005de, +0x52840, 0x3e00008, 0x601021, 0x10c00006, +0x24c6ffff, 0x8ca20000, 0x24a50004, 0xac820000, +0xa0005e8, 0x24840004, 0x3e00008, 0x0, +0x10a00008, 0x24a3ffff, 0xac860000, 0x0, +0x0, 0x2402ffff, 0x2463ffff, 0x1462fffa, +0x24840004, 0x3e00008, 0x0, 0x0 }; +u32_t TPAT_b09FwData[(0x0/4) + 1] = { 0x0 }; +u32_t TPAT_b09FwRodata[(0x4/4) + 1] = { +0x1, +0x0 }; +u32_t TPAT_b09FwBss[(0x12b4/4) + 1] = { 0x0 }; +u32_t TPAT_b09FwSbss[(0x40/4) + 1] = { 0x0 }; +u32_t TPAT_b09FwSdata[(0x0/4) + 1] = { 0x0 }; +/* 4.0.4 */ +#include "bcmtype.h" +int COM_b09FwReleaseMajor = 0x1; +int COM_b09FwReleaseMinor = 0x0; +int COM_b09FwReleaseFix = 0x0; +u32_t COM_b09FwStartAddr = 0x08000118; +u32_t COM_b09FwTextAddr = 0x08000000; +int COM_b09FwTextLen = 0x900c; +u32_t COM_b09FwDataAddr = 0x00000000; +int COM_b09FwDataLen = 0x0; +u32_t COM_b09FwRodataAddr = 0x0800900c; +int COM_b09FwRodataLen = 0x100; +u32_t COM_b09FwBssAddr = 0x08009180; +int COM_b09FwBssLen = 0x124; +u32_t COM_b09FwSbssAddr = 0x08009148; +int COM_b09FwSbssLen = 0x34; +u32_t COM_b09FwSDataAddr = 0x00000000; +int COM_b09FwSDataLen = 0x0; +u32_t COM_b09FwText[(0x900c/4) + 1] = { +0xa000046, +0x0, 0x0, 0xd, 0x636f6d36, +0x2e322e36, 0x0, 0x6020602, 0x0, +0x3, 0xc8, 0x32, 0x3, +0x0, 0x0, 0x0, 0x0, +0x0, 0x10, 0x136, 0xea60, +0x5, 0x0, 0x0, 0x0, +0x8, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x2, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x10, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x10000003, 0x0, +0xd, 0xd, 0x3c020801, 0x24429148, +0x3c030801, 0x246392a4, 0xac400000, 0x43202b, +0x1480fffd, 0x24420004, 0x3c1d0800, 0x37bd9ffc, +0x3a0f021, 0x3c100800, 0x26100118, 0x3c1c0801, +0x279c9148, 0xe000259, 0x0, 0xd, +0x27bdffb4, 0xafa10000, 0xafa20004, 0xafa30008, +0xafa4000c, 0xafa50010, 0xafa60014, 0xafa70018, +0xafa8001c, 0xafa90020, 0xafaa0024, 0xafab0028, +0xafac002c, 0xafad0030, 0xafae0034, 0xafaf0038, +0xafb8003c, 0xafb90040, 0xafbc0044, 0xafbf0048, +0xe0023e2, 0x0, 0x8fbf0048, 0x8fbc0044, +0x8fb90040, 0x8fb8003c, 0x8faf0038, 0x8fae0034, +0x8fad0030, 0x8fac002c, 0x8fab0028, 0x8faa0024, +0x8fa90020, 0x8fa8001c, 0x8fa70018, 0x8fa60014, +0x8fa50010, 0x8fa4000c, 0x8fa30008, 0x8fa20004, +0x8fa10000, 0x27bd004c, 0x3c1b6010, 0x8f7a5030, +0x377b5028, 0x3400008, 0xaf7a0000, 0x3c060801, +0x8cc691fc, 0x3c080800, 0x8d080088, 0x10c80033, +0x0, 0x3c050801, 0x8ca59204, 0x10a0002f, +0x24030900, 0x3c028000, 0xac430020, 0x3c028008, +0x8c42006c, 0x3c040800, 0x8c8400f8, 0xc21823, +0x10640026, 0x83102b, 0x50400003, 0x831823, +0xd, 0x831823, 0xa3102b, 0x3c010801, +0xac239208, 0xc52021, 0x14400003, 0x3821, +0xa33823, 0xc32021, 0x861023, 0x4410003, +0x881023, 0xd, 0x881023, 0x4410007, +0x471021, 0x3c010801, 0xac2491fc, 0x3c010801, +0xac279204, 0xa0000bc, 0x0, 0x3c010801, +0xac2891fc, 0x3c010801, 0xac229204, 0x3c030801, +0x8c6391fc, 0x3c028008, 0x34420240, 0x24040900, +0x2821, 0xa0003b2, 0xac430008, 0x3e00008, +0x0, 0x8f820028, 0x27bdffe0, 0xafb00010, +0xafbf0018, 0xafb10014, 0x8c42000c, 0x3c108000, +0x8e110100, 0x10400034, 0x8fbf0018, 0xe001f68, +0x0, 0x8f850024, 0x24047fff, 0x91202b, +0xacb10000, 0x8e030104, 0x96020108, 0x31c00, +0x3042ffff, 0x621825, 0xaca30004, 0x9202010a, +0x96030114, 0x304200ff, 0x3063ffff, 0x21400, +0x431025, 0xaca20008, 0x9603010c, 0x9602010e, +0x31c00, 0x3042ffff, 0x621825, 0xaca3000c, +0x96030110, 0x96020112, 0x31c00, 0x3042ffff, +0x621825, 0xaca30010, 0x8e020118, 0xaca20014, +0x8e02011c, 0xaca20018, 0x14800008, 0x8f820028, +0x97820000, 0x3c042005, 0x441825, 0x24420001, +0xaca3001c, 0xa000100, 0xa7820000, 0x3c034018, +0x9442001e, 0x431025, 0xaca2001c, 0xe001f8f, +0x24040001, 0x8fbf0018, 0x8fb10014, 0x8fb00010, +0x1021, 0x3e00008, 0x27bd0020, 0x3c078000, +0x8ce202b8, 0x34e50100, 0x4410008, 0x24030001, +0x3c020800, 0x8c420060, 0x24420001, 0x3c010800, +0xac220060, 0x3e00008, 0x601021, 0x3c020800, +0x8c42005c, 0x8ca40020, 0x94a30016, 0x8ca60004, +0x94a5000e, 0x24420001, 0xace40280, 0x2463fffc, +0x3c010800, 0xac22005c, 0x3c021000, 0xa4e30284, +0xa4e50286, 0x1821, 0xace60288, 0xace202b8, +0x3e00008, 0x601021, 0x3c098000, 0x35260100, +0x8cc50000, 0x94c40008, 0x3c020800, 0x8c420044, +0x24a3fe00, 0x2c630381, 0x24480001, 0x30820002, +0x30870004, 0x2102b, 0x10600002, 0x529c2, +0x24a50004, 0x94c40014, 0x30a3000f, 0x31d00, +0x641825, 0xad230080, 0x3c010800, 0xac280044, +0x10e00003, 0x0, 0xa000108, 0x0, +0x3e00008, 0x0, 0x41880, 0x2782fed4, +0x621821, 0x410c0, 0x441023, 0x8c640000, +0x210c0, 0x3c030801, 0x24639234, 0x431021, +0x3c038000, 0xac640090, 0x3e00008, 0xaf820028, +0x3c020800, 0x8c420114, 0x10400025, 0x30844000, +0x30a2007f, 0x231c0, 0x3c020200, 0x10800020, +0xa24025, 0x3c040801, 0x8c849204, 0x3c020800, +0x8c420110, 0x3c030801, 0x8c639200, 0x3c070800, +0x8ce700f8, 0x862021, 0x661821, 0x24490001, +0xe4282b, 0x3c026020, 0xac480014, 0x3c010801, +0xac239200, 0x3c010801, 0xac249204, 0x10a00003, +0x603021, 0x3c010801, 0xac279204, 0x24020900, +0x3c038000, 0xac620020, 0x3c028008, 0xac460064, +0x3c010800, 0xac290110, 0x3e00008, 0x0, +0x3c026020, 0x3e00008, 0xac450014, 0x3e00008, +0x1021, 0x3e00008, 0x1021, 0x30a20008, +0x10400008, 0x24020100, 0x3c020800, 0x8c42010c, +0x24420001, 0x3c010800, 0xac22010c, 0x3e00008, +0x0, 0x14820008, 0x0, 0x3c020800, +0x8c4200fc, 0x24420001, 0x3c010800, 0xac2200fc, +0xa000199, 0x30a20020, 0x3c020800, 0x8c420084, +0x24420001, 0x3c010800, 0xac220084, 0x30a20020, +0x10400008, 0x30a20010, 0x3c020800, 0x8c420108, +0x24420001, 0x3c010800, 0xac220108, 0x3e00008, +0x0, 0x10400008, 0x0, 0x3c020800, +0x8c420104, 0x24420001, 0x3c010800, 0xac220104, +0x3e00008, 0x0, 0x3c020800, 0x8c420100, +0x24420001, 0x3c010800, 0xac220100, 0x3e00008, +0x0, 0x27bdffe0, 0xafb10014, 0x3c118000, +0xafb20018, 0xafbf001c, 0xafb00010, 0x36320100, +0x96500008, 0x32020004, 0x10400007, 0x32030002, +0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, +0xa000108, 0x27bd0020, 0x1060000b, 0x2002821, +0x8e240100, 0xe000180, 0x0, 0x32020080, +0x10400003, 0x240500a1, 0xe001e4e, 0x8e44001c, +0xa0001d9, 0x24020001, 0x8e230104, 0x8f820008, +0x10430006, 0x2002821, 0x8e240100, 0xe000180, +0x0, 0x8e220104, 0xaf820008, 0x1021, +0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, +0x3e00008, 0x27bd0020, 0x2c820004, 0x14400002, +0x1821, 0x2483fffd, 0x24020002, 0x621004, +0x3c036000, 0x3e00008, 0xac626914, 0x27bdffe0, +0xafbf001c, 0xafb20018, 0xafb10014, 0xafb00010, +0x3c068000, 0x94c20108, 0x30437000, 0x24022000, +0x1062000a, 0x28622001, 0x5440005f, 0x8fbf001c, +0x24024000, 0x10620055, 0x24026000, 0x10620057, +0x8fbf001c, 0xa000254, 0x8fb20018, 0x34c20100, +0x90430009, 0x8c500018, 0x9451000c, 0x24020009, +0x10620029, 0x9021, 0x28620009, 0x1440002e, +0x8f820028, 0x2402000a, 0x5062001f, 0x323100ff, +0x2402000b, 0x1062001c, 0x0, 0x2402000c, +0x14620025, 0x8f820028, 0x3c020801, 0x8c429204, +0x3c030801, 0x8c639200, 0x3c050800, 0x8ca500f8, +0x501021, 0x701821, 0xa2202b, 0x3c010801, +0xac239200, 0x3c010801, 0xac229204, 0x10800003, +0x24020900, 0x3c010801, 0xac259204, 0xacc20020, +0x3c030801, 0x8c639200, 0x3c028008, 0xac430064, +0xa000253, 0x8fbf001c, 0xe0001df, 0x102602, +0xa000233, 0x8f820028, 0xe0001df, 0x102602, +0x3c038008, 0x9462001a, 0x8c72000c, 0x3042ffff, +0x2028025, 0x8f820028, 0x8c42000c, 0x5040001e, +0x8fbf001c, 0xe001f68, 0x0, 0x3c028000, +0x34420100, 0x94430008, 0x8f820028, 0x31c00, +0x9444001e, 0x8f820024, 0x641825, 0xac500000, +0x24040001, 0xac510004, 0xac520008, 0xac40000c, +0xac400010, 0xac400014, 0xac400018, 0xe001f8f, +0xac43001c, 0xa000253, 0x8fbf001c, 0xe001141, +0x0, 0xa000253, 0x8fbf001c, 0xe001e86, +0x0, 0x8fbf001c, 0x8fb20018, 0x8fb10014, +0x8fb00010, 0x1021, 0x3e00008, 0x27bd0020, +0x27bdffd8, 0xafb40020, 0x3c036010, 0xafbf0024, +0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, +0x8c645000, 0x2402ff7f, 0x3c140801, 0x26949180, +0x822024, 0x3484380c, 0xac645000, 0x3c028000, +0x24030037, 0xe00234e, 0xac430008, 0x3c070800, +0x24e705f0, 0x2801021, 0x2404001d, 0x2484ffff, +0xac470000, 0x481fffd, 0x24420004, 0x3c020800, +0x244207a0, 0x3c010801, 0xac229188, 0x3c020800, +0x2442049c, 0x3c010801, 0xac22918c, 0x3c020800, +0x2442322c, 0x3c010801, 0xac229194, 0x3c020800, +0x24422cf4, 0x3c010801, 0xac2291a4, 0x3c020800, +0x244206c8, 0x3c010801, 0xac2291ac, 0x3c020800, +0x24421070, 0x3c010801, 0xac2291b0, 0x3c020800, +0x24423134, 0x3c010801, 0xac2291b4, 0x3c020800, +0x24422e24, 0x3c010801, 0xac2291bc, 0x3c020800, +0x24422ef4, 0x3c030800, 0x246305f8, 0x3c040800, +0x24841700, 0x3c050800, 0x24a525ac, 0x3c060800, +0x24c67420, 0x3c010801, 0xac2291c0, 0x3c020800, +0x24420318, 0x3c010801, 0xac25919c, 0x3c010801, +0xac2491a0, 0x3c010801, 0xac2291c8, 0x3c010801, +0xac2791cc, 0x3c010801, 0xac2691dc, 0x3c010801, +0xac2391e4, 0x3c010801, 0xac239184, 0x3c010801, +0xac249190, 0x3c010801, 0xac259198, 0x3c010801, +0xac2091a8, 0x3c010801, 0xac2091b8, 0x3c010801, +0xac2791c4, 0x3c010801, 0xac2691d8, 0x3c010801, +0xac2391e0, 0xe001767, 0x0, 0x3c028000, +0x34420070, 0x8c420000, 0xaf820014, 0x3c028000, +0x8c530000, 0x8f830004, 0x3c020800, 0x8c420020, +0x10620020, 0x0, 0x8821, 0x2792fed4, +0x3c100801, 0x26109234, 0x3c020800, 0x8c420020, +0x24050001, 0x2251804, 0x432024, 0x8f820004, +0x431024, 0x5044000c, 0x26310001, 0x10800008, +0xaf900028, 0x8e430000, 0x3c028000, 0xac430090, +0xe001f32, 0xae05000c, 0xa0002e3, 0x26310001, +0xae00000c, 0x26310001, 0x2e220002, 0x26100038, +0x1440ffe9, 0x26520004, 0x3c020800, 0x8c420020, +0xaf820004, 0x3c020800, 0x8c420114, 0x1040001b, +0x3c098000, 0x3c050801, 0x90a591f8, 0x14a00012, +0x32620001, 0x3c060800, 0x8cc600f8, 0x10c0000e, +0x3c048008, 0x34a50001, 0x24030900, 0x3c028000, +0xac430020, 0x3c010801, 0xac269204, 0x3c010801, +0xa02591f8, 0xac860064, 0xac80006c, 0x3c010801, +0xac269200, 0x32620001, 0x14400004, 0x3c098000, +0xe00008c, 0x0, 0x3c098000, 0x352a0070, +0x8d480000, 0x8f840014, 0x3c070800, 0x8ce700bc, +0x3c060800, 0x8cc600b8, 0x1042023, 0xe43821, +0x1021, 0xe4202b, 0xc23021, 0xc43021, +0x32650007, 0x3c010800, 0xac2700bc, 0xaf880014, +0x3c010800, 0xac2600b8, 0x10a0ffa9, 0x3c028000, +0x8d460000, 0x3c050800, 0x8ca500bc, 0x3c040800, +0x8c8400b8, 0xc83023, 0xa62821, 0x1021, +0xa6302b, 0x822021, 0x862021, 0x32670001, +0x3c010800, 0xac2500bc, 0x3c010800, 0xac2400b8, +0x10e00033, 0x32620002, 0x8d220100, 0x2021, +0xad220020, 0x8d230104, 0x2c420781, 0x10400008, +0xad2300a8, 0x95220108, 0x24032000, 0x30427000, +0x14430003, 0x3c028008, 0x90420005, 0x304400ff, +0xe000143, 0x0, 0x3c028000, 0x9042010b, +0x304300ff, 0x2c62001e, 0x54400004, 0x31080, +0xe00017c, 0xa00034c, 0x0, 0x541021, +0x8c420000, 0x40f809, 0x0, 0x10400005, +0x3c028000, 0x94440108, 0x8c450104, 0xe000151, +0x3084ffff, 0x3c020800, 0x8c420114, 0x10400003, +0x0, 0xe00008c, 0x0, 0x3c020800, +0x8c420034, 0x3c044000, 0x3c038000, 0x24420001, +0xac640138, 0x3c010800, 0xac220034, 0x32620002, +0x10400010, 0x32620004, 0x3c108000, 0x8e020140, +0x2021, 0xe000143, 0xae020020, 0xe000cf9, +0x0, 0x3c024000, 0xae020178, 0x3c020800, +0x8c420038, 0x24420001, 0x3c010800, 0xac220038, +0x32620004, 0x1040ff4e, 0x3c028000, 0x3c108000, +0x8e020180, 0x2021, 0xe000143, 0xae020020, +0x8e030180, 0x24020f00, 0x54620007, 0x3c028008, +0x8e020188, 0x3c0300e0, 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0x8fb00010, 0x3e00008, +0x27bd0020, 0x3c036010, 0x3c020800, 0x24420174, +0xac62502c, 0x8c625000, 0x3c048000, 0x34420080, +0xac625000, 0x3c020801, 0x24428ef4, 0x3c010801, +0xac229140, 0x3c020801, 0x24428eb0, 0x3c010801, +0xac229144, 0x3c020002, 0xac840008, 0xac82000c, +0x3e00008, 0x24020001, 0xa03021, 0x3c1c0801, +0x279c9148, 0x3c020002, 0x3c050400, 0x852826, +0x822026, 0x4102b, 0x2ca50001, 0x2c840001, +0x21080, 0x3c030801, 0x24639140, 0x852025, +0x431821, 0x10800003, 0x1021, 0xac660000, +0x24020001, 0x3e00008, 0x0, 0x3c1c0801, +0x279c9148, 0x3c020002, 0x3c050400, 0x852826, +0x822026, 0x4102b, 0x2ca50001, 0x2c840001, +0x21080, 0x3c030801, 0x24639140, 0x852025, +0x431821, 0x10800005, 0x1021, 0x3c020801, +0x24428eb0, 0xac620000, 0x24020001, 0x3e00008, +0x0, 0x3c020002, 0x3c030400, 0x821026, +0x831826, 0x2c420001, 0x2c630001, 0x431025, +0x1040000b, 0x2821, 0x3c1c0801, 0x279c9148, +0x3c038000, 0x8c620008, 0x24050001, 0x431025, +0xac620008, 0x8c62000c, 0x441025, 0xac62000c, +0x3e00008, 0xa01021, 0x3c1c0801, 0x279c9148, +0x3c058000, 0x8ca3000c, 0x42027, 0x24020001, +0x641824, 0x3e00008, 0xaca3000c, 0x3c020002, +0x14820006, 0x3c056000, 0x8ca208d0, 0x2403fffe, +0x431024, 0x3e00008, 0xaca208d0, 0x3c020400, +0x14820005, 0x0, 0x8ca208d0, 0x2403fffd, +0x431024, 0xaca208d0, 0x3e00008, 0x0, +0x3c02601a, 0x34420010, 0x8c430080, 0x27bdfff8, +0x8c440084, 0xafa30000, 0x93a30000, 0x24020004, +0x1462001a, 0xafa40004, 0x93a20001, 0x10400007, +0x97a30002, 0x3062fffc, 0x3c038000, 0x431021, +0x8c420000, 0xa0023d4, 0xafa20004, 0x3062fffc, +0x3c038000, 0x431021, 0xac440000, 0xa3a00000, +0x3c056000, 0x8ca208d0, 0x2403fffe, 0x3c04601a, +0x431024, 0xaca208d0, 0x8fa30004, 0x8fa20000, +0x34840010, 0xac830084, 0xac820080, 0x3e00008, +0x27bd0008, 0x27bdffe8, 0xafbf0010, 0x3c1c0801, +0x279c9148, 0x3c028000, 0x8c43000c, 0x8c420004, +0x431824, 0x3c020002, 0x10600014, 0x622824, +0x3c020400, 0x3c040002, 0x10a00005, 0x621024, +0x3c020801, 0x8c429140, 0xa0023f9, 0x0, +0x10400007, 0x3c040400, 0x3c020801, 0x8c429144, +0x40f809, 0x0, 0xa0023fe, 0x0, +0xd, 0x3c1c0801, 0x279c9148, 0x8fbf0010, +0x3e00008, 0x27bd0018, 0x0 }; +u32_t COM_b09FwData[(0x0/4) + 1] = { 0x0 }; +u32_t COM_b09FwRodata[(0x100/4) + 1] = { +0x80080240, +0x80080100, 0x80080080, 0x80080000, 0xc80, +0x3200, 0x80032c4, 0x80032c4, 0x80033bc, +0x80033bc, 0x80032cc, 0x80032d4, 0x80033bc, +0x80032dc, 0x80032e4, 0x8003300, 0x8003364, +0x8003398, 0x8003378, 0x8003478, 0x80036fc, +0x8003790, 0x8003834, 0x8003978, 0x8003d0c, +0x8003d14, 0x8003cc8, 0x8003d14, 0x8003d18, +0x8003d14, 0x8003ce0, 0x8003d14, 0x8003d0c, +0x8003d14, 0x8003d0c, 0x8005510, 0x8005530, +0x8005530, 0x8005530, 0x8005530, 0x8005530, +0x8005468, 0x8005530, 0x80054ac, 0x8005530, +0x8005418, 0x8005530, 0x8005530, 0x8005530, +0x800542c, 0x8005490, 0x80054a0, 0x8005634, +0x80054a0, 0x8005634, 0x80054a0, 0x80054a0, +0x80054a0, 0x8005498, 0x80054a0, 0x80054f8, +0x80080100, 0x80080080, 0x80080000, 0x0 }; +u32_t COM_b09FwBss[(0x124/4) + 1] = { 0x0 }; +u32_t COM_b09FwSbss[(0x34/4) + 1] = { 0x0 }; +u32_t COM_b09FwSdata[(0x0/4) + 1] = { 0x0 }; +/* 4.0.4 */ +#include "bcmtype.h" +int RXP_b09FwReleaseMajor = 0x1; +int RXP_b09FwReleaseMinor = 0x0; +int RXP_b09FwReleaseFix = 0x0; +u32_t RXP_b09FwStartAddr = 0x08003210; +u32_t RXP_b09FwTextAddr = 0x08000000; +int RXP_b09FwTextLen = 0x96d4; +u32_t RXP_b09FwDataAddr = 0x00000000; +int RXP_b09FwDataLen = 0x0; +u32_t RXP_b09FwRodataAddr = 0x080096d4; +int RXP_b09FwRodataLen = 0x338; +u32_t RXP_b09FwBssAddr = 0x08009ac8; +int RXP_b09FwBssLen = 0x1f4; +u32_t RXP_b09FwSbssAddr = 0x08009a40; +int RXP_b09FwSbssLen = 0x84; +u32_t RXP_b09FwSDataAddr = 0x00000000; +int RXP_b09FwSDataLen = 0x0; +u32_t RXP_b09FwText[(0x96d4/4) + 1] = { +0xa000c84, +0x0, 0x0, 0xd, 0x72787036, +0x2e322e36, 0x0, 0x6020603, 0x0, +0x1, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 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0xac8a0004, +0x3c050801, 0x90a59b96, 0x24020001, 0x10a2fe1e, +0x24a5ffff, 0xa002370, 0x9084000b, 0x184a023, +0x1a80fd8b, 0x0, 0x3c010801, 0xa02e9b95, +0xa002424, 0x240b0001, 0x3c010801, 0xa4259bba, +0xa0024d6, 0x8f880040, 0x240b0001, 0x106b0022, +0x8f980040, 0x8f850040, 0x90bf00ff, 0x33f900ff, +0x1079002b, 0x0, 0x3c1f0801, 0x93ff9b98, +0x1fc840, 0x33fc021, 0x18a080, 0x2887821, +0x91ee000a, 0xa08e000a, 0x8f8d0080, 0x3c030801, +0x90639b98, 0xcd8821, 0xa0024fc, 0xa223000b, +0x26300001, 0x6000031, 0x1a49023, 0x640002b, +0x24020003, 0x3c010801, 0xa02f9b95, 0xa002424, +0x240b0001, 0x8f890040, 0xa00235a, 0xad270054, +0xa0023b0, 0x24120001, 0x931400fd, 0xa094000b, +0x8f880040, 0x8f8f0080, 0x910e00fe, 0xcf6821, +0xa1ae000a, 0x8f910040, 0xa22700fd, 0x8f830078, +0x8f900040, 0xae030054, 0xa0024fd, 0x8f8d0080, +0x90b000fe, 0xa090000a, 0x8f8b0040, 0x8f8c0080, +0x916a00fd, 0xcc1021, 0xa04a000b, 0x8f840040, +0xa08700fe, 0x8f86007c, 0x8f850040, 0xaca60058, +0xa0024fd, 0x8f8d0080, 0x94b80008, 0xaca40004, +0x3037821, 0xa0023a4, 0xa4af0008, 0x3c010801, +0xa0229b95, 0xa0022e5, 0x0, 0x90cf0009, +0x240d0004, 0x31ee00ff, 0x11cdfd85, 0x24020001, +0x3c010801, 0xa0229b95, 0xa0022e5, 0x0, +0x0 }; +u32_t RXP_b09FwData[(0x0/4) + 1] = { 0x0 }; +u32_t RXP_b09FwRodata[(0x338/4) + 1] = { +0x8003bc8, 0x8003bc8, 0x8003ca4, +0x8003c78, 0x8003c5c, 0x8003bac, 0x8003bac, +0x8003bac, 0x8003bd0, 0x80080100, 0x80080080, +0x80080000, 0x80052a8, 0x80051f4, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80052a8, +0x80051fc, 0x80052a8, 0x80052cc, 0x80051fc, +0x8005218, 0x80051fc, 0x80051fc, 0x80052cc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80052ec, 0x80051fc, +0x80052ec, 0x80052a8, 0x80051fc, 0x80051fc, +0x80052ec, 0x80052ec, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80052ec, 0x80052ec, +0x80051fc, 0x80052ec, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80051fc, 0x80051fc, 0x80051fc, +0x80051fc, 0x80052fc, 0x80059f8, 0x8005da0, +0x8005d88, 0x8005d70, 0x8005d58, 0x8005d4c, +0x8005a28, 0x8005a28, 0x8005ca0, 0x8007ca8, +0x8007f0c, 0x8007cb4, 0x8007aa4, 0x8007cb4, +0x8007d40, 0x8007cb4, 0x8007aa4, 0x8007aa4, +0x8007aa4, 0x8007aa4, 0x8007aa4, 0x8007aa4, +0x8007aa4, 0x8007aa4, 0x8007aa4, 0x8007aa4, +0x8007cd4, 0x8007cc4, 0x8007aa4, 0x8007aa4, +0x8007aa4, 0x8007aa4, 0x8007aa4, 0x8007aa4, +0x8007aa4, 0x8007aa4, 0x8007aa4, 0x8007aa4, +0x8007aa4, 0x8007aa4, 0x8007cc4, 0x8008778, +0x8008604, 0x8008740, 0x8008604, 0x8008710, +0x80084ec, 0x8008604, 0x8008604, 0x8008604, +0x8008604, 0x8008604, 0x8008604, 0x8008604, +0x8008604, 0x8008604, 0x8008604, 0x8008604, +0x8008604, 0x800862c, 0x80091b0, 0x800930c, +0x80092ec, 0x8008d54, 0x80091c8, 0x0 }; +u32_t RXP_b09FwBss[(0x1f4/4) + 1] = { 0x0 }; +u32_t RXP_b09FwSbss[(0x84/4) + 1] = { 0x0 }; +u32_t RXP_b09FwSdata[(0x0/4) + 1] = { 0x0 }; +/* 4.0.4 */ +#include "bcmtype.h" +int CP_b09FwReleaseMajor = 0x1; +int CP_b09FwReleaseMinor = 0x0; +int CP_b09FwReleaseFix = 0x0; +u32_t CP_b09FwStartAddr = 0x080000a0; +u32_t CP_b09FwTextAddr = 0x08000000; +int CP_b09FwTextLen = 0x63f4; +u32_t CP_b09FwDataAddr = 0x08006580; +int CP_b09FwDataLen = 0x84; +u32_t CP_b09FwRodataAddr = 0x080063f4; +int CP_b09FwRodataLen = 0x164; +u32_t CP_b09FwBssAddr = 0x080066c0; +int CP_b09FwBssLen = 0x19c; +u32_t CP_b09FwSbssAddr = 0x08006610; +int CP_b09FwSbssLen = 0xb0; +u32_t CP_b09FwSDataAddr = 0x00000000; +int CP_b09FwSDataLen = 0x0; +u32_t CP_b09FwText[(0x63f4/4) + 1] = { +0xa000028, +0x0, 0x0, 0xd, 0x6370362e, +0x322e3600, 0x0, 0x6020604, 0x0, +0x0, 0x0, 0x0, 0x0, +0x38003c00, 0x0, 0x0, 0x0, +0x0, 0x20, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x21003800, 0x1, 0x2b, 0x0, +0x4, 0x30d40, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x10000003, 0x0, 0xd, 0xd, +0x3c020800, 0x2442660c, 0x3c030800, 0x2463685c, +0xac400000, 0x43202b, 0x1480fffd, 0x24420004, +0x3c1d0800, 0x37bd9ffc, 0x3a0f021, 0x3c100800, +0x261000a0, 0x3c1c0800, 0x279c660c, 0xe000319, +0x0, 0xd, 0x27bdffb4, 0xafa10000, +0xafa20004, 0xafa30008, 0xafa4000c, 0xafa50010, +0xafa60014, 0xafa70018, 0xafa8001c, 0xafa90020, +0xafaa0024, 0xafab0028, 0xafac002c, 0xafad0030, +0xafae0034, 0xafaf0038, 0xafb8003c, 0xafb90040, +0xafbc0044, 0xafbf0048, 0xe00087b, 0x0, +0x8fbf0048, 0x8fbc0044, 0x8fb90040, 0x8fb8003c, +0x8faf0038, 0x8fae0034, 0x8fad0030, 0x8fac002c, +0x8fab0028, 0x8faa0024, 0x8fa90020, 0x8fa8001c, +0x8fa70018, 0x8fa60014, 0x8fa50010, 0x8fa4000c, +0x8fa30008, 0x8fa20004, 0x8fa10000, 0x27bd004c, +0x3c1b6018, 0x8f7a5030, 0x377b5028, 0x3400008, +0xaf7a0000, 0xa01821, 0x801021, 0x802821, +0x3c046000, 0x3c076000, 0x24060008, 0x10600006, +0x34842078, 0x8c420000, 0xace22008, 0x8c630000, +0x3e00008, 0xace3200c, 0xa0011e1, 0x0, +0x24030040, 0x3c026000, 0x3e00008, 0xac432000, +0x3c076000, 0x8f860004, 0x8ce52074, 0x861021, +0xa2182b, 0x14600007, 0x2821, 0x8f8afdf0, +0x24050001, 0xa1440013, 0x8f890004, 0x1244021, +0xaf880004, 0x3e00008, 0xa01021, 0x8f84fdf0, +0x8f850004, 0x90860013, 0x30c300ff, 0xa31023, +0xaf820004, 0x3e00008, 0xa0800013, 0x8f84fdf0, +0x27bdffe8, 0xafb00010, 0xafbf0014, 0x90890011, +0x90870011, 0x24020028, 0x312800ff, 0x39060028, +0x30e300ff, 0x2485002c, 0x2cd00001, 0x10620016, +0x2484001c, 0xe00006e, 0x0, 0x8f8ffdf0, +0x3c056000, 0x24020204, 0x95ee003e, 0x95ed003c, +0xe5c00, 0x31acffff, 0x16c5025, 0xacaa2010, +0x52000001, 0x24020004, 0xaca22000, 0x0, +0x0, 0x0, 0x8fbf0014, 0x8fb00010, +0x3e00008, 0x27bd0018, 0xa0000a6, 0x2821, +0x8f85fdf0, 0x27bdffd8, 0xafbf0020, 0xafb3001c, +0xafb20018, 0xafb10014, 0xafb00010, 0x809821, +0x90a40011, 0x24b0001c, 0x24b1002c, 0x308300ff, +0x38620028, 0xe000090, 0x2c520001, 0xe000098, +0x0, 0x2002021, 0x12400002, 0x2202821, +0x2821, 0xe00006e, 0x0, 0x8f8dfdf0, +0x3c088000, 0x3c056000, 0x95ac003e, 0x95ab003c, +0x2683025, 0xc4c00, 0x316affff, 0x12a3825, +0xaca72010, 0x24020202, 0xaca62014, 0x52400001, +0x24020002, 0x8fbf0020, 0x8fb3001c, 0x8fb20018, +0x8fb10014, 0x8fb00010, 0x27bd0028, 0x3e00008, +0xaca22000, 0x27bdffe0, 0xafb20018, 0xafb10014, +0xafb00010, 0xafbf001c, 0x3c116000, 0x8e232074, +0x8f820004, 0x30d0ffff, 0x30f2ffff, 0x1062000c, +0x2406008f, 0xe00006e, 0x0, 0x3c06801f, +0x104400, 0x34c5ff00, 0x1123825, 0x24040002, +0xae272010, 0x3021, 0xae252014, 0xae242000, +0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, +0xc01021, 0x3e00008, 0x27bd0020, 0x27bdffe0, +0xafb00010, 0x30d0ffff, 0xafbf0018, 0xafb10014, +0xe00006e, 0x30f1ffff, 0x102400, 0x918025, +0x3c036000, 0xac702010, 0x8fbf0018, 0x8fb10014, +0x8fb00010, 0x24020004, 0xac622000, 0x27bd0020, +0x3e00008, 0x1021, 0x27bdffe0, 0x3c046018, +0xafbf0018, 0xafb10014, 0xafb00010, 0x8c885000, +0x2403ff7f, 0x34028071, 0x1033824, 0x34e5380c, +0x241f0031, 0x3c198000, 0xac855000, 0x3c11800a, +0xac8253bc, 0xaf3f0008, 0xe0005a7, 0xaf910044, +0xe000565, 0x3c116000, 0xe00007d, 0x0, +0x8e300808, 0x3c0f5709, 0x2418fff0, 0x2186024, +0x35eee000, 0x35edf000, 0x18e5026, 0x18d5826, +0x2d460001, 0x2d690001, 0xaf860050, 0xe000f69, +0xaf890054, 0x3c066016, 0x8cc70000, 0x3c086014, +0x8d0500a0, 0x3c03ffff, 0xe32024, 0x3c025353, +0x52fc2, 0x10820058, 0x34d07c00, 0x960201f2, +0xa7800070, 0x10400003, 0xa7800080, 0x384b1e1e, +0xa78b0070, 0x960201f8, 0x10400004, 0x8f8d0054, +0x384c1e1e, 0xa78c0080, 0x8f8d0054, 0x11a00005, +0x8f840050, 0x240e0020, 0xa78e0080, 0xa78e0070, +0x8f840050, 0x10800005, 0x97850080, 0x240f0020, +0xa78f0080, 0xa78f0070, 0x97850080, 0x2cb80081, +0x17000002, 0xa3800082, 0x24050080, 0x97830070, +0x2c710401, 0x16200002, 0xa03021, 0x24030400, +0x1080000a, 0x603821, 0x8fbf0018, 0x8fb10014, +0x8fb00010, 0x27bd0020, 0xa7830070, 0xa7860080, +0xa7800078, 0x3e00008, 0xa7800096, 0x3c026000, +0x8c440438, 0x2419103c, 0x309fffff, 0x53f90043, +0x93850082, 0x8e0400f0, 0x30880001, 0x15000027, +0x0, 0x93850082, 0x50a00040, 0xa7860080, +0xa7800080, 0x97830080, 0xa7800070, 0xa7800078, +0xa7800096, 0x3c010800, 0xac230080, 0xe0007e2, +0x0, 0x3c086000, 0x8d040808, 0x2402fff0, +0x3c19600e, 0x261f0388, 0x37310010, 0xc021, +0x7821, 0x823824, 0x3c105709, 0xaf9f0010, +0xaf91004c, 0xaf980018, 0x10f0003f, 0xaf8f0014, +0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x27bd0020, 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+0x2402ff80, 0xb11821, 0x67f821, 0x3e2f024, +0x33f8007f, 0x3c128000, 0x3c19800e, 0xae5e002c, +0x3197021, 0x91d0000d, 0x360f0004, 0xa1cf000d, +0xe001288, 0x24120001, 0x24110001, 0x3c1e8000, +0x8fc40100, 0xe00122e, 0x2e02821, 0x8fc40100, +0xe00123e, 0x2c02821, 0x1620ff55, 0x8f8b00ac, +0xa0014e6, 0x13802b, 0x8f8600ac, 0x90c80001, +0x31040020, 0x10800191, 0x24100001, 0x3c048008, +0x348b0080, 0x916a007c, 0x8f9e0034, 0xafa0002c, +0x31490001, 0x1120000f, 0xafb00028, 0x8ccd0014, +0x8c8e0060, 0x1ae602b, 0x15800002, 0x1a03821, +0x8c870060, 0x3c188008, 0x37030080, 0x8c700070, +0xf0782b, 0x15e00002, 0xe02021, 0x8c640070, +0xafa4002c, 0x3c028008, 0x34450080, 0x8cd20014, +0x8cbf0070, 0x25fc82b, 0x17200002, 0x2402021, +0x8ca40070, 0x8fa7002c, 0x871823, 0x10600003, +0xafa30030, 0x24050002, 0xafa50028, 0x8fa40028, +0x264882b, 0x162000ba, 0x1821, 0x8cd00038, +0x8fce000c, 0x3c0f0080, 0xafd00000, 0x8ccd0034, +0x3c0cff9f, 0x1cf5825, 0xafcd0004, 0x90ca003f, +0x3586ffff, 0x1662024, 0x3c090020, 0x3c08ffef, +0xa3ca000b, 0x893825, 0x3511ffff, 0xf11824, +0x3c050008, 0x8f8700ac, 0x65c825, 0xafd9000c, +0x8ce20014, 0xafc00018, 0x8fa60030, 0xafc20014, +0x8cf80018, 0x8fb0002c, 0x3c1ffffb, 0xafd8001c, +0x8cef0008, 0x37f2ffff, 0x3326824, 0xafcf0024, +0x8cec000c, 0x2067021, 0xafcd000c, 0xa7c00038, +0xa7c0003a, 0xafce002c, 0xafcc0020, 0xafc00028, +0x8cea0014, 0x8fab002c, 0x14b4823, 0x1264023, +0x11000011, 0xafc80010, 0x90eb003d, 0x8fc90004, +0x8fc80000, 0xb5100, 0x12a2821, 0x1021, +0xaa882b, 0x1021821, 0x71f821, 0xafc50004, +0xafdf0000, 0x90f2003d, 0xa3d2000a, 0x8f9900ac, +0x97380006, 0xa7d80008, 0x8f910038, 0x24080002, +0x3c038008, 0xa2280000, 0x34650080, 0x94bf005c, +0x8fa4002c, 0x33f0ffff, 0xe001254, 0x8f920038, +0x2cb80, 0x8f8500ac, 0x2197825, 0x3c184200, +0x1f87025, 0xae4e0004, 0x8f840038, 0x8cad0038, +0xac8d0018, 0x8cac0034, 0xac8c001c, 0xac80000c, +0xac800010, 0xa4800014, 0xa4800016, 0xa4800020, +0xa4800022, 0xac800024, 0x90a6003f, 0x8fa7002c, +0xa4860002, 0x50e00192, 0x24070001, 0x8fa20030, +0x50400002, 0x90a2003d, 0x90a2003e, 0x244a0001, +0xa08a0001, 0x8f840038, 0x8fa9002c, 0xac890008, +0x3c128008, 0x364d0080, 0x91ac007c, 0x31860002, +0x14c00002, 0x24070034, 0x24070030, 0x8f8500ac, +0x3c198008, 0x373f0080, 0x90b00000, 0x93f9007c, +0x240e0004, 0xa0900030, 0x8f8f00ac, 0x8fb8002c, +0x8f8d0038, 0x91f20001, 0x33040003, 0x1c46023, +0xa1b20031, 0x8f8e0038, 0x8f8600ac, 0x2402c000, +0x95ca0032, 0x94c90012, 0x8fab002c, 0x1424024, +0x31233fff, 0x1038825, 0xa5d10032, 0x91d00032, +0x31850003, 0xebf821, 0x3218003f, 0x370f0040, +0xa1cf0032, 0x8fa4002c, 0x3e53821, 0x33280004, +0x10800002, 0x8f850038, 0xe83821, 0x3c0a8008, +0xaca70034, 0x35490100, 0x8d2800d0, 0x8fa3002c, +0x2419ffbf, 0xaca80038, 0x90b1003c, 0x2c640001, +0x240fffdf, 0x3227007f, 0xa0a7003c, 0x8f980038, +0x49140, 0x931f003c, 0x3f98024, 0xa310003c, +0x8f8c0038, 0x918e003c, 0x1cf6824, 0x1b23025, +0xa186003c, 0x8f8900ac, 0x8f880038, 0x8d2b0020, +0xad0b0040, 0x8d220024, 0xad020044, 0x8d2a0028, +0xad0a0048, 0x8d23002c, 0xe001273, 0xad03004c, +0x8fb10028, 0x24070002, 0x12270011, 0x8fa30028, +0x3282b, 0x58023, 0x2709824, 0x608021, +0x609021, 0xa0014cf, 0x10882b, 0x96290012, +0x8f8400a8, 0x9021, 0x3125ffff, 0xa7a90018, +0xe001222, 0x24110001, 0xa00157d, 0x3c1e8000, +0x3c0b8000, 0x3c128008, 0x8d640100, 0x92490008, +0x8f92ff28, 0xe0011f9, 0x3125007f, 0x8f990038, +0x8fa70028, 0x8fa40030, 0xa3270000, 0x965f005c, +0x33f0ffff, 0xe001254, 0x8f910038, 0x26b80, +0x20d8025, 0x3c084200, 0x8f8d00ac, 0x2085025, +0xae2a0004, 0x8da50038, 0x8f8a0038, 0x7821, +0xf1100, 0xad450018, 0x8db80034, 0x3c047fff, +0x3488ffff, 0xad58001c, 0x91a6003e, 0x8d4c001c, +0x8d490018, 0x61900, 0x67702, 0x183c821, +0x4e5825, 0x323882b, 0x12b3821, 0xf1f821, +0xad59001c, 0xad5f0018, 0xad40000c, 0xad400010, +0x91b0003e, 0x8fa40030, 0x24090005, 0xa5500014, +0x95a50004, 0x2419c000, 0x884024, 0xa5450016, +0x91b8003e, 0xa5580020, 0x95af0004, 0xa54f0022, +0xad400024, 0x91ae003f, 0xa54e0002, 0x91a6003e, +0x91ac003d, 0x1861023, 0x244b0001, 0xa14b0001, +0x8f910038, 0x8fa30030, 0x3c028008, 0x344b0100, +0xae230008, 0xa2290030, 0x8f8c0038, 0x8f8700ac, +0x959f0032, 0x94f00012, 0x2407ffbf, 0x33fc024, +0x32053fff, 0x3057825, 0xa58f0032, 0x918e0032, +0x2418ffdf, 0x31cd003f, 0x35a60040, 0xa1860032, +0x8f910038, 0x240dffff, 0x240cff80, 0xae200034, +0x8d6a00d0, 0xae2a0038, 0x9223003c, 0x3069007f, +0xa229003c, 0x8f900038, 0x3c038000, 0x9219003c, +0x327f824, 0xa21f003c, 0x8f8e0038, 0x91c5003c, +0xb87824, 0xa1cf003c, 0x8f8a0038, 0x3c0e8008, +0xad4d0040, 0x8fa6002c, 0xad460044, 0x91420048, +0x4c5825, 0xa14b0048, 0x8f900038, 0x8f9900ac, +0x8e090048, 0x1238824, 0x2283825, 0xae070048, +0x933f003e, 0xa21f004c, 0x8f9800ac, 0x8f8f0038, +0x97050004, 0xa5e5004e, 0xe0003e9, 0x8dc50060, +0x9246007c, 0x8fac0030, 0x26940, 0x29100, +0x402821, 0x30cb0002, 0x1b21021, 0x156000aa, +0x1823021, 0x3c0e8008, 0x35c20080, 0x904c007c, +0x31830004, 0x10600003, 0x8fb90030, 0x57880, +0xcf3021, 0x241f0004, 0x8f910038, 0x332d0003, +0x3ed8023, 0x32080003, 0xc85021, 0xae2a0034, +0x3c188000, 0xa7c50038, 0x3c068008, 0x8f040100, +0x90de0008, 0xe00123e, 0x33c5007f, 0xe001273, +0x0, 0xa00166d, 0x8fa30028, 0x8f980034, +0x8cc90038, 0x241f0003, 0xa7000008, 0xaf090000, +0x8cc50034, 0xa300000a, 0x8f9900ac, 0xaf050004, +0x3c080080, 0x932d003f, 0xa31f000c, 0x8f0a000c, +0x3c02ff9f, 0xa30d000b, 0x148f025, 0x3451ffff, +0x3c12ffef, 0x8f9900ac, 0x3d17024, 0x3646ffff, +0x1c61824, 0xaf03000c, 0x8f2c0014, 0x97290012, +0x8f8400a8, 0xaf0c0010, 0x8f2f0014, 0xaf000018, +0xaf000020, 0xaf0f0014, 0xaf000024, 0x8f270018, +0x312f3fff, 0xf5980, 0xaf070028, 0x8f250008, +0x164f821, 0x312d0001, 0xaf050030, 0x8f31000c, +0x8f920038, 0x1f51c2, 0xd4380, 0x1481021, +0x241e0002, 0x3c068008, 0xa702001c, 0xa7000034, +0xaf11002c, 0xa25e0000, 0x34d20080, 0x964e005c, +0x8f990038, 0x3c034200, 0x31ccffff, 0x1833825, +0xaf270004, 0x8f8b00ac, 0x24050001, 0x2402c000, +0x8d640038, 0x24070034, 0xaf240018, 0x8d690034, +0xaf29001c, 0xaf20000c, 0xaf200010, 0xa7200014, +0xa7200016, 0xa7200020, 0xa7200022, 0xaf200024, +0xa7300002, 0xa3250001, 0x8f880038, 0x8f9f00ac, +0xad100008, 0x93ed0000, 0xa10d0030, 0x8f8a00ac, +0x8f980038, 0x91510001, 0xa3110031, 0x8f8b0038, +0x957e0032, 0x3c27024, 0x1cf6025, 0xa56c0032, +0x91630032, 0x3064003f, 0xa1640032, 0x9249007c, +0x31250002, 0x14a00002, 0x8f840038, 0x24070030, +0x3c198008, 0xac870034, 0x37320100, 0x8e5f00d0, +0x240affbf, 0x2009021, 0xac9f0038, 0x908d003c, +0x31a8007f, 0xa088003c, 0x8f9e0038, 0x93c2003c, +0x4a8824, 0xa3d1003c, 0x8f830038, 0x10882b, +0x9066003c, 0x34ce0020, 0xa06e003c, 0x8f8400ac, +0x8f980038, 0x8c8c0020, 0xaf0c0040, 0x8c8f0024, +0xaf0f0044, 0x8c870028, 0xaf070048, 0x8c8b002c, +0xaf0b004c, 0xe001273, 0x3c1e8000, 0xa0014d0, +0x0, 0x94c80052, 0x3c0a0800, 0x8d4a0024, +0x1488821, 0xa4d10052, 0xa001479, 0x8fb40010, +0xa0870001, 0x8f840038, 0x240b0001, 0xac8b0008, +0xa00161e, 0x3c128008, 0x52080, 0xa001702, +0xc43021, 0x27bdffe0, 0x3c0d8008, 0xafb20018, +0xafb00010, 0xafbf001c, 0xafb10014, 0x35b20080, +0x8e4c0018, 0x35a80100, 0x964b0006, 0x95a70050, +0x910900fc, 0xc5602, 0x1672823, 0x3143007f, +0x312600ff, 0x24020003, 0xaf8300b0, 0xaf8400a8, +0x10c2001b, 0x30b0ffff, 0x910600fc, 0x24120005, +0x30c200ff, 0x10520033, 0x0, 0x16000009, +0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, +0x240d0c00, 0x3c0c8000, 0x27bd0020, 0x3e00008, +0xad8d0024, 0xe00145b, 0x2002021, 0x8fbf001c, +0x8fb20018, 0x8fb10014, 0x8fb00010, 0x240d0c00, +0x3c0c8000, 0x27bd0020, 0x3e00008, 0xad8d0024, +0x96580078, 0x9651007a, 0x924e007d, 0x2387826, +0x31e8ffff, 0x31c400c0, 0x14800009, 0x2d110001, +0x16000037, 0x0, 0x5620ffe2, 0x8fbf001c, +0xe001331, 0x0, 0xa0017ca, 0x8fbf001c, +0x1620ffda, 0x0, 0xe001331, 0x0, +0x1440ffd8, 0x8fbf001c, 0x16000022, 0x0, +0x925f007d, 0x33e2003f, 0xa242007d, 0xa0017ca, +0x8fbf001c, 0x950900ea, 0x8f860084, 0x802821, +0x24040005, 0xe000780, 0x3130ffff, 0x97830096, +0x3c048000, 0x2465ffff, 0xa7850096, 0x8c8a01b8, +0x540fffe, 0x0, 0xac800180, 0x8fbf001c, +0xac900184, 0x8fb20018, 0x8fb10014, 0x8fb00010, +0x3c076013, 0x3c0b1000, 0x240d0c00, 0x3c0c8000, +0x27bd0020, 0xac870188, 0xac8b01b8, 0x3e00008, +0xad8d0024, 0xe00145b, 0x2002021, 0x5040ffb1, +0x8fbf001c, 0x925f007d, 0xa0017f7, 0x33e2003f, +0xe00145b, 0x2002021, 0x1440ffaa, 0x8fbf001c, +0x12200007, 0x0, 0x9259007d, 0x3330003f, +0x36020040, 0xa242007d, 0xa0017ca, 0x8fbf001c, +0xe001331, 0x0, 0x5040ff9e, 0x8fbf001c, +0x9259007d, 0x3330003f, 0xa001826, 0x36020040, +0x411c0, 0x3e00008, 0x24420240, 0x3c050006, +0x851025, 0x3c038000, 0xac620030, 0x0, +0x0, 0x0, 0x3c058000, 0x8ca70000, +0x30e60010, 0x10c0fffd, 0x0, 0x8cab003c, +0x8caa003c, 0x1644821, 0x12a402b, 0x11000004, +0x3c068000, 0x8cad0038, 0x25ac0001, 0xacac0038, +0x8ccf003c, 0x1e47021, 0x3e00008, 0xacce003c, +0x27bdffd0, 0xafb20018, 0xafb00010, 0xafbf0028, +0xafb50024, 0xafb40020, 0xafb3001c, 0xafb10014, +0xa09021, 0x14a00012, 0x808021, 0x8f82003c, +0x21880, 0x14600037, 0x24040010, 0xe001834, +0x0, 0x8fbf0028, 0x8fb50024, 0x8fb40020, +0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, +0x1021, 0x27bd0030, 0x3e00008, 0xaf80003c, +0x10a0001e, 0x8821, 0x3c138000, 0x24140020, +0xa001873, 0x3c150005, 0x26310004, 0x232502b, +0x11400017, 0x2401021, 0x8f88003c, 0x8e070000, +0x24040080, 0x84880, 0x1331821, 0x25060001, +0xac670400, 0x26100004, 0x14d4fff3, 0xaf86003c, +0xe001834, 0x0, 0xae750030, 0x0, +0x0, 0x0, 0x0, 0x26310004, +0x232502b, 0x1540ffec, 0xaf80003c, 0x2401021, +0x8fbf0028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, +0x8fb20018, 0x8fb10014, 0x8fb00010, 0x3e00008, +0x27bd0030, 0x32023, 0x3085000f, 0xa00185c, +0x652021, 0x27bdffd8, 0x3c038000, 0xa03821, +0xac670038, 0xafb10014, 0xac66003c, 0x808821, +0x3c060022, 0xac660030, 0xafb00010, 0xac710028, +0x3c10800c, 0x3c04800c, 0x24050070, 0xafbf0024, +0xafb40020, 0xafb3001c, 0xe00184d, 0xafb20018, +0x26040080, 0xe00184d, 0x24050080, 0x26040100, +0xe00184d, 0x24050100, 0x3c020800, 0x8c420064, +0x10400013, 0x8021, 0x3c148000, 0x2413ff80, +0x3c12800c, 0xe001831, 0x2002021, 0x514821, +0x312a007f, 0x1334024, 0x1522021, 0x24050050, +0xae880028, 0xe00184d, 0x26100001, 0x3c050800, +0x8ca50064, 0x205202b, 0x1480fff2, 0x0, +0x3c060800, 0x8cc60060, 0x10c00015, 0x8021, +0x3c148000, 0x2413ff80, 0x3c12800c, 0x3c190800, +0x8f390058, 0x10c180, 0x24050040, 0x3317821, +0x1f86821, 0x31ae007f, 0x1b36024, 0x1d22021, +0xae8c0028, 0xe00184d, 0x26100001, 0x3c060800, +0x8cc60060, 0x206582b, 0x1560fff0, 0x0, +0x3c100800, 0x8e10005c, 0x2414ff80, 0x3c1f800c, +0x2119821, 0x2749024, 0x3262007f, 0x3c118000, +0x5f2021, 0xae320028, 0xe00184d, 0x62840, +0x8fbf0024, 0x8fb40020, 0x8fb3001c, 0x8fb20018, +0x8fb10014, 0x8fb00010, 0x2021, 0x2821, +0xa00184d, 0x27bd0028, 0x8f83005c, 0x8c620004, +0x10400003, 0x0, 0x3e00008, 0x0, +0x8c640010, 0x8c650008, 0xa001896, 0x8c66000c, +0x0 }; +u32_t CP_b09FwData[(0x84/4) + 1] = { +0x0, +0x1b, 0xf, 0xa, 0x8, +0x6, 0x5, 0x5, 0x4, +0x4, 0x3, 0x3, 0x3, +0x3, 0x3, 0x2, 0x2, +0x2, 0x2, 0x2, 0x2, +0x2, 0x2, 0x2, 0x2, +0x2, 0x2, 0x2, 0x2, +0x2, 0x1, 0x1, 0x1, +0x0 }; +u32_t CP_b09FwRodata[(0x164/4) + 1] = { +0x80080100, 0x80080080, 0x80080000, +0xc00, 0x3080, 0x8001370, 0x800141c, +0x8001434, 0x8001448, 0x8001370, 0x8001370, +0x8001370, 0x800145c, 0x8001498, 0x80014ac, +0x80014f4, 0x8001bf8, 0x8001bf8, 0x8001c30, +0x8001c30, 0x8001c44, 0x8001c14, 0x8001e6c, +0x8001e38, 0x8001ec4, 0x8001ec4, 0x8001f4c, +0x8001e7c, 0x80080240, 0x8002cc4, 0x8002ca4, +0x8002c80, 0x8002b20, 0x8002a90, 0x8002a10, +0x80029c8, 0x8002998, 0x8003148, 0x8003420, +0x8002940, 0x8002940, 0x8003340, 0x80033cc, +0x80033cc, 0x8002940, 0x8003388, 0x80033e4, +0x8002940, 0x80032f0, 0x8002940, 0x8002940, +0x80030ec, 0x8002940, 0x8002940, 0x8002940, +0x8002940, 0x8002940, 0x8002940, 0x8002940, +0x8002940, 0x8002940, 0x8002940, 0x8003030, +0x8002940, 0x8002f48, 0x8002df4, 0x80029bc, +0x8002940, 0x800293c, 0x8002ff4, 0x8002f80, +0x8004664, 0x8004638, 0x8004604, 0x80045d8, +0x80045b8, 0x800456c, 0x80080100, 0x80080080, +0x80080000, 0x80080080, 0x80055e4, 0x800561c, +0x8005564, 0x80055e4, 0x80055e4, 0x8005338, +0x80055e4, 0x80059d0, 0x0 }; +u32_t CP_b09FwBss[(0x19c/4) + 1] = { 0x0 }; +u32_t CP_b09FwSbss[(0xb0/4) + 1] = { 0x0 }; +u32_t CP_b09FwSdata[(0x0/4) + 1] = { 0x0 }; diff --git a/usr/src/boot/sys/boot/zfs/i386/Makefile b/usr/src/uts/common/io/bnx/bnx.conf index 3875f9abd2..cb19ea560a 100644 --- a/usr/src/boot/sys/boot/zfs/i386/Makefile +++ b/usr/src/uts/common/io/bnx/bnx.conf @@ -10,17 +10,10 @@ # # -# Copyright 2016 Toomas Soome <tsoome@me.com> -# Copyright 2016 RackTop Systems. +# Copyright (c) 2017 Joyent, Inc. # -MACHINE= $(MACH) - -all install: libzfsboot.a - -include ../Makefile.com - -CLEANFILES += x86 -CFLAGS += -m32 - -$(OBJS): machine x86 +# +# Driver.conf file for NetExtreme II 1 GbE parts. See bnx(7D) for valid +# options. +# diff --git a/usr/src/uts/common/io/bnx/bnx.h b/usr/src/uts/common/io/bnx/bnx.h new file mode 100644 index 0000000000..e1d53fa9d7 --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnx.h @@ -0,0 +1,435 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2019, Joyent, Inc. + */ + +#ifndef _BNX_H +#define _BNX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <sys/types.h> +#include <sys/stream.h> +#include <sys/stropts.h> +#include <sys/errno.h> +#include <sys/cred.h> +#include <sys/poll.h> +#include <sys/modctl.h> +#ifdef __10u7 +#include <sys/mac.h> +#else +#include <sys/mac_provider.h> +#endif +#include <sys/stat.h> +#include <sys/ddi.h> +#include <sys/sunddi.h> +#include <sys/pattr.h> +#include <sys/sysmacros.h> +#include <sys/ethernet.h> +#include <sys/strsun.h> +#include <netinet/in.h> +#include <netinet/ip.h> +#include <netinet/udp.h> +#include <inet/common.h> +#include <inet/ip.h> +#include <inet/ip_if.h> +#include <sys/strsubr.h> +#include <sys/pci.h> +#include <sys/kstat.h> + + + +/* + */ +#pragma weak hcksum_retrieve +#pragma weak hcksum_assoc + + +#include "listq.h" +#include "lm5706.h" +#include "54xx_reg.h" + +#define BNX_MAGIC 0x0feedead +#define BNX_STR_SIZE 32 + +#ifdef __sparc +#define BNX_DMA_ALIGNMENT 0x2000UL +#else +#define BNX_DMA_ALIGNMENT 0x1000UL +#endif + +#define BNX_MAX_SGL_ENTRIES 16 +#define BNX_MIN_BYTES_PER_FRAGMENT 32 + +#define FW_VER_WITH_UNLOAD_POWER_DOWN 0x01090003 + + +extern ddi_device_acc_attr_t bnxAccessAttribBAR; +extern ddi_device_acc_attr_t bnxAccessAttribBUF; +extern ddi_dma_attr_t bnx_std_dma_attrib; + + +typedef struct _bnx_memreq_t { + void * addr; + size_t size; +} bnx_memreq_t; + + + +/* + * Transmit queue info structure holds information regarding transmit resources. + * This consists of two list, one is a free list of transmit packets and another + * a list of pending packets (packets posted to ASIC for transmit). Upon + * receiving transmit complete notification from the asic, the message blocks + * are freed and and packet structure is moved to the free list. + */ + +typedef struct _um_xmit_qinfo { + ddi_dma_handle_t dcpyhndl; + ddi_acc_handle_t dcpyahdl; + caddr_t dcpyvirt; + lm_u64_t dcpyphys; + size_t dcpyhard; + + /* Packet descriptor memory. */ + u32_t desc_cnt; + bnx_memreq_t desc_mem; + + /* Low resource water marks. */ + u32_t thresh_pdwm; + + /* Free queue mutex */ + kmutex_t free_mutex; + + /* Packet descriptors that are free for use. */ + s_list_t free_tx_desc; + + /* Packet descriptors that have been setup and are awaiting xmit. */ + s_list_t tx_resc_que; +} um_xmit_qinfo; + + + +/* + * Receive queue is mostly managed by the LM (lm_dev->rx_info.chain[]). + * During initialization, UM allocates receive buffers and prepares the + * rx descriptions to posts the receive buffers. + */ +typedef struct _um_recv_qinfo { + volatile boolean_t processing; + + /* For packet descriptors that do not have rx buffers assigned. */ + s_list_t buffq; + + /* For packet descriptors waiting to be sent up. */ + s_list_t waitq; +} um_recv_qinfo; + + +typedef struct _os_param { + u32_t active_resc_flag; +#define DRV_RESOURCE_PCICFG_MAPPED 0x0001 +#define DRV_RESOURCE_MAP_REGS 0x0002 +#define DRV_RESOURCE_INTR_1 0x0004 +#define DRV_RESOURCE_MUTEX 0x0008 +#define DRV_RESOURCE_HDWR_REGISTER 0x0020 +#define DRV_RESOURCE_GLD_REGISTER 0x0040 +#define DRV_RESOURCE_KSTAT 0x0080 +#define DRV_RESOURCE_TIMER 0x0100 +#define DRV_RESOURCE_MINOR_NODE 0x0200 +#define DRV_LINK_TIMEOUT_CB 0x0400 + + dev_info_t *dip; + + ddi_acc_handle_t pci_cfg_handle; + ddi_acc_handle_t reg_acc_handle; + + mac_handle_t macp; + mac_resource_handle_t rx_resc_handle[NUM_RX_CHAIN]; + caddr_t regs_addr; + + kmutex_t gld_mutex; + krwlock_t gld_snd_mutex; + kmutex_t xmit_mutex; + kmutex_t rcv_mutex; + kmutex_t phy_mutex; + kmutex_t ind_mutex; + + /* + * Following are generic DMA handles used for the following - + * 1. Status _ Statistic DMA memory + * 2. TXBD queue + * 3. RXBD queue + */ +#define BNX_MAX_PHYS_MEMREQS 32 + u32_t dma_handles_used; + void *dma_virt[BNX_MAX_PHYS_MEMREQS]; + ddi_dma_handle_t dma_handle[BNX_MAX_PHYS_MEMREQS]; + ddi_acc_handle_t dma_acc_handle[BNX_MAX_PHYS_MEMREQS]; + + ddi_dma_handle_t *status_block_dma_hdl; + +} os_param_t; + + + + +/* + * Following structure hosts attributes related to the device, like media type, + * transmit/receive descriptor queue information, last status index + * processed/acknowledged, etc' + */ + +typedef struct _dev_param { + + u32_t mtu; + + lm_rx_mask_t rx_filter_mask; + lm_offload_t enabled_oflds; + + /* + * This is the last value of 'status_idx' processed and acknowledged + * by the driver. This value is compared with current value in the + * status block to determine if new status block was generated by + * host coalesce block. + */ + u32_t processed_status_idx; + + u32_t fw_ver; + + boolean_t isfiber; + + boolean_t disableMsix; + + lm_status_t indLink; + lm_medium_t indMedium; +} device_param_t; + + +typedef struct _bnx_ndd_lnk_tbl_t { + const char **label; + const boolean_t *value; +} bnx_ndd_lnk_tbl_t; + + +/* NDD parameters related structure members. */ +typedef struct _bnx_ndd_t { + caddr_t ndd_data; + + bnx_ndd_lnk_tbl_t lnktbl[3]; + + int link_speed; + boolean_t link_duplex; + boolean_t link_tx_pause; + boolean_t link_rx_pause; +} bnx_ndd_t; + + +typedef struct _bnx_lnk_cfg_t { + boolean_t link_autoneg; + boolean_t param_2500fdx; + boolean_t param_1000fdx; + boolean_t param_1000hdx; + boolean_t param_100fdx; + boolean_t param_100hdx; + boolean_t param_10fdx; + boolean_t param_10hdx; + boolean_t param_tx_pause; + boolean_t param_rx_pause; +} bnx_lnk_cfg_t; + + + +typedef struct _bnx_phy_cfg_t { + bnx_lnk_cfg_t lnkcfg; + + boolean_t flow_autoneg; + boolean_t wirespeed; +} bnx_phy_cfg_t; + + + +typedef struct _um_device { + /* Lower Module device structure should be the first element */ + struct _lm_device_t lm_dev; + + u32_t magic; + + ddi_intr_handle_t *pIntrBlock; + u32_t intrPriority; + int intrType; + + volatile boolean_t intr_enabled; + kmutex_t intr_mutex; + uint32_t intr_count; + uint32_t intr_no_change; + uint32_t intr_in_disabled; + + volatile boolean_t timer_enabled; + kmutex_t tmr_mutex; + timeout_id_t tmrtid; + unsigned int timer_link_check_interval; + unsigned int timer_link_check_counter; + unsigned int timer_link_check_interval2; + unsigned int timer_link_check_counter2; + + volatile boolean_t dev_start; + volatile boolean_t link_updates_ok; + + os_param_t os_param; + device_param_t dev_var; + + u32_t tx_copy_threshold; + + u32_t no_tx_credits; +#define BNX_TX_RESOURCES_NO_CREDIT 0x01 +#define BNX_TX_RESOURCES_NO_DESC 0x02 +/* Unable to allocate DMA resources. (e.g. bind error) */ +#define BNX_TX_RESOURCES_NO_OS_DMA_RES 0x08 +#define BNX_TX_RESOURCES_TOO_MANY_FRAGS 0x10 + + um_xmit_qinfo txq[NUM_TX_CHAIN]; +#define _TX_QINFO(pdev, chain) (pdev->txq[chain]) +#define _TXQ_FREE_DESC(pdev, chain) (pdev->txq[chain].free_tx_desc) +#define _TXQ_RESC_DESC(pdev, chain) (pdev->txq[chain].tx_resc_que) + + u32_t rx_copy_threshold; + uint32_t recv_discards; + + um_recv_qinfo rxq[NUM_RX_CHAIN]; +#define _RX_QINFO(pdev, chain) (pdev->rxq[chain]) + + bnx_ndd_t nddcfg; + + bnx_phy_cfg_t hwinit; + bnx_phy_cfg_t curcfg; + bnx_lnk_cfg_t remote; + + char dev_name[BNX_STR_SIZE]; + int instance; + char version[BNX_STR_SIZE]; + char versionFW[BNX_STR_SIZE]; + char chipName[BNX_STR_SIZE]; + char intrAlloc[BNX_STR_SIZE]; + u64_t intrFired; + + kstat_t *kstats; + kmutex_t kstatMutex; + +#define BNX_MAX_MEMREQS 2 + unsigned int memcnt; + bnx_memreq_t memreq[BNX_MAX_MEMREQS]; +} um_device_t; + + + +/* + * Following structure defines the packet descriptor as seen by the UM module. + * This is used to map buffers to lm_packet on xmit path and receive path. + */ + +typedef struct _um_txpacket_t { + /* Must be the first entry in this structure. */ + struct _lm_packet_t lm_pkt; + + mblk_t *mp; + + ddi_dma_handle_t *cpyhdl; + caddr_t cpymem; + lm_u64_t cpyphy; + off_t cpyoff; + + u32_t num_handles; + ddi_dma_handle_t dma_handle[BNX_MAX_SGL_ENTRIES]; + + lm_frag_list_t frag_list; + lm_frag_t frag_list_buffer[BNX_MAX_SGL_ENTRIES]; +} um_txpacket_t; + + + +#define BNX_RECV_MAX_FRAGS 1 +typedef struct _um_rxpacket_t { + /* Must be the first entry in this structure. */ + struct _lm_packet_t lmpacket; + + ddi_dma_handle_t dma_handle; + ddi_acc_handle_t dma_acc_handle; +} um_rxpacket_t; + + +#define VLAN_TPID 0x8100u +#define VLAN_TAGSZ 4 +#define VLAN_TAG_SIZE 4 +#define VLAN_VID_MAX 4094 /* 4095 is reserved */ + + +typedef struct ether_vlan_header vlan_hdr_t; +#define DRV_EXTRACT_VLAN_TPID(vhdrp) htons(vhdrp->ether_tpid) +#define DRV_EXTRACT_VLAN_TCI(vhdrp) htons(vhdrp->ether_tci) +#define DRV_SET_VLAN_TPID(vhdrp, tpid) vhdrp->ether_tpid = htons(tpid) +#define DRV_SET_VLAN_TCI(vhdrp, vtag) vhdrp->ether_tci = htons(vtag) + + + + + +/* + * + * 'ndd' Get/Set IOCTL Definition + * + */ + + +/* + * (Internal) return values from ioctl subroutines + */ +enum ioc_reply { + IOC_INVAL = -1, /* bad, NAK with EINVAL */ + IOC_DONE, /* OK, reply sent */ + IOC_ACK, /* OK, just send ACK */ + IOC_REPLY, /* OK, just send reply */ + IOC_RESTART_ACK, /* OK, restart & ACK */ + IOC_RESTART_REPLY /* OK, restart & reply */ +}; + +/* + * Function Prototypes + * + */ + +ddi_dma_handle_t *bnx_find_dma_hdl(um_device_t * const umdevice, + const void * const virtaddr); + +void um_send_driver_pulse(um_device_t *udevp); + +int bnx_find_mchash_collision(lm_mc_table_t *mc_table, + const u8_t *const mc_addr); + +void bnx_update_phy(um_device_t *pdev); + + +boolean_t bnx_kstat_init(um_device_t *pUM); +void bnx_kstat_fini(um_device_t *pUM); + +#ifdef __cplusplus +} +#endif + +#endif /* _BNX_H */ diff --git a/usr/src/uts/common/io/bnx/bnx_kstat.c b/usr/src/uts/common/io/bnx/bnx_kstat.c new file mode 100644 index 0000000000..5daae72afc --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnx_kstat.c @@ -0,0 +1,107 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2019, Joyent, Inc. + */ + +#include "bnx.h" + +typedef struct { + kstat_named_t version; + kstat_named_t versionFW; + kstat_named_t chipName; + kstat_named_t intrAlloc; + kstat_named_t intrFired; + kstat_named_t intrInDisabled; + kstat_named_t intrNoChange; +} bnx_kstat_t; + +#define BNX_KSTAT_SIZE (sizeof (bnx_kstat_t) / sizeof (kstat_named_t)) + + +static int +bnx_kstat_update(kstat_t *kstats, int rw) +{ + bnx_kstat_t *pStats = (bnx_kstat_t *)kstats->ks_data; + um_device_t *pUM = (um_device_t *)kstats->ks_private; + + if (rw == KSTAT_WRITE) { + return (EACCES); + } + + mutex_enter(&pUM->kstatMutex); + + (void) strncpy(pStats->version.value.c, pUM->version, + sizeof (pStats->version.value.c)); + (void) strncpy(pStats->versionFW.value.c, pUM->versionFW, + sizeof (pStats->versionFW.value.c)); + (void) strncpy(pStats->chipName.value.c, pUM->chipName, + sizeof (pStats->chipName.value.c)); + (void) strncpy(pStats->intrAlloc.value.c, pUM->intrAlloc, + sizeof (pStats->intrAlloc.value.c)); + pStats->intrFired.value.ui64 = pUM->intr_count; + pStats->intrInDisabled.value.ui64 = pUM->intr_in_disabled; + pStats->intrNoChange.value.ui64 = pUM->intr_no_change; + + mutex_exit(&pUM->kstatMutex); + + return (0); +} + +#define BNX_KSTAT(f, t) kstat_named_init(&pStats->f, #f, t) + +boolean_t +bnx_kstat_init(um_device_t *pUM) +{ + bnx_kstat_t *pStats; + + if ((pUM->kstats = kstat_create("bnx", pUM->instance, "statistics", + "net", KSTAT_TYPE_NAMED, BNX_KSTAT_SIZE, 0)) == NULL) { + cmn_err(CE_WARN, "%s: Failed to create kstat", pUM->dev_name); + return (B_FALSE); + } + + pStats = (bnx_kstat_t *)pUM->kstats->ks_data; + + BNX_KSTAT(version, KSTAT_DATA_CHAR); + BNX_KSTAT(versionFW, KSTAT_DATA_CHAR); + BNX_KSTAT(chipName, KSTAT_DATA_CHAR); + BNX_KSTAT(intrAlloc, KSTAT_DATA_CHAR); + BNX_KSTAT(intrFired, KSTAT_DATA_UINT64); + BNX_KSTAT(intrInDisabled, KSTAT_DATA_UINT64); + BNX_KSTAT(intrNoChange, KSTAT_DATA_UINT64); + + pUM->kstats->ks_update = bnx_kstat_update; + pUM->kstats->ks_private = (void *)pUM; + + mutex_init(&pUM->kstatMutex, NULL, + MUTEX_DRIVER, DDI_INTR_PRI(pUM->intrPriority)); + + kstat_install(pUM->kstats); + + return (B_TRUE); +} + +void +bnx_kstat_fini(um_device_t *pUM) +{ + if (pUM->kstats) { + kstat_delete(pUM->kstats); + pUM->kstats = NULL; + } + + mutex_destroy(&pUM->kstatMutex); +} diff --git a/usr/src/uts/common/io/bnx/bnx_mm.c b/usr/src/uts/common/io/bnx/bnx_mm.c new file mode 100644 index 0000000000..63811f7c4d --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnx_mm.c @@ -0,0 +1,856 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2019, Joyent, Inc. + */ + +#include "bnx.h" +#include "bnx_mm.h" +#include "bnxgld.h" +#include "bnxsnd.h" +#include "bnxtmr.h" +#include "bnxcfg.h" +#include "serdes.h" + +#include "shmem.h" + +#define MII_REG(_type, _field) (OFFSETOF(_type, _field)/2) + +ddi_dma_attr_t bnx_std_dma_attrib = { + DMA_ATTR_V0, /* dma_attr_version */ + 0, /* dma_attr_addr_lo */ + 0xffffffffffffffff, /* dma_attr_addr_hi */ + 0x0ffffff, /* dma_attr_count_max */ + BNX_DMA_ALIGNMENT, /* dma_attr_align */ + 0xffffffff, /* dma_attr_burstsizes */ + 1, /* dma_attr_minxfer */ + 0x00ffffff, /* dma_attr_maxxfer */ + 0xffffffff, /* dma_attr_seg */ + 1, /* dma_attr_sgllen */ + 1, /* dma_attr_granular */ + 0, /* dma_attr_flags */ +}; + + +static ddi_dma_attr_t bnx_page_dma_attrib = { + DMA_ATTR_V0, /* dma_attr_version */ + 0, /* dma_attr_addr_lo */ + 0xffffffffffffffff, /* dma_attr_addr_hi */ + 0x0ffffff, /* dma_attr_count_max */ + LM_PAGE_SIZE, /* dma_attr_align */ + 0xffffffff, /* dma_attr_burstsizes */ + 1, /* dma_attr_minxfer */ + 0x00ffffff, /* dma_attr_maxxfer */ + 0xffffffff, /* dma_attr_seg */ + 1, /* dma_attr_sgllen */ + 1, /* dma_attr_granular */ + 0, /* dma_attr_flags */ +}; + + + +/* + * Name: mm_wait + * + * Input: ptr to LM's device structure, + * delay value in micro-secs + * + * Return: None. + * + * Description: This funtion will be in a busy loop for specified number of + * micro-seconds and will return only after the time is elasped. + */ +void +mm_wait(lm_device_t *pdev, u32_t delay_us) +{ + FLUSHPOSTEDWRITES(pdev); + drv_usecwait(delay_us * 10); +} /* mm_wait */ + + + +/* + * Name: mm_read_pci + * + * Input: ptr to LM's device structure, + * register offset into config space, + * ptr to u32 where the register value is returned + * + * Return: LM_STATUS_SUCCESS, if successful + * LM_STATUS_FAILURE, if BAR register veiw is not mapped + * + * Description: This routine reads the PCI config space for the given device + * by calling pci_config_get32(). + */ +lm_status_t +mm_read_pci(lm_device_t *pdev, u32_t pci_reg, u32_t *reg_value) +{ + um_device_t *udevp = (um_device_t *)pdev; + + *reg_value = pci_config_get32(udevp->os_param.pci_cfg_handle, + (off_t)pci_reg); + + return (LM_STATUS_SUCCESS); +} /* mm_read_pci */ + + + +/* + * Name: mm_write_pci + * + * Input: ptr to LM's device structure, + * register offset into config space, + * u32 value to be written to PCI config register + * + * Return: LM_STATUS_SUCCESS, if successful + * LM_STATUS_FAILURE, if BAR register veiw is not mapped + * + * Description: This routine writes to PCI config register using DDI call, + * pci_config_put32(). + */ +lm_status_t +mm_write_pci(lm_device_t *pdev, u32_t pci_reg, u32_t reg_value) +{ + um_device_t *udevp = (um_device_t *)pdev; + + pci_config_put32(udevp->os_param.pci_cfg_handle, + (off_t)pci_reg, (uint32_t)reg_value); + + return (LM_STATUS_SUCCESS); +} /* mm_write_pci */ + + + +/* + * Name: mm_map_io_base + * + * Input: ptr to LM's device structure, + * physical address of the BAR reg + * (not used in this implementation), + * size of the register window + * + * Return: ptr to mapped virtual memory + * + * Description: This routine maps the BAR register window and returns the + * virtual address in the CPU address scape + */ +void * +mm_map_io_base(lm_device_t *pdev, lm_address_t base_addr, u32_t size) +{ + um_device_t *udevp = (um_device_t *)pdev; + + pdev->vars.dmaRegAccHandle = udevp->os_param.reg_acc_handle; + + return ((void *)(udevp->os_param.regs_addr)); +} /* mm_map_io_base */ + + + +/* + * Name: mm_desc_size + * + * Input: ptr to LM's device structure, + * descriptor type + * + * Return: size of the descriptor structure + * + * Description: This routine currently returns the size of packet descriptor + * as defined by the UM module (lm_pkt_t is embedded in this + * struct). This is used by LM's init routines trying to allocate + * memory for TX/RX descriptor queues. + */ +u32_t +mm_desc_size(lm_device_t *pdev, u32_t desc_type) +{ + u32_t desc_size; + + switch (desc_type) { + case DESC_TYPE_L2RX_PACKET: + desc_size = sizeof (um_rxpacket_t); + break; + + default: + desc_size = 0; + break; + } + + desc_size = ALIGN_VALUE_TO_WORD_BOUNDARY(desc_size); + + return (desc_size); +} /* mm_desc_size */ + + + +/* + * Name: mm_get_user_config + * + * Input: ptr to LM's device structure + * + * Return: SUCCESS + * + * Description: This rotuine maps user option to corresponding parameters in + * LM and UM device structures. + */ +lm_status_t +mm_get_user_config(lm_device_t *pdev) +{ + u32_t keep_vlan_tag = 0; + u32_t offset; + u32_t val; + um_device_t *umdevice = (um_device_t *)pdev; + + bnx_cfg_init(umdevice); + + bnx_cfg_map_phy(umdevice); + + /* + * If Management Firmware is running ensure that we don't + * keep the VLAN tag, this is for older firmware + */ + offset = pdev->hw_info.shmem_base; + offset += OFFSETOF(shmem_region_t, + dev_info.port_feature_config.config); + REG_RD_IND(pdev, offset, &val); + + if (!(val & PORT_FEATURE_MFW_ENABLED)) + keep_vlan_tag = 1; + + /* + * Newer versions of the firmware can handle VLAN tags + * check to see if this version of the firmware can handle them + */ + offset = pdev->hw_info.shmem_base; + offset += OFFSETOF(shmem_region_t, drv_fw_cap_mb.fw_cap_mb); + REG_RD_IND(pdev, offset, &val); + + if ((val & FW_CAP_SIGNATURE) == FW_CAP_SIGNATURE) { + if ((val & (FW_CAP_MFW_CAN_KEEP_VLAN | + FW_CAP_BC_CAN_UPDATE_VLAN)) == + (FW_CAP_MFW_CAN_KEEP_VLAN | FW_CAP_BC_CAN_UPDATE_VLAN)) { + offset = pdev->hw_info.shmem_base; + offset += OFFSETOF(shmem_region_t, + drv_fw_cap_mb.drv_ack_cap_mb); + REG_WR_IND(pdev, offset, DRV_ACK_CAP_SIGNATURE | + FW_CAP_MFW_CAN_KEEP_VLAN | + FW_CAP_BC_CAN_UPDATE_VLAN); + + keep_vlan_tag = 1; + } + } + + pdev->params.keep_vlan_tag = keep_vlan_tag; + + return (LM_STATUS_SUCCESS); +} /* mm_get_user_config */ + + + +/* + * Name: mm_alloc_mem + * + * Input: ptr to LM's device structure, + * size of the memory block to be allocated + * + * Return: ptr to newly allocated memory region + * + * Description: This routine allocates memory region, updates the + * resource list to reflect this newly allocated memory. + */ +void * +mm_alloc_mem(lm_device_t *pdev, u32_t mem_size, void *resc_list) +{ + void *memptr; + bnx_memreq_t *memreq; + um_device_t *umdevice; + + (void) resc_list; + + umdevice = (um_device_t *)pdev; + + if (mem_size == 0) { + return (NULL); + } + + if (umdevice->memcnt == BNX_MAX_MEMREQS) { + cmn_err(CE_WARN, "%s: Lower module memreq overflow.\n", + umdevice->dev_name); + return (NULL); + } + + memptr = kmem_zalloc(mem_size, KM_NOSLEEP); + if (memptr == NULL) { + cmn_err(CE_WARN, "%s: Failed to allocate local memory.\n", + umdevice->dev_name); + return (NULL); + } + + memreq = &umdevice->memreq[umdevice->memcnt]; + + memreq->addr = memptr; + memreq->size = mem_size; + + umdevice->memcnt++; + + return (memptr); +} /* mm_alloc_mem */ + + + +/* + * Name: mm_alloc_phys_mem + * + * Input: ptr to LM's device structure, + * size of the memory block to be allocated, + * pointer to store phys address, + * memory type + * + * Return: virtual memory ptr to newly allocated memory region + * + * Description: This routine allocates memory region, updates the + * resource list to reflect this newly allocated memory. + * This function returns physical address in addition the + * virtual address pointer. + */ +void * +mm_alloc_phys_mem(lm_device_t *pdev, u32_t mem_size, lm_address_t *phys_mem, + u8_t mem_type, void *resc_list) +{ + int rc; + caddr_t pbuf; + um_device_t *udevp; + size_t real_len; + unsigned int count; + ddi_dma_attr_t *dma_attrib; + ddi_dma_handle_t *dma_handle; + ddi_acc_handle_t *acc_handle; + ddi_dma_cookie_t cookie; + + (void) mem_type; + (void) resc_list; + + udevp = (um_device_t *)pdev; + + if (mem_size == 0) { + return (NULL); + } + + if (udevp->os_param.dma_handles_used == BNX_MAX_PHYS_MEMREQS) { + cmn_err(CE_WARN, "%s: %s: Lower module phys memreq overflow.\n", + udevp->dev_name, __func__); + return (NULL); + } + + if (!(mem_size & LM_PAGE_MASK)) { + /* Size is multiple of page size. */ + dma_attrib = &bnx_page_dma_attrib; + } else { + dma_attrib = &bnx_std_dma_attrib; + } + + rc = udevp->os_param.dma_handles_used; + dma_handle = &udevp->os_param.dma_handle[rc]; + acc_handle = &udevp->os_param.dma_acc_handle[rc]; + + rc = ddi_dma_alloc_handle(udevp->os_param.dip, dma_attrib, + DDI_DMA_DONTWAIT, (void *)0, dma_handle); + if (rc != DDI_SUCCESS) { + cmn_err(CE_WARN, "%s: %s: Failed to alloc phys dma handle.\n", + udevp->dev_name, __func__); + return (NULL); + } + + rc = ddi_dma_mem_alloc(*dma_handle, (size_t)mem_size + + BNX_DMA_ALIGNMENT, &bnxAccessAttribBUF, DDI_DMA_CONSISTENT, + DDI_DMA_DONTWAIT, (void *)0, &pbuf, &real_len, acc_handle); + if (rc != DDI_SUCCESS) { + cmn_err(CE_WARN, "%s: %s: Failed to alloc phys memory.\n", + udevp->dev_name, __func__); + goto error1; + } + + rc = ddi_dma_addr_bind_handle(*dma_handle, (struct as *)0, pbuf, + real_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_DONTWAIT, + (void *)0, &cookie, &count); + if (rc != DDI_SUCCESS) { + cmn_err(CE_WARN, "%s: %s: Failed to bind DMA address.\n", + udevp->dev_name, __func__); + goto error2; + } + + phys_mem->as_u64 = (u64_t)cookie.dmac_laddress; + + /* + * Save the virtual memory address so + * we can get the dma_handle later. + */ + udevp->os_param.dma_virt[udevp->os_param.dma_handles_used] = pbuf; + + udevp->os_param.dma_handles_used++; + + /* Zero the memory... */ + bzero(pbuf, real_len); + + /* ...and make sure the new contents are flushed back to main memory. */ + (void) ddi_dma_sync(*dma_handle, 0, real_len, DDI_DMA_SYNC_FORDEV); + + return (pbuf); + +error2: + ddi_dma_mem_free(acc_handle); + +error1: + ddi_dma_free_handle(dma_handle); + + return (NULL); +} /* mm_alloc_phys_mem */ + + + +/* + * Name: mm_indicate_tx + * + * Input: ptr to LM's device structure, + * TX chain index, + * array of pointers to packet descriptors, + * number of packet descriptors in array + * + * Return: None + * + * Description: + * Lower module calls this API function to return transmit packet + * buffers to the system, and to allow the driver to reclaim + * transmit resources. This function is only called upon transmit + * abort and so is not in the fast path. + */ +void +mm_indicate_tx(lm_device_t *pdev, u32_t chain_idx, + struct _lm_packet_t *packet_arr[], u32_t num_packets) +{ + um_txpacket_t **pkt_ptr; + um_txpacket_t *pkt; + s_list_t comp_list; + + pkt_ptr = (um_txpacket_t **)packet_arr; + + s_list_init(&comp_list, NULL, NULL, 0); + + while (num_packets) { + pkt = *pkt_ptr; + + s_list_push_tail(&comp_list, &(pkt->lm_pkt.link)); + + pkt_ptr++; + num_packets--; + } + + bnx_xmit_ring_reclaim((um_device_t *)pdev, chain_idx, &comp_list); +} /* mm_indicate_tx */ + + + +/* + * Description: + * + * Return: + */ +static void +bnx_display_link_msg(um_device_t * const umdevice) +{ + char *media; + char linkstr[128]; + + if (umdevice->dev_var.isfiber) { + media = "Fiber"; + } else { + media = "Copper"; + } + + if (umdevice->nddcfg.link_speed != 0) { + (void) strlcpy(linkstr, "up (", sizeof (linkstr)); + + switch (umdevice->nddcfg.link_speed) { + case 2500: + (void) strlcat(linkstr, "2500Mbps, ", sizeof (linkstr)); + break; + case 1000: + (void) strlcat(linkstr, "1000Mbps, ", sizeof (linkstr)); + break; + case 100: + (void) strlcat(linkstr, "100Mbps, ", sizeof (linkstr)); + break; + case 10: + (void) strlcat(linkstr, "10Mbps, ", sizeof (linkstr)); + break; + default: + (void) strlcat(linkstr, "0Mbps, ", sizeof (linkstr)); + } + + if (umdevice->nddcfg.link_duplex) { + (void) strlcat(linkstr, "Full Duplex", + sizeof (linkstr)); + } else { + (void) strlcat(linkstr, "Half Duplex", + sizeof (linkstr)); + } + + if (umdevice->nddcfg.link_tx_pause || + umdevice->nddcfg.link_rx_pause) { + (void) strlcat(linkstr, ", ", sizeof (linkstr)); + if (umdevice->nddcfg.link_tx_pause) { + (void) strlcat(linkstr, "Tx", sizeof (linkstr)); + if (umdevice->nddcfg.link_rx_pause) { + (void) strlcat(linkstr, " & Rx", + sizeof (linkstr)); + } + } else { + (void) strlcat(linkstr, "Rx", sizeof (linkstr)); + } + (void) strlcat(linkstr, " Flow Control ON", + sizeof (linkstr)); + } + (void) strlcat(linkstr, ")", sizeof (linkstr)); + } else { + (void) snprintf(linkstr, sizeof (linkstr), "down"); + } + + cmn_err(CE_NOTE, "!%s: %s link is %s", umdevice->dev_name, media, + linkstr); +} /* bnx_display_link_msg */ + + + +/* + * Name: bnx_update_lp_cap + * + * Input: ptr to device structure + * + * Return: None + * + * Description: This function is updates link partners advertised + * capabilities. + */ +static void +bnx_update_lp_cap(um_device_t *const umdevice) +{ + u32_t miireg; + lm_status_t lmstatus; + lm_device_t *lmdevice; + + lmdevice = &(umdevice->lm_dev); + + if (umdevice->dev_var.isfiber) { + lmstatus = lm_mread(lmdevice, lmdevice->params.phy_addr, + MII_REG(serdes_reg_t, mii_aneg_nxt_pg_rcv1), &miireg); + if (lmstatus == LM_STATUS_SUCCESS) { + if (miireg & MII_ANEG_NXT_PG_RCV1_2G5) { + umdevice->remote.param_2500fdx = B_TRUE; + } + } + + lmstatus = lm_mread(lmdevice, lmdevice->params.phy_addr, + PHY_LINK_PARTNER_ABILITY_REG, &miireg); + if (lmstatus == LM_STATUS_SUCCESS) { + miireg &= MII_ABILITY_PAUSE; + if (miireg == MII_ADVERT_SYM_PAUSE) { + umdevice->remote.param_tx_pause = B_TRUE; + umdevice->remote.param_rx_pause = B_TRUE; + } else if (miireg == MII_ADVERT_ASYM_PAUSE) { + umdevice->remote.param_tx_pause = B_TRUE; + } + + if (miireg & MII_ABILITY_FULL) { + umdevice->remote.param_1000fdx = B_TRUE; + } + + if (miireg & MII_ABILITY_HALF) { + umdevice->remote.param_1000hdx = B_TRUE; + } + } + } else { + /* Copper */ + lmstatus = lm_mread(lmdevice, lmdevice->params.phy_addr, + PHY_1000BASET_STATUS_REG, &miireg); + if (lmstatus == LM_STATUS_SUCCESS) { + if (miireg & PHY_LINK_PARTNER_1000BASET_FULL) { + umdevice->remote.param_1000fdx = B_TRUE; + } + + if (miireg & PHY_LINK_PARTNER_1000BASET_HALF) { + umdevice->remote.param_1000hdx = B_TRUE; + } + } + + lmstatus = lm_mread(lmdevice, lmdevice->params.phy_addr, + PHY_LINK_PARTNER_ABILITY_REG, &miireg); + if (lmstatus == LM_STATUS_SUCCESS) { + if (miireg & PHY_LINK_PARTNER_PAUSE_CAPABLE) { + umdevice->remote.param_tx_pause = B_TRUE; + umdevice->remote.param_rx_pause = B_TRUE; + } else if (miireg & PHY_LINK_PARTNER_ASYM_PAUSE) { + umdevice->remote.param_tx_pause = B_TRUE; + } + + if (miireg & PHY_LINK_PARTNER_100BASETX_FULL) { + umdevice->remote.param_100fdx = B_TRUE; + } + + if (miireg & PHY_LINK_PARTNER_100BASETX_HALF) { + umdevice->remote.param_100hdx = B_TRUE; + } + + if (miireg & PHY_LINK_PARTNER_10BASET_FULL) { + umdevice->remote.param_10fdx = B_TRUE; + } + + if (miireg & PHY_LINK_PARTNER_10BASET_HALF) { + umdevice->remote.param_10hdx = B_TRUE; + } + } + } + +#if 0 + /* + * If we can gather _any_ information about our link partner, then + * because this information is exchanged through autonegotiation, we + * know that our link partner supports autonegotiation. + * + * FIXME -- Find a more authoritative way to update link_autoneg. I'm + * not sure it is legal, but it sounds possible to have autonegotiation + * enabled on the remote end with no capabilities advertised. + */ + if (umdevice->remote.param_2500fdx || + umdevice->remote.param_1000fdx || + umdevice->remote.param_1000hdx || + umdevice->remote.param_100fdx || + umdevice->remote.param_100hdx || + umdevice->remote.param_10fdx || + umdevice->remote.param_10hdx || + umdevice->remote.param_tx_pause || + umdevice->remote.param_rx_pause) { + umdevice->remote.param_autoneg = B_TRUE; + } +#else + lmstatus = lm_mread(lmdevice, lmdevice->params.phy_addr, + BCM540X_AUX_STATUS_REG, &miireg); + if (lmstatus == LM_STATUS_SUCCESS) { + if (miireg & BIT_12) { + umdevice->remote.link_autoneg = B_TRUE; + } + } +#endif +} /* bnx_update_lp_cap */ + + + +/* + * Name: mm_indicate_link + * + * Input: ptr to LM's device structure, + * link status, + * lm_medium_t struct + * + * Return: None + * + * Description: Lower module calls this function when ever there is a network + * link status change. This routine updates the driver data + * structure as well calls gld_linkstate() to notify event to GLD. + */ +void +mm_indicate_link(lm_device_t *lmdevice, lm_status_t link, lm_medium_t medium) +{ + int link_speed; + um_device_t *umdevice; + + umdevice = (um_device_t *)lmdevice; + + if (umdevice->link_updates_ok == B_FALSE) { + return; + } + + /* ignore link status if it has not changed since the last indicate */ + if ((umdevice->dev_var.indLink == link) && + (umdevice->dev_var.indMedium == medium)) { + return; + } + + umdevice->dev_var.indLink = link; + umdevice->dev_var.indMedium = medium; + + switch (GET_MEDIUM_SPEED(medium)) { + case LM_MEDIUM_SPEED_10MBPS: + link_speed = 10; + break; + + case LM_MEDIUM_SPEED_100MBPS: + link_speed = 100; + break; + + case LM_MEDIUM_SPEED_1000MBPS: + link_speed = 1000; + break; + + case LM_MEDIUM_SPEED_2500MBPS: + link_speed = 2500; + break; + + default: + link_speed = 0; + break; + } + + /* + * Validate the linespeed against known hardware capabilities. + * This is a common occurance. + */ + if (umdevice->dev_var.isfiber) { + if (link_speed != 2500 && link_speed != 1000) { + link_speed = 0; + } + } + + if (link_speed == 0) { + link = LM_STATUS_LINK_DOWN; + } + + /* + * If neither link-up or link-down flag is present, then there must + * have been multiple link events. Do the right thing. + */ + if (link != LM_STATUS_LINK_ACTIVE && link != LM_STATUS_LINK_DOWN) { + /* Fill in the missing information. */ + if (link_speed != 0) { + link = LM_STATUS_LINK_ACTIVE; + } else { + link = LM_STATUS_LINK_DOWN; + } + } + +#if 0 + if (((umdevice->nddcfg.link_speed == 0) && + (link != LM_STATUS_LINK_ACTIVE)) || + ((umdevice->nddcfg.link_speed != 0) && + (link != LM_STATUS_LINK_DOWN))) { + /* This is a false notification. */ + return; + } +#endif + + if (umdevice->timer_link_check_interval) { + if (link == LM_STATUS_LINK_ACTIVE) { + if (lmdevice->vars.serdes_fallback_status) { + /* + * Start the timer to poll the serdes for + * reception of configs from the link partner. + * When this happens the remote has autoneg + * enabled and we'll restart our autoneg. + */ + bnx_link_timer_restart(umdevice); + } + } else { + if (umdevice->timer_link_check_counter) { + bnx_link_timer_restart(umdevice); + } + } + } + + if (link == LM_STATUS_LINK_DOWN) { + umdevice->nddcfg.link_speed = 0; + umdevice->nddcfg.link_duplex = B_FALSE; + umdevice->nddcfg.link_tx_pause = B_FALSE; + umdevice->nddcfg.link_rx_pause = B_FALSE; + + umdevice->remote.link_autoneg = B_FALSE; + umdevice->remote.param_2500fdx = B_FALSE; + umdevice->remote.param_1000fdx = B_FALSE; + umdevice->remote.param_1000hdx = B_FALSE; + umdevice->remote.param_100fdx = B_FALSE; + umdevice->remote.param_100hdx = B_FALSE; + umdevice->remote.param_10fdx = B_FALSE; + umdevice->remote.param_10hdx = B_FALSE; + umdevice->remote.param_tx_pause = B_FALSE; + umdevice->remote.param_rx_pause = B_FALSE; + + bnx_display_link_msg(umdevice); + + bnx_gld_link(umdevice, LINK_STATE_DOWN); + } else if (link == LM_STATUS_LINK_ACTIVE) { + umdevice->nddcfg.link_speed = link_speed; + + if (GET_MEDIUM_DUPLEX(medium)) { + /* half duplex */ + umdevice->nddcfg.link_duplex = B_FALSE; + } else { + /* full duplex */ + umdevice->nddcfg.link_duplex = B_TRUE; + } + + if (lmdevice->vars.flow_control & + LM_FLOW_CONTROL_TRANSMIT_PAUSE) { + umdevice->nddcfg.link_tx_pause = B_TRUE; + } else { + umdevice->nddcfg.link_tx_pause = B_FALSE; + } + + if (lmdevice->vars.flow_control & + LM_FLOW_CONTROL_RECEIVE_PAUSE) { + umdevice->nddcfg.link_rx_pause = B_TRUE; + } else { + umdevice->nddcfg.link_rx_pause = B_FALSE; + } + + if (umdevice->curcfg.lnkcfg.link_autoneg == B_TRUE) { + bnx_update_lp_cap(umdevice); + } + + bnx_display_link_msg(umdevice); + + bnx_gld_link(umdevice, LINK_STATE_UP); + } +} /* mm_indicate_link */ + + + +/* + * Description: + * + * Return: + */ +void +mm_acquire_ind_reg_lock(struct _lm_device_t *pdev) +{ + um_device_t *umdevice; + + umdevice = (um_device_t *)pdev; + + mutex_enter(&umdevice->os_param.ind_mutex); +} /* mm_acquire_ind_reg_lock */ + + + +/* + * Description: + * + * Return: + */ +void +mm_release_ind_reg_lock(struct _lm_device_t *pdev) +{ + um_device_t *umdevice; + + umdevice = (um_device_t *)pdev; + + mutex_exit(&umdevice->os_param.ind_mutex); +} /* mm_release_ind_reg_lock */ diff --git a/usr/src/uts/common/io/bnx/bnx_mm.h b/usr/src/uts/common/io/bnx/bnx_mm.h new file mode 100644 index 0000000000..1361894b6c --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnx_mm.h @@ -0,0 +1,44 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + */ + +#ifndef _BNX_MM_H +#define _BNX_MM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <sys/atomic.h> + +#define mm_read_barrier() membar_consumer() +#define mm_write_barrier() membar_producer() + +#include "lm.h" +#include "lm5706.h" + +#define FLUSHPOSTEDWRITES(_lmdevice) \ + { \ + volatile uint32_t dummy; \ + REG_RD((_lmdevice), pci_config.pcicfg_int_ack_cmd, &dummy); \ + } + +#ifdef __cplusplus +} +#endif + +#endif /* _BNX_MM_H */ diff --git a/usr/src/uts/common/io/bnx/bnxcfg.c b/usr/src/uts/common/io/bnx/bnxcfg.c new file mode 100644 index 0000000000..fd94c28c59 --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxcfg.c @@ -0,0 +1,714 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2019, Joyent, Inc. + */ + +#include "bnxcfg.h" + +const bnx_lnk_cfg_t bnx_copper_config = { + B_TRUE, /* link_autoneg */ + B_FALSE, /* param_2500fdx */ + B_TRUE, /* param_1000fdx */ + B_TRUE, /* param_1000hdx */ + B_TRUE, /* param_100fdx */ + B_TRUE, /* param_100hdx */ + B_TRUE, /* param_10fdx */ + B_TRUE, /* param_10hdx */ + B_TRUE, /* param_tx_pause */ + B_TRUE /* param_rx_pause */ +}; + +const bnx_lnk_cfg_t bnx_serdes_config = { + B_TRUE, /* link_autoneg */ + B_TRUE, /* param_2500fdx */ + B_TRUE, /* param_1000fdx */ + B_TRUE, /* param_1000hdx */ + B_FALSE, /* param_100fdx */ + B_FALSE, /* param_100hdx */ + B_FALSE, /* param_10fdx */ + B_FALSE, /* param_10hdx */ + B_TRUE, /* param_tx_pause */ + B_TRUE /* param_rx_pause */ +}; + +static void +bnx_cfg_readbool(dev_info_t *dip, char *paramname, boolean_t *paramval) +{ + int rc; + int *option; + uint_t num_options; + + if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_NOTPROM, paramname) == + 1) { + rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, + DDI_PROP_DONTPASS, paramname, &option, &num_options); + + if (rc == DDI_PROP_SUCCESS) { + int inst = ddi_get_instance(dip); + + if (num_options >= inst) { + if (option[inst] == 1) { + *paramval = B_TRUE; + } else { + *paramval = B_FALSE; + } + } + } + + ddi_prop_free(option); + } +} /* bnx_cfg_readbool */ + +static void +bnx_cfg_readint(dev_info_t *dip, char *paramname, int *paramval) +{ + int rc; + int *option; + uint_t num_options; + + rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, + paramname, &option, &num_options); + if (rc == DDI_PROP_SUCCESS) { + int inst = ddi_get_instance(dip); + + if (num_options >= inst) { + *paramval = option[inst]; + } + + ddi_prop_free(option); + } +} /* bnx_cfg_readint */ + +void +bnx_cfg_msix(um_device_t * const umdevice) +{ + umdevice->dev_var.disableMsix = B_FALSE; + + bnx_cfg_readbool(umdevice->os_param.dip, "disable_msix", + &(umdevice->dev_var.disableMsix)); +} + +void +bnx_cfg_init(um_device_t *const umdevice) +{ + int option; + lm_medium_t lmmedium; + lm_device_t *lmdevice; + + lmdevice = &(umdevice->lm_dev); + + lmmedium = lm_get_medium(lmdevice); + if (lmmedium == LM_MEDIUM_TYPE_FIBER) { + umdevice->dev_var.isfiber = B_TRUE; + + bcopy(&bnx_serdes_config, + &(umdevice->hwinit.lnkcfg), + sizeof (bnx_serdes_config)); + } else { + umdevice->dev_var.isfiber = B_FALSE; + + bcopy(&bnx_copper_config, &(umdevice->hwinit.lnkcfg), + sizeof (bnx_copper_config)); + } + + umdevice->hwinit.flow_autoneg = B_TRUE; + umdevice->hwinit.wirespeed = B_TRUE; + + bnx_cfg_readbool(umdevice->os_param.dip, "adv_autoneg_cap", + &(umdevice->hwinit.lnkcfg.link_autoneg)); + + bnx_cfg_readbool(umdevice->os_param.dip, "adv_1000fdx_cap", + &(umdevice->hwinit.lnkcfg.param_1000fdx)); + + bnx_cfg_readbool(umdevice->os_param.dip, "adv_1000hdx_cap", + &(umdevice->hwinit.lnkcfg.param_1000hdx)); + + bnx_cfg_readbool(umdevice->os_param.dip, "tx_pause_cap", + &(umdevice->hwinit.lnkcfg.param_tx_pause)); + + bnx_cfg_readbool(umdevice->os_param.dip, "rx_pause_cap", + &(umdevice->hwinit.lnkcfg.param_rx_pause)); + + if (umdevice->dev_var.isfiber) { + bnx_cfg_readbool(umdevice->os_param.dip, "adv_2500fdx_cap", + &(umdevice->hwinit.lnkcfg.param_2500fdx)); + } else { + bnx_cfg_readbool(umdevice->os_param.dip, "adv_100fdx_cap", + &(umdevice->hwinit.lnkcfg.param_100fdx)); + + bnx_cfg_readbool(umdevice->os_param.dip, "adv_100hdx_cap", + &(umdevice->hwinit.lnkcfg.param_100hdx)); + + bnx_cfg_readbool(umdevice->os_param.dip, "adv_10fdx_cap", + &(umdevice->hwinit.lnkcfg.param_10fdx)); + + bnx_cfg_readbool(umdevice->os_param.dip, "adv_10hdx_cap", + &(umdevice->hwinit.lnkcfg.param_10hdx)); + } + + bnx_cfg_readbool(umdevice->os_param.dip, "autoneg_flow", + &(umdevice->hwinit.flow_autoneg)); + + bnx_cfg_readbool(umdevice->os_param.dip, "wirespeed", + &(umdevice->hwinit.wirespeed)); + +#if 1 + /* FIXME -- Do we really need "transfer-speed"? */ + /* + * The link speed may be forced to 10, 100 or 1000 Mbps using + * the property "transfer-speed". This may be done in OBP by + * using the command "apply transfer-speed=<speed> <device>". + * The speed may be 10, 100 or 1000 - any other value will be + * ignored. Note that this *enables* autonegotiation, but + * restricts it to the speed specified by the property. + */ + option = 0; + bnx_cfg_readint(umdevice->os_param.dip, + "transfer-speed", &option); + switch (option) { + case 1000: + umdevice->hwinit.lnkcfg.link_autoneg = B_TRUE; + umdevice->hwinit.lnkcfg.param_1000fdx = B_TRUE; + umdevice->hwinit.lnkcfg.param_1000hdx = B_TRUE; + umdevice->hwinit.lnkcfg.param_100fdx = B_FALSE; + umdevice->hwinit.lnkcfg.param_100hdx = B_FALSE; + umdevice->hwinit.lnkcfg.param_10fdx = B_FALSE; + umdevice->hwinit.lnkcfg.param_10hdx = B_FALSE; + break; + + case 100: + umdevice->hwinit.lnkcfg.link_autoneg = B_TRUE; + umdevice->hwinit.lnkcfg.param_1000fdx = B_FALSE; + umdevice->hwinit.lnkcfg.param_1000hdx = B_FALSE; + umdevice->hwinit.lnkcfg.param_100fdx = B_TRUE; + umdevice->hwinit.lnkcfg.param_100hdx = B_TRUE; + umdevice->hwinit.lnkcfg.param_10fdx = B_FALSE; + umdevice->hwinit.lnkcfg.param_10hdx = B_FALSE; + break; + + case 10: + umdevice->hwinit.lnkcfg.link_autoneg = B_TRUE; + umdevice->hwinit.lnkcfg.param_1000fdx = B_FALSE; + umdevice->hwinit.lnkcfg.param_1000hdx = B_FALSE; + umdevice->hwinit.lnkcfg.param_100fdx = B_FALSE; + umdevice->hwinit.lnkcfg.param_100hdx = B_FALSE; + umdevice->hwinit.lnkcfg.param_10fdx = B_TRUE; + umdevice->hwinit.lnkcfg.param_10hdx = B_TRUE; + break; + } +#endif + + + /* FIXME -- Make the MAC address hwconf configurable. */ + + /* Checksum configuration */ + option = USER_OPTION_CKSUM_DEFAULT; + bnx_cfg_readint(umdevice->os_param.dip, + "checksum", &option); + switch (option) { + case USER_OPTION_CKSUM_TX_ONLY: + umdevice->dev_var.enabled_oflds = LM_OFFLOAD_TX_IP_CKSUM + | LM_OFFLOAD_TX_TCP_CKSUM + | LM_OFFLOAD_TX_UDP_CKSUM; + break; + + case USER_OPTION_CKSUM_RX_ONLY: + umdevice->dev_var.enabled_oflds = LM_OFFLOAD_RX_IP_CKSUM + | LM_OFFLOAD_RX_TCP_CKSUM + | LM_OFFLOAD_RX_UDP_CKSUM; + break; + + case USER_OPTION_CKSUM_TX_RX: + umdevice->dev_var.enabled_oflds = LM_OFFLOAD_TX_IP_CKSUM + | LM_OFFLOAD_RX_IP_CKSUM + | LM_OFFLOAD_TX_TCP_CKSUM + | LM_OFFLOAD_RX_TCP_CKSUM + | LM_OFFLOAD_TX_UDP_CKSUM + | LM_OFFLOAD_RX_UDP_CKSUM; + break; + + case USER_OPTION_CKSUM_NONE: + default: + umdevice->dev_var.enabled_oflds = LM_OFFLOAD_NONE; + break; + } + + /* Ticks interval between statistics block updates. */ + option = USER_OPTION_STATSTICKS_DEFAULT; + bnx_cfg_readint(umdevice->os_param.dip, + USER_OPTION_KEYWORD_STATSTICKS, &option); + if (option >= USER_OPTION_STATSTICKS_MIN && + option <= USER_OPTION_STATSTICKS_MAX) { + lmdevice->params.stats_ticks = option; + } else { + lmdevice->params.stats_ticks = USER_OPTION_STATSTICKS_DEFAULT; + } + + /* Tx ticks for interrupt coalescing */ + option = USER_OPTION_TXTICKS_DEFAULT; + bnx_cfg_readint(umdevice->os_param.dip, + "tx_coalesce_ticks", &option); + if (option >= USER_OPTION_TICKS_MIN && + option <= USER_OPTION_TICKS_MAX) { + lmdevice->params.tx_ticks = option; + } else { + lmdevice->params.tx_ticks = USER_OPTION_TXTICKS_DEFAULT; + } + + /* Interrupt mode Tx ticks for interrupt coalescing */ + option = USER_OPTION_TXTICKS_INT_DEFAULT; + bnx_cfg_readint(umdevice->os_param.dip, + "tx_coalesce_ticks_int", &option); + if (option >= USER_OPTION_TICKS_MIN && + option <= USER_OPTION_TICKS_MAX) { + lmdevice->params.tx_ticks_int = option; + } else { + lmdevice->params.tx_ticks_int = USER_OPTION_TXTICKS_INT_DEFAULT; + } + + /* Rx ticks for interrupt coalescing */ + option = USER_OPTION_RXTICKS_DEFAULT; + bnx_cfg_readint(umdevice->os_param.dip, + "rx_coalesce_ticks", &option); + if (option >= USER_OPTION_TICKS_MIN && + option <= USER_OPTION_TICKS_MAX) { + lmdevice->params.rx_ticks = option; + } else { + lmdevice->params.rx_ticks = USER_OPTION_RXTICKS_DEFAULT; + } + + /* Interrupt mode Rx ticks for interrupt coalescing */ + option = USER_OPTION_RXTICKS_INT_DEFAULT; + bnx_cfg_readint(umdevice->os_param.dip, + "rx_coalesce_ticks_int", &option); + if (option >= USER_OPTION_TICKS_INT_MIN && + option <= USER_OPTION_TICKS_INT_MAX) { + lmdevice->params.rx_ticks_int = option; + } else { + lmdevice->params.rx_ticks_int = USER_OPTION_RXTICKS_INT_DEFAULT; + } + + + /* Tx frames for interrupt coalescing */ + option = USER_OPTION_TXFRAMES_DEFAULT; + bnx_cfg_readint(umdevice->os_param.dip, + "tx_coalesce_frames", &option); + if (option >= USER_OPTION_FRAMES_MIN && + option <= USER_OPTION_FRAMES_MAX) { + lmdevice->params.tx_quick_cons_trip = option; + } else { + lmdevice->params.tx_quick_cons_trip = + USER_OPTION_TXFRAMES_DEFAULT; + } + + /* Interrupt mode Tx frames for interrupt coalescing */ + option = USER_OPTION_TXFRAMES_INT_DEFAULT; + bnx_cfg_readint(umdevice->os_param.dip, + "tx_coalesce_frames_int", &option); + if (option >= USER_OPTION_FRAMES_MIN && + option <= USER_OPTION_FRAMES_MAX) { + lmdevice->params.tx_quick_cons_trip_int = option; + } else { + lmdevice->params.tx_quick_cons_trip_int = + USER_OPTION_TXFRAMES_INT_DEFAULT; + } + + /* Rx frames for interrupt coalescing */ + option = USER_OPTION_RXFRAMES_DEFAULT; + bnx_cfg_readint(umdevice->os_param.dip, + "rx_coalesce_frames", &option); + if (option >= USER_OPTION_FRAMES_MIN && + option <= USER_OPTION_FRAMES_MAX) { + lmdevice->params.rx_quick_cons_trip = option; + } else { + lmdevice->params.rx_quick_cons_trip = + USER_OPTION_RXFRAMES_DEFAULT; + } + + /* Interrupt mode Rx frames for interrupt coalescing */ + option = USER_OPTION_RXFRAMES_INT_DEFAULT; + bnx_cfg_readint(umdevice->os_param.dip, + "rx_coalesce_frames_int", &option); + if (option >= USER_OPTION_FRAMES_MIN && + option <= USER_OPTION_FRAMES_MAX) { + lmdevice->params.rx_quick_cons_trip_int = option; + } else { + lmdevice->params.rx_quick_cons_trip_int = + USER_OPTION_RXFRAMES_INT_DEFAULT; + } + + + option = USER_OPTION_TX_DESC_CNT_DEFAULT; + bnx_cfg_readint(umdevice->os_param.dip, + "tx_descriptor_count", &option); + if (option < USER_OPTION_TX_DESC_CNT_MIN || + option > USER_OPTION_TX_DESC_CNT_MAX) { + option = USER_OPTION_TX_DESC_CNT_DEFAULT; + } + + /* FIXME -- tx bd pages assumes 1 pd === 1 bd */ + _TX_QINFO(umdevice, 0).desc_cnt = option; + lmdevice->params.l2_tx_bd_page_cnt[0] = option / MAX_BD_PER_PAGE; + if (option % MAX_BD_PER_PAGE) { + lmdevice->params.l2_tx_bd_page_cnt[0]++; + } + if (lmdevice->params.l2_tx_bd_page_cnt[0] > 127) { + lmdevice->params.l2_tx_bd_page_cnt[0] = 127; + } + + + option = USER_OPTION_RX_DESC_CNT_DEFAULT; + bnx_cfg_readint(umdevice->os_param.dip, + "rx_descriptor_count", &option); + if (option < USER_OPTION_RX_DESC_CNT_MIN || + option > USER_OPTION_RX_DESC_CNT_MAX) { + option = USER_OPTION_RX_DESC_CNT_DEFAULT; + } + + lmdevice->params.l2_rx_desc_cnt[0] = option; + option = (option * BNX_RECV_MAX_FRAGS) / MAX_BD_PER_PAGE; + lmdevice->params.l2_rx_bd_page_cnt[0] = option; + if (option % MAX_BD_PER_PAGE) { + lmdevice->params.l2_rx_bd_page_cnt[0]++; + } + + option = USER_OPTION_MTU_DEFAULT; + bnx_cfg_readint(umdevice->os_param.dip, + "mtu", &option); + if (option < USER_OPTION_MTU_MIN) { + umdevice->dev_var.mtu = USER_OPTION_MTU_MIN; + } else if (option > USER_OPTION_MTU_MAX) { + umdevice->dev_var.mtu = USER_OPTION_MTU_MAX; + } else { + umdevice->dev_var.mtu = option; + } + lmdevice->params.mtu = umdevice->dev_var.mtu + + sizeof (struct ether_header) + VLAN_TAGSZ; + + /* Flag to enable double copy of transmit payload. */ + option = USER_OPTION_TX_DCOPY_THRESH_DEFAULT; + bnx_cfg_readint(umdevice->os_param.dip, + "tx_copy_thresh", &option); + if (option < MIN_ETHERNET_PACKET_SIZE) { + option = MIN_ETHERNET_PACKET_SIZE; + } + umdevice->tx_copy_threshold = option; + + /* Flag to enable double copy of receive packet. */ + option = USER_OPTION_RX_DCOPY_DEFAULT; + bnx_cfg_readint(umdevice->os_param.dip, USER_OPTION_KEYWORD_RX_DCOPY, + &option); + if (option) { + umdevice->rx_copy_threshold = 0xffffffff; + } else { + umdevice->rx_copy_threshold = 0; + } +} /* bnx_cfg_init */ + + +void +bnx_cfg_reset(um_device_t *const umdevice) +{ + /* Reset the link status. */ + umdevice->nddcfg.link_speed = 0; + umdevice->nddcfg.link_duplex = B_FALSE; + umdevice->nddcfg.link_tx_pause = B_FALSE; + umdevice->nddcfg.link_rx_pause = B_FALSE; + + /* Reset the link partner status. */ + umdevice->remote.link_autoneg = B_FALSE; + umdevice->remote.param_2500fdx = B_FALSE; + umdevice->remote.param_1000fdx = B_FALSE; + umdevice->remote.param_1000hdx = B_FALSE; + umdevice->remote.param_100fdx = B_FALSE; + umdevice->remote.param_100hdx = B_FALSE; + umdevice->remote.param_10fdx = B_FALSE; + umdevice->remote.param_10hdx = B_FALSE; + umdevice->remote.param_tx_pause = B_FALSE; + umdevice->remote.param_rx_pause = B_FALSE; + + /* Reset the configuration to the hardware default. */ + bcopy(&(umdevice->hwinit), &(umdevice->curcfg), sizeof (bnx_phy_cfg_t)); +} /* bnx_cfg_reset */ + + + +static lm_medium_t +bnx_cfg_map_serdes(um_device_t *const umdevice) +{ + lm_medium_t lmmedium; + lm_device_t *lmdevice; + + lmdevice = &(umdevice->lm_dev); + + lmmedium = LM_MEDIUM_TYPE_FIBER; + + if (umdevice->curcfg.lnkcfg.link_autoneg) { + if (umdevice->curcfg.lnkcfg.param_2500fdx && + umdevice->curcfg.lnkcfg.param_1000fdx && + umdevice->curcfg.lnkcfg.param_1000hdx) { + /* + * All autoneg speeds are advertised. + * Don't specify a speed so we get the full range. + */ + lmmedium |= LM_MEDIUM_SPEED_AUTONEG; + } else { + lmdevice->params.selective_autoneg = + SELECTIVE_AUTONEG_SINGLE_SPEED; + + if (umdevice->curcfg.lnkcfg.param_2500fdx) { + lmmedium |= LM_MEDIUM_SPEED_2500MBPS + | LM_MEDIUM_FULL_DUPLEX; + } else if (umdevice->curcfg.lnkcfg.param_1000fdx) { + lmmedium |= LM_MEDIUM_SPEED_1000MBPS + | LM_MEDIUM_FULL_DUPLEX; + } else if (umdevice->curcfg.lnkcfg.param_1000hdx) { + lmmedium |= LM_MEDIUM_SPEED_1000MBPS + | LM_MEDIUM_HALF_DUPLEX; + } else { + /* Configuration error. */ + lmdevice->params.selective_autoneg = + SELECTIVE_AUTONEG_OFF; + goto error; + } + } + + /* + * Enable serdes fallback for all but one particular HP + * platform. + */ + if (CHIP_NUM(lmdevice) == CHIP_NUM_5706 && + !(lmdevice->hw_info.svid == 0x103c && + lmdevice->hw_info.ssid == 0x310c)) { + if (umdevice->curcfg.lnkcfg.param_2500fdx) { + lmmedium |= + LM_MEDIUM_SPEED_AUTONEG_2_5G_FALLBACK; + } else { + lmmedium |= LM_MEDIUM_SPEED_AUTONEG_1G_FALLBACK; + } + } + } else { + if (umdevice->curcfg.lnkcfg.param_2500fdx) { + lmmedium |= LM_MEDIUM_SPEED_2500MBPS + | LM_MEDIUM_FULL_DUPLEX; + } else if (umdevice->curcfg.lnkcfg.param_1000fdx) { + lmmedium |= LM_MEDIUM_SPEED_1000MBPS + | LM_MEDIUM_FULL_DUPLEX; + } else { + /* Configuration error. */ + goto error; + } + } + + return (lmmedium); + +error: + /* Just give them full autoneg with no fallback capabilities. */ + lmmedium |= LM_MEDIUM_SPEED_AUTONEG; + + return (lmmedium); +} /* bnx_cfg_map_serdes */ + + + +static lm_medium_t +bnx_cfg_map_copper(um_device_t *const umdevice) +{ + lm_medium_t lmmedium; + lm_device_t *lmdevice; + + lmdevice = &(umdevice->lm_dev); + + lmmedium = LM_MEDIUM_TYPE_UTP; + + if (umdevice->curcfg.lnkcfg.link_autoneg) { + if (umdevice->curcfg.lnkcfg.param_1000fdx == B_TRUE && + umdevice->curcfg.lnkcfg.param_1000hdx == B_TRUE && + umdevice->curcfg.lnkcfg.param_100fdx == B_TRUE && + umdevice->curcfg.lnkcfg.param_100hdx == B_TRUE && + umdevice->curcfg.lnkcfg.param_10fdx == B_TRUE && + umdevice->curcfg.lnkcfg.param_10hdx == B_TRUE) { + /* + * All autoneg speeds are advertised. + * Don't specify a speed so we get the full range. + */ + lmmedium |= LM_MEDIUM_SPEED_AUTONEG; + } else { + lmdevice->params.selective_autoneg = + SELECTIVE_AUTONEG_SINGLE_SPEED; + + if (umdevice->curcfg.lnkcfg.param_1000fdx) { + lmmedium |= LM_MEDIUM_SPEED_1000MBPS + | LM_MEDIUM_FULL_DUPLEX; + } else if (umdevice->curcfg.lnkcfg.param_1000hdx) { + lmmedium |= LM_MEDIUM_SPEED_1000MBPS + | LM_MEDIUM_HALF_DUPLEX; + + if (umdevice->curcfg.lnkcfg.param_100fdx == + B_TRUE && + umdevice->curcfg.lnkcfg.param_100hdx == + B_TRUE && + umdevice->curcfg.lnkcfg.param_10fdx == + B_TRUE && + umdevice->curcfg.lnkcfg.param_10hdx == + B_TRUE) { + lmdevice->params.selective_autoneg = + SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS; + } + } else if (umdevice->curcfg.lnkcfg.param_100fdx) { + lmmedium |= LM_MEDIUM_SPEED_100MBPS + | LM_MEDIUM_FULL_DUPLEX; + + if (umdevice->curcfg.lnkcfg.param_100hdx == + B_TRUE && + umdevice->curcfg.lnkcfg.param_10fdx == + B_TRUE && + umdevice->curcfg.lnkcfg.param_10hdx == + B_TRUE) { + lmdevice->params.selective_autoneg = + SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS; + } + } else if (umdevice->curcfg.lnkcfg.param_100hdx) { + lmmedium |= LM_MEDIUM_SPEED_100MBPS + | LM_MEDIUM_HALF_DUPLEX; + + if (umdevice->curcfg.lnkcfg.param_10fdx == + B_TRUE && + umdevice->curcfg.lnkcfg.param_10hdx == + B_TRUE) { + lmdevice->params.selective_autoneg = + SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS; + } + } else if (umdevice->curcfg.lnkcfg.param_10fdx) { + lmmedium |= LM_MEDIUM_SPEED_10MBPS + | LM_MEDIUM_FULL_DUPLEX; + + if (umdevice->curcfg.lnkcfg.param_10hdx == + B_TRUE) { + lmdevice->params.selective_autoneg = + SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS; + } + } else if (umdevice->curcfg.lnkcfg.param_10hdx) { + lmmedium |= LM_MEDIUM_SPEED_10MBPS + | LM_MEDIUM_HALF_DUPLEX; + } else { + /* Configuration error. */ + lmdevice->params.selective_autoneg = + SELECTIVE_AUTONEG_OFF; + goto error; + } + } + } else { + /* + * Forced speeds greater than 100Mbps intentionally omitted. + * Forcing speeds greater than 100Mbps on copper media is + * illegal. + */ + if (umdevice->curcfg.lnkcfg.param_100fdx) { + lmmedium |= LM_MEDIUM_SPEED_100MBPS + | LM_MEDIUM_FULL_DUPLEX; + } else if (umdevice->curcfg.lnkcfg.param_100hdx) { + lmmedium |= LM_MEDIUM_SPEED_100MBPS + | LM_MEDIUM_HALF_DUPLEX; + } else if (umdevice->curcfg.lnkcfg.param_10fdx) { + lmmedium |= LM_MEDIUM_SPEED_10MBPS + | LM_MEDIUM_FULL_DUPLEX; + } else if (umdevice->curcfg.lnkcfg.param_10hdx) { + lmmedium |= LM_MEDIUM_SPEED_10MBPS + | LM_MEDIUM_HALF_DUPLEX; + } else { + /* Configuration error. */ + goto error; + } + } + + return (lmmedium); + +error: + /* Just give them full autoneg. */ + lmmedium |= LM_MEDIUM_SPEED_AUTONEG; + + return (lmmedium); +} /* bnx_cfg_map_copper */ + + + +/* + * Name: bnx_cfg_map_phy + * + * Input: ptr to device structure + * + * Return: None + * + * Description: This function is translates user configuration parameter, + * ones accessible through 'ndd' commands to LM driver settings. + * Driver chooses best possible parameters if conflicting ones + * are set by the user. + */ +void +bnx_cfg_map_phy(um_device_t *const umdevice) +{ + lm_medium_t lmmedium; + lm_device_t *lmdevice; + lm_flow_control_t flowctrl; + + lmdevice = &(umdevice->lm_dev); + + /* Disable the remote PHY. */ + lmdevice->params.enable_remote_phy = 0; + + /* Assume selective autonegotiation is turned off. */ + lmdevice->params.selective_autoneg = SELECTIVE_AUTONEG_OFF; + + /* FIXME -- Clean up configuration parameters. */ + if (umdevice->dev_var.isfiber) { + lmmedium = bnx_cfg_map_serdes(umdevice); + } else { + lmmedium = bnx_cfg_map_copper(umdevice); + } + + lmdevice->params.req_medium = lmmedium; + + + flowctrl = LM_FLOW_CONTROL_NONE; + + if (umdevice->curcfg.lnkcfg.param_tx_pause) { + flowctrl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; + } + + if (umdevice->curcfg.lnkcfg.param_rx_pause) { + flowctrl |= LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + + if (umdevice->curcfg.flow_autoneg == B_TRUE && + flowctrl != LM_FLOW_CONTROL_NONE) { + /* + * FIXME -- LM Flow control constraint. + * LM_FLOW_CONTROL_AUTO_PAUSE == + * (LM_FLOW_CONTROL_AUTO_PAUSE | + * LM_FLOW_CONTROL_TRANSMIT_PAUSE | + * LM_FLOW_CONTROL_RECEIVE_PAUSE) + * The LM does not allow us finer selection of what + * pause features to autoneg. + */ + flowctrl |= LM_FLOW_CONTROL_AUTO_PAUSE; + } + + lmdevice->params.flow_ctrl_cap = flowctrl; + + lmdevice->params.wire_speed = umdevice->curcfg.wirespeed; +} /* bnx_cfg_map_phy */ diff --git a/usr/src/uts/common/io/bnx/bnxcfg.h b/usr/src/uts/common/io/bnx/bnxcfg.h new file mode 100644 index 0000000000..27d898462b --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxcfg.h @@ -0,0 +1,90 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + */ + +#ifndef _BNXCFG_H +#define _BNXCFG_H + +#include "bnx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define USER_OPTION_KEYWORD_STATSTICKS "statticks" +#define USER_OPTION_KEYWORD_RX_DCOPY "RxDCopy" + + +#define USER_OPTION_CKSUM_NONE 0x0 +#define USER_OPTION_CKSUM_TX_ONLY 0x1 +#define USER_OPTION_CKSUM_RX_ONLY 0x2 +#define USER_OPTION_CKSUM_TX_RX 0x3 +#define USER_OPTION_CKSUM_DEFAULT 0x3 + +#define USER_OPTION_STATSTICKS_MIN 0 +#define USER_OPTION_STATSTICKS_MAX 1000000 +#define USER_OPTION_STATSTICKS_DEFAULT 1000000 + +#define USER_OPTION_TICKS_MIN 0 +#define USER_OPTION_TICKS_MAX LM_HC_RX_TICKS_VAL_MAX + +#define USER_OPTION_TICKS_INT_MIN 0 +#define USER_OPTION_TICKS_INT_MAX LM_HC_RX_TICKS_INT_MAX + +#define USER_OPTION_TXTICKS_DEFAULT 45 +#define USER_OPTION_TXTICKS_INT_DEFAULT 15 +#define USER_OPTION_RXTICKS_DEFAULT 20 +#define USER_OPTION_RXTICKS_INT_DEFAULT 15 + +#define USER_OPTION_FRAMES_MIN 0 +#define USER_OPTION_FRAMES_MAX LM_HC_RX_QUICK_CONS_TRIP_VAL_MAX + +#define USER_OPTION_TXFRAMES_DEFAULT 16 +#define USER_OPTION_TXFRAMES_INT_DEFAULT 8 +#define USER_OPTION_RXFRAMES_DEFAULT 4 +#define USER_OPTION_RXFRAMES_INT_DEFAULT 4 + +#define USER_OPTION_TX_DESC_CNT_MIN 1 +#define USER_OPTION_TX_DESC_CNT_MAX 32385 +#define USER_OPTION_TX_DESC_CNT_DEFAULT \ + (1024 - (1024 % MAX_BD_PER_PAGE)) + +#define USER_OPTION_RX_DESC_CNT_MIN 1 +#define USER_OPTION_RX_DESC_CNT_MAX 32385 +#define USER_OPTION_RX_DESC_CNT_DEFAULT (512 - (512 % MAX_BD_PER_PAGE)) + +#define USER_OPTION_MTU_MIN 60 +#define USER_OPTION_MTU_MAX 9000 +#define USER_OPTION_MTU_DEFAULT 1500 + +#define USER_OPTION_TX_DCOPY_THRESH_DEFAULT 512 +#define USER_OPTION_RX_DCOPY_DEFAULT 0xffffffff + + +extern const bnx_lnk_cfg_t bnx_copper_config; +extern const bnx_lnk_cfg_t bnx_serdes_config; + +void bnx_cfg_msix(um_device_t * const umdevice); +void bnx_cfg_init(um_device_t * const umdevice); +void bnx_cfg_reset(um_device_t * const umdevice); +void bnx_cfg_map_phy(um_device_t * const umdevice); + +#ifdef __cplusplus +} +#endif + +#endif /* _BNXCFG_H */ diff --git a/usr/src/uts/common/io/bnx/bnxdbg.c b/usr/src/uts/common/io/bnx/bnxdbg.c new file mode 100644 index 0000000000..c703d223c3 --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxdbg.c @@ -0,0 +1,76 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2019, Joyent, Inc. + */ + +#include "bnx.h" + +#define BNX_BUF_SIZE 256 + + +void +debug_break(void *ctx) +{ + um_device_t *um = (um_device_t *)ctx; + cmn_err(CE_PANIC, "-> %s panic <-", (um) ? um->dev_name : "(unknown)"); +} + + +void +debug_msg(void *ctx, unsigned long level, char *file, unsigned long line, + char *msg, ...) +{ + um_device_t *um = (um_device_t *)ctx; + char buf[BNX_BUF_SIZE]; + va_list argp; + + *buf = '\0'; + + if (um != NULL) { + (void) snprintf(buf, BNX_BUF_SIZE, "%s %s:%lu ", um->dev_name, + file, line); + } else { + (void) snprintf(buf, BNX_BUF_SIZE, "%s:%lu ", file, line); + } + + (void) strlcat(buf, msg, BNX_BUF_SIZE); + + va_start(argp, msg); + vcmn_err(CE_WARN, buf, argp); + va_end(argp); +} + + +void +debug_msgx(void *ctx, unsigned long level, char *msg, ...) +{ + um_device_t *um = (um_device_t *)ctx; + char buf[BNX_BUF_SIZE]; + va_list argp; + + *buf = '\0'; + + if (um != NULL) { + (void) snprintf(buf, BNX_BUF_SIZE, "%s ", um->dev_name); + } + + (void) strlcat(buf, msg, BNX_BUF_SIZE); + + va_start(argp, msg); + vcmn_err(CE_WARN, buf, argp); + va_end(argp); +} diff --git a/usr/src/uts/common/io/bnx/bnxgld.h b/usr/src/uts/common/io/bnx/bnxgld.h new file mode 100644 index 0000000000..1822d24291 --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxgld.h @@ -0,0 +1,36 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + */ + +#ifndef _BNXGLD_H +#define _BNXGLD_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bnx.h" + +int bnx_gld_init(um_device_t *const); +void bnx_gld_link(um_device_t *const, const link_state_t linkup); +int bnx_gld_fini(um_device_t *const); + +#ifdef __cplusplus +} +#endif + +#endif /* _BNXGLD_H */ diff --git a/usr/src/uts/common/io/bnx/bnxgldv3.c b/usr/src/uts/common/io/bnx/bnxgldv3.c new file mode 100644 index 0000000000..5ebc19ab26 --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxgldv3.c @@ -0,0 +1,1594 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2019, Joyent, Inc. + */ + +#include "bnxgld.h" +#include "bnxhwi.h" +#include "bnxsnd.h" +#include "bnxrcv.h" +#include "bnxcfg.h" + +#include <sys/mac_provider.h> +#include <sys/mac_ether.h> +#include <sys/dlpi.h> +#include <sys/policy.h> + +/* + * Name: bnx_m_start + * + * Input: ptr to driver device structure. + * + * Return: DDI_SUCCESS or DDI_FAILURE + * + * Description: + * This routine is called by GLD to enable device for + * packet reception and enable interrupts. + */ +static int +bnx_m_start(void *arg) +{ + int rc; + um_device_t *umdevice; + + umdevice = (um_device_t *)arg; + + mutex_enter(&umdevice->os_param.gld_mutex); + + if (umdevice->dev_start == B_TRUE) { + /* We're already started. Success! */ + rc = 0; + goto done; + } + + /* Always report the initial link state as unknown. */ + bnx_gld_link(umdevice, LINK_STATE_UNKNOWN); + + umdevice->link_updates_ok = B_TRUE; + + if (bnx_hdwr_acquire(umdevice)) { + rc = EIO; + goto done; + } + + umdevice->dev_start = B_TRUE; + + rc = 0; + +done: + mutex_exit(&umdevice->os_param.gld_mutex); + + return (rc); +} + +/* + * Name: bnx_m_stop + * + * Input: ptr to driver device structure. + * + * Return: DDI_SUCCESS or DDI_FAILURE + * + * Description: + * This routine stops packet reception by clearing RX MASK + * register. Also interrupts are disabled for this device. + */ +static void +bnx_m_stop(void *arg) +{ + um_device_t *umdevice; + + umdevice = (um_device_t *)arg; + + mutex_enter(&umdevice->os_param.gld_mutex); + + if (umdevice->dev_start == B_TRUE) { + umdevice->dev_start = B_FALSE; + umdevice->link_updates_ok = B_FALSE; + + bnx_hdwr_release(umdevice); + + /* Report the link state back to unknown. */ + bnx_gld_link(umdevice, LINK_STATE_UNKNOWN); + + umdevice->dev_var.indLink = 0; + umdevice->dev_var.indMedium = 0; + } + + mutex_exit(&umdevice->os_param.gld_mutex); +} + + + +/* + * Name: bnx_m_unicast + * + * Input: ptr to driver device structure, + * pointer to buffer containing MAC address. + * + * Return: DDI_SUCCESS or DDI_FAILURE + * + * Description: + */ +static int +bnx_m_unicast(void *arg, const uint8_t *macaddr) +{ + int rc; + um_device_t *umdevice; + lm_device_t *lmdevice; + + umdevice = (um_device_t *)arg; + lmdevice = &(umdevice->lm_dev); + + mutex_enter(&umdevice->os_param.gld_mutex); + + /* Validate MAC address */ + if (IS_ETH_MULTICAST(macaddr)) { + cmn_err(CE_WARN, "%s: Attempt to program a multicast / " + "broadcast address as a MAC address.", umdevice->dev_name); + rc = EINVAL; + goto done; + } + + if (umdevice->dev_start == B_TRUE) { + if (lm_set_mac_addr(lmdevice, 0, + &(lmdevice->params.mac_addr[0])) != LM_STATUS_SUCCESS) { + cmn_err(CE_WARN, "%s: failed to program MAC address.", + umdevice->dev_name); + rc = EIO; + goto done; + } + } + + bcopy(macaddr, &(lmdevice->params.mac_addr[0]), ETHERADDRL); + + rc = 0; + +done: + mutex_exit(&umdevice->os_param.gld_mutex); + + return (rc); +} + +static int +bnx_mc_add(um_device_t *umdevice, const uint8_t *const mc_addr) +{ + int rc; + int index; + lm_status_t lmstatus; + lm_device_t *lmdevice; + + lmdevice = &(umdevice->lm_dev); + + index = bnx_find_mchash_collision(&(lmdevice->mc_table), mc_addr); + if (index == -1) { + lmstatus = lm_add_mc(lmdevice, (u8_t *)mc_addr); + if (lmstatus == LM_STATUS_SUCCESS) { + umdevice->dev_var.rx_filter_mask |= + LM_RX_MASK_ACCEPT_MULTICAST; + rc = 0; + } else { + rc = ENOMEM; + } + } else { + lmdevice->mc_table.addr_arr[index].ref_cnt++; + rc = 0; + } + + return (rc); +} + +static int +bnx_mc_del(um_device_t *umdevice, const uint8_t *const mc_addr) +{ + int rc; + int index; + lm_status_t lmstatus; + lm_device_t *lmdevice; + + lmdevice = &(umdevice->lm_dev); + + index = bnx_find_mchash_collision(&(lmdevice->mc_table), mc_addr); + if (index == -1) { + rc = ENXIO; + } else { + lmstatus = lm_del_mc(lmdevice, + lmdevice->mc_table.addr_arr[index].mc_addr); + if (lmstatus == LM_STATUS_SUCCESS) { + if (lmdevice->mc_table.entry_cnt == 0) { + umdevice->dev_var.rx_filter_mask &= + ~LM_RX_MASK_ACCEPT_MULTICAST; + } + + rc = 0; + } else { + rc = ENXIO; + } + } + + return (rc); +} + + + +/* + * Name: bnx_m_multicast + * + * Input: ptr to driver device structure, + * boolean describing whether to enable or disable this address, + * pointer to buffer containing multicast address. + * + * Return: DDI_SUCCESS or DDI_FAILURE + * + * Description: + * This function is used to enable or disable multicast packet + * reception for particular multicast addresses. + */ +static int +bnx_m_multicast(void * arg, boolean_t multiflag, const uint8_t *multicastaddr) +{ + um_device_t *umdevice; + int rc; + + umdevice = (um_device_t *)arg; + + mutex_enter(&umdevice->os_param.gld_mutex); + + if (umdevice->dev_start != B_TRUE) { + rc = EAGAIN; + goto done; + } + + switch (multiflag) { + case B_TRUE: + rc = bnx_mc_add(umdevice, multicastaddr); + break; + + case B_FALSE: + rc = bnx_mc_del(umdevice, multicastaddr); + break; + + default: + rc = EINVAL; + break; + } + +done: + mutex_exit(&umdevice->os_param.gld_mutex); + + return (rc); +} + + + +/* + * Name: bnx_m_promiscuous + * + * Input: ptr to driver device structure, + * boolean describing whether to enable or disable promiscuous mode. + * + * Return: DDI_SUCCESS or DDI_FAILURE + * + * Description: + * This function enables promiscuous mode for this device. + * 'flags' argument determines the type of mode being set, + * "PROMISC_PHY" enables reception of all packet types including + * bad/error packets. "PROMISC_MULTI" mode will enable all + * multicast packets, unicasts and broadcast packets to be + * received. "PROMISC_NONE" will enable only broadcast and + * unicast packets. + */ +static int +bnx_m_promiscuous(void *arg, boolean_t promiscflag) +{ + int rc; + um_device_t *umdevice; + + umdevice = (um_device_t *)arg; + + mutex_enter(&umdevice->os_param.gld_mutex); + + if (umdevice->dev_start != B_TRUE) { + rc = EAGAIN; + goto done; + } + + switch (promiscflag) { + case B_TRUE: + umdevice->dev_var.rx_filter_mask |= + LM_RX_MASK_PROMISCUOUS_MODE; + break; + + case B_FALSE: + umdevice->dev_var.rx_filter_mask &= + ~LM_RX_MASK_PROMISCUOUS_MODE; + break; + + default: + rc = EINVAL; + goto done; + } + + (void) lm_set_rx_mask(&(umdevice->lm_dev), RX_FILTER_USER_IDX0, + umdevice->dev_var.rx_filter_mask); + + rc = 0; + +done: + mutex_exit(&umdevice->os_param.gld_mutex); + + return (rc); +} + + +static mblk_t * +bnx_m_tx(void *arg, mblk_t *mp) +{ + int rc; + mblk_t *nmp; + um_device_t *umdevice; + + umdevice = (um_device_t *)arg; + + rw_enter(&umdevice->os_param.gld_snd_mutex, RW_READER); + + if (umdevice->dev_start != B_TRUE || + umdevice->nddcfg.link_speed == 0) { + freemsgchain(mp); + mp = NULL; + goto done; + } + + nmp = NULL; + + while (mp) { + /* Save the next pointer, in case we do double copy. */ + nmp = mp->b_next; + mp->b_next = NULL; + + rc = bnx_xmit_ring_xmit_mblk(umdevice, 0, mp); + + if (rc == BNX_SEND_GOODXMIT) { + mp = nmp; + continue; + } + + if (rc == BNX_SEND_DEFERPKT) + mp = nmp; + else + mp->b_next = nmp; + + break; + } + +done: + rw_exit(&umdevice->os_param.gld_snd_mutex); + + return (mp); +} + + +static u64_t +shift_left32(u32_t val) +{ + lm_u64_t tmp; + + /* FIXME -- Get rid of shift_left32() */ + + tmp.as_u32.low = 0; + tmp.as_u32.high = val; + + return (tmp.as_u64); +} + + + +/* + * Name: bnx_m_stats + * + * Input: ptr to mac info structure, ptr to gld_stats struct + * + * Return: DDI_SUCCESS or DDI_FAILURE + * + * Description: bnx_m_stats() populates gld_stats structure elements + * from latest data from statistic block. + */ +static int +bnx_m_stats(void * arg, uint_t stat, uint64_t *val) +{ + int rc; + um_device_t *umdevice; + lm_device_t *lmdevice; + const bnx_lnk_cfg_t *linkconf; + + umdevice = (um_device_t *)arg; + + if (umdevice == NULL || val == NULL) { + return (EINVAL); + } + + lmdevice = &(umdevice->lm_dev); + + /* FIXME -- Fix STATS collections */ + + if (umdevice->dev_var.isfiber) { + linkconf = &bnx_serdes_config; + } else { + linkconf = &bnx_copper_config; + } + + mutex_enter(&umdevice->os_param.gld_mutex); + + if (umdevice->dev_start != B_TRUE) { + rc = EAGAIN; + goto done; + } + + *val = 0; + switch (stat) { + case MAC_STAT_IFSPEED: + *val = umdevice->nddcfg.link_speed * 1000000ull; + break; + case MAC_STAT_MULTIRCV: + *val += shift_left32( + lmdevice->vars.stats_virt->stat_IfHCInMulticastPkts_hi); + *val += + lmdevice->vars.stats_virt->stat_IfHCInMulticastPkts_lo; + break; + case MAC_STAT_BRDCSTRCV: + *val += shift_left32( + lmdevice->vars.stats_virt->stat_IfHCInBroadcastPkts_hi); + *val += + lmdevice->vars.stats_virt->stat_IfHCInBroadcastPkts_lo; + break; + case MAC_STAT_MULTIXMT: + *val += shift_left32( + lmdevice->vars.stats_virt->stat_IfHCOutMulticastPkts_hi); + *val += + lmdevice->vars.stats_virt->stat_IfHCOutMulticastPkts_lo; + break; + case MAC_STAT_BRDCSTXMT: + *val += shift_left32( + lmdevice->vars.stats_virt->stat_IfHCOutBroadcastPkts_hi); + *val += + lmdevice->vars.stats_virt->stat_IfHCOutBroadcastPkts_lo; + break; + case MAC_STAT_NORCVBUF: + *val = lmdevice->vars.stats_virt->stat_IfInMBUFDiscards; + break; + case ETHER_STAT_MACRCV_ERRORS: + case MAC_STAT_IERRORS: + *val = lmdevice->vars.stats_virt->stat_Dot3StatsFCSErrors + + lmdevice->vars.stats_virt->stat_Dot3StatsAlignmentErrors + + lmdevice->vars.stats_virt->stat_EtherStatsUndersizePkts + + lmdevice->vars.stats_virt->stat_EtherStatsOverrsizePkts; + break; + case MAC_STAT_OERRORS: + *val = lmdevice->vars.stats_virt-> + stat_emac_tx_stat_dot3statsinternalmactransmiterrors; + break; + case MAC_STAT_COLLISIONS: + *val = lmdevice->vars.stats_virt->stat_EtherStatsCollisions; + break; + case MAC_STAT_RBYTES: + *val += shift_left32( + lmdevice->vars.stats_virt->stat_IfHCInOctets_hi); + *val += + lmdevice->vars.stats_virt->stat_IfHCInOctets_lo; + break; + case MAC_STAT_IPACKETS: + *val += shift_left32(lmdevice->vars.stats_virt-> + stat_IfHCInUcastPkts_hi); + *val += lmdevice->vars.stats_virt->stat_IfHCInUcastPkts_lo; + + *val += shift_left32(lmdevice->vars.stats_virt-> + stat_IfHCInMulticastPkts_hi); + *val += lmdevice->vars.stats_virt->stat_IfHCInMulticastPkts_lo; + + *val += shift_left32(lmdevice->vars.stats_virt-> + stat_IfHCInBroadcastPkts_hi); + *val += lmdevice->vars.stats_virt->stat_IfHCInBroadcastPkts_lo; + break; + case MAC_STAT_OBYTES: + *val += shift_left32( + lmdevice->vars.stats_virt->stat_IfHCOutOctets_hi); + *val += + lmdevice->vars.stats_virt->stat_IfHCOutOctets_lo; + break; + case MAC_STAT_OPACKETS: + *val += shift_left32(lmdevice->vars.stats_virt-> + stat_IfHCOutUcastPkts_hi); + *val += lmdevice->vars.stats_virt->stat_IfHCOutUcastPkts_lo; + + *val += shift_left32(lmdevice->vars.stats_virt-> + stat_IfHCOutMulticastPkts_hi); + *val += lmdevice->vars.stats_virt->stat_IfHCOutMulticastPkts_lo; + + *val += shift_left32(lmdevice->vars.stats_virt-> + stat_IfHCOutBroadcastPkts_hi); + *val += lmdevice->vars.stats_virt->stat_IfHCOutBroadcastPkts_lo; + break; + case ETHER_STAT_ALIGN_ERRORS: + *val = lmdevice->vars.stats_virt->stat_Dot3StatsAlignmentErrors; + break; + case ETHER_STAT_FCS_ERRORS: + *val = lmdevice->vars.stats_virt->stat_Dot3StatsFCSErrors; + break; + case ETHER_STAT_FIRST_COLLISIONS: + *val = lmdevice->vars.stats_virt-> + stat_Dot3StatsSingleCollisionFrames; + break; + case ETHER_STAT_MULTI_COLLISIONS: + *val = lmdevice->vars.stats_virt-> + stat_Dot3StatsMultipleCollisionFrames; + break; + case ETHER_STAT_DEFER_XMTS: + *val = lmdevice->vars.stats_virt-> + stat_Dot3StatsDeferredTransmissions; + break; + case ETHER_STAT_TX_LATE_COLLISIONS: + *val = lmdevice->vars.stats_virt-> + stat_Dot3StatsLateCollisions; + break; + case ETHER_STAT_EX_COLLISIONS: + *val = lmdevice->vars.stats_virt-> + stat_Dot3StatsExcessiveCollisions; + break; + case ETHER_STAT_MACXMT_ERRORS: + *val = lmdevice->vars.stats_virt-> + stat_emac_tx_stat_dot3statsinternalmactransmiterrors; + break; + case ETHER_STAT_CARRIER_ERRORS: + *val = lmdevice->vars.stats_virt-> + stat_Dot3StatsCarrierSenseErrors; + break; + case ETHER_STAT_TOOLONG_ERRORS: + *val = lmdevice->vars.stats_virt-> + stat_EtherStatsOverrsizePkts; + break; +#if (MAC_VERSION > 1) + case ETHER_STAT_TOOSHORT_ERRORS: + *val = lmdevice->vars.stats_virt-> + stat_EtherStatsUndersizePkts; + break; +#endif + case ETHER_STAT_XCVR_ADDR: + *val = lmdevice->params.phy_addr; + break; + case ETHER_STAT_XCVR_ID: + *val = lmdevice->hw_info.phy_id; + break; + case ETHER_STAT_XCVR_INUSE: + switch (umdevice->nddcfg.link_speed) { + case 1000: + *val = (umdevice->dev_var.isfiber) ? + XCVR_1000X : XCVR_1000T; + break; + case 100: + *val = XCVR_100X; + break; + case 10: + *val = XCVR_10; + break; + default: + *val = XCVR_NONE; + break; + } + break; + case ETHER_STAT_CAP_1000FDX: + *val = 1; + break; + case ETHER_STAT_CAP_1000HDX: + *val = linkconf->param_1000hdx; + break; + case ETHER_STAT_CAP_100FDX: + *val = linkconf->param_100fdx; + break; + case ETHER_STAT_CAP_100HDX: + *val = linkconf->param_100hdx; + break; + case ETHER_STAT_CAP_10FDX: + *val = linkconf->param_10fdx; + break; + case ETHER_STAT_CAP_10HDX: + *val = linkconf->param_10hdx; + break; + case ETHER_STAT_CAP_ASMPAUSE: + *val = 1; + break; + case ETHER_STAT_CAP_PAUSE: + *val = 1; + break; + case ETHER_STAT_CAP_AUTONEG: + *val = 1; + break; +#if (MAC_VERSION > 1) + case ETHER_STAT_CAP_REMFAULT: + *val = 1; + break; +#endif + case ETHER_STAT_ADV_CAP_1000FDX: + *val = umdevice->curcfg.lnkcfg.param_1000fdx; + break; + case ETHER_STAT_ADV_CAP_1000HDX: + *val = umdevice->curcfg.lnkcfg.param_1000hdx; + break; + case ETHER_STAT_ADV_CAP_100FDX: + *val = umdevice->curcfg.lnkcfg.param_100fdx; + break; + case ETHER_STAT_ADV_CAP_100HDX: + *val = umdevice->curcfg.lnkcfg.param_100hdx; + break; + case ETHER_STAT_ADV_CAP_10FDX: + *val = umdevice->curcfg.lnkcfg.param_10fdx; + break; + case ETHER_STAT_ADV_CAP_10HDX: + *val = umdevice->curcfg.lnkcfg.param_10hdx; + break; + case ETHER_STAT_ADV_CAP_ASMPAUSE: + *val = 1; + break; + case ETHER_STAT_ADV_CAP_PAUSE: + *val = 1; + break; + case ETHER_STAT_ADV_CAP_AUTONEG: + *val = umdevice->curcfg.lnkcfg.link_autoneg; + break; +#if (MAC_VERSION > 1) + case ETHER_STAT_ADV_REMFAULT: + *val = 1; + break; +#endif + case ETHER_STAT_LP_CAP_1000FDX: + *val = umdevice->remote.param_1000fdx; + break; + case ETHER_STAT_LP_CAP_1000HDX: + *val = umdevice->remote.param_1000hdx; + break; + case ETHER_STAT_LP_CAP_100FDX: + *val = umdevice->remote.param_100fdx; + break; + case ETHER_STAT_LP_CAP_100HDX: + *val = umdevice->remote.param_100hdx; + break; + case ETHER_STAT_LP_CAP_10FDX: + *val = umdevice->remote.param_10fdx; + break; + case ETHER_STAT_LP_CAP_10HDX: + *val = umdevice->remote.param_10hdx; + break; + case ETHER_STAT_LP_CAP_ASMPAUSE: + /* FIXME -- Implement LP_ASYM_PAUSE stat */ + break; + case ETHER_STAT_LP_CAP_PAUSE: + /* FIXME -- Implement LP_PAUSE stat */ + break; + case ETHER_STAT_LP_CAP_AUTONEG: + *val = umdevice->remote.link_autoneg; + break; +#if (MAC_VERSION > 1) + case ETHER_STAT_LP_REMFAULT: + /* FIXME -- Implement LP_REMFAULT stat */ + break; +#endif + case ETHER_STAT_LINK_ASMPAUSE: + /* FIXME -- Implement ASMPAUSE stat */ + break; + case ETHER_STAT_LINK_PAUSE: + /* FIXME -- Implement PAUSE stat */ + break; + case ETHER_STAT_LINK_AUTONEG: + *val = umdevice->curcfg.lnkcfg.link_autoneg; + break; + case ETHER_STAT_LINK_DUPLEX: + *val = umdevice->nddcfg.link_duplex == B_TRUE ? + LINK_DUPLEX_FULL: LINK_DUPLEX_HALF; + break; + default: + rc = ENOTSUP; + } + + rc = 0; + +done: + mutex_exit(&umdevice->os_param.gld_mutex); + + return (rc); +} + +static boolean_t +bnx_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) +{ + um_device_t *umdevice; + + umdevice = (um_device_t *)arg; + + switch (cap) { + case MAC_CAPAB_HCKSUM: { + uint32_t *txflags = cap_data; + + *txflags = 0; + + if (umdevice->dev_var.enabled_oflds & + (LM_OFFLOAD_TX_IP_CKSUM | LM_OFFLOAD_RX_IP_CKSUM)) { + *txflags |= HCKSUM_IPHDRCKSUM; + } + + if (umdevice->dev_var.enabled_oflds & + (LM_OFFLOAD_TX_TCP_CKSUM | LM_OFFLOAD_TX_UDP_CKSUM | + LM_OFFLOAD_RX_TCP_CKSUM | LM_OFFLOAD_RX_UDP_CKSUM)) { + *txflags |= HCKSUM_INET_FULL_V4; + } + break; + } + default: + return (B_FALSE); + } + + return (B_TRUE); +} + +static int +bnx_refresh_rx_tx_pkts(um_device_t *umdevice) +{ + if (umdevice->os_param.active_resc_flag & DRV_RESOURCE_HDWR_REGISTER) { + bnx_hdwr_fini(umdevice); + /* + * Initialize the adapter resource. Mainly allocating memory + * needed by the driver, such as packet descriptors, shared + * memory, etc. + */ + if (lm_init_resc(&(umdevice->lm_dev)) != LM_STATUS_SUCCESS) { + return (EIO); + } + + if (bnx_txpkts_init(umdevice)) { + return (EIO); + } + + if (bnx_rxpkts_init(umdevice)) { + return (EIO); + } + } + return (0); +} + +static int +bnx_set_priv_prop(um_device_t *umdevice, const char *pr_name, + uint_t pr_valsize, const void *pr_val) +{ + boolean_t refresh = B_FALSE; + long result; + int err = 0; + + if (strcmp(pr_name, "_adv_2500fdx_cap") == 0) { + if (lm_get_medium(&umdevice->lm_dev) != LM_MEDIUM_TYPE_FIBER) { + return (ENOTSUP); + } + if (ddi_strtol(pr_val, (char **)NULL, 0, &result)) { + return (EINVAL); + } + if (result != 1 && result != 0) { + return (EINVAL); + } + if (umdevice->hwinit.lnkcfg.param_2500fdx != (uint32_t)result) { + umdevice->hwinit.lnkcfg.param_2500fdx = + (uint32_t)result; + umdevice->curcfg.lnkcfg.param_2500fdx = + (uint32_t)result; + bnx_update_phy(umdevice); + } + } else if (strcmp(pr_name, "_checksum") == 0) { + if (umdevice->dev_start == B_TRUE) { + return (EBUSY); + } + if (ddi_strtol(pr_val, (char **)NULL, 0, &result)) { + return (EINVAL); + } + switch (result) { + case USER_OPTION_CKSUM_TX_ONLY: + umdevice->dev_var.enabled_oflds = + LM_OFFLOAD_TX_IP_CKSUM | + LM_OFFLOAD_TX_TCP_CKSUM | + LM_OFFLOAD_TX_UDP_CKSUM; + break; + + case USER_OPTION_CKSUM_RX_ONLY: + umdevice->dev_var.enabled_oflds = + LM_OFFLOAD_RX_IP_CKSUM | + LM_OFFLOAD_RX_TCP_CKSUM | + LM_OFFLOAD_RX_UDP_CKSUM; + break; + + case USER_OPTION_CKSUM_TX_RX: + umdevice->dev_var.enabled_oflds = + LM_OFFLOAD_TX_IP_CKSUM | + LM_OFFLOAD_RX_IP_CKSUM | + LM_OFFLOAD_TX_TCP_CKSUM | + LM_OFFLOAD_RX_TCP_CKSUM | + LM_OFFLOAD_TX_UDP_CKSUM | + LM_OFFLOAD_RX_UDP_CKSUM; + break; + + case USER_OPTION_CKSUM_NONE: + umdevice->dev_var.enabled_oflds = + LM_OFFLOAD_NONE; + break; + + default: + return (EINVAL); + } + } else if (strcmp(pr_name, "_tx_descriptor_count") == 0) { + if (umdevice->dev_start == B_TRUE) { + return (EBUSY); + } + if (ddi_strtol(pr_val, (char **)NULL, 0, &result)) { + return (EINVAL); + } + if (result < USER_OPTION_TX_DESC_CNT_MIN || + result > USER_OPTION_TX_DESC_CNT_MAX) { + return (EINVAL); + } + _TX_QINFO(umdevice, 0).desc_cnt = result; + umdevice->lm_dev.params.l2_tx_bd_page_cnt[0] = + result / MAX_BD_PER_PAGE; + if (result % MAX_BD_PER_PAGE) { + umdevice->lm_dev.params.l2_tx_bd_page_cnt[0]++; + } + if (umdevice->lm_dev.params.l2_tx_bd_page_cnt[0] > 127) { + umdevice->lm_dev.params.l2_tx_bd_page_cnt[0] = 127; + } + refresh = B_TRUE; + } else if (strcmp(pr_name, "_rx_descriptor_count") == 0) { + if (umdevice->dev_start == B_TRUE) { + return (EBUSY); + } + if (ddi_strtol(pr_val, (char **)NULL, 0, &result)) { + return (EINVAL); + } + if (result < USER_OPTION_RX_DESC_CNT_MIN || + result > USER_OPTION_RX_DESC_CNT_MAX) { + return (EINVAL); + } + umdevice->lm_dev.params.l2_rx_desc_cnt[0] = result; + result = (result * BNX_RECV_MAX_FRAGS) / MAX_BD_PER_PAGE; + umdevice->lm_dev.params.l2_rx_bd_page_cnt[0] = result; + if (result % MAX_BD_PER_PAGE) { + umdevice->lm_dev.params.l2_rx_bd_page_cnt[0]++; + } + refresh = B_TRUE; + } +#if 0 + /* Initialized by init_hc() */ + else if (strcmp(pr_name, "_tx_coalesce_ticks") == 0) { + if (umdevice->dev_start == B_TRUE) { + return (EBUSY); + } + if (ddi_strtol(pr_val, (char **)NULL, 0, &result)) { + return (EINVAL); + } + if (result < USER_OPTION_TICKS_MIN || + result > USER_OPTION_TICKS_MAX) { + return (EINVAL); + } + umdevice->lm_dev.params.tx_ticks = result; + } else if (strcmp(pr_name, "_tx_coalesce_ticks_int") == 0) { + if (umdevice->dev_start == B_TRUE) { + return (EBUSY); + } + if (ddi_strtol(pr_val, (char **)NULL, 0, &result)) { + return (EINVAL); + } + if (result < USER_OPTION_TICKS_INT_MIN || + result > USER_OPTION_TICKS_INT_MAX) { + return (EINVAL); + } + umdevice->lm_dev.params.tx_ticks_int = result; + } else if (strcmp(pr_name, "_rx_coalesce_ticks") == 0) { + if (umdevice->dev_start == B_TRUE) { + return (EBUSY); + } + if (ddi_strtol(pr_val, (char **)NULL, 0, &result)) { + return (EINVAL); + } + if (result < USER_OPTION_TICKS_MIN || + result > USER_OPTION_TICKS_MAX) { + return (EINVAL); + } + umdevice->lm_dev.params.rx_ticks = result; + } else if (strcmp(pr_name, "_rx_coalesce_ticks_int") == 0) { + if (umdevice->dev_start == B_TRUE) { + return (EBUSY); + } + if (ddi_strtol(pr_val, (char **)NULL, 0, &result)) { + return (EINVAL); + } + if (result < USER_OPTION_TICKS_INT_MIN || + result > USER_OPTION_TICKS_INT_MAX) { + return (EINVAL); + } + umdevice->lm_dev.params.rx_ticks_int = result; + } else if (strcmp(pr_name, "_tx_coalesce_frames") == 0) { + if (umdevice->dev_start == B_TRUE) { + return (EBUSY); + } + if (ddi_strtol(pr_val, (char **)NULL, 0, &result)) { + return (EINVAL); + } + if (result < USER_OPTION_FRAMES_MIN || + result > USER_OPTION_FRAMES_MAX) { + return (EINVAL); + } + umdevice->lm_dev.params.tx_quick_cons_trip = result; + } else if (strcmp(pr_name, "_tx_coalesce_frames_int") == 0) { + if (umdevice->dev_start == B_TRUE) { + return (EBUSY); + } + if (ddi_strtol(pr_val, (char **)NULL, 0, &result)) { + return (EINVAL); + } + if (result < USER_OPTION_FRAMES_MIN || + result > USER_OPTION_FRAMES_MAX) { + return (EINVAL); + } + umdevice->lm_dev.params.tx_quick_cons_trip_int = result; + } else if (strcmp(pr_name, "_rx_coalesce_frames") == 0) { + if (umdevice->dev_start == B_TRUE) { + return (EBUSY); + } + if (ddi_strtol(pr_val, (char **)NULL, 0, &result)) { + return (EINVAL); + } + if (result < USER_OPTION_FRAMES_MIN || + result > USER_OPTION_FRAMES_MAX) { + return (EINVAL); + } + umdevice->lm_dev.params.rx_quick_cons_trip = result; + } else if (strcmp(pr_name, "_rx_coalesce_frames_int") == 0) { + if (umdevice->dev_start == B_TRUE) { + return (EBUSY); + } + if (ddi_strtol(pr_val, (char **)NULL, 0, &result)) { + return (EINVAL); + } + if (result < USER_OPTION_FRAMES_MIN || + result > USER_OPTION_FRAMES_MAX) { + return (EINVAL); + } + umdevice->lm_dev.params.rx_quick_cons_trip_int = result; + } else if (strcmp(pr_name, "_statticks") == 0) { + if (umdevice->dev_start == B_TRUE) { + return (EBUSY); + } + if (ddi_strtol(pr_val, (char **)NULL, 0, &result)) { + return (EINVAL); + } + if (result < USER_OPTION_STATSTICKS_MIN || + result > USER_OPTION_STATSTICKS_MAX) { + return (EINVAL); + } + umdevice->lm_dev.params.stats_ticks = result; + } +#endif + else if (strcmp(pr_name, "_disable_msix") == 0) { + err = ENOTSUP; + } else { + err = ENOTSUP; + } + + if (!err && refresh) { + err = bnx_refresh_rx_tx_pkts(umdevice); + } + return (err); +} + + +static int +bnx_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, + uint_t pr_valsize, const void *pr_val) +{ + um_device_t *umdevice = arg; + boolean_t reprogram = B_FALSE; + boolean_t rxpause; + boolean_t txpause; + uint32_t mtu; + link_flowctrl_t fl; + int err = 0; + + mutex_enter(&umdevice->os_param.gld_mutex); + + if (lm_get_medium(&umdevice->lm_dev) == LM_MEDIUM_TYPE_FIBER) { + if (pr_num == MAC_PROP_EN_100FDX_CAP || + pr_num == MAC_PROP_EN_100HDX_CAP || + pr_num == MAC_PROP_EN_10FDX_CAP || + pr_num == MAC_PROP_EN_10HDX_CAP) { + mutex_exit(&umdevice->os_param.gld_mutex); + return (ENOTSUP); + } + } + + switch (pr_num) { + /* read-only properties */ + case MAC_PROP_ADV_1000FDX_CAP: + case MAC_PROP_ADV_1000HDX_CAP: + case MAC_PROP_ADV_100FDX_CAP: + case MAC_PROP_ADV_100HDX_CAP: + case MAC_PROP_ADV_10FDX_CAP: + case MAC_PROP_ADV_10HDX_CAP: + case MAC_PROP_STATUS: + case MAC_PROP_SPEED: + case MAC_PROP_DUPLEX: + default: + + err = ENOTSUP; + break; + + +/* BEGIN CSTYLED */ +#define BNX_SETPROP_CASE(cap, param) \ + case cap: \ + if (umdevice->hwinit.lnkcfg.param != *(uint8_t *)pr_val) { \ + umdevice->hwinit.lnkcfg.param = *(uint8_t *)pr_val; \ + umdevice->curcfg.lnkcfg.param = *(uint8_t *)pr_val; \ + reprogram = B_TRUE; \ + } \ + break +/* END CSTYLED */ + + + BNX_SETPROP_CASE(MAC_PROP_EN_1000FDX_CAP, param_1000fdx); + BNX_SETPROP_CASE(MAC_PROP_EN_1000HDX_CAP, param_1000hdx); + BNX_SETPROP_CASE(MAC_PROP_EN_100FDX_CAP, param_100fdx); + BNX_SETPROP_CASE(MAC_PROP_EN_100HDX_CAP, param_100hdx); + BNX_SETPROP_CASE(MAC_PROP_EN_10FDX_CAP, param_10fdx); + BNX_SETPROP_CASE(MAC_PROP_EN_10HDX_CAP, param_10hdx); + BNX_SETPROP_CASE(MAC_PROP_AUTONEG, link_autoneg); + + case MAC_PROP_FLOWCTRL: + bcopy(pr_val, &fl, sizeof (fl)); + switch (fl) { + case LINK_FLOWCTRL_NONE: + + rxpause = B_FALSE; + txpause = B_FALSE; + break; + + case LINK_FLOWCTRL_RX: + + rxpause = B_TRUE; + txpause = B_FALSE; + break; + + case LINK_FLOWCTRL_TX: + + rxpause = B_FALSE; + txpause = B_TRUE; + break; + + case LINK_FLOWCTRL_BI: + + rxpause = B_TRUE; + txpause = B_TRUE; + break; + + default: + + err = ENOTSUP; + break; + } + + if (err == 0) { + if (umdevice->hwinit.lnkcfg.param_tx_pause != + txpause || + umdevice->hwinit.lnkcfg.param_rx_pause != + rxpause) { + umdevice->hwinit.lnkcfg.param_tx_pause = + txpause; + umdevice->hwinit.lnkcfg.param_rx_pause = + rxpause; + umdevice->curcfg.lnkcfg.param_tx_pause = + txpause; + umdevice->curcfg.lnkcfg.param_rx_pause = + rxpause; + reprogram = B_TRUE; + } + } + + break; + + case MAC_PROP_MTU: + if (umdevice->dev_start == B_TRUE) { + err = EBUSY; + break; + } + + bcopy(pr_val, &mtu, sizeof (mtu)); + + if (mtu < USER_OPTION_MTU_MIN || + mtu > USER_OPTION_MTU_MAX) { + err = EINVAL; + break; + } + + if (umdevice->dev_var.mtu == mtu) { + break; + } + + umdevice->dev_var.mtu = mtu; + umdevice->lm_dev.params.mtu = umdevice->dev_var.mtu + + sizeof (struct ether_header) + VLAN_TAGSZ; + + if (bnx_refresh_rx_tx_pkts(umdevice) != 0) { + err = EIO; + } else { + reprogram = B_TRUE; + } + break; + + case MAC_PROP_PRIVATE: + err = bnx_set_priv_prop(umdevice, pr_name, pr_valsize, + pr_val); + reprogram = B_TRUE; + break; + } + + if (!err && reprogram) { + bnx_update_phy(umdevice); + } + + mutex_exit(&umdevice->os_param.gld_mutex); + + return (err); +} + +static int +bnx_get_priv_prop(um_device_t *umdevice, const char *pr_name, + uint_t pr_valsize, void *pr_val) +{ + int value; + + if (strcmp(pr_name, "_adv_2500fdx_cap") == 0) { + if (lm_get_medium(&umdevice->lm_dev) != + LM_MEDIUM_TYPE_FIBER) { + return (ENOTSUP); + } + value = umdevice->curcfg.lnkcfg.param_2500fdx; + } else if (strcmp(pr_name, "_checksum") == 0) { + value = umdevice->dev_var.enabled_oflds; + } else if (strcmp(pr_name, "_tx_descriptor_count") == 0) { + value = _TX_QINFO(umdevice, 0).desc_cnt; + } else if (strcmp(pr_name, "_rx_descriptor_count") == 0) { + value = umdevice->lm_dev.params.l2_rx_desc_cnt[0]; + } else if (strcmp(pr_name, "_tx_coalesce_ticks") == 0) { + value = umdevice->lm_dev.params.tx_ticks; + } else if (strcmp(pr_name, "_tx_coalesce_ticks_int") == 0) { + value = umdevice->lm_dev.params.tx_ticks_int; + } else if (strcmp(pr_name, "_rx_coalesce_ticks") == 0) { + value = umdevice->lm_dev.params.rx_ticks; + } else if (strcmp(pr_name, "_rx_coalesce_ticks_int") == 0) { + value = umdevice->lm_dev.params.rx_ticks_int; + } else if (strcmp(pr_name, "_tx_coalesce_frames") == 0) { + value = umdevice->lm_dev.params.tx_quick_cons_trip; + } else if (strcmp(pr_name, "_tx_coalesce_frames_int") == 0) { + value = umdevice->lm_dev.params.tx_quick_cons_trip_int; + } else if (strcmp(pr_name, "_rx_coalesce_frames") == 0) { + value = umdevice->lm_dev.params.rx_quick_cons_trip; + } else if (strcmp(pr_name, "_rx_coalesce_frames_int") == 0) { + value = umdevice->lm_dev.params.rx_quick_cons_trip_int; + } else if (strcmp(pr_name, "_statticks") == 0) { + value = umdevice->lm_dev.params.stats_ticks; + } else if (strcmp(pr_name, "_disable_msix") == 0) { + value = umdevice->dev_var.disableMsix; + } else { + return (ENOTSUP); + } + + (void) snprintf(pr_val, pr_valsize, "%d", value); + return (0); + +} + +static int +bnx_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, + uint_t pr_valsize, void *pr_val) +{ + um_device_t *umdevice = arg; + link_duplex_t link_duplex; + uint64_t link_speed; + link_state_t link_state; + link_flowctrl_t fl; + + if (lm_get_medium(&umdevice->lm_dev) == LM_MEDIUM_TYPE_FIBER) { + if (pr_num == MAC_PROP_EN_100FDX_CAP || + pr_num == MAC_PROP_EN_100HDX_CAP || + pr_num == MAC_PROP_EN_10FDX_CAP || + pr_num == MAC_PROP_EN_10HDX_CAP) { + return (ENOTSUP); + } + } + + switch (pr_num) { + case MAC_PROP_DUPLEX: + link_duplex = umdevice->nddcfg.link_duplex == B_TRUE ? + LINK_DUPLEX_FULL: LINK_DUPLEX_HALF; + + ASSERT(pr_valsize >= sizeof (link_duplex_t)); + + bcopy(&link_duplex, pr_val, sizeof (link_duplex_t)); + break; + + case MAC_PROP_SPEED: + link_speed = umdevice->nddcfg.link_speed * 1000000ull; + + ASSERT(pr_valsize >= sizeof (link_speed)); + + bcopy(&link_speed, pr_val, sizeof (link_speed)); + break; + + case MAC_PROP_STATUS: + link_state = umdevice->nddcfg.link_speed ? + LINK_STATE_UP : LINK_STATE_DOWN; + + ASSERT(pr_valsize >= sizeof (link_state_t)); + + bcopy(&link_state, pr_val, sizeof (link_state)); + break; + + case MAC_PROP_AUTONEG: + *(uint8_t *)pr_val = + umdevice->curcfg.lnkcfg.link_autoneg; + break; + + case MAC_PROP_FLOWCTRL: + ASSERT(pr_valsize >= sizeof (fl)); + + boolean_t txpause = + umdevice->curcfg.lnkcfg.param_tx_pause; + boolean_t rxpause = + umdevice->curcfg.lnkcfg.param_rx_pause; + if (txpause) { + if (rxpause) { + fl = LINK_FLOWCTRL_BI; + } else { + fl = LINK_FLOWCTRL_TX; + } + } else { + if (rxpause) { + fl = LINK_FLOWCTRL_RX; + } else { + fl = LINK_FLOWCTRL_NONE; + } + } + bcopy(&fl, pr_val, sizeof (fl)); + break; + + case MAC_PROP_ADV_1000FDX_CAP: + *(uint8_t *)pr_val = + umdevice->curcfg.lnkcfg.param_1000fdx; + break; + + case MAC_PROP_EN_1000FDX_CAP: + *(uint8_t *)pr_val = + umdevice->curcfg.lnkcfg.param_1000fdx; + break; + + case MAC_PROP_ADV_1000HDX_CAP: + *(uint8_t *)pr_val = + umdevice->curcfg.lnkcfg.param_1000hdx; + break; + + case MAC_PROP_EN_1000HDX_CAP: + *(uint8_t *)pr_val = + umdevice->curcfg.lnkcfg.param_1000hdx; + break; + + case MAC_PROP_ADV_100FDX_CAP: + *(uint8_t *)pr_val = + umdevice->curcfg.lnkcfg.param_100fdx; + break; + + case MAC_PROP_EN_100FDX_CAP: + *(uint8_t *)pr_val = + umdevice->curcfg.lnkcfg.param_100fdx; + break; + + case MAC_PROP_ADV_100HDX_CAP: + *(uint8_t *)pr_val = + umdevice->curcfg.lnkcfg.param_100hdx; + break; + + case MAC_PROP_EN_100HDX_CAP: + *(uint8_t *)pr_val = + umdevice->curcfg.lnkcfg.param_100hdx; + break; + + case MAC_PROP_ADV_10FDX_CAP: + *(uint8_t *)pr_val = + umdevice->curcfg.lnkcfg.param_10fdx; + break; + + case MAC_PROP_EN_10FDX_CAP: + *(uint8_t *)pr_val = + umdevice->curcfg.lnkcfg.param_10fdx; + break; + + case MAC_PROP_ADV_10HDX_CAP: + *(uint8_t *)pr_val = + umdevice->curcfg.lnkcfg.param_10hdx; + break; + + case MAC_PROP_EN_10HDX_CAP: + *(uint8_t *)pr_val = + umdevice->curcfg.lnkcfg.param_10hdx; + break; + + case MAC_PROP_PRIVATE: + return (bnx_get_priv_prop(umdevice, pr_name, pr_valsize, + pr_val)); + + default: + + return (ENOTSUP); + + } + + return (0); + +} + +static void +bnx_priv_propinfo(um_device_t *umdevice, const char *pr_name, + mac_prop_info_handle_t prh) +{ + char valstr[64]; + int value; + + if (strcmp(pr_name, "_adv_2500fdx_cap") == 0) { + if (lm_get_medium(&umdevice->lm_dev) != LM_MEDIUM_TYPE_FIBER) { + return; + } + value = umdevice->curcfg.lnkcfg.param_2500fdx; + } else if (strcmp(pr_name, "_checksum") == 0) { + value = umdevice->dev_var.enabled_oflds; + } else if (strcmp(pr_name, "_tx_descriptor_count") == 0) { + value = _TX_QINFO(umdevice, 0).desc_cnt; + } else if (strcmp(pr_name, "_rx_descriptor_count") == 0) { + value = umdevice->lm_dev.params.l2_rx_desc_cnt[0]; + } else if (strcmp(pr_name, "_tx_coalesce_ticks") == 0) { + value = umdevice->lm_dev.params.tx_ticks; + } else if (strcmp(pr_name, "_tx_coalesce_ticks_int") == 0) { + value = umdevice->lm_dev.params.tx_ticks_int; + } else if (strcmp(pr_name, "_rx_coalesce_ticks") == 0) { + value = umdevice->lm_dev.params.rx_ticks; + } else if (strcmp(pr_name, "_rx_coalesce_ticks_int") == 0) { + value = umdevice->lm_dev.params.rx_ticks_int; + } else if (strcmp(pr_name, "_tx_coalesce_frames") == 0) { + value = umdevice->lm_dev.params.tx_quick_cons_trip; + } else if (strcmp(pr_name, "_tx_coalesce_frames_int") == 0) { + value = umdevice->lm_dev.params.tx_quick_cons_trip_int; + } else if (strcmp(pr_name, "_rx_coalesce_frames") == 0) { + value = umdevice->lm_dev.params.rx_quick_cons_trip; + } else if (strcmp(pr_name, "_rx_coalesce_frames_int") == 0) { + value = umdevice->lm_dev.params.rx_quick_cons_trip_int; + } else if (strcmp(pr_name, "_statticks") == 0) { + value = umdevice->lm_dev.params.stats_ticks; + } else if (strcmp(pr_name, "_disable_msix") == 0) { + value = umdevice->dev_var.disableMsix; + } else { + return; + } + + (void) snprintf(valstr, sizeof (valstr), "%d", value); + mac_prop_info_set_default_str(prh, valstr); + +} + +static void +bnx_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t pr_num, + mac_prop_info_handle_t prh) +{ + um_device_t *umdevice = arg; + + if (lm_get_medium(&umdevice->lm_dev) == LM_MEDIUM_TYPE_FIBER) { + if (pr_num == MAC_PROP_EN_100FDX_CAP || + pr_num == MAC_PROP_ADV_100FDX_CAP || + pr_num == MAC_PROP_EN_100HDX_CAP || + pr_num == MAC_PROP_ADV_100HDX_CAP || + pr_num == MAC_PROP_EN_10FDX_CAP || + pr_num == MAC_PROP_ADV_10FDX_CAP || + pr_num == MAC_PROP_EN_10HDX_CAP || + pr_num == MAC_PROP_ADV_10HDX_CAP) { + mac_prop_info_set_default_uint8(prh, 0); + return; + } + } + switch (pr_num) { + case MAC_PROP_ADV_1000FDX_CAP: + case MAC_PROP_ADV_1000HDX_CAP: + case MAC_PROP_ADV_100FDX_CAP: + case MAC_PROP_ADV_100HDX_CAP: + case MAC_PROP_ADV_10FDX_CAP: + case MAC_PROP_ADV_10HDX_CAP: + case MAC_PROP_STATUS: + case MAC_PROP_SPEED: + case MAC_PROP_DUPLEX: + + mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); + break; + + case MAC_PROP_EN_1000FDX_CAP: + + mac_prop_info_set_default_uint8(prh, 1); + break; + + case MAC_PROP_EN_1000HDX_CAP: + case MAC_PROP_EN_100FDX_CAP: + case MAC_PROP_EN_100HDX_CAP: + case MAC_PROP_EN_10FDX_CAP: + case MAC_PROP_EN_10HDX_CAP: + + if (lm_get_medium(&umdevice->lm_dev) == + LM_MEDIUM_TYPE_FIBER) { + mac_prop_info_set_default_uint8(prh, 0); + } else { + mac_prop_info_set_default_uint8(prh, 1); + } + break; + + case MAC_PROP_AUTONEG: + + mac_prop_info_set_default_uint8(prh, 1); + break; + + case MAC_PROP_FLOWCTRL: + + mac_prop_info_set_default_link_flowctrl(prh, + LINK_FLOWCTRL_BI); + break; + + case MAC_PROP_MTU: + + mac_prop_info_set_range_uint32(prh, + USER_OPTION_MTU_MIN, USER_OPTION_MTU_MAX); + break; + + case MAC_PROP_PRIVATE: + + bnx_priv_propinfo(umdevice, pr_name, prh); + break; + default: + break; + } +} + +static mac_callbacks_t bnx_callbacks = { + (MC_GETCAPAB | MC_SETPROP | MC_GETPROP| MC_PROPINFO), + bnx_m_stats, + bnx_m_start, + bnx_m_stop, + bnx_m_promiscuous, + bnx_m_multicast, + bnx_m_unicast, + bnx_m_tx, + NULL, + NULL, + bnx_m_getcapab, + NULL, + NULL, + bnx_m_setprop, + bnx_m_getprop, + bnx_m_propinfo +}; + + + +/* + * Name: bnx_gld_init + * + * Input: ptr to device structure. + * + * Return: DDI_SUCCESS or DDI_FAILURE + * + * Description: + * This routine populates mac info structure for this device + * instance and registers device with GLD. + */ +int +bnx_gld_init(um_device_t *const umdevice) +{ + mac_register_t *macp; + int rc; + + umdevice->dev_start = B_FALSE; + + mutex_init(&umdevice->os_param.gld_mutex, NULL, + MUTEX_DRIVER, DDI_INTR_PRI(umdevice->intrPriority)); + + rw_init(&umdevice->os_param.gld_snd_mutex, NULL, RW_DRIVER, NULL); + + macp = mac_alloc(MAC_VERSION); + if (macp == NULL) { + cmn_err(CE_WARN, + "%s: Failed to allocate GLD MAC memory.\n", + umdevice->dev_name); + goto error; + } + + macp->m_driver = umdevice; + macp->m_dip = umdevice->os_param.dip; + macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; + macp->m_callbacks = &bnx_callbacks; + macp->m_min_sdu = 0; + macp->m_max_sdu = umdevice->dev_var.mtu; + macp->m_src_addr = &(umdevice->lm_dev.params.mac_addr[0]); + + macp->m_margin = VLAN_TAG_SIZE; + + /* + * Call mac_register() after initializing all + * the required elements of mac_t struct. + */ + rc = mac_register(macp, &umdevice->os_param.macp); + + mac_free(macp); + + if (rc != 0) { + cmn_err(CE_WARN, + "%s: Failed to register with GLD.\n", + umdevice->dev_name); + goto error; + } + + /* Always report the initial link state as unknown. */ + bnx_gld_link(umdevice, LINK_STATE_UNKNOWN); + + return (0); + +error: + rw_destroy(&umdevice->os_param.gld_snd_mutex); + mutex_destroy(&umdevice->os_param.gld_mutex); + + return (-1); +} + +void +bnx_gld_link(um_device_t * const umdevice, const link_state_t linkup) +{ + mac_link_update(umdevice->os_param.macp, linkup); +} + +int +bnx_gld_fini(um_device_t * const umdevice) +{ + if (umdevice->dev_start != B_FALSE) { + cmn_err(CE_WARN, + "%s: Detaching device from GLD that is still started!!!\n", + umdevice->dev_name); + return (-1); + } + + if (mac_unregister(umdevice->os_param.macp)) { + cmn_err(CE_WARN, + "%s: Failed to unregister with the GLD.\n", + umdevice->dev_name); + return (-1); + } + + rw_destroy(&umdevice->os_param.gld_snd_mutex); + mutex_destroy(&umdevice->os_param.gld_mutex); + + return (0); +} diff --git a/usr/src/uts/common/io/bnx/bnxhwi.c b/usr/src/uts/common/io/bnx/bnxhwi.c new file mode 100644 index 0000000000..aedd4fbde1 --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxhwi.c @@ -0,0 +1,402 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2019, Joyent, Inc. + */ + +#include "bnx.h" +#include "bnx_mm.h" +#include "bnxsnd.h" +#include "bnxrcv.h" +#include "bnxint.h" +#include "bnxtmr.h" +#include "bnxcfg.h" + +void +bnx_update_phy(um_device_t * const umdevice) +{ + lm_status_t lmstatus; + lm_device_t *lmdevice; + + lmdevice = &(umdevice->lm_dev); + + /* Map 'ndd' parameters to LM struct. */ + bnx_cfg_map_phy(umdevice); + + mutex_enter(&umdevice->os_param.phy_mutex); + + /* Reset, re-program and bring-up phy. */ + lmstatus = lm_init_phy(lmdevice, lmdevice->params.req_medium, + lmdevice->params.flow_ctrl_cap, lmdevice->params.selective_autoneg, + lmdevice->params.wire_speed, 0); + if (lmstatus != LM_STATUS_SUCCESS) { + cmn_err(CE_WARN, "%s: Failed to configure the PHY.", + umdevice->dev_name); + } + + lm_service_phy_int(lmdevice, TRUE); + + mutex_exit(&umdevice->os_param.phy_mutex); +} + +ddi_dma_handle_t * +bnx_find_dma_hdl(um_device_t *const umdevice, const void *const virtaddr) +{ + int i; + ddi_dma_handle_t *dmahdl; + + dmahdl = NULL; + for (i = 0; i < umdevice->os_param.dma_handles_used; i++) { + if (umdevice->os_param.dma_virt[i] == virtaddr) { + dmahdl = &(umdevice->os_param.dma_handle[i]); + } + } + + return (dmahdl); +} + +static void +bnx_free_lmmem(um_device_t * const umdevice) +{ + int i; + bnx_memreq_t *memreq; + ddi_dma_handle_t *dma_handle; + ddi_acc_handle_t *acc_handle; + + if (umdevice->os_param.dma_handles_used != 0) { + i = umdevice->os_param.dma_handles_used - 1; + + dma_handle = &(umdevice->os_param.dma_handle[i]); + acc_handle = &(umdevice->os_param.dma_acc_handle[i]); + + /* Free all shared memory. */ + for (; i >= 0; i--) { + (void) ddi_dma_unbind_handle(*dma_handle); + + ddi_dma_mem_free(acc_handle); + + ddi_dma_free_handle(dma_handle); + + dma_handle--; + acc_handle--; + } + + umdevice->os_param.dma_handles_used = 0; + } + + if (umdevice->memcnt != 0) { + /* Free all local memory. */ + for (i = umdevice->memcnt - 1; i >= 0; i--) { + memreq = &umdevice->memreq[i]; + + kmem_free(memreq->addr, memreq->size); + + memreq->addr = NULL; + memreq->size = 0; + } + + umdevice->memcnt = 0; + } +} + +int +bnx_hdwr_init(um_device_t *const umdevice) +{ + lm_status_t lmstatus; + lm_device_t *lmdevice; + + lmdevice = &(umdevice->lm_dev); + + lmstatus = lm_get_dev_info(lmdevice); + if (lmstatus != LM_STATUS_SUCCESS) { + cmn_err(CE_WARN, "%s: Failed to get device information.\n", + umdevice->dev_name); + return (-1); + } + + /* + * Initialize the adapter resource. Mainly allocating memory needed + * by the driver, such as packet descriptors, shared memory, etc. + */ + lmstatus = lm_init_resc(lmdevice); + if (lmstatus != LM_STATUS_SUCCESS) { + cmn_err(CE_WARN, "%s: Failed to allocate device resources.\n", + umdevice->dev_name); + goto error1; + } + + if (bnx_txpkts_init(umdevice)) { + goto error1; + } + + if (bnx_rxpkts_init(umdevice)) { + goto error2; + } + + /* Find the DMA handle associated with the status block memory. */ + umdevice->os_param.status_block_dma_hdl = bnx_find_dma_hdl(umdevice, + (void *)(umdevice->lm_dev.vars.status_virt)); + + /* Reset the local interrupt event index. */ + umdevice->dev_var.processed_status_idx = 0; + + /* Initialize the receive mask to a sane default. */ + umdevice->dev_var.rx_filter_mask = LM_RX_MASK_ACCEPT_UNICAST | + LM_RX_MASK_ACCEPT_BROADCAST; + + return (0); + +error2: + bnx_txpkts_fini(umdevice); + +error1: + bnx_free_lmmem(umdevice); + + return (-1); +} + +int +bnx_hdwr_acquire(um_device_t *const umdevice) +{ + lm_status_t lmstatus; + lm_device_t *lmdevice; + + lmdevice = &(umdevice->lm_dev); + + /* Reset the configuration to the hardware default. */ + bnx_cfg_reset(umdevice); + + /* + * A call to lm_reset() implicitly means we are relieving the firmware + * of it's responsibility to maintain the device. The driver assumes + * control. The LM vars.medium field normally gets set with a call to + * lm_init_phy(), but this function cannot be called before we assume + * control of the device. If we did, we run the risk of contending + * with the firmware for PHY accesses. Do the next best thing. + */ + lmdevice->vars.medium = lm_get_medium(lmdevice); + + /* Map 'ndd' parameters to LM struct. */ + bnx_cfg_map_phy(umdevice); + + /* Bring the chip under driver control. */ + lmstatus = lm_reset(lmdevice, LM_REASON_DRIVER_RESET); + if (lmstatus != LM_STATUS_SUCCESS) { + cmn_err(CE_WARN, "%s: Failed to reset chip.\n", + umdevice->dev_name); + return (-1); + } + + /* Configure the PHY to the requested settings. */ + lmstatus = lm_init_phy(lmdevice, lmdevice->params.req_medium, + lmdevice->params.flow_ctrl_cap, lmdevice->params.selective_autoneg, + lmdevice->params.wire_speed, 0); + if (lmstatus != LM_STATUS_SUCCESS) { + cmn_err(CE_WARN, "%s: Failed to initialize the PHY.", + umdevice->dev_name); + } + + lm_service_phy_int(lmdevice, FALSE); /* force a phy status update */ + + umdevice->dev_var.indLink = lmdevice->vars.link_status; + umdevice->dev_var.indMedium = lmdevice->vars.medium; + + /* + * Need to clear TX PATCH scratch register at offset 0x420 + * to instruct chip to do full TCP checksum calculations. + */ + REG_WR_IND(lmdevice, (OFFSETOF(reg_space_t, tpat.tpat_scratch[0]) + + 0x420), 0); + + FLUSHPOSTEDWRITES(lmdevice); + + umdevice->recv_discards = 0; + + /* Make sure the rx statistics counters are reset. */ + bzero(&(lmdevice->rx_info.stats), sizeof (lm_rx_stats_t)); + + /* Post rx buffers to the chip. */ + (void) lm_post_buffers(lmdevice, 0, NULL); + + /* Allow the hardware to accept rx traffic. */ + (void) lm_set_rx_mask(lmdevice, RX_FILTER_USER_IDX0, + umdevice->dev_var.rx_filter_mask); + + FLUSHPOSTEDWRITES(lmdevice); + + /* Enable interrupts. */ + bnx_intr_enable(umdevice); + + /* Start the periodic timer. */ + bnx_timer_start(umdevice); + + return (0); +} + +void +bnx_hdwr_release(um_device_t *const umdevice) +{ + int reason; + lm_device_t *lmdevice; + + lmdevice = &(umdevice->lm_dev); + + /* Stop the periodic timer. */ + bnx_timer_stop(umdevice); + + /* Disable interrupts. */ + bnx_intr_disable(umdevice); + + /* + * In Solaris when RX traffic is accepted, the system might generate + * and attempt to send some TX packets (from within gld_recv() !). + * Claiming any TX locks before this point would create a deadlock. + * The ISR would be waiting for a lock acquired here that would never + * be freed, since we in-turn would be waiting for the ISR to finish + * here. Consequently, we acquire the TX lock as soon as we know that + * no TX traffic is a result of RX traffic. + */ + rw_enter(&umdevice->os_param.gld_snd_mutex, RW_WRITER); + + /* Set RX mask to stop receiving any further packets */ + (void) lm_set_rx_mask(lmdevice, RX_FILTER_USER_IDX0, + LM_RX_MASK_ACCEPT_NONE); + + FLUSHPOSTEDWRITES(lmdevice); + + if (umdevice->dev_var.fw_ver < FW_VER_WITH_UNLOAD_POWER_DOWN) { + reason = LM_REASON_DRIVER_SHUTDOWN; + } else { + reason = LM_REASON_DRIVER_UNLOAD_POWER_DOWN; + } + + lm_chip_reset(lmdevice, reason); + + FLUSHPOSTEDWRITES(lmdevice); + + /* Reclaim all tx buffers submitted to the hardware. */ + bnx_txpkts_flush(umdevice); + + /* Reclaim all rx buffers submitted to the hardware. */ + bnx_rxpkts_recycle(umdevice); + + rw_exit(&umdevice->os_param.gld_snd_mutex); +} + +void +bnx_hdwr_fini(um_device_t *const umdevice) +{ + bnx_rxpkts_fini(umdevice); + + bnx_txpkts_fini(umdevice); + + bnx_free_lmmem(umdevice); +} + +static u32_t +compute_crc32(const u8_t *const buf, u32_t buf_size) +{ + u32_t reg; + u32_t tmp; + u32_t j; + u32_t k; + + reg = 0xffffffff; + + for (j = 0; j < buf_size; j++) { + reg ^= buf[j]; + + for (k = 0; k < 8; k++) { + tmp = reg & 0x01; + + reg >>= 1; + + if (tmp) { + reg ^= 0xedb88320; + } + } + } + + return (~reg); +} + +int +bnx_find_mchash_collision(lm_mc_table_t *mc_table, const uint8_t *const mc_addr) +{ + u32_t cur_bit_pos; + u32_t tgt_bit_pos; + u32_t idx; + u32_t crc32; + + crc32 = compute_crc32(mc_addr, ETHERNET_ADDRESS_SIZE); + + tgt_bit_pos = ~crc32 & 0xff; + + for (idx = 0; idx < mc_table->entry_cnt; idx++) { + crc32 = compute_crc32(mc_table->addr_arr[idx].mc_addr, + ETHERNET_ADDRESS_SIZE); + + /* + * The most significant 7 bits of the CRC32 (no inversion), + * are used to index into one of the possible 128 bit positions. + */ + cur_bit_pos = ~crc32 & 0xff; + + if (tgt_bit_pos == cur_bit_pos) { + return (idx); + } + } + + return (-1); +} + + + +/* + * Name: um_send_driver_pulse + * + * Input: ptr to driver structure + * + * Return: none + * + * Description: um_send_driver_pulse routine sends heartbeat pulse to firmware. + */ +void +um_send_driver_pulse(um_device_t *const umdevice) +{ + u32_t msg_code; + u32_t offset; + lm_device_t *lmdevice; + + lmdevice = &(umdevice->lm_dev); + + offset = lmdevice->hw_info.shmem_base; + offset += OFFSETOF(shmem_region_t, drv_fw_mb.drv_pulse_mb); + + mutex_enter(&umdevice->os_param.ind_mutex); + + lmdevice->vars.drv_pulse_wr_seq++; + + msg_code = lmdevice->vars.drv_pulse_wr_seq & DRV_PULSE_SEQ_MASK; + + mutex_exit(&umdevice->os_param.ind_mutex); + + if (lmdevice->params.test_mode & TEST_MODE_DRIVER_PULSE_ALWAYS_ALIVE) { + msg_code |= DRV_PULSE_ALWAYS_ALIVE; + } + + REG_WR_IND(lmdevice, offset, msg_code); +} diff --git a/usr/src/uts/common/io/bnx/bnxhwi.h b/usr/src/uts/common/io/bnx/bnxhwi.h new file mode 100644 index 0000000000..91d64b1d07 --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxhwi.h @@ -0,0 +1,37 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + */ + +#ifndef _BNXHWI_H +#define _BNXHWI_H + +#include "bnx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int bnx_hdwr_init(um_device_t * const umdevice); +int bnx_hdwr_acquire(um_device_t * const umdevice); +void bnx_hdwr_release(um_device_t * const umdevice); +void bnx_hdwr_fini(um_device_t * const umdevice); + +#ifdef __cplusplus +} +#endif + +#endif /* _BNXHWI_H */ diff --git a/usr/src/uts/common/io/bnx/bnxint.c b/usr/src/uts/common/io/bnx/bnxint.c new file mode 100644 index 0000000000..93290393fc --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxint.c @@ -0,0 +1,455 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2019, Joyent, Inc. + */ + +#include "bnxint.h" +#include "bnxsnd.h" +#include "bnxrcv.h" + + +#define BNX_INTR_NUMBER 0 + +/* + * Name: bnx_intr_priv + * + * Input: ptr to um_device_t + * + * Return: Interrupt status + * + * Description: + * This routine is called from ISR and POLL API routines to consume + * any pending events. This function determines if there is any + * pending status and calls corresponding LM functions to consume + * the event. L2 driver consumes three events - L2 Tx compete, + * L2 Rx indication and link status change. + */ +static lm_interrupt_status_t +bnx_intr_priv(um_device_t *const umdevice) +{ + u32_t idx; + lm_device_t *lmdevice; + lm_interrupt_status_t intrstat; + + lmdevice = &(umdevice->lm_dev); + + /* + * Following LM routine checks for pending interrupts and + * returns corresponding bits set in a 32bit integer value. + */ + intrstat = lm_get_interrupt_status(lmdevice); + + if (intrstat & LM_KNOCK_KNOCK_EVENT) { + um_send_driver_pulse(umdevice); + } + + if (intrstat & LM_RX_EVENT_MASK) { + for (idx = RX_CHAIN_IDX0; idx < NUM_RX_CHAIN; idx++) { + if (intrstat & (LM_RX0_EVENT_ACTIVE << idx)) { + s_list_t *waitq; + + waitq = &(_RX_QINFO(umdevice, idx).waitq); + + mutex_enter(&umdevice->os_param.rcv_mutex); + (void) lm_get_packets_rcvd(lmdevice, idx, 0, + waitq); + mutex_exit(&umdevice->os_param.rcv_mutex); + } + } + } + + if (intrstat & LM_TX_EVENT_MASK) { + for (idx = TX_CHAIN_IDX0; idx < NUM_TX_CHAIN; idx++) { + if (intrstat & (LM_TX0_EVENT_ACTIVE << idx)) { + /* This call is mutex protected internally. */ + bnx_xmit_ring_intr(umdevice, idx); + } + } + } + + if (intrstat & LM_PHY_EVENT_ACTIVE) { + mutex_enter(&umdevice->os_param.phy_mutex); + lm_service_phy_int(lmdevice, FALSE); + mutex_exit(&umdevice->os_param.phy_mutex); + } + + return (intrstat); +} + +/* + * Description: + * + * This function sends rx traffic up the stack and replenishes the hardware + * rx buffers. Although we share the responsibility of replenishing the + * rx buffers with the timer, we still need to wait here indefinitely. This + * is the only place where we send rx traffic back up the stack. + * + * We go through a lot of mental gymnastics to make sure we are not holding a + * lock while calling gld_recv(). We can deadlock in the following scenario + * if we aren't careful : + * + * Thread 1: + * bnx_intr_disable() + * bnx_intr_wait() + * mutex_enter(intr_*_mutex) + * + * Thread 2: + * bnx_intr_[soft|1lvl]() + * bnx_intr_recv() + * mutex_enter(rcv_mutex) + * + * Thread 3: + * bnx_intr_[soft|1lvl]() + * mutex_enter(intr_*_mutex) + * mutex_enter(rcv_mutex) + * + * Return: + */ +static void +bnx_intr_recv(um_device_t * const umdevice) +{ + mutex_enter(&umdevice->os_param.rcv_mutex); + + if (umdevice->intr_enabled == B_TRUE) { + /* + * Send the rx packets up. This function will release and + * acquire the receive mutex across calls to gld_recv(). + */ + bnx_rxpkts_intr(umdevice); + } + + /* + * Since gld_recv() can hang while decommisioning the driver, we + * need to double check that interrupts are still enabled before + * attempting to replenish the rx buffers. + */ + if (umdevice->intr_enabled == B_TRUE) { + /* This function does an implicit *_fill(). */ + bnx_rxpkts_post(umdevice); + } + + mutex_exit(&umdevice->os_param.rcv_mutex); +} + +static void +bnx_intr_xmit(um_device_t *const umdevice) +{ + mutex_enter(&umdevice->os_param.xmit_mutex); + + if (umdevice->intr_enabled == B_TRUE) { + /* + * Send the tx packets in waitq & notify the GLD. + */ + bnx_txpkts_intr(umdevice); + } + + mutex_exit(&umdevice->os_param.xmit_mutex); +} + +static unsigned int +bnx_intr_1lvl(caddr_t arg1, caddr_t arg2) +{ + lm_device_t *lmdevice; + um_device_t *umdevice; + lm_interrupt_status_t intrstat = 0; + u32_t value32; + umdevice = (um_device_t *)arg1; + + lmdevice = &(umdevice->lm_dev); + + mutex_enter(&umdevice->intr_mutex); + + if (umdevice->intr_enabled != B_TRUE) { + /* + * The interrupt cannot be ours. Interrupts + * from our device have been disabled. + */ + mutex_exit(&umdevice->intr_mutex); + umdevice->intr_in_disabled++; + return (DDI_INTR_UNCLAIMED); + } + + /* Make sure we are working with current data. */ + (void) ddi_dma_sync(*(umdevice->os_param.status_block_dma_hdl), 0, + STATUS_BLOCK_BUFFER_SIZE, DDI_DMA_SYNC_FORKERNEL); + + /* Make sure it is our device that is interrupting. */ + if (lmdevice->vars.status_virt->deflt.status_idx == + umdevice->dev_var.processed_status_idx) { + /* + * It is possible that we could have arrived at the ISR + * before the status block had a chance to be DMA'd into + * host memory. Reading the status of the INTA line will + * implicitly force the DMA, and inform us of whether we + * are truly interrupting. INTA is active low. + */ + REG_RD(lmdevice, pci_config.pcicfg_misc_status, &value32); + if (value32 & PCICFG_MISC_STATUS_INTA_VALUE) { + /* This isn't our interrupt. */ + umdevice->intr_no_change++; + mutex_exit(&umdevice->intr_mutex); + return (DDI_INTR_UNCLAIMED); + } + } + + umdevice->intrFired++; + + /* Disable interrupt and enqueue soft intr processing. */ + REG_WR(lmdevice, pci_config.pcicfg_int_ack_cmd, + (PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | + PCICFG_INT_ACK_CMD_MASK_INT)); + + FLUSHPOSTEDWRITES(lmdevice); + + umdevice->dev_var.processed_status_idx = + lmdevice->vars.status_virt->deflt.status_idx; + + /* Service the interrupts. */ + intrstat = bnx_intr_priv(umdevice); + + value32 = umdevice->dev_var.processed_status_idx; + value32 |= PCICFG_INT_ACK_CMD_INDEX_VALID; + + /* + * Inform the hardware of the last interrupt event we processed + * and reinstate the hardware's ability to assert interrupts. + */ + REG_WR(lmdevice, pci_config.pcicfg_int_ack_cmd, value32); + + FLUSHPOSTEDWRITES(lmdevice); + + umdevice->intr_count++; + + if (intrstat & LM_RX_EVENT_MASK) { + bnx_intr_recv(umdevice); + } + + if (intrstat & LM_TX_EVENT_MASK) { + bnx_intr_xmit(umdevice); + } + + mutex_exit(&umdevice->intr_mutex); + + return (DDI_INTR_CLAIMED); +} + +void +bnx_intr_enable(um_device_t * const umdevice) +{ + int rc; + + umdevice->intr_count = 0; + + /* + * Allow interrupts to touch the hardware. + */ + umdevice->intr_enabled = B_TRUE; + + if ((rc = ddi_intr_enable(umdevice->pIntrBlock[0])) != DDI_SUCCESS) { + cmn_err(CE_WARN, "%s: Failed to enable default isr block (%d)", + umdevice->dev_name, rc); + return; /* XXX return error */ + } + + /* Allow the hardware to generate interrupts. */ + lm_enable_int(&(umdevice->lm_dev)); + + FLUSHPOSTEDWRITES(&(umdevice->lm_dev)); + + /* + * XXX This delay is here because of a discovered problem regarding a + * call to ddi_intr_disable immediately after enabling interrupts. This + * can occur with the "ifconfig -a plumb up" command which brings an + * interface up/down/up/down/up. There seems to be a race condition + * between the ddi_intr_enable/lm_enable_int and ddi_intr_disable + * routines that results in interrupts to no longer fire on the + * interface and a REBOOT IS REQUIRED to fix! + */ + drv_usecwait(2000000); +} + +/* + * Description: + * + * This function makes sure the ISR no longer touches the hardware. It + * accomplishes this by making sure the ISR either completes, or that it + * acknowledges the intr_enabled status change. + * + * Return: + */ +static void +bnx_intr_wait(um_device_t * const umdevice) +{ + if (mutex_tryenter(&umdevice->intr_mutex)) { + /* + * If we were able to get the hardware interrupt mutex, then it + * means that either the ISR wasn't processing at this time, or + * that it was at the end, processing the receive packets. If it + * the latter case, then all we need to do is acquire the + * rcv_mutex. If we can acquire it, it means the receive + * processing is stalled, waiting for a GLD mutex, or that the + * ISR is not processing RX packets. + */ + mutex_enter(&umdevice->os_param.rcv_mutex); + mutex_exit(&umdevice->os_param.rcv_mutex); + } else { + /* + * We couldn't acquire the hardware interrupt mutex. This means + * the ISR is running. Wait for it to complete by + * (re)attempting to acquire the interrupt mutex. Whether we + * acquire it immediately or not, we will know the ISR has + * acknowledged the intr_enabled status change. + */ + mutex_enter(&umdevice->intr_mutex); + } + mutex_exit(&umdevice->intr_mutex); +} + + +void +bnx_intr_disable(um_device_t * const umdevice) +{ + int rc; + + /* + * Prevent any future interrupts to no longer touch the hardware. + */ + umdevice->intr_enabled = B_FALSE; + + /* + * Wait for any currently running interrupt to complete. + */ + bnx_intr_wait(umdevice); + + /* Stop the device from generating any interrupts. */ + lm_disable_int(&(umdevice->lm_dev)); + + FLUSHPOSTEDWRITES(&(umdevice->lm_dev)); + + if ((rc = ddi_intr_disable(umdevice->pIntrBlock[0])) != DDI_SUCCESS) { + cmn_err(CE_WARN, "%s: Failed to disable default isr (%d)", + umdevice->dev_name, rc); + } +} + +int +bnxIntrInit(um_device_t *umdevice) +{ + dev_info_t *pDev = umdevice->os_param.dip; + int intrActual, rc; + + if ((umdevice->pIntrBlock = kmem_zalloc(sizeof (ddi_intr_handle_t), + KM_SLEEP)) == NULL) { + cmn_err(CE_WARN, "%s: Failed to allocate interrupt handle " + "block!", umdevice->dev_name); + return (-1); + } + + umdevice->intrType = (umdevice->dev_var.disableMsix) ? + DDI_INTR_TYPE_FIXED : DDI_INTR_TYPE_MSIX; + + while (1) { + if ((rc = ddi_intr_alloc(pDev, umdevice->pIntrBlock, + umdevice->intrType, 0, 1, &intrActual, + DDI_INTR_ALLOC_NORMAL)) != DDI_SUCCESS) { + cmn_err(CE_WARN, "!%s: Failed to initialize default " + "%s isr handle block (%d)", umdevice->dev_name, + (umdevice->intrType == DDI_INTR_TYPE_MSIX) ? + "MSIX" : "Fixed", rc); + + if (umdevice->intrType == DDI_INTR_TYPE_MSIX) { + cmn_err(CE_WARN, "!%s: Reverting to Fixed " + "level interrupts", umdevice->dev_name); + + umdevice->intrType = DDI_INTR_TYPE_FIXED; + continue; + } else { + kmem_free(umdevice->pIntrBlock, + sizeof (ddi_intr_handle_t)); + return (-1); + } + } + break; + } + + if (intrActual != 1) { + cmn_err(CE_WARN, "%s: Failed to alloc minimum default " + "isr handler!", umdevice->dev_name); + (void) ddi_intr_free(umdevice->pIntrBlock[0]); + kmem_free(umdevice->pIntrBlock, sizeof (ddi_intr_handle_t)); + return (-1); + } + + if ((rc = ddi_intr_get_pri(umdevice->pIntrBlock[0], + &umdevice->intrPriority)) != DDI_SUCCESS) { + cmn_err(CE_WARN, "%s: Failed to get isr priority (%d)", + umdevice->dev_name, rc); + (void) ddi_intr_free(umdevice->pIntrBlock[0]); + kmem_free(umdevice->pIntrBlock, sizeof (ddi_intr_handle_t)); + return (-1); + } + + if (umdevice->intrPriority >= ddi_intr_get_hilevel_pri()) { + cmn_err(CE_WARN, "%s: Interrupt priority is too high", + umdevice->dev_name); + (void) ddi_intr_free(umdevice->pIntrBlock[0]); + kmem_free(umdevice->pIntrBlock, sizeof (ddi_intr_handle_t)); + return (-1); + } + + if ((rc = ddi_intr_add_handler(umdevice->pIntrBlock[0], bnx_intr_1lvl, + (caddr_t)umdevice, NULL)) != DDI_SUCCESS) { + cmn_err(CE_WARN, "%s: Failed to add the default isr " + "handler (%d)", umdevice->dev_name, rc); + (void) ddi_intr_free(umdevice->pIntrBlock[0]); + kmem_free(umdevice->pIntrBlock, sizeof (ddi_intr_handle_t)); + return (-1); + } + + /* Intialize the mutex used by the hardware interrupt handler. */ + mutex_init(&umdevice->intr_mutex, NULL, MUTEX_DRIVER, + DDI_INTR_PRI(umdevice->intrPriority)); + + umdevice->lm_dev.vars.interrupt_mode = + (umdevice->intrType == DDI_INTR_TYPE_FIXED) ? + IRQ_MODE_LINE_BASED : IRQ_MODE_MSIX_BASED; + return (0); +} + +void +bnxIntrFini(um_device_t *umdevice) +{ + int ret; + + if ((ret = ddi_intr_disable(umdevice->pIntrBlock[0])) != 0) { + dev_err(umdevice->os_param.dip, CE_WARN, + "failed to disable interrupt: %d", ret); + } + if ((ret = ddi_intr_remove_handler(umdevice->pIntrBlock[0])) != 0) { + dev_err(umdevice->os_param.dip, CE_WARN, + "failed to remove interrupt: %d", ret); + } + if ((ret = ddi_intr_free(umdevice->pIntrBlock[0])) != 0) { + dev_err(umdevice->os_param.dip, CE_WARN, + "failed to free interrupt: %d", ret); + } + kmem_free(umdevice->pIntrBlock, sizeof (ddi_intr_handle_t)); + + umdevice->pIntrBlock = NULL; + + mutex_destroy(&umdevice->intr_mutex); +} diff --git a/usr/src/uts/common/io/bnx/bnxint.h b/usr/src/uts/common/io/bnx/bnxint.h new file mode 100644 index 0000000000..d864af4966 --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxint.h @@ -0,0 +1,39 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2019, Joyent, Inc. + */ + +#ifndef _BNXINT_H +#define _BNXINT_H + +#include "bnx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void bnx_intr_enable(um_device_t *const); +void bnx_intr_disable(um_device_t *const); + +int bnxIntrInit(um_device_t *); +void bnxIntrFini(um_device_t *); + +#ifdef __cplusplus +} +#endif + +#endif /* _BNXINT_H */ diff --git a/usr/src/uts/common/io/bnx/bnxmod.c b/usr/src/uts/common/io/bnx/bnxmod.c new file mode 100644 index 0000000000..c106361176 --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxmod.c @@ -0,0 +1,578 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2019, Joyent, Inc. + */ + +#include "bnx.h" +#include "bnxgld.h" +#include "bnxhwi.h" +#include "bnxint.h" +#include "bnxtmr.h" +#include "bnxcfg.h" + +#define BNX_PRODUCT_BANNER "QLogic 570x/571x Gigabit Ethernet Driver "\ + BRCMVERSION + +#define BNX_PRODUCT_INFO "QLogic 570x/571x GbE "\ + BRCMVERSION + +ddi_device_acc_attr_t bnxAccessAttribBAR = { + DDI_DEVICE_ATTR_V0, /* devacc_attr_version */ + DDI_STRUCTURE_LE_ACC, /* devacc_attr_endian_flags */ + DDI_STRICTORDER_ACC, /* devacc_attr_dataorder */ + DDI_DEFAULT_ACC /* devacc_attr_access */ +}; + +ddi_device_acc_attr_t bnxAccessAttribBUF = { + DDI_DEVICE_ATTR_V0, /* devacc_attr_version */ + DDI_NEVERSWAP_ACC, /* devacc_attr_endian_flags */ + DDI_STRICTORDER_ACC, /* devacc_attr_dataorder */ + DDI_DEFAULT_ACC /* devacc_attr_access */ +}; + + +/* + * Name: bnx_free_system_resources + * + * Input: ptr to device structure + * + * Return: void + * + * Description: + * This function is called from detach() entry point to free most + * resources held by this device instance. + */ +static int +bnx_free_system_resources(um_device_t * const umdevice) +{ + if (umdevice->os_param.active_resc_flag & DRV_RESOURCE_MINOR_NODE) { + umdevice->os_param.active_resc_flag &= ~DRV_RESOURCE_MINOR_NODE; +#ifdef _USE_FRIENDLY_NAME + ddi_remove_minor_node(umdevice->os_param.dip, + (char *)ddi_driver_name(umdevice->os_param.dip)); +#else + ddi_remove_minor_node(umdevice->os_param.dip, + ddi_get_name(umdevice->os_param.dip)); +#endif + } + + if (umdevice->os_param.active_resc_flag & DRV_RESOURCE_TIMER) { + umdevice->os_param.active_resc_flag &= + ~DRV_RESOURCE_TIMER; + bnx_timer_fini(umdevice); + } + + if (umdevice->os_param.active_resc_flag & DRV_RESOURCE_GLD_REGISTER) { + if (bnx_gld_fini(umdevice)) { + /* + * FIXME -- If bnx_gld_fini() fails, we need to + * reactivate resources. + */ + return (-1); + } + umdevice->os_param.active_resc_flag &= + ~DRV_RESOURCE_GLD_REGISTER; + } + + if (umdevice->os_param.active_resc_flag & DRV_RESOURCE_KSTAT) { + umdevice->os_param.active_resc_flag &= ~DRV_RESOURCE_KSTAT; + bnx_kstat_fini(umdevice); + } + + if (umdevice->os_param.active_resc_flag & DRV_RESOURCE_HDWR_REGISTER) { + umdevice->os_param.active_resc_flag &= + ~DRV_RESOURCE_HDWR_REGISTER; + bnx_hdwr_fini(umdevice); + } + + if (umdevice->os_param.active_resc_flag & DRV_RESOURCE_MUTEX) { + umdevice->os_param.active_resc_flag &= ~DRV_RESOURCE_MUTEX; + mutex_destroy(&umdevice->os_param.ind_mutex); + mutex_destroy(&umdevice->os_param.phy_mutex); + mutex_destroy(&umdevice->os_param.rcv_mutex); + } + + if (umdevice->os_param.active_resc_flag & DRV_RESOURCE_INTR_1) { + umdevice->os_param.active_resc_flag &= ~DRV_RESOURCE_INTR_1; + bnxIntrFini(umdevice); + } + + if (umdevice->os_param.active_resc_flag & DRV_RESOURCE_MAP_REGS) { + umdevice->os_param.active_resc_flag &= ~DRV_RESOURCE_MAP_REGS; + ddi_regs_map_free(&umdevice->os_param.reg_acc_handle); + umdevice->lm_dev.vars.dmaRegAccHandle = NULL; + umdevice->os_param.reg_acc_handle = NULL; + } + + if (umdevice->os_param.active_resc_flag & DRV_RESOURCE_PCICFG_MAPPED) { + umdevice->os_param.active_resc_flag &= + ~DRV_RESOURCE_PCICFG_MAPPED; + pci_config_teardown(&umdevice->os_param.pci_cfg_handle); + } + + return (0); +} + + + +/* + * Name: bnx_attach_attach + * + * Input: ptr to dev_info_t + * + * Return: DDI_SUCCESS or DDI_FAILURE. + * + * Description: This is the main code involving all important driver data struct + * and device initialization stuff. This function allocates driver + * soft state for this instance of the driver, sets access up + * attributes for the device, maps BAR register space, initializes + * the hardware, determines interrupt pin, registers interrupt + * service routine with the OS and initializes receive/transmit + * mutex. After successful completion of above mentioned tasks, + * the driver registers with the GLD and creates minor node in + * the file system tree for this device. + */ +static int +bnx_attach_attach(um_device_t *umdevice) +{ + int rc; + int instance; + unsigned int val; + int chip_id; + int device_id; + int subdevice_id; + off_t regSize; + + dev_info_t *dip; + + dip = umdevice->os_param.dip; + + umdevice->os_param.active_resc_flag = 0; + + rc = pci_config_setup(umdevice->os_param.dip, + &umdevice->os_param.pci_cfg_handle); + if (rc != DDI_SUCCESS) { + cmn_err(CE_WARN, + "%s: Failed to setup PCI configuration space accesses.\n", + umdevice->dev_name); + goto error; + } + + umdevice->os_param.active_resc_flag |= DRV_RESOURCE_PCICFG_MAPPED; + + rc = ddi_dev_regsize(dip, 1, ®Size); + if (rc != DDI_SUCCESS) { + cmn_err(CE_WARN, "%s: failed to determine register set size.", + umdevice->dev_name); + } + + /* + * Setup device memory mapping so that LM driver can start accessing it. + */ + rc = ddi_regs_map_setup(dip, + 1, /* BAR */ + &umdevice->os_param.regs_addr, + 0, /* OFFSET */ + regSize, + &bnxAccessAttribBAR, + &umdevice->os_param.reg_acc_handle); + if (rc != DDI_SUCCESS) { + cmn_err(CE_WARN, + "%s: Failed to memory map device.\n", + umdevice->dev_name); + goto error; + } + + umdevice->os_param.active_resc_flag |= DRV_RESOURCE_MAP_REGS; + + bnx_cfg_msix(umdevice); + + if (bnxIntrInit(umdevice) != 0) { + goto error; + } + + umdevice->os_param.active_resc_flag |= DRV_RESOURCE_INTR_1; + + mutex_init(&umdevice->os_param.rcv_mutex, NULL, + MUTEX_DRIVER, DDI_INTR_PRI(umdevice->intrPriority)); + mutex_init(&umdevice->os_param.phy_mutex, NULL, + MUTEX_DRIVER, DDI_INTR_PRI(umdevice->intrPriority)); + mutex_init(&umdevice->os_param.ind_mutex, NULL, + MUTEX_DRIVER, DDI_INTR_PRI(umdevice->intrPriority)); + + umdevice->os_param.active_resc_flag |= DRV_RESOURCE_MUTEX; + + /* + * Call lower module's initialization routines to initialize + * hardware and related components within BNX. + */ + if (bnx_hdwr_init(umdevice)) { + goto error; + } + + umdevice->os_param.active_resc_flag |= DRV_RESOURCE_HDWR_REGISTER; + + if (!bnx_kstat_init(umdevice)) { + goto error; + } + + umdevice->os_param.active_resc_flag |= DRV_RESOURCE_KSTAT; + + if (bnx_gld_init(umdevice)) { + goto error; + } + + umdevice->os_param.active_resc_flag |= DRV_RESOURCE_GLD_REGISTER; + + bnx_timer_init(umdevice); + + umdevice->os_param.active_resc_flag |= DRV_RESOURCE_TIMER; + + instance = ddi_get_instance(umdevice->os_param.dip); + + /* Create a minor node entry in /devices . */ +#ifdef _USE_FRIENDLY_NAME + rc = ddi_create_minor_node(dip, (char *)ddi_driver_name(dip), + S_IFCHR, instance, DDI_PSEUDO, 0); +#else + rc = ddi_create_minor_node(dip, ddi_get_name(dip), + S_IFCHR, instance, DDI_PSEUDO, 0); +#endif + if (rc == DDI_FAILURE) { + cmn_err(CE_WARN, "%s: Failed to create device minor node.\n", + umdevice->dev_name); + goto error; + } + + umdevice->os_param.active_resc_flag |= DRV_RESOURCE_MINOR_NODE; + + ddi_report_dev(dip); + + device_id = pci_config_get16(umdevice->os_param.pci_cfg_handle, + 0x2); + subdevice_id = pci_config_get16(umdevice->os_param.pci_cfg_handle, + 0x2e); + + /* Dip into PCI config space to determine if we have 5716's */ + if ((device_id == 0x163b) && (subdevice_id == 0x163b)) { + chip_id = 0x5716; + } else { + chip_id = CHIP_NUM(&umdevice->lm_dev) >> 16; + } + + (void) snprintf(umdevice->version, sizeof (umdevice->version), "%s", + BRCMVERSION); + + /* Get firmware version. */ + REG_RD_IND(&umdevice->lm_dev, + umdevice->lm_dev.hw_info.shmem_base + + OFFSETOF(shmem_region_t, dev_info.bc_rev), &val); + umdevice->dev_var.fw_ver = (val & 0xFFFF0000) | ((val & 0xFF00) >> 8); + + (void) snprintf(umdevice->versionFW, sizeof (umdevice->versionFW), + "0x%x", umdevice->dev_var.fw_ver); + + (void) snprintf(umdevice->chipName, sizeof (umdevice->chipName), + "BCM%x", chip_id); + + (void) snprintf(umdevice->intrAlloc, sizeof (umdevice->intrAlloc), + "1 %s", (umdevice->intrType == DDI_INTR_TYPE_MSIX) ? "MSIX" : + (umdevice->intrType == DDI_INTR_TYPE_MSI) ? "MSI" : + "Fixed"); + + cmn_err(CE_NOTE, + "!%s: (%s) BCM%x device with F/W Ver%x is initialized (%s)", + umdevice->dev_name, umdevice->version, + chip_id, umdevice->dev_var.fw_ver, + umdevice->intrAlloc); + + return (0); + +error: + (void) bnx_free_system_resources(umdevice); + + return (-1); +} + +/* + * Name: bnx_attach + * + * Input: ptr to dev_info_t, command code for the task to be executed + * + * Return: DDI_SUCCESS or DDI_FAILURE. + * + * Description: OS determined module attach entry point. + */ +static int +bnx_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) +{ + um_device_t *umdevice; + int ret_val = DDI_SUCCESS; + + switch (cmd) { + case DDI_ATTACH: + umdevice = kmem_zalloc(sizeof (um_device_t), + KM_NOSLEEP); + if (umdevice == NULL) { + cmn_err(CE_WARN, "%s: Failed to allocate " + "device memory.\n", __func__); + ret_val = DDI_FAILURE; + break; + } + + /* Save dev_info_t info in the driver struture. */ + umdevice->os_param.dip = dip; + + /* + * Obtain a human-readable name to prepend all our + * messages with. + */ + umdevice->instance = ddi_get_instance(dip); + (void) snprintf(umdevice->dev_name, + sizeof (umdevice->dev_name), "%s%d", "bnx", + umdevice->instance); + + /* + * Set driver private pointer to per device structure + * ptr. + */ + ddi_set_driver_private(dip, (caddr_t)umdevice); + + umdevice->magic = BNX_MAGIC; + + if (bnx_attach_attach(umdevice)) { + ddi_set_driver_private(dip, (caddr_t)NULL); + kmem_free(umdevice, sizeof (um_device_t)); + ret_val = DDI_FAILURE; + } + break; + + case DDI_RESUME: + /* Retrieve our device structure. */ + umdevice = ddi_get_driver_private(dip); + if (umdevice == NULL) { + ret_val = DDI_FAILURE; + break; + } + break; + + default: + ret_val = DDI_FAILURE; + break; + } + + return (ret_val); +} + +/* + * Name: bnx_detach + * + * Input: ptr to dev_info_t, command code for the task to be executed + * + * Return: DDI_SUCCESS or DDI_FAILURE. + * + * Description: OS determined module detach entry point. + */ +static int +bnx_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) +{ + um_device_t *umdevice; + int ret_val = DDI_SUCCESS; + + switch (cmd) { + case DDI_DETACH: + umdevice = ddi_get_driver_private(dip); + if (umdevice == NULL) { + /* Must have failed attach. */ + ret_val = DDI_SUCCESS; + break; + } + + /* Sanity check. */ + if (umdevice == NULL) { + cmn_err(CE_WARN, + "%s: Sanity check failed(1).", __func__); + ret_val = DDI_SUCCESS; + break; + } + + /* Sanity check. */ + if (umdevice->os_param.dip != dip) { + cmn_err(CE_WARN, + "%s: Sanity check failed(2).", __func__); + ret_val = DDI_SUCCESS; + break; + } + + /* Another sanity check. */ + if (umdevice->intr_enabled != B_FALSE) { + cmn_err(CE_WARN, "%s: Detaching a device " + "that is currently running!!!\n", + umdevice->dev_name); + ret_val = DDI_FAILURE; + break; + } + + if (bnx_free_system_resources(umdevice)) { + ret_val = DDI_FAILURE; + break; + } + + ddi_set_driver_private(dip, (caddr_t)NULL); + kmem_free(umdevice, sizeof (um_device_t)); + break; + + case DDI_SUSPEND: + /* Retrieve our device structure. */ + umdevice = ddi_get_driver_private(dip); + if (umdevice == NULL) { + ret_val = DDI_FAILURE; + break; + } + break; + + default: + ret_val = DDI_FAILURE; + break; + } + + return (ret_val); +} + +/* + * Name: bnx_quiesce + * + * Input: ptr to dev_info_t + * + * Return: DDI_SUCCESS or DDI_FAILURE. + * + * Description: quiesce(9E) entry point. + * This function will make sure no more interrupts and DMA of + * the hardware. It is called when the system is single-threaded + * at high PIL with preemption disabled. Thus this function should + * not be blocked. + */ +static int +bnx_quiesce(dev_info_t *dip) +{ + um_device_t *umdevice; + + umdevice = ddi_get_driver_private(dip); + + /* Sanity check. */ + if (umdevice == NULL || umdevice->os_param.dip != dip) { + cmn_err(CE_WARN, "%s: Sanity check failed.", __func__); + return (DDI_FAILURE); + } + + /* Stop the device from generating any interrupts. */ + lm_disable_int(&(umdevice->lm_dev)); + + /* Set RX mask to stop receiving any further packets */ + (void) lm_set_rx_mask(&(umdevice->lm_dev), RX_FILTER_USER_IDX0, + LM_RX_MASK_ACCEPT_NONE); + + return (DDI_SUCCESS); +} + +DDI_DEFINE_STREAM_OPS(bnx_dev_ops, nulldev, nulldev, bnx_attach, bnx_detach, \ + nodev, NULL, (D_MP | D_64BIT), NULL, bnx_quiesce); + +static struct modldrv bnx_modldrv = { + &mod_driverops, /* drv_modops */ + BNX_PRODUCT_INFO, /* drv_linkinfo */ + &bnx_dev_ops /* drv_dev_ops */ +}; + +static struct modlinkage bnx_modlinkage = { + MODREV_1, /* ml_rev */ + &bnx_modldrv, /* ml_linkage */ + NULL /* NULL termination */ +}; + +/* + * Name: _init + * + * Input: None + * + * Return: SUCCESS or FAILURE. + * + * Description: OS determined driver module load entry point. + */ +int +_init(void) +{ + int rc; + + mac_init_ops(&bnx_dev_ops, "bnx"); + + /* Install module information with O/S */ + rc = mod_install(&bnx_modlinkage); + if (rc != 0) { + cmn_err(CE_WARN, "%s:_init - mod_install returned 0x%x", "bnx", + rc); + return (rc); + } + + cmn_err(CE_NOTE, "!%s", BNX_PRODUCT_BANNER); + + return (rc); +} + + + +/* + * Name: _fini + * + * Input: None + * + * Return: SUCCESS or FAILURE. + * + * Description: OS determined driver module unload entry point. + */ +int +_fini(void) +{ + int rc; + + rc = mod_remove(&bnx_modlinkage); + + if (rc == 0) { + mac_fini_ops(&bnx_dev_ops); + } + + return (rc); +} + +/* + * Name: _info + * + * Input: None + * + * Return: SUCCESS or FAILURE. + * + * Description: OS determined module info entry point. + */ +int +_info(struct modinfo *modinfop) +{ + int rc; + + rc = mod_info(&bnx_modlinkage, modinfop); + + return (rc); +} diff --git a/usr/src/uts/common/io/bnx/bnxrcv.c b/usr/src/uts/common/io/bnx/bnxrcv.c new file mode 100644 index 0000000000..41268bb8ab --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxrcv.c @@ -0,0 +1,646 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2019, Joyent, Inc. + */ + +#include "bnxrcv.h" + + +#define BNX_RECV_INIT_FAIL_THRESH 1 + +#ifndef NUM_RX_CHAIN +#error NUM_RX_CHAIN is not defined. +#else +/* + * Range check NUM_RX_CHAIN. Technically the LM controls this definition, + * but it makes sense to use what the LM uses. + */ +#if NUM_RX_CHAIN < 0 +#error Invalid NUM_RX_CHAIN definition. +#elif NUM_RX_CHAIN > 1 +#warning NUM_RX_CHAIN is greater than 1. +#endif +#endif + + +static ddi_dma_attr_t bnx_rx_jmb_dma_attrib = { + DMA_ATTR_V0, /* dma_attr_version */ + 0, /* dma_attr_addr_lo */ + 0xffffffffffffffff, /* dma_attr_addr_hi */ + 0x0ffffff, /* dma_attr_count_max */ + BNX_DMA_ALIGNMENT, /* dma_attr_align */ + 0xffffffff, /* dma_attr_burstsizes */ + 1, /* dma_attr_minxfer */ + 0x00ffffff, /* dma_attr_maxxfer */ + 0xffffffff, /* dma_attr_seg */ + BNX_RECV_MAX_FRAGS, /* dma_attr_sgllen */ + BNX_MIN_BYTES_PER_FRAGMENT, /* dma_attr_granular */ + 0, /* dma_attr_flags */ +}; + +static int +bnx_rxbuffer_alloc(um_device_t *const umdevice, um_rxpacket_t *const umpacket) +{ + int rc; + size_t pktsize; + size_t reallen; + uint_t dc_count; + lm_packet_t *lmpacket; + ddi_dma_cookie_t cookie; + + lmpacket = &(umpacket->lmpacket); + + rc = ddi_dma_alloc_handle(umdevice->os_param.dip, + &bnx_rx_jmb_dma_attrib, DDI_DMA_DONTWAIT, + (void *)0, &(umpacket->dma_handle)); + if (rc != DDI_SUCCESS) { + return (-1); + } + + /* + * The buffer size as set by the lower module is the actual buffer + * size plus room for a small, 16 byte inline rx buffer descriptor + * header plus an implied two byte TCP shift optimization. We + * don't need to adjust the size at all. + */ + pktsize = lmpacket->u1.rx.buf_size; + + rc = ddi_dma_mem_alloc(umpacket->dma_handle, pktsize, + &bnxAccessAttribBUF, DDI_DMA_STREAMING, DDI_DMA_DONTWAIT, + (void *)0, (caddr_t *)&lmpacket->u1.rx.mem_virt, &reallen, + &umpacket->dma_acc_handle); + if (rc != DDI_SUCCESS) { + goto error1; + } + + /* Bind the message block buffer address to the handle. */ + rc = ddi_dma_addr_bind_handle(umpacket->dma_handle, NULL, + (caddr_t)lmpacket->u1.rx.mem_virt, pktsize, + DDI_DMA_READ | DDI_DMA_STREAMING, DDI_DMA_DONTWAIT, NULL, + &cookie, &dc_count); + if (rc != DDI_DMA_MAPPED) { + goto error2; + } + + lmpacket->u1.rx.mem_phy.as_u64 = cookie.dmac_laddress; + + return (0); + +error2: + ddi_dma_mem_free(&(umpacket->dma_acc_handle)); + +error1: + ddi_dma_free_handle(&(umpacket->dma_handle)); + + return (-1); +} + +static void +bnx_rxbuffer_free(um_device_t * const umdevice, um_rxpacket_t * const umpacket) +{ + lm_packet_t *lmpacket; + + lmpacket = &(umpacket->lmpacket); + + lmpacket->u1.rx.mem_phy.as_u64 = 0; + lmpacket->u1.rx.buf_size = 0; + + (void) ddi_dma_unbind_handle(umpacket->dma_handle); + + lmpacket->u1.rx.mem_virt = NULL; + ddi_dma_mem_free(&umpacket->dma_acc_handle); + + ddi_dma_free_handle(&(umpacket->dma_handle)); +} + +static void +bnx_recv_ring_init(um_device_t * const umdevice, const unsigned int ringidx) +{ + s_list_t *srcq; + s_list_t *dstq; + lm_rx_chain_t *lmrxring; + um_recv_qinfo *recvinfo; + um_rxpacket_t *umpacket; + + recvinfo = &_RX_QINFO(umdevice, ringidx); + + recvinfo->processing = B_FALSE; + + lmrxring = &umdevice->lm_dev.rx_info.chain[ringidx]; + + srcq = &(lmrxring->free_descq); + + dstq = &(recvinfo->buffq); + + s_list_init(dstq, NULL, NULL, 0); + + /* CONSTANTCONDITION */ + /* + * Put all available packet descriptors in our special wait queue. + * The wait queue is an area to store packet descriptors that do + * not yet have buffers associated with them. + */ + while (1) { + umpacket = (um_rxpacket_t *)s_list_pop_head(srcq); + if (umpacket == NULL) { + break; + } + + s_list_push_tail(dstq, &(umpacket->lmpacket.link)); + } + + dstq = &(recvinfo->waitq); + + s_list_init(dstq, NULL, NULL, 0); +} + +static void +bnx_recv_ring_fill(um_device_t * const umdevice, const unsigned int ringidx) +{ + s_list_t *srcq; + s_list_t *dstq; + um_rxpacket_t *umpacket; + um_recv_qinfo *recvinfo; + + recvinfo = &(_RX_QINFO(umdevice, ringidx)); + + srcq = &(recvinfo->buffq); + + dstq = &(umdevice->lm_dev.rx_info.chain[ringidx].free_descq); + + /* CONSTANTCONDITION */ + /* Populate as many of the packet descriptors as we can. */ + while (1) { + umpacket = (um_rxpacket_t *)s_list_pop_head(srcq); + if (umpacket == NULL) { + break; + } + + if (bnx_rxbuffer_alloc(umdevice, umpacket) != 0) { + s_list_push_head(srcq, &umpacket->lmpacket.link); + break; + } + + s_list_push_tail(dstq, &umpacket->lmpacket.link); + } +} + +/* + * NOTE!!! This function assumes the rcv_mutex is already held. + */ +static void +bnx_recv_ring_recv(um_device_t *const umdevice, const unsigned int ringidx) +{ + mblk_t *head = NULL; + mblk_t *tail = NULL; + s_list_t *srcq; + s_list_t *recvq; + s_list_t *freeq; + boolean_t dcopy; + boolean_t lm_rcvq_empty; + lm_packet_t *lmpacket; + um_rxpacket_t *umpacket; + um_recv_qinfo *recvinfo; + + recvinfo = &(_RX_QINFO(umdevice, ringidx)); + + /* + * We can't hold the receive mutex across the receive function or + * deadlock results. So that other threads know we are still doing + * business, toggle a flag they can look at. If the flag says, + * we're processing, other threads should back off. + */ + recvinfo->processing = B_TRUE; + + srcq = &(recvinfo->waitq); + freeq = &(umdevice->lm_dev.rx_info.chain[ringidx].free_descq); + + recvq = &(umdevice->lm_dev.rx_info.chain[ringidx].active_descq); + if (s_list_entry_cnt(recvq)) { + lm_rcvq_empty = B_FALSE; + } else { + lm_rcvq_empty = B_TRUE; + } + + /* CONSTANTCONDITION */ + /* Send the rx packets up. */ + while (1) { + mblk_t *mp = NULL; + unsigned int pktlen; + int ofld_flags; + + umpacket = (um_rxpacket_t *)s_list_pop_head(srcq); + if (umpacket == NULL) { + break; + } + + lmpacket = &(umpacket->lmpacket); + + if (lmpacket->status != LM_STATUS_SUCCESS) { + s_list_push_tail(freeq, &(lmpacket->link)); + continue; + } + + pktlen = lmpacket->size; + + /* + * FIXME -- Implement mm_flush_cache(). + * + * The LM uses mm_flush_cache() to make sure the processor is + * working with current data. The call to ddi_dma_sync should + * go there instead. How mm_flush_cache() should be + * implemented depends on what test mode we are in. + * + * if (lmdevice->params.test_mode & TEST_MODE_VERIFY_RX_CRC) { + * // The LM will need access to the complete rx buffer. + * } else { + * // The LM only needs access to the 16 byte inline rx BD. + * // Be sure in this case to ddi_dma_sync() as many + * // fragments as necessary to get the full rx BD in + * // host memory. + * } + */ + (void) ddi_dma_sync(umpacket->dma_handle, 0, + pktlen + L2RX_FRAME_HDR_LEN, DDI_DMA_SYNC_FORKERNEL); + + dcopy = B_FALSE; + + if (pktlen < umdevice->rx_copy_threshold) { + lm_device_t *lmdevice; + lmdevice = &(umdevice->lm_dev); + + if ((lmdevice->params.keep_vlan_tag == 0) && + (lmpacket->u1.rx.flags & + LM_RX_FLAG_VALID_VLAN_TAG)) { + + /* + * The hardware stripped the VLAN tag + * we must now reinsert the tag. This is + * done to be compatiable with older firmware + * who could not handle VLAN tags + */ + mp = allocb(pktlen + 6, BPRI_MED); + if (mp != NULL) { + uint8_t *dataptr; + const uint16_t tpid = htons(0x8100); + uint16_t vlan_tag; + + vlan_tag = + htons(lmpacket->u1.rx.vlan_tag); + + /* + * For analysis of the packet contents, + * we first need to advance + * the pointer beyond the inlined return + * buffer descriptor. + */ + dataptr = lmpacket->u1.rx.mem_virt + + L2RX_FRAME_HDR_LEN; + + /* TCP alignment optimization. */ + mp->b_rptr += 2; + + /* + * First copy the dest/source MAC + * addresses + */ + bcopy(dataptr, mp->b_rptr, 12); + + /* Second copy the VLAN tag */ + bcopy(&tpid, mp->b_rptr + 12, 2); + bcopy(&vlan_tag, mp->b_rptr + 14, 2); + + /* Third copy the reset of the packet */ + dataptr = dataptr + 12; + + bcopy(dataptr, mp->b_rptr + 16, + pktlen - 12); + mp->b_wptr = mp->b_rptr + pktlen + 4; + + dcopy = B_TRUE; + + goto sendup; + } + } else { + /* The hardware didn't strip the VLAN tag */ + mp = allocb(pktlen + 2, BPRI_MED); + if (mp != NULL) { + uint8_t *dataptr; + + /* + * For analysis of the packet contents, + * we first need to advance + * the pointer beyond the inlined return + * buffer descriptor. + */ + dataptr = lmpacket->u1.rx.mem_virt + + L2RX_FRAME_HDR_LEN; + + /* TCP alignment optimization. */ + mp->b_rptr += 2; + + bcopy(dataptr, mp->b_rptr, pktlen); + mp->b_wptr = mp->b_rptr + pktlen; + + dcopy = B_TRUE; + + goto sendup; + } + } + + umdevice->recv_discards++; + + s_list_push_tail(freeq, &(lmpacket->link)); + + continue; + } + + if (lm_rcvq_empty == B_TRUE && !(s_list_entry_cnt(srcq))) { + /* + * If the hardware is out of receive buffers and we are + * on the last receive packet, we need to drop the + * packet. We do this because we might not be able to + * allocate _any_ new receive buffers before the ISR + * completes. If this happens, the driver will enter + * an infinite interrupt loop where the hardware is + * requesting rx buffers the driver cannot allocate. + * So that the system doesn't livelock, we leave one + * buffer perpetually available. Note that we do this + * _after_ giving the double copy code a chance to + * claim the packet. + */ + + /* + * FIXME -- Make sure to add one more to the rx packet + * descriptor count before allocating them. + */ + + umdevice->recv_discards++; + + s_list_push_tail(freeq, &(lmpacket->link)); + + continue; + } + +sendup: + + /* + * Check if the checksum was offloaded. + * If so, pass the result to stack. + */ + ofld_flags = 0; + if ((umdevice->dev_var.enabled_oflds & + LM_OFFLOAD_RX_IP_CKSUM) && + (lmpacket->u1.rx.flags & LM_RX_FLAG_IP_CKSUM_IS_GOOD)) { + ofld_flags |= HCK_IPV4_HDRCKSUM_OK; + } + + if (((umdevice->dev_var.enabled_oflds & + LM_OFFLOAD_RX_TCP_CKSUM) && + (lmpacket->u1.rx.flags & LM_RX_FLAG_TCP_CKSUM_IS_GOOD)) || + ((umdevice->dev_var.enabled_oflds & + LM_OFFLOAD_RX_UDP_CKSUM) && + (lmpacket->u1.rx.flags & LM_RX_FLAG_UDP_CKSUM_IS_GOOD))) { + ofld_flags |= HCK_FULLCKSUM_OK; + } + + if (ofld_flags != 0) { + mac_hcksum_set(mp, 0, 0, 0, 0, ofld_flags); + } + + /* + * Push the packet descriptor onto one of the queues before we + * attempt to send the packet up. If the send-up function + * hangs during driver unload, we want all our packet + * descriptors to be available for deallocation. + */ + if (dcopy == B_TRUE) { + s_list_push_tail(freeq, &(lmpacket->link)); + } + + if (head == NULL) { + head = mp; + tail = mp; + } else { + tail->b_next = mp; + tail = mp; + } + tail->b_next = NULL; + } + + if (head) { + mutex_exit(&umdevice->os_param.rcv_mutex); + + mac_rx(umdevice->os_param.macp, + umdevice->os_param.rx_resc_handle[ringidx], head); + + mutex_enter(&umdevice->os_param.rcv_mutex); + } + + recvinfo->processing = B_FALSE; +} + +static void +bnx_recv_ring_dump(um_device_t *const umdevice, const unsigned int ringidx) +{ + s_list_t *srcq; + s_list_t *dstq; + um_rxpacket_t *umpacket; + + srcq = &(_RX_QINFO(umdevice, ringidx).waitq); + dstq = &(umdevice->lm_dev.rx_info.chain[ringidx].free_descq); + + /* CONSTANTCONDITION */ + /* Dump all the packets pending a send-up. */ + while (1) { + umpacket = (um_rxpacket_t *)s_list_pop_head(srcq); + if (umpacket == NULL) { + break; + } + + s_list_push_tail(dstq, &(umpacket->lmpacket.link)); + } +} + +static void +bnx_recv_ring_free(um_device_t *const umdevice, const unsigned int ringidx) +{ + s_list_t *srcq; + s_list_t *dstq; + um_rxpacket_t *umpacket; + + srcq = &(umdevice->lm_dev.rx_info.chain[ringidx].free_descq); + + dstq = &(_RX_QINFO(umdevice, ringidx).buffq); + + /* CONSTANTCONDITION */ + /* + * Back out all the packets submitted to the "available for hardware + * use" queue. Free the buffers associated with the descriptors as + * we go. + */ + while (1) { + umpacket = (um_rxpacket_t *)s_list_pop_head(srcq); + if (umpacket == NULL) { + break; + } + + bnx_rxbuffer_free(umdevice, umpacket); + + s_list_push_tail(dstq, &umpacket->lmpacket.link); + } +} + +static void +bnx_recv_ring_fini(um_device_t *const umdevice, const unsigned int ringidx) +{ + s_list_t *srcq; + um_rxpacket_t *umpacket; + um_recv_qinfo *recvinfo; + + recvinfo = &(_RX_QINFO(umdevice, ringidx)); + + srcq = &(recvinfo->buffq); + + /* CONSTANTCONDITION */ + while (1) { + umpacket = (um_rxpacket_t *)s_list_pop_head(srcq); + if (umpacket == NULL) { + break; + } + + /* + * Intentionally throw the packet away. The memory was + * allocated by the lower module and will be reclaimed when + * we do our final memory cleanup. + */ + } +} + +int +bnx_rxpkts_init(um_device_t *const umdevice) +{ + int i; + int alloccnt; + lm_device_t *lmdevice; + + lmdevice = &(umdevice->lm_dev); + + alloccnt = 0; + + for (i = RX_CHAIN_IDX0; i < NUM_RX_CHAIN; i++) { + int post_count = 0; + + bnx_recv_ring_init(umdevice, i); + + bnx_recv_ring_fill(umdevice, i); + + post_count = + s_list_entry_cnt(&lmdevice->rx_info.chain[i].free_descq); + + if (post_count != lmdevice->params.l2_rx_desc_cnt[i]) { + cmn_err(CE_NOTE, + "!%s: %d rx buffers requested. %d allocated.\n", + umdevice->dev_name, + umdevice->lm_dev.params.l2_rx_desc_cnt[i], + post_count); + } + + alloccnt += post_count; + } + + /* FIXME -- Set rxbuffer allocation failure threshold. */ + if (alloccnt < BNX_RECV_INIT_FAIL_THRESH) { + cmn_err(CE_WARN, + "%s: Failed to allocate minimum number of RX buffers.\n", + umdevice->dev_name); + +/* BEGIN CSTYLED */ +#if BNX_RECV_INIT_FAIL_THRESH > 1 +#warning Need to implement code to free previously allocated rx buffers in bnx_rxpkts_init error path. +#endif +/* END CSTYLED */ + + return (-1); + } + + return (0); +} + +void +bnx_rxpkts_intr(um_device_t *const umdevice) +{ + int i; + um_recv_qinfo * recvinfo; + + for (i = RX_CHAIN_IDX0; i < NUM_RX_CHAIN; i++) { + recvinfo = &(_RX_QINFO(umdevice, i)); + + if (recvinfo->processing == B_FALSE) { + /* Send the packets up the stack. */ + bnx_recv_ring_recv(umdevice, i); + } + } +} + +void +bnx_rxpkts_post(um_device_t *const umdevice) +{ + int i; + um_recv_qinfo *recvinfo; + + for (i = RX_CHAIN_IDX0; i < NUM_RX_CHAIN; i++) { + recvinfo = &(_RX_QINFO(umdevice, i)); + + if (recvinfo->processing == B_FALSE) { + /* Allocate new rx buffers. */ + bnx_recv_ring_fill(umdevice, i); + + /* Submit the rx buffers to the hardware. */ + (void) lm_post_buffers(&(umdevice->lm_dev), i, NULL); + } + } +} + +void +bnx_rxpkts_recycle(um_device_t *const umdevice) +{ + int i; + + for (i = NUM_RX_CHAIN - 1; i >= RX_CHAIN_IDX0; i--) { + bnx_recv_ring_dump(umdevice, i); + + lm_abort(&(umdevice->lm_dev), ABORT_OP_RX_CHAIN, i); + } +} + +void +bnx_rxpkts_fini(um_device_t *const umdevice) +{ + int i; + + for (i = NUM_RX_CHAIN - 1; i >= RX_CHAIN_IDX0; i--) { + /* Dump shouldn't be necessary, but just to be safe... */ + bnx_recv_ring_dump(umdevice, i); + + /* Recycle shouldn't be necessary, but just to be safe... */ + lm_abort(&(umdevice->lm_dev), ABORT_OP_RX_CHAIN, i); + + bnx_recv_ring_free(umdevice, i); + bnx_recv_ring_fini(umdevice, i); + } +} diff --git a/usr/src/uts/common/io/bnx/bnxrcv.h b/usr/src/uts/common/io/bnx/bnxrcv.h new file mode 100644 index 0000000000..322c1c8e49 --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxrcv.h @@ -0,0 +1,38 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + */ + +#ifndef _BNXRCV_H +#define _BNXRCV_H + +#include "bnx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int bnx_rxpkts_init(um_device_t *const); +void bnx_rxpkts_intr(um_device_t *const); +void bnx_rxpkts_post(um_device_t *const); +void bnx_rxpkts_recycle(um_device_t *const); +void bnx_rxpkts_fini(um_device_t *const); + +#ifdef __cplusplus +} +#endif + +#endif /* _BNXRCV_H */ diff --git a/usr/src/uts/common/io/bnx/bnxsnd.c b/usr/src/uts/common/io/bnx/bnxsnd.c new file mode 100644 index 0000000000..16f1b03c10 --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxsnd.c @@ -0,0 +1,835 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2019, Joyent, Inc. + */ + +#include "bnxsnd.h" + + +/* Low water marks for transmit credits. */ +#define BNX_DCOPY_ALIGN 32 +#define BNX_XMIT_INIT_FAIL_THRESH 1 +#define BNX_PDWM_THRESHOLD 8 + + +#ifndef NUM_TX_CHAIN +#error NUM_TX_CHAIN is not defined. +#else +/* + * Range check NUM_TX_CHAIN. Technically the LM controls this definition, + * but it makes sense to use what the LM uses. + */ +#if NUM_TX_CHAIN < 0 +#error Invalid NUM_TX_CHAIN definition. +#elif NUM_TX_CHAIN > 1 +#warning NUM_TX_CHAIN is greater than 1. +#endif +#endif + + +static ddi_dma_attr_t bnx_snd_dma_attrib = { + DMA_ATTR_V0, /* dma_attr_version */ + 0, /* dma_attr_addr_lo */ + 0xffffffffffffffff, /* dma_attr_addr_hi */ + 0x0ffffff, /* dma_attr_count_max */ + BNX_DMA_ALIGNMENT, /* dma_attr_align */ + 0xffffffff, /* dma_attr_burstsizes */ + 1, /* dma_attr_minxfer */ + 0x00ffffff, /* dma_attr_maxxfer */ + 0xffffffff, /* dma_attr_seg */ + BNX_MAX_SGL_ENTRIES, /* dma_attr_sgllen */ + BNX_MIN_BYTES_PER_FRAGMENT, /* dma_attr_granular */ + 0, /* dma_attr_flags */ +}; + +/* + * Description: This function will map the fragments of the message block + * + * Return: DDI_DMA_MAPPED: Success + * DDI_DMA_INUSE: Another I/O transaction is using the DMA handle + * DDI_DMA_NORESOURCES: No resources are available at the present time + * DDI_DMA_NOMAPPING: The object cannot be reached by the device + * requesting the resources. + * DDI_DMA_TOOBIG: The object is too big. A request of this size can + * never be satisfied on this particular system. + * The maximum size varies depending on machine + * and configuration. + */ +static int +bnx_xmit_frag_map(mblk_t *mp, ddi_dma_handle_t *handle, + lm_frag_list_t *fraglist) +{ + int i; + uint_t ccount; + ddi_dma_cookie_t cookie; + lm_frag_t *fragment; + + if (fraglist->cnt >= BNX_MAX_SGL_ENTRIES) { + return (DDI_DMA_NOMAPPING); + } + + i = ddi_dma_addr_bind_handle(*handle, NULL, + (caddr_t)mp->b_rptr, mp->b_wptr - mp->b_rptr, + DDI_DMA_WRITE | DDI_DMA_STREAMING, DDI_DMA_DONTWAIT, NULL, + &cookie, &ccount); + if (i != DDI_DMA_MAPPED) { + return (i); + } + + /* + * It looks strange at first, but the below check is needed. + * ddi_dma_addr_bind_handle() correctly returns an error if + * the physical fragment count exceeds the maximum fragment + * count specified in the ddi_dma_attrib structure for the + * current mp. However, a packet can span multiple mp's. + * The purpose of the check below is to make sure we do not + * overflow the global fragment count limit. + */ + if (fraglist->cnt + ccount > BNX_MAX_SGL_ENTRIES) { + /* We hit our fragment count limit. */ + (void) ddi_dma_unbind_handle(*handle); + + return (DDI_DMA_NOMAPPING); + } + + fragment = &(fraglist->frag_arr[fraglist->cnt]); + fraglist->cnt += ccount; + + for (i = 0; i < ccount-1; i++) { + fragment->addr.as_u64 = cookie.dmac_laddress; + fragment->size = cookie.dmac_size; + + fragment++; + + ddi_dma_nextcookie(*handle, &cookie); + } + + fragment->addr.as_u64 = cookie.dmac_laddress; + fragment->size = cookie.dmac_size; + + return (0); +} + +static void +bnx_xmit_pkt_unmap(um_txpacket_t * const umpacket) +{ + int i; + + for (i = 0; i < umpacket->num_handles; i++) { + (void) ddi_dma_unbind_handle(umpacket->dma_handle[i]); + } + + umpacket->num_handles = 0; +} + +int +bnx_xmit_pkt_map(um_txpacket_t * const umpacket, mblk_t * mp) +{ + int rc; + u32_t num_dma_handle; + + num_dma_handle = umpacket->num_handles; + + if (num_dma_handle == BNX_MAX_SGL_ENTRIES) { + return (BNX_TX_RESOURCES_TOO_MANY_FRAGS); + } + + rc = bnx_xmit_frag_map(mp, &umpacket->dma_handle[num_dma_handle++], + &(umpacket->frag_list)); + if (rc) { + return (BNX_TX_RESOURCES_NO_OS_DMA_RES); + } + + umpacket->num_handles = num_dma_handle; + + return (0); +} + +static void +bnx_xmit_pkt_cpy(um_device_t * const umdevice, um_txpacket_t * const umpacket) +{ + size_t msgsize; + u32_t cpysize; + lm_frag_t *cpyfrag; + boolean_t map_enable; + mblk_t *mp; + int rc; + + map_enable = B_TRUE; + cpysize = 0; + cpyfrag = NULL; + + for (mp = umpacket->mp; mp; mp = mp->b_cont) { + msgsize = MBLKL(mp); + + if (msgsize == 0) + continue; + + if (map_enable && msgsize > umdevice->tx_copy_threshold) { + rc = bnx_xmit_pkt_map(umpacket, mp); + if (rc == 0) { + cpyfrag = NULL; + continue; + } else { + map_enable = B_FALSE; + } + } + + ASSERT(cpysize + msgsize <= umdevice->dev_var.mtu + + sizeof (struct ether_vlan_header)); + + bcopy(mp->b_rptr, (char *)umpacket->cpymem + cpysize, msgsize); + + if (cpyfrag != NULL) { + cpyfrag->size += msgsize; + } else { + cpyfrag = &umpacket->frag_list.frag_arr[ + umpacket->frag_list.cnt++]; + ASSERT(umpacket->frag_list.cnt <= BNX_MAX_SGL_ENTRIES + + 1); + cpyfrag->size = msgsize; + + cpyfrag->addr.as_u64 = umpacket->cpyphy.as_u64 + + cpysize; + } + + cpysize += msgsize; + } + + if (cpysize > 0) { + (void) ddi_dma_sync(*(umpacket->cpyhdl), umpacket->cpyoff, + cpysize, DDI_DMA_SYNC_FORDEV); + } + + if (umpacket->num_handles == 0) { + freemsg(umpacket->mp); + umpacket->mp = NULL; + } + +} + +static int +bnx_xmit_pkt_init(um_device_t * const umdevice, um_txpacket_t * const umpacket, + int num, lm_u64_t memphys) +{ + int i; + int rc; + um_xmit_qinfo * xmitinfo; + + xmitinfo = &_TX_QINFO(umdevice, 0); + + for (i = 0; i < BNX_MAX_SGL_ENTRIES; i++) { + rc = ddi_dma_alloc_handle(umdevice->os_param.dip, + &bnx_snd_dma_attrib, DDI_DMA_DONTWAIT, + (void *)0, &umpacket->dma_handle[i]); + if (rc != DDI_SUCCESS) { + cmn_err(CE_WARN, "%s:%s failed. (errno=%d)", + umdevice->dev_name, __func__, rc); + goto error; + } + } + + /* Init the relavant informations in the packet structure */ + umpacket->mp = NULL; + umpacket->num_handles = 0; + umpacket->frag_list.cnt = 0; + + umpacket->cpyhdl = &(xmitinfo->dcpyhndl); + umpacket->cpyoff = num * xmitinfo->dcpyhard; + umpacket->cpymem = xmitinfo->dcpyvirt + umpacket->cpyoff; + umpacket->cpyphy = memphys; + + return (rc); + +error: + for (i--; i >= 0; i--) { + ddi_dma_free_handle(&umpacket->dma_handle[i]); + } + + return (-1); +} + +static void +bnx_xmit_pkt_fini(um_txpacket_t * const umpacket) +{ + int i; + + for (i = BNX_MAX_SGL_ENTRIES - 1; i >= 0; i--) { + ddi_dma_free_handle(&umpacket->dma_handle[i]); + } + + umpacket->mp = NULL; + umpacket->num_handles = 0; + umpacket->frag_list.cnt = 0; + + umpacket->cpyhdl = NULL; + umpacket->cpyoff = 0; + umpacket->cpymem = NULL; +} + +static int +bnx_xmit_packet(um_device_t * const umdevice, const unsigned int ringidx, + um_txpacket_t * const umpacket) +{ + int rc; + s_list_t *waitq; + lm_tx_chain_t *txq; + lm_packet_t *lmpacket; + lm_device_t *lmdevice; + lm_frag_list_t *lmfraglist; + + lmdevice = &(umdevice->lm_dev); + lmpacket = &(umpacket->lm_pkt); + + lmfraglist = &(umpacket->frag_list); + txq = &lmdevice->tx_info.chain[ringidx]; + + /* Try to recycle, if available bd is lower than threshold */ + if (txq->bd_left < BNX_MAX_SGL_ENTRIES) { + s_list_t xmitpkts; + + s_list_init(&xmitpkts, NULL, NULL, 0); + + rc = lm_get_packets_sent(lmdevice, ringidx, 0, &xmitpkts); + + if (rc) { + bnx_xmit_ring_reclaim(umdevice, ringidx, &xmitpkts); + } + } + + waitq = &_TXQ_RESC_DESC(umdevice, ringidx); + if (s_list_is_empty(waitq) && txq->bd_left >= lmfraglist->cnt) { + (void) lm_send_packet(lmdevice, ringidx, lmpacket, lmfraglist); + + return (BNX_SEND_GOODXMIT); + } + + s_list_push_tail(waitq, &umpacket->lm_pkt.link); + + if (txq->bd_left >= BNX_MAX_SGL_ENTRIES) { + rc = bnx_xmit_ring_xmit_qpkt(umdevice, ringidx); + if (rc == BNX_SEND_GOODXMIT) { + return (BNX_SEND_GOODXMIT); + } + } + + umdevice->no_tx_credits |= BNX_TX_RESOURCES_NO_CREDIT; + + return (BNX_SEND_DEFERPKT); +} + +static int +bnx_xmit_ring_cpybuf_alloc(um_device_t * const umdevice, + um_xmit_qinfo * const xmitinfo, + unsigned int buffsize) +{ + int rc; + size_t actualsize; + unsigned int alignedsize; + unsigned int count; + ddi_dma_cookie_t cookie; + + ASSERT(buffsize > 0); + + alignedsize = buffsize; + alignedsize += (BNX_DCOPY_ALIGN - 1); + alignedsize &= ~((unsigned int)(BNX_DCOPY_ALIGN - 1)); + + /* We want double copy buffers to be completely contiguous. */ + rc = ddi_dma_alloc_handle(umdevice->os_param.dip, &bnx_std_dma_attrib, + DDI_DMA_DONTWAIT, (void *)0, &xmitinfo->dcpyhndl); + if (rc != DDI_SUCCESS) { + cmn_err(CE_WARN, + "%s: %s: Failed to alloc phys dma handle.\n", + umdevice->dev_name, __func__); + return (-1); + } + + rc = ddi_dma_mem_alloc(xmitinfo->dcpyhndl, + alignedsize * xmitinfo->desc_cnt, &bnxAccessAttribBUF, + DDI_DMA_STREAMING, DDI_DMA_DONTWAIT, (void *)0, + &xmitinfo->dcpyvirt, &actualsize, &xmitinfo->dcpyahdl); + if (rc != DDI_SUCCESS) { + cmn_err(CE_WARN, + "%s: %s: Failed to alloc phys memory.\n", + umdevice->dev_name, __func__); + goto error1; + } + + rc = ddi_dma_addr_bind_handle(xmitinfo->dcpyhndl, + (struct as *)0, xmitinfo->dcpyvirt, actualsize, + DDI_DMA_WRITE | DDI_DMA_STREAMING, DDI_DMA_DONTWAIT, (void *)0, + &cookie, &count); + if (rc != DDI_SUCCESS) { + cmn_err(CE_WARN, + "%s: %s: Failed to bind DMA address.\n", + umdevice->dev_name, __func__); + goto error2; + } + + xmitinfo->dcpyhard = alignedsize; + xmitinfo->dcpyphys.as_u64 = (u64_t)cookie.dmac_laddress; + + return (0); + +error2: + ddi_dma_mem_free(&xmitinfo->dcpyahdl); + +error1: + ddi_dma_free_handle(&xmitinfo->dcpyhndl); + + return (-1); +} + +static void +bnx_xmit_ring_cpybuf_free(um_device_t * const umdevice, + um_xmit_qinfo * const xmitinfo) +{ + (void) ddi_dma_unbind_handle(xmitinfo->dcpyhndl); + ddi_dma_mem_free(&xmitinfo->dcpyahdl); + ddi_dma_free_handle(&xmitinfo->dcpyhndl); + + xmitinfo->dcpyvirt = NULL; + xmitinfo->dcpyphys.as_u64 = 0; + xmitinfo->dcpyhard = 0; +} + +static int +bnx_xmit_ring_init(um_device_t * const umdevice, const unsigned int ringidx) +{ + int i; + size_t memsize; + void *memvirt; + s_list_t *freeq; + lm_u64_t memphys; + um_txpacket_t *umpacket; + um_xmit_qinfo *xmitinfo; + + xmitinfo = &_TX_QINFO(umdevice, ringidx); + + s_list_init(&_TXQ_FREE_DESC(umdevice, ringidx), NULL, NULL, 0); + s_list_init(&_TXQ_RESC_DESC(umdevice, ringidx), NULL, NULL, 0); + + if (xmitinfo->desc_cnt == 0) { + return (0); + } + + xmitinfo->thresh_pdwm = BNX_PDWM_THRESHOLD; + + memsize = xmitinfo->desc_cnt * sizeof (um_txpacket_t); + memvirt = kmem_zalloc(memsize, KM_NOSLEEP); + if (memvirt == NULL) { + cmn_err(CE_WARN, "%s: Failed to allocate TX packet " + "descriptor memory (%d).\n", umdevice->dev_name, ringidx); + return (-1); + } + + xmitinfo->desc_mem.addr = memvirt; + xmitinfo->desc_mem.size = memsize; + + if (bnx_xmit_ring_cpybuf_alloc(umdevice, xmitinfo, + umdevice->dev_var.mtu + sizeof (struct ether_vlan_header))) { + kmem_free(xmitinfo->desc_mem.addr, xmitinfo->desc_mem.size); + xmitinfo->desc_mem.addr = NULL; + xmitinfo->desc_mem.size = 0; + + return (-1); + } + + /* + * Driver successfully allocated memory for this transmit queue, now + * link them together and place them in the free pool. + */ + + freeq = &_TXQ_FREE_DESC(umdevice, ringidx); + umpacket = (um_txpacket_t *)memvirt; + + memphys = xmitinfo->dcpyphys; + + for (i = 0; i < xmitinfo->desc_cnt; i++) { + if (bnx_xmit_pkt_init(umdevice, umpacket, i, memphys)) { + break; + } + + LM_INC64(&memphys, xmitinfo->dcpyhard); + + s_list_push_tail(freeq, &umpacket->lm_pkt.link); + + umpacket++; + } + + mutex_init(&xmitinfo->free_mutex, NULL, MUTEX_DRIVER, + DDI_INTR_PRI(umdevice->intrPriority)); + + return (0); +} + +void +bnx_xmit_ring_reclaim(um_device_t * const umdevice, + const unsigned int ringidx, s_list_t *srcq) +{ + s_list_t *freeq; + s_list_entry_t *lmpacket; + um_txpacket_t *umpacket; + um_xmit_qinfo *xmitinfo; + + if (s_list_entry_cnt(srcq) == 0) { + return; + } + + for (lmpacket = s_list_peek_head(srcq); lmpacket; + lmpacket = s_list_next_entry(lmpacket)) { + + umpacket = (um_txpacket_t *)lmpacket; + + if (umpacket->num_handles > 0) { + bnx_xmit_pkt_unmap(umpacket); + } + + if (umpacket->mp != NULL) { + freemsg(umpacket->mp); + umpacket->mp = NULL; + } + } + + freeq = &_TXQ_FREE_DESC(umdevice, ringidx); + xmitinfo = &_TX_QINFO(umdevice, ringidx); + + mutex_enter(&xmitinfo->free_mutex); + s_list_add_tail(freeq, srcq); + mutex_exit(&xmitinfo->free_mutex); + +} + +int +bnx_xmit_ring_xmit_qpkt(um_device_t * const umdevice, + const unsigned int ringidx) +{ + s_list_t *waitq; + lm_tx_chain_t *txq; + lm_packet_t *lmpacket; + lm_device_t *lmdevice; + lm_frag_list_t *lmfraglist; + um_txpacket_t *umpacket; + int rc = 0; + + lmdevice = &(umdevice->lm_dev); + waitq = &_TXQ_RESC_DESC(umdevice, ringidx); + txq = &lmdevice->tx_info.chain[ringidx]; + + while (s_list_entry_cnt(waitq)) { + umpacket = (um_txpacket_t *)s_list_peek_head(waitq); + lmfraglist = &(umpacket->frag_list); + + if (lmfraglist->cnt > txq->bd_left) { + rc = BNX_SEND_DEFERPKT; + break; + } + + umpacket = (um_txpacket_t *)s_list_pop_head(waitq); + lmpacket = &(umpacket->lm_pkt); + + /* + * The main way that this can fail is in the check we just + * performed around the fragment list versus txq, so we ignore + * the return value. + */ + (void) lm_send_packet(lmdevice, ringidx, lmpacket, lmfraglist); + } + + return (rc); +} + +int +bnx_xmit_ring_xmit_mblk(um_device_t * const umdevice, + const unsigned int ringidx, mblk_t *mp) +{ + int rc; + uint32_t pflags; + s_list_t *txfreeq; + lm_packet_t *lmpacket; + um_txpacket_t *umpacket; + um_xmit_qinfo *xmitinfo; + + xmitinfo = &_TX_QINFO(umdevice, ringidx); + + txfreeq = &_TXQ_FREE_DESC(umdevice, ringidx); + + mutex_enter(&xmitinfo->free_mutex); + umpacket = (um_txpacket_t *)s_list_pop_head(txfreeq); + mutex_exit(&xmitinfo->free_mutex); + + /* Try to recycle, if no more packet available */ + if (umpacket == NULL) { + s_list_t xmitpkts; + lm_device_t *lmdevice; + + lmdevice = &(umdevice->lm_dev); + + s_list_init(&xmitpkts, NULL, NULL, 0); + + mutex_enter(&umdevice->os_param.xmit_mutex); + rc = lm_get_packets_sent(lmdevice, ringidx, 0, &xmitpkts); + if (rc == 0) { + umdevice->no_tx_credits |= BNX_TX_RESOURCES_NO_DESC; + + mutex_exit(&umdevice->os_param.xmit_mutex); + return (BNX_SEND_HDWRFULL); + } + mutex_exit(&umdevice->os_param.xmit_mutex); + + umpacket = (um_txpacket_t *)s_list_pop_head(&xmitpkts); + if (umpacket->num_handles > 0) { + bnx_xmit_pkt_unmap(umpacket); + } + if (umpacket->mp != NULL) { + freemsg(umpacket->mp); + umpacket->mp = NULL; + } + + /* clean up resources */ + bnx_xmit_ring_reclaim(umdevice, ringidx, &xmitpkts); + } + + umpacket->lm_pkt.link.next = NULL; + ASSERT(umpacket->mp == NULL); + ASSERT(umpacket->num_handles == 0); + umpacket->frag_list.cnt = 0; + umpacket->mp = mp; + + hcksum_retrieve(mp, NULL, NULL, NULL, NULL, NULL, NULL, &pflags); + + bnx_xmit_pkt_cpy(umdevice, umpacket); + + lmpacket = &(umpacket->lm_pkt); + + lmpacket->u1.tx.flags = 0; + lmpacket->u1.tx.lso_mss = 0; + + lmpacket->u1.tx.vlan_tag = 0; + + if (pflags & HCK_IPV4_HDRCKSUM) { + lmpacket->u1.tx.flags |= LM_TX_FLAG_COMPUTE_IP_CKSUM; + } + + if (pflags & HCK_FULLCKSUM) { + lmpacket->u1.tx.flags |= LM_TX_FLAG_COMPUTE_TCP_UDP_CKSUM; + } + + mutex_enter(&umdevice->os_param.xmit_mutex); + rc = bnx_xmit_packet(umdevice, ringidx, umpacket); + mutex_exit(&umdevice->os_param.xmit_mutex); + + return (rc); +} + +void +bnx_xmit_ring_intr(um_device_t * const umdevice, const unsigned int ringidx) +{ + u32_t rc; + s_list_t xmitpkts; + lm_device_t *lmdevice; + + lmdevice = &(umdevice->lm_dev); + + s_list_init(&xmitpkts, NULL, NULL, 0); + + mutex_enter(&umdevice->os_param.xmit_mutex); + + rc = lm_get_packets_sent(lmdevice, ringidx, 0, &xmitpkts); + + mutex_exit(&umdevice->os_param.xmit_mutex); + + if (rc) { + bnx_xmit_ring_reclaim(umdevice, ringidx, &xmitpkts); + } +} + +void +bnx_xmit_ring_post(um_device_t * const umdevice, const unsigned int ringidx) +{ + int rc; + s_list_t *freeq; + lm_device_t *lmdevice; + um_xmit_qinfo *xmitinfo; + lm_tx_chain_t *lmtxring; + + if (umdevice->no_tx_credits != 0) { + if (umdevice->no_tx_credits & BNX_TX_RESOURCES_NO_CREDIT) { + rc = bnx_xmit_ring_xmit_qpkt(umdevice, ringidx); + + if (rc == BNX_SEND_GOODXMIT) { + lmdevice = &(umdevice->lm_dev); + lmtxring = &(lmdevice->tx_info.chain[ringidx]); + + if (lmtxring->bd_left >= BNX_MAX_SGL_ENTRIES) { + umdevice->no_tx_credits &= + ~BNX_TX_RESOURCES_NO_CREDIT; + } + } + } + + if (umdevice->no_tx_credits & BNX_TX_RESOURCES_NO_DESC) { + freeq = &_TXQ_FREE_DESC(umdevice, ringidx); + xmitinfo = &_TX_QINFO(umdevice, ringidx); + + if (s_list_entry_cnt(freeq) > xmitinfo->thresh_pdwm) { + umdevice->no_tx_credits &= + ~BNX_TX_RESOURCES_NO_DESC; + } + } + + if (umdevice->no_tx_credits == 0) { + mac_tx_update(umdevice->os_param.macp); + } + } +} + +static void +bnx_xmit_ring_fini(um_device_t * const umdevice, const unsigned int ringidx) +{ + s_list_t *srcq; + um_txpacket_t *umpacket; + um_xmit_qinfo *xmitinfo; + + xmitinfo = &_TX_QINFO(umdevice, ringidx); + + mutex_destroy(&xmitinfo->free_mutex); + + srcq = &_TXQ_FREE_DESC(umdevice, ringidx); + + /* CONSTANTCONDITION */ + /* Pop all the packet descriptors off the free list and discard them. */ + while (1) { + umpacket = (um_txpacket_t *)s_list_pop_head(srcq); + if (umpacket == NULL) { + break; + } + + bnx_xmit_pkt_fini(umpacket); + } + + bnx_xmit_ring_cpybuf_free(umdevice, xmitinfo); + + kmem_free(xmitinfo->desc_mem.addr, xmitinfo->desc_mem.size); + xmitinfo->desc_mem.addr = NULL; + xmitinfo->desc_mem.size = 0; +} + +int +bnx_txpkts_init(um_device_t * const umdevice) +{ + int i; + int alloccnt; + um_xmit_qinfo *xmitinfo; + + xmitinfo = &_TX_QINFO(umdevice, 0); + + mutex_init(&umdevice->os_param.xmit_mutex, NULL, + MUTEX_DRIVER, DDI_INTR_PRI(umdevice->intrPriority)); + + alloccnt = 0; + + /* Allocate packet descriptors for the TX queue. */ + for (i = TX_CHAIN_IDX0; i < NUM_TX_CHAIN; i++) { + int desc_cnt; + + if (bnx_xmit_ring_init(umdevice, i)) { + goto error; + } + + desc_cnt = s_list_entry_cnt(&_TXQ_FREE_DESC(umdevice, i)); + + if (desc_cnt != xmitinfo->desc_cnt) { + cmn_err(CE_NOTE, + "%s: %d tx buffers requested. %d allocated.\n", + umdevice->dev_name, xmitinfo->desc_cnt, desc_cnt); + } + + alloccnt += desc_cnt; + } + + /* FIXME -- Review TX buffer allocation failure threshold. */ + if (alloccnt < BNX_XMIT_INIT_FAIL_THRESH) { + cmn_err(CE_WARN, + "%s: Failed to allocate minimum number of TX buffers.\n", + umdevice->dev_name); + + goto error; + } + + return (0); + +error: + for (i--; i >= TX_CHAIN_IDX0; i--) { + bnx_xmit_ring_fini(umdevice, i); + } + + mutex_destroy(&umdevice->os_param.xmit_mutex); + + return (-1); +} + +void +bnx_txpkts_flush(um_device_t * const umdevice) +{ + int i; + boolean_t notx_fl = B_FALSE; + + for (i = NUM_TX_CHAIN - 1; i >= TX_CHAIN_IDX0; i--) { + lm_abort(&(umdevice->lm_dev), ABORT_OP_TX_CHAIN, i); + + bnx_xmit_ring_reclaim(umdevice, i, + &_TXQ_RESC_DESC(umdevice, i)); + + s_list_init(&_TXQ_RESC_DESC(umdevice, i), NULL, NULL, 0); + + if (umdevice->no_tx_credits & BNX_TX_RESOURCES_NO_CREDIT) { + umdevice->no_tx_credits &= ~BNX_TX_RESOURCES_NO_CREDIT; + notx_fl = B_TRUE; + } + if (umdevice->no_tx_credits & BNX_TX_RESOURCES_NO_DESC) { + umdevice->no_tx_credits &= ~BNX_TX_RESOURCES_NO_DESC; + notx_fl = B_TRUE; + } + if (umdevice->no_tx_credits == 0 && notx_fl == B_TRUE) { + mac_tx_update(umdevice->os_param.macp); + } + } +} + +void +bnx_txpkts_intr(um_device_t * const umdevice) +{ + int i; + + for (i = TX_CHAIN_IDX0; i < NUM_TX_CHAIN; i++) { + bnx_xmit_ring_post(umdevice, i); + } +} + +void +bnx_txpkts_fini(um_device_t * const umdevice) +{ + int i; + + for (i = NUM_TX_CHAIN - 1; i >= TX_CHAIN_IDX0; i--) { + bnx_xmit_ring_fini(umdevice, i); + } + + mutex_destroy(&umdevice->os_param.xmit_mutex); +} diff --git a/usr/src/uts/common/io/bnx/bnxsnd.h b/usr/src/uts/common/io/bnx/bnxsnd.h new file mode 100644 index 0000000000..acbbf587bd --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxsnd.h @@ -0,0 +1,55 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + */ + +#ifndef _BNXSND_H +#define _BNXSND_H + +#include "bnx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int bnx_txpkts_init(um_device_t *const); +void bnx_txpkts_flush(um_device_t *const); +void bnx_txpkts_fini(um_device_t *const); + +#define BNX_SEND_GOODXMIT 0 +#define BNX_SEND_LINKDOWN 1 +#define BNX_SEND_DEFERPKT 2 +#define BNX_SEND_HDWRFULL 3 + +int bnx_xmit_pkt_map(um_txpacket_t *const, mblk_t *); + +int bnx_xmit_ring_xmit_qpkt(um_device_t *const, const unsigned int); + +int bnx_xmit_ring_xmit_mblk(um_device_t *const, const unsigned int, mblk_t *); + +void bnx_xmit_ring_reclaim(um_device_t *const, const unsigned int, s_list_t *); + +void bnx_xmit_ring_intr(um_device_t *const, const unsigned int); + +void bnx_txpkts_intr(um_device_t *const); + +void bnx_xmit_ring_post(um_device_t *const, const unsigned int); + +#ifdef __cplusplus +} +#endif + +#endif /* _BNXSND_H */ diff --git a/usr/src/uts/common/io/bnx/bnxtmr.c b/usr/src/uts/common/io/bnx/bnxtmr.c new file mode 100644 index 0000000000..1a5d142d84 --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxtmr.c @@ -0,0 +1,253 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2019, Joyent, Inc. + */ + +#include "bnxtmr.h" +#include "bnxrcv.h" +#include "bnxgld.h" + + +/* 1.5 seconds */ +#define BNX_LINK_CHECK_INTERVAL 10 + +/* Approximately every second. */ +#define BNX_LINK_CHECK_INTERVAL2 7 + +/* 500 msecs */ +#define BNX_TIMER_INTERVAL 500000 + + +typedef struct _bnx_fw_t { + u32_t shmemaddr; + u32_t length; + u32_t nvramaddr; +} bnx_fw_t; + +static void +bnx_link_check(lm_device_t *const lmdevice) +{ + if (lmdevice->vars.link_status == LM_STATUS_LINK_ACTIVE) { + /* + * If we have link and we are in the fallback (1gb forced), + * mode, we need to see if our link partner is sending us + * configs. If this is the case, we'll switch back to autoneg. + */ + if (lmdevice->vars.serdes_fallback_status) { + u32_t intr_exp_status; + + (void) lm_mwrite(lmdevice, lmdevice->params.phy_addr, + 0x17, 0x0f01); + (void) lm_mread(lmdevice, lmdevice->params.phy_addr, + 0x15, &intr_exp_status); + (void) lm_mread(lmdevice, lmdevice->params.phy_addr, + 0x15, &intr_exp_status); + + if (intr_exp_status & 0x20) { + (void) lm_mwrite(lmdevice, + lmdevice->params.phy_addr, + PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | + PHY_CTRL_RESTART_AUTO_NEG); + } + } + } else { + lm_service_phy_int(lmdevice, TRUE); + } +} + +static void +bnx_link_check2(lm_device_t *const lmdevice) +{ + if (lmdevice->vars.link_status == LM_STATUS_LINK_ACTIVE) { + u32_t val; + u32_t phy_addr; + + phy_addr = lmdevice->params.phy_addr; + + /* Is the link really up? */ + (void) lm_mwrite(lmdevice, phy_addr, 0x1c, 0x6800); + (void) lm_mread(lmdevice, phy_addr, 0x1c, &val); + (void) lm_mread(lmdevice, phy_addr, 0x1c, &val); + + if (val & 2) { + /* Nope. Force the link down. */ + (void) lm_mwrite(lmdevice, phy_addr, 0x17, 0x0f03); + (void) lm_mread(lmdevice, phy_addr, 0x15, &val); + (void) lm_mwrite(lmdevice, phy_addr, 0x15, + val & 0xff0f); + + lmdevice->vars.bcm5706s_tx_drv_cur = (u16_t)val; + } + } +} + + + +/* + * Name: bnx_timer + * + * Input: ptr to device structure + * + * Return: None + * + * Description: bnx_timer is the periodic timer callback funtion. + */ +static void +bnx_timer(void *arg) +{ + lm_device_t *lmdevice; + um_device_t *umdevice; + + umdevice = (um_device_t *)arg; + lmdevice = &(umdevice->lm_dev); + + mutex_enter(&umdevice->tmr_mutex); + + if (umdevice->timer_enabled != B_TRUE) { + goto done; + } + + um_send_driver_pulse(umdevice); + + /* + * Take this opportunity to replenish any unused Rx Bds. Don't + * wait around for the rcv_mutex though. We share the + * responsibility of replenishing the rx buffers with the ISR. + */ + if (mutex_tryenter(&umdevice->os_param.rcv_mutex)) { + /* This function does an implicit *_fill(). */ + bnx_rxpkts_post(umdevice); + + mutex_exit(&umdevice->os_param.rcv_mutex); + } + + if (umdevice->timer_link_check_interval2) { + /* + * If enabled, check to see if the serdes + * PHY can fallback to a forced mode. + */ + if (umdevice->timer_link_check_interval) { + if (umdevice->timer_link_check_counter) { + if (umdevice->timer_link_check_counter == 1) { + mutex_enter( + &umdevice->os_param.phy_mutex); + bnx_link_check(lmdevice); + mutex_exit( + &umdevice->os_param.phy_mutex); + } + umdevice->timer_link_check_counter--; + } + } + + umdevice->timer_link_check_counter2--; + if (umdevice->timer_link_check_counter2 == 0) { + mutex_enter(&umdevice->os_param.phy_mutex); + bnx_link_check2(lmdevice); + mutex_exit(&umdevice->os_param.phy_mutex); + + umdevice->timer_link_check_counter2 = + umdevice->timer_link_check_interval2; + } + } + + FLUSHPOSTEDWRITES(lmdevice); + + umdevice->tmrtid = timeout(bnx_timer, (void *)umdevice, + drv_usectohz(BNX_TIMER_INTERVAL)); + +done: + mutex_exit(&umdevice->tmr_mutex); +} + +void +bnx_timer_start(um_device_t *const umdevice) +{ + lm_device_t *lmdevice; + + lmdevice = &(umdevice->lm_dev); + + umdevice->timer_enabled = B_TRUE; + + if (CHIP_NUM(lmdevice) == CHIP_NUM_5706 && + umdevice->dev_var.isfiber == B_TRUE) { + if (lmdevice->vars.serdes_fallback_select != + SERDES_FALLBACK_NONE) { + umdevice->timer_link_check_interval = + BNX_LINK_CHECK_INTERVAL; + } else { + umdevice->timer_link_check_interval = 0; + } + + umdevice->timer_link_check_interval2 = BNX_LINK_CHECK_INTERVAL2; + umdevice->timer_link_check_counter2 = + umdevice->timer_link_check_interval2; + } else { + umdevice->timer_link_check_interval2 = 0; + } + + umdevice->tmrtid = timeout(bnx_timer, (void *)umdevice, + drv_usectohz(BNX_TIMER_INTERVAL)); +} + + +void +bnx_timer_stop(um_device_t *const umdevice) +{ + mutex_enter(&umdevice->tmr_mutex); + umdevice->timer_enabled = B_FALSE; + mutex_exit(&umdevice->tmr_mutex); + + (void) untimeout(umdevice->tmrtid); + umdevice->tmrtid = 0; +} + + + +/* + * Name: bnx_link_timer_restart + * + * Input: ptr to device structure + * + * Return: None + * + * Description: This function restarts the link poll timer + * + */ +void +bnx_link_timer_restart(um_device_t *const umdevice) +{ + /* FIXME -- Make timer_link_check_counter atomic */ + umdevice->timer_link_check_counter = + umdevice->timer_link_check_interval; +} + + + +void +bnx_timer_init(um_device_t *const umdevice) +{ + mutex_init(&umdevice->tmr_mutex, NULL, MUTEX_DRIVER, + DDI_INTR_PRI(umdevice->intrPriority)); +} + + + +void +bnx_timer_fini(um_device_t *const umdevice) +{ + mutex_destroy(&umdevice->tmr_mutex); +} diff --git a/usr/src/uts/common/io/bnx/bnxtmr.h b/usr/src/uts/common/io/bnx/bnxtmr.h new file mode 100644 index 0000000000..e85117a50f --- /dev/null +++ b/usr/src/uts/common/io/bnx/bnxtmr.h @@ -0,0 +1,38 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + */ + +#ifndef _BNXTMR_H +#define _BNXTMR_H + +#include "bnx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void bnx_timer_init(um_device_t *const); +void bnx_timer_start(um_device_t *const); +void bnx_timer_stop(um_device_t *const); +void bnx_timer_fini(um_device_t *const); +void bnx_link_timer_restart(um_device_t *); + +#ifdef __cplusplus +} +#endif + +#endif /* _BNXTMR_H */ diff --git a/usr/src/uts/common/io/bnx/debug.h b/usr/src/uts/common/io/bnx/debug.h new file mode 100644 index 0000000000..5912adb80a --- /dev/null +++ b/usr/src/uts/common/io/bnx/debug.h @@ -0,0 +1,243 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved. + */ + +#ifndef _DEBUG_H +#define _DEBUG_H + + + +/* + * Debug break and output routines. + */ + +void +debug_break(void *ctx); + +void debug_msg(void *ctx, unsigned long level, char *file, unsigned long line, + char *msg, ...); + +void debug_msgx(void *ctx, unsigned long level, char *msg, ...); + + + +/* + * Debug macros + */ + +/* Code paths. */ +#define CP_INIT 0x010000 /* Initialization */ +#define CP_SEND 0x020000 /* Transmit */ +#define CP_RCV 0x040000 /* Recieve */ +#define CP_INT 0x080000 /* Interrupt */ +#define CP_UINIT 0x100000 /* Unload */ +#define CP_RESET 0x200000 /* Reset */ +#define CP_GEN_BUF 0x400000 /* Generic buffer. */ +#define CP_ALL 0xffff0000 /* All code path */ + +#define CP_MASK 0xffff0000 + + +/* Mess ge levels. */ +#define LV_VERBOSE 0x03 +#define LV_INFORM 0x02 +#define LV_WARN 0x01 +#define LV_FATAL 0x00 + +#define LV_MASK 0xffff + + +/* + * Code path and messsage level combined. These are the first argument + * of the DbgMessage macro. + */ + +#define VERBOSEi (CP_INIT | LV_VERBOSE) +#define INFORMi (CP_INIT | LV_INFORM) +#define WARNi (CP_INIT | LV_WARN) + +#define VERBOSEtx (CP_SEND | LV_VERBOSE) +#define INFORMtx (CP_SEND | LV_INFORM) +#define WARNtx (CP_SEND | LV_WARN) + +#define VERBOSErx (CP_RCV | LV_VERBOSE) +#define INFORMrx (CP_RCV | LV_INFORM) +#define WARNrx (CP_RCV | LV_WARN) + +#define VERBOSEint (CP_INT | LV_VERBOSE) +#define INFORMint (CP_INT | LV_INFORM) +#define WARNint (CP_INT | LV_WARN) + +#define VERBOSEu (CP_UINIT | LV_VERBOSE) +#define INFORMu (CP_UINIT | LV_INFORM) +#define WARNu (CP_UINIT | LV_WARN) + +#define VERBOSErs (CP_RESET | LV_VERBOSE) +#define INFORMrs (CP_RESET | LV_INFORM) +#define WARNrs (CP_RESET | LV_WARN) + +#define VERBOSEgb (CP_GEN_BUF | LV_VERBOSE) +#define INFORMgb (CP_GEN_BUF | LV_INFORM) +#define WARNgb (CP_GEN_BUF | LV_WARN) + + +#define FATAL (CP_ALL | LV_FATAL) +#define WARN (CP_ALL | LV_WARN) +#define INFORM (CP_ALL | LV_INFORM) +#define VERBOSE (CP_ALL | LV_VERBOSE) + + +#if DBG + +/* + * These constants control the output of messages. + * Set your debug message output level and code path here. + */ +#ifndef DBG_MSG_CP +#define DBG_MSG_CP CP_ALL /* Where to output messages. */ +#endif + +#ifndef DBG_MSG_LV +#define DBG_MSG_LV LV_VERBOSE /* Level of message output. */ +#endif + + +/* CSTYLED */ +#define STATIC +#define DbgBreak(_c) debug_break(_c) + + +#define CODE_PATH(_m) ((_m) & DBG_MSG_CP) +#define MSG_LEVEL(_m) ((_m) & LV_MASK) +#define LOG_MSG(_m) (CODE_PATH(_m) && \ + MSG_LEVEL(_m) <= DBG_MSG_LV) + + +/* BEGIN CSTYLED */ +#define DbgMessage(_c, _m, _s) \ + if (LOG_MSG(_m)) \ + { \ + debug_msg(_c, _m, __FILE__, __LINE__, _s); \ + } +#define DbgMessage1(_c, _m, _s, _d1) \ + if (LOG_MSG(_m)) \ + { \ + debug_msg(_c, _m, __FILE__, __LINE__, _s, _d1); \ + } +#define DbgMessage2(_c, _m, _s, _d1, _d2) \ + if (LOG_MSG(_m)) \ + { \ + debug_msg(_c, _m, __FILE__, __LINE__, _s, _d1, _d2); \ + } +#define DbgMessage3(_c, _m, _s, _d1, _d2, _d3) \ + if (LOG_MSG(_m)) \ + { \ + debug_msg(_c, _m, __FILE__, __LINE__, _s, _d1, _d2, _d3); \ + } +#define DbgMessage4(_c, _m, _s, _d1, _d2, _d3, _d4) \ + if (LOG_MSG(_m)) \ + { \ + debug_msg(_c, _m, __FILE__, __LINE__, _s, _d1, _d2, _d3, _d4); \ + } +#define DbgMessage5(_c, _m, _s, _d1, _d2, _d3, _d4, _d5) \ + if (LOG_MSG(_m)) \ + { \ + debug_msg(_c, _m, __FILE__, __LINE__, _s, _d1, _d2, _d3, _d4, _d5); \ + } +#define DbgMessage6(_c, _m, _s, _d1, _d2, _d3, _d4, _d5, _d6) \ + if (LOG_MSG(_m)) \ + { \ + debug_msg(_c, _m, __FILE__, __LINE__, _s, _d1,_d2,_d3,_d4,_d5,_d6); \ + } + +#define DbgMessageX(_c, _m, _s) \ + if (LOG_MSG(_m)) \ + { \ + debug_msgx(_c, _m, _s); \ + } +#define DbgMessageX1(_c, _m, _s, _d1) \ + if (LOG_MSG(_m)) \ + { \ + debug_msgx(_c, _m, _s, _d1); \ + } +#define DbgMessageX2(_c, _m, _s, _d1, _d2) \ + if (LOG_MSG(_m)) \ + { \ + debug_msgx(_c, _m, _s, _d1, _d2); \ + } +#define DbgMessageX3(_c, _m, _s, _d1, _d2, _d3) \ + if (LOG_MSG(_m)) \ + { \ + debug_msgx(_c, _m, _s, _d1, _d2, _d3); \ + } +#define DbgMessageX4(_c, _m, _s, _d1, _d2, _d3, _d4) \ + if (LOG_MSG(_m)) \ + { \ + debug_msgx(_c, _m, _s, _d1, _d2, _d3, _d4); \ + } +#define DbgMessageX5(_c, _m, _s, _d1, _d2, _d3, _d4, _d5) \ + if (LOG_MSG(_m)) \ + { \ + debug_msgx(_c, _m, _s, _d1, _d2, _d3, _d4, _d5); \ + } +#define DbgMessageX6(_c, _m, _s, _d1, _d2, _d3, _d4, _d5, _d6) \ + if (LOG_MSG(_m)) \ + { \ + debug_msgx(_c, _m, _s, _d1,_d2,_d3,_d4,_d5,_d6); \ + } + +#define DbgBreakIf(_c) \ + if (_c) \ + { \ + debug_msg(NULL, FATAL, __FILE__, __LINE__, "if("#_c##")\n"); \ + debug_break(NULL); \ + } + +#define DbgBreakMsg(_m) debug_msg(NULL, FATAL, __FILE__, __LINE__, _m); \ + debug_break(NULL) +/* END CSTYLED */ + + +#else + +/* CSTYLED */ +#define STATIC static + +#define DbgBreak(_c) + +#define DbgMessage(_c, _m, _s) +#define DbgMessage1(_c, _m, _s, _d1) +#define DbgMessage2(_c, _m, _s, _d1, _d2) +#define DbgMessage3(_c, _m, _s, _d1, _d2, _d3) +#define DbgMessage4(_c, _m, _s, _d1, _d2, _d3, _d4) +#define DbgMessage5(_c, _m, _s, _d1, _d2, _d3, _d4, _d5) +#define DbgMessage6(_c, _m, _s, _d1, _d2, _d3, _d4, _d5, _d6) + +#define DbgMessageX(_c, _m, _s) +#define DbgMessageX1(_c, _m, _s, _d1) +#define DbgMessageX2(_c, _m, _s, _d1, _d2) +#define DbgMessageX3(_c, _m, _s, _d1, _d2, _d3) +#define DbgMessageX4(_c, _m, _s, _d1, _d2, _d3, _d4) +#define DbgMessageX5(_c, _m, _s, _d1, _d2, _d3, _d4, _d5) +#define DbgMessageX6(_c, _m, _s, _d1, _d2, _d3, _d4, _d5, _d6) + +#define DbgBreakIf(_c) +#define DbgBreakMsg(_m) + +#endif + +#endif /* _DEBUG_H */ diff --git a/usr/src/uts/common/io/bnx/include/bcmtype.h b/usr/src/uts/common/io/bnx/include/bcmtype.h new file mode 100644 index 0000000000..2f9dfb9787 --- /dev/null +++ b/usr/src/uts/common/io/bnx/include/bcmtype.h @@ -0,0 +1,279 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __bcmtype_h__ +#define __bcmtype_h__ + +#if defined(UEFI) && defined (EVEREST_DIAG) +#include <machine/endian.h> +#endif + +#ifndef IN +#define IN +#endif /* IN */ + +#ifndef OUT +#define OUT +#endif /* OUT */ + +#ifndef INOUT +#define INOUT +#endif /* INOUT */ + +#ifndef OPTIONAL +#define OPTIONAL +#endif /* OPTIONAL */ + +#if defined(__LINUX) || defined (USER_LINUX) + +#ifdef __LINUX + +#ifdef __BIG_ENDIAN +#ifndef BIG_ENDIAN +#define BIG_ENDIAN +#endif +#else /* __LITTLE_ENDIAN */ +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN +#endif +#endif + +/* + * define underscore-t types + */ +typedef u64 u64_t; +typedef u32 u32_t; +typedef u16 u16_t; +typedef u8 u8_t; + +typedef s64 s64_t; +typedef s32 s32_t; +typedef s16 s16_t; +typedef s8 s8_t; + +typedef unsigned long int_ptr_t; + +#else /* USER_LINUX */ + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#undef BIG_ENDIAN +#undef __BIG_ENDIAN +#else +#undef LITTLE_ENDIAN +#undef __LITTLE_ENDIAN +#endif + +/* + * define underscore-t types + */ +typedef u_int64_t u64_t; +typedef u_int32_t u32_t; +typedef u_int16_t u16_t; +typedef u_int8_t u8_t; + +typedef int64_t s64_t; +typedef int32_t s32_t; +typedef int16_t s16_t; +typedef int8_t s8_t; + +typedef u_int64_t u64; +typedef u_int32_t u32; +typedef u_int16_t u16; +typedef u_int8_t u8; + +typedef int64_t s64; +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef unsigned long int_ptr_t; + +/* Define upper case types */ + +typedef u64_t U64; +typedef u32_t U32; +typedef u16_t U16; +typedef u8_t U8; + +typedef s64_t S64; +typedef s32_t S32; +typedef s16_t S16; +typedef s8_t S8; + +#endif + + + +#else +/* + * define the data model + */ +#if !defined(LP64) && !defined(P64) && !defined(LLP64) + /* VC 32-bit compiler 5.0 or later */ + #if (defined(_MSC_VER) && (_MSC_VER > 800)) || defined(TARGET_WINDOWS) + #define P64 + #elif defined(__sun) + /* Solaris */ + #define LP64 + #elif defined(_HPUX_SOURCE) + /* HP/UX */ + #define LP64 + #elif defined(__FreeBSD__) + /* FreeBSD */ + #define LP64 + #elif defined(LINUX) + /* Linux */ + #define LP64 + #elif defined(__bsdi__) + /* BSDI */ + #define LP64 + #elif defined(_IRIX) + /* IRIX */ + #define LP64 + #elif defined(UNIXWARE) + /* UnixWare */ + #define LP64 + #endif /* UNIXWARE */ +#endif /* !LP64 && !P64 && !LLP64 */ + +/* + * define sized type + */ +#if defined(P64) || defined(LLP64) + /* P64 */ + typedef unsigned __int64 U64; + typedef unsigned int U32; + typedef unsigned short U16; + typedef unsigned char U8; + typedef signed __int64 S64; + typedef signed int S32; + typedef signed short S16; + typedef signed char S8; + + #if defined(IA64) || defined(AMD64) + typedef U64 int_ptr_t; + #else + #ifndef UEFI64 + typedef unsigned long int_ptr_t; + #endif + #endif +#elif defined(LP64) + /* LP64: Sun, HP and etc */ + typedef unsigned long long U64; + typedef unsigned int U32; + typedef unsigned short U16; + typedef unsigned char U8; + typedef signed long long S64; + typedef signed int S32; + typedef signed short S16; + typedef signed char S8; + typedef unsigned long int_ptr_t; +#elif defined(__WATCOMC__) + typedef unsigned __int64 U64; + typedef unsigned long U32; + typedef unsigned short U16; + typedef unsigned char U8; + typedef signed __int64 S64; + typedef signed long S32; + typedef signed short S16; + typedef signed char S8; + typedef unsigned long int_ptr_t; +#else + /* assume others: 16-bit */ + typedef unsigned char U64[8]; + typedef unsigned long U32; + typedef unsigned short U16; + typedef unsigned char U8; + typedef signed char S64[8]; + typedef signed long S32; + typedef signed short S16; + typedef signed char S8; + typedef unsigned long int_ptr_t; +#endif /* */ + + + +/* + * define lower case types + */ +typedef U64 u64_t; +typedef U32 u32_t; +typedef U16 u16_t; +typedef U8 u8_t; + +typedef S64 s64_t; +typedef S32 s32_t; +typedef S16 s16_t; +typedef S8 s8_t; + +#ifndef LINUX +typedef U64 u64; +typedef U32 u32; +typedef U16 u16; +typedef U8 u8; + +typedef S64 s64; +typedef S32 s32; +typedef S16 s16; +typedef S8 s8; +#endif + +#endif + +#ifdef UEFI +#if BYTE_ORDER == LITTLE_ENDIAN +#undef BIG_ENDIAN +#endif +#ifdef UEFI64 +typedef u64_t int_ptr_t; +#endif +#endif + +#ifdef LITTLE_ENDIAN +#ifndef __LITTLE_ENDIAN +#define __LITTLE_ENDIAN LITTLE_ENDIAN +#endif /* __LITTLE_ENDIAN */ +#endif /* LITTLE_ENDIAN */ + +#ifdef BIG_ENDIAN +#ifndef __BIG_ENDIAN +#define __BIG_ENDIAN BIG_ENDIAN +#endif /* __BIG_ENDIAN */ +#endif /* BIG_ENDIAN */ + +#ifdef __FreeBSD__ +#if _BYTE_ORDER == _LITTLE_ENDIAN +#undef BIG_ENDIAN +#undef __BIG_ENDIAN +#else +#undef LITTLE_ENDIAN +#undef __LITTLE_ENDIAN +#endif +#endif /* __FreeBSD__ */ + +/* Signed subtraction macros with no sign extending. */ +#define S64_SUB(_a, _b) ((s64_t) ((s64_t) (_a) - (s64_t) (_b))) +#define u64_SUB(_a, _b) ((u64_t) ((s64_t) (_a) - (s64_t) (_b))) +#define S32_SUB(_a, _b) ((s32_t) ((s32_t) (_a) - (s32_t) (_b))) +#define uS32_SUB(_a, _b) ((u32_t) ((s32_t) (_a) - (s32_t) (_b))) +#define S16_SUB(_a, _b) ((s16_t) ((s16_t) (_a) - (s16_t) (_b))) +#define u16_SUB(_a, _b) ((u16_t) ((s16_t) (_a) - (s16_t) (_b))) +#define PTR_SUB(_a, _b) ((u8_t *) (_a) - (u8_t *) (_b)) + +#if (!defined LINUX ) && (!defined MFW) +#define __builtin_offsetof(path1_nvm_image_t, f) (u32_t)((int_ptr_t)(&(((path1_nvm_image_t *)0)->f))) +#endif + +#endif/* __bcmtype_h__ */ + diff --git a/usr/src/uts/common/io/bnx/include/bits.h b/usr/src/uts/common/io/bnx/include/bits.h new file mode 100644 index 0000000000..e3e2464dc2 --- /dev/null +++ b/usr/src/uts/common/io/bnx/include/bits.h @@ -0,0 +1,97 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _BITS_H +#define _BITS_H + +/* + * Bit Mask definitions + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define BIT_NONE 0x00 +#define BIT_0 0x01 +#define BIT_1 0x02 +#define BIT_2 0x04 +#define BIT_3 0x08 +#define BIT_4 0x10 +#define BIT_5 0x20 +#define BIT_6 0x40 +#define BIT_7 0x80 +#define BIT_8 0x0100 +#define BIT_9 0x0200 +#define BIT_10 0x0400 +#define BIT_11 0x0800 +#define BIT_12 0x1000 +#define BIT_13 0x2000 +#define BIT_14 0x4000 +#define BIT_15 0x8000 +#define BIT_16 0x010000 +#define BIT_17 0x020000 +#define BIT_18 0x040000 +#define BIT_19 0x080000 +#define BIT_20 0x100000 +#define BIT_21 0x200000 +#define BIT_22 0x400000 +#define BIT_23 0x800000 +#define BIT_24 0x01000000 +#define BIT_25 0x02000000 +#define BIT_26 0x04000000 +#define BIT_27 0x08000000 +#define BIT_28 0x10000000 +#define BIT_29 0x20000000 +#define BIT_30 0x40000000 +#define BIT_31 0x80000000 + +#define BIT_32 0x0100000000 +#define BIT_33 0x0200000000 +#define BIT_34 0x0400000000 +#define BIT_35 0x0800000000 +#define BIT_36 0x1000000000 +#define BIT_37 0x2000000000 +#define BIT_38 0x4000000000 +#define BIT_39 0x8000000000 +#define BIT_40 0x010000000000 +#define BIT_41 0x020000000000 +#define BIT_42 0x040000000000 +#define BIT_43 0x080000000000 +#define BIT_44 0x100000000000 +#define BIT_45 0x200000000000 +#define BIT_46 0x400000000000 +#define BIT_47 0x800000000000 +#define BIT_48 0x01000000000000 +#define BIT_49 0x02000000000000 +#define BIT_50 0x04000000000000 +#define BIT_51 0x08000000000000 +#define BIT_52 0x10000000000000 +#define BIT_53 0x20000000000000 +#define BIT_54 0x40000000000000 +#define BIT_55 0x80000000000000 +#define BIT_56 0x0100000000000000 +#define BIT_57 0x0200000000000000 +#define BIT_58 0x0400000000000000 +#define BIT_59 0x0800000000000000 +#define BIT_60 0x1000000000000000 +#define BIT_61 0x2000000000000000 +#define BIT_62 0x4000000000000000 +#define BIT_63 0x8000000000000000 + +#ifdef __cplusplus +} +#endif + +#endif /* _BITS_H */ diff --git a/usr/src/uts/common/io/bnx/include/hsi.h b/usr/src/uts/common/io/bnx/include/hsi.h new file mode 100644 index 0000000000..4f5bb07654 --- /dev/null +++ b/usr/src/uts/common/io/bnx/include/hsi.h @@ -0,0 +1,32 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PRIVATE_HSI_H +#define PRIVATE_HSI_H + +#define tcp_syn_dos_defense (0x10 + 0x020) +#define rxp_unicast_bytes_rcvd (0x10 + 0x0d0) +#define rxp_multicast_bytes_rcvd (0x10 + 0x0d8) +#define rxp_broadcast_bytes_rcvd (0x10 + 0x0e0) +#define RXP_HSI_OFFSETOFF(x) (x) + +#define com_no_buffer (0x10 + 0x074) +#define COM_HSI_OFFSETOFF(x) (x) + +#define unicast_bytes_xmit (0x410 + 0x030) +#define multicast_bytes_xmit (0x410 + 0x038) +#define broadcast_bytes_xmit (0x410 + 0x040) +#define TPAT_HSI_OFFSETOFF(x) (x) + +#endif diff --git a/usr/src/uts/common/io/bnx/include/listq.h b/usr/src/uts/common/io/bnx/include/listq.h new file mode 100644 index 0000000000..c5f71284d1 --- /dev/null +++ b/usr/src/uts/common/io/bnx/include/listq.h @@ -0,0 +1,1227 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/******************************************************************************* + * + * Single link list routines: + * void s_list_init (s_list_t *, *head, *tail, cnt) + * void s_list_clear (s_list_t *) + * void s_list_push_head (s_list_t *, s_list_entry_t *) + * s_list_entry_t * s_list_pop_head (s_list_t *) + * void s_list_push_tail (s_list_t *, s_list_entry_t *) + * s_list_entry_t * s_list_peek_head (s_list_t *) + * s_list_entry_t * s_list_peek_tail (s_list_t *) + * s_list_entry_t * s_list_next_entry (s_list_entry_t *) + * unsigned long s_list_entry_cnt (s_list_t *) + * char s_list_is_empty (s_list_t *) + * void s_list_add_head (s_list_t *, s_list_t *) + * void s_list_add_tail (s_list_t *, s_list_t *) + * void s_list_split (d_list_t *, d_list_t *, d_list_entry_t *, ulong) + * + * Double link list routines: + * void d_list_init (d_list_t *, *head, *tail, cnt) + * void d_list_clear (d_list_t *) + * void d_list_push_head (d_list_t *, d_list_entry_t *) + * d_list_entry_t * d_list_pop_head (d_list_t *) + * void d_list_push_tail (d_list_t *, d_list_entry_t *) + * d_list_entry_t * d_list_pop_tail (d_list_t *) + * d_list_entry_t * d_list_peek_head (d_list_t *) + * d_list_entry_t * d_list_peek_tail (d_list_t *) + * d_list_entry_t * d_list_next_entry (d_list_entry_t *) + * void d_list_remove_entry(d_list_t *, d_list_entry_t *) + * void d_list_insert_entry(d_list_t *, *prev, *next, *new) + * d_list_entry_t * d_list_prev_entry (d_list_entry_t *) + * unsigned long d_list_entry_cnt (d_list_t *) + * char d_list_is_empty (d_list_t *) + * void d_list_add_head (d_list_t *, d_list_t *) + * void d_list_add_tail (d_list_t *, d_list_t *) + * + * Array list routines: + * void q_list_init (q_list_t *, q_list_entry *, ulong) + * void q_list_clear (q_list_t *) + * void q_list_push_head (q_list_t *, q_list_entry_t) + * q_list_entry_t q_list_pop_head (q_list_t *) + * void q_list_push_tail (q_list_t *, q_list_entry_t) + * q_list_entry_t q_list_pop_tail (q_list_t *) + * q_list_entry_t q_list_peek_head (q_list_t *) + * q_list_entry_t q_list_peek_tail (q_list_t *) + * unsigned long q_list_entry_cnt (q_list_t *) + * char q_list_is_empty (q_list_t *) + * char q_list_is_full (q_list_t *) + * + * History: + * 03/30/98 Hav Khauv Initial version. + ******************************************************************************/ + +#ifndef _listq_h_ +#define _listq_h_ + + + +/******************************************************************************* + * Single link list. + ******************************************************************************/ + +typedef struct _s_list_entry_t +{ + struct _s_list_entry_t *next; +} s_list_entry_t; + +#define S_LINK_CAST(_p) ((s_list_entry_t *) (_p)) + + +typedef struct _s_list_t +{ + s_list_entry_t *head; + s_list_entry_t *tail; + unsigned long cnt; +} s_list_t; + + + +#ifdef _INLINE_LISTQ_CALLS + + +__inline +void +s_list_init( + s_list_t *s_list, + s_list_entry_t *head_entry, + s_list_entry_t *tail_entry, + unsigned long entry_cnt) +{ + s_list->head = head_entry; + s_list->tail = tail_entry; + s_list->cnt = entry_cnt; +} + + +__inline +void +s_list_clear( + s_list_t *s_list) +{ + s_list->head = (s_list_entry_t *) 0; + s_list->tail = (s_list_entry_t *) 0; + s_list->cnt = 0; +} + + +__inline +void +s_list_push_head( + s_list_t *s_list, + s_list_entry_t *s_entry) +{ + s_entry->next = s_list->head; + + if(s_list->tail == (s_list_entry_t *) 0) + { + s_list->tail = s_entry; + } + s_list->head = s_entry; + + s_list->cnt++; +} + + +__inline +s_list_entry_t * +s_list_pop_head( + s_list_t *s_list) +{ + s_list_entry_t *s_entry; + + s_entry = s_list->head; + if(s_list->head) + { + s_list->head = s_list->head->next; + if(s_list->head == (s_list_entry_t *) 0) + { + s_list->tail = (s_list_entry_t *) 0; + } + + s_list->cnt--; + } + + return s_entry; +} + + +__inline +void +s_list_push_tail( + s_list_t *s_list, + s_list_entry_t *s_entry) +{ + s_entry->next = (s_list_entry_t *) 0; + + if(s_list->tail) + { + s_list->tail->next = s_entry; + } + else + { + s_list->head = s_entry; + } + s_list->tail = s_entry; + + s_list->cnt++; +} + + +__inline +s_list_entry_t * +s_list_peek_head( + s_list_t *s_list) +{ + return s_list->head; +} + + +__inline +s_list_entry_t * +s_list_peek_tail( + s_list_t *s_list) +{ + return s_list->tail; +} + + +__inline +s_list_entry_t * +s_list_next_entry( + s_list_entry_t *s_entry) +{ + return s_entry->next; +} + + +__inline +unsigned long +s_list_entry_cnt( + s_list_t *s_list) +{ + return s_list->cnt; +} + + +__inline +char +s_list_is_empty( + s_list_t *s_list) +{ + return s_list->cnt == 0; +} + + +__inline +void +s_list_add_head( + s_list_t *s_list, + s_list_t *s_list_head) +{ + if(s_list->cnt == 0) + { + *s_list = *s_list_head; + } + else if(s_list_head->cnt) + { + s_list_head->tail->next = s_list->head; + s_list->head = s_list_head->head; + s_list->cnt += s_list_head->cnt; + } +} + + +__inline +void +s_list_add_tail( + s_list_t *s_list, + s_list_t *s_list_tail) +{ + if(s_list->cnt == 0) + { + *s_list = *s_list_tail; + } + else if(s_list_tail->cnt) + { + s_list->tail->next = s_list_tail->head; + s_list->tail = s_list_tail->tail; + s_list->cnt += s_list_tail->cnt; + } +} + +__inline +void +s_list_split( + s_list_t * s_list, + s_list_t * s_list_head, + s_list_entry_t * split_entry, + unsigned long entry_cnt) +{ + if (split_entry->next == NULL) { + s_list_head->head = s_list->head; + s_list_head->tail = split_entry; + s_list_head->cnt = entry_cnt; + + s_list->head = NULL; + s_list->tail = NULL; + s_list->cnt = 0; + } else { + s_list_head->head = s_list->head; + s_list_head->tail = split_entry; + s_list_head->cnt = entry_cnt; + + s_list->head = split_entry->next; + s_list->cnt = s_list->cnt - entry_cnt; + split_entry->next = NULL; + + } +} + +#else + + +#define s_list_init(_s_list, _head_entry, _tail_entry, _entry_cnt) \ + (_s_list)->head = (_head_entry); \ + (_s_list)->tail = (_tail_entry); \ + (_s_list)->cnt = (_entry_cnt) + + +#define s_list_clear(_s_list) \ + (_s_list)->head = (s_list_entry_t *) 0; \ + (_s_list)->tail = (s_list_entry_t *) 0; \ + (_s_list)->cnt = 0 + + +#define s_list_push_head(_s_list, _s_entry) \ + (_s_entry)->next = (_s_list)->head; \ + if((_s_list)->tail == (s_list_entry_t *) 0) \ + { \ + (_s_list)->tail = (_s_entry); \ + } \ + (_s_list)->head = (_s_entry); \ + (_s_list)->cnt++ + + +#define s_list_pop_head(_s_list) \ + (_s_list)->head; \ + if((_s_list)->head) \ + { \ + (_s_list)->head = (_s_list)->head->next; \ + if((_s_list)->head == (s_list_entry_t *) 0) \ + { \ + (_s_list)->tail = (s_list_entry_t *) 0; \ + } \ + (_s_list)->cnt--; \ + } + + +#define s_list_push_tail(_s_list, _s_entry) \ + (_s_entry)->next = (s_list_entry_t *) 0; \ + if((_s_list)->tail) \ + { \ + (_s_list)->tail->next = (_s_entry); \ + } \ + else \ + { \ + (_s_list)->head = (_s_entry); \ + } \ + (_s_list)->tail = (_s_entry); \ + (_s_list)->cnt++ + + +#define s_list_peek_head(_s_list) ((_s_list)->head) + + +#define s_list_peek_tail(_s_list) ((_s_list)->tail) + + +#define s_list_next_entry(_s_entry) ((_s_entry)->next) + + +#define s_list_entry_cnt(_s_list) ((_s_list)->cnt) + + +#define s_list_is_empty(_s_list) ((_s_list)->cnt == 0) + + +#define s_list_add_head(_s_list, _s_list_head) \ + if((_s_list)->cnt == 0) \ + { \ + *(_s_list) = *(_s_list_head); \ + } \ + else if((_s_list_head)->cnt) \ + { \ + (_s_list_head)->tail->next = (_s_list)->head; \ + (_s_list)->head = (_s_list_head)->head; \ + (_s_list)->cnt += (_s_list_head)->cnt; \ + } + +#define s_list_add_tail(_s_list, _s_list_tail) \ + if((_s_list)->cnt == 0) \ + { \ + *(_s_list) = *(_s_list_tail); \ + } \ + else if((_s_list_tail)->cnt) \ + { \ + (_s_list)->tail->next = (_s_list_tail)->head; \ + (_s_list)->tail = (_s_list_tail)->tail; \ + (_s_list)->cnt += (_s_list_tail)->cnt; \ + } + +#define s_list_split(_s_list, _s_list_head, _split_entry, _entry_cnt) \ + if ((_split_entry)->next == NULL) { \ + (_s_list_head)->head = (_s_list)->head; \ + (_s_list_head)->tail = _split_entry; \ + (_s_list_head)->cnt = _entry_cnt; \ + (_s_list)->head = NULL; \ + (_s_list)->tail = NULL; \ + (_s_list)->cnt = 0; \ + } else { \ + (_s_list_head)->head = (_s_list)->head; \ + (_s_list_head)->tail = _split_entry; \ + (_s_list_head)->cnt = (_entry_cnt); \ + (_s_list)->head = (_split_entry)->next; \ + (_s_list)->cnt = (_s_list)->cnt - (_entry_cnt); \ + (_split_entry)->next = NULL; \ + } + +#endif + + + +/******************************************************************************* + * Double link list entry. + ******************************************************************************/ + +typedef struct _d_list_entry_t +{ + struct _d_list_entry_t *next; + struct _d_list_entry_t *prev; +} d_list_entry_t; + +#define D_LINK_CAST(_p) ((d_list_entry_t *) (_p)) + + +typedef struct _d_list_t +{ + d_list_entry_t *head; + d_list_entry_t *tail; + unsigned long cnt; +} d_list_t; + + + +#ifdef _INLINE_LISTQ_CALLS + + +__inline +void +d_list_init( + d_list_t *d_list, + d_list_entry_t *head_entry, + d_list_entry_t *tail_entry, + unsigned long entry_cnt) +{ + d_list->head = head_entry; + d_list->tail = tail_entry; + d_list->cnt = entry_cnt; +} + + +__inline +void +d_list_clear( + d_list_t *d_list) +{ + d_list->head = (d_list_entry_t *) 0; + d_list->tail = (d_list_entry_t *) 0; + d_list->cnt = 0; +} + + +__inline +void +d_list_push_head( + d_list_t *d_list, + d_list_entry_t *d_entry) +{ + d_entry->prev = (d_list_entry_t *) 0; + d_entry->next = d_list->head; + + if(d_list->tail == (d_list_entry_t *) 0) + { + d_list->tail = d_entry; + } + else + { + d_list->head->prev = d_entry; + } + + d_list->head = d_entry; + + d_list->cnt++; +} + + +__inline +d_list_entry_t * +d_list_pop_head( + d_list_t *d_list) +{ + d_list_entry_t *d_entry; + + d_entry = d_list->head; + if(d_list->head) + { + d_list->head = d_list->head->next; + if(d_list->head) + { + d_list->head->prev = (d_list_entry_t *) 0; + } + else + { + d_list->tail = (d_list_entry_t *) 0; + } + + d_list->cnt--; + } + + return d_entry; +} + + +__inline +void +d_list_push_tail( + d_list_t *d_list, + d_list_entry_t *d_entry) +{ + d_entry->next = (d_list_entry_t *) 0; + d_entry->prev = d_list->tail; + + if(d_list->tail) + { + d_list->tail->next = d_entry; + } + else + { + d_list->head = d_entry; + } + d_list->tail = d_entry; + + d_list->cnt++; +} + + +__inline +d_list_entry_t * +d_list_pop_tail( + d_list_t *d_list) +{ + d_list_entry_t *d_entry; + + d_entry = d_list->tail; + + if(d_list->tail) + { + d_list->tail = d_list->tail->prev; + if(d_list->tail) + { + d_list->tail->next = (d_list_entry_t *) 0; + } + else + { + d_list->head = (d_list_entry_t *) 0; + } + + d_list->cnt--; + } + + return d_entry; +} + + +__inline +d_list_entry_t * +d_list_peek_head( + d_list_t *d_list) +{ + return d_list->head; +} + + +__inline +d_list_entry_t * +d_list_peek_tail( + d_list_t *d_list) +{ + return d_list->tail; +} + + +__inline +d_list_entry_t * +d_list_next_entry( + d_list_entry_t *d_entry) +{ + return d_entry->next; +} + + +__inline +void +d_list_remove_entry( + d_list_t *d_list, + d_list_entry_t *d_entry) +{ + if(d_list->head == d_entry) + { + d_list_pop_head(d_list); + } + else if(d_list->tail == d_entry) + { + d_list_pop_tail(d_list); + } + else + { + d_entry->prev->next = d_entry->next; + d_entry->next->prev = d_entry->prev; + d_list->cnt--; + } +} + +__inline +void +d_list_insert_entry( + d_list_t *d_list, + d_list_entry_t *d_entry_prev, + d_list_entry_t *d_entry_next, + d_list_entry_t *d_entry) +{ + if (d_entry_prev == NULL) + { + d_list_push_head(d_list, d_entry); + } + else if (d_entry_next == NULL) + { + d_list_push_tail(d_list, d_entry); + } + else + { + d_entry->next = d_entry_next; + d_entry->prev = d_entry_prev; + d_entry_prev->next = d_entry; + d_entry_next->prev = d_entry; + d_list->cnt++; + } +} + + +__inline +d_list_entry_t * +d_list_prev_entry( + d_list_entry_t *d_entry) +{ + return d_entry->prev; +} + + +__inline +unsigned long +d_list_entry_cnt( + d_list_t *d_list) +{ + return d_list->cnt; +} + + +__inline +char +d_list_is_empty( + d_list_t *d_list) +{ + return d_list->cnt == 0; +} + + +__inline +void +d_list_add_head( + d_list_t *d_list, + d_list_t *d_list_head) +{ + d_list_head->tail->next = d_list->head; + + if(d_list->head) + { + d_list->head->prev = d_list_head->tail; + } + else + { + d_list->tail = d_list_head->tail; + } + d_list->head = d_list_head->head; + + d_list->cnt += d_list_head->cnt; +} + + +__inline +void +d_list_add_tail( + d_list_t *d_list, + d_list_t *d_list_tail) +{ + d_list_tail->head->prev = d_list->tail; + + if(d_list->tail) + { + d_list->tail->next = d_list_tail->head; + } + else + { + d_list->head = d_list_tail->head; + } + d_list->tail = d_list_tail->tail; + + d_list->cnt += d_list_tail->cnt; +} + + +#else + + +#define d_list_init(_d_list, _head_entry, _tail_entry, _entry_cnt) \ + (_d_list)->head = (_head_entry); \ + (_d_list)->tail = (_tail_entry); \ + (_d_list)->cnt = (_entry_cnt) + + +#define d_list_clear(_d_list) \ + (_d_list)->head = (d_list_entry_t *) 0; \ + (_d_list)->tail = (d_list_entry_t *) 0; \ + (_d_list)->cnt = 0 + + +#define d_list_push_head(_d_list, _d_entry) \ + (_d_entry)->prev = (d_list_entry_t *) 0; \ + (_d_entry)->next = (_d_list)->head; \ + if((_d_list)->tail == (d_list_entry_t *) 0) \ + { \ + (_d_list)->tail = (_d_entry); \ + } \ + else \ + { \ + (_d_list)->head->prev = (_d_entry); \ + } \ + (_d_list)->head = (_d_entry); \ + (_d_list)->cnt++ + + +#define d_list_pop_head(_d_list) \ + (_d_list)->head; \ + if((_d_list)->head) \ + { \ + (_d_list)->head = (_d_list)->head->next; \ + if((_d_list)->head) \ + { \ + (_d_list)->head->prev = (d_list_entry_t *) 0; \ + } \ + else \ + { \ + (_d_list)->tail = (d_list_entry_t *) 0; \ + } \ + (_d_list)->cnt--; \ + } + + +#define d_list_push_tail(_d_list, _d_entry) \ + (_d_entry)->next = (d_list_entry_t *) 0; \ + (_d_entry)->prev = (_d_list)->tail; \ + if((_d_list)->tail) \ + { \ + (_d_list)->tail->next = (_d_entry); \ + } \ + else \ + { \ + (_d_list)->head = (_d_entry); \ + } \ + (_d_list)->tail = (_d_entry); \ + (_d_list)->cnt++ + + +#define d_list_pop_tail(_d_list) \ + (_d_list)->tail; \ + if((_d_list)->tail) \ + { \ + (_d_list)->tail = (_d_list)->tail->prev; \ + if((_d_list)->tail) \ + { \ + (_d_list)->tail->next = (d_list_entry_t *) 0; \ + } \ + else \ + { \ + (_d_list)->head = (d_list_entry_t *) 0; \ + } \ + (_d_list)->cnt--; \ + } + + +#define d_list_peek_head(_d_list) ((_d_list)->head) + + +#define d_list_peek_tail(_d_list) ((_d_list)->tail) + + +#define d_list_next_entry(_d_entry) ((_d_entry)->next) + +#define d_list_insert_entry(_d_list, _d_entry_prev, _d_entry_next, _d_entry) \ + if (_d_entry_prev == NULL ) \ + { \ + (_d_entry)->prev = (d_list_entry_t *) 0; \ + (_d_entry)->next = (_d_list)->head; \ + if((_d_list)->tail == (d_list_entry_t *) 0) \ + { \ + (_d_list)->tail = (_d_entry); \ + } \ + (_d_list)->head = (_d_entry); \ + (_d_list)->cnt++; \ + } \ + else if (_d_entry_next == NULL ) \ + { \ + (_d_entry)->next = (d_list_entry_t *) 0; \ + (_d_entry)->prev = (_d_list)->tail; \ + if((_d_list)->tail) \ + { \ + (_d_list)->tail->next = (_d_entry); \ + } \ + else \ + { \ + (_d_list)->head = (_d_entry); \ + } \ + (_d_list)->tail = (_d_entry); \ + (_d_list)->cnt++; \ + } \ + else \ + { \ + (_d_entry)->next = (_d_entry_next); \ + (_d_entry)->prev = (_d_entry_prev); \ + (_d_entry_prev)->next = (_d_entry); \ + (_d_entry_next)->prev = (_d_entry); \ + (_d_list)->cnt++; \ + } + +#define d_list_remove_entry(_d_list, _d_entry) \ + if((_d_list)->head == (_d_entry)) \ + { \ + if((_d_list)->head) \ + { \ + (_d_list)->head = (_d_list)->head->next; \ + if((_d_list)->head) \ + { \ + (_d_list)->head->prev = (d_list_entry_t *) 0; \ + } \ + else \ + { \ + (_d_list)->tail = (d_list_entry_t *) 0; \ + } \ + (_d_list)->cnt--; \ + } \ + } \ + else if((_d_list)->tail == (_d_entry)) \ + { \ + if((_d_list)->tail) \ + { \ + (_d_list)->tail = (_d_list)->tail->prev; \ + if((_d_list)->tail) \ + { \ + (_d_list)->tail->next = (d_list_entry_t *) 0; \ + } \ + else \ + { \ + (_d_list)->head = (d_list_entry_t *) 0; \ + } \ + (_d_list)->cnt--; \ + } \ + } \ + else \ + { \ + (_d_entry)->prev->next = (_d_entry)->next; \ + (_d_entry)->next->prev = (_d_entry)->prev; \ + (_d_list)->cnt--; \ + } + + +#define d_list_prev_entry(_d_entry) ((_d_entry)->prev) + + +#define d_list_entry_cnt(_d_list) ((_d_list)->cnt) + + +#define d_list_is_empty(_d_list) ((_d_list)->cnt == 0) + + +#define d_list_add_head(_d_list, _d_list_head) \ + (_d_list_head)->tail->next = (_d_list)->head; \ + if((_d_list)->head) \ + { \ + (_d_list)->head->prev = (_d_list_head)->tail; \ + } \ + else \ + { \ + (_d_list)->tail = (_d_list_head)->tail; \ + } \ + (_d_list)->head = (_d_list_head)->head; \ + (_d_list)->cnt += (_d_list_head)->cnt + + +#define d_list_add_tail(_d_list, _d_list_tail) \ + (_d_list_tail)->head->prev = (_d_list)->tail; \ + if((_d_list)->tail) \ + { \ + (_d_list)->tail->next = (_d_list_tail)->head; \ + } \ + else \ + { \ + (_d_list)->head = (_d_list_tail)->head; \ + } \ + (_d_list)->tail = (_d_list_tail)->tail; \ + (_d_list)->cnt += (_d_list_tail)->cnt + + +#endif + + + +/******************************************************************************* + * Array list. + ******************************************************************************/ + +typedef void *q_list_entry_t; + +typedef struct _q_list_t +{ + q_list_entry_t *head; + q_list_entry_t *tail; + unsigned long cnt; + + unsigned long max_cnt; + q_list_entry_t *first_entry_addr; + q_list_entry_t *last_entry_addr; +} q_list_t; + + + +#ifdef _INLINE_LISTQ_CALLS + + +__inline +void +q_list_init( + q_list_t *q_list, + q_list_entry_t q_list_arr[], + unsigned long max_cnt) +{ + q_list->max_cnt = max_cnt; + q_list->first_entry_addr = q_list_arr; + q_list->last_entry_addr = q_list_arr + (max_cnt-1); + + q_list->head = q_list->first_entry_addr; + q_list->tail = q_list->first_entry_addr; + q_list->cnt = 0; +} + + +__inline +void +q_list_clear( + q_list_t *q_list) +{ + q_list->head = q_list->first_entry_addr; + q_list->tail = q_list->first_entry_addr; + q_list->cnt = 0; +} + + +__inline +void +q_list_push_head( + q_list_t *q_list, + q_list_entry_t q_entry) +{ + if(q_list->cnt < q_list->max_cnt) + { + if(q_list->head == q_list->first_entry_addr) + { + q_list->head = q_list->last_entry_addr; + } + else + { + q_list->head--; + } + + *(q_list->head) = q_entry; + q_list->cnt++; + } +} + + +__inline +q_list_entry_t +q_list_pop_head( + q_list_t *q_list) +{ + q_list_entry_t q_entry; + + q_entry = q_list->cnt ? *q_list->head : (q_list_entry_t *) 0; + if(q_list->cnt) + { + if(q_list->head == q_list->last_entry_addr) + { + q_list->head = q_list->first_entry_addr; + } + else + { + q_list->head++; + } + + q_list->cnt--; + } + + return q_entry; +} + + +__inline +void +q_list_push_tail( + q_list_t *q_list, + q_list_entry_t q_entry) +{ + if(q_list->cnt < q_list->max_cnt) + { + *q_list->tail = q_entry; + if(q_list->tail == q_list->last_entry_addr) + { + q_list->tail = q_list->first_entry_addr; + } + else + { + q_list->tail++; + } + + q_list->cnt++; + } +} + + +__inline +q_list_entry_t +q_list_pop_tail( + q_list_t *q_list) +{ + q_list_entry_t q_entry; + + q_entry = q_list->cnt ? + (q_list->tail == q_list->first_entry_addr ? + *q_list->last_entry_addr : *(q_list->tail-1)) : + (q_list_entry_t *) 0; + + if(q_list->cnt) + { + if(q_list->tail == q_list->first_entry_addr) + { + q_list->tail = q_list->last_entry_addr; + } + else + { + q_list->tail--; + } + + q_list->cnt--; + } + + return q_entry; +} + + +__inline +q_list_entry_t +q_list_peek_head( + q_list_t *q_list) +{ + q_list_entry_t q_entry; + + q_entry = q_list->cnt ? *q_list->head : (q_list_entry_t *) 0; + + return q_entry; +} + + +__inline +q_list_entry_t +q_list_peek_tail( + q_list_t *q_list) +{ + q_list_entry_t q_entry; + + q_entry = q_list->cnt ? + (q_list->tail == q_list->first_entry_addr ? + *q_list->last_entry_addr : *(q_list->tail - 1)) : + (q_list_entry_t *) 0; + + return q_entry; +} + + +__inline +unsigned long +q_list_entry_cnt( + q_list_t *q_list) +{ + return q_list->cnt; +} + + +__inline +char +q_list_is_empty( + q_list_t *q_list) +{ + return q_list->cnt == 0; +} + + +__inline +char +q_list_is_full( + q_list_t *q_list) +{ + return q_list->cnt == q_list->max_cnt; +} + + +#else + + +#define q_list_init(_q_list, _q_list_arr, _max_cnt) \ + (_q_list)->max_cnt = (_max_cnt); \ + (_q_list)->first_entry_addr = (_q_list_arr); \ + (_q_list)->last_entry_addr = (_q_list_arr) + ((_max_cnt) - 1); \ + (_q_list)->head = (_q_list)->first_entry_addr; \ + (_q_list)->tail = (_q_list)->first_entry_addr; \ + (_q_list)->cnt = 0 + + +#define q_list_clear(_q_list) \ + (_q_list)->head = (_q_list)->first_entry_addr; \ + (_q_list)->tail = (_q_list)->first_entry_addr; \ + (_q_list)->cnt = 0 + + +#define q_list_push_head(_q_list, _q_entry) \ + if((_q_list)->cnt < (_q_list)->max_cnt) \ + { \ + if((_q_list)->head == (_q_list)->first_entry_addr) \ + { \ + (_q_list)->head = (_q_list)->last_entry_addr; \ + } \ + else \ + { \ + (_q_list)->head--; \ + } \ + *((_q_list)->head) = (_q_entry); \ + (_q_list)->cnt++; \ + } + + +#define q_list_pop_head(_q_list) \ + (_q_list)->cnt ? *(_q_list)->head : (q_list_entry_t *) 0; \ + if((_q_list)->cnt) \ + { \ + if((_q_list)->head == (_q_list)->last_entry_addr) \ + { \ + (_q_list)->head = (_q_list)->first_entry_addr; \ + } \ + else \ + { \ + (_q_list)->head++; \ + } \ + (_q_list)->cnt--; \ + } + + +#define q_list_push_tail(_q_list, _q_entry) \ + if((_q_list)->cnt < (_q_list)->max_cnt) \ + { \ + *(_q_list)->tail = (_q_entry); \ + if((_q_list)->tail == (_q_list)->last_entry_addr) \ + { \ + (_q_list)->tail = (_q_list)->first_entry_addr; \ + } \ + else \ + { \ + (_q_list)->tail++; \ + } \ + (_q_list)->cnt++; \ + } + + +#define q_list_pop_tail(_q_list) \ + (_q_list)->cnt ? ((_q_list)->tail == (_q_list)->first_entry_addr ? \ + *(_q_list)->last_entry_addr : *((_q_list)->tail-1)) : \ + (q_list_entry_t *) 0; \ + if((_q_list)->cnt) \ + { \ + if((_q_list)->tail == (_q_list)->first_entry_addr) \ + { \ + (_q_list)->tail = (_q_list)->last_entry_addr; \ + } \ + else \ + { \ + (_q_list)->tail--; \ + } \ + (_q_list)->cnt--; \ + } \ + + +#define q_list_peek_head(_q_list) \ + ((_q_list)->cnt ? *(_q_list)->head : (q_list_entry_t *) 0) + + +#define q_list_peek_tail(_q_list) \ + ((_q_list)->cnt ? ((_q_list)->tail == (_q_list)->first_entry_addr ? \ + *(_q_list)->last_entry_addr : *((_q_list)->tail - 1)) : \ + (q_list_entry_t *) 0) + + +#define q_list_entry_cnt(_q_list) ((_q_list)->cnt) + + +#define q_list_is_empty(_q_list) ((_q_list)->cnt == 0) + + +#define q_list_is_full(_q_list) ((_q_list)->cnt == (_q_list)->max_cnt) + + +#endif + + + + +#endif /* _listq_h_ */ + diff --git a/usr/src/uts/common/io/bnx/include/lm_defs.h b/usr/src/uts/common/io/bnx/include/lm_defs.h new file mode 100644 index 0000000000..71b7c78b46 --- /dev/null +++ b/usr/src/uts/common/io/bnx/include/lm_defs.h @@ -0,0 +1,827 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _LM_DEFS_H +#define _LM_DEFS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtype.h" + +/* + * Simple constants. + */ + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef NULL +#define NULL ((void *) 0) +#endif + + +/* Signatures for integrity checks. */ +#define LM_DEVICE_SIG 0x6d635242 /* BRcm */ +#define L2PACKET_RX_SIG 0x7872324c /* L2rx */ +#define L2PACKET_TX_SIG 0x7874324c /* L2tx */ +#define L4BUFFER_RX_SIG 0x7872344c /* L4rx */ +#define L4BUFFER_TX_SIG 0x7874344c /* L4tx */ +#define L4BUFFER_SIG 0x66754254 /* TBuf */ +#define L4GEN_BUFFER_SIG 0x006e6567 /* gen */ +#define L4GEN_BUFFER_SIG_END 0x0067656e /* neg */ + +#define SIZEOF_SIG 16 +#define SIG(_p) (*((u32_t *)((u8_t *)(_p) - sizeof (u32_t)))) +#define END_SIG(_p, _size) (*((u32_t *)((u8_t *)(_p) + (_size)))) + +/* + * This macro rounds the given value to the next word boundary if it + * is not already at a word boundary. + */ +#define ALIGN_VALUE_TO_WORD_BOUNDARY(_v) \ + (((_v) + (sizeof (void *) - 1)) & ~(sizeof (void *) - 1)) + +/* + * This macro determines the delta to the next alignment which is + * either 1, 2, 4, 8, 16, 32, etc. + */ +#define ALIGN_DELTA_TO_BOUNDARY(_p, _a) \ + (((((u8_t *)(_p) - (u8_t *)0) + ((_a) - 1)) & ~((_a) - 1)) - \ + ((u8_t *)(_p) - (u8_t *)0)) + +/* + * This macro returns the pointer to the next alignment if the pointer + * is not currently on the indicated alignment boundary. + */ +#define ALIGN_PTR_TO_BOUNDARY(_p, _a) \ + ((u8_t *)(_p) + ALIGN_DELTA_TO_BOUNDARY(_p, _a)) + + + +/* + * Status codes. + */ + +typedef enum +{ + LM_STATUS_SUCCESS = 0, + LM_STATUS_LINK_UNKNOWN = 0, + LM_STATUS_FAILURE = 1, + LM_STATUS_RESOURCE = 2, + LM_STATUS_ABORTED = 3, + LM_STATUS_PENDING = 4, + LM_STATUS_PAUSED = 5, + LM_STATUS_INVALID_PARAMETER = 6, + LM_STATUS_LINK_ACTIVE = 7, + LM_STATUS_LINK_DOWN = 8, + LM_STATUS_UNKNOWN_ADAPTER = 9, + LM_STATUS_UNKNOWN_PHY = 10, + LM_STATUS_UNKNOWN_MEDIUM = 11, + LM_STATUS_TOO_MANY_FRAGMENTS = 12, + LM_STATUS_BUFFER_TOO_SHORT = 16, + LM_STATUS_UPLOAD_IN_PROGRESS = 17, + LM_STATUS_BUSY = 18, + LM_STATUS_INVALID_KEY = 19, + LM_STATUS_TIMEOUT = 20, + LM_STATUS_REQUEST_NOT_ACCEPTED = 21, + LM_STATUS_CONNECTION_CLOSED = 22, + LM_STATUS_BAD_SIGNATURE = 23, + LM_STATUS_CONNECTION_RESET = 24, + LM_STATUS_EXISTING_OBJECT = 25, + LM_STATUS_OBJECT_NOT_FOUND = 26, + LM_STATUS_CONNECTION_RM_DISC = 27, + LM_STATUS_VF_LAMAC_REJECTED = 28, + LM_STATUS_NOT_IMPLEMENTED = 29, + LM_STATUS_UNKNOWN_EVENT_CODE = 30 +} lm_status_t; + + +/* + * Receive filter masks. + */ + +typedef u32_t lm_rx_mask_t; + +#define LM_RX_MASK_ACCEPT_NONE 0x0000 +#define LM_RX_MASK_ACCEPT_UNICAST 0x0001 +#define LM_RX_MASK_ACCEPT_MULTICAST 0x0002 +#define LM_RX_MASK_ACCEPT_ALL_MULTICAST 0x0004 +#define LM_RX_MASK_ACCEPT_BROADCAST 0x0008 +#define LM_RX_MASK_ACCEPT_ERROR_PACKET 0x0010 + +#define LM_RX_MASK_PROMISCUOUS_MODE 0x10000 + + + +/* + * Flow control. + */ + +typedef u32_t lm_flow_control_t; + +#define LM_FLOW_CONTROL_NONE 0x00 +#define LM_FLOW_CONTROL_RECEIVE_PAUSE 0x01 +#define LM_FLOW_CONTROL_TRANSMIT_PAUSE 0x02 + +/* + * This value can be or-ed with RECEIVE_PAUSE and TRANSMIT_PAUSE. If the + * auto-negotiation is disabled and the RECEIVE_PAUSE and TRANSMIT_PAUSE bits + * are set, then flow control is enabled regardless of link partner's flow + * control capability. Otherwise, if this bit is set, then flow is negotiated + * with the link partner. Values 0x80000000 and 0x80000003 are equivalent. + */ +#define LM_FLOW_CONTROL_AUTO_PAUSE 0x80000000 + + +/* + * EEE control. + */ + +/* + * values match the registry values for EeeCtrlMode . Default is MED + * ("Balanced") + */ +typedef enum +{ + LM_EEE_CONTROL_HIGH = 0, // MaxPowerSave + LM_EEE_CONTROL_MED = 1, // Balance + LM_EEE_CONTROL_LOW = 2, // MaxPreformance + LM_EEE_CONTROL_NVRAM = 3, // use NVRAM + LM_EEE_CONTROL_NA = 4 // either N/A or disabled +} lm_eee_policy_t; + +/* + * media type. + */ + +typedef u32_t lm_medium_t; + +#define LM_MEDIUM_AUTO_DETECT 0x0000 + +#define LM_MEDIUM_TYPE_UNKNOWN 0x0000 +#define LM_MEDIUM_TYPE_BNC 0x0001 +#define LM_MEDIUM_TYPE_UTP 0x0002 +#define LM_MEDIUM_TYPE_FIBER 0x0003 +#define LM_MEDIUM_TYPE_SERDES 0x0004 +#define LM_MEDIUM_TYPE_SERDES_SGMII 0x0005 +#define LM_MEDIUM_TYPE_XGXS 0x0006 +#define LM_MEDIUM_TYPE_XGXS_SGMII 0x0007 +#define LM_MEDIUM_TYPE_XMAC_LOOPBACK 0x0008 +#define LM_MEDIUM_TYPE_UMAC_LOOPBACK 0x0009 +#define LM_MEDIUM_TYPE_EXT_LOOPBACK 0x00f6 +#define LM_MEDIUM_TYPE_EXT_PHY_LOOPBACK 0x00f7 +#define LM_MEDIUM_TYPE_SERDES_LOOPBACK 0x00f8 +#define LM_MEDIUM_TYPE_XGXS_LOOPBACK 0x00f9 +#define LM_MEDIUM_TYPE_XGXS_10_LOOPBACK 0x00fa +#define LM_MEDIUM_TYPE_BMAC_LOOPBACK 0x00fb +#define LM_MEDIUM_TYPE_EMAC_LOOPBACK 0x00fc +#define LM_MEDIUM_TYPE_PHY_LOOPBACK 0x00fd +#define LM_MEDIUM_TYPE_MAC_LOOPBACK 0x00fe +#define LM_MEDIUM_TYPE_NULL 0x00ff +#define LM_MEDIUM_TYPE_MASK 0x00ff +#define GET_MEDIUM_TYPE(m) ((m) & LM_MEDIUM_TYPE_MASK) +#define SET_MEDIUM_TYPE(m, t) \ + (m) = ((m) & ~LM_MEDIUM_TYPE_MASK) | (t) + +#define LM_MEDIUM_IS_LOOPBACK(_medium) \ + (((GET_MEDIUM_TYPE(_medium)) == LM_MEDIUM_TYPE_BMAC_LOOPBACK) || \ + ((GET_MEDIUM_TYPE(_medium)) == LM_MEDIUM_TYPE_UMAC_LOOPBACK) || \ + ((GET_MEDIUM_TYPE(_medium)) == LM_MEDIUM_TYPE_XMAC_LOOPBACK) || \ + ((GET_MEDIUM_TYPE(_medium)) == LM_MEDIUM_TYPE_EXT_LOOPBACK) || \ + ((GET_MEDIUM_TYPE(_medium)) == LM_MEDIUM_TYPE_EXT_PHY_LOOPBACK) || \ + ((GET_MEDIUM_TYPE(_medium)) == LM_MEDIUM_TYPE_SERDES_LOOPBACK) || \ + ((GET_MEDIUM_TYPE(_medium)) == LM_MEDIUM_TYPE_XGXS_LOOPBACK) || \ + ((GET_MEDIUM_TYPE(_medium)) == LM_MEDIUM_TYPE_XGXS_10_LOOPBACK) || \ + ((GET_MEDIUM_TYPE(_medium)) == LM_MEDIUM_TYPE_PHY_LOOPBACK) || \ + ((GET_MEDIUM_TYPE(_medium)) == LM_MEDIUM_TYPE_MAC_LOOPBACK)) + +#define LM_MEDIUM_SPEED_AUTONEG 0x0000 + +#define LM_MEDIUM_SPEED_UNKNOWN 0x0000 +#define LM_MEDIUM_SPEED_10MBPS 0x0100 +#define LM_MEDIUM_SPEED_100MBPS 0x0200 +#define LM_MEDIUM_SPEED_1000MBPS 0x0300 +#define LM_MEDIUM_SPEED_2500MBPS 0x0400 +#define LM_MEDIUM_SPEED_10GBPS 0x0600 +#define LM_MEDIUM_SPEED_12GBPS 0x0700 +#define LM_MEDIUM_SPEED_12_5GBPS 0x0800 +#define LM_MEDIUM_SPEED_13GBPS 0x0900 +#define LM_MEDIUM_SPEED_15GBPS 0x0a00 +#define LM_MEDIUM_SPEED_16GBPS 0x0b00 +#define LM_MEDIUM_SPEED_20GBPS 0x0c00 +#define LM_MEDIUM_SPEED_25GBPS 0x0d00 +#define LM_MEDIUM_SPEED_40GBPS 0x0e00 +#define LM_MEDIUM_SPEED_50GBPS 0x0f00 +#define LM_MEDIUM_SPEED_SEQ_START 0x1d00 // 100Mbps +#define LM_MEDIUM_SPEED_SEQ_END 0xE400 // 20Gbps +#define LM_MEDIUM_SPEED_AUTONEG_1G_FALLBACK 0xFD00 /* Serdes */ +#define LM_MEDIUM_SPEED_AUTONEG_2_5G_FALLBACK 0xFE00 /* Serdes */ +#define LM_MEDIUM_SPEED_HARDWARE_DEFAULT 0xff00 /* Serdes nvram def. */ +#define LM_MEDIUM_SPEED_MASK 0xff00 +#define GET_MEDIUM_SPEED(m) ((m) & LM_MEDIUM_SPEED_MASK) +#define SET_MEDIUM_SPEED(m, s) \ + (m) = ((m) & ~LM_MEDIUM_SPEED_MASK) | (s) + +#define LM_MEDIUM_FULL_DUPLEX 0x00000 +#define LM_MEDIUM_HALF_DUPLEX 0x10000 +#define GET_MEDIUM_DUPLEX(m) ((m) & LM_MEDIUM_HALF_DUPLEX) +#define SET_MEDIUM_DUPLEX(m, d) \ + (m) = ((m) & ~LM_MEDIUM_HALF_DUPLEX) | (d) + +#define LM_MEDIUM_SELECTIVE_AUTONEG 0x01000000 +#define GET_MEDIUM_AUTONEG_MODE(m) ((m) & 0xff000000) + +typedef struct _lm_link_settings_t +{ + u32_t flag; +#define LINK_FLAG_SELECTIVE_AUTONEG_MASK 0x0f +#define LINK_FLAG_SELECTIVE_AUTONEG_ONE_SPEED 0x01 +#define LINK_FLAG_SELECTIVE_AUTONEG_ENABLE_SLOWER_SPEEDS 0x02 +#define LINK_FLAG_WIRE_SPEED 0x10 + + lm_medium_t req_medium; + lm_flow_control_t flow_ctrl; + + u32_t _reserved; +} lm_link_settings_t; + + + +/* + * Power state. + */ + +typedef enum +{ + LM_POWER_STATE_D0 = 0, + LM_POWER_STATE_D1 = 1, + LM_POWER_STATE_D2 = 2, + LM_POWER_STATE_D3 = 3 +} lm_power_state_t; + + + +/* + * offloading. + */ + +typedef u32_t lm_offload_t; + +#define LM_OFFLOAD_NONE 0x00000000 +#define LM_OFFLOAD_TX_IP_CKSUM 0x00000001 +#define LM_OFFLOAD_RX_IP_CKSUM 0x00000002 +#define LM_OFFLOAD_TX_TCP_CKSUM 0x00000004 +#define LM_OFFLOAD_RX_TCP_CKSUM 0x00000008 +#define LM_OFFLOAD_TX_UDP_CKSUM 0x00000010 +#define LM_OFFLOAD_RX_UDP_CKSUM 0x00000020 +#define LM_OFFLOAD_IPV4_TCP_LSO 0x00000040 +#define LM_OFFLOAD_IPV6_TCP_LSO 0x00000080 +#define LM_OFFLOAD_CHIMNEY 0x00000100 +#define LM_OFFLOAD_IPV6_CHIMNEY 0x00000200 +#define LM_OFFLOAD_TX_TCP6_CKSUM 0x00001000 +#define LM_OFFLOAD_RX_TCP6_CKSUM 0x00002000 +#define LM_OFFLOAD_TX_UDP6_CKSUM 0x00004000 +#define LM_OFFLOAD_RX_UDP6_CKSUM 0x00008000 +#define LM_OFFLOAD_RSC_IPV4 0x00010000 +#define LM_OFFLOAD_RSC_IPV6 0x00020000 +#define LM_OFFLOAD_ENCAP_PACKET 0x00040000 + + + +/* + * RSS Hash Types + */ + +typedef u32_t lm_rss_hash_t; + +#define LM_RSS_HASH_IPV4 0x00000100 +#define LM_RSS_HASH_TCP_IPV4 0x00000200 +#define LM_RSS_HASH_IPV6 0x00000400 +#define LM_RSS_HASH_IPV6_EX 0x00000800 +#define LM_RSS_HASH_TCP_IPV6 0x00001000 +#define LM_RSS_HASH_TCP_IPV6_EX 0x00002000 + + + +/* + * Chip reset reasons. + */ + +typedef enum +{ + LM_REASON_NONE = 0, + LM_REASON_DRIVER_RESET = 1, + LM_REASON_DRIVER_UNLOAD = 2, + LM_REASON_DRIVER_SHUTDOWN = 3, + LM_REASON_WOL_SUSPEND = 4, + LM_REASON_NO_WOL_SUSPEND = 5, + LM_REASON_DIAG = 6, + /* Power down phy/serdes */ + LM_REASON_DRIVER_UNLOAD_POWER_DOWN = 7, + LM_REASON_ERROR_RECOVERY = 8 +} lm_reason_t; + + + +/* + * Wake up mode. + */ + +typedef u32_t lm_wake_up_mode_t; + +#define LM_WAKE_UP_MODE_NONE 0 +#define LM_WAKE_UP_MODE_MAGIC_PACKET 1 +#define LM_WAKE_UP_MODE_NWUF 2 +#define LM_WAKE_UP_MODE_LINK_CHANGE 4 + + + +/* + * Event code. + */ +typedef enum +{ + LM_EVENT_CODE_LINK_CHANGE = 0, + LM_EVENT_CODE_PAUSE_OFFLOAD = 1, + LM_EVENT_CODE_RESUME_OFFLOAD = 2, + /* For Error Recovery Flow */ + LM_EVENT_CODE_STOP_CHIP_ACCESS = 3, + /* For Error Recovery Flow */ + LM_EVENT_CODE_RESTART_CHIP_ACCESS = 4, + LM_EVENT_CODE_UPLOAD_ALL = 5, + LM_EVENT_CODE_DCBX_OPERA_CHANGE = 6, + LM_EVENT_CODE_DCBX_REMOTE_CHANGE = 7, + LM_EVENT_CODE_INVALIDATE_VF_BLOCK = 8, +} lm_event_code_t; + + +/* + * Transmit control flags. + */ + +typedef u32_t lm_tx_flag_t; + +#define LM_TX_FLAG_INSERT_VLAN_TAG 0x01 +#define LM_TX_FLAG_COMPUTE_IP_CKSUM 0x02 +#define LM_TX_FLAG_COMPUTE_TCP_UDP_CKSUM 0x04 +#define LM_TX_FLAG_TCP_LSO_FRAME 0x08 +#define LM_TX_FLAG_TCP_LSO_SNAP_FRAME 0x10 +#define LM_TX_FLAG_COAL_NOW 0x20 +#define LM_TX_FLAG_DONT_COMPUTE_CRC 0x40 +#define LM_TX_FLAG_SKIP_MBQ_WRITE 0x80 +#define LM_TX_FLAG_IPV6_PACKET 0x100 +#define LM_TX_FLAG_VLAN_TAG_EXISTS 0x200 +/* + * If this flag is set, the firmware will ignore global + * configuration (except Outer VLAN)and will handle inner Vlan + * only according to driver instructions on the bd: + * 1. LM_TX_FLAG_VLAN_TAG_EXISTS. + * 2. LM_TX_FLAG_INSERT_VLAN_TAG. + * Note that if set the firmware will not handle default vlan / + * NIV tag / DCB. + */ +#define LM_TX_FLAG_FORCE_VLAN_MODE 0x400 +/* Encapsulated packet offload flags. */ +#define LM_TX_FLAG_IS_ENCAP_PACKET 0x800 +#define LM_TX_FLAG_ENCAP_PACKET_IS_INNER_IPV6 0x1000 + +typedef struct _lm_pkt_tx_info_t +{ + lm_tx_flag_t flags; + + u16_t vlan_tag; + u16_t lso_mss; + u16_t lso_ip_hdr_len; + u16_t lso_tcp_hdr_len; + u32_t lso_payload_len; + + /* Everest only fields. */ + u32_t lso_tcp_send_seq; + u16_t lso_ipid; + u16_t tcp_pseudo_csum; + u8_t lso_tcp_flags; + u8_t tcp_nonce_sum_bit; + u16_t fw_ip_csum; + + u8_t dst_mac_addr[8]; + s8_t cs_any_offset; + u8_t src_mac_addr[8]; + u8_t _unused1; + u8_t eth_type[4]; + + /* + * Encapsulated packet offsets. These fields are only valid when + * LM_TX_FLAG_IS_ENCAP_PACKET is set. + */ + u8_t encap_packet_inner_frame_offset; + u8_t encap_packet_inner_ip_relative_offset; + u16_t encap_packet_inner_tcp_relative_offset; +} lm_pkt_tx_info_t; + + + +/* + * Receive control flags. + */ + +typedef u32_t lm_rx_flag_t; + +#define LM_RX_FLAG_VALID_VLAN_TAG 0x00000001 +#define LM_RX_FLAG_VALID_HASH_VALUE 0x00000010 + +#define LM_RX_FLAG_IS_IPV4_DATAGRAM 0x00000100 +#define LM_RX_FLAG_IS_IPV6_DATAGRAM 0x00000200 +#define LM_RX_FLAG_IP_CKSUM_IS_GOOD 0x00000400 +#define LM_RX_FLAG_IP_CKSUM_IS_BAD 0x00000800 + +#define LM_RX_FLAG_IS_UDP_DATAGRAM 0x00001000 +#define LM_RX_FLAG_UDP_CKSUM_IS_GOOD 0x00002000 +#define LM_RX_FLAG_UDP_CKSUM_IS_BAD 0x00004000 + +#define LM_RX_FLAG_IS_TCP_SEGMENT 0x00010000 +#define LM_RX_FLAG_TCP_CKSUM_IS_GOOD 0x00020000 +#define LM_RX_FLAG_TCP_CKSUM_IS_BAD 0x00040000 +#define LM_RX_FLAG_START_RSC_TPA 0x00080000 + +#define LM_RX_FLAG_HASH_TYPE_IPV4 0x00100000 +#define LM_RX_FLAG_HASH_TYPE_TCP_IPV4 0x00200000 +#define LM_RX_FLAG_HASH_TYPE_IPV6 0x00400000 +#define LM_RX_FLAG_HASH_TYPE_TCP_IPV6 0x00800000 +#define LM_RX_FLAG_HASH_TYPE_MASK 0x00f00000 + +typedef struct _lm_pkt_rx_info_t +{ + lm_rx_flag_t flags; + + u32_t size; + + u16_t vlan_tag; + u16_t _pad; + + /* + * Virtual address corresponding to the first byte of the first SGL + * entry. This is the starting location of the packet which may begin + * with some control information. + */ + u8_t *mem_virt; + u32_t mem_size; + + /* these fields only valid when LM_RX_FLAG_START_RSC_TPA is set */ + u16_t coal_seg_cnt; + u16_t dup_ack_cnt; + u32_t ts_delta; /* valid when timestamp is enabled */ + /* + * if the packet is RSC, this field will hold the total size of the + * RSC SCU + */ + u32_t total_packet_size; + + u32_t unused; +} lm_pkt_rx_info_t; + + + +/* + * various type of counters. + */ + +typedef enum +{ + LM_STATS_BASE = 0x686b3000, + LM_STATS_FRAMES_XMITTED_OK = 0x686b3001, + LM_STATS_FRAMES_RECEIVED_OK = 0x686b3002, + LM_STATS_ERRORED_TRANSMIT_CNT = 0x686b3003, + LM_STATS_ERRORED_RECEIVE_CNT = 0x686b3004, + LM_STATS_RCV_CRC_ERROR = 0x686b3005, + LM_STATS_ALIGNMENT_ERROR = 0x686b3006, + LM_STATS_SINGLE_COLLISION_FRAMES = 0x686b3007, + LM_STATS_MULTIPLE_COLLISION_FRAMES = 0x686b3008, + LM_STATS_FRAMES_DEFERRED = 0x686b3009, + LM_STATS_MAX_COLLISIONS = 0x686b300a, + LM_STATS_RCV_OVERRUN = 0x686b300b, + LM_STATS_XMIT_UNDERRUN = 0x686b300c, + LM_STATS_UNICAST_FRAMES_XMIT = 0x686b300d, + LM_STATS_MULTICAST_FRAMES_XMIT = 0x686b300e, + LM_STATS_BROADCAST_FRAMES_XMIT = 0x686b300f, + LM_STATS_UNICAST_FRAMES_RCV = 0x686b3010, + LM_STATS_MULTICAST_FRAMES_RCV = 0x686b3011, + LM_STATS_BROADCAST_FRAMES_RCV = 0x686b3012, + LM_STATS_RCV_NO_BUFFER_DROP = 0x686b3013, + LM_STATS_BYTES_RCV = 0x686b3014, + LM_STATS_BYTES_XMIT = 0x686b3015, + LM_STATS_IP4_OFFLOAD = 0x686b3016, + LM_STATS_TCP_OFFLOAD = 0x686b3017, + LM_STATS_IF_IN_DISCARDS = 0x686b3018, + LM_STATS_IF_IN_ERRORS = 0x686b3019, + LM_STATS_IF_OUT_ERRORS = 0x686b301a, + LM_STATS_IP6_OFFLOAD = 0x686b301b, + LM_STATS_TCP6_OFFLOAD = 0x686b301c, + LM_STATS_XMIT_DISCARDS = 0x686b301d, + LM_STATS_DIRECTED_BYTES_RCV = 0x686b301e, + LM_STATS_MULTICAST_BYTES_RCV = 0x686b301f, + LM_STATS_BROADCAST_BYTES_RCV = 0x686b3020, + LM_STATS_DIRECTED_BYTES_XMIT = 0x686b3021, + LM_STATS_MULTICAST_BYTES_XMIT = 0x686b3022, + LM_STATS_BROADCAST_BYTES_XMIT = 0x686b3023, +} lm_stats_t; + +#define NUM_OF_LM_STATS 36 + + +/* + * 64-bit value. + */ + +typedef union _lm_u64_t +{ + struct _lm_u64_as_u32_t + { +#ifdef BIG_ENDIAN_HOST + u32_t high; + u32_t low; +#else + u32_t low; + u32_t high; +#endif + } as_u32; + + u64_t as_u64; + + void *as_ptr; +} lm_u64_t; + + +typedef lm_u64_t lm_address_t; + + +/* 64-bit increment. The second argument is a 32-bit value. */ +#define LM_INC64(result, addend32) \ + { \ + u32_t low; \ + \ + low = (result)->as_u32.low; \ + (result)->as_u32.low += (addend32); \ + if ((result)->as_u32.low < low) \ + { \ + (result)->as_u32.high++; \ + } \ + } + + +/* 64-bit decrement. The second argument is a 32-bit value. */ +#define LM_DEC64(result, addend32) \ + { \ + u32_t low; \ + \ + low = (result)->as_u32.low; \ + (result)->as_u32.low -= (addend32); \ + if ((result)->as_u32.low > low) \ + { \ + (result)->as_u32.high--; \ + } \ + } + +/* + * IP4 and TCP offload stats. + */ + +typedef struct _lm_ip4_offload_stats_t +{ + u64_t in_receives; + u64_t in_delivers; + u64_t out_requests; + u32_t in_header_errors; + u32_t in_discards; + u32_t out_discards; + u32_t out_no_routes; + + u32_t _pad[8]; +} lm_ip4_offload_stats_t; + + +typedef struct _lm_tcp_offload_stats_t +{ + u64_t in_segments; + u64_t out_segments; + u32_t retran_segments; + u32_t in_errors; + u32_t out_resets; + + u32_t _pad[8]; +} lm_tcp_offload_stats_t; + + + +/* + * Host to network order conversion. + */ + +#ifdef BIG_ENDIAN_HOST + +#ifndef HTON16 +#define HTON16(_val16) (_val16) +#endif +#ifndef HTON32 +#define HTON32(_val32) (_val32) +#ifndef NTOH16 +#endif +#define NTOH16(_val16) (_val16) +#endif +#ifndef NTOH32 +#define NTOH32(_val32) (_val32) +#endif + +#else + +#ifndef HTON16 +#define HTON16(_val16) (((_val16 & 0xff00) >> 8) | ((_val16 & 0xff) << 8)) +#endif +#ifndef HTON32 +#define HTON32(_val32) ((HTON16(_val32) << 16) | (HTON16(_val32 >> 16))) +#endif +#ifndef NTOH16 +#define NTOH16(_val16) HTON16(_val16) +#endif +#ifndef NTOH32 +#define NTOH32(_val32) HTON32(_val32) +#endif + +#endif + + + +/* + * Fragment structure. + */ + +typedef struct _lm_frag_t +{ + lm_address_t addr; + u32_t size; + u32_t _reserved; +} lm_frag_t; + +typedef struct _lm_frag_list_t +{ + u32_t cnt; + u32_t size; + + lm_frag_t frag_arr[1]; +} lm_frag_list_t; + +/* a macro for declaring 'lm_frag_list_t' with various array sizes. */ +#define DECLARE_FRAG_LIST_BUFFER_TYPE(_FRAG_LIST_TYPE_NAME, _MAX_FRAG_CNT) \ + typedef struct _##_FRAG_LIST_TYPE_NAME \ + { \ + lm_frag_list_t list; \ + lm_frag_t frag_arr[_MAX_FRAG_CNT-1]; \ + } _FRAG_LIST_TYPE_NAME + +/* + * DCBX indicate event parameters. + */ +typedef enum _dcb_condition_selector_t +{ + DCB_CONDITION_RESERVED, + DCB_CONDITION_DEFAULT, + DCB_CONDITION_TCP_PORT, + DCB_CONDITION_UDP_PORT, + DCB_CONDITION_TCP_OR_UDP_PORT, + DCB_CONDITION_ETHERTYPE, + DCB_CONDITION_NETDIRECT_PORT, + DCB_CONDITION_MAX, +}dcb_condition_selector_t; + +typedef enum _action_selector_t +{ + DCB_ACTION_PRIORITY, + DCB_ACTION_MAX, +} action_selector_t; + +typedef struct _dcb_classif_elem_t +{ + u32_t flags; +#define DCB_CLASSIF_ENFORCED_BY_VBD 0x1 + dcb_condition_selector_t condition_selector; + u16_t condition_field; + action_selector_t action_selector; + u16_t action_field; +}dcb_classif_elem_t; + +typedef enum _dcb_classif_version_t +{ + DCB_CLASSIFI_VER_SIMPLE_ELEM, + DCB_CLASSIFI_VER_SIMPLE_ELEM_MAX, +}dcb_classif_version_t; + +typedef struct _dcb_classif_params_t +{ + u16_t num_classif_elements; + u16_t _pad; + dcb_classif_version_t classif_version; + void *classif_table; +}dcb_classif_params_t; + +typedef struct _dcb_pfc_param_t +{ + u32_t pfc_enable; +#define DCB_PFC_MAX_BIT_ENABLE_MASK (0xFF) +}dcb_pfc_param_t; + +typedef enum _tsa_assignment +{ + TSA_ASSIGNMENT_DCB_TSA_STRICT, + TSA_ASSIGNMENT_DCB_TSA_CBS, + TSA_ASSIGNMENT_DCB_TSA_ETS, +} tsa_assignment; + +typedef struct _dcb_ets_tsa_param_t +{ + u32_t num_traffic_classes; + u8_t priority_assignment_table[8]; + u8_t tc_bw_assignment_table[8]; + tsa_assignment tsa_assignment_table[8]; +} dcb_ets_tsa_param_t; + +typedef struct _dcb_indicate_event_params_t +{ + u32_t flags; +#define DCB_PARAMS_ETS_ENABLED 0x00000001 +#define DCB_PARAMS_ETS_CHANGED 0x00000002 +#define DCB_PARAMS_PFC_ENABLED 0x00000004 +#define DCB_PARAMS_PFC_CHANGED 0x00000008 +#define DCB_PARAMS_CLASSIF_ENABLED 0x00000020 +#define DCB_PARAMS_CLASSIF_CHANGED 0x00000040 +#define DCB_PARAMS_WILLING 0x00000080 + + dcb_ets_tsa_param_t ets_params; + dcb_pfc_param_t pfc_params; + dcb_classif_params_t classif_params; + u32_t reserved[4]; +} dcb_indicate_event_params_t; + +/* + * Macro fore calculating the address of the base of the structure given its + * type, and an address of a field within the structure. + */ + +#define GET_CONTAINING_RECORD(address, type, field) \ + ((type *)((u8_t *)(address) - (u8_t *)(&((type *)0)->field))) + + + +/* + * Simple macros. + */ + +#define IS_ETH_BROADCAST(eth_addr) \ + (((unsigned char *) (eth_addr))[0] == ((unsigned char) 0xff)) + +#define IS_ETH_MULTICAST(eth_addr) \ + (((unsigned char *) (eth_addr))[0] & ((unsigned char) 0x01)) + +#define IS_ETH_ADDRESS_EQUAL(eth_addr1, eth_addr2) \ + ((((unsigned char *) (eth_addr1))[0] == \ + ((unsigned char *) (eth_addr2))[0]) && \ + (((unsigned char *) (eth_addr1))[1] == \ + ((unsigned char *) (eth_addr2))[1]) && \ + (((unsigned char *) (eth_addr1))[2] == \ + ((unsigned char *) (eth_addr2))[2]) && \ + (((unsigned char *) (eth_addr1))[3] == \ + ((unsigned char *) (eth_addr2))[3]) && \ + (((unsigned char *) (eth_addr1))[4] == \ + ((unsigned char *) (eth_addr2))[4]) && \ + (((unsigned char *) (eth_addr1))[5] == \ + ((unsigned char *) (eth_addr2))[5])) + +#define COPY_ETH_ADDRESS(src, dst) \ + ((unsigned char *) (dst))[0] = ((unsigned char *) (src))[0]; \ + ((unsigned char *) (dst))[1] = ((unsigned char *) (src))[1]; \ + ((unsigned char *) (dst))[2] = ((unsigned char *) (src))[2]; \ + ((unsigned char *) (dst))[3] = ((unsigned char *) (src))[3]; \ + ((unsigned char *) (dst))[4] = ((unsigned char *) (src))[4]; \ + ((unsigned char *) (dst))[5] = ((unsigned char *) (src))[5]; + +#ifdef __cplusplus +} +#endif + +#endif /* _LM_DEFS_H */ diff --git a/usr/src/uts/common/io/bnx/lm_desc.h b/usr/src/uts/common/io/bnx/lm_desc.h new file mode 100644 index 0000000000..a037f3ea98 --- /dev/null +++ b/usr/src/uts/common/io/bnx/lm_desc.h @@ -0,0 +1,45 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved. + */ + +#ifndef _LM_DESC_H +#define _LM_DESC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* driver version. */ +#define LM_DRIVER_MAJOR_VER 7 +#define LM_DRIVER_MINOR_VER 0 +#define LM_DRIVER_REL_NUM 1 +#define LM_DRIVER_FIX_NUM 0 + +/* major product release version which corresponds to T2.8, T3.0, etc. */ +#define LM_PRODUCT_MAJOR_VER 16 +#define LM_PRODUCT_MINOR_VER 0 +#define LM_PRODUCT_FIX_NUM 0 + +#define LM_COMPANY_NAME_STR "QLogic Corporation" +#define LM_COPYRIGHT_STR "Copyright 2014 QLogic Corporation" +#define LM_PRODUCT_NAME_STR "QLogic 570x/571x GigE" + +#ifdef __cplusplus +} +#endif + +#endif /* _LM_DESC_H */ diff --git a/usr/src/uts/common/io/bnx/mm.h b/usr/src/uts/common/io/bnx/mm.h new file mode 100644 index 0000000000..a93c1e725f --- /dev/null +++ b/usr/src/uts/common/io/bnx/mm.h @@ -0,0 +1,45 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved. + */ + +#ifndef _MM_H_ +#define _MM_H_ + +#include "bnx_mm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Add some preprocessor definitions that + * should technically be part of the LM. + */ +#define LM_HC_RX_QUICK_CONS_TRIP_VAL_MAX 256 +#define LM_HC_RX_QUICK_CONS_TRIP_INT_MAX 256 + +#define LM_HC_RX_TICKS_VAL_MAX 511 +#define LM_HC_RX_TICKS_INT_MAX 1023 + + +#define mm_indicate_rx(a, b, c, d) + +#ifdef __cplusplus +} +#endif + +#endif /* _MM_H_ */ diff --git a/usr/src/uts/common/io/bnx/version.h b/usr/src/uts/common/io/bnx/version.h new file mode 100644 index 0000000000..ad8b8f0fe6 --- /dev/null +++ b/usr/src/uts/common/io/bnx/version.h @@ -0,0 +1,30 @@ +/* + * Copyright 2014-2017 Cavium, Inc. + * The contents of this file are subject to the terms of the Common Development + * and Distribution License, v.1, (the "License"). + * + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the License at available + * at http://opensource.org/licenses/CDDL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _VERSION_H +#define _VERSION_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAJVERSION 7 +#define MINVERSION 10 +#define REVVERSION 4 + +#ifdef __cplusplus +} +#endif + +#endif /* _VERSION_H */ diff --git a/usr/src/uts/common/io/bofi.c b/usr/src/uts/common/io/bofi.c index dc52302851..903e3339e6 100644 --- a/usr/src/uts/common/io/bofi.c +++ b/usr/src/uts/common/io/bofi.c @@ -367,7 +367,7 @@ dmareq_pplist_mapin(uint_t len, caddr_t addr, page_t **pplist, struct as *as, */ static caddr_t ddi_dmareq_mapin(struct ddi_dma_req *dmareqp, caddr_t *mapaddrp, - offset_t *lenp) + offset_t *lenp) { int sleep = (dmareqp->dmar_fp == DDI_DMA_SLEEP) ? VM_SLEEP: VM_NOSLEEP; @@ -909,7 +909,7 @@ bofi_close(dev_t dev, int flag, int otyp, cred_t *credp) /* ARGSUSED */ static int bofi_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, - int *rvalp) + int *rvalp) { struct bofi_errent *softc; int minor = (int)getminor(dev); @@ -1730,7 +1730,7 @@ bofi_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, */ static int bofi_errdef_alloc(struct bofi_errdef *errdefp, char *namep, - struct bofi_errent *softc) + struct bofi_errent *softc) { struct bofi_errent *ep; struct bofi_shadow *hp; @@ -2291,7 +2291,7 @@ log_acc_event(struct bofi_errent *ep, uint_t at, offset_t offset, off_t len, */ static void do_dma_corrupt(struct bofi_shadow *hp, struct bofi_errent *ep, - uint_t synctype, off_t off, off_t length) + uint_t synctype, off_t off, off_t length) { uint64_t operand; int i; @@ -2405,7 +2405,7 @@ static uint64_t do_bofi_rd64(struct bofi_shadow *, caddr_t); */ static uint64_t do_pior_corrupt(struct bofi_shadow *hp, caddr_t addr, - uint64_t (*func)(), size_t repcount, size_t accsize) + uint64_t (*func)(), size_t repcount, size_t accsize) { struct bofi_errent *ep; struct bofi_link *lp; @@ -2523,7 +2523,7 @@ do_pior_corrupt(struct bofi_shadow *hp, caddr_t addr, */ static int do_piow_corrupt(struct bofi_shadow *hp, caddr_t addr, uint64_t *valuep, - size_t size, size_t repcount) + size_t size, size_t repcount) { struct bofi_errent *ep; struct bofi_link *lp; @@ -2843,7 +2843,7 @@ bofi_wr64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t value) */ static void bofi_rep_rd8(ddi_acc_impl_t *handle, uint8_t *host_addr, uint8_t *dev_addr, - size_t repcount, uint_t flags) + size_t repcount, uint_t flags) { struct bofi_shadow *hp; int i; @@ -2870,7 +2870,7 @@ bofi_rep_rd8(ddi_acc_impl_t *handle, uint8_t *host_addr, uint8_t *dev_addr, */ static void bofi_rep_rd16(ddi_acc_impl_t *handle, uint16_t *host_addr, - uint16_t *dev_addr, size_t repcount, uint_t flags) + uint16_t *dev_addr, size_t repcount, uint_t flags) { struct bofi_shadow *hp; int i; @@ -2897,7 +2897,7 @@ bofi_rep_rd16(ddi_acc_impl_t *handle, uint16_t *host_addr, */ static void bofi_rep_rd32(ddi_acc_impl_t *handle, uint32_t *host_addr, - uint32_t *dev_addr, size_t repcount, uint_t flags) + uint32_t *dev_addr, size_t repcount, uint_t flags) { struct bofi_shadow *hp; int i; @@ -2924,7 +2924,7 @@ bofi_rep_rd32(ddi_acc_impl_t *handle, uint32_t *host_addr, */ static void bofi_rep_rd64(ddi_acc_impl_t *handle, uint64_t *host_addr, - uint64_t *dev_addr, size_t repcount, uint_t flags) + uint64_t *dev_addr, size_t repcount, uint_t flags) { struct bofi_shadow *hp; int i; @@ -2964,7 +2964,7 @@ bofi_rep_rd64(ddi_acc_impl_t *handle, uint64_t *host_addr, */ static void bofi_rep_wr8(ddi_acc_impl_t *handle, uint8_t *host_addr, uint8_t *dev_addr, - size_t repcount, uint_t flags) + size_t repcount, uint_t flags) { struct bofi_shadow *hp; int i; @@ -2995,7 +2995,7 @@ bofi_rep_wr8(ddi_acc_impl_t *handle, uint8_t *host_addr, uint8_t *dev_addr, */ static void bofi_rep_wr16(ddi_acc_impl_t *handle, uint16_t *host_addr, - uint16_t *dev_addr, size_t repcount, uint_t flags) + uint16_t *dev_addr, size_t repcount, uint_t flags) { struct bofi_shadow *hp; int i; @@ -3026,7 +3026,7 @@ bofi_rep_wr16(ddi_acc_impl_t *handle, uint16_t *host_addr, */ static void bofi_rep_wr32(ddi_acc_impl_t *handle, uint32_t *host_addr, - uint32_t *dev_addr, size_t repcount, uint_t flags) + uint32_t *dev_addr, size_t repcount, uint_t flags) { struct bofi_shadow *hp; int i; @@ -3057,7 +3057,7 @@ bofi_rep_wr32(ddi_acc_impl_t *handle, uint32_t *host_addr, */ static void bofi_rep_wr64(ddi_acc_impl_t *handle, uint64_t *host_addr, - uint64_t *dev_addr, size_t repcount, uint_t flags) + uint64_t *dev_addr, size_t repcount, uint_t flags) { struct bofi_shadow *hp; int i; @@ -3088,7 +3088,7 @@ bofi_rep_wr64(ddi_acc_impl_t *handle, uint64_t *host_addr, */ static int bofi_map(dev_info_t *dip, dev_info_t *rdip, - ddi_map_req_t *reqp, off_t offset, off_t len, caddr_t *vaddrp) + ddi_map_req_t *reqp, off_t offset, off_t len, caddr_t *vaddrp) { ddi_acc_impl_t *ap; struct bofi_shadow *hp; @@ -3339,7 +3339,7 @@ xbcopy(void *from, void *to, u_longlong_t len) */ static int bofi_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, - int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep) + int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep) { int retval = DDI_DMA_NORESOURCES; struct bofi_shadow *hp, *xhp; @@ -3365,7 +3365,7 @@ bofi_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, * what to do here? Wait a bit and try again */ if (waitfp != DDI_DMA_DONTWAIT) - (void) timeout((void (*)())waitfp, arg, 10); + (void) timeout((void (*)())(uintptr_t)waitfp, arg, 10); return (retval); } (void) strncpy(hp->name, ddi_get_name(rdip), NAMESIZE); @@ -3504,8 +3504,8 @@ bofi_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) */ static int bofi_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, - ddi_dma_handle_t handle, struct ddi_dma_req *dmareqp, - ddi_dma_cookie_t *cookiep, uint_t *ccountp) + ddi_dma_handle_t handle, struct ddi_dma_req *dmareqp, + ddi_dma_cookie_t *cookiep, uint_t *ccountp) { int retval = DDI_DMA_NORESOURCES; auto struct ddi_dma_req dmareq; @@ -3610,7 +3610,7 @@ error: /* * what to do here? Wait a bit and try again */ - (void) timeout((void (*)())dmareqp->dmar_fp, + (void) timeout((void (*)())(uintptr_t)dmareqp->dmar_fp, dmareqp->dmar_arg, 10); } error2: @@ -3711,7 +3711,7 @@ bofi_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) */ static int bofi_dma_flush(dev_info_t *dip, dev_info_t *rdip, - ddi_dma_handle_t handle, off_t off, size_t len, uint_t flags) + ddi_dma_handle_t handle, off_t off, size_t len, uint_t flags) { struct bofi_link *lp; struct bofi_errent *ep; @@ -3791,8 +3791,8 @@ bofi_dma_flush(dev_info_t *dip, dev_info_t *rdip, */ static int bofi_dma_win(dev_info_t *dip, dev_info_t *rdip, - ddi_dma_handle_t handle, uint_t win, off_t *offp, - size_t *lenp, ddi_dma_cookie_t *cookiep, uint_t *ccountp) + ddi_dma_handle_t handle, uint_t win, off_t *offp, + size_t *lenp, ddi_dma_cookie_t *cookiep, uint_t *ccountp) { struct bofi_shadow *hp; struct bofi_shadow *hhashp; @@ -3833,8 +3833,8 @@ bofi_dma_win(dev_info_t *dip, dev_info_t *rdip, */ static int bofi_dma_ctl(dev_info_t *dip, dev_info_t *rdip, - ddi_dma_handle_t handle, enum ddi_dma_ctlops request, - off_t *offp, size_t *lenp, caddr_t *objp, uint_t flags) + ddi_dma_handle_t handle, enum ddi_dma_ctlops request, + off_t *offp, size_t *lenp, caddr_t *objp, uint_t flags) { struct bofi_shadow *hp; struct bofi_shadow *hhashp; @@ -4041,7 +4041,7 @@ bofi_dvma_reserve(dev_info_t *rdip, ddi_dma_handle_t handle) */ static void bofi_dvma_kaddr_load(ddi_dma_handle_t h, caddr_t a, uint_t len, uint_t index, - ddi_dma_cookie_t *cp) + ddi_dma_cookie_t *cp) { struct bofi_shadow *dummyhp; struct bofi_shadow *hp; @@ -4449,7 +4449,7 @@ bofi_check_dma_hdl(ddi_dma_impl_t *handle) /* ARGSUSED */ static int bofi_post_event(dev_info_t *dip, dev_info_t *rdip, - ddi_eventcookie_t eventhdl, void *impl_data) + ddi_eventcookie_t eventhdl, void *impl_data) { ddi_eventcookie_t ec; struct ddi_fault_event_data *arg; diff --git a/usr/src/uts/intel/Makefile.intel b/usr/src/uts/intel/Makefile.intel index 658c80cd32..00785ef1be 100644 --- a/usr/src/uts/intel/Makefile.intel +++ b/usr/src/uts/intel/Makefile.intel @@ -394,6 +394,7 @@ DRV_KMODS += pvscsi DRV_KMODS += afe DRV_KMODS += atge DRV_KMODS += bfe +DRV_KMODS += bnx DRV_KMODS += bnxe DRV_KMODS += dmfe DRV_KMODS += e1000g diff --git a/usr/src/uts/intel/bnx/Makefile b/usr/src/uts/intel/bnx/Makefile new file mode 100644 index 0000000000..bf202d2bde --- /dev/null +++ b/usr/src/uts/intel/bnx/Makefile @@ -0,0 +1,104 @@ +# +# This file and its contents are supplied under the terms of the +# Common Development and Distribution License ("CDDL"), version 1.0. +# You may only use this file in accordance with the terms of version +# 1.0 of the CDDL. +# +# A full copy of the text of the CDDL should have accompanied this +# source. A copy of the CDDL is also available via the Internet at +# http://www.illumos.org/license/CDDL. +# + +# +# Copyright (c) 2018, Joyent, Inc. +# + +# +# uts/intel/bnx/Makefile +# +# This makefile drives the production of the bnx +# driver kernel module. +# +# intel architecture dependent +# + +# +# Paths to the base of the uts directory trees +# +UTSBASE = ../.. + +# +# Define the module and object file sets. +# +MODULE = bnx +OBJECTS = $(BNX_OBJS:%=$(OBJS_DIR)/%) +LINTS = $(LINTS_DIR)/bnx_lint.ln +ROOTMODULE = $(ROOT_DRV_DIR)/$(MODULE) +SRCDIR = $(UTSBASE)/common/io/bnx +CONF_SRCDIR = $(SRCDIR) + +# +# Include common rules. +# +include $(UTSBASE)/intel/Makefile.intel + +# +# Define targets +# +ALL_TARGET = $(BINARY) $(CONFMOD) +LINT_TARGET = $(MODULE).lint +INSTALL_TARGET = $(BINARY) $(ROOTMODULE) $(ROOT_CONFFILE) + +C99MODE= -xc99=%all +C99LMODE= -Xc99=%all + +# +# Driver-specific flags +# +CPPFLAGS += \ + -D_USE_FRIENDLY_NAME \ + -DEXCLUDE_RSS_SUPPORT \ + -DEXCLUDE_KQE_SUPPORT \ + -DL2_ONLY \ + -DSOLARIS \ + -D_ANSI_C_ \ + -DLM_MAX_MC_TABLE_SIZE=256 \ + -DBRCMVERSION="\"7.10.4\"" \ + -DLITTLE_ENDIAN \ + -DLITTLE_ENDIAN_HOST \ + -D__LITTLE_ENDIAN + +CPPFLAGS += \ + -I$(SRCDIR) \ + -I$(SRCDIR)/include \ + -I$(SRCDIR)/570x/common/include \ + -I$(SRCDIR)/570x/driver/common/lmdev + + +LDFLAGS += -dy -r -Ndrv/ip -Nmisc/mac + +# +# Default build targets. +# +.KEEP_STATE: + +def: $(DEF_DEPS) + +all: $(ALL_DEPS) + +clean: $(CLEAN_DEPS) + +clobber: $(CLOBBER_DEPS) + +lint: $(LINT_DEPS) + +modlintlib: $(MODLINTLIB_DEPS) + +clean.lint: $(CLEAN_LINT_DEPS) + +install: $(INSTALL_DEPS) + +# +# Include common targets. +# +include $(UTSBASE)/intel/Makefile.targ |