6404610 OPL power-fault event is logged even IO slot is empty

6408647 PCIe Power Fault handling should be hardened
6411109 Oberon hotplug debug messages need to be changed to macros

7 files changed, 204 insertions, 98 deletions

diff --git a/usr/src/uts/common/io/hotplug/pciehpc/pciehpc.c b/usr/src/uts/common/io/hotplug/pciehpc/pciehpc.c
index 737a83ea7c..ae204da376 100644
--- a/usr/src/uts/common/io/hotplug/pciehpc/pciehpc.c
+++ b/usr/src/uts/common/io/hotplug/pciehpc/pciehpc.c
@@ -380,7 +380,7 @@ pciehpc_probe_hpc(pciehpc_t *ctrl_p)
 int
 pciehpc_slotinfo_init(pciehpc_t *ctrl_p)
 {
-	uint32_t slot_capabilities;
+	uint32_t slot_capabilities, link_capabilities;
 	pciehpc_slot_t *p = &ctrl_p->slot;
 
 	/*
@@ -420,12 +420,19 @@ pciehpc_slotinfo_init(pciehpc_t *ctrl_p)
 		B_TRUE : B_FALSE;
 
 	/*
-	 * PCI-E (draft) version 1.1 defines EMI Lock Present bit
+	 * PCI-E version 1.1 defines EMI Lock Present bit
 	 * in Slot Capabilities register. Check for it.
 	 */
 	ctrl_p->has_emi_lock = (slot_capabilities &
 		PCIE_SLOTCAP_EMI_LOCK_PRESENT) ? B_TRUE : B_FALSE;
 
+	link_capabilities = pciehpc_reg_get32(ctrl_p,
+		ctrl_p->pcie_caps_reg_offset + PCIE_LINKCAP);
+	ctrl_p->dll_active_rep = (link_capabilities &
+		PCIE_LINKCAP_DLL_ACTIVE_REP_CAPABLE) ? B_TRUE : B_FALSE;
+	if (ctrl_p->dll_active_rep)
+		cv_init(&ctrl_p->slot.dll_active_cv, NULL, CV_DRIVER, NULL);
+
 	/* initialize synchronization conditional variable */
 	cv_init(&ctrl_p->slot.cmd_comp_cv, NULL, CV_DRIVER, NULL);
 	ctrl_p->slot.command_pending = B_FALSE;
@@ -469,6 +476,9 @@ pciehpc_slotinfo_uninit(pciehpc_t *ctrl_p)
 	    mutex_exit(&ctrl_p->pciehpc_mutex);
 	}
 
+	if (ctrl_p->dll_active_rep)
+		cv_destroy(&ctrl_p->slot.dll_active_cv);
+
 	return (DDI_SUCCESS);
 }
 
@@ -676,6 +686,12 @@ pciehpc_hpc_init(pciehpc_t *ctrl_p)
 	pciehpc_reg_put16(ctrl_p, ctrl_p->pcie_caps_reg_offset +
 		PCIE_SLOTCTL, reg);
 
+	/* clear any interrupt status bits */
+	reg = pciehpc_reg_get16(ctrl_p,
+		ctrl_p->pcie_caps_reg_offset + PCIE_SLOTSTS);
+	pciehpc_reg_put16(ctrl_p,
+		ctrl_p->pcie_caps_reg_offset + PCIE_SLOTSTS, reg);
+
 	/* initialize the interrupt mutex */
 	mutex_init(&ctrl_p->pciehpc_mutex, NULL, MUTEX_DRIVER,
 		(void *)PCIEHPC_INTR_PRI);
@@ -746,7 +762,10 @@ pciehpc_enable_intr(pciehpc_t *ctrl_p)
 	reg = pciehpc_reg_get16(ctrl_p,
 		ctrl_p->pcie_caps_reg_offset + PCIE_SLOTCTL);
 
-	/* enable interrupts */
+	/*
+	 * enable interrupts: power fault detection interrupt is enabled
+	 * only when the slot is 'connected', i.e. power is ON
+	 */
 	if (ctrl_p->slot.slot_state == HPC_SLOT_CONNECTED)
 		pciehpc_reg_put16(ctrl_p, ctrl_p->pcie_caps_reg_offset +
 			PCIE_SLOTCTL, reg | SLOTCTL_SUPPORTED_INTRS_MASK);
@@ -819,7 +838,7 @@ int
 pciehpc_intr(dev_info_t *dip)
 {
 	pciehpc_t *ctrl_p;
-	uint16_t status;
+	uint16_t status, control;
 
 	/* get the soft state structure for this dip */
 	if ((ctrl_p = pciehpc_get_soft_state(dip)) == NULL)
@@ -877,9 +896,23 @@ pciehpc_intr(dev_info_t *dip)
 
 	/* check for power fault interrupt */
 	if (status & PCIE_SLOTSTS_PWR_FAULT_DETECTED) {
-	    /* send the event to HPS framework */
-	    (void) hpc_slot_event_notify(ctrl_p->slot.slot_handle,
-		HPC_EVENT_SLOT_POWER_FAULT, HPC_EVENT_NORMAL);
+	    PCIEHPC_DEBUG3((CE_NOTE,
+		"pciehpc_intr(): POWER FAULT interrupt received"
+		" on slot %d\n", ctrl_p->slot.slotNum));
+	    control =  pciehpc_reg_get16(ctrl_p,
+		ctrl_p->pcie_caps_reg_offset + PCIE_SLOTCTL);
+	    if (control & PCIE_SLOTCTL_PWR_FAULT_EN) {
+		/* disable power fault detction interrupt */
+		pciehpc_reg_put16(ctrl_p, ctrl_p->pcie_caps_reg_offset +
+		    PCIE_SLOTCTL, control & ~PCIE_SLOTCTL_PWR_FAULT_EN);
+
+		/* turn on ATTN LED */
+		pciehpc_set_led_state(ctrl_p, HPC_ATTN_LED, HPC_LED_OFF);
+
+		/* send the event to HPS framework */
+		(void) hpc_slot_event_notify(ctrl_p->slot.slot_handle,
+		    HPC_EVENT_SLOT_POWER_FAULT, HPC_EVENT_NORMAL);
+	    }
 	}
 
 	/* check for MRL SENSOR CHANGED interrupt */
@@ -895,7 +928,40 @@ pciehpc_intr(dev_info_t *dip)
 	    PCIEHPC_DEBUG3((CE_NOTE,
 		"pciehpc_intr(): PRESENCE CHANGED interrupt received"
 		" on slot %d\n", ctrl_p->slot.slotNum));
-	    /* For now (phase-I), no action is taken on this event */
+
+	    if (status & PCIE_SLOTSTS_PRESENCE_DETECTED) {
+		/* card is inserted into the slot */
+
+		/* send the event to HPS framework */
+		(void) hpc_slot_event_notify(ctrl_p->slot.slot_handle,
+		    HPC_EVENT_SLOT_INSERTION, HPC_EVENT_NORMAL);
+	    } else {
+		/* card is removed from the slot */
+
+		/* make sure to disable power fault detction interrupt */
+		control =  pciehpc_reg_get16(ctrl_p,
+		    ctrl_p->pcie_caps_reg_offset + PCIE_SLOTCTL);
+		if (control & PCIE_SLOTCTL_PWR_FAULT_EN)
+		    pciehpc_reg_put16(ctrl_p, ctrl_p->pcie_caps_reg_offset +
+			PCIE_SLOTCTL, control & ~PCIE_SLOTCTL_PWR_FAULT_EN);
+
+		/* turn off ATTN LED */
+		pciehpc_set_led_state(ctrl_p, HPC_ATTN_LED, HPC_LED_OFF);
+
+		/* send the event to HPS framework */
+		(void) hpc_slot_event_notify(ctrl_p->slot.slot_handle,
+		    HPC_EVENT_SLOT_REMOVAL, HPC_EVENT_NORMAL);
+	    }
+	}
+
+	/* check for DLL state changed interrupt */
+	if (ctrl_p->dll_active_rep &&
+		(status & PCIE_SLOTSTS_DLL_STATE_CHANGED)) {
+	    PCIEHPC_DEBUG3((CE_NOTE,
+		"pciehpc_intr(): DLL STATE CHANGED interrupt received"
+		" on slot %d\n", ctrl_p->slot.slotNum));
+
+	    cv_signal(&ctrl_p->slot.dll_active_cv);
 	}
 
 	mutex_exit(&ctrl_p->pciehpc_mutex);
@@ -1001,8 +1067,7 @@ int
 pciehpc_slot_connect(caddr_t ops_arg, hpc_slot_t slot_hdl,
 	void *data, uint_t flags)
 {
-	uint16_t status;
-	uint16_t control;
+	uint16_t status, control;
 
 	pciehpc_t *ctrl_p = (pciehpc_t *)ops_arg;
 
@@ -1063,11 +1128,11 @@ pciehpc_slot_connect(caddr_t ops_arg, hpc_slot_t slot_hdl,
 	 *	1. Set power LED to blink and ATTN led to OFF.
 	 *	2. Set power control ON in Slot Control Reigster and
 	 *	   wait for Command Completed Interrupt or 1 sec timeout.
-	 *	3. Set power LED to be ON.
-	 *	4. If Data Link Layer State Changed events are supported
+	 *	3. If Data Link Layer State Changed events are supported
 	 *	   then wait for the event to indicate Data Layer Link
 	 *	   is active. The time out value for this event is 1 second.
-	 *	   This is specified in PCI-E (draft) version 1.1.
+	 *	   This is specified in PCI-E version 1.1.
+	 *	4. Set power LED to be ON.
 	 */
 
 	/* 1. set power LED to blink & ATTN led to OFF */
@@ -1080,7 +1145,34 @@ pciehpc_slot_connect(caddr_t ops_arg, hpc_slot_t slot_hdl,
 	control &= ~PCIE_SLOTCTL_PWR_CONTROL;
 	pciehpc_issue_hpc_command(ctrl_p, control);
 
-	/* check power is really turned ON? */
+	/* 3. wait for DLL State Change event, if it's supported */
+	if (ctrl_p->dll_active_rep) {
+		status =  pciehpc_reg_get16(ctrl_p,
+		    ctrl_p->pcie_caps_reg_offset + PCIE_LINKSTS);
+
+		if (!(status & PCIE_LINKSTS_DLL_LINK_ACTIVE)) {
+			/* wait 1 sec for the DLL State Changed event */
+			(void) cv_timedwait(&ctrl_p->slot.dll_active_cv,
+			    &ctrl_p->pciehpc_mutex,
+			    ddi_get_lbolt() +
+			    SEC_TO_TICK(PCIEHPC_DLL_STATE_CHANGE_TIMEOUT));
+
+			/* check Link status */
+			status =  pciehpc_reg_get16(ctrl_p,
+			    ctrl_p->pcie_caps_reg_offset +
+			    PCIE_LINKSTS);
+			if (!(status & PCIE_LINKSTS_DLL_LINK_ACTIVE))
+				goto cleanup2;
+		}
+
+		/* wait 100ms after DLL_LINK_ACTIVE field reads 1b */
+		delay(drv_usectohz(100000));
+	} else {
+		/* wait 1 sec for link to come up */
+		delay(drv_usectohz(1000000));
+	}
+
+	/* check power is really turned ON */
 	control =  pciehpc_reg_get16(ctrl_p,
 		ctrl_p->pcie_caps_reg_offset + PCIE_SLOTCTL);
 	if (control & PCIE_SLOTCTL_PWR_CONTROL) {
@@ -1091,49 +1183,42 @@ pciehpc_slot_connect(caddr_t ops_arg, hpc_slot_t slot_hdl,
 		goto cleanup1;
 	}
 
-	/* check power-fault on the slot? */
-	status = pciehpc_reg_get16(ctrl_p,
-		ctrl_p->pcie_caps_reg_offset + PCIE_SLOTSTS);
-	if (status & PCIE_SLOTSTS_PWR_FAULT_DETECTED) {
-		PCIEHPC_DEBUG((CE_NOTE,
-		    "slot %d detects power fault on connect\n",
-		    ctrl_p->slot.slotNum));
-
-		/* set power control to OFF */
-		control =  pciehpc_reg_get16(ctrl_p,
-			ctrl_p->pcie_caps_reg_offset + PCIE_SLOTCTL);
-		control |= PCIE_SLOTCTL_PWR_CONTROL;
-		pciehpc_issue_hpc_command(ctrl_p, control);
-
-		/* clear the status */
-		pciehpc_reg_put16(ctrl_p,
-			ctrl_p->pcie_caps_reg_offset + PCIE_SLOTSTS, status);
-		goto cleanup1;
-	}
+	/* enable power fault detection interrupt */
+	control |= PCIE_SLOTCTL_PWR_FAULT_EN;
+	pciehpc_issue_hpc_command(ctrl_p, control);
 
-	/* enable all interrupts */
-	pciehpc_reg_put16(ctrl_p,
-		ctrl_p->pcie_caps_reg_offset + PCIE_SLOTSTS, status);
+	/* 4. Set power LED to be ON */
+	pciehpc_set_led_state(ctrl_p, HPC_POWER_LED, HPC_LED_ON);
 
-	control = pciehpc_reg_get16(ctrl_p,
-		ctrl_p->pcie_caps_reg_offset + PCIE_SLOTCTL);
-	pciehpc_reg_put16(ctrl_p, ctrl_p->pcie_caps_reg_offset +
-		PCIE_SLOTCTL, control | SLOTCTL_SUPPORTED_INTRS_MASK);
+	/* if EMI is present, turn it ON */
+	if (ctrl_p->has_emi_lock) {
+		status =  pciehpc_reg_get16(ctrl_p,
+		    ctrl_p->pcie_caps_reg_offset + PCIE_SLOTSTS);
 
-	/* 3. Set power LED to be ON */
-	pciehpc_set_led_state(ctrl_p, HPC_POWER_LED, HPC_LED_ON);
+		if (!(status & PCIE_SLOTSTS_EMI_LOCK_SET)) {
+			control =  pciehpc_reg_get16(ctrl_p,
+			    ctrl_p->pcie_caps_reg_offset + PCIE_SLOTCTL);
+			control |= PCIE_SLOTCTL_EMI_LOCK_CONTROL;
+			pciehpc_issue_hpc_command(ctrl_p, control);
 
-	/*
-	 * NOTE - needs work for pci-e 1.1 features
-	 * - if EMI Lock is present then it should be turned ON
-	 * - if DLL State Change events are supported then we need
-	 *   to wait for DLL Active event.
-	 */
+			/* wait 1 sec after toggling the state of EMI lock */
+			delay(drv_usectohz(1000000));
+		}
+	}
 
 	ctrl_p->slot.slot_state = HPC_SLOT_CONNECTED;
 	mutex_exit(&ctrl_p->pciehpc_mutex);
 	return (HPC_SUCCESS);
 
+cleanup2:
+	control =  pciehpc_reg_get16(ctrl_p,
+		ctrl_p->pcie_caps_reg_offset + PCIE_SLOTCTL);
+	/* if power is ON, set power control to OFF */
+	if (!(control & PCIE_SLOTCTL_PWR_CONTROL)) {
+		control |= PCIE_SLOTCTL_PWR_CONTROL;
+		pciehpc_issue_hpc_command(ctrl_p, control);
+	}
+
 cleanup1:
 	/* set power led to OFF */
 	pciehpc_set_led_state(ctrl_p, HPC_POWER_LED, HPC_LED_OFF);
@@ -1205,6 +1290,12 @@ pciehpc_slot_disconnect(caddr_t ops_arg, hpc_slot_t slot_hdl,
 	/* 1. set power LED to blink */
 	pciehpc_set_led_state(ctrl_p, HPC_POWER_LED, HPC_LED_BLINK);
 
+	/* disable power fault detection interrupt */
+	control = pciehpc_reg_get16(ctrl_p,
+		ctrl_p->pcie_caps_reg_offset + PCIE_SLOTCTL);
+	control &= ~PCIE_SLOTCTL_PWR_FAULT_EN;
+	pciehpc_issue_hpc_command(ctrl_p, control);
+
 	/* 2. set power control to OFF */
 	control =  pciehpc_reg_get16(ctrl_p,
 		ctrl_p->pcie_caps_reg_offset + PCIE_SLOTCTL);
@@ -1222,12 +1313,21 @@ pciehpc_slot_disconnect(caddr_t ops_arg, hpc_slot_t slot_hdl,
 	pciehpc_set_led_state(ctrl_p, HPC_POWER_LED, HPC_LED_OFF);
 	pciehpc_set_led_state(ctrl_p, HPC_ATTN_LED, HPC_LED_OFF);
 
-	/* disable interrupt of power fault detection */
-	control = pciehpc_reg_get16(ctrl_p,
-		ctrl_p->pcie_caps_reg_offset + PCIE_SLOTCTL);
-	pciehpc_reg_put16(ctrl_p, ctrl_p->pcie_caps_reg_offset +
-		PCIE_SLOTCTL, control | (SLOTCTL_SUPPORTED_INTRS_MASK &
-				~PCIE_SLOTCTL_PWR_FAULT_EN));
+	/* if EMI is present, turn it OFF */
+	if (ctrl_p->has_emi_lock) {
+		status =  pciehpc_reg_get16(ctrl_p,
+		    ctrl_p->pcie_caps_reg_offset + PCIE_SLOTSTS);
+
+		if (status & PCIE_SLOTSTS_EMI_LOCK_SET) {
+			control =  pciehpc_reg_get16(ctrl_p,
+			    ctrl_p->pcie_caps_reg_offset + PCIE_SLOTCTL);
+			control |= PCIE_SLOTCTL_EMI_LOCK_CONTROL;
+			pciehpc_issue_hpc_command(ctrl_p, control);
+
+			/* wait 1 sec after toggling the state of EMI lock */
+			delay(drv_usectohz(1000000));
+		}
+	}
 
 	ctrl_p->slot.slot_state = HPC_SLOT_DISCONNECTED;
 	mutex_exit(&ctrl_p->pciehpc_mutex);
diff --git a/usr/src/uts/common/io/hotplug/pcihp/pcihp.c b/usr/src/uts/common/io/hotplug/pcihp/pcihp.c
index 1a9e236856..11385b5194 100644
--- a/usr/src/uts/common/io/hotplug/pcihp/pcihp.c
+++ b/usr/src/uts/common/io/hotplug/pcihp/pcihp.c
@@ -2,9 +2,8 @@
  * CDDL HEADER START
  *
  * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License").  You may not use this file except in compliance
- * with the License.
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
  *
  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  * or http://www.opensolaris.org/os/licensing.
@@ -2660,13 +2659,14 @@ pcihp_event_handler(caddr_t slot_arg, uint_t event_mask)
 			    ddi_driver_name(pcihp_p->dip),
 			    ddi_get_instance(pcihp_p->dip),
 			    slotinfop->name);
-		}
-		else
+		} else {
+			slotinfop->condition = AP_COND_UNKNOWN;
 			cmn_err(CE_NOTE, "pcihp (%s%d): card is removed"
 			    " from the slot %s",
 			    ddi_driver_name(pcihp_p->dip),
 			    ddi_get_instance(pcihp_p->dip),
 			    slotinfop->name);
+		}
 
 		slotinfop->rstate = AP_RSTATE_EMPTY;
 
@@ -2945,6 +2945,10 @@ pcihp_event_handler(caddr_t slot_arg, uint_t event_mask)
 		    ddi_get_instance(pcihp_p->dip),
 		    slotinfop->name);
 
+		if (slotinfop->rstate == AP_RSTATE_CONNECTED)
+			(void) hpc_nexus_disconnect(slotinfop->slot_hdl,
+			    NULL, 0);
+
 		slotinfop->condition = AP_COND_FAILED;
 
 		pcihp_gen_sysevent(slotinfop->name, PCIHP_DR_AP_STATE_CHANGE,
diff --git a/usr/src/uts/common/sys/hotplug/pci/pciehpc_impl.h b/usr/src/uts/common/sys/hotplug/pci/pciehpc_impl.h
index 249f75df24..278e213e3c 100644
--- a/usr/src/uts/common/sys/hotplug/pci/pciehpc_impl.h
+++ b/usr/src/uts/common/sys/hotplug/pci/pciehpc_impl.h
@@ -62,6 +62,7 @@ typedef struct pciehpc_slot
 	boolean_t	attn_btn_pending;
 	kthread_t	*attn_btn_threadp;	/* ATTN button event thread */
 	boolean_t	attn_btn_thread_exit;
+	kcondvar_t	dll_active_cv;		/* DLL State Changed intr */
 } pciehpc_slot_t;
 
 typedef enum {
@@ -106,6 +107,9 @@ typedef struct pciehpc
 	boolean_t		has_mrl;	/* Do we have MRL? */
 	boolean_t		has_emi_lock;	/* Do we have EMI Lock? */
 
+	/* link capablities */
+	boolean_t	dll_active_rep;	/* Do we report DLL DL_Active state? */
+
 	/* register read/write ops for non-standard HPC (e.g: OPL) */
 	pciehpc_regops_t	regops;
 
@@ -140,20 +144,27 @@ typedef struct pciehpc_ops pciehpc_ops_t;
 #define	PCIEHPC_CMD_WAIT_TIME	10000
 #define	PCIEHPC_CMD_WAIT_RETRY	100
 
+/*
+ * PCI-E HPC Dll State Change time out in seconds
+ */
+#define	PCIEHPC_DLL_STATE_CHANGE_TIMEOUT 1
+
 #define	SLOTCTL_SUPPORTED_INTRS_MASK	\
 	(PCIE_SLOTCTL_ATTN_BTN_EN \
 	| PCIE_SLOTCTL_PWR_FAULT_EN \
 	| PCIE_SLOTCTL_MRL_SENSOR_EN \
 	| PCIE_SLOTCTL_PRESENCE_CHANGE_EN \
 	| PCIE_SLOTCTL_CMD_INTR_EN \
-	| PCIE_SLOTCTL_HP_INTR_EN)
+	| PCIE_SLOTCTL_HP_INTR_EN \
+	| PCIE_SLOTCTL_DLL_STATE_EN)
 
 #define	SLOT_STATUS_EVENTS	\
 	(PCIE_SLOTSTS_ATTN_BTN_PRESSED \
 	| PCIE_SLOTSTS_PWR_FAULT_DETECTED \
 	| PCIE_SLOTSTS_MRL_SENSOR_CHANGED \
 	| PCIE_SLOTSTS_COMMAND_COMPLETED \
-	| PCIE_SLOTSTS_PRESENCE_CHANGED)
+	| PCIE_SLOTSTS_PRESENCE_CHANGED \
+	| PCIE_SLOTSTS_DLL_STATE_CHANGED)
 
 /*
  * function prototype defintions for common native mode functions in
diff --git a/usr/src/uts/common/sys/pcie.h b/usr/src/uts/common/sys/pcie.h
index 61812bab0f..f6f2d96432 100644
--- a/usr/src/uts/common/sys/pcie.h
+++ b/usr/src/uts/common/sys/pcie.h
@@ -2,9 +2,8 @@
  * CDDL HEADER START
  *
  * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License").  You may not use this file except in compliance
- * with the License.
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
  *
  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  * or http://www.opensolaris.org/os/licensing.
@@ -20,7 +19,7 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
@@ -250,6 +249,9 @@ extern "C" {
 #define	PCIE_LINKSTS_LINK_TRAINING	0x800	/* Link Training */
 #define	PCIE_LINKSTS_SLOT_CLK_CFG	0x1000	/* Slot Clock Configuration */
 
+/* PCIe v1.1 spec based */
+#define	PCIE_LINKSTS_DLL_LINK_ACTIVE	0x2000	/* DLL Link Active */
+
 /*
  * Slot Capability Register (4 bytes)
  */
@@ -290,6 +292,7 @@ extern "C" {
 #define	PCIE_SLOTCTL_HP_INTR_EN		0x20	/* Hot-Plug Interrupt Enable */
 #define	PCIE_SLOTCTL_PWR_CONTROL	0x0400	/* Power controller Control */
 #define	PCIE_SLOTCTL_EMI_LOCK_CONTROL	0x0800	/* EMI Lock control */
+#define	PCIE_SLOTCTL_DLL_STATE_EN	0x1000	/* DLL State Changed En */
 #define	PCIE_SLOTCTL_ATTN_INDICATOR_MASK 0x00C0	/* Attn Indicator mask */
 #define	PCIE_SLOTCTL_PWR_INDICATOR_MASK	0x0300	/* Power Indicator mask */
 
diff --git a/usr/src/uts/sun4/io/px/px_debug.c b/usr/src/uts/sun4/io/px/px_debug.c
index 10eefafb16..281dbfc2e4 100644
--- a/usr/src/uts/sun4/io/px/px_debug.c
+++ b/usr/src/uts/sun4/io/px/px_debug.c
@@ -107,6 +107,8 @@ static char *px_debug_sym [] = {	/* same sequence as px_debug_bit */
 
 	/* 52 */ "tools",
 	/* 53 */ "phys_acc",
+
+	/* 54 */ "hotplug",
 	/* LAST */ "unknown"
 };
 
diff --git a/usr/src/uts/sun4/io/px/px_debug.h b/usr/src/uts/sun4/io/px/px_debug.h
index 96c63a68e5..5916a6928b 100644
--- a/usr/src/uts/sun4/io/px/px_debug.h
+++ b/usr/src/uts/sun4/io/px/px_debug.h
@@ -2,9 +2,8 @@
  * CDDL HEADER START
  *
  * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License").  You may not use this file except in compliance
- * with the License.
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
  *
  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  * or http://www.opensolaris.org/os/licensing.
@@ -20,7 +19,7 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
@@ -103,7 +102,9 @@ typedef enum {	/* same sequence as px_debug_sym[] */
 	/* 51 */ DBG_RSV5,
 
 	/* 52 */ DBG_TOOLS,
-	/* 53 */ DBG_PHYS_ACC
+	/* 53 */ DBG_PHYS_ACC,
+
+	/* 54 */ DBG_HP
 } px_debug_bit_t;
 
 #define	DBG_BITS	6
diff --git a/usr/src/uts/sun4u/io/px/px_hlib.c b/usr/src/uts/sun4u/io/px/px_hlib.c
index 1cd79e686c..5e69c3a7ae 100644
--- a/usr/src/uts/sun4u/io/px/px_hlib.c
+++ b/usr/src/uts/sun4u/io/px/px_hlib.c
@@ -2990,16 +2990,12 @@ oberon_hp_pwron(caddr_t csr_base)
 {
 	volatile uint64_t reg;
 
-#ifdef  DEBUG
-	cmn_err(CE_CONT, "oberon_hp_pwron the slot\n");
-#endif
+	DBG(DBG_HP, NULL, "oberon_hp_pwron the slot\n");
 
 	/* Check Leaf Reset status */
 	reg = CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE);
 	if (!(reg & (1ull << ILU_ERROR_LOG_ENABLE_SPARE3))) {
-#ifdef DEBUG
-		cmn_err(CE_WARN, "oberon_hp_pwron fails: leaf not reset\n");
-#endif
+		DBG(DBG_HP, NULL, "oberon_hp_pwron fails: leaf not reset\n");
 		goto fail;
 	}
 
@@ -3008,10 +3004,8 @@ oberon_hp_pwron(caddr_t csr_base)
 	if (!(reg & (1ull << TLU_SLOT_STATUS_PSD)) ||
 	    (reg & (1ull << TLU_SLOT_STATUS_MRLS)) ||
 	    (reg & (1ull << TLU_SLOT_STATUS_PWFD))) {
-#ifdef DEBUG
-		cmn_err(CE_WARN, "oberon_hp_pwron fails: slot status %lx\n",
+		DBG(DBG_HP, NULL, "oberon_hp_pwron fails: slot status %lx\n",
 		    reg);
-#endif
 		goto fail;
 	}
 
@@ -3034,9 +3028,7 @@ oberon_hp_pwroff(caddr_t csr_base)
 {
 	volatile uint64_t reg;
 
-#ifdef  DEBUG
-	cmn_err(CE_CONT, "oberon_hp_pwroff the slot\n");
-#endif
+	DBG(DBG_HP, NULL, "oberon_hp_pwroff the slot\n");
 
 	/* Blink power LED, this is done from pciehpc already */
 
@@ -3110,9 +3102,7 @@ static uint_t oberon_hp_pwrledon(caddr_t csr_base)
 {
 	volatile uint64_t reg;
 
-#ifdef  DEBUG
-	cmn_err(CE_CONT, "oberon_hp_pwrledon the slot\n");
-#endif
+	DBG(DBG_HP, NULL, "oberon_hp_pwrledon the slot\n");
 
 	CSR_BS(csr_base, TLU_SLOT_CONTROL, PWFDEN);
 
@@ -3148,8 +3138,11 @@ static uint_t oberon_hp_pwrledon(caddr_t csr_base)
 	delay(drv_usectohz(10000));
 	reg = CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_CLEAR);
 	if (!(reg & (1ull << TLU_OTHER_EVENT_STATUS_CLEAR_LUP_P)) &&
-	    !(reg & (1ull << TLU_OTHER_EVENT_STATUS_CLEAR_LUP_S)))
+	    !(reg & (1ull << TLU_OTHER_EVENT_STATUS_CLEAR_LUP_S))) {
+		DBG(DBG_HP, NULL, "oberon_hp_pwrledon fails to enable "
+		    "PCI-E port\n");
 		goto fail;
+	}
 
 	/* Turn on Power LED */
 	reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
@@ -3207,10 +3200,8 @@ oberon_hpreg_get(void *cookie, off_t off)
 		val = CSR_XR(csr_base, TLU_SLOT_STATUS);
 		break;
 	default:
-#ifdef  DEBUG
-		cmn_err(CE_WARN, "oberon_hpreg_get(): "
+		DBG(DBG_HP, NULL, "oberon_hpreg_get(): "
 		    "unsupported offset 0x%lx\n", off);
-#endif
 		break;
 	}
 
@@ -3225,10 +3216,8 @@ oberon_hpreg_put(void *cookie, off_t off, uint_t val)
 	uint16_t pwr_led_state, pwr_led_ctrl;
 	uint_t pwr_off, ret = DDI_SUCCESS;
 
-#ifdef DEBUG
-	cmn_err(CE_CONT, "oberon_hpreg_put 0x%lx: cur %x, new %x\n",
+	DBG(DBG_HP, NULL, "oberon_hpreg_put 0x%lx: cur %x, new %x\n",
 	    off, oberon_hpreg_get(cookie, off), val);
-#endif
 
 	switch (off) {
 	case PCIE_SLOTCTL:
@@ -3264,10 +3253,8 @@ oberon_hpreg_put(void *cookie, off_t off, uint_t val)
 		CSR_XS(csr_base, TLU_SLOT_STATUS, val);
 		break;
 	default:
-#ifdef  DEBUG
-		cmn_err(CE_WARN, "oberon_hpreg_put(): "
+		DBG(DBG_HP, NULL, "oberon_hpreg_put(): "
 		    "unsupported offset 0x%lx\n", off);
-#endif
 		ret = DDI_FAILURE;
 		break;
 	}
@@ -3285,10 +3272,8 @@ hvio_hotplug_init(dev_info_t *dip, void *arg)
 	if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) {
 		if (!CSR_BR((caddr_t)pxu_p->px_address[PX_REG_CSR],
 		    TLU_SLOT_CAPABILITIES, HP)) {
-#ifdef	DEBUG
-			cmn_err(CE_WARN, "%s%d: hotplug capabale not set\n",
+			DBG(DBG_HP, NULL, "%s%d: hotplug capabale not set\n",
 			    ddi_driver_name(dip), ddi_get_instance(dip));
-#endif
 			return (DDI_FAILURE);
 		}