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| author | Dan McDonald <danmcd@mnx.io> | 2022-05-13 17:20:24 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-13 17:20:24 -0400 |
| commit | bb7d6c9b47695f41cbacbcf6662baf3d0e152fdf (patch) | |
| tree | 75f2d0cab5fb92f97f2ab2c3186a0b5d1579a33a /usr/src/uts/common/sys/mac_flow.h | |
| parent | 8ca5534c77e93c25d2c1f777499b12da0f7cc0cd (diff) | |
| parent | 402559e299331588f209b3a9693e3bcd6a83d22c (diff) | |
| download | illumos-joyent-OS-8149.tar.gz | |
Merge branch 'master' into OS-8149OS-8149
Diffstat (limited to 'usr/src/uts/common/sys/mac_flow.h')
| -rw-r--r-- | usr/src/uts/common/sys/mac_flow.h | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/usr/src/uts/common/sys/mac_flow.h b/usr/src/uts/common/sys/mac_flow.h index d37752ec23..a9a2a5f61e 100644 --- a/usr/src/uts/common/sys/mac_flow.h +++ b/usr/src/uts/common/sys/mac_flow.h @@ -23,6 +23,7 @@ * Copyright 2010 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. * Copyright 2017 Joyent, Inc. All rights reserved. + * Copyright 2020 RackTop Systems, Inc. */ #ifndef _MAC_FLOW_H @@ -92,7 +93,7 @@ typedef struct flow_desc_s { uint8_t fd_dsfield_mask; } flow_desc_t; -#define MRP_NCPUS 128 +#define MRP_NCPUS 256 /* * In MCM_CPUS mode, cpu bindings is user specified. In MCM_FANOUT mode, @@ -118,7 +119,7 @@ typedef struct mac_tx_intr_cpus_s { typedef struct mac_cpus_props_s { uint32_t mc_ncpus; /* num of cpus */ - uint32_t mc_cpus[MRP_NCPUS]; /* cpu list */ + uint32_t mc_cpus[MRP_NCPUS]; /* cpu list */ uint32_t mc_rx_fanout_cnt; /* soft ring cpu cnt */ uint32_t mc_rx_fanout_cpus[MRP_NCPUS]; /* SR cpu list */ uint32_t mc_rx_pollid; /* poll thr binding */ @@ -198,10 +199,10 @@ typedef struct mac_protect_s { /* The default priority for flows */ #define MPL_SUBFLOW_DEFAULT MPL_MEDIUM -#define MRP_MAXBW 0x00000001 /* Limit set */ -#define MRP_CPUS 0x00000002 /* CPU/fanout set */ -#define MRP_CPUS_USERSPEC 0x00000004 /* CPU/fanout from user */ -#define MRP_PRIORITY 0x00000008 /* Priority set */ +#define MRP_MAXBW 0x00000001 /* Limit set */ +#define MRP_CPUS 0x00000002 /* CPU/fanout set */ +#define MRP_CPUS_USERSPEC 0x00000004 /* CPU/fanout from user */ +#define MRP_PRIORITY 0x00000008 /* Priority set */ #define MRP_PROTECT 0x00000010 /* Protection set */ #define MRP_RX_RINGS 0x00000020 /* Rx rings */ #define MRP_TX_RINGS 0x00000040 /* Tx rings */ |