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| author | Krishna Elango <Krishna.Elango@Sun.COM> | 2009-06-20 15:42:11 -0700 |
|---|---|---|
| committer | Krishna Elango <Krishna.Elango@Sun.COM> | 2009-06-20 15:42:11 -0700 |
| commit | c85864d8472aaccb47ceb468ebd9b3a85b66d161 (patch) | |
| tree | 4c0db6e039b61e267801715e505357c13cd4b94f /usr/src/uts/common/sys/pcie.h | |
| parent | 41a5f560d7437bb41abade5dce25dc6875da156a (diff) | |
| download | illumos-joyent-c85864d8472aaccb47ceb468ebd9b3a85b66d161.tar.gz | |
6768098 system panics with PCIe fabric.(0x0)(0x43) due to masked errors.
6814026 PLX disable RO algorithm is incorrect
6813298 Legacy PCI Express Endpoint is not used correctly in pcie module
6841301 PCI ECS accesses with pcitool don't work on AMD processors
6813766 faulty EPKT FMA rules need to expect ereports coming from hostbridge
6841816 PCIe Error Handling's scan_fabric doesn't handle failed IO Addresses well
6798264 PCIe error handling doesn't handle zero bdf well
6802636 fault address may not be decoded correctly during PCIe error handling
6843716 suspicious definition of PCIE_REQ_ID_DEV_MASK
6831766 coredump in pci_bridge_declare()
Diffstat (limited to 'usr/src/uts/common/sys/pcie.h')
| -rw-r--r-- | usr/src/uts/common/sys/pcie.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/usr/src/uts/common/sys/pcie.h b/usr/src/uts/common/sys/pcie.h index f86b286dd6..6ffa4ac033 100644 --- a/usr/src/uts/common/sys/pcie.h +++ b/usr/src/uts/common/sys/pcie.h @@ -19,7 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2008 Sun Microsystems, Inc. All rights reserved. + * Copyright 2009 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ @@ -62,7 +62,7 @@ extern "C" { #define PCIE_PCIECAP_VER_1_0 0x1 /* PCI-E spec 1.0 */ #define PCIE_PCIECAP_VER_MASK 0xF /* Version Mask */ #define PCIE_PCIECAP_DEV_TYPE_PCIE_DEV 0x00 /* PCI-E Endpont Device */ -#define PCIE_PCIECAP_DEV_TYPE_PCI_DEV 0x10 /* Leg PCI Endpont Device */ +#define PCIE_PCIECAP_DEV_TYPE_PCI_DEV 0x10 /* "Leg PCI" Endpont Device */ #define PCIE_PCIECAP_DEV_TYPE_ROOT 0x40 /* Root Port of Root Complex */ #define PCIE_PCIECAP_DEV_TYPE_UP 0x50 /* Upstream Port of Switch */ #define PCIE_PCIECAP_DEV_TYPE_DOWN 0x60 /* Downstream Port of Switch */ @@ -216,7 +216,9 @@ extern "C" { #define PCIE_LINKCAP_DLL_ACTIVE_REP_CAPABLE 0x100000 /* DLL Active */ /* Capable bit */ -#define PCIE_LINKCAP_PORT_NUMBER 0xF0000000 /* Port Number */ +#define PCIE_LINKCAP_PORT_NUMBER 0xFF000000 /* Port Number */ +#define PCIE_LINKCAP_PORT_NUMBER_SHIFT 24 /* Port Number Shift */ +#define PCIE_LINKCAP_PORT_NUMBER_MASK 0xFF /* Port Number Mask */ /* * Link Control Register (2 bytes) @@ -590,7 +592,7 @@ typedef uint16_t pcie_req_id_t; #define PCIE_REQ_ID_BUS_SHIFT 8 #define PCIE_REQ_ID_BUS_MASK 0xFF00 #define PCIE_REQ_ID_DEV_SHIFT 3 -#define PCIE_REQ_ID_DEV_MASK 0x00F1 +#define PCIE_REQ_ID_DEV_MASK 0x00F8 #define PCIE_REQ_ID_FUNC_SHIFT 0 #define PCIE_REQ_ID_FUNC_MASK 0x0007 |