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authorJohn Sonnenschein <johns@joyent.com>2012-05-17 18:26:57 +0000
committerJohn Sonnenschein <johns@joyent.com>2012-05-17 18:26:57 +0000
commit04b244dd661c24b510ac22936decfc0972d202d3 (patch)
tree3ebfef98afc303fddf3415d6fba64e8682f495e8 /usr/src/uts/i86pc/os/mp_machdep.c
parenteac250589e41f1b705e1b7427b02b3379aac9f9e (diff)
parenta69187741b83640a90dd8586195456dd50c016a8 (diff)
downloadillumos-joyent-20120517.tar.gz
Merge git.joyent.com:illumos-joyent20120517
Diffstat (limited to 'usr/src/uts/i86pc/os/mp_machdep.c')
-rw-r--r--usr/src/uts/i86pc/os/mp_machdep.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/usr/src/uts/i86pc/os/mp_machdep.c b/usr/src/uts/i86pc/os/mp_machdep.c
index d7aab080a6..7062df90ff 100644
--- a/usr/src/uts/i86pc/os/mp_machdep.c
+++ b/usr/src/uts/i86pc/os/mp_machdep.c
@@ -245,6 +245,11 @@ pg_plat_hw_shared(cpu_t *cp, pghw_type_t hw)
} else {
return (0);
}
+ case PGHW_FPU:
+ if (cpuid_get_cores_per_compunit(cp) > 1)
+ return (1);
+ else
+ return (0);
case PGHW_PROCNODE:
if (cpuid_get_procnodes_per_pkg(cp) > 1)
return (1);
@@ -306,6 +311,8 @@ pg_plat_hw_instance_id(cpu_t *cpu, pghw_type_t hw)
return (cpuid_get_coreid(cpu));
case PGHW_CACHE:
return (cpuid_get_last_lvl_cacheid(cpu));
+ case PGHW_FPU:
+ return (cpuid_get_compunitid(cpu));
case PGHW_PROCNODE:
return (cpuid_get_procnodeid(cpu));
case PGHW_CHIP:
@@ -331,6 +338,7 @@ pg_plat_hw_rank(pghw_type_t hw1, pghw_type_t hw2)
static pghw_type_t hw_hier[] = {
PGHW_IPIPE,
PGHW_CACHE,
+ PGHW_FPU,
PGHW_PROCNODE,
PGHW_CHIP,
PGHW_POW_IDLE,
@@ -361,8 +369,13 @@ pg_plat_cmt_policy(pghw_type_t hw)
/*
* For shared caches, also load balance across them to
* maximize aggregate cache capacity
+ *
+ * On AMD family 0x15 CPUs, cores come in pairs called
+ * compute units, sharing the FPU and the I$ and L2
+ * caches. Use balancing and cache affinity.
*/
switch (hw) {
+ case PGHW_FPU:
case PGHW_CACHE:
return (CMT_BALANCE|CMT_AFFINITY);
default: