6715149 T-State support for intel based processors

--HG--
rename : usr/src/uts/i86pc/io/cpu_acpi.c => usr/src/uts/i86pc/io/cpudrv/cpu_acpi.c
rename : usr/src/uts/i86pc/io/cpudrv_plat.c => usr/src/uts/i86pc/io/cpudrv/cpudrv_mach.c
rename : usr/src/uts/i86pc/io/pwrnow.c => usr/src/uts/i86pc/io/cpudrv/pwrnow.c
rename : usr/src/uts/i86pc/io/speedstep.c => usr/src/uts/i86pc/io/cpudrv/speedstep.c
rename : usr/src/uts/i86pc/sys/cpudrv_plat.h => usr/src/uts/i86pc/sys/cpudrv_mach.h
rename : usr/src/uts/sun4u/io/cpudrv_plat.c => usr/src/uts/sun4u/io/cpudrv_mach.c
rename : usr/src/uts/sun4u/sys/cpudrv_plat.h => usr/src/uts/sun4u/sys/cpudrv_mach.h

7 files changed, 373 insertions, 190 deletions

diff --git a/usr/src/uts/i86pc/sys/cpu_acpi.h b/usr/src/uts/i86pc/sys/cpu_acpi.h
index da9e23d9b9..8a5d264028 100644
--- a/usr/src/uts/i86pc/sys/cpu_acpi.h
+++ b/usr/src/uts/i86pc/sys/cpu_acpi.h
@@ -19,15 +19,13 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
 #ifndef	_CPU_ACPI_H
 #define	_CPU_ACPI_H
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/acpi/acpi.h>
 #include <sys/acpi/acresrc.h>
 #include <sys/acpi/acglobal.h>
@@ -37,56 +35,96 @@
 extern "C" {
 #endif
 
+/*
+ * P-state related macros
+ */
 #define	CPU_ACPI_PPC(sp)		sp->cs_ppc
 #define	CPU_ACPI_PSD(sp)		sp->cs_psd
 #define	CPU_ACPI_PCT(sp)		sp->cs_pct
 #define	CPU_ACPI_PCT_CTRL(sp)		&sp->cs_pct[0]
 #define	CPU_ACPI_PCT_STATUS(sp)		&sp->cs_pct[1]
-#define	CPU_ACPI_PSTATES(sp)		sp->cs_pstates->pss_pstates
-#define	CPU_ACPI_PSTATES_COUNT(sp)	sp->cs_pstates->pss_count
+#define	CPU_ACPI_PSTATES(sp)		sp->cs_pstates.ss_states
+#define	CPU_ACPI_PSTATES_COUNT(sp)	sp->cs_pstates.ss_count
 
-#define	CPU_ACPI_PSTATE(sp, i)		&sp->cs_pstates->pss_pstates[i]
 #define	CPU_ACPI_FREQ(pstate)		pstate->ps_freq
-#define	CPU_ACPI_TRANSLAT(pstate)	pstate->ps_translat
-#define	CPU_ACPI_CTRL(pstate)		pstate->ps_ctrl
-#define	CPU_ACPI_STAT(pstate)		pstate->ps_state
+#define	CPU_ACPI_PSTATE_TRANSLAT(pstate) pstate->ps_translat
+#define	CPU_ACPI_PSTATE_CTRL(pstate)	pstate->ps_ctrl
+#define	CPU_ACPI_PSTATE_STAT(pstate)	pstate->ps_state
+
+/*
+ * T-state related macros
+ */
+#define	CPU_ACPI_TPC(sp)		sp->cs_tpc
+#define	CPU_ACPI_TSD(sp)		sp->cs_tsd
+#define	CPU_ACPI_PTC(sp)		sp->cs_ptc
+#define	CPU_ACPI_PTC_CTRL(sp)		&sp->cs_ptc[0]
+#define	CPU_ACPI_PTC_STATUS(sp)		&sp->cs_ptc[1]
+#define	CPU_ACPI_TSTATES(sp)		sp->cs_tstates.ss_states
+#define	CPU_ACPI_TSTATES_COUNT(sp)	sp->cs_tstates.ss_count
+
+#define	CPU_ACPI_FREQPER(tstate)	tstate->ts_freqper
+#define	CPU_ACPI_TSTATE_TRANSLAT(tstate) tstate->ts_translat
+#define	CPU_ACPI_TSTATE_CTRL(tstate)	tstate->ts_ctrl
+#define	CPU_ACPI_TSTATE_STAT(tstate)	tstate->ts_state
 
 #define	CPU_ACPI_NONE_CACHED		0x00
 #define	CPU_ACPI_PCT_CACHED		0x01
 #define	CPU_ACPI_PSS_CACHED		0x02
 #define	CPU_ACPI_PSD_CACHED		0x04
 #define	CPU_ACPI_PPC_CACHED		0x08
+#define	CPU_ACPI_PTC_CACHED		0x10
+#define	CPU_ACPI_TSS_CACHED		0x20
+#define	CPU_ACPI_TSD_CACHED		0x40
+#define	CPU_ACPI_TPC_CACHED		0x80
 
 #define	CPU_ACPI_IS_OBJ_CACHED(sp, obj)	(sp->cpu_acpi_cached & obj)
 #define	CPU_ACPI_OBJ_IS_CACHED(sp, obj)	(sp->cpu_acpi_cached |= obj)
 #define	CPU_ACPI_OBJ_IS_NOT_CACHED(sp, obj) (sp->cpu_acpi_cached &= ~obj)
 
+#define	CPU_ACPI_PSTATES_SIZE(cnt) (cnt * sizeof (cpu_acpi_pstate_t))
+#define	CPU_ACPI_PSS_CNT (sizeof (cpu_acpi_pstate_t) / sizeof (uint32_t))
+#define	CPU_ACPI_TSTATES_SIZE(cnt) (cnt * sizeof (cpu_acpi_tstate_t))
+#define	CPU_ACPI_TSS_CNT (sizeof (cpu_acpi_tstate_t) / sizeof (uint32_t))
+
 /*
- * Container for _PSD information
+ * CPU Domain Coordination Types
  */
-typedef struct cpu_acpi_psd
+#define	CPU_ACPI_SW_ALL	0xfc
+#define	CPU_ACPI_SW_ANY	0xfd
+#define	CPU_ACPI_HW_ALL	0xfe
+
+/*
+ * Container for ACPI processor state dependency information
+ */
+typedef struct cpu_acpi_state_dependency
 {
-	uint8_t pd_entries;
-	uint8_t pd_revision;
-	uint32_t pd_domain;
-	uint32_t pd_type;
-	uint32_t pd_num;
-} cpu_acpi_psd_t;
+	uint8_t sd_entries;
+	uint8_t sd_revision;
+	uint32_t sd_domain;
+	uint32_t sd_type;
+	uint32_t sd_num;
+} cpu_acpi_state_dependency_t;
+
+typedef cpu_acpi_state_dependency_t cpu_acpi_psd_t;
+typedef cpu_acpi_state_dependency_t cpu_acpi_tsd_t;
 
 /*
- * Container for _PCT information
+ * Container for ACPI processor control register information
  */
-typedef struct cpu_acpi_pct
+typedef struct cpu_acpi_ctrl_regs
 {
-	uint8_t pc_addrspace_id;
-	uint8_t pc_width;
-	uint8_t pc_offset;
-	uint8_t pc_asize;
-	ACPI_IO_ADDRESS pc_address;
-} cpu_acpi_pct_t;
+	uint8_t cr_addrspace_id;
+	uint8_t cr_width;
+	uint8_t cr_offset;
+	uint8_t cr_asize;
+	ACPI_IO_ADDRESS cr_address;
+} cpu_acpi_ctrl_regs_t;
+
+typedef cpu_acpi_ctrl_regs_t cpu_acpi_pct_t;
+typedef cpu_acpi_ctrl_regs_t cpu_acpi_ptc_t;
 
 /*
- * Containers for _PSS information
+ * Container for ACPI _PSS information
  */
 typedef struct cpu_acpi_pstate
 {
@@ -98,12 +136,30 @@ typedef struct cpu_acpi_pstate
 	uint32_t ps_state;
 } cpu_acpi_pstate_t;
 
-typedef struct cpu_acpi_pstates {
-	cpu_acpi_pstate_t *pss_pstates;
-	uint32_t pss_count;
-} cpu_acpi_pstates_t;
+/*
+ * Container for _TSS information
+ */
+typedef struct cpu_acpi_tstate
+{
+	uint32_t ts_freqper;
+	uint32_t ts_disp;
+	uint32_t ts_translat;
+	uint32_t ts_ctrl;
+	uint32_t ts_state;
+
+} cpu_acpi_tstate_t;
+
+typedef struct cpu_acpi_supported_states {
+	void *ss_states;
+	uint32_t ss_count;
+} cpu_acpi_supported_states_t;
 
+typedef cpu_acpi_supported_states_t cpu_acpi_pstates_t;
+typedef cpu_acpi_supported_states_t cpu_acpi_tstates_t;
+
+typedef int cpu_acpi_present_capabilities_t;
 typedef int cpu_acpi_ppc_t;
+typedef int cpu_acpi_tpc_t;
 
 /*
  * Container for cached ACPI data.
@@ -112,22 +168,25 @@ typedef struct cpu_acpi_state {
 	ACPI_HANDLE cs_handle;
 	dev_info_t *cs_dip;
 	uint_t cpu_acpi_cached;
-	cpu_acpi_pstates_t *cs_pstates;
+	cpu_acpi_pstates_t cs_pstates;
 	cpu_acpi_pct_t cs_pct[2];
 	cpu_acpi_psd_t cs_psd;
 	cpu_acpi_ppc_t cs_ppc;
+	cpu_acpi_tstates_t cs_tstates;
+	cpu_acpi_ptc_t cs_ptc[2];
+	cpu_acpi_tsd_t cs_tsd;
+	cpu_acpi_tpc_t cs_tpc;
 } cpu_acpi_state_t;
 
 typedef cpu_acpi_state_t *cpu_acpi_handle_t;
 
-extern cpu_acpi_handle_t cpu_acpi_init(dev_info_t *);
-extern void cpu_acpi_fini(cpu_acpi_handle_t);
-extern int cpu_acpi_cache_pstates(cpu_acpi_handle_t);
-extern int cpu_acpi_cache_pct(cpu_acpi_handle_t);
-extern int cpu_acpi_cache_psd(cpu_acpi_handle_t);
 extern void cpu_acpi_cache_ppc(cpu_acpi_handle_t);
-extern int cpu_acpi_cache_data(cpu_acpi_handle_t);
-extern void cpu_acpi_install_ppc_handler(cpu_acpi_handle_t,
+extern void cpu_acpi_cache_tpc(cpu_acpi_handle_t);
+extern int cpu_acpi_cache_pstate_data(cpu_acpi_handle_t);
+extern void cpu_acpi_free_pstate_data(cpu_acpi_handle_t);
+extern int cpu_acpi_cache_tstate_data(cpu_acpi_handle_t);
+extern void cpu_acpi_free_tstate_data(cpu_acpi_handle_t);
+extern void cpu_acpi_install_notify_handler(cpu_acpi_handle_t,
     ACPI_NOTIFY_HANDLER, dev_info_t *);
 extern int cpu_acpi_write_pdc(cpu_acpi_handle_t, uint32_t, uint32_t,
     uint32_t *);
@@ -135,6 +194,8 @@ extern int cpu_acpi_write_port(ACPI_IO_ADDRESS, uint32_t, uint32_t);
 extern int cpu_acpi_read_port(ACPI_IO_ADDRESS, uint32_t *, uint32_t);
 extern uint_t cpu_acpi_get_speeds(cpu_acpi_handle_t, int **);
 extern void cpu_acpi_free_speeds(int *, uint_t);
+extern cpu_acpi_handle_t cpu_acpi_init(dev_info_t *);
+extern void cpu_acpi_fini(cpu_acpi_handle_t);
 
 #ifdef __cplusplus
 }
diff --git a/usr/src/uts/i86pc/sys/cpudrv_mach.h b/usr/src/uts/i86pc/sys/cpudrv_mach.h
new file mode 100644
index 0000000000..2657ec3be0
--- /dev/null
+++ b/usr/src/uts/i86pc/sys/cpudrv_mach.h
@@ -0,0 +1,211 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_CPUDRV_MACH_H
+#define	_SYS_CPUDRV_MACH_H
+
+#include <sys/cpuvar.h>
+#include <sys/cpupm.h>
+#include <sys/cpu_acpi.h>
+#include <sys/cpudrv.h>
+#include <sys/ksynch.h>
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+/*
+ * We currently refuse to power manage if the CPU in not ready to
+ * take cross calls (cross calls fail silently if CPU is not ready
+ * for it).
+ */
+extern cpuset_t cpu_ready_set;
+#define	CPUDRV_PM_XCALL_IS_READY(cpuid) CPU_IN_SET(cpu_ready_set, (cpuid))
+
+/*
+ * An error attaching any of the devices results in disabling
+ * CPU power management.
+ */
+#define	CPUDRV_PM_DISABLE() cpupm_disable(CPUPM_ALL_STATES)
+
+/*
+ * If no power management states are enabled, then CPU power
+ * management is disabled.
+ */
+#define	CPUDRV_PM_DISABLED() \
+	(!cpupm_is_enabled(CPUPM_P_STATES) && !cpupm_is_enabled(CPUPM_T_STATES))
+
+/*
+ * Is P-state management enabled?
+ */
+#define	CPUDRV_PM_POWER_ENABLED(cpudsp) \
+	(((cpudrv_mach_state_t *)cpudsp->mach_state)->caps & CPUDRV_P_STATES)
+
+/*
+ * We're about to exit the _PPC thread so reset tag.
+ */
+#define	CPUDRV_PM_RESET_GOVERNOR_THREAD(cpupm) { \
+	if (curthread == cpupm->pm_governor_thread) \
+		cpupm->pm_governor_thread = NULL; \
+}
+
+/*
+ * Install a _PPC/_TPC change notification handler.
+ */
+#define	CPUDRV_PM_INSTALL_MAX_CHANGE_HANDLER(cpudsp, dip) \
+	cpudrv_pm_install_notify_handler(cpudsp, dip);
+
+/*
+ * Redefine the topspeed.
+ */
+#define	CPUDRV_PM_REDEFINE_TOPSPEED(dip) cpudrv_pm_redefine_topspeed(dip)
+
+/*
+ * Set callbacks so that PPM can callback into CPUDRV
+ */
+#define	CPUDRV_PM_SET_PPM_CALLBACKS() { \
+	cpupm_get_topspeed = cpudrv_pm_get_topspeed; \
+	cpupm_set_topspeed = cpudrv_pm_set_topspeed; \
+}
+
+/*
+ * ACPI provides the supported speeds.
+ */
+#define	CPUDRV_PM_GET_SPEEDS(cpudsp, speeds, nspeeds) \
+	nspeeds = cpudrv_pm_get_speeds(cpudsp, &speeds);
+#define	CPUDRV_PM_FREE_SPEEDS(speeds, nspeeds) \
+	cpudrv_pm_free_speeds(speeds, nspeeds);
+
+/*
+ * Convert speed to Hz.
+ */
+#define	CPUDRV_PM_SPEED_HZ(unused, mhz) ((uint64_t)mhz * 1000000)
+
+/*
+ * Compute the idle cnt percentage for a given speed.
+ */
+#define	CPUDRV_PM_IDLE_CNT_PERCENT(hwm, speeds, i) \
+	(100 - (((100 - hwm) * speeds[0]) / speeds[i]))
+
+/*
+ * Compute the user cnt percentage for a given speed.
+ */
+#define	CPUDRV_PM_USER_CNT_PERCENT(hwm, speeds, i) \
+	((hwm * speeds[i]) / speeds[i - 1]);
+
+/*
+ * pm-components property defintions for this machine type.
+ *
+ * Fully constructed pm-components property should be an array of
+ * strings that look something like:
+ *
+ * pmc[0] = "NAME=CPU Speed"
+ * pmc[1] = "1=2800MHz"
+ * pmc[2] = "2=3200MHz"
+ *
+ * The amount of memory needed for each string is:
+ * 	digits for power level + '=' +  digits for freq + 'MHz' + '\0'
+ */
+#define	CPUDRV_PM_COMP_SIZE() \
+	(CPUDRV_PM_COMP_MAX_DIG + 1 + CPUDRV_PM_COMP_MAX_DIG + 3 + 1);
+#define	CPUDRV_PM_COMP_SPEED(cpupm, cur_spd) cur_spd->speed;
+#define	CPUDRV_PM_COMP_SPRINT(pmc, cpupm, cur_spd, comp_spd) \
+	(void) sprintf(pmc, "%d=%dMHz", cur_spd->pm_level, comp_spd);
+
+/*
+ * T-State domain list
+ */
+typedef struct cpudrv_tstate_domain_node {
+	struct cpudrv_tstate_domain_node	*tdn_next;
+	struct cpudrv_tstate_domain		*tdn_domain;
+	cpudrv_devstate_t			*tdn_cpudsp;
+} cpudrv_tstate_domain_node_t;
+
+typedef struct cpudrv_tstate_domain {
+	struct cpudrv_tstate_domain	*td_next;
+	cpudrv_tstate_domain_node_t	*td_node;
+	uint32_t			td_domain;
+	uint32_t			td_type;
+	kmutex_t			td_lock;
+} cpudrv_tstate_domain_t;
+
+extern cpudrv_tstate_domain_t *cpudrv_tstate_domains;
+
+/*
+ * Different processor families have their own technologies for supporting
+ * CPU power management (i.e., Intel has Enhanced SpeedStep for some of it's
+ * processors and AMD has PowerNow! for some of it's processors). We support
+ * these different technologies via modules that export the interfaces
+ * described below.
+ *
+ * If a module implements the technology that should be used to manage
+ * the current CPU device, then the cpups_init() module should return
+ * succesfully (i.e., return code of 0) and perform any initialization
+ * such that future power transistions can be performed by calling
+ * the cpups_power() interface(). And the cpups_fini() interface can be
+ * used to free any resources allocated by cpups_init().
+ */
+typedef struct cpudrv_pstate_ops {
+	char	*cpups_label;
+	int	(*cpups_init)(cpudrv_devstate_t *);
+	void	(*cpups_fini)(cpudrv_devstate_t *);
+	int	(*cpups_power)(cpudrv_devstate_t *, uint32_t);
+} cpudrv_pstate_ops_t;
+
+/*
+ * T-state support.
+ */
+typedef struct cpudrv_tstate_ops {
+	char	*cputs_label;
+	int	(*cputs_init)(cpudrv_devstate_t *);
+	void	(*cputs_fini)(cpudrv_devstate_t *);
+	int	(*cputs_throttle)(cpudrv_devstate_t *,  uint32_t);
+} cpudrv_tstate_ops_t;
+
+typedef struct cpudrv_mach_state {
+	void			*acpi_handle;
+	cpudrv_pstate_ops_t	*cpupm_pstate_ops;
+	cpudrv_tstate_ops_t	*cpupm_tstate_ops;
+	cpudrv_tstate_domain_node_t *tstate_domain_node;
+	uint32_t		pstate;
+	uint32_t		tstate;
+	uint32_t		caps;
+} cpudrv_mach_state_t;
+
+#define	CPUDRV_NO_STATES	0x00
+#define	CPUDRV_P_STATES		0x01
+#define	CPUDRV_T_STATES		0x02
+
+extern uint_t cpudrv_pm_get_speeds(cpudrv_devstate_t *, int **);
+extern void cpudrv_pm_free_speeds(int *, uint_t);
+extern void cpudrv_pm_set_topspeed(void *, int);
+extern int cpudrv_pm_get_topspeed(void *);
+extern void cpudrv_pm_redefine_topspeed(void *);
+extern void cpudrv_pm_install_notify_handler(cpudrv_devstate_t *, dev_info_t *);
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* _SYS_CPUDRV_MACH_H */
diff --git a/usr/src/uts/i86pc/sys/cpudrv_plat.h b/usr/src/uts/i86pc/sys/cpudrv_plat.h
deleted file mode 100644
index 73d85ff814..0000000000
--- a/usr/src/uts/i86pc/sys/cpudrv_plat.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-/*
- * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
- * Use is subject to license terms.
- */
-
-#ifndef _SYS_CPUDRV_PLAT_H
-#define	_SYS_CPUDRV_PLAT_H
-
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#include <sys/cpuvar.h>
-#include <sys/cpupm.h>
-#include <sys/cpu_acpi.h>
-
-#ifdef  __cplusplus
-extern "C" {
-#endif
-
-/*
- * We currently refuse to power manage if the CPU in not ready to
- * take cross calls (cross calls fail silently if CPU is not ready
- * for it).
- */
-extern cpuset_t cpu_ready_set;
-#define	CPUDRV_PM_XCALL_IS_READY(cpuid) CPU_IN_SET(cpu_ready_set, (cpuid))
-
-/*
- * An error attaching any of the devices results in disabling
- * CPU power management.
- */
-#define	CPUDRV_PM_DISABLE() cpupm_enable(B_FALSE)
-
-/*
- * We're about to exit the _PPC thread so reset tag.
- */
-#define	CPUDRV_PM_RESET_THROTTLE_THREAD(cpupm) { \
-	if (curthread == cpupm->pm_throttle_thread) \
-		cpupm->pm_throttle_thread = NULL; \
-}
-
-/*
- * Install a _PPC change notification handler.
- */
-#define	CPUDRV_PM_INSTALL_TOPSPEED_CHANGE_HANDLER(cpudsp, dip) \
-	cpu_acpi_install_ppc_handler(cpudsp->acpi_handle, \
-	    cpudrv_pm_ppc_notify_handler, dip);
-
-/*
- * Redefine the topspeed.
- */
-#define	CPUDRV_PM_REDEFINE_TOPSPEED(dip) cpudrv_pm_redefine_topspeed(dip)
-
-/*
- * Set callbacks so that PPM can callback into CPUDRV
- */
-#define	CPUDRV_PM_SET_PPM_CALLBACKS() { \
-	cpupm_get_topspeed = cpudrv_pm_get_topspeed; \
-	cpupm_set_topspeed = cpudrv_pm_set_topspeed; \
-}
-
-/*
- * ACPI provides the supported speeds.
- */
-#define	CPUDRV_PM_GET_SPEEDS(cpudsp, speeds, nspeeds) \
-	nspeeds = cpu_acpi_get_speeds(cpudsp->acpi_handle, &speeds);
-#define	CPUDRV_PM_FREE_SPEEDS(speeds, nspeeds) \
-	cpu_acpi_free_speeds(speeds, nspeeds);
-
-/*
- * Convert speed to Hz.
- */
-#define	CPUDRV_PM_SPEED_HZ(unused, mhz) ((uint64_t)mhz * 1000000)
-
-/*
- * Compute the idle cnt percentage for a given speed.
- */
-#define	CPUDRV_PM_IDLE_CNT_PERCENT(hwm, speeds, i) \
-	(100 - (((100 - hwm) * speeds[0]) / speeds[i]))
-
-/*
- * Compute the user cnt percentage for a given speed.
- */
-#define	CPUDRV_PM_USER_CNT_PERCENT(hwm, speeds, i) \
-	((hwm * speeds[i]) / speeds[i - 1]);
-
-/*
- * pm-components property defintions for this platform.
- *
- * Fully constructed pm-components property should be an array of
- * strings that look something like:
- *
- * pmc[0] = "NAME=CPU Speed"
- * pmc[1] = "1=2800MHz"
- * pmc[2] = "2=3200MHz"
- *
- * The amount of memory needed for each string is:
- * 	digits for power level + '=' +  digits for freq + 'MHz' + '\0'
- */
-#define	CPUDRV_PM_COMP_SIZE() \
-	(CPUDRV_PM_COMP_MAX_DIG + 1 + CPUDRV_PM_COMP_MAX_DIG + 3 + 1);
-#define	CPUDRV_PM_COMP_SPEED(cpupm, cur_spd) cur_spd->speed;
-#define	CPUDRV_PM_COMP_SPRINT(pmc, cpupm, cur_spd, comp_spd) \
-	(void) sprintf(pmc, "%d=%dMHz", cur_spd->pm_level, comp_spd);
-
-extern void cpudrv_pm_set_topspeed(void *, int);
-extern int cpudrv_pm_get_topspeed(void *);
-extern void cpudrv_pm_redefine_topspeed(void *);
-extern void cpudrv_pm_ppc_notify_handler(ACPI_HANDLE, UINT32, void *);
-
-#ifdef  __cplusplus
-}
-#endif
-
-#endif /* _SYS_CPUDRV_PLAT_H */
diff --git a/usr/src/uts/i86pc/sys/cpudrv_throttle.h b/usr/src/uts/i86pc/sys/cpudrv_throttle.h
new file mode 100644
index 0000000000..ae4d352c14
--- /dev/null
+++ b/usr/src/uts/i86pc/sys/cpudrv_throttle.h
@@ -0,0 +1,41 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_CPUDRV_THROTTLE_H
+#define	_CPUDRV_THROTTLE_H
+
+#include <sys/cpudrv_mach.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+cpudrv_tstate_ops_t cpudrv_throttle_ops;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* _CPUDRV_THROTTLE_H */
diff --git a/usr/src/uts/i86pc/sys/cpupm.h b/usr/src/uts/i86pc/sys/cpupm.h
index eb32f3e494..2510a0fb60 100644
--- a/usr/src/uts/i86pc/sys/cpupm.h
+++ b/usr/src/uts/i86pc/sys/cpupm.h
@@ -19,15 +19,13 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
 #ifndef	_CPUPM_H
 #define	_CPUPM_H
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -51,6 +49,15 @@ typedef struct cpupm_cpu_dependency {
 } cpupm_cpu_dependency_t;
 
 /*
+ * If any states are added, then make sure to add them to
+ * CPUPM_ALL_STATES.
+ */
+#define	CPUPM_NO_STATES		0x00
+#define	CPUPM_P_STATES		0x01
+#define	CPUPM_T_STATES		0x02
+#define	CPUPM_ALL_STATES	(CPUPM_P_STATES | CPUPM_T_STATES)
+
+/*
  * Callbacks used for CPU power management.
  */
 extern void (*cpupm_rebuild_cpu_domains)(void);
@@ -71,7 +78,8 @@ extern void cpupm_free_cpu_dependencies();
  *
  */
 extern boolean_t cpupm_is_ready();
-extern void cpupm_enable(boolean_t);
+extern boolean_t cpupm_is_enabled(uint32_t);
+extern void cpupm_disable(uint32_t);
 extern void cpupm_post_startup();
 
 #ifdef __cplusplus
diff --git a/usr/src/uts/i86pc/sys/pwrnow.h b/usr/src/uts/i86pc/sys/pwrnow.h
index 1ea3ccf66d..1e3cc24e3f 100644
--- a/usr/src/uts/i86pc/sys/pwrnow.h
+++ b/usr/src/uts/i86pc/sys/pwrnow.h
@@ -19,24 +19,22 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
 #ifndef	_PWRNOW_H
 #define	_PWRNOW_H
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#include <sys/cpudrv.h>
+#include <sys/cpudrv_mach.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-extern int pwrnow_init(cpudrv_devstate_t *);
-extern void pwrnow_fini(cpudrv_devstate_t *);
-extern int pwrnow_power(cpudrv_devstate_t *, uint32_t);
+boolean_t pwrnow_supported();
+
+cpudrv_pstate_ops_t pwrnow_ops;
 
 #ifdef __cplusplus
 }
diff --git a/usr/src/uts/i86pc/sys/speedstep.h b/usr/src/uts/i86pc/sys/speedstep.h
index 32f593f679..f9debb2758 100644
--- a/usr/src/uts/i86pc/sys/speedstep.h
+++ b/usr/src/uts/i86pc/sys/speedstep.h
@@ -19,24 +19,22 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
 #ifndef	_SPEEDSTEP_H
 #define	_SPEEDSTEP_H
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#include <sys/cpudrv.h>
+#include <sys/cpudrv_mach.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-extern int speedstep_init(cpudrv_devstate_t *);
-extern void speedstep_fini(cpudrv_devstate_t *);
-extern int speedstep_power(cpudrv_devstate_t *, uint32_t);
+boolean_t speedstep_supported(uint_t, uint_t);
+
+cpudrv_pstate_ops_t speedstep_ops;
 
 #ifdef __cplusplus
 }