[illumos-gate merge]release-20201105

commit 059f070059c50b83e8b46b39b4dde67bf2feb1dc
    13236 Want Zen 3 socket information
commit e9abe9d6424a9213df11b3243f6957e6a0b91e48
    13235 amdzen(7D) support for Zen 3
commit 5edbd2fec7b63b423df5bd21c4b0f7b775123a40
    13238 vaes, vpclmulqdq should be plumbed through isainfo
    13239 umip, etc. are incorrectly conditioned in cpuid.c
commit c4b98ceff2f78fc5bb2f6bbe2e76627f04ef66f5
    13237 Plumb through PCID on AMD

2 files changed, 77 insertions, 17 deletions

diff --git a/usr/src/uts/i86pc/os/cpuid.c b/usr/src/uts/i86pc/os/cpuid.c
index ae450f1d9b..6f54dee7f9 100644
--- a/usr/src/uts/i86pc/os/cpuid.c
+++ b/usr/src/uts/i86pc/os/cpuid.c
@@ -1437,7 +1437,9 @@ static char *x86_feature_names[NUM_X86_FEATURES] = {
 	"pkg_thermal",
 	"tsx_ctrl",
 	"taa_no",
-	"ppin"
+	"ppin",
+	"vaes",
+	"vpclmulqdq"
 };
 
 boolean_t
@@ -3595,6 +3597,8 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
 			ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_ALL_AVX512;
 			ecp->cp_ecx &= ~CPUID_INTC_ECX_7_0_ALL_AVX512;
 			ecp->cp_edx &= ~CPUID_INTC_EDX_7_0_ALL_AVX512;
+			ecp->cp_ecx &= ~CPUID_INTC_ECX_7_0_VAES;
+			ecp->cp_ecx &= ~CPUID_INTC_ECX_7_0_VPCLMULQDQ;
 		}
 
 		if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_SMEP)
@@ -3622,10 +3626,17 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
 		if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_CLFLUSHOPT)
 			add_x86_feature(featureset, X86FSET_CLFLUSHOPT);
 
-		if (cpi->cpi_vendor == X86_VENDOR_Intel) {
-			if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_INVPCID)
-				add_x86_feature(featureset, X86FSET_INVPCID);
+		if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_INVPCID)
+			add_x86_feature(featureset, X86FSET_INVPCID);
+
+		if (ecp->cp_ecx & CPUID_INTC_ECX_7_0_UMIP)
+			add_x86_feature(featureset, X86FSET_UMIP);
+		if (ecp->cp_ecx & CPUID_INTC_ECX_7_0_PKU)
+			add_x86_feature(featureset, X86FSET_PKU);
+		if (ecp->cp_ecx & CPUID_INTC_ECX_7_0_OSPKE)
+			add_x86_feature(featureset, X86FSET_OSPKE);
 
+		if (cpi->cpi_vendor == X86_VENDOR_Intel) {
 			if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_MPX)
 				add_x86_feature(featureset, X86FSET_MPX);
 
@@ -3717,13 +3728,6 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
 		if (cpi->cpi_std[7].cp_ebx & CPUID_INTC_EBX_7_0_SHA)
 			add_x86_feature(featureset, X86FSET_SHA);
 
-		if (cpi->cpi_std[7].cp_ecx & CPUID_INTC_ECX_7_0_UMIP)
-			add_x86_feature(featureset, X86FSET_UMIP);
-		if (cpi->cpi_std[7].cp_ecx & CPUID_INTC_ECX_7_0_PKU)
-			add_x86_feature(featureset, X86FSET_PKU);
-		if (cpi->cpi_std[7].cp_ecx & CPUID_INTC_ECX_7_0_OSPKE)
-			add_x86_feature(featureset, X86FSET_OSPKE);
-
 		if (cp->cp_ecx & CPUID_INTC_ECX_XSAVE) {
 			add_x86_feature(featureset, X86FSET_XSAVE);
 
@@ -3759,6 +3763,16 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
 				    CPUID_INTC_EBX_7_0_AVX2)
 					add_x86_feature(featureset,
 					    X86FSET_AVX2);
+
+				if (cpi->cpi_std[7].cp_ecx &
+				    CPUID_INTC_ECX_7_0_VAES)
+					add_x86_feature(featureset,
+					    X86FSET_VAES);
+
+				if (cpi->cpi_std[7].cp_ecx &
+				    CPUID_INTC_ECX_7_0_VPCLMULQDQ)
+					add_x86_feature(featureset,
+					    X86FSET_VPCLMULQDQ);
 			}
 
 			if (cpi->cpi_vendor == X86_VENDOR_Intel &&
@@ -3820,10 +3834,8 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
 		}
 	}
 
-	if (cpi->cpi_vendor == X86_VENDOR_Intel) {
-		if (cp->cp_ecx & CPUID_INTC_ECX_PCID) {
-			add_x86_feature(featureset, X86FSET_PCID);
-		}
+	if (cp->cp_ecx & CPUID_INTC_ECX_PCID) {
+		add_x86_feature(featureset, X86FSET_PCID);
 	}
 
 	if (cp->cp_ecx & CPUID_INTC_ECX_X2APIC) {
@@ -4492,6 +4504,10 @@ cpuid_pass2(cpu_t *cpu)
 					    X86FSET_AVX512NNIW);
 					remove_x86_feature(x86_featureset,
 					    X86FSET_AVX512FMAPS);
+					remove_x86_feature(x86_featureset,
+					    X86FSET_VAES);
+					remove_x86_feature(x86_featureset,
+					    X86FSET_VPCLMULQDQ);
 
 					CPI_FEATURES_ECX(cpi) &=
 					    ~CPUID_INTC_ECX_XSAVE;
@@ -4515,6 +4531,11 @@ cpuid_pass2(cpu_t *cpu)
 					CPI_FEATURES_7_0_ECX(cpi) &=
 					    ~CPUID_INTC_ECX_7_0_ALL_AVX512;
 
+					CPI_FEATURES_7_0_ECX(cpi) &=
+					    ~CPUID_INTC_ECX_7_0_VAES;
+					CPI_FEATURES_7_0_ECX(cpi) &=
+					    ~CPUID_INTC_ECX_7_0_VPCLMULQDQ;
+
 					CPI_FEATURES_7_0_EDX(cpi) &=
 					    ~CPUID_INTC_EDX_7_0_ALL_AVX512;
 
@@ -5305,6 +5326,10 @@ cpuid_pass4(cpu_t *cpu, uint_t *hwcap_out)
 					hwcap_flags_2 |= AV_386_2_AVX512_VNNI;
 				if (*ecx_7 & CPUID_INTC_ECX_7_0_AVX512VPOPCDQ)
 					hwcap_flags_2 |= AV_386_2_AVX512VPOPCDQ;
+				if (*ecx_7 & CPUID_INTC_ECX_7_0_VAES)
+					hwcap_flags_2 |= AV_386_2_VAES;
+				if (*ecx_7 & CPUID_INTC_ECX_7_0_VPCLMULQDQ)
+					hwcap_flags_2 |= AV_386_2_VPCLMULQDQ;
 
 				if (*edx_7 & CPUID_INTC_EDX_7_0_AVX5124NNIW)
 					hwcap_flags_2 |= AV_386_2_AVX512_4NNIW;
diff --git a/usr/src/uts/i86pc/os/cpuid_subr.c b/usr/src/uts/i86pc/os/cpuid_subr.c
index 83b3e115eb..faa3e75b03 100644
--- a/usr/src/uts/i86pc/os/cpuid_subr.c
+++ b/usr/src/uts/i86pc/os/cpuid_subr.c
@@ -88,10 +88,12 @@
  *		15 for family 0x17, models 30 - 3f
  *		16 for family 0x17, models 60 - 6f
  *		17 for family 0x17, models 70 - 7f
+ *		18 for family 0x19, models 00 - 0f
+ *		19 for family 0x19, models 20 - 2f
  * Second index by (model & 0x3) for family 0fh,
  * CPUID pkg bits (Fn8000_0001_EBX[31:28]) for later families.
  */
-static uint32_t amd_skts[18][8] = {
+static uint32_t amd_skts[20][8] = {
 	/*
 	 * Family 0xf revisions B through E
 	 */
@@ -361,6 +363,36 @@ static uint32_t amd_skts[18][8] = {
 		X86_SOCKET_UNKNOWN,	/* 0b110 */
 		X86_SOCKET_UNKNOWN	/* 0b111 */
 	},
+
+	/*
+	 * Family 0x19 models 00-0f	(Zen 3 - Milan)
+	 */
+#define	A_SKTS_18			18
+	{
+		X86_SOCKET_UNKNOWN,	/* 0b000 */
+		X86_SOCKET_UNKNOWN,	/* 0b001 */
+		X86_SOCKET_UNKNOWN,	/* 0b010 */
+		X86_SOCKET_UNKNOWN,	/* 0b011 */
+		X86_SOCKET_SP3,		/* 0b100 */
+		X86_SOCKET_UNKNOWN,	/* 0b101 */
+		X86_SOCKET_UNKNOWN,	/* 0b110 */
+		X86_SOCKET_STRX4	/* 0b111 */
+	},
+
+	/*
+	 * Family 0x19 models 20-2f	(Zen 3 - Vermeer)
+	 */
+#define	A_SKTS_19			19
+	{
+		X86_SOCKET_UNKNOWN,	/* 0b000 */
+		X86_SOCKET_UNKNOWN,	/* 0b001 */
+		X86_SOCKET_AM4,		/* 0b010 */
+		X86_SOCKET_UNKNOWN,	/* 0b011 */
+		X86_SOCKET_UNKNOWN,	/* 0b100 */
+		X86_SOCKET_UNKNOWN,	/* 0b101 */
+		X86_SOCKET_UNKNOWN,	/* 0b110 */
+		X86_SOCKET_UNKNOWN	/* 0b111 */
+	}
 };
 
 struct amd_sktmap_s {
@@ -401,6 +433,7 @@ static struct amd_sktmap_s amd_sktmap_strs[X86_NUM_SOCKETS_AMD + 1] = {
 	{ X86_SOCKET_SP3R2,	"SP3r2" },
 	{ X86_SOCKET_FP5,	"FP5" },
 	{ X86_SOCKET_FP6,	"FP6" },
+	{ X86_SOCKET_STRX4,	"sTRX4" },
 	{ X86_SOCKET_UNKNOWN,	"Unknown" }
 };
 
@@ -425,7 +458,9 @@ static const struct amd_skt_mapent {
 	{ 0x17, 0x10, 0x2f, A_SKTS_14 },
 	{ 0x17, 0x30, 0x3f, A_SKTS_15 },
 	{ 0x17, 0x60, 0x6f, A_SKTS_16 },
-	{ 0x17, 0x70, 0x7f, A_SKTS_17 }
+	{ 0x17, 0x70, 0x7f, A_SKTS_17 },
+	{ 0x19, 0x00, 0x0f, A_SKTS_18 },
+	{ 0x19, 0x20, 0x2f, A_SKTS_19 }
 };
 
 /*