[illumos-gate merge]

commit f8e9c7b3ba7100b047717589235b6d05ec43646c
    14925 plumb DFv4 into amdzen(4D)
commit ba215efe42e70993d3838f7af671f9d9fc0ebc33
    14936 need a better SMN addressing mechanism
commit 56726c7e321b6e5ecb2f10215f5386016547e68c
    14821 Add additional AVX512 capabilities
    14822 Need new word of hardware capabilities
    14823 aux vector feature mapping should use x86_featureset
commit f2ae17ede4a9a93585872a9aa83120497285bdd0
    14077 Want wrapper for external SMB server tests
commit 544783ca6fcbe20a0c82b42aabd4e88a9ac69e68
    14960 mountd: cleaning up some build gags
commit 153f3212c5a48deec74be10ba87dd04bc99edbbb
    14815 nvmeadm: identify support for namespace management

Conflicts:
    manifest
    usr/src/cmd/sgs/libconv/common/corenote.c
    usr/src/cmd/sgs/libconv/common/corenote.msg
    usr/src/cmd/sgs/rtld/common/globals.c
    usr/src/cmd/sgs/rtld/common/rtld.msg
    usr/src/cmd/sgs/rtld/common/setup.c
    usr/src/uts/common/exec/elf/elf.c
    usr/src/uts/common/os/exec.c
    usr/src/uts/common/sys/user.h
    usr/src/uts/intel/os/cpuid.c
    usr/src/uts/intel/os/driver_aliases

5 files changed, 151 insertions, 107 deletions

diff --git a/usr/src/uts/intel/io/amdzen/amdzen.c b/usr/src/uts/intel/io/amdzen/amdzen.c
index c3617c9742..8f430a6f6a 100644
--- a/usr/src/uts/intel/io/amdzen/amdzen.c
+++ b/usr/src/uts/intel/io/amdzen/amdzen.c
@@ -171,8 +171,14 @@ static const uint16_t amdzen_nb_ids[] = {
 	0x15d0,
 	/* Family 17h/19h Rome, Milan, Matisse, Vermeer Zen 2/Zen 3 uarch */
 	0x1480,
-	/* Family 17h/19h Renoir, Cezanne Zen 2/3 uarch) */
-	0x1630
+	/* Family 17h/19h Renoir, Cezanne, Van Gogh Zen 2/3 uarch */
+	0x1630,
+	/* Family 19h Genoa */
+	0x14a4,
+	/* Family 17h Mendocino, Family 19h Rembrandt */
+	0x14b5,
+	/* Family 19h Raphael */
+	0x14d8
 };
 
 typedef struct {
@@ -277,18 +283,19 @@ amdzen_df_read32_bcast(amdzen_t *azn, amdzen_df_t *df, const df_reg_def_t def)
 
 
 static uint32_t
-amdzen_smn_read32(amdzen_t *azn, amdzen_df_t *df, uint32_t reg)
+amdzen_smn_read32(amdzen_t *azn, amdzen_df_t *df, const smn_reg_t reg)
 {
 	VERIFY(MUTEX_HELD(&azn->azn_mutex));
-	amdzen_stub_put32(df->adf_nb, AMDZEN_NB_SMN_ADDR, reg);
+	amdzen_stub_put32(df->adf_nb, AMDZEN_NB_SMN_ADDR, SMN_REG_ADDR(reg));
 	return (amdzen_stub_get32(df->adf_nb, AMDZEN_NB_SMN_DATA));
 }
 
 static void
-amdzen_smn_write32(amdzen_t *azn, amdzen_df_t *df, uint32_t reg, uint32_t val)
+amdzen_smn_write32(amdzen_t *azn, amdzen_df_t *df, const smn_reg_t reg,
+    const uint32_t val)
 {
 	VERIFY(MUTEX_HELD(&azn->azn_mutex));
-	amdzen_stub_put32(df->adf_nb, AMDZEN_NB_SMN_ADDR, reg);
+	amdzen_stub_put32(df->adf_nb, AMDZEN_NB_SMN_ADDR, SMN_REG_ADDR(reg));
 	amdzen_stub_put32(df->adf_nb, AMDZEN_NB_SMN_DATA, val);
 }
 
@@ -321,7 +328,7 @@ amdzen_df_find(amdzen_t *azn, uint_t dfno)
  * Client functions that are used by nexus children.
  */
 int
-amdzen_c_smn_read32(uint_t dfno, uint32_t reg, uint32_t *valp)
+amdzen_c_smn_read32(uint_t dfno, const smn_reg_t reg, uint32_t *valp)
 {
 	amdzen_df_t *df;
 	amdzen_t *azn = amdzen_data;
@@ -344,7 +351,7 @@ amdzen_c_smn_read32(uint_t dfno, uint32_t reg, uint32_t *valp)
 }
 
 int
-amdzen_c_smn_write32(uint_t dfno, uint32_t reg, uint32_t val)
+amdzen_c_smn_write32(uint_t dfno, const smn_reg_t reg, const uint32_t val)
 {
 	amdzen_df_t *df;
 	amdzen_t *azn = amdzen_data;
@@ -486,17 +493,13 @@ amdzen_c_df_iter(uint_t dfno, zen_df_type_t type, amdzen_c_iter_f func,
 		}
 		break;
 	case ZEN_DF_TYPE_CCM_CPU:
-		df_type = DF_TYPE_CCM;
 		/*
-		 * In the Genoa/DFv4 timeframe, with the introduction of CXL and
-		 * related, a subtype was added here where as previously it was
-		 * always zero.
+		 * While the wording of the PPR is a little weird, the CCM still
+		 * has subtype 0 in DFv4 systems; however, what's said to be for
+		 * the CPU appears to apply to the ACM.
 		 */
-		if (df->adf_major >= 4) {
-			df_subtype = DF_CCM_SUBTYPE_CPU;
-		} else {
-			df_subtype = 0;
-		}
+		df_type = DF_TYPE_CCM;
+		df_subtype = 0;
 		break;
 	default:
 		return (EINVAL);
diff --git a/usr/src/uts/intel/io/amdzen/amdzen_client.h b/usr/src/uts/intel/io/amdzen/amdzen_client.h
index 4d937a1321..fc82c1039e 100644
--- a/usr/src/uts/intel/io/amdzen/amdzen_client.h
+++ b/usr/src/uts/intel/io/amdzen/amdzen_client.h
@@ -22,6 +22,7 @@
 
 #include <sys/types.h>
 #include <sys/amdzen/df.h>
+#include <sys/amdzen/smn.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -51,8 +52,8 @@ extern int amdzen_c_df_fabric_decomp(df_fabric_decomp_t *);
 /*
  * SMN and DF access routines.
  */
-extern int amdzen_c_smn_read32(uint_t, uint32_t, uint32_t *);
-extern int amdzen_c_smn_write32(uint_t, uint32_t, uint32_t);
+extern int amdzen_c_smn_read32(uint_t, const smn_reg_t, uint32_t *);
+extern int amdzen_c_smn_write32(uint_t, const smn_reg_t, const uint32_t);
 extern int amdzen_c_df_read32(uint_t, uint8_t, const df_reg_def_t, uint32_t *);
 extern int amdzen_c_df_read64(uint_t, uint8_t, const df_reg_def_t, uint64_t *);
 
diff --git a/usr/src/uts/intel/io/amdzen/smntemp.c b/usr/src/uts/intel/io/amdzen/smntemp.c
index aa595f5ce5..94b7aa8b83 100644
--- a/usr/src/uts/intel/io/amdzen/smntemp.c
+++ b/usr/src/uts/intel/io/amdzen/smntemp.c
@@ -11,7 +11,7 @@
 
 /*
  * Copyright 2019, Joyent, Inc.
- * Copyright 2020 Oxide Computer Company
+ * Copyright 2022 Oxide Computer Company
  */
 
 /*
@@ -31,6 +31,7 @@
 #include <sys/cpuvar.h>
 #include <sys/sensors.h>
 #include <sys/sysmacros.h>
+#include <sys/amdzen/smn.h>
 #include <amdzen_client.h>
 
 /*
@@ -39,7 +40,7 @@
  * accessed through the northbridge. They are not addresses in PCI configuration
  * space.
  */
-#define	SMN_SMU_THERMAL_CURTEMP			0x00059800
+#define	SMN_SMU_THERMAL_CURTEMP			SMN_MAKE_REG(0x00059800)
 #define	SMN_SMU_THERMAL_CURTEMP_TEMPERATURE(x)	((x) >> 21)
 #define	SMN_SMU_THERMAL_CURTEMP_RANGE_SEL		(1 << 19)
 
diff --git a/usr/src/uts/intel/io/amdzen/usmn.c b/usr/src/uts/intel/io/amdzen/usmn.c
index d5050def92..789e15830e 100644
--- a/usr/src/uts/intel/io/amdzen/usmn.c
+++ b/usr/src/uts/intel/io/amdzen/usmn.c
@@ -10,7 +10,7 @@
  */
 
 /*
- * Copyright 2021 Oxide Computer Company
+ * Copyright 2022 Oxide Computer Company
  */
 
 /*
@@ -101,7 +101,8 @@ usmn_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
 			return (EINVAL);
 		}
 
-		ret = amdzen_c_smn_read32(dfno, usr.usr_addr, &usr.usr_data);
+		ret = amdzen_c_smn_read32(dfno, SMN_MAKE_REG(usr.usr_addr),
+		    &usr.usr_data);
 		if (ret != 0) {
 			return (ret);
 		}
@@ -112,7 +113,8 @@ usmn_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
 			return (EINVAL);
 		}
 
-		ret = amdzen_c_smn_write32(dfno, usr.usr_addr, usr.usr_data);
+		ret = amdzen_c_smn_write32(dfno, SMN_MAKE_REG(usr.usr_addr),
+		    usr.usr_data);
 		if (ret != 0) {
 			return (ret);
 		}
diff --git a/usr/src/uts/intel/io/amdzen/zen_umc.c b/usr/src/uts/intel/io/amdzen/zen_umc.c
index bf5914fae6..947c17b4ff 100644
--- a/usr/src/uts/intel/io/amdzen/zen_umc.c
+++ b/usr/src/uts/intel/io/amdzen/zen_umc.c
@@ -1840,6 +1840,71 @@ zen_umc_fill_ccm_cb(const uint_t dfno, const uint32_t fabid,
 }
 
 /*
+ * This is used to fill in the common properties about a DIMM. This should occur
+ * after the rank information has been filled out. The information used is the
+ * same between DDR4 and DDR5 DIMMs. The only major difference is the register
+ * offset.
+ */
+static boolean_t
+zen_umc_fill_dimm_common(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
+    const uint_t dimmno, boolean_t ddr4)
+{
+	umc_dimm_t *dimm;
+	int ret;
+	smn_reg_t reg;
+	uint32_t val;
+	const uint32_t id = chan->chan_logid;
+
+	dimm = &chan->chan_dimms[dimmno];
+	dimm->ud_dimmno = dimmno;
+
+	if (ddr4) {
+		reg = UMC_DIMMCFG_DDR4(id, dimmno);
+	} else {
+		reg = UMC_DIMMCFG_DDR5(id, dimmno);
+	}
+	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+		dev_err(umc->umc_dip, CE_WARN, "failed to read DIMM "
+		    "configuration register %x: %d", SMN_REG_ADDR(reg), ret);
+		return (B_FALSE);
+	}
+	dimm->ud_dimmcfg_raw = val;
+
+	if (UMC_DIMMCFG_GET_X16(val) != 0) {
+		dimm->ud_width = UMC_DIMM_W_X16;
+	} else if (UMC_DIMMCFG_GET_X4(val) != 0) {
+		dimm->ud_width = UMC_DIMM_W_X4;
+	} else {
+		dimm->ud_width = UMC_DIMM_W_X8;
+	}
+
+	if (UMC_DIMMCFG_GET_3DS(val) != 0) {
+		dimm->ud_kind = UMC_DIMM_K_3DS_RDIMM;
+	} else if (UMC_DIMMCFG_GET_LRDIMM(val) != 0) {
+		dimm->ud_kind = UMC_DIMM_K_LRDIMM;
+	} else if (UMC_DIMMCFG_GET_RDIMM(val) != 0) {
+		dimm->ud_kind = UMC_DIMM_K_RDIMM;
+	} else {
+		dimm->ud_kind = UMC_DIMM_K_UDIMM;
+	}
+
+	/*
+	 * DIMM information in a UMC can be somewhat confusing. There are quite
+	 * a number of non-zero reset values that are here. Flag whether or not
+	 * we think this entry should be usable based on enabled chip-selects.
+	 */
+	for (uint_t i = 0; i < ZEN_UMC_MAX_CHAN_BASE; i++) {
+		if (dimm->ud_cs[i].ucs_base.udb_valid ||
+		    dimm->ud_cs[i].ucs_sec.udb_valid) {
+			dimm->ud_flags |= UMC_DIMM_F_VALID;
+			break;
+		}
+	}
+
+	return (B_TRUE);
+}
+
+/*
  * Fill all the information about a DDR4 DIMM. In the DDR4 UMC, some of this
  * information is on a per-chip select basis while at other times it is on a
  * per-DIMM basis.  In general, chip-selects 0/1 correspond to DIMM 0, and
@@ -1856,11 +1921,11 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
 	umc_cs_t *cs0, *cs1;
 	const uint32_t id = chan->chan_logid;
 	int ret;
-	uint32_t val, reg;
+	uint32_t val;
+	smn_reg_t reg;
 
 	ASSERT3U(dimmno, <, ZEN_UMC_MAX_DIMMS);
 	dimm = &chan->chan_dimms[dimmno];
-	dimm->ud_dimmno = dimmno;
 	cs0 = &dimm->ud_cs[0];
 	cs1 = &dimm->ud_cs[1];
 
@@ -1872,11 +1937,11 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
 	 */
 	for (uint_t i = 0; i < ZEN_UMC_MAX_CS_PER_DIMM; i++) {
 		uint64_t addr;
-		const uint32_t reginst = i + dimmno * 2;
+		const uint16_t reginst = i + dimmno * 2;
 		reg = UMC_BASE(id, reginst);
 		if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 			dev_err(umc->umc_dip, CE_WARN, "failed to read base "
-			    "register %x: %d", reg, ret);
+			    "register %x: %d", SMN_REG_ADDR(reg), ret);
 			return (B_FALSE);
 		}
 
@@ -1887,7 +1952,8 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
 		reg = UMC_BASE_SEC(id, reginst);
 		if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 			dev_err(umc->umc_dip, CE_WARN, "failed to read "
-			    "secondary base register %x: %d", reg, ret);
+			    "secondary base register %x: %d", SMN_REG_ADDR(reg),
+			    ret);
 			return (B_FALSE);
 		}
 
@@ -1899,7 +1965,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_MASK_DDR4(id, dimmno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read mask register "
-		    "%x: %d", reg, ret);
+		    "%x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 
@@ -1915,7 +1981,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_MASK_SEC_DDR4(id, dimmno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read secondary mask "
-		    "register %x: %d", reg, ret);
+		    "register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	cs0->ucs_sec_mask = (uint64_t)UMC_MASK_GET_ADDR(val) <<
@@ -1926,7 +1992,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_ADDRCFG_DDR4(id, dimmno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read address config "
-		    "register %x: %d", reg, ret);
+		    "register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 
@@ -1962,7 +2028,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_ADDRSEL_DDR4(id, dimmno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read bank address "
-		    "select register %x: %d", reg, ret);
+		    "select register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	cs0->ucs_row_hi_bit = UMC_ADDRSEL_DDR4_GET_ROW_HI(val) +
@@ -1987,7 +2053,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_COLSEL_LO_DDR4(id, dimmno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read column address "
-		    "select low register %x: %d", reg, ret);
+		    "select low register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	for (uint_t i = 0; i < ZEN_UMC_MAX_COLSEL_PER_REG; i++) {
@@ -1998,7 +2064,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_COLSEL_HI_DDR4(id, dimmno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read column address "
-		    "select high register %x: %d", reg, ret);
+		    "select high register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	for (uint_t i = 0; i < ZEN_UMC_MAX_COLSEL_PER_REG; i++) {
@@ -2017,7 +2083,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_RMSEL_DDR4(id, dimmno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read rank address "
-		    "select register %x: %d", reg, ret);
+		    "select register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	cs0->ucs_inv_msbs = UMC_RMSEL_DDR4_GET_INV_MSBE(val);
@@ -2033,7 +2099,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_RMSEL_SEC_DDR4(id, dimmno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read secondary rank "
-		    "address select register %x: %d", reg, ret);
+		    "address select register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	cs0->ucs_inv_msbs_sec = UMC_RMSEL_DDR4_GET_INV_MSBE(val);
@@ -2047,46 +2113,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
 	bcopy(cs0->ucs_rm_bits_sec, cs1->ucs_rm_bits_sec,
 	    sizeof (cs0->ucs_rm_bits_sec));
 
-	reg = UMC_DIMMCFG_DDR4(id, dimmno);
-	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
-		dev_err(umc->umc_dip, CE_WARN, "failed to read DIMM "
-		    "configuration register %x: %d", reg, ret);
-		return (B_FALSE);
-	}
-	dimm->ud_dimmcfg_raw = val;
-
-	if (UMC_DIMMCFG_GET_X16(val) != 0) {
-		dimm->ud_width = UMC_DIMM_W_X16;
-	} else if (UMC_DIMMCFG_GET_X4(val) != 0) {
-		dimm->ud_width = UMC_DIMM_W_X4;
-	} else {
-		dimm->ud_width = UMC_DIMM_W_X8;
-	}
-
-	if (UMC_DIMMCFG_GET_3DS(val) != 0) {
-		dimm->ud_kind = UMC_DIMM_K_3DS_RDIMM;
-	} else if (UMC_DIMMCFG_GET_LRDIMM(val) != 0) {
-		dimm->ud_kind = UMC_DIMM_K_LRDIMM;
-	} else if (UMC_DIMMCFG_GET_RDIMM(val) != 0) {
-		dimm->ud_kind = UMC_DIMM_K_RDIMM;
-	} else {
-		dimm->ud_kind = UMC_DIMM_K_UDIMM;
-	}
-
-	/*
-	 * DIMM information in a UMC can be somewhat confusing. There are quite
-	 * a number of non-zero reset values that are here. Flag whether or not
-	 * we think this entry should be usable based on enabled chip-selects.
-	 */
-	for (uint_t i = 0; i < ZEN_UMC_MAX_CHAN_BASE; i++) {
-		if (dimm->ud_cs[i].ucs_base.udb_valid ||
-		    dimm->ud_cs[i].ucs_sec.udb_valid) {
-			dimm->ud_flags |= UMC_DIMM_F_VALID;
-			break;
-		}
-	}
-
-	return (B_TRUE);
+	return (zen_umc_fill_dimm_common(umc, df, chan, dimmno, B_TRUE));
 }
 
 /*
@@ -2100,7 +2127,8 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
 {
 	int ret;
 	umc_cs_t *cs;
-	uint32_t reg, val;
+	uint32_t val;
+	smn_reg_t reg;
 	const uint32_t id = chan->chan_logid;
 	const uint32_t regno = dimmno * 2 + rankno;
 
@@ -2111,7 +2139,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_BASE(id, regno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read base "
-		    "register %x: %d", reg, ret);
+		    "register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	cs->ucs_base.udb_base = (uint64_t)UMC_BASE_GET_ADDR(val) <<
@@ -2124,7 +2152,8 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
 		if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) !=
 		    0) {
 			dev_err(umc->umc_dip, CE_WARN, "failed to read "
-			    "extended base register %x: %d", reg, ret);
+			    "extended base register %x: %d", SMN_REG_ADDR(reg),
+			    ret);
 			return (B_FALSE);
 		}
 
@@ -2136,7 +2165,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_BASE_SEC(id, regno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read secondary base "
-		    "register %x: %d", reg, ret);
+		    "register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	cs->ucs_sec.udb_base = (uint64_t)UMC_BASE_GET_ADDR(val) <<
@@ -2149,8 +2178,8 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
 		if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) !=
 		    0) {
 			dev_err(umc->umc_dip, CE_WARN, "failed to read "
-			    "extended secondary base register %x: %d", reg,
-			    ret);
+			    "extended secondary base register %x: %d",
+			    SMN_REG_ADDR(reg), ret);
 			return (B_FALSE);
 		}
 
@@ -2162,7 +2191,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_MASK_DDR5(id, regno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read mask "
-		    "register %x: %d", reg, ret);
+		    "register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	cs->ucs_base_mask = (uint64_t)UMC_MASK_GET_ADDR(val) <<
@@ -2175,7 +2204,8 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
 		if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) !=
 		    0) {
 			dev_err(umc->umc_dip, CE_WARN, "failed to read "
-			    "extended mask register %x: %d", reg, ret);
+			    "extended mask register %x: %d", SMN_REG_ADDR(reg),
+			    ret);
 			return (B_FALSE);
 		}
 
@@ -2188,7 +2218,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_MASK_SEC_DDR5(id, regno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read secondary mask "
-		    "register %x: %d", reg, ret);
+		    "register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	cs->ucs_sec_mask = (uint64_t)UMC_MASK_GET_ADDR(val) <<
@@ -2201,7 +2231,8 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
 		if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) !=
 		    0) {
 			dev_err(umc->umc_dip, CE_WARN, "failed to read "
-			    "extended mask register %x: %d", reg, ret);
+			    "extended mask register %x: %d", SMN_REG_ADDR(reg),
+			    ret);
 			return (B_FALSE);
 		}
 
@@ -2213,7 +2244,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_ADDRCFG_DDR5(id, regno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read address config "
-		    "register %x: %d", reg, ret);
+		    "register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	if ((umc->umc_fdata->zufd_flags & ZEN_UMC_FAM_F_CS_XOR) != 0) {
@@ -2234,7 +2265,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_ADDRSEL_DDR5(id, regno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read address select "
-		    "register %x: %d", reg, ret);
+		    "register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	cs->ucs_row_hi_bit = 0;
@@ -2254,7 +2285,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_COLSEL_LO_DDR5(id, regno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read column address "
-		    "select low register %x: %d", reg, ret);
+		    "select low register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	for (uint_t i = 0; i < ZEN_UMC_MAX_COLSEL_PER_REG; i++) {
@@ -2265,7 +2296,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_COLSEL_HI_DDR5(id, regno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read column address "
-		    "select high register %x: %d", reg, ret);
+		    "select high register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	for (uint_t i = 0; i < ZEN_UMC_MAX_COLSEL_PER_REG; i++) {
@@ -2282,7 +2313,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
 	reg = UMC_RMSEL_DDR5(id, regno);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read rank multiply "
-		    "select register %x: %d", reg, ret);
+		    "select register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 
@@ -2303,9 +2334,10 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
 	bcopy(cs->ucs_rm_bits, cs->ucs_rm_bits_sec,
 	    sizeof (cs->ucs_rm_bits));
 
-	return (B_TRUE);
+	return (zen_umc_fill_dimm_common(umc, df, chan, dimmno, B_FALSE));
 }
 
+
 static void
 zen_umc_fill_ddr_type(zen_umc_chan_t *chan, boolean_t ddr4)
 {
@@ -2358,7 +2390,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
     boolean_t ddr4)
 {
 	int ret;
-	uint32_t reg;
+	smn_reg_t reg;
 	uint32_t val;
 
 	const umc_chan_hash_flags_t flags = umc->umc_fdata->zufd_chan_hash;
@@ -2379,7 +2411,8 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
 			if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg,
 			    &val)) != 0) {
 				dev_err(umc->umc_dip, CE_WARN, "failed to read "
-				    "bank hash register %x: %d", reg, ret);
+				    "bank hash register %x: %d",
+				    SMN_REG_ADDR(reg), ret);
 				return (B_FALSE);
 			}
 
@@ -2403,7 +2436,8 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
 			if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg,
 			    &val)) != 0) {
 				dev_err(umc->umc_dip, CE_WARN, "failed to read "
-				    "rm hash register %x: %d", reg, ret);
+				    "rm hash register %x: %d",
+				    SMN_REG_ADDR(reg), ret);
 				return (B_FALSE);
 			}
 
@@ -2420,7 +2454,8 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
 			if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg,
 			    &val)) != 0) {
 				dev_err(umc->umc_dip, CE_WARN, "failed to read "
-				    "rm hash ext register %x: %d", reg, ret);
+				    "rm hash ext register %x: %d",
+				    SMN_REG_ADDR(reg), ret);
 				return (B_FALSE);
 			}
 
@@ -2441,7 +2476,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
 
 		if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 			dev_err(umc->umc_dip, CE_WARN, "failed to read pc hash "
-			    "register %x: %d", reg, ret);
+			    "register %x: %d", SMN_REG_ADDR(reg), ret);
 			return (B_FALSE);
 		}
 
@@ -2457,7 +2492,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
 
 		if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 			dev_err(umc->umc_dip, CE_WARN, "failed to read pc hash "
-			    "2 register %x: %d", reg, ret);
+			    "2 register %x: %d", SMN_REG_ADDR(reg), ret);
 			return (B_FALSE);
 		}
 
@@ -2478,7 +2513,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
 			if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg,
 			    &val)) != 0) {
 				dev_err(umc->umc_dip, CE_WARN, "failed to read "
-				    "cs hash register %x", reg);
+				    "cs hash register %x", SMN_REG_ADDR(reg));
 				return (B_FALSE);
 			}
 
@@ -2495,7 +2530,8 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
 			if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg,
 			    &val)) != 0) {
 				dev_err(umc->umc_dip, CE_WARN, "failed to read "
-				    "cs hash ext register %x", reg);
+				    "cs hash ext register %x",
+				    SMN_REG_ADDR(reg));
 				return (B_FALSE);
 			}
 
@@ -2514,7 +2550,8 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
 static boolean_t
 zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
 {
-	uint32_t reg, val;
+	uint32_t val;
+	smn_reg_t reg;
 	const uint32_t id = chan->chan_logid;
 	int ret;
 	boolean_t ddr4;
@@ -2538,7 +2575,7 @@ zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
 	reg = UMC_UMCCFG(id);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read UMC "
-		    "configuration register %x: %d", reg, ret);
+		    "configuration register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 
@@ -2561,7 +2598,7 @@ zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
 	reg = UMC_DATACTL(id);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read data control "
-		    "register %x: %d", reg, ret);
+		    "register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	chan->chan_datactl_raw = val;
@@ -2582,7 +2619,7 @@ zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
 	reg = UMC_ECCCTL(id);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read ECC control "
-		    "register %x: %d", reg, ret);
+		    "register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	chan->chan_eccctl_raw = val;
@@ -2594,7 +2631,7 @@ zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
 	reg = UMC_UMCCAP(id);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read UMC cap"
-		    "register %x: %d", reg, ret);
+		    "register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	chan->chan_umccap_raw = val;
@@ -2602,7 +2639,7 @@ zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
 	reg = UMC_UMCCAP_HI(id);
 	if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
 		dev_err(umc->umc_dip, CE_WARN, "failed to read UMC cap high "
-		    "register %x: %d", reg, ret);
+		    "register %x: %d", SMN_REG_ADDR(reg), ret);
 		return (B_FALSE);
 	}
 	chan->chan_umccap_hi_raw = val;