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| author | sherrym <none@none> | 2007-07-02 14:05:35 -0700 |
|---|---|---|
| committer | sherrym <none@none> | 2007-07-02 14:05:35 -0700 |
| commit | 2449e17f82f6097fd2c665b64723e31ceecbeca6 (patch) | |
| tree | 4adce4537b78e91f1ac4f87433c9dddb715fffd2 /usr/src/uts/intel/sys/controlregs.h | |
| parent | 76bc40308a78598795fbedd14f726061bcd17cad (diff) | |
| download | illumos-joyent-2449e17f82f6097fd2c665b64723e31ceecbeca6.tar.gz | |
PSARC/2007/349 Intel Microcode Update Support
6558456 Need to support microcode update on Intel platforms
Diffstat (limited to 'usr/src/uts/intel/sys/controlregs.h')
| -rw-r--r-- | usr/src/uts/intel/sys/controlregs.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/usr/src/uts/intel/sys/controlregs.h b/usr/src/uts/intel/sys/controlregs.h index 385a89fe07..8acded36d8 100644 --- a/usr/src/uts/intel/sys/controlregs.h +++ b/usr/src/uts/intel/sys/controlregs.h @@ -135,6 +135,16 @@ extern "C" { #define MSR_INTC_SEP_ESP 0x175 /* kernel esp MSR */ #define MSR_INTC_SEP_EIP 0x176 /* kernel eip MSR */ +/* Intel's microcode registers */ +#define MSR_INTC_UCODE_WRITE 0x79 /* microcode write */ +#define MSR_INTC_UCODE_REV 0x8b /* microcode revision */ +#define INTC_UCODE_REV_SHIFT 32 /* Bits 63:32 */ + +/* Intel's platform identification */ +#define MSR_INTC_PLATFORM_ID 0x17 +#define INTC_PLATFORM_ID_SHIFT 50 /* Bit 52:50 */ +#define INTC_PLATFORM_ID_MASK 0x7 + /* AMD's EFER register */ #define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */ |