PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors

PSARC 2006/566 eversholt language enhancements: confprop_defined
6362846 eversholt doesn't allow dashes in pathname components
6391591 AMD NB config should not set NbMcaToMstCpuEn
6391605 AMD DRAM scrubber should be disabled when errata #99 applies
6398506 memory controller driver should not bother to attach at all on rev F
6424822 FMA needs to support AMD family 0xf revs F and G
6443847 FMA x64 multibit ChipKill rules need to follow MQSC guidelines
6443849 Accrue inf_sys and s_ecc ECC errors against memory
6443858 mc-amd can free unitsrtr before usage in subsequent error path
6443891 mc-amd does not recognise mismatched dimm support
6455363 x86 error injector should allow addr option for most errors
6455370 Opteron erratum 101 only applies on revs D and earlier
6455373 Identify chip-select lines used on a dimm
6455377 improve x64 quadrank dimm support
6455382 add generic interfaces for amd chip revision and package/socket type
6468723 mem scheme fmri containment test for hc scheme is busted
6473807 eversholt could use some mdb support
6473811 eversholt needs a confprop_defined function
6473819 eversholt should show version of rules active in DE
6475302 ::nvlist broken by some runtime link ordering changes

1 files changed, 578 insertions, 116 deletions

diff --git a/usr/src/uts/intel/sys/mc_amd.h b/usr/src/uts/intel/sys/mc_amd.h
index fba266b14f..c1fc1f2513 100644
--- a/usr/src/uts/intel/sys/mc_amd.h
+++ b/usr/src/uts/intel/sys/mc_amd.h
@@ -2,9 +2,8 @@
  * CDDL HEADER START
  *
  * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License").  You may not use this file except in compliance
- * with the License.
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
  *
  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  * or http://www.opensolaris.org/os/licensing.
@@ -28,6 +27,74 @@
 
 #pragma ident	"%Z%%M%	%I%	%E% SMI"
 
+#include <sys/mc.h>
+#include <sys/x86_archext.h>
+
+/*
+ * The mc-amd driver exports an nvlist to userland, where the primary
+ * consumer is the "chip" topology enumerator for this platform type which
+ * builds a full topology subtree from this information.  Others can use
+ * it, too, but don't depend on it not changing without an ARC contract.
+ *
+ * In the initial mc-amd implementation this nvlist was not versioned;
+ * we'll think of that as version 0 and it may be recognised by the absence
+ * of a "mcamd-nvlist-version member.
+ *
+ * Version 1 is defined as follows.  A name in square brackets indicates
+ * that member is optional (only present if the actual value is valid).
+ *
+ * Name			Type		Description
+ * -------------------- --------------- ---------------------------------------
+ * mcamd-nvlist-version	uint8		Exported nvlist version number
+ * num			uint64		Chip id of this memory controller
+ * revision		uint64		cpuid_getchiprev() result
+ * revname		string		cpuid_getchiprevstr() result
+ * socket		string		"Socket 755|939|940|AM2|F(1207)|S1g1"
+ * ecc-type		string		"ChipKill 128/16" or "Normal 64/8"
+ * base-addr		uint64		Node base address
+ * lim-addr		uint64		Node limit address
+ * node-ilen		uint64		0|1|3|7 for 0/2/4/8 way node interleave
+ * node-ilsel		uint64		Node interleave position of this node
+ * cs-intlv-factor	uint64		chip-select interleave: 1/2/4/8
+ * dram-hole-size	uint64		size in bytes from dram hole addr reg
+ * access-width		uint64		MC mode, 64 or 128 bit
+ * bank-mapping		uint64		Raw DRAM Bank Address Mapping Register
+ * bankswizzle		uint64		1 if bank swizzling enabled; else 0
+ * mismatched-dimm-support uint64	1 if active; else 0
+ * [spare-csnum]	uint64		Chip-select pair number of any spare
+ * [bad-csnum]		uint64		Chip-select pair number of swapped cs
+ * cslist		nvlist array	See below; may have 0 members
+ * dimmlist		nvlist array	See below; may have 0 members
+ *
+ * cslist is an array of nvlist, each as follows:
+ *
+ * Name			Type		Description
+ * -------------------- --------------- ---------------------------------------
+ * num			uint64		Chip-select base/mask pair number
+ * base-addr		uint64		Chip-select base address (rel to node)
+ * mask			uint64		Chip-select mask
+ * size			uint64		Chip-select size in bytes
+ * dimm1-num		uint64		First dimm (lodimm if a pair)
+ * dimm1-csname		string		Socket cs# line name for 1st dimm rank
+ * [dimm2-num]		uint64		Second dimm if applicable (updimm)
+ * [dimm2-csname]	string		Socket cs# line name for 2nd dimm rank
+ *
+ * dimmlist is an array of nvlist, each as follows:
+ *
+ * Name			Type		Description
+ * -------------------- --------------- ---------------------------------------
+ * num			uint64		DIMM instance number
+ * size			uint64		DIMM size in bytes
+ * csnums		uint64 array	CS base/mask pair(s) on this DIMM
+ * csnames		string array	Socket cs# line name(s) on this DIMM
+ *
+ *	The n'th csnums entry corresponds to the n'th csnames entry
+ */
+#define	MC_NVLIST_VERSTR	"mcamd-nvlist-version"
+#define	MC_NVLIST_VERS0		0
+#define	MC_NVLIST_VERS1		1
+#define	MC_NVLIST_VERS		MC_NVLIST_VERS1
+
 /*
  * Definitions describing various memory controller constant properties and
  * the structure of configuration registers.
@@ -38,155 +105,550 @@ extern "C" {
 #endif
 
 /*
+ * Constants and feature/revision test macros that are not expected to vary
+ * among different AMD family 0xf processor revisions.
+ */
+
+/*
  * Configuration constants
  */
+#define	MC_CHIP_MAXNODES	8	/* max number of MCs in system */
 #define	MC_CHIP_NDIMM		8	/* max dimms per MC */
 #define	MC_CHIP_NCS		8	/* number of chip-selects per MC */
+#define	MC_CHIP_NDRAMCHAN	2	/* maximum number of dram channels */
 #define	MC_CHIP_DIMMRANKMAX	4	/* largest number of ranks per dimm */
 #define	MC_CHIP_DIMMPERCS	2	/* max number of dimms per cs */
 #define	MC_CHIP_DIMMPAIR(csnum)	(csnum / MC_CHIP_DIMMPERCS)
 
+#if	MC_CHIP_DIMMPERCS > MC_UNUM_NDIMM
+#error	"MC_CHIP_DIMMPERCS exceeds MC_UNUM_NDIMM"
+#endif
+
+/*
+ * MC_REV_* are used a a convenient shorter form of the X86_CHIPREV
+ * counterparts; these must map directly as we fill mcp_rev from
+ * a cpuid_getchiprev call.
+ */
+#define	MC_REV_UNKNOWN	X86_CHIPREV_UNKNOWN
+#define	MC_REV_B	X86_CHIPREV_AMD_F_REV_B
+#define	MC_REV_C	(X86_CHIPREV_AMD_F_REV_C0 | X86_CHIPREV_AMD_F_REV_CG)
+#define	MC_REV_D	X86_CHIPREV_AMD_F_REV_D
+#define	MC_REV_E	X86_CHIPREV_AMD_F_REV_E
+#define	MC_REV_F	X86_CHIPREV_AMD_F_REV_F
+#define	MC_REV_G	X86_CHIPREV_AMD_F_REV_G
+
 /*
- * Encoding of chip version variations that we need to distinguish
+ * The most common groupings for memory controller features.
  */
-#define	MC_REV_UNKNOWN	-1u	/* unknown AMD revision */
-#define	MC_REV_PRE_D	0	/* B/C/CG */
-#define	MC_REV_D_E	1	/* D or E */
-#define	MC_REV_F	2	/* F */
+#define	MC_REVS_BC	(MC_REV_B | MC_REV_C)
+#define	MC_REVS_DE	(MC_REV_D | MC_REV_E)
+#define	MC_REVS_BCDE	(MC_REVS_BC | MC_REVS_DE)
+#define	MC_REVS_FG	(MC_REV_F | MC_REV_G)
 
 /*
- * BKDG 3.29 section 3.4.4.1 - DRAM base i registers
+ * Is 'rev' included in the 'revmask' bitmask?
  */
-#define	MC_AM_DB_DRAMBASE_MASK	0xffff0000
-#define	MC_AM_DB_DRAMBASE_LSHFT	8
-#define	MC_AM_DB_DRAMBASE(regval) \
-	(((uint64_t)(regval) & MC_AM_DB_DRAMBASE_MASK) << \
-	MC_AM_DB_DRAMBASE_LSHFT)
-#define	MC_AM_DB_INTLVEN_MASK	0x00000700
-#define	MC_AM_DB_INTLVEN_SHIFT	8
-#define	MC_AM_DB_WE		0x00000002
-#define	MC_AM_DB_RE		0x00000001
+#define	MC_REV_MATCH(rev, revmask)	X86_CHIPREV_MATCH(rev, revmask)
 
 /*
- * BKDG 3.29 section 3.4.4.2 - DRAM limit i registers
+ * Is 'rev' at least revision 'revmin' or greater
  */
-#define	MC_AM_DL_DRAMLIM_MASK	0xffff0000
-#define	MC_AM_DL_DRAMLIM_SHIFT	16
-#define	MC_AM_DL_DRAMLIM_LSHFT	8
-#define	MC_AM_DL_DRAMLIM(regval) \
-	((((uint64_t)(regval) & MC_AM_DL_DRAMLIM_MASK) << \
-	MC_AM_DL_DRAMLIM_LSHFT) | ((regval) ? \
-	((1 << (MC_AM_DL_DRAMLIM_SHIFT + MC_AM_DL_DRAMLIM_LSHFT)) - 1) : 0))
-#define	MC_AM_DL_INTLVSEL_MASK	0x00000700
-#define	MC_AM_DL_INTLVSEL_SHIFT	8
-#define	MC_AM_DL_DSTNODE_MASK	0x00000007
+#define	MC_REV_ATLEAST(rev, minrev)	X86_CHIPREV_ATLEAST(rev, minrev)
 
 /*
- * BKDG 3.29 section 3.5.4 - DRAM CS Base Address Registers.
+ * Chip socket types
+ */
+#define	MC_SKT_UNKNOWN	0x0
+#define	MC_SKT_754	0x1
+#define	MC_SKT_939	0x2
+#define	MC_SKT_940	0x3
+#define	MC_SKT_S1g1	0x4
+#define	MC_SKT_AM2	0x5
+#define	MC_SKT_F1207	0x6
+
+/*
+ * Memory controller registers are read via PCI config space accesses on
+ * bus 0, device 24 + NodeId, and function as follows:
+ *
+ * Function 0: HyperTransport Technology Configuration
+ * Function 1: Address Map
+ * Function 2: DRAM Controller & HyperTransport Technology Trace Mode
+ * Function 3: Miscellaneous Control
+ *
+ * For a given (bus, device, function) a particular offset selects the
+ * desired register.  All registers are 32-bits wide.
  *
- * MC_DC_CSB_CSBASE combines the BaseAddrHi and BaseAddrLo into a single
- * uint64_t, shifting them into the dram address bits they describe.
+ * Different family 0xf processor revisions vary slightly in the content
+ * of these configuration registers.  The biggest change is with rev F
+ * where DDR2 support has been introduced along with some hardware-controlled
+ * correctable memory error thresholding.  Fortunately most of the config info
+ * required by the mc-amd driver is similar across revisions.
+ *
+ * We will try to insulate most of the driver code from config register
+ * details by reading all memory-controller PCI config registers that we
+ * will need at driver attach time for each of functions 0 through 3, and
+ * storing them in a "cooked" form as memory controller properties.
+ * These are to be accessed directly where we have an mc_t to hand, otherwise
+ * through mcamd_get_numprop.  As such we expect most/all use of the
+ * structures and macros defined below to be in those attach codepaths.
  */
-#define	MC_DC_CSB_BASEHI_MASK	0xffe00000
-#define	MC_DC_CSB_BASEHI_LSHFT	4
 
-#define	MC_DC_CSB_BASELO_MASK	0x0000fe00
-#define	MC_DC_CSB_BASELO_LSHFT	4
+/*
+ * Registers will be represented as unions, with one fixed-width unsigned
+ * integer member providing access to the raw register value and one or more
+ * structs breaking the register out into bitfields (more than one struct if
+ * the register definitions varies across processor revisions).
+ *
+ * The "raw" union member will always be '_val32'.  Use MCREG_VAL32 to
+ * access this member.
+ *
+ * The bitfield structs are all named _fmt_xxx where xxx identifies the
+ * processor revision to which it applies.  At this point the only xxx
+ * values in use are:
+ *			'cmn' - applies to all revisions
+ *			'preF' - applies to revisions E and earlier
+ *			'revFG' - applies to revisions F and G
+ * Variants such as 'preD', 'revDE', 'postCG' etc should be introduced
+ * as requirements arise.  The MC_REV_* and MC_REV_MATCH etc macros
+ * will also need to grow to match.  Use MCREG_FIELD_* to access the
+ * individual bitfields of a register, perhaps using MC_REV_* and MC_REV_MATCH
+ * to decide which revision suffix to provide.  Where a bitfield appears
+ * in different revisions but has the same use it should be named identically
+ * (even if the BKDG varies a little) so that the MC_REG_FIELD_* macros
+ * can lookup that member based on revision only.
+ */
 
-#define	MC_DC_CSB_CSBASE(regval) \
-	((((uint64_t)(regval) & MC_DC_CSB_BASEHI_MASK) << \
-	MC_DC_CSB_BASEHI_LSHFT) | (((uint64_t)(regval) & \
-	MC_DC_CSB_BASELO_MASK) << MC_DC_CSB_BASELO_LSHFT))
+#define	_MCREG_FIELD(up, revsuffix, field) ((up)->_fmt_##revsuffix.field)
 
-#define	MC_DC_CSB_CSBE		0x00000001
+#define	MCREG_VAL32(up) ((up)->_val32)
+
+#define	MCREG_FIELD_CMN(up, field)	_MCREG_FIELD(up, cmn, field)
+#define	MCREG_FIELD_preF(up, field)	_MCREG_FIELD(up, preF, field)
+#define	MCREG_FIELD_revFG(up, field)	_MCREG_FIELD(up, revFG, field)
 
 /*
- * BKDG 3.29 section 3.5.5 - DRAM CS Mask Registers.
+ * Function 1 - DRAM Address Map: DRAM Base i Registers
  *
- * MC_DC_CSM_CSMASK combines the AddrMaskHi and AddrMaskLo into a single
- * uint64_t, shifting them into the dram address bit positions they mask.
- * It also fills the gaps between high and low mask and below the low mask.
- * MC_DC_CSM_UNMASKED_BITS indicates the number of high dram address bits
- * above MC_DC_CSM_MASKHI_HIBIT that cannot be masked.
  */
-#define	MC_DC_CSM_MASKHI_MASK	0x3fe00000
-#define	MC_DC_CSM_MASKHI_LSHFT	4
-#define	MC_DC_CSM_MASKHI_LOBIT	25
-#define	MC_DC_CSM_MASKHI_HIBIT	33
 
-#define	MC_DC_CSM_MASKLO_MASK	0x0000fe00
-#define	MC_DC_CSM_MASKLO_LOBIT	13
-#define	MC_DC_CSM_MASKLO_HIBIT	19
-#define	MC_DC_CSM_MASKLO_LSHFT	4
+union mcreg_drambase {
+	uint32_t	_val32;
+	struct {
+		uint32_t	RE:1;		/*  0:0  - Read Enable */
+		uint32_t	WE:1;		/*  1:1  - Write Enable */
+		uint32_t	reserved1:6;	/*  7:2 */
+		uint32_t	IntlvEn:3;	/* 10:8  - Interleave Enable */
+		uint32_t	reserved2:5;	/* 15:11 */
+		uint32_t	DRAMBasei:16;	/* 31:16 - Base Addr 39:24 */
+	} _fmt_cmn;
+};
+
+#define	MC_DRAMBASE(up)	((uint64_t)MCREG_FIELD_CMN(up, DRAMBasei) << 24)
+
+/*
+ * Function 1 - DRAM Address Map: DRAM Limit i Registers
+ *
+ */
+
+union mcreg_dramlimit {
+	uint32_t	_val32;
+	struct {
+		uint32_t	DstNode:3;	/*  2:0  - Destination Node */
+		uint32_t	reserved1:5;	/*  7:3 */
+		uint32_t	IntlvSel:3;	/* 10:8  - Interleave Select */
+		uint32_t	reserved2:5;	/* 15:11 */
+		uint32_t	DRAMLimiti:16;	/* 31:16 - Limit Addr 39:24 */
+	} _fmt_cmn;
+};
+
+#define	MC_DRAMLIM(up) \
+	((uint64_t)MCREG_FIELD_CMN(up, DRAMLimiti) << 24 |		\
+	(MCREG_FIELD_CMN(up, DRAMLimiti) ?  ((1 << 24) - 1) : 0))
+
+/*
+ * Function 1 - DRAM Address Map: DRAM Hole Address Register
+ */
+
+union mcreg_dramhole {
+	uint32_t	_val32;
+	struct {
+		uint32_t	DramHoleValid:1;	/*  0:0 */
+		uint32_t	reserved1:7;		/*  7:1 */
+		uint32_t	DramHoleOffset:8;	/* 15:8 */
+		uint32_t	reserved2:8;		/* 23:16 */
+		uint32_t	DramHoleBase:8;		/* 31:24 */
+	} _fmt_cmn;
+};
+
+#define	MC_DRAMHOLE_SIZE(up) (MCREG_FIELD_CMN(up, DramHoleOffset) << 24)
+
+/*
+ * Function 2 - DRAM Controller: DRAM CS Base Address Registers
+ */
+
+union mcreg_csbase {
+	uint32_t	_val32;
+	/*
+	 * Register format in revisions E and earlier
+	 */
+	struct {
+		uint32_t	CSEnable:1;	/*  0:0  - CS Bank Enable */
+		uint32_t	reserved1:8;	/*  8:1 */
+		uint32_t	BaseAddrLo:7;	/* 15:9  - Base Addr 19:13 */
+		uint32_t	reserved2:5;	/* 20:16 */
+		uint32_t	BaseAddrHi:11;	/* 31:21 - Base Addr 35:25 */
+	} _fmt_preF;
+	/*
+	 * Register format in revisions F and G
+	 */
+	struct {
+		uint32_t	CSEnable:1;	/*  0:0  - CS Bank Enable */
+		uint32_t	Spare:1;	/*  1:1  - Spare Rank */
+		uint32_t	TestFail:1;	/*  2:2  - Memory Test Failed */
+		uint32_t	reserved1:2;	/*  4:3 */
+		uint32_t	BaseAddrLo:9;	/* 13:5  - Base Addr 21:13 */
+		uint32_t	reserved2:5;	/* 18:14 */
+		uint32_t	BaseAddrHi:10;	/* 28:19 - Base Addr 36:27 */
+		uint32_t	reserved3:3;	/* 31:39 */
+	} _fmt_revFG;
+};
+
+#define	MC_CSBASE(up, rev) (MC_REV_MATCH(rev, MC_REV_F) ?	\
+	(uint64_t)MCREG_FIELD_revFG(up, BaseAddrHi) << 27 |		\
+	(uint64_t)MCREG_FIELD_revFG(up, BaseAddrLo) << 13 :		\
+	(uint64_t)MCREG_FIELD_preF(up, BaseAddrHi) << 25 |		\
+	(uint64_t)MCREG_FIELD_preF(up, BaseAddrLo) << 13)
+
+/*
+ * Function 2 - DRAM Controller: DRAM CS Mask Registers
+ */
+
+union mcreg_csmask {
+	uint32_t	_val32;
+	/*
+	 * Register format in revisions E and earlier
+	 */
+	struct {
+		uint32_t	reserved1:9;	/*  8:0 */
+		uint32_t	AddrMaskLo:7;	/* 15:9  - Addr Mask 19:13 */
+		uint32_t	reserved2:5;	/* 20:16 */
+		uint32_t	AddrMaskHi:9;	/* 29:21 - Addr Mask 33:25 */
+		uint32_t	reserved3:2;	/* 31:30 */
+	} _fmt_preF;
+	/*
+	 * Register format in revisions F and G
+	 */
+	struct {
+		uint32_t	reserved1:5;	/*  4:0 */
+		uint32_t	AddrMaskLo:9;	/* 13:5  - Addr Mask 21:13 */
+		uint32_t	reserved2:5;	/* 18:14 */
+		uint32_t	AddrMaskHi:10;	/* 28:19 - Addr Mask 36:27 */
+		uint32_t	reserved3:3;	/* 31:29 */
+	} _fmt_revFG;
+};
 
-#define	MC_DC_CSM_MASKFILL	0x1f01fff	/* [24:20] and [12:0] */
+#define	MC_CSMASKLO_LOBIT(rev) (MC_REV_MATCH(rev, MC_REV_F) ? 13 : 13)
+#define	MC_CSMASKLO_HIBIT(rev) (MC_REV_MATCH(rev, MC_REV_F) ? 21 : 19)
 
-#define	MC_DC_CSM_UNMASKED_BITS	2
+#define	MC_CSMASKHI_LOBIT(rev) (MC_REV_MATCH(rev, MC_REV_F) ? 27 : 25)
+#define	MC_CSMASKHI_HIBIT(rev) (MC_REV_MATCH(rev, MC_REV_F) ? 36 : 33)
 
-#define	MC_DC_CSM_CSMASK(regval) \
-	((((uint64_t)(regval) & MC_DC_CSM_MASKHI_MASK) << \
-	MC_DC_CSM_MASKHI_LSHFT) | (((uint64_t)(regval) & \
-	MC_DC_CSM_MASKLO_MASK) << MC_DC_CSM_MASKLO_LSHFT) | \
-	MC_DC_CSM_MASKFILL)
+#define	MC_CSMASK_UNMASKABLE(rev) (MC_REV_MATCH(rev, MC_REV_F) ? 0 : 2)
+
+#define	MC_CSMASK(up, rev) (MC_REV_MATCH(rev, MC_REV_F) ?		\
+	(uint64_t)MCREG_FIELD_revFG(up, AddrMaskHi) << 27 |		\
+	(uint64_t)MCREG_FIELD_revFG(up, AddrMaskLo) << 13 | 0x7c01fff :	\
+	(uint64_t)MCREG_FIELD_preF(up, AddrMaskHi) << 25 |		\
+	(uint64_t)MCREG_FIELD_preF(up, AddrMaskLo) << 13 | 0x1f01fff)
 
 /*
- * BKDG 3.29 section 3.5.6 - DRAM Bank Address Mapping Register
+ * Function 2 - DRAM Controller: DRAM Bank Address Mapping Registers
  */
+
+union mcreg_bankaddrmap {
+	uint32_t	_val32;
+	/*
+	 * Register format in revisions E and earlier
+	 */
+	struct {
+		uint32_t	cs10:4;			/*  3:0  - CS1/0 */
+		uint32_t	cs32:4;			/*  7:4  - CS3/2 */
+		uint32_t	cs54:4;			/* 11:8  - CS5/4 */
+		uint32_t	cs76:4;			/* 15:12 - CS7/6 */
+		uint32_t	reserved1:14;		/* 29:16 */
+		uint32_t	BankSwizzleMode:1;	/* 30:30 */
+		uint32_t	reserved2:1;		/* 31:31 */
+	} _fmt_preF;
+	/*
+	 * Register format in revisions F and G
+	 */
+	struct {
+		uint32_t	cs10:4;			/*  3:0  - CS1/0 */
+		uint32_t	cs32:4;			/*  7:4  - CS3/2 */
+		uint32_t	cs54:4;			/* 11:8  - CS5/4 */
+		uint32_t	cs76:4;			/* 15:12 - CS7/6 */
+		uint32_t	reserved1:16;		/* 31:16 */
+	} _fmt_revFG;
+	/*
+	 * Accessing all mode encodings as one uint16
+	 */
+	struct {
+		uint32_t	allcsmodes:16;		/* 15:0 */
+		uint32_t	pad:16;			/* 31:16 */
+	} _fmt_bankmodes;
+};
+
 #define	MC_DC_BAM_CSBANK_MASK	0x0000000f
 #define	MC_DC_BAM_CSBANK_SHIFT	4
-#define	MC_DC_BAM_CSBANK_SWIZZLE 0x40000000
-
-/*
- * BKDG 3.29 section 3.4.8 - DRAM Hole register, revs E and later
- */
-#define	MC_DC_HOLE_VALID		0x00000001
-#define	MC_DC_HOLE_OFFSET_MASK		0x0000ff00
-#define	MC_DC_HOLE_OFFSET_LSHIFT	16
-
-/*
- * BKDG 3.29 section 3.5.11  - DRAM configuration high and low registers.
- * The following defines may be applied to a uint64_t made by
- * concatenating those two 32-bit registers.
- */
-#define	MC_DC_DCFG_DLL_DIS		0x0000000000000001
-#define	MC_DC_DCFG_D_DRV		0x0000000000000002
-#define	MC_DC_DCFG_QFC_EN		0x0000000000000004
-#define	MC_DC_DCFG_DISDQSYS		0x0000000000000008
-#define	MC_DC_DCFG_BURST2OPT		0x0000000000000020
-#define	MC_DC_DCFG_MOD64BITMUX		0x0000000000000040
-#define	MC_DC_DCFG_PWRDWNTRIEN		0x0000000000000080 /* >= rev E */
-#define	MC_DC_DCFG_SCRATCHBIT		0x0000000000000080 /* <= rev D */
-#define	MC_DC_DCFG_DRAMINIT		0x0000000000000100
-#define	MC_DC_DCFG_DUALDIMMEN		0x0000000000000200
-#define	MC_DC_DCFG_DRAMENABLE		0x0000000000000400
-#define	MC_DC_DCFG_MEMCLRSTATUS		0x0000000000000800
-#define	MC_DC_DCFG_ESR			0x0000000000001000
-#define	MC_DC_DCFG_SR_S			0x0000000000002000
-#define	MC_DC_DCFG_RDWRQBYP_MASK	0x000000000000c000
-#define	MC_DC_DCFG_128			0x0000000000010000
-#define	MC_DC_DCFG_DIMMECEN		0x0000000000020000
-#define	MC_DC_DCFG_UNBUFFDIMM		0x0000000000040000
-#define	MC_DC_DCFG_32BYTEEN		0x0000000000080000
-#define	MC_DC_DCFG_X4DIMMS_MASK		0x0000000000f00000
-#define	MC_DC_DCFG_X4DIMMS_SHIFT	20
-#define	MC_DC_DCFG_DISINRCVRS		0x0000000001000000
-#define	MC_DC_DCFG_BYPMAX_MASK		0x000000000e000000
-#define	MC_DC_DCFG_EN2T			0x0000000010000000
-#define	MC_DC_DCFG_UPPERCSMAP		0x0000000020000000
-#define	MC_DC_DCFG_PWRDOWNCTL_MASK	0x00000000c0000000
-#define	MC_DC_DCFG_ASYNCLAT_MASK	0x0000000f00000000
-#define	MC_DC_DCFG_RDPREAMBLE_MASK	0x00000f0000000000
-#define	MC_DC_DCFG_MEMDQDRVSTREN_MASK	0x0000600000000000
-#define	MC_DC_DCFG_DISABLEJITTER	0x0000800000000000
-#define	MC_DC_DCFG_ILD_LMT_MASK		0x0007000000000000
-#define	MC_DC_DCFG_ECC_EN		0x0008000000000000
-#define	MC_DC_DCFG_MEMCLK_MASK		0x0070000000000000
-#define	MC_DC_DCFG_MCR			0x0200000000000000
-#define	MC_DC_DCFG_MC0_EN		0x0400000000000000
-#define	MC_DC_DCFG_MC1_EN		0x0800000000000000
-#define	MC_DC_DCFG_MC2_EN		0x1000000000000000
-#define	MC_DC_DCFG_MC3_EN		0x2000000000000000
-#define	MC_DC_DCFG_ODDDIVISORCORRECT	0x8000000000000000
+
+#define	MC_CSBANKMODE(up, csnum) ((up)->_fmt_bankmodes.allcsmodes >>	\
+    MC_DC_BAM_CSBANK_SHIFT * MC_CHIP_DIMMPAIR(csnum) & MC_DC_BAM_CSBANK_MASK)
+
+/*
+ * Function 2 - DRAM Controller: DRAM Configuration Low and High
+ */
+
+union mcreg_dramcfg_lo {
+	uint32_t _val32;
+	/*
+	 * Register format in revisions E and earlier.
+	 * Bit 7 is a BIOS ScratchBit in revs D and earlier,
+	 * PwrDwnTriEn in revision E;  we don't use it so
+	 * we'll call it ambig1.
+	 */
+	struct {
+		uint32_t	DLL_Dis:1;	/* 0 */
+		uint32_t	D_DRV:1;	/* 1 */
+		uint32_t	QFC_EN:1;	/* 2 */
+		uint32_t	DisDqsHys:1;	/* 3 */
+		uint32_t	reserved1:1;	/* 4 */
+		uint32_t	Burst2Opt:1;	/* 5 */
+		uint32_t	Mod64BitMux:1;	/* 6 */
+		uint32_t	ambig1:1;	/* 7 */
+		uint32_t	DramInit:1;	/* 8 */
+		uint32_t	DualDimmEn:1;	/* 9 */
+		uint32_t	DramEnable:1;	/* 10 */
+		uint32_t	MemClrStatus:1;	/* 11 */
+		uint32_t	ESR:1;		/* 12 */
+		uint32_t	SR_S:1;		/* 13 */
+		uint32_t	RdWrQByp:2;	/* 15:14 */
+		uint32_t	Width128:1;	/* 16 */
+		uint32_t	DimmEcEn:1;	/* 17 */
+		uint32_t	UnBufDimm:1;	/* 18 */
+		uint32_t	ByteEn32:1;	/* 19 */
+		uint32_t	x4DIMMs:4;	/* 23:20 */
+		uint32_t	DisInRcvrs:1;	/* 24 */
+		uint32_t	BypMax:3;	/* 27:25 */
+		uint32_t	En2T:1;		/* 28 */
+		uint32_t	UpperCSMap:1;	/* 29 */
+		uint32_t	PwrDownCtl:2;	/* 31:30 */
+	} _fmt_preF;
+	/*
+	 * Register format in revisions F and G
+	 */
+	struct {
+		uint32_t	InitDram:1;		/* 0 */
+		uint32_t	ExitSelfRef:1;		/* 1 */
+		uint32_t	reserved1:2;		/* 3:2 */
+		uint32_t	DramTerm:2;		/* 5:4 */
+		uint32_t	reserved2:1;		/* 6 */
+		uint32_t	DramDrvWeak:1;		/* 7 */
+		uint32_t	ParEn:1;		/* 8 */
+		uint32_t	SelRefRateEn:1;		/* 9 */
+		uint32_t	BurstLength32:1;	/* 10 */
+		uint32_t	Width128:1;		/* 11 */
+		uint32_t	x4DIMMs:4;		/* 15:12 */
+		uint32_t	UnBuffDimm:1;		/* 16 */
+		uint32_t	reserved3:2;		/* 18:17 */
+		uint32_t	DimmEccEn:1;		/* 19 */
+		uint32_t	reserved4:12;		/* 31:20 */
+	} _fmt_revFG;
+};
+
+/*
+ * Function 2 - DRAM Controller: DRAM Controller Miscellaneous Data
+ */
+
+union mcreg_drammisc {
+	uint32_t _val32;
+	/*
+	 * Register format in revisions F and G
+	 */
+	struct {
+		uint32_t	reserved2:1;		/* 0 */
+		uint32_t	DisableJitter:1;	/* 1 */
+		uint32_t	RdWrQByp:2;		/* 3:2 */
+		uint32_t	Mod64Mux:1;		/* 4 */
+		uint32_t	DCC_EN:1;		/* 5 */
+		uint32_t	ILD_lmt:3;		/* 8:6 */
+		uint32_t	DramEnabled:1;		/* 9 */
+		uint32_t	PwrSavingsEn:1;		/* 10 */
+		uint32_t	reserved1:13;		/* 23:11 */
+		uint32_t	MemClkDis:8;		/* 31:24 */
+	} _fmt_revFG;
+};
+
+union mcreg_dramcfg_hi {
+	uint32_t _val32;
+	/*
+	 * Register format in revisions E and earlier.
+	 */
+	struct {
+		uint32_t	AsyncLat:4;		/* 3:0 */
+		uint32_t	reserved1:4;		/* 7:4 */
+		uint32_t	RdPreamble:4;		/* 11:8 */
+		uint32_t	reserved2:1;		/* 12 */
+		uint32_t	MemDQDrvStren:2;	/* 14:13 */
+		uint32_t	DisableJitter:1;	/* 15 */
+		uint32_t	ILD_lmt:3;		/* 18:16 */
+		uint32_t	DCC_EN:1;		/* 19 */
+		uint32_t	MemClk:3;		/* 22:20 */
+		uint32_t	reserved3:2;		/* 24:23 */
+		uint32_t	MCR:1;			/* 25 */
+		uint32_t	MC0_EN:1;		/* 26 */
+		uint32_t	MC1_EN:1;		/* 27 */
+		uint32_t	MC2_EN:1;		/* 28 */
+		uint32_t	MC3_EN:1;		/* 29 */
+		uint32_t	reserved4:1;		/* 30 */
+		uint32_t	OddDivisorCorrect:1;	/* 31 */
+	} _fmt_preF;
+	/*
+	 * Register format in revisions F and G
+	 */
+	struct {
+		uint32_t	MemClkFreq:3;		/* 2:0 */
+		uint32_t	MemClkFreqVal:1;	/* 3 */
+		uint32_t	MaxAsyncLat:4;		/* 7:4 */
+		uint32_t	reserved1:4;		/* 11:8 */
+		uint32_t	RDqsEn:1;		/* 12 */
+		uint32_t	reserved2:1;		/* 13 */
+		uint32_t	DisDramInterface:1;	/* 14 */
+		uint32_t	PowerDownEn:1;		/* 15 */
+		uint32_t	PowerDownMode:1;	/* 16 */
+		uint32_t	FourRankSODimm:1;	/* 17 */
+		uint32_t	FourRankRDimm:1;	/* 18 */
+		uint32_t	reserved3:1;		/* 19 */
+		uint32_t	SlowAccessMode:1;	/* 20 */
+		uint32_t	reserved4:1;		/* 21 */
+		uint32_t	BankSwizzleMode:1;	/* 22 */
+		uint32_t	undocumented1:1;	/* 23 */
+		uint32_t	DcqBypassMax:4;		/* 27:24 */
+		uint32_t	FourActWindow:4;	/* 31:28 */
+	} _fmt_revFG;
+};
+
+/*
+ * Function 3 - Miscellaneous Control: Scrub Control Register
+ */
+
+union mcreg_scrubctl {
+	uint32_t _val32;
+	struct {
+		uint32_t	DramScrub:5;		/* 4:0 */
+		uint32_t	reserved3:3;		/* 7:5 */
+		uint32_t	L2Scrub:5;		/* 12:8 */
+		uint32_t	reserved2:3;		/* 15:13 */
+		uint32_t	DcacheScrub:5;		/* 20:16 */
+		uint32_t	reserved1:11;		/* 31:21 */
+	} _fmt_cmn;
+};
+
+/*
+ * Function 3 - Miscellaneous Control: On-Line Spare Control Register
+ */
+
+union mcreg_nbcfg {
+	uint32_t _val32;
+	/*
+	 * Register format in revisions E and earlier.
+	 */
+	struct {
+		uint32_t	CpuEccErrEn:1;			/* 0 */
+		uint32_t	CpuRdDatErrEn:1;		/* 1 */
+		uint32_t	SyncOnUcEccEn:1;		/* 2 */
+		uint32_t	SyncPktGenDis:1;		/* 3 */
+		uint32_t	SyncPktPropDis:1;		/* 4 */
+		uint32_t	IoMstAbortDis:1;		/* 5 */
+		uint32_t	CpuErrDis:1;			/* 6 */
+		uint32_t	IoErrDis:1;			/* 7 */
+		uint32_t	WdogTmrDis:1;			/* 8 */
+		uint32_t	WdogTmrCntSel:3;		/* 11:9 */
+		uint32_t	WdogTmrBaseSel:2;		/* 13:12 */
+		uint32_t	LdtLinkSel:2;			/* 15:14 */
+		uint32_t	GenCrcErrByte0:1;		/* 16 */
+		uint32_t	GenCrcErrByte1:1;		/* 17 */
+		uint32_t	reserved1:2;			/* 19:18 */
+		uint32_t	SyncOnWdogEn:1;			/* 20 */
+		uint32_t	SyncOnAnyErrEn:1;		/* 21 */
+		uint32_t	EccEn:1;			/* 22 */
+		uint32_t	ChipKillEccEn:1;		/* 23 */
+		uint32_t	IoRdDatErrEn:1;			/* 24 */
+		uint32_t	DisPciCfgCpuErrRsp:1;		/* 25 */
+		uint32_t	reserved2:1;			/* 26 */
+		uint32_t	NbMcaToMstCpuEn:1;		/* 27 */
+		uint32_t	reserved3:4;			/* 31:28 */
+	} _fmt_preF;
+	/*
+	 * Register format in revisions F and G
+	 */
+	struct {
+		uint32_t	CpuEccErrEn:1;			/* 0 */
+		uint32_t	CpuRdDatErrEn:1;		/* 1 */
+		uint32_t	SyncOnUcEccEn:1;		/* 2 */
+		uint32_t	SyncPktGenDis:1;		/* 3 */
+		uint32_t	SyncPktPropDis:1;		/* 4 */
+		uint32_t	IoMstAbortDis:1;		/* 5 */
+		uint32_t	CpuErrDis:1;			/* 6 */
+		uint32_t	IoErrDis:1;			/* 7 */
+		uint32_t	WdogTmrDis:1;			/* 8 */
+		uint32_t	WdogTmrCntSel:3;		/* 11:9 */
+		uint32_t	WdogTmrBaseSel:2;		/* 13:12 */
+		uint32_t	LdtLinkSel:2;			/* 15:14 */
+		uint32_t	GenCrcErrByte0:1;		/* 16 */
+		uint32_t	GenCrcErrByte1:1;		/* 17 */
+		uint32_t	reserved1:2;			/* 19:18 */
+		uint32_t	SyncOnWdogEn:1;			/* 20 */
+		uint32_t	SyncOnAnyErrEn:1;		/* 21 */
+		uint32_t	EccEn:1;			/* 22 */
+		uint32_t	ChipKillEccEn:1;		/* 23 */
+		uint32_t	IoRdDatErrEn:1;			/* 24 */
+		uint32_t	DisPciCfgCpuErrRsp:1;		/* 25 */
+		uint32_t	reserved2:1;			/* 26 */
+		uint32_t	NbMcaToMstCpuEn:1;		/* 27 */
+		uint32_t	DisTgtAbtCpuErrRsp:1;		/* 28 */
+		uint32_t	DisMstAbtCpuErrRsp:1;		/* 29 */
+		uint32_t	SyncOnDramAdrParErrEn:1;	/* 30 */
+		uint32_t	reserved3:1;			/* 31 */
+
+	} _fmt_revFG;
+};
+
+/*
+ * Function 3 - Miscellaneous Control: On-Line Spare Control Register
+ */
+
+union mcreg_sparectl {
+	uint32_t _val32;
+	/*
+	 * Register format in revisions F and G
+	 */
+	struct {
+		uint32_t	SwapEn:1;		/* 0 */
+		uint32_t	SwapDone:1;		/* 1 */
+		uint32_t	reserved1:2;		/* 3:2 */
+		uint32_t	BadDramCs:3;		/* 6:4 */
+		uint32_t	reserved2:5;		/* 11:7 */
+		uint32_t	SwapDoneInt:2;		/* 13:12 */
+		uint32_t	EccErrInt:2;		/* 15:14 */
+		uint32_t	EccErrCntDramCs:3;	/* 18:16 */
+		uint32_t	reserved3:1;		/* 19 */
+		uint32_t	EccErrCntDramChan:1;	/* 20 */
+		uint32_t	reserved4:2;		/* 22:21 */
+		uint32_t	EccErrCntWrEn:1;	/* 23 */
+		uint32_t	EccErrCnt:4;		/* 27:24 */
+		uint32_t	reserved5:4;		/* 31:28 */
+	} _fmt_revFG;
+};
 
 #ifdef __cplusplus
 }