PSARC 2006/020 FMA for Athlon 64 and Opteron Processors

PSARC 2006/028 eversholt language enhancements
6181364 Eversholt needs method to revise value of a fault's property
6183842 eft can construct extra propagations in the instance tree
6187143 eversholt needs to use fmd_case_add_serd() to add counted ereports against open case
6232253 wildcarding may not pick up matches buried in config path
6284455 eversholt wildcarding and vertical expansion have trouble working together
6298484 properties are not auto-converting to integers in eversholt constraints
6298972 eversholt should be able to mark faults as no-message like the cpumem DE
6298974 nested SERD engines don't work
6298981 eft memory usage could improve by caching common constraint expressions
6323319 call() is not allowing string-valued returns
6323322 a global variable should be allowed as the RHS of an nvpair
6323393 eversholt caches a little too much info when caching constraints
6323554 eversholt type conversion can cause core dump
6328144 libexacct leaks like a really big sieve when faced with non-exacct input
6331093 payloadprop should be able to read and interpret hc scheme fmris
6332245 payloadprop() returns cached value from existing FME when not appropriate
6333617 eversholt should have way to check if a global is defined
6346926 eversholt needs a way to maintain diagnosis statistics
6359264 Provide FMA support for AMD64 processors
6363503 Can not register error handler callbacks for root node
6366821 cpu scheme serial number should be a string
6367031 eft.so leaks memory
6370284 cpumem-diagnosis checks the asru version against FM_EREPORT_VERSION instead of FM_CPU_SCHEME_VERSION
6377319 eft could close cases for resources already in the faulty state
6379498 fmd dies on assertion failure when repairing an fmd module
6381022 fmd_case_insert_event() should reject duplicates and save memory

--HG--
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rename : usr/src/uts/common/sys/fm/cpu/UltraSPARC-II.h => usr/src/uts/sparc/sys/fm/cpu/UltraSPARC-II.h
rename : usr/src/uts/common/sys/fm/cpu/UltraSPARC-III.h => usr/src/uts/sparc/sys/fm/cpu/UltraSPARC-III.h
rename : usr/src/uts/common/sys/fm/cpu/UltraSPARC-T1.h => usr/src/uts/sparc/sys/fm/cpu/UltraSPARC-T1.h

10 files changed, 1182 insertions, 53 deletions

diff --git a/usr/src/uts/intel/sys/Makefile b/usr/src/uts/intel/sys/Makefile
index 31cb0ddb03..de2867be84 100644
--- a/usr/src/uts/intel/sys/Makefile
+++ b/usr/src/uts/intel/sys/Makefile
@@ -20,7 +20,7 @@
 # CDDL HEADER END
 #
 #
-# Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+# Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
 # Use is subject to license terms.
 #
 # ident	"%Z%%M%	%I%	%E% SMI"
@@ -55,6 +55,11 @@ HDRS	=			\
 	machlock.h		\
 	machsig.h		\
 	machtypes.h		\
+	mc.h			\
+	mc_amd.h		\
+	mca_amd.h		\
+	mca_x86.h		\
+	memtest.h		\
 	mii.h			\
 	miipriv.h		\
 	mmu.h			\
diff --git a/usr/src/uts/intel/sys/archsystm.h b/usr/src/uts/intel/sys/archsystm.h
index 76c33e8c05..5ed70f0cb2 100644
--- a/usr/src/uts/intel/sys/archsystm.h
+++ b/usr/src/uts/intel/sys/archsystm.h
@@ -19,7 +19,7 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
@@ -60,6 +60,8 @@ extern void tenmicrosec(void);
 extern void restore_int_flag(int);
 extern int clear_int_flag(void);
 
+extern void int3(void);
+extern void int18(void);
 extern void int20(void);
 
 #if defined(__amd64)
diff --git a/usr/src/uts/intel/sys/controlregs.h b/usr/src/uts/intel/sys/controlregs.h
index b0001c62be..5863b0c201 100644
--- a/usr/src/uts/intel/sys/controlregs.h
+++ b/usr/src/uts/intel/sys/controlregs.h
@@ -20,7 +20,7 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
@@ -145,7 +145,8 @@ extern "C" {
 
 #define	MSR_AMD_HWCR	0xc0010015
 
-#define	AMD_HWCR_FFDIS	0x40		/* set to disable TLB Flush Filter */
+#define	AMD_HWCR_FFDIS			0x00040	/* disable TLB Flush Filter */
+#define	AMD_HWCR_MCI_STATUS_WREN	0x40000	/* enable write of MCi_STATUS */
 
 /* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */
 
diff --git a/usr/src/uts/intel/sys/fm/cpu/AMD.h b/usr/src/uts/intel/sys/fm/cpu/AMD.h
new file mode 100644
index 0000000000..bb7aa427e5
--- /dev/null
+++ b/usr/src/uts/intel/sys/fm/cpu/AMD.h
@@ -0,0 +1,223 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_FM_CPU_AMD_H
+#define	_SYS_FM_CPU_AMD_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Ereport class subcategory for AMD processors */
+#define	FM_EREPORT_CPU_AMD	"amd"
+
+/*
+ * Ereport payload definitions
+ */
+#define	FM_EREPORT_PAYLOAD_NAME_BANK_STAT	"bank-status"
+#define	FM_EREPORT_PAYLOAD_NAME_BANK_NUM	"bank-number"
+#define	FM_EREPORT_PAYLOAD_NAME_ADDR		"addr"
+#define	FM_EREPORT_PAYLOAD_NAME_ADDR_VALID	"addr-valid"
+#define	FM_EREPORT_PAYLOAD_NAME_SYND		"syndrome"
+#define	FM_EREPORT_PAYLOAD_NAME_SYND_TYPE	"syndrome-type"
+#define	FM_EREPORT_PAYLOAD_NAME_IP		"ip"
+#define	FM_EREPORT_PAYLOAD_NAME_PRIV		"privileged"
+#define	FM_EREPORT_PAYLOAD_NAME_RESOURCE	"resource"
+
+#define	FM_EREPORT_PAYLOAD_FLAG_BANK_STAT	0x0000000000000001
+#define	FM_EREPORT_PAYLOAD_FLAG_BANK_NUM	0x0000000000000002
+#define	FM_EREPORT_PAYLOAD_FLAG_ADDR		0x0000000000000004
+#define	FM_EREPORT_PAYLOAD_FLAG_ADDR_VALID	0x0000000000000008
+#define	FM_EREPORT_PAYLOAD_FLAG_SYND		0x0000000000000010
+#define	FM_EREPORT_PAYLOAD_FLAG_SYND_TYPE	0x0000000000000020
+#define	FM_EREPORT_PAYLOAD_FLAG_IP		0x0000000000000040
+#define	FM_EREPORT_PAYLOAD_FLAG_PRIV		0x0000000000000080
+#define	FM_EREPORT_PAYLOAD_FLAG_RESOURCE	0x0000000000000100
+#define	FM_EREPORT_PAYLOAD_FLAG_STACK		0x0000000000000200
+
+#define	FM_EREPORT_PAYLOAD_FLAGS_BANK \
+	(FM_EREPORT_PAYLOAD_FLAG_BANK_STAT | FM_EREPORT_PAYLOAD_FLAG_BANK_NUM)
+#define	FM_EREPORT_PAYLOAD_FLAGS_ADDR \
+	(FM_EREPORT_PAYLOAD_FLAG_ADDR | FM_EREPORT_PAYLOAD_FLAG_ADDR_VALID)
+#define	FM_EREPORT_PAYLOAD_FLAGS_SYND \
+	(FM_EREPORT_PAYLOAD_FLAG_SYND | FM_EREPORT_PAYLOAD_FLAG_SYND_TYPE)
+#define	FM_EREPORT_PAYLOAD_FLAGS_RESOURCE \
+	(FM_EREPORT_PAYLOAD_FLAG_RESOURCE)
+#define	FM_EREPORT_PAYLOAD_FLAGS_COMMON \
+	(FM_EREPORT_PAYLOAD_FLAGS_BANK | FM_EREPORT_PAYLOAD_FLAG_IP | \
+	FM_EREPORT_PAYLOAD_FLAG_PRIV)
+#define	FM_EREPORT_PAYLOAD_FLAGS_NB \
+	(FM_EREPORT_PAYLOAD_FLAG_STACK)
+
+#define	FM_EREPORT_PAYLOAD_FLAGS_1(f1) \
+	(FM_EREPORT_PAYLOAD_FLAGS_COMMON | FM_EREPORT_PAYLOAD_FLAGS_##f1)
+#define	FM_EREPORT_PAYLOAD_FLAGS_2(f1, f2) \
+	(FM_EREPORT_PAYLOAD_FLAGS_COMMON | FM_EREPORT_PAYLOAD_FLAGS_##f1 | \
+	FM_EREPORT_PAYLOAD_FLAGS_##f2)
+#define	FM_EREPORT_PAYLOAD_FLAGS_3(f1, f2, f3) \
+	(FM_EREPORT_PAYLOAD_FLAGS_COMMON | FM_EREPORT_PAYLOAD_FLAGS_##f1 | \
+	FM_EREPORT_PAYLOAD_FLAGS_##f2 | FM_EREPORT_PAYLOAD_FLAGS_##f3)
+
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_SYS_ECC1 \
+	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_L2_ECC1 \
+	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_SYS_ECCM \
+	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_L2_ECCM \
+	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECC1 \
+	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECC1_UC \
+	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECCM \
+	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_TAG_PAR \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_STAG_PAR \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_L1TLB_PAR \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_L2TLB_PAR \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_SYS_ECC1 \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_L2_ECC1 \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_SYS_ECCM \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_L2_ECCM \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_DATA_PAR \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_TAG_PAR \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_STAG_PAR \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_L1TLB_PAR \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_L2TLB_PAR \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_RDDE \
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
+
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2D_ECC1 \
+	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2D_ECCM \
+	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_PAR \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_ECC1 \
+	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_ECCM \
+	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_RDE \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_ECC1 \
+	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_ECCM \
+	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_LS_S_RDE \
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
+
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MEM_CE \
+	FM_EREPORT_PAYLOAD_FLAGS_3(ADDR, SYND, RESOURCE)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MEM_UE \
+	FM_EREPORT_PAYLOAD_FLAGS_3(ADDR, SYND, RESOURCE)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_HT_CRC \
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_HT_SYNC \
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MA \
+	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, NB)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_TA \
+	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, NB)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_GART_WALK \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_RMW \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_WDOG \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+
+#define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_UNKNOWN \
+	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+
+#define	FM_EREPORT_CPU_AMD_DC_INF_SYS_ECC1	"dc.inf_sys_ecc1"
+#define	FM_EREPORT_CPU_AMD_DC_INF_SYS_ECCM	"dc.inf_sys_eccm"
+#define	FM_EREPORT_CPU_AMD_DC_INF_L2_ECC1	"dc.inf_l2_ecc1"
+#define	FM_EREPORT_CPU_AMD_DC_INF_L2_ECCM	"dc.inf_l2_eccm"
+#define	FM_EREPORT_CPU_AMD_DC_DATA_ECC1		"dc.data_ecc1"
+#define	FM_EREPORT_CPU_AMD_DC_DATA_ECC1_UC	"dc.data_ecc1_uc"
+#define	FM_EREPORT_CPU_AMD_DC_DATA_ECCM		"dc.data_eccm"
+#define	FM_EREPORT_CPU_AMD_DC_TAG_PAR		"dc.tag_par"
+#define	FM_EREPORT_CPU_AMD_DC_STAG_PAR		"dc.stag_par"
+#define	FM_EREPORT_CPU_AMD_DC_L1TLB_PAR		"dc.l1tlb_par"
+#define	FM_EREPORT_CPU_AMD_DC_L2TLB_PAR		"dc.l2tlb_par"
+
+#define	FM_EREPORT_CPU_AMD_IC_INF_SYS_ECC1	"ic.inf_sys_ecc1"
+#define	FM_EREPORT_CPU_AMD_IC_INF_SYS_ECCM	"ic.inf_sys_eccm"
+#define	FM_EREPORT_CPU_AMD_IC_INF_L2_ECC1	"ic.inf_l2_ecc1"
+#define	FM_EREPORT_CPU_AMD_IC_INF_L2_ECCM	"ic.inf_l2_eccm"
+#define	FM_EREPORT_CPU_AMD_IC_DATA_PAR		"ic.data_par"
+#define	FM_EREPORT_CPU_AMD_IC_TAG_PAR		"ic.tag_par"
+#define	FM_EREPORT_CPU_AMD_IC_STAG_PAR		"ic.stag_par"
+#define	FM_EREPORT_CPU_AMD_IC_L1TLB_PAR		"ic.l1tlb_par"
+#define	FM_EREPORT_CPU_AMD_IC_L2TLB_PAR		"ic.l2tlb_par"
+#define	FM_EREPORT_CPU_AMD_IC_RDDE		"ic.rdde"
+
+#define	FM_EREPORT_CPU_AMD_BU_L2D_ECC1		"bu.l2d_ecc1"
+#define	FM_EREPORT_CPU_AMD_BU_L2D_ECCM		"bu.l2d_eccm"
+#define	FM_EREPORT_CPU_AMD_BU_L2T_PAR		"bu.l2t_par"
+#define	FM_EREPORT_CPU_AMD_BU_L2T_ECC1		"bu.l2t_ecc1"
+#define	FM_EREPORT_CPU_AMD_BU_L2T_ECCM		"bu.l2t_eccm"
+#define	FM_EREPORT_CPU_AMD_BU_S_RDE		"bu.s_rde"
+#define	FM_EREPORT_CPU_AMD_BU_S_ECC1		"bu.s_ecc1"
+#define	FM_EREPORT_CPU_AMD_BU_S_ECCM		"bu.s_eccm"
+
+#define	FM_EREPORT_CPU_AMD_LS_S_RDE		"ls.s_rde"
+
+#define	FM_EREPORT_CPU_AMD_NB_MEM_CE		"nb.mem_ce"
+#define	FM_EREPORT_CPU_AMD_NB_MEM_UE		"nb.mem_ue"
+#define	FM_EREPORT_CPU_AMD_NB_HT_CRC		"nb.ht_crc"
+#define	FM_EREPORT_CPU_AMD_NB_HT_SYNC		"nb.ht_sync"
+#define	FM_EREPORT_CPU_AMD_NB_MA		"nb.ma"
+#define	FM_EREPORT_CPU_AMD_NB_TA		"nb.ta"
+#define	FM_EREPORT_CPU_AMD_NB_GART_WALK		"nb.gart_walk"
+#define	FM_EREPORT_CPU_AMD_NB_RMW		"nb.rmw"
+#define	FM_EREPORT_CPU_AMD_NB_WDOG		"nb.wdog"
+
+#define	FM_EREPORT_CPU_AMD_UNKNOWN		"unknown"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_FM_CPU_AMD_H */
diff --git a/usr/src/uts/intel/sys/mc.h b/usr/src/uts/intel/sys/mc.h
new file mode 100644
index 0000000000..416f323c86
--- /dev/null
+++ b/usr/src/uts/intel/sys/mc.h
@@ -0,0 +1,80 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ *
+ * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_MC_H
+#define	_SYS_MC_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * Public interfaces exposed by the memory controller driver
+ */
+
+#include <sys/cpuvar.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define	MC_UNUM_NAMLEN		192
+#define	MC_UNUM_NDIMM		8
+
+typedef struct mc_unum {
+	int unum_board;
+	int unum_chip;
+	int unum_mc;
+	int unum_cs;
+	uint64_t unum_offset;
+	int unum_dimms[MC_UNUM_NDIMM];
+} mc_unum_t;
+
+#define	MC_AMD_DEV_OFFSET	24	/* node ID + offset == PCI dev num */
+
+#define	MC_IOC			(0x4d43 << 16)
+#define	MC_IOC_SNAPSHOT_INFO	(MC_IOC | 1)
+#define	MC_IOC_SNAPSHOT		(MC_IOC | 2)
+
+/*
+ * Prior to requesting a copy of the snapshot, consumers are advised to request
+ * information regarding the snapshot.  An mc_snapshot_info_t will be returned,
+ * containing the snapshot size as well as the snapshot generation number.  Note
+ * that, due to the potentially dynamic nature of the system, the snapshot may
+ * change at any time.  As such, the information in the mc_snapshot_info_t may
+ * be out of date by the time it is used.  The generation number is used to
+ * track snapshot changes.  That is, the generation number will be updated each
+ * time the source data for the snapshot is updated.  The consumer should not
+ * attach any meaning to the magnitude of a generation number change, and pay
+ * attention only to the fact that the number has changed.
+ */
+typedef struct mc_snapshot_info {
+	uint32_t mcs_size;	/* snapshot size */
+	uint_t mcs_gen;		/* snapshot generation number */
+} mc_snapshot_info_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_MC_H */
diff --git a/usr/src/uts/intel/sys/mc_amd.h b/usr/src/uts/intel/sys/mc_amd.h
new file mode 100644
index 0000000000..fba266b14f
--- /dev/null
+++ b/usr/src/uts/intel/sys/mc_amd.h
@@ -0,0 +1,195 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ *
+ * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _MC_AMD_H
+#define	_MC_AMD_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * Definitions describing various memory controller constant properties and
+ * the structure of configuration registers.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Configuration constants
+ */
+#define	MC_CHIP_NDIMM		8	/* max dimms per MC */
+#define	MC_CHIP_NCS		8	/* number of chip-selects per MC */
+#define	MC_CHIP_DIMMRANKMAX	4	/* largest number of ranks per dimm */
+#define	MC_CHIP_DIMMPERCS	2	/* max number of dimms per cs */
+#define	MC_CHIP_DIMMPAIR(csnum)	(csnum / MC_CHIP_DIMMPERCS)
+
+/*
+ * Encoding of chip version variations that we need to distinguish
+ */
+#define	MC_REV_UNKNOWN	-1u	/* unknown AMD revision */
+#define	MC_REV_PRE_D	0	/* B/C/CG */
+#define	MC_REV_D_E	1	/* D or E */
+#define	MC_REV_F	2	/* F */
+
+/*
+ * BKDG 3.29 section 3.4.4.1 - DRAM base i registers
+ */
+#define	MC_AM_DB_DRAMBASE_MASK	0xffff0000
+#define	MC_AM_DB_DRAMBASE_LSHFT	8
+#define	MC_AM_DB_DRAMBASE(regval) \
+	(((uint64_t)(regval) & MC_AM_DB_DRAMBASE_MASK) << \
+	MC_AM_DB_DRAMBASE_LSHFT)
+#define	MC_AM_DB_INTLVEN_MASK	0x00000700
+#define	MC_AM_DB_INTLVEN_SHIFT	8
+#define	MC_AM_DB_WE		0x00000002
+#define	MC_AM_DB_RE		0x00000001
+
+/*
+ * BKDG 3.29 section 3.4.4.2 - DRAM limit i registers
+ */
+#define	MC_AM_DL_DRAMLIM_MASK	0xffff0000
+#define	MC_AM_DL_DRAMLIM_SHIFT	16
+#define	MC_AM_DL_DRAMLIM_LSHFT	8
+#define	MC_AM_DL_DRAMLIM(regval) \
+	((((uint64_t)(regval) & MC_AM_DL_DRAMLIM_MASK) << \
+	MC_AM_DL_DRAMLIM_LSHFT) | ((regval) ? \
+	((1 << (MC_AM_DL_DRAMLIM_SHIFT + MC_AM_DL_DRAMLIM_LSHFT)) - 1) : 0))
+#define	MC_AM_DL_INTLVSEL_MASK	0x00000700
+#define	MC_AM_DL_INTLVSEL_SHIFT	8
+#define	MC_AM_DL_DSTNODE_MASK	0x00000007
+
+/*
+ * BKDG 3.29 section 3.5.4 - DRAM CS Base Address Registers.
+ *
+ * MC_DC_CSB_CSBASE combines the BaseAddrHi and BaseAddrLo into a single
+ * uint64_t, shifting them into the dram address bits they describe.
+ */
+#define	MC_DC_CSB_BASEHI_MASK	0xffe00000
+#define	MC_DC_CSB_BASEHI_LSHFT	4
+
+#define	MC_DC_CSB_BASELO_MASK	0x0000fe00
+#define	MC_DC_CSB_BASELO_LSHFT	4
+
+#define	MC_DC_CSB_CSBASE(regval) \
+	((((uint64_t)(regval) & MC_DC_CSB_BASEHI_MASK) << \
+	MC_DC_CSB_BASEHI_LSHFT) | (((uint64_t)(regval) & \
+	MC_DC_CSB_BASELO_MASK) << MC_DC_CSB_BASELO_LSHFT))
+
+#define	MC_DC_CSB_CSBE		0x00000001
+
+/*
+ * BKDG 3.29 section 3.5.5 - DRAM CS Mask Registers.
+ *
+ * MC_DC_CSM_CSMASK combines the AddrMaskHi and AddrMaskLo into a single
+ * uint64_t, shifting them into the dram address bit positions they mask.
+ * It also fills the gaps between high and low mask and below the low mask.
+ * MC_DC_CSM_UNMASKED_BITS indicates the number of high dram address bits
+ * above MC_DC_CSM_MASKHI_HIBIT that cannot be masked.
+ */
+#define	MC_DC_CSM_MASKHI_MASK	0x3fe00000
+#define	MC_DC_CSM_MASKHI_LSHFT	4
+#define	MC_DC_CSM_MASKHI_LOBIT	25
+#define	MC_DC_CSM_MASKHI_HIBIT	33
+
+#define	MC_DC_CSM_MASKLO_MASK	0x0000fe00
+#define	MC_DC_CSM_MASKLO_LOBIT	13
+#define	MC_DC_CSM_MASKLO_HIBIT	19
+#define	MC_DC_CSM_MASKLO_LSHFT	4
+
+#define	MC_DC_CSM_MASKFILL	0x1f01fff	/* [24:20] and [12:0] */
+
+#define	MC_DC_CSM_UNMASKED_BITS	2
+
+#define	MC_DC_CSM_CSMASK(regval) \
+	((((uint64_t)(regval) & MC_DC_CSM_MASKHI_MASK) << \
+	MC_DC_CSM_MASKHI_LSHFT) | (((uint64_t)(regval) & \
+	MC_DC_CSM_MASKLO_MASK) << MC_DC_CSM_MASKLO_LSHFT) | \
+	MC_DC_CSM_MASKFILL)
+
+/*
+ * BKDG 3.29 section 3.5.6 - DRAM Bank Address Mapping Register
+ */
+#define	MC_DC_BAM_CSBANK_MASK	0x0000000f
+#define	MC_DC_BAM_CSBANK_SHIFT	4
+#define	MC_DC_BAM_CSBANK_SWIZZLE 0x40000000
+
+/*
+ * BKDG 3.29 section 3.4.8 - DRAM Hole register, revs E and later
+ */
+#define	MC_DC_HOLE_VALID		0x00000001
+#define	MC_DC_HOLE_OFFSET_MASK		0x0000ff00
+#define	MC_DC_HOLE_OFFSET_LSHIFT	16
+
+/*
+ * BKDG 3.29 section 3.5.11  - DRAM configuration high and low registers.
+ * The following defines may be applied to a uint64_t made by
+ * concatenating those two 32-bit registers.
+ */
+#define	MC_DC_DCFG_DLL_DIS		0x0000000000000001
+#define	MC_DC_DCFG_D_DRV		0x0000000000000002
+#define	MC_DC_DCFG_QFC_EN		0x0000000000000004
+#define	MC_DC_DCFG_DISDQSYS		0x0000000000000008
+#define	MC_DC_DCFG_BURST2OPT		0x0000000000000020
+#define	MC_DC_DCFG_MOD64BITMUX		0x0000000000000040
+#define	MC_DC_DCFG_PWRDWNTRIEN		0x0000000000000080 /* >= rev E */
+#define	MC_DC_DCFG_SCRATCHBIT		0x0000000000000080 /* <= rev D */
+#define	MC_DC_DCFG_DRAMINIT		0x0000000000000100
+#define	MC_DC_DCFG_DUALDIMMEN		0x0000000000000200
+#define	MC_DC_DCFG_DRAMENABLE		0x0000000000000400
+#define	MC_DC_DCFG_MEMCLRSTATUS		0x0000000000000800
+#define	MC_DC_DCFG_ESR			0x0000000000001000
+#define	MC_DC_DCFG_SR_S			0x0000000000002000
+#define	MC_DC_DCFG_RDWRQBYP_MASK	0x000000000000c000
+#define	MC_DC_DCFG_128			0x0000000000010000
+#define	MC_DC_DCFG_DIMMECEN		0x0000000000020000
+#define	MC_DC_DCFG_UNBUFFDIMM		0x0000000000040000
+#define	MC_DC_DCFG_32BYTEEN		0x0000000000080000
+#define	MC_DC_DCFG_X4DIMMS_MASK		0x0000000000f00000
+#define	MC_DC_DCFG_X4DIMMS_SHIFT	20
+#define	MC_DC_DCFG_DISINRCVRS		0x0000000001000000
+#define	MC_DC_DCFG_BYPMAX_MASK		0x000000000e000000
+#define	MC_DC_DCFG_EN2T			0x0000000010000000
+#define	MC_DC_DCFG_UPPERCSMAP		0x0000000020000000
+#define	MC_DC_DCFG_PWRDOWNCTL_MASK	0x00000000c0000000
+#define	MC_DC_DCFG_ASYNCLAT_MASK	0x0000000f00000000
+#define	MC_DC_DCFG_RDPREAMBLE_MASK	0x00000f0000000000
+#define	MC_DC_DCFG_MEMDQDRVSTREN_MASK	0x0000600000000000
+#define	MC_DC_DCFG_DISABLEJITTER	0x0000800000000000
+#define	MC_DC_DCFG_ILD_LMT_MASK		0x0007000000000000
+#define	MC_DC_DCFG_ECC_EN		0x0008000000000000
+#define	MC_DC_DCFG_MEMCLK_MASK		0x0070000000000000
+#define	MC_DC_DCFG_MCR			0x0200000000000000
+#define	MC_DC_DCFG_MC0_EN		0x0400000000000000
+#define	MC_DC_DCFG_MC1_EN		0x0800000000000000
+#define	MC_DC_DCFG_MC2_EN		0x1000000000000000
+#define	MC_DC_DCFG_MC3_EN		0x2000000000000000
+#define	MC_DC_DCFG_ODDDIVISORCORRECT	0x8000000000000000
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MC_AMD_H */
diff --git a/usr/src/uts/intel/sys/mca_amd.h b/usr/src/uts/intel/sys/mca_amd.h
new file mode 100644
index 0000000000..21524f8713
--- /dev/null
+++ b/usr/src/uts/intel/sys/mca_amd.h
@@ -0,0 +1,418 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_MCA_AMD_H
+#define	_SYS_MCA_AMD_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * Constants the Memory Check Architecture as implemented on AMD CPUs.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define	AMD_MSR_MCG_CAP			0x179
+#define	AMD_MSR_MCG_STATUS		0x17a
+#define	AMD_MSR_MCG_CTL			0x17b
+
+#define	AMD_MCA_BANK_DC			0	/* Data Cache */
+#define	AMD_MCA_BANK_IC			1	/* Instruction Cache */
+#define	AMD_MCA_BANK_BU			2	/* Bus Unit */
+#define	AMD_MCA_BANK_LS			3	/* Load/Store Unit */
+#define	AMD_MCA_BANK_NB			4	/* Northbridge */
+#define	AMD_MCA_BANK_COUNT		5
+
+#define	AMD_MSR_DC_CTL			0x400
+#define	AMD_MSR_DC_MASK			0xc0010044
+#define	AMD_MSR_DC_STATUS		0x401
+#define	AMD_MSR_DC_ADDR			0x402
+
+#define	AMD_MSR_IC_CTL			0x404
+#define	AMD_MSR_IC_MASK			0xc0010045
+#define	AMD_MSR_IC_STATUS		0x405
+#define	AMD_MSR_IC_ADDR			0x406
+
+#define	AMD_MSR_BU_CTL			0x408
+#define	AMD_MSR_BU_MASK			0xc0010046
+#define	AMD_MSR_BU_STATUS		0x409
+#define	AMD_MSR_BU_ADDR			0x40a
+
+#define	AMD_MSR_LS_CTL			0x40c
+#define	AMD_MSR_LS_MASK			0xc0010047
+#define	AMD_MSR_LS_STATUS		0x40d
+#define	AMD_MSR_LS_ADDR			0x40e
+
+#define	AMD_MSR_NB_CTL			0x410
+#define	AMD_MSR_NB_MASK			0xc0010048
+#define	AMD_MSR_NB_STATUS		0x411
+#define	AMD_MSR_NB_ADDR			0x412
+
+#define	AMD_MCG_EN_DC			0x01
+#define	AMD_MCG_EN_IC			0x02
+#define	AMD_MCG_EN_BU			0x04
+#define	AMD_MCG_EN_LS			0x08
+#define	AMD_MCG_EN_NB			0x10
+#define	AMD_MCG_EN_ALL \
+	(AMD_MCG_EN_DC | AMD_MCG_EN_IC | AMD_MCG_EN_BU | AMD_MCG_EN_LS | \
+	AMD_MCG_EN_NB)
+
+/*
+ * Data Cache (DC) bank error-detection enabling bits and CTL register
+ * initializer value.
+ */
+
+#define	AMD_DC_EN_ECCI			0x00000001ULL
+#define	AMD_DC_EN_ECCM			0x00000002ULL
+#define	AMD_DC_EN_DECC			0x00000004ULL
+#define	AMD_DC_EN_DMTP			0x00000008ULL
+#define	AMD_DC_EN_DSTP			0x00000010ULL
+#define	AMD_DC_EN_L1TP			0x00000020ULL
+#define	AMD_DC_EN_L2TP			0x00000040ULL
+
+#define	AMD_DC_CTL_INIT \
+	(AMD_DC_EN_ECCI | AMD_DC_EN_ECCM | AMD_DC_EN_DECC | AMD_DC_EN_DMTP | \
+	AMD_DC_EN_DSTP | AMD_DC_EN_L1TP | AMD_DC_EN_L2TP)
+
+/*
+ * Instruction Cache (IC) bank error-detection enabling bits and CTL register
+ * initializer value.
+ *
+ * The Northbridge will handle Read Data errors.  Our initializer will enable
+ * all but the RDDE detector.
+ */
+
+#define	AMD_IC_EN_ECCI			0x00000001ULL
+#define	AMD_IC_EN_ECCM			0x00000002ULL
+#define	AMD_IC_EN_IDP			0x00000004ULL
+#define	AMD_IC_EN_IMTP			0x00000008ULL
+#define	AMD_IC_EN_ISTP			0x00000010ULL
+#define	AMD_IC_EN_L1TP			0x00000020ULL
+#define	AMD_IC_EN_L2TP			0x00000040ULL
+#define	AMD_IC_EN_RDDE			0x00000200ULL
+
+#define	AMD_IC_CTL_INIT \
+	(AMD_IC_EN_ECCI | AMD_IC_EN_ECCM | AMD_IC_EN_IDP | AMD_IC_EN_IMTP | \
+	AMD_IC_EN_ISTP | AMD_IC_EN_L1TP | AMD_IC_EN_L2TP)
+
+/*
+ * Bus Unit (BU) bank error-detection enabling bits and CTL register
+ * initializer value.
+ *
+ * The Northbridge will handle Read Data errors.  Our initializer will enable
+ * all but the S_RDE_* detectors.
+ */
+
+#define	AMD_BU_EN_S_RDE_HP		0x00000001ULL
+#define	AMD_BU_EN_S_RDE_TLB		0x00000002ULL
+#define	AMD_BU_EN_S_RDE_ALL		0x00000004ULL
+#define	AMD_BU_EN_S_ECC1_TLB		0x00000008ULL
+#define	AMD_BU_EN_S_ECC1_HP		0x00000010ULL
+#define	AMD_BU_EN_S_ECCM_TLB		0x00000020ULL
+#define	AMD_BU_EN_S_ECCM_HP		0x00000040ULL
+#define	AMD_BU_EN_L2T_PAR_ICDC		0x00000080ULL
+#define	AMD_BU_EN_L2T_PAR_TLB		0x00000100ULL
+#define	AMD_BU_EN_L2T_PAR_SNP		0x00000200ULL
+#define	AMD_BU_EN_L2T_PAR_CPB		0x00000400ULL
+#define	AMD_BU_EN_L2T_PAR_SCR		0x00000800ULL
+#define	AMD_BU_EN_L2D_ECC1_TLB		0x00001000ULL
+#define	AMD_BU_EN_L2D_ECC1_SNP		0x00002000ULL
+#define	AMD_BU_EN_L2D_ECC1_CPB		0x00004000ULL
+#define	AMD_BU_EN_L2D_ECCM_TLB		0x00008000ULL
+#define	AMD_BU_EN_L2D_ECCM_SNP		0x00010000ULL
+#define	AMD_BU_EN_L2D_ECCM_CPB		0x00020000ULL
+#define	AMD_BU_EN_L2T_ECC1_SCR		0x00040000ULL
+#define	AMD_BU_EN_L2T_ECCM_SCR		0x00080000ULL
+
+#define	AMD_BU_CTL_INIT \
+	(AMD_BU_EN_S_ECC1_TLB | AMD_BU_EN_S_ECC1_HP | \
+	AMD_BU_EN_S_ECCM_TLB | AMD_BU_EN_S_ECCM_HP | \
+	AMD_BU_EN_L2T_PAR_ICDC | AMD_BU_EN_L2T_PAR_TLB | \
+	AMD_BU_EN_L2T_PAR_SNP |	AMD_BU_EN_L2T_PAR_CPB | \
+	AMD_BU_EN_L2T_PAR_SCR |	AMD_BU_EN_L2D_ECC1_TLB | \
+	AMD_BU_EN_L2D_ECC1_SNP | AMD_BU_EN_L2D_ECC1_CPB | \
+	AMD_BU_EN_L2D_ECCM_TLB | AMD_BU_EN_L2D_ECCM_SNP | \
+	AMD_BU_EN_L2D_ECCM_CPB | AMD_BU_EN_L2T_ECC1_SCR | \
+	AMD_BU_EN_L2T_ECCM_SCR)
+
+/*
+ * Load/Store (LS) bank error-detection enabling bits and CTL register
+ * initializer value.
+ *
+ * The Northbridge will handle Read Data errors.  That's the only type of
+ * error the LS unit can detect at present, so we won't be enabling any
+ * LS detectors.
+ */
+
+#define	AMD_LS_EN_S_RDE_S		0x00000001ULL
+#define	AMD_LS_EN_S_RDE_L		0x00000002ULL
+
+#define	AMD_LS_CTL_INIT			0ULL
+
+/*
+ * The Northbridge (NB) is configured using both the standard MCA CTL register
+ * and a NB-specific configuration register (NB CFG).  The AMD_NB_EN_* macros
+ * are the detector enabling bits for the NB MCA CTL register.  The
+ * AMD_NB_CFG_* bits are for the NB CFG register.
+ *
+ * The CTL register can be initialized statically, but portions of the NB CFG
+ * register must be initialized based on the current machine's configuration.
+ *
+ * The MCA NB Control Register maps to MC4_CTL[31:0].
+ *
+ */
+#define	AMD_NB_EN_CORRECC		0x00000001
+#define	AMD_NB_EN_UNCORRECC		0x00000002
+#define	AMD_NB_EN_CRCERR0		0x00000004
+#define	AMD_NB_EN_CRCERR1		0x00000008
+#define	AMD_NB_EN_CRCERR2		0x00000010
+#define	AMD_NB_EN_SYNCPKT0		0x00000020
+#define	AMD_NB_EN_SYNCPKT1		0x00000040
+#define	AMD_NB_EN_SYNCPKT2		0x00000080
+#define	AMD_NB_EN_MSTRABRT		0x00000100
+#define	AMD_NB_EN_TGTABRT		0x00000200
+#define	AMD_NB_EN_GARTTBLWK		0x00000400
+#define	AMD_NB_EN_ATOMICRMW		0x00000800
+#define	AMD_NB_EN_WCHDOGTMR		0x00001000
+
+#define	AMD_NB_CTL_INIT /* All but GARTTBLWK */ \
+	(AMD_NB_EN_CORRECC | AMD_NB_EN_UNCORRECC | \
+	AMD_NB_EN_CRCERR0 | AMD_NB_EN_CRCERR1 | AMD_NB_EN_CRCERR2 | \
+	AMD_NB_EN_SYNCPKT0 | AMD_NB_EN_SYNCPKT1 | AMD_NB_EN_SYNCPKT2 | \
+	AMD_NB_EN_MSTRABRT | AMD_NB_EN_TGTABRT | \
+	AMD_NB_EN_ATOMICRMW | AMD_NB_EN_WCHDOGTMR)
+
+#define	AMD_NB_CFG_CPUECCERREN		0x00000001
+#define	AMD_NB_CFG_CPURDDATERREN	0x00000002
+#define	AMD_NB_CFG_SYNCONUCECCEN	0x00000004
+#define	AMD_NB_CFG_SYNCPKTGENDIS	0x00000008
+#define	AMD_NB_CFG_SYNCPKTPROPDIS	0x00000010
+#define	AMD_NB_CFG_IOMSTABORTDIS	0x00000020
+#define	AMD_NB_CFG_CPUERRDIS		0x00000040
+#define	AMD_NB_CFG_IOERRDIS		0x00000080
+#define	AMD_NB_CFG_WDOGTMRDIS		0x00000100
+#define	AMD_NB_CFG_SYNCONWDOGEN		0x00100000
+#define	AMD_NB_CFG_SYNCONANYERREN	0x00200000
+#define	AMD_NB_CFG_ECCEN		0x00400000
+#define	AMD_NB_CFG_CHIPKILLECCEN	0x00800000
+#define	AMD_NB_CFG_IORDDATERREN		0x01000000
+#define	AMD_NB_CFG_DISPCICFGCPUERRRSP	0x02000000
+#define	AMD_NB_CFG_NBMCATOMSTCPUEN	0x08000000
+
+#define	AMD_NB_CFG_WDOGTMRCNTSEL_4095	0x00000000
+#define	AMD_NB_CFG_WDOGTMRCNTSEL_2047	0x00000200
+#define	AMD_NB_CFG_WDOGTMRCNTSEL_1023	0x00000400
+#define	AMD_NB_CFG_WDOGTMRCNTSEL_511	0x00000600
+#define	AMD_NB_CFG_WDOGTMRCNTSEL_255	0x00000800
+#define	AMD_NB_CFG_WDOGTMRCNTSEL_127	0x00000a00
+#define	AMD_NB_CFG_WDOGTMRCNTSEL_63	0x00000c00
+#define	AMD_NB_CFG_WDOGTMRCNTSEL_31	0x00000e00
+#define	AMD_NB_CFG_WDOGTMRCNTSEL_MASK	0x00000e00
+#define	AMD_NB_CFG_WDOGTMRCNTSEL_SHIFT	9
+
+#define	AMD_NB_CFG_WDOGTMRBASESEL_1MS	0x00000000
+#define	AMD_NB_CFG_WDOGTMRBASESEL_1US	0x00001000
+#define	AMD_NB_CFG_WDOGTMRBASESEL_5NS	0x00002000
+#define	AMD_NB_CFG_WDOGTMRBASESEL_MASK	0x00003000
+#define	AMD_NB_CFG_WDOGTMRBASESEL_SHIFT	12
+
+#define	AMD_NB_CFG_LDTLINKSEL_MASK	0x0000c000
+#define	AMD_NB_CFG_LDTLINKSEL_SHIFT	14
+
+#define	AMD_NB_CFG_GENCRCERRBYTE0	0x00010000
+#define	AMD_NB_CFG_GENCRCERRBYTE1	0x00020000
+
+/* Generic bank status register bits */
+#define	AMD_BANK_STAT_VALID		0x8000000000000000
+#define	AMD_BANK_STAT_OVER		0x4000000000000000
+#define	AMD_BANK_STAT_UC		0x2000000000000000
+#define	AMD_BANK_STAT_EN		0x1000000000000000
+#define	AMD_BANK_STAT_MISCV		0x0800000000000000
+#define	AMD_BANK_STAT_ADDRV		0x0400000000000000
+#define	AMD_BANK_STAT_PCC		0x0200000000000000
+
+#define	AMD_BANK_STAT_CECC		0x0000400000000000
+#define	AMD_BANK_STAT_UECC		0x0000200000000000
+#define	AMD_BANK_STAT_SCRUB		0x0000010000000000
+
+#define	AMD_BANK_STAT_SYND_MASK		0x007f800000000000 /* syndrome[7:0] */
+#define	AMD_BANK_STAT_SYND_SHIFT	47
+
+#define	AMD_BANK_SYND(stat) \
+	(((stat) & AMD_BANK_STAT_SYND_MASK) >> AMD_BANK_STAT_SYND_SHIFT)
+#define	AMD_BANK_MKSYND(synd) \
+	(((uint64_t)(synd) << AMD_BANK_STAT_SYND_SHIFT) & \
+	AMD_BANK_STAT_SYND_MASK)
+
+/* northbridge (NB) status registers */
+
+#define	AMD_NB_FUNC			3
+#define	AMD_NB_REG_CFG			0x44
+#define	AMD_NB_REG_STLO			0x48	/* alias: NB_STATUS[0:31] */
+#define	AMD_NB_REG_STHI			0x4c	/* alias: NB_STATUS[32:63] */
+#define	AMD_NB_REG_ADDRLO		0x50	/* alias: NB_ADDR[0:31] */
+#define	AMD_NB_REG_ADDRHI		0x54	/* alias: NB_ADDR[32:63] */
+
+#define	AMD_NB_REG_SCRUBCTL		0x58
+#define	AMD_NB_REG_SCRUBADDR_LO		0x5c
+#define	AMD_NB_REG_SCRUBADDR_HI		0x60
+
+#define	AMD_NB_STAT_LDTLINK_MASK	0x0000007000000000
+#define	AMD_NB_STAT_LDTLINK_SHIFT	4
+#define	AMD_NB_STAT_ERRCPU1		0x0000000200000000
+#define	AMD_NB_STAT_ERRCPU0		0x0000000100000000
+#define	AMD_NB_STAT_CKSYND_MASK		0x00000000ff000000 /* syndrome[15:8] */
+#define	AMD_NB_STAT_CKSYND_SHIFT	(24 - 8) /* shift [31:24] to [15:8] */
+
+#define	AMD_NB_STAT_CKSYND(stat) \
+	((((stat) & AMD_NB_STAT_CKSYND_MASK) >> AMD_NB_STAT_CKSYND_SHIFT) | \
+	AMD_BANK_SYND((stat)))
+
+#define	AMD_NB_STAT_MKCKSYND(synd) \
+	((((uint64_t)(synd) << AMD_NB_STAT_CKSYND_SHIFT) & \
+	AMD_NB_STAT_CKSYND_MASK) | AMD_BANK_MKSYND(synd))
+
+#define	AMD_ERRCODE_MASK		0x000000000000ffff
+#define	AMD_ERREXT_MASK			0x00000000000f0000
+#define	AMD_ERREXT_SHIFT		16
+
+#define	AMD_ERRCODE_TT_MASK		0x000c
+#define	AMD_ERRCODE_TT_SHIFT		2
+#define	AMD_ERRCODE_TT_INSTR		0x0
+#define	AMD_ERRCODE_TT_DATA		0x1
+#define	AMD_ERRCODE_TT_GEN		0x2
+
+#define	AMD_ERRCODE_LL_MASK		0x0003
+#define	AMD_ERRCODE_LL_L0		0x0
+#define	AMD_ERRCODE_LL_L1		0x1
+#define	AMD_ERRCODE_LL_L2		0x2
+#define	AMD_ERRCODE_LL_LG		0x3
+
+#define	AMD_ERRCODE_R4_MASK		0x00f0
+#define	AMD_ERRCODE_R4_SHIFT		4
+#define	AMD_ERRCODE_R4_GEN		0x0
+#define	AMD_ERRCODE_R4_RD		0x1
+#define	AMD_ERRCODE_R4_WR		0x2
+#define	AMD_ERRCODE_R4_DRD		0x3
+#define	AMD_ERRCODE_R4_DWR		0x4
+#define	AMD_ERRCODE_R4_IRD		0x5
+#define	AMD_ERRCODE_R4_PREFETCH		0x6
+#define	AMD_ERRCODE_R4_EVICT		0x7
+#define	AMD_ERRCODE_R4_SNOOP		0x8
+
+#define	AMD_ERRCODE_PP_MASK		0x0600
+#define	AMD_ERRCODE_PP_SHIFT		9
+#define	AMD_ERRCODE_PP_SRC		0x0
+#define	AMD_ERRCODE_PP_RSP		0x1
+#define	AMD_ERRCODE_PP_OBS		0x2
+#define	AMD_ERRCODE_PP_GEN		0x3
+
+#define	AMD_ERRCODE_T_MASK		0x0100
+#define	AMD_ERRCODE_T_SHIFT		8
+#define	AMD_ERRCODE_T_NONE		0x0
+#define	AMD_ERRCODE_T_TIMEOUT		0x1
+
+#define	AMD_ERRCODE_II_MASK		0x000c
+#define	AMD_ERRCODE_II_SHIFT		2
+#define	AMD_ERRCODE_II_MEM		0x0
+#define	AMD_ERRCODE_II_IO		0x2
+#define	AMD_ERRCODE_II_GEN		0x3
+
+#define	AMD_ERRCODE_TLB_BIT		4
+#define	AMD_ERRCODE_MEM_BIT		8
+#define	AMD_ERRCODE_BUS_BIT		11
+
+#define	AMD_ERRCODE_TLB_MASK		0xfff0
+#define	AMD_ERRCODE_TLB_VAL		0x0010
+#define	AMD_ERRCODE_MEM_MASK		0xff00
+#define	AMD_ERRCODE_MEM_VAL		0x0100
+#define	AMD_ERRCODE_BUS_MASK		0xf800
+#define	AMD_ERRCODE_BUS_VAL		0x0800
+
+#define	AMD_ERRCODE_MKTLB(tt, ll) \
+	(AMD_ERRCODE_TLB_VAL | \
+	(((tt) << AMD_ERRCODE_TT_SHIFT) & AMD_ERRCODE_TT_MASK) | \
+	((ll) & AMD_ERRCODE_LL_MASK))
+#define	AMD_ERRCODE_ISTLB(code) \
+	(((code) & AMD_ERRCODE_TLB_MASK) == AMD_ERRCODE_TLB_VAL)
+
+#define	AMD_ERRCODE_MKMEM(r4, tt, ll) \
+	(AMD_ERRCODE_MEM_VAL | \
+	(((r4) << AMD_ERRCODE_R4_SHIFT) & AMD_ERRCODE_R4_MASK) | \
+	(((tt) << AMD_ERRCODE_TT_SHIFT) & AMD_ERRCODE_TT_MASK) | \
+	((ll) & AMD_ERRCODE_LL_MASK))
+#define	AMD_ERRCODE_ISMEM(code) \
+	(((code) & AMD_ERRCODE_MEM_MASK) == AMD_ERRCODE_MEM_VAL)
+
+#define	AMD_ERRCODE_MKBUS(pp, t, r4, ii, ll) \
+	(AMD_ERRCODE_BUS_VAL | \
+	(((pp) << AMD_ERRCODE_PP_SHIFT) & AMD_ERRCODE_PP_MASK) | \
+	(((t) << AMD_ERRCODE_T_SHIFT) & AMD_ERRCODE_T_MASK) | \
+	(((r4) << AMD_ERRCODE_R4_SHIFT) & AMD_ERRCODE_R4_MASK) | \
+	(((ii) << AMD_ERRCODE_II_SHIFT) & AMD_ERRCODE_II_MASK) | \
+	((ll) & AMD_ERRCODE_LL_MASK))
+#define	AMD_ERRCODE_ISBUS(code) \
+	(((code) & AMD_ERRCODE_BUS_MASK) == AMD_ERRCODE_BUS_VAL)
+
+#define	AMD_NB_ADDRLO_MASK		0xfffffff8
+#define	AMD_NB_ADDRHI_MASK		0x000000ff
+
+#define	AMD_SYNDTYPE_ECC		0
+#define	AMD_SYNDTYPE_CHIPKILL		1
+
+#define	AMD_NB_SCRUBCTL_DRAM_MASK	0x0000001f
+#define	AMD_NB_SCRUBCTL_DRAM_SHIFT	0
+#define	AMD_NB_SCRUBCTL_L2_MASK		0x00001f00
+#define	AMD_NB_SCRUBCTL_L2_SHIFT	8
+#define	AMD_NB_SCRUBCTL_DC_MASK		0x001f0000
+#define	AMD_NB_SCRUBCTL_DC_SHIFT	16
+
+#define	AMD_NB_SCRUBCTL_RATE_NONE	0
+#define	AMD_NB_SCRUBCTL_RATE_MAX	0x16
+
+#define	AMD_NB_SCRUBADDR_LO_MASK	0xffffffc0
+#define	AMD_NB_SCRUBADDR_LO_SCRUBREDIREN 0x1
+#define	AMD_NB_SCRUBADDR_HI_MASK	0x000000ff
+
+#define	AMD_NB_SCRUBADDR_MKLO(addr) \
+	((addr) & AMD_NB_SCRUBADDR_LO_MASK)
+
+#define	AMD_NB_SCRUBADDR_MKHI(addr) \
+	(((addr) >> 32) & AMD_NB_SCRUBADDR_HI_MASK)
+
+#define	AMD_NB_MKSCRUBCTL(dc, l2, dr) ( \
+	(((dc) << AMD_NB_SCRUBCTL_DC_SHIFT) & AMD_NB_SCRUBCTL_DC_MASK) | \
+	(((l2) << AMD_NB_SCRUBCTL_L2_SHIFT) & AMD_NB_SCRUBCTL_L2_MASK) | \
+	(((dr) << AMD_NB_SCRUBCTL_DRAM_SHIFT) & AMD_NB_SCRUBCTL_DRAM_MASK))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_MCA_AMD_H */
diff --git a/usr/src/uts/intel/sys/mca_x86.h b/usr/src/uts/intel/sys/mca_x86.h
new file mode 100644
index 0000000000..78066bdc63
--- /dev/null
+++ b/usr/src/uts/intel/sys/mca_x86.h
@@ -0,0 +1,126 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ *
+ * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_MCA_X86_H
+#define	_SYS_MCA_X86_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * Constants for the Memory Check Architecture as implemented on generic x86
+ * CPUs.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Intel has defined a number of MSRs as part of the IA32 architecture.  The
+ * MCG registers are part of that set, as are the first four banks (0-3) as
+ * implemented by the P4 processor.  Bank MSRs were laid out slightly
+ * differently on the P6 family of processors, and thus have their own #defines
+ * following the architecture-generic ones.
+ */
+#define	IA32_MSR_MCG_CAP		0x179
+#define	IA32_MSR_MCG_STATUS		0x17a
+#define	IA32_MSR_MCG_CTL		0x17b
+
+#define	MCG_CAP_COUNT_MASK		0x000000ffULL
+#define	MCG_CAP_CTL_P			0x00000100ULL
+#define	MCG_CAP_EXT_P			0x00000200ULL
+#define	MCG_CAP_EXT_CNT_MASK		0x00ff0000ULL
+#define	MCG_CAP_EXT_CNT_SHIFT		16
+
+#define	MCG_STATUS_RIPV			0x01
+#define	MCG_STATUS_EIPV			0x02
+#define	MCG_STATUS_MCIP			0x04
+
+#define	IA32_MSR_MC0_CTL		0x400
+#define	IA32_MSR_MC0_STATUS		0x401
+#define	IA32_MSR_MC0_ADDR		0x402
+#define	IA32_MSR_MC0_MISC		0x403
+
+#define	IA32_MSR_MC1_CTL		0x404
+#define	IA32_MSR_MC1_STATUS		0x405
+#define	IA32_MSR_MC1_ADDR		0x406
+#define	IA32_MSR_MC1_MISC		0x407
+
+#define	IA32_MSR_MC2_CTL		0x408
+#define	IA32_MSR_MC2_STATUS		0x409
+#define	IA32_MSR_MC2_ADDR		0x40a
+#define	IA32_MSR_MC2_MISC		0x40b
+
+#define	IA32_MSR_MC3_CTL		0x40c
+#define	IA32_MSR_MC3_STATUS		0x40d
+#define	IA32_MSR_MC3_ADDR		0x40e
+#define	IA32_MSR_MC3_MISC		0x40f
+
+#define	MSR_MC_STATUS_VAL		0x8000000000000000ULL
+#define	MSR_MC_STATUS_O			0x4000000000000000ULL
+#define	MSR_MC_STATUS_UC		0x2000000000000000ULL
+#define	MSR_MC_STATUS_EN		0x1000000000000000ULL
+#define	MSR_MC_STATUS_MISCV		0x0800000000000000ULL
+#define	MSR_MC_STATUS_ADDRV		0x0400000000000000ULL
+#define	MSR_MC_STATUS_PCC		0x0200000000000000ULL
+#define	MSR_MC_STATUS_OTHER_MASK	0x01ffffff00000000ULL
+#define	MSR_MC_STATUS_OTHER_SHIFT	32
+#define	MSR_MC_STATUS_MSERR_MASK	0x00000000ffff0000ULL
+#define	MSR_MC_STATUS_MSERR_SHIFT	16
+#define	MSR_MC_STATUS_MCAERR_MASK	0x000000000000ffffULL
+
+/*
+ * P6 MCA bank MSRs.  Note that the ordering is 0, 1, 2, *4*, 3.  Yes, really.
+ */
+#define	P6_MSR_MC0_CTL			0x400
+#define	P6_MSR_MC0_STATUS		0x401
+#define	P6_MSR_MC0_ADDR			0x402
+#define	P6_MSR_MC0_MISC			0x403
+
+#define	P6_MSR_MC1_CTL			0x404
+#define	P6_MSR_MC1_STATUS		0x405
+#define	P6_MSR_MC1_ADDR			0x406
+#define	P6_MSR_MC1_MISC			0x407
+
+#define	P6_MSR_MC2_CTL			0x408
+#define	P6_MSR_MC2_STATUS		0x409
+#define	P6_MSR_MC2_ADDR			0x40a
+#define	P6_MSR_MC2_MISC			0x40b
+
+#define	P6_MSR_MC4_CTL			0x40c
+#define	P6_MSR_MC4_STATUS		0x40d
+#define	P6_MSR_MC4_ADDR			0x40e
+#define	P6_MSR_MC4_MISC			0x40f
+
+#define	P6_MSR_MC3_CTL			0x410
+#define	P6_MSR_MC3_STATUS		0x411
+#define	P6_MSR_MC3_ADDR			0x412
+#define	P6_MSR_MC3_MISC			0x413
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_MCA_X86_H */
diff --git a/usr/src/uts/intel/sys/memtest.h b/usr/src/uts/intel/sys/memtest.h
new file mode 100644
index 0000000000..8e9d4fc8ef
--- /dev/null
+++ b/usr/src/uts/intel/sys/memtest.h
@@ -0,0 +1,126 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _MEMTEST_H
+#define	_MEMTEST_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * Interfaces for the memory error injection driver (memtest).  This driver is
+ * intended for use only by mtst.
+ */
+
+#include <sys/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define	MEMTEST_DEVICE		"/devices/pseudo/memtest@0:memtest"
+
+#define	MEMTEST_VERSION		1
+
+#define	MEMTESTIOC		('M' << 8)
+#define	MEMTESTIOC_INQUIRE	(MEMTESTIOC | 0)
+#define	MEMTESTIOC_CONFIG	(MEMTESTIOC | 1)
+#define	MEMTESTIOC_INJECT	(MEMTESTIOC | 2)
+#define	MEMTESTIOC_MEMREQ	(MEMTESTIOC | 3)
+#define	MEMTESTIOC_MEMREL	(MEMTESTIOC | 4)
+
+#define	MEMTEST_F_DEBUG		0x1
+
+typedef struct memtest_inq {
+	uint_t minq_version;		/* [out] driver version */
+} memtest_inq_t;
+
+/*
+ * Used by the userland injector to request a memory region from the driver.
+ * This region (or a portion thereof) will be used for the error.  The caller
+ * is expected to fill in the restrictions, if any, that are to be applied to
+ * the region.  If the driver cannot allocate a region that meets the supplied
+ * restrictions, the ioctl will fail.  Upon success, all members will be filled
+ * in with values that reflect the allocated area.
+ */
+
+#define	MEMTEST_MEMREQ_MAXNUM	5	/* maximum number of open allocations */
+#define	MEMTEST_MEMREQ_MAXSIZE	8192	/* maximum size of each allocation */
+
+#define	MEMTEST_MEMREQ_UNSPEC	((uint64_t)-1)
+
+typedef struct memtest_memreq {
+	int mreq_cpuid;			/* cpu restriction (opt, -1 if unset) */
+	uint32_t mreq_size;		/* size of allocation */
+	uint64_t mreq_vaddr;		/* [out] VA of allocation */
+	uint64_t mreq_paddr;		/* [out] PA of allocation */
+} memtest_memreq_t;
+
+/*
+ * Arrays of statements are passed to the memtest driver for error injection.
+ */
+#define	MEMTEST_INJECT_MAXNUM	20	/* Max # of stmts per INJECT ioctl */
+
+#define	MEMTEST_INJ_STMT_MSR	0x1	/* an MSR to be written */
+#define	MEMTEST_INJ_STMT_PCICFG	0x2	/* address in PCI config space */
+#define	MEMTEST_INJ_STMT_INT	0x3	/* a specific interrupt to be raised */
+#define	MEMTEST_INJ_STMT_POLL	0x4	/* tell CPU module to poll for CEs */
+
+/* Must be kept in sync with mtst_inj_statement in mtst_cpumod_api.h */
+typedef struct memtest_inj_stmt {
+	int mis_cpuid;			/* target CPU for statement */
+	uint_t mis_type;		/* MEMTEST_INJ_STMT_* */
+	union {
+		struct {		/* MEMTEST_INJ_STMT_MSR */
+			uint32_t _mis_msrnum;	/* MSR number */
+			uint32_t _mis_pad;	/* reserved */
+			uint64_t _mis_msrval;	/* value for MSR */
+		} _mis_msr;
+		struct {		/* MEMTEST_INJ_STMT_PCICFG */
+			uint32_t _mis_pciaddr;	/* address in config space */
+			uint32_t _mis_pcival;	/* value for PCI config reg */
+		} _mis_pci;
+		uint8_t _mis_int;	/* MEMTEST_INJ_STMT_INT; int num */
+	} _mis_data;
+} memtest_inj_stmt_t;
+
+#define	mis_msrnum	_mis_data._mis_msr._mis_msrnum
+#define	mis_msrval	_mis_data._mis_msr._mis_msrval
+#define	mis_pciaddr	_mis_data._mis_pci._mis_pciaddr
+#define	mis_pcival	_mis_data._mis_pci._mis_pcival
+#define	mis_int		_mis_data._mis_int
+
+typedef struct memtest_inject {
+	int mi_nstmts;
+	uint32_t mi_pad;
+	memtest_inj_stmt_t mi_stmts[1];
+} memtest_inject_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MEMTEST_H */
diff --git a/usr/src/uts/intel/sys/x86_archext.h b/usr/src/uts/intel/sys/x86_archext.h
index 4b93663dbd..2f52d6ee4b 100644
--- a/usr/src/uts/intel/sys/x86_archext.h
+++ b/usr/src/uts/intel/sys/x86_archext.h
@@ -262,54 +262,7 @@ extern "C" {
 #define	MSR_PRP4_LBSTK_TO_14	0x6ce
 #define	MSR_PRP4_LBSTK_TO_15	0x6cf
 
-#define	REG_MCG_CAP		0x179
-#define	REG_MCG_STATUS		0x17a
-#define	REG_MCG_CTL		0x17b
-
-#define	REG_MC0_CTL		0x400
-#define	REG_MC0_STATUS		0x401
-#define	REG_MC0_ADDR		0x402
-#define	REG_MC0_MISC		0x403
-#define	REG_MC1_CTL		0x404
-#define	REG_MC1_STATUS		0x405
-#define	REG_MC1_ADDR		0x406
-#define	REG_MC1_MISC		0x407
-#define	REG_MC2_CTL		0x408
-#define	REG_MC2_STATUS		0x409
-#define	REG_MC2_ADDR		0x40a
-#define	REG_MC2_MISC		0x40b
-#define	REG_MC4_CTL		0x40c
-#define	REG_MC4_STATUS		0x40d
-#define	REG_MC4_ADDR		0x40e
-#define	REG_MC4_MISC		0x40f
-#define	REG_MC3_CTL		0x410
-#define	REG_MC3_STATUS		0x411
-#define	REG_MC3_ADDR		0x412
-#define	REG_MC3_MISC		0x413
-
-#define	P6_MCG_CAP_COUNT	5
-#define	MCG_CAP_COUNT_MASK	0xff
-#define	MCG_CAP_CTL_P		0x100
-
-#define	MCG_STATUS_RIPV		0x01
-#define	MCG_STATUS_EIPV		0x02
-#define	MCG_STATUS_MCIP		0x04
-
-#define	MCG_CTL_VALUE		0xffffffff
-
 #define	MCI_CTL_VALUE		0xffffffff
-#define	MCI_STATUS_ERRCODE	0xffff
-#define	MCI_STATUS_MSERRCODE	0xffff0000
-#define	MCI_STATUS_PCC		((long long)0x200000000000000)
-#define	MCI_STATUS_ADDRV	((long long)0x400000000000000)
-#define	MCI_STATUS_MISCV	((long long)0x800000000000000)
-#define	MCI_STATUS_EN		((long long)0x1000000000000000)
-#define	MCI_STATUS_UC		((long long)0x2000000000000000)
-#define	MCI_STATUS_O		((long long)0x4000000000000000)
-#define	MCI_STATUS_VAL		((long long)0x8000000000000000)
-
-#define	MSERRCODE_SHFT		16
-
 
 #define	MTRRTYPE_MASK		0xff
 
@@ -437,6 +390,8 @@ typedef	struct	mtrrvar {
 #define	X86_VENDOR_TM		9	/* GenuineTMx86 */
 #define	X86_VENDOR_NSC		10	/* Geode by NSC */
 
+#define	X86_VENDOR_STRLEN	13	/* vendor string max len + \0 */
+
 #if !defined(_ASM)
 
 #if defined(_KERNEL) || defined(_KMEMUSER)
@@ -471,8 +426,6 @@ struct cpuid_regs {
 extern uint64_t rdmsr(uint_t);
 extern void wrmsr(uint_t, const uint64_t);
 extern void invalidate_cache(void);
-struct regs;
-extern int mca_exception(struct regs *);
 extern ulong_t getcr4(void);
 extern void setcr4(ulong_t);
 extern void mtrr_sync(void);