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| author | Jerry Jelinek <jerry.jelinek@joyent.com> | 2019-01-11 13:16:51 +0000 |
|---|---|---|
| committer | Jerry Jelinek <jerry.jelinek@joyent.com> | 2019-01-11 13:16:51 +0000 |
| commit | 882fee1ee6c160a1c4cb56a4874b0039ff1410c0 (patch) | |
| tree | add61009c9f1e3c5849055eedf68b1ad9a8b7d97 /usr/src/uts/intel/sys | |
| parent | b7e394a4a3da3fcdb717314a5ebcd7a5f14def92 (diff) | |
| parent | 247b7da039fd88350c50e3d7fef15bdab6bef215 (diff) | |
| download | illumos-joyent-882fee1ee6c160a1c4cb56a4874b0039ff1410c0.tar.gz | |
[illumos-gate merge]
commit 247b7da039fd88350c50e3d7fef15bdab6bef215
10205 Mounting zfs filesystems on startup shows incorrect data
commit b928ac841f6012f92d5aedbd7dfacf443921fee3
10182 dd: print scaled stats
commit c65ebfc7045424bd04a6c7719a27b0ad3399ad54
8886 mdns: update to mDNSResponder-878.1.1
commit 35786f6866ae52207d0f1a25fe7ca5f652f32ce0
9823 Deadlock in ACPI Method Evaluation
9824 Update ACPI to joyent/20180629
commit bc36eafdde0c7048471866fc7cea7b93852592db
9822 want iasl
commit b75e7d76519aa3dc2e72aa357a039a6b65372a1c
9821 want a way to run vendor-specific commands via libscsi
commit 2a613b5974ae49c8b068a3998ff554f8c6f0f593
9747 Implement CPU autoreplace based on Intel PPIN
commit ca13eaa51ee900abba73dfb6624e492f7e48863e
9979 Support python3 for in-gate tools
Conflicts:
usr/src/uts/intel/sys/x86_archext.h
usr/src/uts/i86pc/os/cmi_hw.c
usr/src/tools/onbld/Checks/DbLookups.py
usr/src/lib/fm/topo/modules/i86pc/chip/chip_subr.c
Diffstat (limited to 'usr/src/uts/intel/sys')
| -rw-r--r-- | usr/src/uts/intel/sys/x86_archext.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/usr/src/uts/intel/sys/x86_archext.h b/usr/src/uts/intel/sys/x86_archext.h index 13f488457c..ca629c0a79 100644 --- a/usr/src/uts/intel/sys/x86_archext.h +++ b/usr/src/uts/intel/sys/x86_archext.h @@ -907,6 +907,19 @@ extern "C" { #define INTC_MODEL_DENVERTON 0x5f #define INTC_MODEL_GEMINI_LAKE 0x7a + +/* + * Definitions for Intel processor models. Note, these model values can overlap + * in a given family. Processor models are added here on an as needed basis. The + * Xeon extension here is to refer to what has been called the EP/EX lines or + * E5/E7, generally multi-socket capable processors. + */ +#define INTC_MODEL_IVYBRIDGE_XEON 0x3E +#define INTC_MODEL_HASWELL_XEON 0x3F +#define INTC_MODEL_BROADWELL_XEON 0x4F +#define INTC_MODEL_BROADWELL_XEON_D 0x56 +#define INTC_MODEL_SKYLAKE_XEON 0x55 + /* * xgetbv/xsetbv support * See section 13.3 in vol. 1 of the Intel devlopers manual. |