OpenSolaris Launch

author: stevel@tonic-gate <none@none> 2005-06-14 00:00:00 -0700
committer: stevel@tonic-gate <none@none> 2005-06-14 00:00:00 -0700
commit: 7c478bd95313f5f23a4c958a745db2134aa03244 (patch)
tree: c871e58545497667cbb4b0a4f2daf204743e1fe7 /usr/src/uts/sun4u/sys
download: illumos-joyent-7c478bd95313f5f23a4c958a745db2134aa03244.tar.gz
159 files changed, 41508 insertions, 0 deletions
diff --git a/usr/src/uts/sun4u/sys/Makefile b/usr/src/uts/sun4u/sys/Makefile
new file mode 100644
index 0000000000..1748dd9a89
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/Makefile
@@ -0,0 +1,209 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License, Version 1.0 only
+# (the "License").  You may not use this file except in compliance
+# with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+#
+#ident	"%Z%%M%	%I%	%E% SMI"
+#
+# Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+# Use is subject to license terms.
+#
+# uts/sun4u/sys/Makefile
+#
+UTSBASE	= ../..
+
+#
+# include global definitions
+#
+include ../Makefile.sun4u
+
+#
+# Override defaults.
+#
+FILEMODE	 = 644
+GROUP = bin
+
+SUN4_HDRS=			\
+	async.h			\
+	clock.h			\
+	cmp.h			\
+	cpc_ultra.h		\
+	cpu_sgnblk_defs.h 	\
+	ddi_subrdefs.h		\
+	dvma.h			\
+	eeprom.h		\
+	fcode.h			\
+	idprom.h		\
+	intr.h			\
+	intreg.h		\
+	ivintr.h		\
+	memlist_plat.h  	\
+	memnode.h		\
+	nexusdebug.h		\
+	nexusintr_impl.h	\
+	prom_debug.h		\
+	scb.h			\
+	sun4asi.h		\
+	tod.h			\
+	trapstat.h		\
+	vis.h			\
+	vm_machparam.h		\
+	x_call.h		\
+	xc_impl.h		\
+	zsmach.h
+
+HDRS=	\
+	cheetahregs.h		\
+	cpr_impl.h		\
+	ecc_kstat.h		\
+	envctrl.h		\
+	envctrl_gen.h		\
+	envctrl_ue250.h		\
+	envctrl_ue450.h		\
+	errclassify.h		\
+	gpio_87317.h		\
+	fc_plat.h		\
+	iocache.h		\
+	iommu.h			\
+	machasi.h		\
+	machclock.h		\
+	machcpuvar.h		\
+	machparam.h		\
+	machsystm.h		\
+	machthread.h		\
+	memtestio.h		\
+	memtestio_ch.h		\
+	memtestio_chp.h		\
+	memtestio_ja.h		\
+	memtestio_jg.h		\
+	memtestio_sf.h		\
+	memtestio_sr.h		\
+	mmu.h			\
+	prom_plat.h		\
+	pte.h			\
+	sbd_ioctl.h		\
+	spitregs.h		\
+	starfire.h		\
+	sysioerr.h		\
+	sysiosbus.h		\
+	todmostek.h		\
+	traptrace.h		\
+	us_drv.h		\
+	wci_cmmu.h		\
+	wci_common.h		\
+	wci_offsets.h		\
+	wci_regs.h		\
+	wrsm.h			\
+	wrsm_config.h		\
+	wrsm_plugin.h		\
+	wrsm_plat.h		\
+	wrsm_common.h		\
+	wrsm_types.h
+
+DMFEHDRS =	dmfe.h dmfe_impl.h miiregs.h
+
+ROOTDMFEDIR = $(ROOT)/usr/include/sys
+
+ROOTDMFEHDRS = $(DMFEHDRS:%=$(ROOTDMFEDIR)/%)
+
+I2CHDRS =	clients/max1617.h misc/i2c_svc.h clients/i2c_client.h	\
+		clients/scmi2c.h clients/hpc3130.h clients/lm75.h	\
+		clients/pcf8591.h clients/ssc050.h
+I2C_DIRS=	clients misc
+USR_PSM_ISYS_I2C_ROOT=	$(USR_PSM_ISYS_DIR)/i2c
+USR_PSM_ISYS_I2C_DIRS=	$(USR_PSM_ISYS_I2C_ROOT) \
+			$(I2C_DIRS:%=$(USR_PSM_ISYS_I2C_ROOT)/%)
+
+ROOTI2CHDRS=		$(I2CHDRS:%=$(USR_PSM_ISYS_I2C_ROOT)/%)
+
+
+MONHDRS=
+#MONHDRS=	eeprom.h    idprom.h    keyboard.h  password.h
+
+USR_PSM_MON_DIR=	$(USR_PSM_ISYS_DIR)/mon
+
+ROOTHDRS=		$(HDRS:%=$(USR_PSM_ISYS_DIR)/%)
+SUN4_ROOTHDRS=		$(SUN4_HDRS:%=$(USR_PSM_ISYS_DIR)/%)
+
+ROOTMONHDRS=		$(MONHDRS:%=$(USR_PSM_MON_DIR)/%)
+
+ROOTDIR=		$(ROOT)/usr/share/src
+ROOTDIRS=		$(ROOTDIR)/uts $(ROOTDIR)/uts/$(PLATFORM)
+
+ROOTLINK=		$(ROOTDIR)/uts/$(PLATFORM)/sys
+LINKDEST=		../../../../platform/$(PLATFORM)/include/sys
+
+CHECKHDRS=		$(HDRS:%.h=%.check) \
+			$(MONHDRS:%.h=mon/%.check) \
+			$(SUN4_HDRS:%.h=%.cmncheck)
+
+.KEEP_STATE:
+
+.PARALLEL: $(CHECKHDRS) $(ROOTHDRS) $(ROOTMONHDRS) $(SUN4_ROOTHDRS)
+
+install_h: $(ROOTDIRS) $(USR_PSM_ISYS_I2C_DIRS) $(ROOTDMFEDIR) .WAIT \
+		$(ROOTHDRS) $(ROOTI2CHDRS) \
+		$(ROOTMONHDRS) $(ROOTDMFEHDRS) \
+		$(SUN4_ROOTHDRS) $(ROOTLINK)
+
+check:	$(CHECKHDRS)
+
+#
+# install rules
+#
+$(USR_PSM_MON_DIR):	$(USR_PSM_ISYS_DIR)
+	$(INS.dir.root.bin)
+
+$(USR_PSM_ISYS_I2C_DIRS):
+	$(INS.dir.root.bin)
+
+$(USR_PSM_ISYS_DIR)/%:	../../sfmmu/sys/% $(USR_PSM_ISYS_DIR)
+	$(INS.file)
+
+$(USR_PSM_ISYS_DIR)/%:	../../sun4/sys/% $(USR_PSM_ISYS_DIR)
+	$(INS.file)
+
+$(USR_PSM_MON_DIR)/%:	mon/% $(USR_PSM_MON_DIR)
+	$(INS.file)
+
+$(ROOTDMFEDIR)/%: % $(ROOTDMFEDIR)
+	$(INS.file)
+
+$(ROOTDMFEDIR):
+	$(INS.dir.root.bin)
+
+$(ROOTDIRS):
+	$(INS.dir.root.bin)
+
+# -r because this used to be a directory and is now a link.
+$(ROOTLINK):	$(ROOTDIRS)
+	-$(RM) -r $@; $(SYMLINK) $(LINKDEST) $@ $(CHOWNLINK) $(CHGRPLINK)
+
+mon/%.check:	mon/%.h
+	$(DOT_H_CHECK)
+
+%.check:	../../sfmmu/sys/%.h
+	$(DOT_H_CHECK)
+%.cmncheck:	../../sun4/sys/%.h
+	$(DOT_H_CHECK)
+
+FRC:
+
+include ../../Makefile.targ
diff --git a/usr/src/uts/sun4u/sys/cheetahasm.h b/usr/src/uts/sun4u/sys/cheetahasm.h
new file mode 100644
index 0000000000..b1d919eb73
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/cheetahasm.h
@@ -0,0 +1,1255 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_CHEETAHASM_H
+#define	_CHEETAHASM_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifdef _ASM
+/* BEGIN CSTYLED */
+
+#define	ASM_LD(reg, symbol)						\
+	sethi	%hi(symbol), reg;					\
+	ld	[reg + %lo(symbol)], reg;				\
+
+#define	ASM_LDX(reg, symbol)						\
+	sethi	%hi(symbol), reg;					\
+	ldx	[reg + %lo(symbol)], reg;				\
+
+#define	ASM_JMP(reg, symbol)						\
+	sethi	%hi(symbol), reg;					\
+	jmp	reg + %lo(symbol);					\
+	nop
+
+/*
+ * Macro for getting to offset from 'cpu_private' ptr.  The 'cpu_private'
+ * ptr is in the machcpu structure.
+ *  off_reg:  Register offset from 'cpu_private' ptr.
+ *  scr1:    Scratch, ptr is returned in this register.
+ *  scr2:    Scratch
+ *  label:   Label to branch to if cpu_private ptr is null/zero.
+ */
+#define	GET_CPU_PRIVATE_PTR(off_reg, scr1, scr2, label)			\
+	CPU_ADDR(scr1, scr2);						\
+	ldn	[scr1 + CPU_PRIVATE], scr1;				\
+	cmp	scr1, 0;						\
+	be	label;							\
+	  nop;								\
+	add	scr1, off_reg, scr1
+
+/*
+ * Macro version of get_dcache_dtag.  We use this macro in the
+ * CPU logout code. Since the Dcache is virtually indexed, only
+ * bits [12:5] of the AFAR can be used so we need to search through
+ * 8 indexes (4 ways + bit 13) in order to find the tag we want.
+ *   afar:  input AFAR, not modified.
+ *   datap: input ptr to ch_dc_data_t, at end pts to end of ch_dc_data_t.
+ *   scr1:  scratch.
+ *   scr2:  scratch, will hold tag to look for.
+ *   scr3:  used for Dcache index, loops through 4 ways.
+ */
+#define	GET_DCACHE_DTAG(afar, datap, scr1, scr2, scr3)			\
+	set	CH_DCACHE_IDX_MASK, scr3;				\
+	and	afar, scr3, scr3;					\
+	srlx	afar, CH_DCTAG_PA_SHIFT, scr2;				\
+	b	1f;							\
+	  or	scr2, CH_DCTAG_VALID_BIT, scr2; /* tag we want */	\
+	.align	128;							\
+1:									\
+	ldxa	[scr3]ASI_DC_TAG, scr1;		/* read tag */		\
+	cmp	scr1, scr2;						\
+	bne	4f;				/* not found? */	\
+	  nop;								\
+	stxa	scr3, [datap + CH_DC_IDX]%asi;	/* store index */	\
+	stxa	scr1, [datap + CH_DC_TAG]%asi;	/* store tag */		\
+	membar	#Sync;			/* Cheetah PRM 10.6.3 */	\
+	ldxa	[scr3]ASI_DC_UTAG, scr1;	/* read utag */		\
+	membar	#Sync;			/* Cheetah PRM 10.6.3 */	\
+	stxa	scr1, [datap + CH_DC_UTAG]%asi;				\
+	ldxa	[scr3]ASI_DC_SNP_TAG, scr1;	/* read snoop tag */	\
+	stxa	scr1, [datap + CH_DC_SNTAG]%asi;			\
+	add	datap, CH_DC_DATA, datap;				\
+	clr	scr2;							\
+2:									\
+	membar	#Sync;			/* Cheetah PRM 10.6.1 */	\
+	ldxa	[scr3 + scr2]ASI_DC_DATA, scr1;	/* read data */		\
+	membar	#Sync;			/* Cheetah PRM 10.6.1 */	\
+	stxa	scr1, [datap]%asi;					\
+	add	datap, 8, datap;					\
+	cmp	scr2, CH_DC_DATA_REG_SIZE - 8;				\
+	blt	2b;							\
+	  add	scr2, 8, scr2;						\
+									\
+	GET_CPU_IMPL(scr2);	/* Parity bits are elsewhere for */	\
+	cmp	scr2, PANTHER_IMPL;	/* panther processors. */	\
+	bne,a	5f;			/* Done if not panther. */	\
+	  add	datap, 8, datap; /* Skip to the end of the struct. */	\
+	clr	scr2;							\
+	add	datap, 7, datap; /* offset of the last parity byte */	\
+	mov	1, scr1;						\
+	sll	scr1, PN_DC_DATA_PARITY_BIT_SHIFT, scr1;		\
+	or	scr3, scr1, scr3; /* add DC_data_parity bit to index */	\
+3:									\
+	membar	#Sync;			/* Cheetah PRM 10.6.1 */	\
+	ldxa	[scr3 + scr2]ASI_DC_DATA, scr1;	/* read parity bits */	\
+	membar	#Sync;			/* Cheetah PRM 10.6.1 */	\
+	stba	scr1, [datap]%asi;					\
+	dec	datap;							\
+	cmp	scr2, CH_DC_DATA_REG_SIZE - 8;				\
+	blt	3b;							\
+	  add	scr2, 8, scr2;						\
+	b	5f;							\
+	  add	datap, 5, datap; /* set pointer to end of our struct */	\
+4:									\
+	set	CH_DCACHE_IDX_INCR, scr1;	/* incr. idx (scr3) */	\
+	add	scr3, scr1, scr3;					\
+	set	CH_DCACHE_IDX_LIMIT, scr1;	/* done? */		\
+	cmp	scr3, scr1;						\
+	blt	1b;							\
+	  nop;								\
+	add	datap, CH_DC_DATA_SIZE, datap;				\
+5:
+
+/*
+ * Macro version of get_icache_dtag.  We use this macro in the CPU
+ * logout code. If the Icache is on, we don't want to capture the data.
+ *   afar:  input AFAR, not modified.
+ *   datap: input ptr to ch_ic_data_t, at end pts to end of ch_ic_data_t.
+ *   scr1:  scratch.
+ *   scr2:  scratch, will hold tag to look for.
+ *   scr3:  used for Icache index, loops through 4 ways.
+ * Note: For Panther, the Icache is virtually indexed and increases in
+ * size to 64KB (instead of 32KB) with a line size of 64 bytes (instead
+ * of 32). This means the IC_addr index bits[14:7] for Panther now
+ * correspond to VA bits[13:6]. But since it is virtually indexed, we
+ * still mask out only bits[12:5] from the AFAR (we have to manually
+ * check bit 13). In order to make this code work for all processors,
+ * we end up checking twice as many indexes (8 instead of 4) as required
+ * for non-Panther CPUs and saving off twice as much data (16 instructions
+ * instead of just 8).
+ */
+#define	GET_ICACHE_DTAG(afar, datap, scr1, scr2, scr3)			\
+	ldxa	[%g0]ASI_DCU, scr1;					\
+	btst	DCU_IC, scr1;		/* is Icache enabled? */	\
+	bne,a	6f;			/* yes, don't capture */	\
+	  add	datap, CH_IC_DATA_SIZE, datap;	/* anul if no branch */	\
+	GET_CPU_IMPL(scr2);	/* Panther only uses VA[13:6] */	\
+	cmp	scr2, PANTHER_IMPL;	/* and we also want to mask */	\
+	be	1f;			/* out bit 13 since the */	\
+	  nop;				/* Panther I$ is VIPT. */	\
+	set	CH_ICACHE_IDX_MASK, scr3;				\
+	b	2f;							\
+	  nop;								\
+1:									\
+	set	PN_ICACHE_VA_IDX_MASK, scr3;				\
+2:									\
+	and	afar, scr3, scr3;					\
+	sllx	scr3, CH_ICACHE_IDX_SHIFT, scr3;			\
+	srlx	afar, CH_ICPATAG_SHIFT, scr2;	/* pa tag we want */	\
+	andn	scr2, CH_ICPATAG_LBITS, scr2;	/* mask off lower */	\
+	b	3f;							\
+	  nop;								\
+	.align	128;							\
+3:									\
+	ldxa	[scr3]ASI_IC_TAG, scr1;		/* read pa tag */	\
+	andn	scr1, CH_ICPATAG_LBITS, scr1;	/* mask off lower */	\
+	cmp	scr1, scr2;						\
+	bne	5f;				/* not found? */	\
+	  nop;								\
+	stxa	scr3, [datap + CH_IC_IDX]%asi;	/* store index */	\
+	stxa	scr1, [datap + CH_IC_PATAG]%asi; /* store pa tag */	\
+	add	scr3, CH_ICTAG_UTAG, scr3;	/* read utag */		\
+	ldxa	[scr3]ASI_IC_TAG, scr1;					\
+	add	scr3, (CH_ICTAG_UPPER - CH_ICTAG_UTAG), scr3;		\
+	stxa	scr1, [datap + CH_IC_UTAG]%asi;				\
+	ldxa	[scr3]ASI_IC_TAG, scr1;		/* read upper tag */	\
+	add	scr3, (CH_ICTAG_LOWER - CH_ICTAG_UPPER), scr3;		\
+	stxa	scr1, [datap + CH_IC_UPPER]%asi;			\
+	ldxa	[scr3]ASI_IC_TAG, scr1;		/* read lower tag */	\
+	andn	scr3, CH_ICTAG_TMASK, scr3;				\
+	stxa	scr1, [datap + CH_IC_LOWER]%asi;			\
+	ldxa	[scr3]ASI_IC_SNP_TAG, scr1;	/* read snoop tag */	\
+	stxa	scr1, [datap + CH_IC_SNTAG]%asi;			\
+	add	datap, CH_IC_DATA, datap;				\
+	clr	scr2;							\
+4:									\
+	ldxa	[scr3 + scr2]ASI_IC_DATA, scr1;	/* read ins. data */	\
+	stxa	scr1, [datap]%asi;					\
+	add	datap, 8, datap;					\
+	cmp	scr2, PN_IC_DATA_REG_SIZE - 8;				\
+	blt	4b;							\
+	  add	scr2, 8, scr2;						\
+	b	6f;							\
+	  nop;								\
+5:									\
+	set	CH_ICACHE_IDX_INCR, scr1;	/* incr. idx (scr3) */	\
+	add	scr3, scr1, scr3;					\
+	set	PN_ICACHE_IDX_LIMIT, scr1;	/* done? */		\
+	cmp	scr3, scr1;						\
+	blt	3b;							\
+	  nop;								\
+	add	datap, CH_IC_DATA_SIZE, datap;				\
+6:
+
+#if defined(JALAPENO) || defined(SERRANO)
+/*
+ * Macro version of get_ecache_dtag.  We use this macro in the
+ * CPU logout code.
+ *   afar:	input AFAR, not modified
+ *   datap:	Ptr to ch_ec_data_t, at end pts just past ch_ec_data_t.
+ *   ec_way:	Constant value (way number) 
+ *   scr1:      Scratch
+ *   scr2:	Scratch.
+ *   scr3:	Scratch.
+ */
+#define	GET_ECACHE_DTAG(afar, datap, ec_way, scr1, scr2, scr3)		\
+	mov	ec_way, scr1;						\
+	and	scr1, JP_ECACHE_NWAY - 1, scr1;	/* mask E$ way bits */	\
+	sllx	scr1, JP_EC_TAG_DATA_WAY_SHIFT, scr1;			\
+	set	((JP_ECACHE_MAX_SIZE / JP_ECACHE_NWAY) - 1), scr2;	\
+	and	afar, scr2, scr3;		/* get set offset */	\
+	andn	scr3, (JP_ECACHE_MAX_LSIZE - 1), scr3; /* VA<5:0>=0 */	\
+	or	scr3, scr1, scr3;		/* or WAY bits */	\
+	b	1f;							\
+	  stxa	scr3, [datap + CH_EC_IDX]%asi;	/* store E$ index */	\
+	.align	64;							\
+1:									\
+	JP_EC_DIAG_ACCESS_MEMBAR;					\
+	ldxa    [scr3]ASI_EC_DIAG, scr1;	/* get E$ tag */	\
+	JP_EC_DIAG_ACCESS_MEMBAR;					\
+	stxa	scr1, [datap + CH_EC_TAG]%asi;				\
+	add	datap, CH_EC_DATA, datap;				\
+2:									\
+	ldxa	[scr3]ASI_EC_R, %g0;		/* ld E$ stging regs */	\
+	clr	scr1;							\
+3:						/* loop thru 5 regs */	\
+	ldxa	[scr1]ASI_EC_DATA, scr2;				\
+	stxa	scr2, [datap]%asi;					\
+	add	datap, 8, datap;					\
+	cmp	scr1, CH_ECACHE_STGREG_TOTALSIZE - 8;			\
+	bne	3b;							\
+	   add	scr1, 8, scr1;						\
+	btst	CH_ECACHE_STGREG_SIZE, scr3;	/* done? */		\
+	beq	2b;							\
+	   add	scr3, CH_ECACHE_STGREG_SIZE, scr3
+
+#define	GET_ECACHE_DTAGS(afar, datap, scr1, scr2, scr3)			\
+	GET_ECACHE_DTAG(afar, datap, 0, scr1, scr2, scr3);		\
+	GET_ECACHE_DTAG(afar, datap, 1, scr1, scr2, scr3);		\
+	GET_ECACHE_DTAG(afar, datap, 2, scr1, scr2, scr3);		\
+	GET_ECACHE_DTAG(afar, datap, 3, scr1, scr2, scr3);		\
+	add	datap, (CHD_EC_DATA_SETS-4)*CH_EC_DATA_SIZE, datap;	\
+	add	datap, CH_EC_DATA_SIZE * PN_L2_NWAYS, datap;		\
+
+/*
+ * Jalapeno does not have cores so these macros are null.
+ */
+#define	PARK_SIBLING_CORE(dcucr_reg, scr1, scr2)
+#define	UNPARK_SIBLING_CORE(dcucr_reg, scr1, scr2)
+
+#if defined(JALAPENO)
+/*
+ * Jalapeno gets primary AFSR and AFAR.  All bits in the AFSR except
+ * the fatal error bits are cleared.
+ *	datap:		pointer to cpu logout structure.
+ *	afar:		returned primary AFAR value.
+ *	scr1:		scratch
+ *	scr2:		scratch
+ */
+#define	GET_AFSR_AFAR(datap, afar, scr1, scr2)				\
+	ldxa	[%g0]ASI_AFAR, afar;					\
+	stxa	afar, [datap + (CH_CLO_DATA + CH_CHD_AFAR)]%asi;	\
+	ldxa	[%g0]ASI_AFSR, scr2;					\
+	stxa	scr2, [datap + (CH_CLO_DATA + CH_CHD_AFSR)]%asi;	\
+	sethi	%hh(C_AFSR_FATAL_ERRS), scr1;				\
+	sllx	scr1, 32, scr1;						\
+	bclr	scr1, scr2;	/* Clear fatal error bits here, so */	\
+	stxa	scr2, [%g0]ASI_AFSR; /* they're left as is in AFSR */	\
+	membar	#Sync
+
+/*
+ * Jalapeno has no shadow AFAR, null operation.
+ */
+#define	GET_SHADOW_DATA(afar, datap, scr1, scr2, scr3)
+
+#elif defined(SERRANO)
+/*
+ * Serrano gets primary AFSR and AFAR.  All bits in the AFSR except
+ * the fatal error bits are cleared.  For Serrano, we also save the
+ * AFAR2 register. 
+ *	datap:	pointer to cpu logout structure.
+ *	afar:	returned primary AFAR value.
+ *	scr1:	scratch
+ *	scr2:	scratch
+ */
+#define GET_AFSR_AFAR(datap, afar, scr1, scr2)				\
+	set	ASI_MCU_AFAR2_VA, scr1;					\
+	ldxa	[scr1]ASI_MCU_CTRL, afar;				\
+	stxa	afar, [datap + (CH_CLO_DATA + CH_CHD_AFAR2)]%asi;	\
+	ldxa	[%g0]ASI_AFAR, afar;					\
+	stxa	afar, [datap + (CH_CLO_DATA + CH_CHD_AFAR)]%asi;	\
+	ldxa	[%g0]ASI_AFSR, scr2;					\
+	stxa	scr2, [datap + (CH_CLO_DATA + CH_CHD_AFSR)]%asi;	\
+	sethi	%hh(C_AFSR_FATAL_ERRS), scr1;				\
+	sllx	scr1, 32, scr1;						\
+	bclr	scr1, scr2;	/* Clear fatal error bits here, so */	\
+	stxa	scr2, [%g0]ASI_AFSR; /* they're left as is in AFSR */ 	\
+	membar	#Sync
+
+/*
+ * Serrano needs to capture E$, D$ and I$ lines associated with afar2.
+ *      afar:   scratch, holds afar2.
+ *      datap:  pointer to cpu logout structure
+ *      scr1:   scratch
+ *      scr2:   scratch
+ *      scr3:   scratch
+ */
+#define	GET_SHADOW_DATA(afar, datap, scr1, scr2, scr3)		\
+	ldxa	[datap + (CH_CLO_DATA + CH_CHD_AFAR2)]%asi, afar;	\
+	add	datap, CH_CLO_SDW_DATA + CH_CHD_EC_DATA, datap;		\
+	GET_ECACHE_DTAGS(afar, datap, scr1, scr2, scr3);		\
+	GET_DCACHE_DTAG(afar, datap, scr1, scr2, scr3);			\
+	GET_ICACHE_DTAG(afar, datap, scr1, scr2, scr3);			\
+	sub	datap, CH_CPU_LOGOUT_SIZE, datap
+#endif /* SERRANO */
+
+#elif defined(CHEETAH_PLUS)
+/*
+ * Macro version of get_ecache_dtag.  We use this macro in the
+ * CPU logout code.
+ *   afar:	input AFAR, not modified.
+ *   datap:	Ptr to ch_ec_data_t, at end pts just past ch_ec_data_t.
+ *   pn_way:	ecache way for panther (value = 0-3). For non-panther
+ *		cpus, this macro will be called with pn_way = 0.
+ *   scr1:	Scratch.
+ *   scr2:	Scratch.
+ *   scr3:	Scratch.
+ */
+#define	GET_ECACHE_DTAG(afar, datap, pn_way, scr1, scr2, scr3)		\
+	mov	afar, scr3;						\
+	andn	scr3, (CH_ECACHE_SUBBLK_SIZE - 1), scr3; /* VA<5:0>=0 */\
+	set	(CH_ECACHE_8M_SIZE - 1), scr2;				\
+	and	scr3, scr2, scr3;		/* VA<63:23>=0 */	\
+	mov	pn_way, scr1;	/* panther L3$ is 4-way so we ...    */	\
+	sllx	scr1, PN_L3_WAY_SHIFT, scr1;	/* need to mask...   */	\
+	or	scr3, scr1, scr3;	/* in the way bits <24:23>.  */	\
+	b	1f;							\
+	   stxa	scr3, [datap + CH_EC_IDX]%asi;	/* store E$ index */	\
+	.align	64;							\
+1:									\
+	ldxa    [scr3]ASI_EC_DIAG, scr1;	/* get E$ tag */	\
+	stxa     scr1, [datap + CH_EC_TAG]%asi;				\
+	set	CHP_ECACHE_IDX_TAG_ECC, scr1;				\
+	or	scr3, scr1, scr1;					\
+	ldxa    [scr1]ASI_EC_DIAG, scr1;	/* get E$ tag ECC */	\
+	stxa	scr1, [datap + CH_EC_TAG_ECC]%asi;			\
+	add	datap, CH_EC_DATA, datap;				\
+2:									\
+	ldxa	[scr3]ASI_EC_R, %g0;		/* ld E$ stging regs */	\
+	clr	scr1;							\
+3:						/* loop thru 5 regs */	\
+	ldxa	[scr1]ASI_EC_DATA, scr2;				\
+	stxa	scr2, [datap]%asi;					\
+	add	datap, 8, datap;					\
+	cmp	scr1, CH_ECACHE_STGREG_TOTALSIZE - 8;			\
+	bne	3b;							\
+	   add	scr1, 8, scr1;						\
+	btst	CH_ECACHE_STGREG_SIZE, scr3;	/* done? */		\
+	beq	2b;							\
+	   add	scr3, CH_ECACHE_STGREG_SIZE, scr3
+
+/*
+ * If this is a panther, we need to make sure the sibling core is
+ * parked so that we avoid any race conditions during diagnostic
+ * accesses to the shared L2 and L3 caches.
+ * dcucr_reg:	This register will be used to keep track of whether
+ *		or not we need to unpark the core later.
+ *		It just so happens that we also use this same register
+ *		to keep track of our saved DCUCR value so we only touch
+ *		bit 4 of the register (which is a "reserved" bit in the
+ *		DCUCR) for keeping track of core parking.
+ * scr1:	Scratch register.
+ * scr2:	Scratch register.
+ */
+#define	PARK_SIBLING_CORE(dcucr_reg, scr1, scr2)			\
+	GET_CPU_IMPL(scr1);						\
+	cmp	scr1, PANTHER_IMPL;	/* only park for panthers */	\
+	bne,a	%xcc, 2f;						\
+	  andn	dcucr_reg, PN_PARKED_OTHER_CORE, dcucr_reg;		\
+	set	ASI_CORE_RUNNING_STATUS, scr1;	/* check other core */	\
+	ldxa	[scr1]ASI_CMP_SHARED, scr2;	/* is it running?   */	\
+	cmp	scr2, PN_BOTH_CORES_RUNNING;				\
+	bne,a	%xcc, 2f;	/* if not running, we are done */	\
+	  andn	dcucr_reg, PN_PARKED_OTHER_CORE, dcucr_reg;		\
+	or	dcucr_reg, PN_PARKED_OTHER_CORE, dcucr_reg;		\
+	set	ASI_CORE_ID, scr1;					\
+	ldxa	[scr1]ASI_CMP_PER_CORE, scr2;				\
+	and	scr2, COREID_MASK, scr2;				\
+	or	%g0, 1, scr1;		/* find out which core... */	\
+	sll	scr1, scr2, scr2;	/* ... we need to park... */	\
+1:									\
+	set	ASI_CORE_RUNNING_RW, scr1;				\
+	stxa	scr2, [scr1]ASI_CMP_SHARED;	/* ... and park it. */	\
+	membar	#Sync;				/* spin until the... */	\
+	ldxa	[scr1]ASI_CMP_SHARED, scr1;	/* ... the other...  */	\
+	cmp	scr1, scr2;	/* ...core is parked according to... */	\
+	bne,a	%xcc, 1b;	/* ...the core running status reg.  */	\
+	  nop;								\
+2:
+
+/*
+ * The core running this code will unpark its sibling core if the
+ * sibling core had been parked by the current core earlier in this
+ * trap handler.
+ * dcucr_reg:	This register is used to keep track of whether or not
+ *		we need to unpark our sibling core.
+ *		It just so happens that we also use this same register
+ *		to keep track of our saved DCUCR value so we only touch
+ *		bit 4 of the register (which is a "reserved" bit in the
+ *		DCUCR) for keeping track of core parking.
+ * scr1:	Scratch register.
+ * scr2:	Scratch register.
+ */
+#define	UNPARK_SIBLING_CORE(dcucr_reg, scr1, scr2)			\
+	btst	PN_PARKED_OTHER_CORE, dcucr_reg;			\
+	bz,pt	%xcc, 1f;	/* if nothing to unpark, we are done */	\
+	  andn	dcucr_reg, PN_PARKED_OTHER_CORE, dcucr_reg;		\
+	set	ASI_CORE_RUNNING_RW, scr1;				\
+	set	PN_BOTH_CORES_RUNNING, scr2;	/* we want both...   */	\
+	stxa	scr2, [scr1]ASI_CMP_SHARED;	/* ...cores running. */	\
+	membar	#Sync;							\
+1:
+
+/*
+ * Cheetah+ and Jaguar get both primary and secondary AFSR/AFAR.  All bits
+ * in the primary AFSR are cleared except the fatal error bits.  For Panther,
+ * we also have to read and clear the AFSR_EXT, again leaving the fatal
+ * error bits alone.
+ *	datap:		pointer to cpu logout structure.
+ *	afar:		returned primary AFAR value.
+ *	scr1:		scratch
+ *	scr2:		scratch
+ */
+#define	GET_AFSR_AFAR(datap, afar, scr1, scr2)				\
+	set	ASI_SHADOW_REG_VA, scr1;				\
+	ldxa	[scr1]ASI_AFAR, scr2;					\
+	stxa	scr2, [datap + (CH_CLO_SDW_DATA + CH_CHD_AFAR)]%asi;	\
+	ldxa	[scr1]ASI_AFSR, scr2;					\
+	stxa	scr2, [datap + (CH_CLO_SDW_DATA + CH_CHD_AFSR)]%asi;	\
+	ldxa	[%g0]ASI_AFAR, afar;					\
+	stxa	afar, [datap + (CH_CLO_DATA + CH_CHD_AFAR)]%asi;	\
+	ldxa	[%g0]ASI_AFSR, scr2;					\
+	stxa	scr2, [datap + (CH_CLO_DATA + CH_CHD_AFSR)]%asi;	\
+	sethi	%hh(C_AFSR_FATAL_ERRS), scr1;				\
+	sllx	scr1, 32, scr1;						\
+	bclr	scr1, scr2;	/* Clear fatal error bits here, so */ 	\
+	stxa	scr2, [%g0]ASI_AFSR; /* they're left as is in AFSR */	\
+	membar	#Sync;							\
+	GET_CPU_IMPL(scr1);						\
+	cmp	scr1, PANTHER_IMPL;					\
+	bne	%xcc, 1f;						\
+	   nop;								\
+	set	ASI_SHADOW_AFSR_EXT_VA, scr1;	/* shadow AFSR_EXT */	\
+	ldxa	[scr1]ASI_AFSR, scr2;					\
+	stxa	scr2, [datap + (CH_CLO_SDW_DATA + CH_CHD_AFSR_EXT)]%asi; \
+	set	ASI_AFSR_EXT_VA, scr1;		/* primary AFSR_EXT */	\
+	ldxa	[scr1]ASI_AFSR, scr2;					\
+	stxa	scr2, [datap + (CH_CLO_DATA + CH_CHD_AFSR_EXT)]%asi;	\
+	set	C_AFSR_EXT_FATAL_ERRS, scr1;				\
+	bclr	scr1, scr2;	/* Clear fatal error bits here, */	\
+	set	ASI_AFSR_EXT_VA, scr1;	/* so they're left */		\
+	stxa	scr2, [scr1]ASI_AFSR;	/* as is in AFSR_EXT */		\
+	membar	#Sync;							\
+1:
+
+/*
+ * This macro is used in the CPU logout code to capture diagnostic
+ * information from the L2 cache on panther processors.
+ *   afar:	input AFAR, not modified.
+ *   datap:	Ptr to pn_l2_data_t, at end pts just past pn_l2_data_t.
+ *   scr1:	Scratch.
+ *   scr2:	Scratch.
+ *   scr3:	Scratch.
+ */
+#define	GET_PN_L2_CACHE_DTAGS(afar, datap, scr1, scr2, scr3)		\
+	mov	afar, scr3;						\
+	set	PN_L2_INDEX_MASK, scr1;					\
+	and	scr3, scr1, scr3;					\
+	b	1f;	/* code to read tags and data should be ...  */	\
+	   nop;		/* ...on the same cache line if possible.    */	\
+	.align	128;	/* update this line if you add lines below. */	\
+1:									\
+	stxa	scr3, [datap + CH_EC_IDX]%asi;	/* store L2$ index  */	\
+	ldxa	[scr3]ASI_L2_TAG, scr1;		/* read the L2$ tag */	\
+	stxa	scr1, [datap + CH_EC_TAG]%asi;				\
+	add	datap, CH_EC_DATA, datap;				\
+	clr	scr1;							\
+2:									\
+	ldxa	[scr3 + scr1]ASI_L2_DATA, scr2;	/* loop through     */	\
+	stxa	scr2, [datap]%asi;		/* <511:256> of L2  */	\
+	add	datap, 8, datap;		/* data and record  */	\
+	cmp	scr1, (PN_L2_LINESIZE / 2) - 8;	/* it in the cpu    */	\
+	bne	2b;				/* logout struct.   */	\
+	  add	scr1, 8, scr1;						\
+	set	PN_L2_DATA_ECC_SEL, scr2;	/* ECC_sel bit.     */	\
+	ldxa	[scr3 + scr2]ASI_L2_DATA, scr2;	/* Read and record  */	\
+	stxa	scr2, [datap]%asi;		/* ecc of <511:256> */	\
+	add	datap, 8, datap;					\
+3:									\
+	ldxa	[scr3 + scr1]ASI_L2_DATA, scr2;	/* loop through     */	\
+	stxa	scr2, [datap]%asi;		/* <255:0> of L2    */	\
+	add	datap, 8, datap;		/* data and record  */	\
+	cmp	scr1, PN_L2_LINESIZE - 8;	/* it in the cpu    */	\
+	bne	3b;				/* logout struct.   */	\
+	  add	scr1, 8, scr1;						\
+	set	PN_L2_DATA_ECC_SEL, scr2;	/* ECC_sel bit.     */	\
+	add	scr2, PN_L2_ECC_LO_REG, scr2;				\
+	ldxa	[scr3 + scr2]ASI_L2_DATA, scr2;	/* Read and record  */	\
+	stxa	scr2, [datap]%asi;		/* ecc of <255:0>.  */	\
+	add	datap, 8, datap;		/* Advance pointer  */	\
+	set	PN_L2_SET_SIZE, scr2;					\
+	set	PN_L2_MAX_SET, scr1;					\
+	cmp	scr1, scr3;	/* more ways to try for this line? */	\
+	bg,a	%xcc, 1b;	/* if so, start over with next way */	\
+	  add	scr3, scr2, scr3
+
+/*
+ * Cheetah+ assumes E$ is 2-way and grabs both E$ lines associated with afar.
+ *	afar:	AFAR from access.
+ *	datap:	pointer to cpu logout structure.
+ *	scr1:	scratch
+ *	scr2:	scratch
+ *	scr3:	scratch
+ */
+#define	GET_ECACHE_DTAGS(afar, datap, scr1, scr2, scr3)			\
+	GET_CPU_IMPL(scr1);						\
+	cmp	scr1, PANTHER_IMPL;					\
+	bne	%xcc, 4f;						\
+	  nop;								\
+	GET_ECACHE_DTAG(afar, datap, 0, scr1, scr2, scr3);		\
+	GET_ECACHE_DTAG(afar, datap, 1, scr1, scr2, scr3);		\
+	GET_ECACHE_DTAG(afar, datap, 2, scr1, scr2, scr3);		\
+	GET_ECACHE_DTAG(afar, datap, 3, scr1, scr2, scr3);		\
+	add	datap, (CHD_EC_DATA_SETS-4)*CH_EC_DATA_SIZE, datap;	\
+	GET_PN_L2_CACHE_DTAGS(afar, datap, scr1, scr2, scr3);		\
+	b	5f;							\
+	  nop;								\
+4:									\
+	GET_ECACHE_DTAG(afar, datap, 0, scr1, scr2, scr3);		\
+	GET_ECACHE_WAY_BIT(scr1, scr2);					\
+	xor	afar, scr1, afar;					\
+	GET_ECACHE_DTAG(afar, datap, 0, scr1, scr2, scr3);		\
+	GET_ECACHE_WAY_BIT(scr1, scr2);		/* restore AFAR */	\
+	xor	afar, scr1, afar;					\
+	add	datap, (CHD_EC_DATA_SETS-2)*CH_EC_DATA_SIZE, datap;	\
+	add	datap, CH_EC_DATA_SIZE * PN_L2_NWAYS, datap;		\
+5:
+
+/*
+ * Cheetah+ needs to capture E$, D$ and I$ lines associated with
+ * shadow afar.
+ *	afar:	scratch, holds shadow afar.
+ *	datap:	pointer to cpu logout structure
+ *	scr1:	scratch
+ *	scr2:	scratch
+ *	scr3:	scratch
+ */
+#define	GET_SHADOW_DATA(afar, datap, scr1, scr2, scr3)		\
+	ldxa	[datap + (CH_CLO_SDW_DATA + CH_CHD_AFAR)]%asi, afar;	\
+	add	datap, CH_CLO_SDW_DATA + CH_CHD_EC_DATA, datap;	\
+	GET_ECACHE_DTAGS(afar, datap, scr1, scr2, scr3);		\
+	GET_DCACHE_DTAG(afar, datap, scr1, scr2, scr3);			\
+	GET_ICACHE_DTAG(afar, datap, scr1, scr2, scr3);			\
+	sub	datap, CH_CPU_LOGOUT_SIZE, datap
+
+/*
+ * Compute the "Way" bit for 2-way Ecache for Cheetah+.
+ */
+#define	GET_ECACHE_WAY_BIT(scr1, scr2)					\
+	CPU_INDEX(scr1, scr2);						\
+	mulx	scr1, CPU_NODE_SIZE, scr1;				\
+	add	scr1, ECACHE_SIZE, scr1;				\
+	set	cpunodes, scr2;						\
+	ld	[scr1 + scr2], scr1;					\
+	srlx	scr1, 1, scr1
+
+#else /* CHEETAH_PLUS */
+/*
+ * Macro version of get_ecache_dtag.  We use this macro in the
+ * CPU logout code.
+ *   afar:	input AFAR, not modified.
+ *   datap:	Ptr to ch_ec_data_t, at end pts just past ch_ec_data_t.
+ *   scr1:      Scratch.
+ *   scr2:	Scratch.
+ *   scr3:	Scratch.
+ */
+#define	GET_ECACHE_DTAG(afar, datap, scr1, scr2, scr3)			\
+	mov	afar, scr3;						\
+	andn	scr3, (CH_ECACHE_SUBBLK_SIZE - 1), scr3; /* VA<5:0>=0 */\
+	set	(CH_ECACHE_8M_SIZE - 1), scr2;				\
+	and	scr3, scr2, scr3;		/* VA<63:23>=0 */	\
+	b	1f;							\
+	   stxa	scr3, [datap + CH_EC_IDX]%asi;	/* store E$ index */	\
+	.align	64;							\
+1:									\
+	ldxa    [scr3]ASI_EC_DIAG, scr1;	/* get E$ tag */	\
+	stxa	scr1, [datap + CH_EC_TAG]%asi;				\
+	add	datap, CH_EC_DATA, datap;				\
+2:									\
+	ldxa	[scr3]ASI_EC_R, %g0;		/* ld E$ stging regs */	\
+	clr	scr1;							\
+3:						/* loop thru 5 regs */	\
+	ldxa	[scr1]ASI_EC_DATA, scr2;				\
+	stxa	scr2, [datap]%asi;					\
+	add	datap, 8, datap;					\
+	cmp	scr1, CH_ECACHE_STGREG_TOTALSIZE - 8;			\
+	bne	3b;							\
+	   add	scr1, 8, scr1;						\
+	btst	CH_ECACHE_STGREG_SIZE, scr3;	/* done? */		\
+	beq	2b;							\
+	   add	scr3, CH_ECACHE_STGREG_SIZE, scr3
+
+/*
+ * Cheetah does not have cores so these macros are null.
+ */
+#define	PARK_SIBLING_CORE(dcucr_reg, scr1, scr2)
+#define	UNPARK_SIBLING_CORE(dcucr_reg, scr1, scr2)
+
+/*
+ * Cheetah gets primary AFSR and AFAR and clears the AFSR, except for the
+ * fatal error bits.
+ *	datap:		pointer to cpu logout structure.
+ *	afar:		returned primary AFAR value.
+ *	scr1:		scratch
+ *	scr2:		scratch
+ */
+#define	GET_AFSR_AFAR(datap, afar, scr1, scr2)	\
+	ldxa	[%g0]ASI_AFAR, afar;					\
+	stxa	afar, [datap + (CH_CLO_DATA + CH_CHD_AFAR)]%asi;	\
+	ldxa	[%g0]ASI_AFSR, scr2;					\
+	stxa	scr2, [datap + (CH_CLO_DATA + CH_CHD_AFSR)]%asi;	\
+	sethi	%hh(C_AFSR_FATAL_ERRS), scr1;				\
+	sllx	scr1, 32, scr1;						\
+	bclr	scr1, scr2;	/* Clear fatal error bits here, so */	\
+	stxa	scr2, [%g0]ASI_AFSR; /* they're left as is in AFSR */	\
+	membar	#Sync
+
+/*
+ * Cheetah E$ is direct-mapped, so we grab line data and skip second line.
+ *	afar:	AFAR from access.
+ *	datap:	pointer to cpu logout structure.
+ *	scr1:	scratch
+ *	scr2:	scratch
+ *	scr3:	scratch
+ */
+#define	GET_ECACHE_DTAGS(afar, datap, scr1, scr2, scr3)			\
+	GET_ECACHE_DTAG(afar, datap, scr1, scr2, scr3);			\
+	add	datap, (CHD_EC_DATA_SETS-1)*CH_EC_DATA_SIZE, datap;	\
+	add	datap, CH_EC_DATA_SIZE * PN_L2_NWAYS, datap;		\
+
+/*
+ * Cheetah has no shadow AFAR, null operation.
+ */
+#define	GET_SHADOW_DATA(afar, datap, scr1, scr2, scr3)
+
+#endif	/* CHEETAH_PLUS */
+
+/*
+ * Cheetah/(Cheetah+ Jaguar Panther)/Jalapeno Macro for capturing CPU
+ * logout data at TL>0. r_val is a register that returns the "failure count"
+ * to the caller, and may be used as a scratch register until the end of
+ * the macro.  afar is used to return the primary AFAR value to the caller
+ * and it too can be used as a scratch register until the end. r_or_s is
+ * a reg or symbol that has the offset within the "cpu_private" data area
+ * to deposit the logout data.  t_flags is a register that has the
+ * trap-type/trap-level/CEEN info. This t_flags register may be used after
+ * the GET_AFSR_AFAR macro.
+ *
+ * The CPU logout operation will fail (r_val > 0) if the logout
+ * structure in question is already being used. Otherwise, the CPU
+ * logout operation will succeed (r_val = 0). For failures, r_val
+ * returns the busy count (# of times we tried using this CPU logout
+ * structure when it was busy.)
+ *
+ *   Register usage:
+ *	%asi:   Must be set to either ASI_MEM if the address in datap
+ *		is a physical address or to ASI_N if the address in
+ *		datap is a virtual address.
+ *	r_val:	This register is the return value which tells the
+ *		caller whether or not the LOGOUT operation was successful.
+ *		For failures, r_val returns the fail count (i.e. number of
+ *		times we have tried to use this logout structure when it was
+ *		already being used.
+ *	afar:	output: contains AFAR on exit
+ *	t_flags: input trap type info, may be used as scratch after stored
+ *		to cpu log out structure.
+ *	datap:	Points to log out data area.
+ *	scr1:	Scratch
+ *	scr2:	Scratch (may be r_val)
+ *	scr3:   Scratch (may be t_flags)
+ */
+#define	DO_TL1_CPU_LOGOUT(r_val, afar, t_flags, datap, scr1, scr2, scr3) \
+	setx	LOGOUT_INVALID, scr2, scr1;				\
+	ldxa	[datap + (CH_CLO_DATA + CH_CHD_AFAR)]%asi, scr2;	\
+	cmp	scr2, scr1;						\
+	bne	8f;							\
+	  nop;								\
+	stxa	t_flags, [datap + CH_CLO_FLAGS]%asi;			\
+	GET_AFSR_AFAR(datap, afar, scr1, scr2);				\
+	add	datap, CH_CLO_DATA + CH_CHD_EC_DATA, datap;		\
+	GET_ECACHE_DTAGS(afar, datap, scr1, scr2, scr3);		\
+	GET_DCACHE_DTAG(afar, datap, scr1, scr2, scr3);			\
+	GET_ICACHE_DTAG(afar, datap, scr1, scr2, scr3);			\
+	sub	datap, CH_CLO_DATA + CH_DIAG_DATA_SIZE, datap;		\
+	GET_SHADOW_DATA(afar, datap, scr1, scr2, scr3);			\
+	ldxa	[datap + (CH_CLO_DATA + CH_CHD_AFAR)]%asi, afar;	\
+	set	0, r_val;	/* return value for success */		\
+	ba	9f;							\
+	  nop;								\
+8:									\
+	ldxa	[%g0]ASI_AFAR, afar;					\
+	ldxa	[datap + CH_CLO_NEST_CNT]%asi, r_val;			\
+	inc	r_val;		/* return value for failure */		\
+	stxa	r_val, [datap + CH_CLO_NEST_CNT]%asi;			\
+	membar	#Sync;							\
+9:
+
+/*
+ * Cheetah/(Cheetah+ Jaguar Panther)/Jalapeno Macro for capturing CPU
+ * logout data.  Uses DO_TL1_CPU_LOGOUT macro defined above, and sets
+ * up the expected data pointer in the scr1 register and sets the %asi
+ * register to ASI_N for kernel virtual addresses instead of ASI_MEM as
+ * is used at TL>0.
+ *
+ * The CPU logout operation will fail (r_val > 0) if the logout
+ * structure in question is already being used. Otherwise, the CPU
+ * logout operation will succeed (r_val = 0). For failures, r_val
+ * returns the busy count (# of times we tried using this CPU logout
+ * structure when it was busy.)
+ *
+ *   Register usage:
+ *	r_val:	This register is the return value which tells the
+ *		caller whether or not the LOGOUT operation was successful.
+ *		For failures, r_val returns the fail count (i.e. number of
+ *		times we have tried to use this logout structure when it was
+ *		already being used.
+ *	afar:	returns AFAR, used internally as afar value.
+ *		output: if the cpu_private struct has not been initialized,
+ *		        then we return the t_flags value listed below.
+ *	r_or_s:	input offset, either register or constant (symbol).  It's
+ *		OK for r_or_s to be a register as long as it's not scr1 or
+ *		scr3.
+ *	t_flags: input trap type info, may be used as scratch after stored
+ *		to cpu log out structure.
+ *	scr1:	Scratch, points to log out data area.
+ *	scr2:	Scratch (may be r_or_s)
+ *	scr3:	Scratch (may be r_val)
+ *	scr4:   Scratch (may be t_flags)
+ */
+#define	DO_CPU_LOGOUT(r_val, afar, r_or_s, t_flags, scr1, scr2, scr3, scr4) \
+	GET_CPU_PRIVATE_PTR(r_or_s, scr1, scr3, 7f); /* can't use scr2/4 */ \
+	wr	%g0, ASI_N, %asi;					\
+	DO_TL1_CPU_LOGOUT(r_val, afar, t_flags, scr1, scr2, scr3, scr4)	\
+	ba	6f;							\
+	  nop;								\
+7:									\
+	mov	t_flags, afar;		/* depends on afar = %g2  */	\
+	set	0, r_val;		/* success in this case.  */	\
+6:
+
+/*
+ * The P$ is flushed as a side effect of writing to the Primary
+ * or Secondary Context Register. After writing to a context
+ * register, every line of the P$ in the Valid state is invalidated,
+ * regardless of which context it belongs to.
+ * This routine simply touches the Primary context register by
+ * reading the current value and writing it back. The Primary
+ * context is not changed.
+ */
+#define	PCACHE_FLUSHALL(tmp1, tmp2, tmp3)				\
+	sethi	%hi(FLUSH_ADDR), tmp1					;\
+	set	MMU_PCONTEXT, tmp2					;\
+	ldxa	[tmp2]ASI_DMMU, tmp3					;\
+	stxa	tmp3, [tmp2]ASI_DMMU					;\
+	flush	tmp1	/* See Cheetah PRM 8.10.2 */
+
+/*
+ * Macro that flushes the entire Dcache.
+ *
+ * arg1 = dcache size
+ * arg2 = dcache linesize
+ */
+#define	CH_DCACHE_FLUSHALL(arg1, arg2, tmp1)				\
+	sub	arg1, arg2, tmp1;					\
+1:									\
+	stxa	%g0, [tmp1]ASI_DC_TAG;					\
+	membar	#Sync;							\
+	cmp	%g0, tmp1;						\
+	bne,pt	%icc, 1b;						\
+	  sub	tmp1, arg2, tmp1;
+
+/*
+ * Macro that flushes the entire Icache.
+ *
+ * Note that we cannot access ASI 0x67 (ASI_IC_TAG) with the Icache on,
+ * because accesses to ASI 0x67 interfere with Icache coherency.  We
+ * must make sure the Icache is off, then turn it back on after the entire
+ * cache has been invalidated.  If the Icache is originally off, we'll just
+ * clear the tags but not turn the Icache on.
+ *
+ * arg1 = icache size
+ * arg2 = icache linesize
+ */
+#define	CH_ICACHE_FLUSHALL(arg1, arg2, tmp1, tmp2)			\
+	ldxa	[%g0]ASI_DCU, tmp2;					\
+	andn	tmp2, DCU_IC, tmp1;					\
+	stxa	tmp1, [%g0]ASI_DCU;					\
+	flush	%g0;	/* flush required after changing the IC bit */	\
+	sllx	arg2, 1, arg2;		/* arg2 = linesize * 2 */	\
+	sllx	arg1, 1, arg1;		/* arg1 = size * 2 */		\
+	sub	arg1, arg2, arg1;					\
+	or	arg1, CH_ICTAG_LOWER, arg1;	/* "write" tag */	\
+1:									\
+	stxa	%g0, [arg1]ASI_IC_TAG;					\
+	membar	#Sync;				/* Cheetah PRM 8.9.3 */	\
+	cmp	arg1, CH_ICTAG_LOWER;					\
+	bne,pt	%icc, 1b;						\
+	  sub	arg1, arg2, arg1;					\
+	stxa	tmp2, [%g0]ASI_DCU;					\
+	flush	%g0;	/* flush required after changing the IC bit */
+
+
+#if defined(JALAPENO) || defined(SERRANO)
+
+/*
+ * ASI access to the L2 tag or L2 flush can hang the cpu when interacting 
+ * with combinations of L2 snoops, victims and stores.
+ *
+ * A possible workaround is to surround each L2 ASI access with membars
+ * and make sure that the code is hitting in the Icache.  This requires
+ * aligning code sequence at E$ boundary and forcing I$ fetch by
+ * jumping to selected offsets so that we don't take any I$ misses
+ * during ASI access to the L2 tag or L2 flush.  This also requires
+ * making sure that we don't take any interrupts or traps (such as
+ * fast ECC trap, I$/D$ tag parity error) which can result in eviction
+ * of this code sequence from I$, thus causing a miss.
+ *
+ * Because of the complexity/risk, we have decided to do a partial fix
+ * of adding membar around each ASI access to the L2 tag or L2 flush.
+ */
+
+#define	JP_EC_DIAG_ACCESS_MEMBAR	\
+	membar	#Sync
+
+/*
+ * Jalapeno version of macro that flushes the entire Ecache.
+ *
+ * Uses Jalapeno displacement flush feature of ASI_EC_DIAG.
+ *
+ * arg1 = ecache size
+ * arg2 = ecache linesize - not modified; can be an immediate constant.
+ */
+#define	ECACHE_FLUSHALL(arg1, arg2, tmp1, tmp2)	\
+	CPU_INDEX(tmp1, tmp2);						\
+	set	JP_ECACHE_IDX_DISP_FLUSH, tmp2;				\
+	sllx	tmp1, JP_ECFLUSH_PORTID_SHIFT, tmp1;			\
+	or	tmp1, tmp2, tmp1;					\
+	srlx	arg1, JP_EC_TO_SET_SIZE_SHIFT, tmp2;			\
+1:									\
+	subcc	tmp2, arg2, tmp2;					\
+	JP_EC_DIAG_ACCESS_MEMBAR;					\
+	ldxa	[tmp1 + tmp2]ASI_EC_DIAG, %g0;				\
+	JP_EC_DIAG_ACCESS_MEMBAR;					\
+	bg,pt	%xcc, 1b;						\
+	  nop;								\
+	mov	1, tmp2;						\
+	sllx	tmp2, JP_ECFLUSH_EC_WAY_SHIFT, tmp2;			\
+	add	tmp1, tmp2, tmp1;					\
+	mov	(JP_ECACHE_NWAY-1), tmp2;				\
+	sllx	tmp2, JP_ECFLUSH_EC_WAY_SHIFT, tmp2;			\
+	andcc	tmp1, tmp2, tmp2;					\
+	bnz,pt	%xcc, 1b;						\
+	  srlx	arg1, JP_EC_TO_SET_SIZE_SHIFT, tmp2
+
+#else	/* JALAPENO || SERRANO */
+
+/*
+ * Cheetah version of macro that flushes the entire Ecache.
+ *
+ *  Need to displacement flush 2x ecache size from Ecache flush area.
+ *
+ * arg1 = ecache size
+ * arg2 = ecache linesize
+ * arg3 = ecache flush address - for cheetah only
+ */
+#define	CH_ECACHE_FLUSHALL(arg1, arg2, arg3)				\
+	sllx	arg1, 1, arg1;						\
+1:									\
+	subcc	arg1, arg2, arg1;					\
+	bg,pt	%xcc, 1b;						\
+	  ldxa	[arg1 + arg3]ASI_MEM, %g0;
+
+/*
+ * Cheetah+ version of macro that flushes the entire Ecache.
+ *
+ * Uses the displacement flush feature.
+ *
+ * arg1 = ecache size
+ * arg2 = ecache linesize
+ * impl = CPU implementation as returned from GET_CPU_IMPL()
+ *        The value in this register is destroyed during execution
+ *        of the macro.
+ */
+#if defined(CHEETAH_PLUS)
+#define	CHP_ECACHE_FLUSHALL(arg1, arg2, impl)				\
+	cmp	impl, PANTHER_IMPL;					\
+	bne	%xcc, 1f;						\
+	  nop;								\
+	set	PN_L3_IDX_DISP_FLUSH, impl;				\
+	b	2f;							\
+	  nop;								\
+1:									\
+	set	CHP_ECACHE_IDX_DISP_FLUSH, impl;			\
+2:									\
+	subcc	arg1, arg2, arg1;					\
+	bg,pt	%xcc, 2b;						\
+	  ldxa	[arg1 + impl]ASI_EC_DIAG, %g0;
+#else	/* CHEETAH_PLUS */
+#define	CHP_ECACHE_FLUSHALL(arg1, arg2, impl)
+#endif	/* CHEETAH_PLUS */
+
+/*
+ * Macro that flushes the entire Ecache.
+ *
+ * arg1 = ecache size
+ * arg2 = ecache linesize
+ * arg3 = ecache flush address - for cheetah only
+ */
+#define	ECACHE_FLUSHALL(arg1, arg2, arg3, tmp1)				\
+	GET_CPU_IMPL(tmp1);						\
+	cmp	tmp1, CHEETAH_IMPL;					\
+	bne	%xcc, 2f;						\
+	  nop;								\
+	CH_ECACHE_FLUSHALL(arg1, arg2, arg3);				\
+	ba	3f;							\
+	  nop;								\
+2:									\
+	CHP_ECACHE_FLUSHALL(arg1, arg2, tmp1);				\
+3:
+
+#endif	/* JALAPENO || SERRANO */
+
+/*
+ * Macro that flushes the Panther L2 cache.
+ */
+#if defined(CHEETAH_PLUS)
+#define	PN_L2_FLUSHALL(scr1, scr2, scr3)				\
+	GET_CPU_IMPL(scr3);						\
+	cmp	scr3, PANTHER_IMPL;					\
+	bne	%xcc, 2f;						\
+	  nop;								\
+	set	PN_L2_SIZE, scr1;					\
+	set	PN_L2_LINESIZE, scr2;					\
+	set	PN_L2_IDX_DISP_FLUSH, scr3;				\
+1:									\
+	subcc	scr1, scr2, scr1;					\
+	bg,pt	%xcc, 1b;						\
+	  ldxa	[scr1 + scr3]ASI_L2_TAG, %g0;				\
+2:
+#else	/* CHEETAH_PLUS */
+#define	PN_L2_FLUSHALL(scr1, scr2, scr3)
+#endif	/* CHEETAH_PLUS */
+
+/*
+ * Given a VA and page size (page size as encoded in ASI_MMU_TAG_ACCESS_EXT),
+ * this macro returns the TLB index for that mapping based on a 512 entry
+ * (2-way set associative) TLB. Aaside from the 16 entry fully associative
+ * TLBs, all TLBs in Panther are 512 entry, 2-way set associative.
+ *  
+ * To find the index, we shift the VA right by 13 + (3 * pg_sz) and then
+ * mask out all but the lower 8 bits because:
+ *
+ *    ASI_[D|I]MMU_TAG_ACCESS_EXT.PgSz = 0 for   8K
+ *    ASI_[D|I]MMU_TAG_ACCESS_EXT.PgSz = 1 for  64K
+ *    ASI_[D|I]MMU_TAG_ACCESS_EXT.PgSz = 2 for 512K
+ *    ASI_[D|I]MMU_TAG_ACCESS_EXT.PgSz = 3 for   4M
+ *    ASI_[D|I]MMU_TAG_ACCESS_EXT.PgSz = 4 for  32M
+ *    ASI_[D|I]MMU_TAG_ACCESS_EXT.PgSz = 5 for 256M
+ *
+ * and
+ *
+ *    array index for   8K pages = VA[20:13]
+ *    array index for  64K pages = VA[23:16]
+ *    array index for 512K pages = VA[26:19]
+ *    array index for   4M pages = VA[29:22]
+ *    array index for  32M pages = VA[32:25]
+ *    array index for 256M pages = VA[35:28]
+ *
+ * Inputs:
+ *
+ *    va	- Register.
+ *		  Input: Virtual address in which we are interested.
+ *		  Output: TLB index value.
+ *    pg_sz	- Register. Page Size of the TLB in question as encoded
+ *		  in the ASI_[D|I]MMU_TAG_ACCESS_EXT register.
+ */
+#if defined(CHEETAH_PLUS)
+#define	PN_GET_TLB_INDEX(va, pg_sz)					\
+	srlx	va, 13, va;	/* first shift the 13 bits and then */	\
+	srlx	va, pg_sz, va;	/* shift by pg_sz three times. */	\
+	srlx	va, pg_sz, va;						\
+	srlx	va, pg_sz, va;						\
+	and	va, 0xff, va;	/* mask out all but the lower 8 bits */
+#endif	/* CHEETAH_PLUS */
+
+/*
+ * The following macros are for error traps at TL>0.
+ * The issue with error traps at TL>0 is that there are no safely
+ * available global registers.  So we use the trick of generating a
+ * software trap, then using the %tpc, %tnpc and %tstate registers to
+ * temporarily save the values of %g1 and %g2.
+ */
+
+/*
+ * Macro to generate 8-instruction trap table entry for TL>0 trap handlers.
+ * Does the following steps:
+ *	1. membar #Sync - required for USIII family errors.
+ *	2. Specified software trap.
+ * NB: Must be 8 instructions or less to fit in trap table and code must
+ *     be relocatable.
+ */
+#define	CH_ERR_TL1_TRAPENTRY(trapno)		\
+	membar	#Sync;				\
+	ta	trapno;				\
+	nop; nop; nop; nop; nop; nop
+
+/*
+ * Macro to generate 8-instruction trap table entry for TL>0 software trap.
+ * We save the values of %g1 and %g2 in %tpc, %tnpc and %tstate (since
+ * the low-order two bits of %tpc/%tnpc are reserved and read as zero,
+ * we need to put the low-order two bits of %g1 and %g2 in %tstate).
+ * Note that %tstate has a reserved hole from bits 3-7, so we put the
+ * low-order two bits of %g1 in bits 0-1 and the low-order two bits of
+ * %g2 in bits 10-11 (insuring bits 8-9 are zero for use by the D$/I$
+ * state bits).  Note that we must do a jmp instruction, since this
+ * is moved into the trap table entry.
+ * NB: Must be 8 instructions or less to fit in trap table and code must
+ *     be relocatable.
+ */
+#define	CH_ERR_TL1_SWTRAPENTRY(label)		\
+	wrpr	%g1, %tpc;			\
+	and	%g1, 3, %g1;			\
+	wrpr	%g2, %tnpc;			\
+	sllx	%g2, CH_ERR_G2_TO_TSTATE_SHFT, %g2; \
+	or	%g1, %g2, %g2;			\
+	sethi	%hi(label), %g1;		\
+	jmp	%g1+%lo(label);			\
+	  wrpr	%g2, %tstate
+
+/*
+ * Macro to get ptr to ch_err_tl1_data.
+ * reg1 will either point to a physaddr with ASI_MEM in %asi OR it
+ * will point to a kernel nucleus virtual address with ASI_N in %asi.
+ * This allows us to:
+ *   1. Avoid getting MMU misses.  We may have gotten the original
+ *	Fast ECC error in an MMU handler and if we get an MMU trap
+ *	in the TL>0 handlers, we'll scribble on the MMU regs.
+ *   2. Allows us to use the same code in the TL>0 handlers whether
+ *	we're accessing kernel nucleus virtual addresses or physical
+ *	addresses.
+ * pseudo-code:
+ *	reg1 <- ch_err_tl1_paddrs[CPUID];
+ *	if (reg1 == NULL) {
+ *		reg1 <- &ch_err_tl1_data
+ *		%asi <- ASI_N
+ *	} else {
+ *		reg1 <- reg1 + offset +
+ *		    sizeof (ch_err_tl1_data) * (%tl - 3)
+ *		%asi <- ASI_MEM
+ *	}
+ */
+#define	GET_CH_ERR_TL1_PTR(reg1, reg2, offset)	\
+	CPU_INDEX(reg1, reg2);			\
+	sllx	reg1, 3, reg1;			\
+	set	ch_err_tl1_paddrs, reg2;	\
+	ldx	[reg1+reg2], reg1;		\
+	brnz	reg1, 1f;			\
+	add	reg1, offset, reg1;		\
+	set	ch_err_tl1_data, reg1;		\
+	ba	2f;				\
+	wr	%g0, ASI_N, %asi;		\
+1:	rdpr	%tl, reg2;			\
+	sub	reg2, 3, reg2;			\
+	mulx	reg2, CH_ERR_TL1_DATA_SIZE, reg2;	\
+	add	reg1, reg2, reg1;		\
+	wr	%g0, ASI_MEM, %asi;		\
+2:
+
+/*
+ * Macro to generate entry code for TL>0 error handlers.
+ * At the end of this macro, %g1 will point to the ch_err_tl1_data
+ * structure and %g2 will have the original flags in the ch_err_tl1_data
+ * structure and %g5 will have the value of %tstate where the Fast ECC
+ * routines will save the state of the D$ in Bit2 CH_ERR_TSTATE_DC_ON.
+ * All %g registers except for %g1, %g2 and %g5 will be available after
+ * this macro.
+ * Does the following steps:
+ *   1. Compute physical address of per-cpu/per-tl save area using
+ *	only %g1+%g2 (which we've saved in %tpc, %tnpc, %tstate)
+ *	leaving address in %g1 and updating the %asi register.
+ *	If there is no data area available, we branch to label.
+ *   2. Save %g3-%g7 in save area.
+ *   3. Save %tpc->%g3, %tnpc->%g4, %tstate->%g5, which contain
+ *	original %g1+%g2 values (because we're going to change %tl).
+ *   4. set %tl <- %tl - 1.  We do this ASAP to make window of
+ *	running at %tl+1 as small as possible.
+ *   5. Reconstitute %g1+%g2 from %tpc (%g3), %tnpc (%g4),
+ *	%tstate (%g5) and save in save area, carefully preserving %g5
+ *	because it has the CH_ERR_TSTATE_DC_ON value.
+ *   6. Load existing ch_err_tl1_data flags in %g2
+ *   7. Compute the new flags
+ *   8. If %g2 is non-zero (the structure was busy), shift the new
+ *	flags by CH_ERR_ME_SHIFT and or them with the old flags.
+ *   9. Store the updated flags into ch_err_tl1_data flags.
+ *   10. If %g2 is non-zero, read the %tpc and store it in
+ *	ch_err_tl1_data.
+ */
+#define	CH_ERR_TL1_ENTER(flags)			\
+	GET_CH_ERR_TL1_PTR(%g1, %g2, CHPR_TL1_ERR_DATA);	\
+	stxa	%g3, [%g1 + CH_ERR_TL1_G3]%asi;	\
+	stxa	%g4, [%g1 + CH_ERR_TL1_G4]%asi;	\
+	stxa	%g5, [%g1 + CH_ERR_TL1_G5]%asi;	\
+	stxa	%g6, [%g1 + CH_ERR_TL1_G6]%asi;	\
+	stxa	%g7, [%g1 + CH_ERR_TL1_G7]%asi;	\
+	rdpr	%tpc, %g3;			\
+	rdpr	%tnpc, %g4;			\
+	rdpr	%tstate, %g5;			\
+	rdpr	%tl, %g6;			\
+	sub	%g6, 1, %g6;			\
+	wrpr	%g6, %tl;			\
+	and	%g5, 3, %g6;			\
+	andn	%g3, 3, %g3;			\
+	or	%g3, %g6, %g3;			\
+	stxa	%g3, [%g1 + CH_ERR_TL1_G1]%asi;	\
+	srlx	%g5, CH_ERR_G2_TO_TSTATE_SHFT, %g6;	\
+	and	%g6, 3, %g6;			\
+	andn	%g4, 3, %g4;			\
+	or	%g6, %g4, %g4;			\
+	stxa	%g4, [%g1 + CH_ERR_TL1_G2]%asi;	\
+	ldxa	[%g1 + CH_ERR_TL1_FLAGS]%asi, %g2;	\
+	set	flags | CH_ERR_TL, %g3;		\
+	brz	%g2, 9f;			\
+	sllx	%g3, CH_ERR_ME_SHIFT, %g4;	\
+	or	%g2, %g4, %g3;			\
+9:	stxa	%g3, [%g1 + CH_ERR_TL1_FLAGS]%asi;	\
+	brnz	%g2, 8f;			\
+	rdpr	%tpc, %g4;			\
+	stxa	%g4, [%g1 + CH_ERR_TL1_TPC]%asi;	\
+8:
+
+/*
+ * Turns off D$/I$ and saves the state of DCU_DC+DCU_IC in %tstate Bits 8+9
+ * (CH_ERR_TSTATE_DC_ON/CH_ERR_TSTATE_IC_ON).  This is invoked on Fast ECC
+ * at TL>0 handlers because the D$ may have corrupted data and we need to
+ * turn off the I$ to allow for diagnostic accesses.  We then invoke
+ * the normal entry macro and after it is done we save the values of
+ * the original D$/I$ state, which is in %g5 bits CH_ERR_TSTATE_DC_ON/
+ * CH_ERR_TSTATE_IC_ON in ch_err_tl1_tmp.
+ */
+#define	CH_ERR_TL1_FECC_ENTER			\
+	ldxa	[%g0]ASI_DCU, %g1;		\
+	andn	%g1, DCU_DC + DCU_IC, %g2;	\
+	stxa	%g2, [%g0]ASI_DCU;		\
+	flush	%g0;	/* DCU_IC need flush */	\
+	rdpr	%tstate, %g2;			\
+	and	%g1, DCU_DC + DCU_IC, %g1;	\
+	sllx	%g1, CH_ERR_DCU_TO_TSTATE_SHFT, %g1;	\
+	or	%g1, %g2, %g2;			\
+	wrpr	%g2, %tstate;			\
+	CH_ERR_TL1_ENTER(CH_ERR_FECC);		\
+	and	%g5, CH_ERR_TSTATE_DC_ON + CH_ERR_TSTATE_IC_ON, %g5;	\
+	stxa	%g5, [%g1 + CH_ERR_TL1_TMP]%asi
+
+/*
+ * Macro to generate exit code for TL>0 error handlers.
+ * We fall into this macro if we've successfully logged the error in
+ * the ch_err_tl1_data structure and want the PIL15 softint to pick
+ * it up and log it.
+ * Does the following steps:
+ *   1.	Set pending flag for this cpu in ch_err_tl1_pending.
+ *   2.	Write %set_softint with (1<<pil) to cause a pil level trap
+ *   3.	Restore registers from ch_err_tl1_data, which is pointed to
+ *	by %g1, last register to restore is %g1 since it's pointing
+ *	to the save area.
+ *   4. Execute retry
+ */
+#define	CH_ERR_TL1_EXIT				\
+	CPU_INDEX(%g2, %g3);			\
+	set	ch_err_tl1_pending, %g3;	\
+	set	-1, %g4;			\
+	stb	%g4, [%g2 + %g3];		\
+	mov	1, %g2;				\
+	sll	%g2, PIL_15, %g2;		\
+	wr	%g2, SET_SOFTINT;		\
+	ldxa	[%g1 + CH_ERR_TL1_G7]%asi, %g7;	\
+	ldxa	[%g1 + CH_ERR_TL1_G6]%asi, %g6;	\
+	ldxa	[%g1 + CH_ERR_TL1_G5]%asi, %g5;	\
+	ldxa	[%g1 + CH_ERR_TL1_G4]%asi, %g4;	\
+	ldxa	[%g1 + CH_ERR_TL1_G3]%asi, %g3;	\
+	ldxa	[%g1 + CH_ERR_TL1_G2]%asi, %g2;	\
+	ldxa	[%g1 + CH_ERR_TL1_G1]%asi, %g1;	\
+	retry
+
+/*
+ * Generates unrecoverable error label for TL>0 handlers.
+ * At label (Unrecoverable error routine)
+ *   1. Sets flags in ch_err_tl1_data and leaves in %g2 (first
+ *	argument to cpu_tl1_err_panic).
+ *   2.	Call cpu_tl1_err_panic via systrap at PIL 15
+ */
+#define	CH_ERR_TL1_PANIC_EXIT(label)		\
+label:	ldxa	[%g1 + CH_ERR_TL1_FLAGS]%asi, %g2;	\
+	or	%g2, CH_ERR_TL | CH_ERR_PANIC, %g2;	\
+	stxa	%g2, [%g1 + CH_ERR_TL1_FLAGS]%asi;	\
+	set	cpu_tl1_err_panic, %g1;		\
+	ba	sys_trap;			\
+	  mov	PIL_15, %g4
+
+
+
+/* END CSTYLED */
+#endif	/* _ASM */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _CHEETAHASM_H */
diff --git a/usr/src/uts/sun4u/sys/cheetahregs.h b/usr/src/uts/sun4u/sys/cheetahregs.h
new file mode 100644
index 0000000000..4405c2d45a
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/cheetahregs.h
@@ -0,0 +1,1617 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_CHEETAHREGS_H
+#define	_SYS_CHEETAHREGS_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/machasi.h>
+#ifdef _KERNEL
+#include <sys/fpras.h>
+#endif /* _KERNEL */
+
+/*
+ * This file is cpu dependent.
+ */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Definitions of UltraSparc III cpu implementations as specified
+ * in version register
+ */
+#define	CHEETAH_IMPL			0x14
+#define	IS_CHEETAH(impl)		((impl) == CHEETAH_IMPL)
+#define	CHEETAH_MAJOR_VERSION(rev)	(((rev) >> 4) & 0xf)
+#define	CHEETAH_MINOR_VERSION(rev)	((rev) & 0xf)
+
+/*
+ * Definitions of UltraSPARC III+ cpu implementation as specified
+ * in version register
+ */
+#define	CHEETAH_PLUS_IMPL		0x15
+#define	IS_CHEETAH_PLUS(impl)		((impl) == CHEETAH_PLUS_IMPL)
+#define	CHEETAH_PLUS_MAJOR_VERSION(rev)	CHEETAH_MAJOR_VERSION(rev)
+#define	CHEETAH_PLUS_MINOR_VERSION(rev)	CHEETAH_MINOR_VERSION(rev)
+
+/*
+ * Definitions of UltraSPARC IIIi cpu implementation as specified
+ * in version register.  Jalapeno major and minor rev's are in
+ * the same location and are the same size as Cheetah/Cheetah+.
+ */
+#define	JALAPENO_IMPL			0x16
+#define	IS_JALAPENO(impl)		((impl) == JALAPENO_IMPL)
+#define	JALAPENO_MAJOR_VERSION(rev)	CHEETAH_MAJOR_VERSION(rev)
+#define	JALAPENO_MINOR_VERSION(rev)	CHEETAH_MINOR_VERSION(rev)
+
+/*
+ * Definitions of UltraSPARC IV cpu implementation as specified
+ * in version register. Jaguar major and minor rev's are in
+ * the same location and are the same size as Cheetah/Cheetah+.
+ */
+#define	JAGUAR_IMPL			0x18
+#define	IS_JAGUAR(impl)			((impl) == JAGUAR_IMPL)
+#define	JAGUAR_MAJOR_VERSION(rev)	CHEETAH_MAJOR_VERSION(rev)
+#define	JAGUAR_MINOR_VERSION(rev)	CHEETAH_MINOR_VERSION(rev)
+
+/*
+ * Definitions of UltraSPARC IIIi+ cpu implementation as specified
+ * in version register.  Serrano major and minor rev's are in
+ * the same location and are the same size as Cheetah/Cheetah+.
+ */
+#define	SERRANO_IMPL			0x22
+#define	IS_SERRANO(impl)		((impl) == SERRANO_IMPL)
+#define	SERRANO_MAJOR_VERSION(rev)	CHEETAH_MAJOR_VERSION(rev)
+#define	SERRANO_MINOR_VERSION(rev)	CHEETAH_MINOR_VERSION(rev)
+
+/*
+ * Definitions of UltraSPARC IV+ cpu implementation as specified
+ * in version register. Panther major and minor rev's are in
+ * the same location and are the same size as Cheetah/Cheetah+.
+ */
+#define	PANTHER_IMPL			0x19
+#define	IS_PANTHER(impl)		((impl) == PANTHER_IMPL)
+#define	PANTHER_MAJOR_VERSION(rev)	CHEETAH_MAJOR_VERSION(rev)
+#define	PANTHER_MINOR_VERSION(rev)	CHEETAH_MINOR_VERSION(rev)
+
+#define	CPU_IMPL_IS_CMP(impl)		(IS_JAGUAR(impl) || IS_PANTHER(impl))
+
+/*
+ * Cheetah includes the process info in its mask to make things
+ * more difficult.  The process is the low bit of the major mask,
+ * so to convert to the netlist major:
+ * netlist_major = ((mask_major >> 1) + 1)
+ */
+#define	REMAP_CHEETAH_MASK(x)	(((((x) >> 1) + 0x10) & 0xf0) | ((x) & 0xf))
+
+#ifdef _ASM
+/*
+ * assembler doesn't understand the 'ull' suffix for C constants so
+ * use the inttypes.h macros and undefine them here for assembly code
+ */
+#undef INT64_C
+#undef UINT64_C
+#define	INT64_C(x)	(x)
+#define	UINT64_C(x)	(x)
+#endif	/* _ASM */
+
+/*
+ * DCU Control Register
+ *
+ * +------+----+----+----+----+----+-----+-----+----+----+----+
+ * | Resv | CP | CV | ME | RE | PE | HPE | SPE | SL | WE | PM |
+ * +------+----+----+----+----+----+-----+-----+----+----+----+
+ *  63:50   49   48   47   46	45    44    43   42   41 40:33
+ *
+ * +----+----+----+----+----+----------+-----+----+----+----+---+
+ * | VM | PR | PW | VR | VW | Reserved | WIH | DM | IM | DC | IC|
+ * +----+----+----+----+----+----------+-----+----+----+----+---+
+ * 32:25  24   23   22   21      20:5     4     3    2    1   0
+ */
+
+#define	ASI_DCU	ASI_LSU			    /* same as spitfire ASI_LSU 0x45 */
+#define	DCU_IC	INT64_C(0x0000000000000001) /* icache enable		*/
+#define	DCU_DC	INT64_C(0x0000000000000002) /* dcache enable		*/
+#define	DCU_IM	INT64_C(0x0000000000000004) /* immu enable		*/
+#define	DCU_DM	INT64_C(0x0000000000000008) /* dmmu enable		*/
+#define	DCU_WIH	INT64_C(0x0000000000000010) /* Jaguar only - W$ hash index */
+#define	DCU_VW	INT64_C(0x0000000000200000) /* virt watchpoint write enable  */
+#define	DCU_VR	INT64_C(0x0000000000400000) /* virt watchpoint read enable   */
+#define	DCU_PW	INT64_C(0x0000000000800000) /* phys watchpoint write enable  */
+#define	DCU_PR	INT64_C(0x0000000001000000) /* phys watchpoint read enable   */
+#define	DCU_VM	INT64_C(0x00000001FE000000) /* virtual watchpoint write mask */
+#define	DCU_PM	INT64_C(0x000001FE00000000) /* phys watchpoint write mask    */
+#define	DCU_WE	INT64_C(0x0000020000000000) /* write cache enable	*/
+#define	DCU_SL	INT64_C(0x0000040000000000) /* second load control	*/
+#define	DCU_SPE	INT64_C(0x0000080000000000) /* software prefetch enable */
+#define	DCU_HPE	INT64_C(0x0000100000000000) /* hardware prefetch enable */
+#define	DCU_PE	INT64_C(0x0000200000000000) /* prefetch enable		*/
+#define	DCU_RE	INT64_C(0x0000400000000000) /* RAW bypass enable	*/
+#define	DCU_ME	INT64_C(0x0000800000000000) /* noncache store merging enable */
+#define	DCU_CV	INT64_C(0x0001000000000000) /* virt cacheability when DM=0   */
+#define	DCU_CP	INT64_C(0x0002000000000000) /* phys cacheable when DM,IM=0   */
+#define	DCU_CACHE (DCU_IC|DCU_DC|DCU_WE|DCU_SPE|DCU_HPE|DCU_PE)
+
+/*
+ * bit shifts for the prefetch enable bit
+ */
+#define	DCU_PE_SHIFT	45
+
+/*
+ * Safari Configuration Register
+ */
+#define	ASI_SAFARI_CONFIG	ASI_UPA_CONFIG /* Safari Config Reg, 0x4A */
+#define	SAFARI_CONFIG_ECLK_1	INT64_C(0x0000000000000000) /* 1/1 clock */
+#define	SAFARI_CONFIG_ECLK_1_DIV	1	/* clock divisor: 1 */
+#define	SAFARI_CONFIG_ECLK_2	INT64_C(0x0000000040000000) /* 1/2 clock */
+#define	SAFARI_CONFIG_ECLK_2_DIV	2	/* clock divisor: 2 */
+#define	SAFARI_CONFIG_ECLK_32	INT64_C(0x0000000080000000) /* 1/32 clock */
+#define	SAFARI_CONFIG_ECLK_32_DIV	32	/* clock divisor: 32 */
+#define	SAFARI_CONFIG_ECLK_MASK	(SAFARI_CONFIG_ECLK_32 | SAFARI_CONFIG_ECLK_2)
+
+#if defined(JALAPENO) || defined(SERRANO)
+/*
+ * JBUS Configuration Register
+ */
+#define	ASI_JBUS_CONFIG		ASI_UPA_CONFIG /* JBUS Config Reg, 0x4A */
+#define	JBUS_CONFIG_ECLK_1	INT64_C(0x0000000000000000) /* 1/1 clock */
+#define	JBUS_CONFIG_ECLK_1_DIV	1	/* clock divisor: 1 */
+#define	JBUS_CONFIG_ECLK_2	INT64_C(0x0000000000002000) /* 1/2 clock */
+#define	JBUS_CONFIG_ECLK_2_DIV	2	/* clock divisor: 2 */
+#define	JBUS_CONFIG_ECLK_32	INT64_C(0x0000000000004000) /* 1/32 clock */
+#define	JBUS_CONFIG_ECLK_32_DIV	32	/* clock divisor: 32 */
+#define	JBUS_CONFIG_ECLK_MASK	(JBUS_CONFIG_ECLK_32 | JBUS_CONFIG_ECLK_2)
+#define	JBUS_CONFIG_ECLK_SHIFT	13
+
+/*
+ * Jalapeno/Serrano MCU control registers and ASI
+ */
+#define	ASI_MCU_CTRL		0x72		/* MCU Control Reg ASI */
+#define	JP_MCU_FSM_MASK		INT64_C(0x0000000006000000) /* 26..25 */
+#define	JP_MCU_FSM_SHIFT	25
+#endif /* JALAPENO || SERRANO */
+
+#if defined(SERRANO)
+#define	ASI_MCU_AFAR2_VA	0x18	/* captures FRC/FRU addr */
+#endif	/* SERRANO */
+
+#if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
+/*
+ * Tomatillo Estar control registers (for JP Errataum 85)
+ */
+#define	JBUS_SLAVE_T_PORT_BIT	48
+#define	TOM_HIGH_PA		0x400		/* Hi 32 bit of Tom reg PA */
+#define	M_T_ESTAR_CTRL_PA	0x0f410050	/* M T estar PA */
+#define	S_T_ESTAR_CTRL_PA	0x0e410050	/* S T estar PA */
+#define	M_T_J_CHNG_INIT_PA	0x0f410058	/* Master T estar PA */
+#define	TOM_ESTAR_ELCK_MASK	0x23		/* bit 5,1,0 */
+#define	TOM_FULL_SPEED		0x1
+#define	TOM_HALF_SPEED		0x2
+#define	TOM_SLOW_SPEED		0x20
+#define	TOM_TRIGGER_MASK	0x18
+#define	TOM_TRIGGER		0x10
+
+#endif /* JALAPENO && JALAPENO_ERRATA_85 */
+
+
+/*
+ * Miscellaneous ASI definitions not in machasi.h
+ */
+#define	ASI_DC_UTAG		0x43	/* Dcache Microtag Fields */
+#define	ASI_DC_SNP_TAG		0x44	/* Dcache Snoop Tag Fields */
+#define	ASI_IC_SNP_TAG		0x68	/* Icache Snoop Tag Fields */
+#define	ASI_IPB_DATA		0x69	/* Instruction Prefetch Buffer Data */
+#define	ASI_IPB_TAG		0x6A	/* Instruction Prefetch Buffer Tag */
+#define	ASI_MC_DECODE		0x72	/* Memory Address Decoding Registers */
+#define	ASI_EC_CFG_TIMING	0x73	/* Jaguar shared Ecache Control Reg */
+#define	ASI_EC_DATA		0x74	/* Ecache Data Staging Registers */
+#define	ASI_EC_CTRL		0x75	/* Ecache Control Register */
+#define	ASI_PC_STATUS_DATA	0x30	/* Pcache Status Data Access */
+#define	ASI_PC_DATA		0x31	/* Pcache Diagnostic Data Register */
+#define	ASI_PC_TAG		0x32	/* Pcache Virtual Tag/Valid Field */
+#define	ASI_PC_SNP_TAG		0x33	/* Pcache Snoop Tag Register */
+#define	ASI_L2_DATA		0x6B	/* L2 cache Data Diagnostic Access */
+#define	ASI_L2_TAG		0x6C	/* L2 cache Tag Diagnostic Access */
+
+/*
+ * Bits of Cheetah Asynchronous Fault Status Register
+ *
+ * +---+--+----+----+----+----+---+---+---+---+--+----
+ * |rsv|ME|PRIV|PERR|IERR|ISAP|EMC|EMU|IVC|IVU|TO|BERR
+ * +---+--+----+----+----+----+---+---+---+---+--+----
+ * 63:54 53 52   51   50   49   48  47  46  45 44  43
+ * +---+---+---+---+---+---+---+---+--+--+---+------+---+-------+
+ * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|rsv|M_SYND|rsv||E_SYND|
+ * +---+---+---+---+---+---+---+---+--+--+---+------+---+-------+
+ *   42  41  40  39  38  37  36  35 34 33 32:20 19:16 15:9 8:0
+ *
+ */
+#if defined(CHEETAH_PLUS)
+/*
+ * Bits of Cheetah+ Asynchronous Fault Status Register
+ *
+ * +------------------+----------------------------
+ * |rsv|TUE_SH|IMC|IMU|DTO|DBERR|THCE|TSCE|TUE|DUE|
+ * +------------------+---------------------------- . . .
+ *   63    62   61  60  59    58   57   56  55  54
+ *
+ * Note that bits 60-62 are only implemented in Panther (reserved
+ * in Cheetah+ and Jaguar. Also, bit 56 is reserved in Panther instead
+ * of TSCE since those errors are HW corrected in Panther.
+ */
+#define	C_AFSR_TUE_SH INT64_C(0x4000000000000000) /* uncorrectable tag UE  */
+#define	C_AFSR_IMC  INT64_C(0x2000000000000000)	/* intr vector MTAG ECC */
+#define	C_AFSR_IMU  INT64_C(0x1000000000000000)	/* intr vector MTAG ECC */
+#define	C_AFSR_DTO  INT64_C(0x0800000000000000)	/* disrupting TO error */
+#define	C_AFSR_DBERR INT64_C(0x0400000000000000) /* disrupting BERR error */
+#define	C_AFSR_THCE INT64_C(0x0200000000000000)	/* h/w correctable E$ tag err */
+#define	C_AFSR_TSCE INT64_C(0x0100000000000000)	/* s/w correctable E$ tag err */
+#define	C_AFSR_TUE  INT64_C(0x0080000000000000)	/* uncorrectable E$ tag error */
+#define	C_AFSR_DUE  INT64_C(0x0040000000000000)	/* disrupting UE error */
+#endif	/* CHEETAH_PLUS */
+#define	C_AFSR_ME   INT64_C(0x0020000000000000)	/* errors > 1, same type!=CE */
+#define	C_AFSR_PRIV INT64_C(0x0010000000000000)	/* priv code access error    */
+#define	C_AFSR_PERR INT64_C(0x0008000000000000)	/* system interface protocol */
+#define	C_AFSR_IERR INT64_C(0x0004000000000000)	/* internal system interface */
+#define	C_AFSR_ISAP INT64_C(0x0002000000000000)	/* system request parity err */
+#define	C_AFSR_EMC  INT64_C(0x0001000000000000)	/* mtag   with   CE   error  */
+#define	C_AFSR_EMU  INT64_C(0x0000800000000000)	/* mtag   with   UE   error  */
+#define	C_AFSR_IVC  INT64_C(0x0000400000000000)	/* intr vector with CE error */
+#define	C_AFSR_IVU  INT64_C(0x0000200000000000)	/* intr vector with UE error */
+#define	C_AFSR_TO   INT64_C(0x0000100000000000)	/* bus timeout from sys bus  */
+#define	C_AFSR_BERR INT64_C(0x0000080000000000)	/* bus error from system bus */
+#define	C_AFSR_UCC  INT64_C(0x0000040000000000)	/* E$ with software CE error */
+#define	C_AFSR_UCU  INT64_C(0x0000020000000000)	/* E$ with software UE error */
+#define	C_AFSR_CPC  INT64_C(0x0000010000000000) /* copyout  with  CE  error  */
+#define	C_AFSR_CPU  INT64_C(0x0000008000000000) /* copyout  with  UE  error  */
+#define	C_AFSR_WDC  INT64_C(0x0000004000000000) /* writeback ecache CE error */
+#define	C_AFSR_WDU  INT64_C(0x0000002000000000) /* writeback ecache UE error */
+#define	C_AFSR_EDC  INT64_C(0x0000001000000000) /* ecache  CE  ECC  error    */
+#define	C_AFSR_EDU  INT64_C(0x0000000800000000) /* ecache  UE  ECC  error    */
+#define	C_AFSR_UE   INT64_C(0x0000000400000000) /* uncorrectable ECC error   */
+#define	C_AFSR_CE   INT64_C(0x0000000200000000) /* correctable   ECC error   */
+#define	C_AFSR_M_SYND	INT64_C(0x00000000000f0000) /* mtag  ECC  syndrome   */
+#define	C_AFSR_E_SYND	INT64_C(0x00000000000001ff) /* data  ECC  syndrome   */
+
+/* AFSR bits that could result in CPU removal due to E$ error */
+#define	C_AFSR_L2_SERD_FAIL_UE	(C_AFSR_UCU | C_AFSR_CPU | C_AFSR_WDU | \
+				C_AFSR_EDU)
+#define	C_AFSR_L2_SERD_FAIL_CE	(C_AFSR_UCC | C_AFSR_CPC | C_AFSR_WDC | \
+				C_AFSR_EDC)
+/*
+ * Bits of the Panther Extended Asynchronous Fault Status Register (AFSR_EXT)
+ *
+ * +-----+-------+-----------+-------+-------+---------+------+------+------+
+ * | rsv |RED_ERR|EFA_PAR_ERR|L3_MECC|L3_THCE|L3_TUE_SH|L3_TUE|L3_EDC|L3_EDU|
+ * +-----+-------+-----------+-------+-------+---------+------+------+------+
+ *  63:14   13        12        11       10       9        8      7      6
+ *
+ * +------+------+------+------+------+------+
+ * |L3_UCC|L3_UCU|L3_CPC|L3_CPU|L3_WDC|L3_WDU|
+ * +------+------+------+------+------+------+
+ *     5      4      3      2      1      0
+ *
+ * If the L3_MECC bit is set along with any of the L3 cache errors (bits 0-7)
+ * above, it indicates that an address parity error has occured.
+ */
+#define	C_AFSR_RED_ERR   INT64_C(0x0000000000002000) /* redunancy Efuse error */
+#define	C_AFSR_EFA_PAR_ERR INT64_C(0x0000000000001000) /* Efuse parity error */
+#define	C_AFSR_L3_MECC   INT64_C(0x0000000000000800) /* L3 address parity */
+#define	C_AFSR_L3_THCE   INT64_C(0x0000000000000400) /* tag CE */
+#define	C_AFSR_L3_TUE_SH INT64_C(0x0000000000000200) /* tag UE from snp/cpy */
+#define	C_AFSR_L3_TUE    INT64_C(0x0000000000000100) /* tag UE */
+#define	C_AFSR_L3_EDC    INT64_C(0x0000000000000080) /* L3 cache CE */
+#define	C_AFSR_L3_EDU    INT64_C(0x0000000000000040) /* L3 cache UE */
+#define	C_AFSR_L3_UCC    INT64_C(0x0000000000000020) /* software recover CE */
+#define	C_AFSR_L3_UCU    INT64_C(0x0000000000000010) /* software recover UE */
+#define	C_AFSR_L3_CPC    INT64_C(0x0000000000000008) /* copyout with CE */
+#define	C_AFSR_L3_CPU    INT64_C(0x0000000000000004) /* copyout with UE */
+#define	C_AFSR_L3_WDC    INT64_C(0x0000000000000002) /* writeback CE */
+#define	C_AFSR_L3_WDU    INT64_C(0x0000000000000001) /* writeback UE */
+
+#if defined(JALAPENO) || defined(SERRANO)
+/*
+ * Bits of Jalapeno Asynchronous Fault Status Register
+ *
+ * +-----+------------------------------------------------------------------
+ * | rsv |JETO|SCE|JEIC|JEIT|ME|PRIV|JEIS|IERR|ISAP|ETP|OM|UMS|IVPE|TO|BERR|
+ * +-----+------------------------------------------------------------------
+ * 63:58   57   56   55  54  53  52   51   50   49  48  47  46  45  44  43
+ *
+ * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+
+ * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|RUE|RCE|BP|WBP|FRC|FRU|
+ * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+
+ *   42  41  40  39  38  37  36  35 34 33 32  31  30 29  28  27
+ *
+ * +-----+-----+-----+------+-----------+-------+
+ * | JREQ| ETW | rsv |B_SYND| rsv | AID | E_SYND|
+ * +-----+-----+-----+------+-----+-----+-------+
+ *  26:24 23:22 21:20  19:16 15:14 13:9   8:0
+ *
+ */
+
+/*
+ * Bits of Serrano Asynchronous Fault Status Register
+ *
+ * +-----+------------------------------------------------------------------
+ * | rsv |JETO|SCE|JEIC|JEIT|ME|PRIV|JEIS|IERR|ISAP|ETU|OM|UMS|IVPE|TO|BERR|
+ * +-----+------------------------------------------------------------------
+ * 63:58   57   56   55  54  53  52   51   50   49  48  47  46  45  44  43
+ *
+ * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+
+ * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|RUE|RCE|BP|WBP|FRC|FRU|
+ * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+
+ *   42  41  40  39  38  37  36  35 34 33 32  31  30 29  28  27
+ *
+ * +-----+-----+------+---+------+---+---+-----+-------+
+ * | JREQ| ETW | EFES |ETS|B_SYND|ETI|ETC| AID | E_SYND|
+ * +-----+-----+------+---+------+---+---+-----+-------+
+ *  26:24 23:22    21   20  19:16  15  14  13:9    8:0
+ *
+ */
+
+#define	C_AFSR_JETO	INT64_C(0x0200000000000000) /* JBus Timeout */
+#define	C_AFSR_SCE	INT64_C(0x0100000000000000) /* Snoop parity error */
+#define	C_AFSR_JEIC	INT64_C(0x0080000000000000) /* JBus Illegal Cmd */
+#define	C_AFSR_JEIT	INT64_C(0x0040000000000000) /* Illegal ADTYPE */
+#define	C_AFSR_JEIS	INT64_C(0x0008000000000000) /* Illegal Install State */
+#if defined(SERRANO)
+#define	C_AFSR_ETU	INT64_C(0x0001000000000000) /* L2$ tag CE error */
+#elif defined(JALAPENO)
+#define	C_AFSR_ETP	INT64_C(0x0001000000000000) /* L2$ tag parity error */
+#endif /* JALAPENO */
+#define	C_AFSR_OM	INT64_C(0x0000800000000000) /* out of range mem error */
+#define	C_AFSR_UMS	INT64_C(0x0000400000000000) /* Unsupported store */
+#define	C_AFSR_IVPE	INT64_C(0x0000200000000000) /* intr vector parity err */
+#define	C_AFSR_RUE	INT64_C(0x0000000100000000) /* remote mem UE error */
+#define	C_AFSR_RCE	INT64_C(0x0000000080000000) /* remote mem CE error */
+#define	C_AFSR_BP	INT64_C(0x0000000040000000) /* read data parity err */
+#define	C_AFSR_WBP	INT64_C(0x0000000020000000) /* wb/bs data parity err */
+#define	C_AFSR_FRC	INT64_C(0x0000000010000000) /* foregin mem CE error */
+#define	C_AFSR_FRU	INT64_C(0x0000000008000000) /* foregin mem UE error */
+#define	C_AFSR_JREQ	INT64_C(0x0000000007000000) /* Active JBus req at err */
+#define	C_AFSR_ETW	INT64_C(0x0000000000c00000) /* AID causing UE/CE */
+
+#if defined(SERRANO)
+#define	C_AFSR_EFES	INT64_C(0x0000000000200000) /* E-fuse error summary */
+#define	C_AFSR_ETS	INT64_C(0x0000000000100000) /* L2$ tag SRAM stuck-at */
+#endif /* SERRANO */
+
+#define	C_AFSR_B_SYND	INT64_C(0x00000000000f0000) /* jbus parity syndrome */
+
+#if defined(SERRANO)
+#define	C_AFSR_ETI	INT64_C(0x0000000000008000) /* L2$ tag intermittent */
+#define	C_AFSR_ETC	INT64_C(0x0000000000004000) /* L2$ tag CE */
+#endif /* SERRANO */
+
+#define	C_AFSR_AID	INT64_C(0x0000000000003e00) /* AID causing UE/CE */
+
+/* bit shifts for selected errors */
+#define	C_AFSR_WDU_SHIFT	37
+#define	C_AFSR_UCU_SHIFT	41
+#define	C_AFSR_UCC_SHIFT	42
+#define	C_AFSR_JREQ_SHIFT	24
+#define	C_AFSR_AID_SHIFT	9
+
+/*
+ * Overloaded AFSR fields. During error processing, some of the reserved
+ * fields within the saved AFSR are overwritten with extra information.
+ */
+#define	C_AFSR_PANIC_SHIFT		62
+#define	C_AFSR_IPE_SHIFT		59
+#define	C_AFSR_DPE_SHIFT		58
+
+#else /* JALAPENO || SERRANO */
+
+/* bit shifts for selected errors */
+#define	C_AFSR_WDU_SHIFT	37
+#define	C_AFSR_UCU_SHIFT	41
+#define	C_AFSR_UCC_SHIFT	42
+#define	C_AFSR_L3_UCU_SHIFT	4
+
+/*
+ * Overloaded AFSR fields. During error processing, some of the reserved fields
+ * within the saved AFSR are overwritten with extra information.
+ */
+#define	C_AFSR_FIRSTFLT_SHIFT	63
+#define	C_AFSR_PANIC_SHIFT	30
+#define	C_AFSR_DPE_SHIFT	20
+#define	C_AFSR_IPE_SHIFT	21
+
+#endif /* JALAPENO || SERRANO */
+
+#if defined(JALAPENO) || defined(SERRANO)
+/*
+ * Jalapeno L2 Cache Control Register Bits.
+ *
+ *	Bit#	Name		Description
+ *	63-24	-		reserved
+ *	23:20	EC_ACT_WAY	(read only) indicates which sets are present
+ *	19:16	EC_BLK_WAY	Bit mask indicating which sets are blocked
+ *				from replacement
+ *	15:14	EC_SIZE		L2 cache size
+ *	13:12	-		reserved
+ *	11	EC_PAR_EN	Enables parity checking on L2 cache tags
+ *	10	EC_ECC_EN	Enables ECC checking on L2 cache data
+ *	9	EC_ECC_FORCE	Enables EC_CHECK[8:0] onto L2 cache ECC bits
+ *	8:0	EC_CHECK	ECC check vector to force onto ECC bits
+ */
+
+#define	JP_ECCTRL_ECSIZE_MASK		0xc000
+#define	JP_ECCTRL_ECSIZE_SHIFT		14
+#define	JP_ECCTRL_ECSIZE_MIN		0x80000
+
+/*
+ * Jalapeno L2 Cache Error Enable Register Bits
+ *
+ *	Bit#	Name	Description
+ *	63-33	-	reserved
+ *	32	SCDE	Enable detection of JBUS control parity error
+ *	31:24	-	reserved
+ *	23	IAEN	Enable trap on illegal physical address
+ *	22	IERREN	Enable FERR system reset on CPU internal errors
+ *	21	PERREN	Enable FERR system reset on JBUS protocol errors
+ *	20	SCEN	Enable FERR system reset on JBUS control parity error
+ *	19:11	FMED	Forced error on the memory ECC
+ *	10	FME	Force error on memory ECC
+ *	9:6	FPD	Bits to use when FSP forces JBUS addr/data parity error
+ *	5	FSP	Force error on outgoing JBUS addr/data parity
+ *	4	ETPEN	Enable FERR system reset on L2 tags parity error
+ *	3	UCEEN	Enable trap on SW handled external cache error
+ *	2	ISAPEN	Enable FERR system reset on request parity error
+ *	1	NCEEN	Enable trap on uncorrectable ECC error and system err
+ *	0	CEEN	Enable trap on correctable ECC errors
+ */
+
+#define	EN_REG_UCEEN	INT64_C(0x0000000000000008) /* enable UCC,UCU */
+#define	EN_REG_ISAPEN	INT64_C(0x0000000000000004) /* enable ISAP */
+#define	EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */
+#define	EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */
+
+#define	EN_REG_DISABLE	INT64_C(0x0000000000000000) /* no errors enabled */
+#define	EN_REG_ECC_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN)
+#define	EN_REG_CE_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN)
+#define	EN_REG_ENABLE \
+	(EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN | EN_REG_CEEN)
+
+#else /* JALAPENO || SERRANO */
+#if defined(CHEETAH_PLUS)
+/*
+ * Cheetah+ External Cache Control Register Bits.
+ */
+#define	ECCR_ASSOC	INT64_C(0x0000000001000000) /* Ecache Assoc. */
+#define	ECCR_ASSOC_SHIFT	24
+#endif	/* CHEETAH_PLUS */
+
+/*
+ * Bits of Cheetah External Cache Error Enable Register
+ *
+ * +-----+-----+-------+-----+-------+-------+--------+-------+------+
+ * | rsv | FMT | FMECC | FMD | FDECC | UCEEN | ISAPEN | NCEEN | CEEN |
+ * +-----+-----+-------+-----+-------+-------+--------+-------+------+
+ *  63:19   18  17  14    13    12:4     3        2       1       0
+ *
+ */
+#define	EN_REG_FMT	INT64_C(0x0000000000040000) /* force system mtag ECC */
+#define	EN_REG_FMECC	INT64_C(0x000000000003C000) /* forced mtag ECC vector */
+#define	EN_REG_FMD	INT64_C(0x0000000000002000) /* force system data ECC */
+#define	EN_REG_FDECC	INT64_C(0x0000000000001ff0) /* forced data ECC vector */
+#define	EN_REG_UCEEN	INT64_C(0x0000000000000008) /* enable UCC,UCU */
+#define	EN_REG_ISAPEN	INT64_C(0x0000000000000004) /* enable ISAP */
+#define	EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */
+#define	EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */
+#define	EN_REG_DISABLE	INT64_C(0x0000000000000000) /* no errors enabled */
+#define	EN_REG_ECC_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN)
+#define	EN_REG_CE_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN)
+#define	EN_REG_ENABLE \
+	(EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN | EN_REG_CEEN)
+#endif	/* JALAPENO || SERRANO */
+
+/*
+ * bit shifts for selected bits
+ */
+#define	EN_REG_CEEN_SHIFT	0
+
+/* Cheetah/Cheetah+ Dcache size */
+#define	CH_DCACHE_SIZE		0x10000
+
+/* Cheetah/Cheetah+ Dcache linesize */
+#define	CH_DCACHE_LSIZE		0x20
+
+/* Cheetah/Cheetah+/Jaguar Icache size */
+#define	CH_ICACHE_SIZE		0x8000
+
+/* Cheetah/Cheetah+/Jaguar Icache linesize */
+#define	CH_ICACHE_LSIZE		0x20
+
+/* Panther Icache size */
+#define	PN_ICACHE_SIZE		0x10000
+
+/* Panther Icache linesize */
+#define	PN_ICACHE_LSIZE		0x40
+
+/* Pcache size for the cheetah family of CPUs */
+#define	CH_PCACHE_SIZE		0x800
+
+/* Pcache linesize  for the cheetah family of CPUs */
+#define	CH_PCACHE_LSIZE		0x40
+
+/*
+ * The cheetah+ CPU module handles Cheetah+, Jaguar, and Panther so
+ * we have to pick max size and min linesize values for the Icache
+ * accordingly.
+ */
+#define	CHP_ICACHE_MAX_SIZE	PN_ICACHE_SIZE
+#define	CHP_ICACHE_MIN_LSIZE	CH_ICACHE_LSIZE
+
+/*
+ * The minimum size needed to ensure consistency on a virtually address
+ * cache.  Computed by taking the largest virtually indexed cache and dividing
+ * by its associativity.
+ */
+#define	CH_VAC_SIZE		0x4000
+
+/*
+ * The following definitions give the syndromes that will be seen when attempts
+ * are made to read data that has been intentionally poisoned.  Intentional
+ * poisoning is performed when an error has been detected, and is designed to
+ * allow software to effectively distinguish between root problems and secondary
+ * effects.  The following syndromes and their descriptions are taken from the
+ * UltraSPARC-III Cu Error Manual, Section 5.4.3.1.
+ */
+
+/*
+ * For a DSTAT = 2 or 3 event (see Sec 5.3.4.4) from the system bus for a
+ * cacheable load, data bits [1:0] are inverted in the data stored in the
+ * L2-cache.  The syndrome seen when one of these signalling words is read will
+ * be 0x11c.
+ */
+#define	CH_POISON_SYND_FROM_DSTAT23	0x11c
+
+/*
+ * For an uncorrectable data ECC error from the L2-cache, data bits [127:126]
+ * are inverted in data sent to the system bus as part of a writeback or
+ * copyout.  The syndrome seen when one of these signalling words is read will
+ * be 0x071.
+ */
+#define	CH_POISON_SYND_FROM_XXU_WRITE	0x71
+
+/*
+ * For uncorrectable data ECC error on the L2-cache read done to complete a
+ * store merge event, where bytes written by the processor are merged with
+ * bytes from an L2-cache line, ECC check bits [1:0] are inverted in the data
+ * scrubbed back to the L2-cache.  The syndrome seen when one of these
+ * signalling words is read will be 0x003.
+ */
+#define	CH_POISON_SYND_FROM_XXU_WRMERGE	0x3
+
+/*
+ * To help understand the following definitions, this block of comments
+ * provides information on Cheetah's E$.
+ *
+ * Cheetah supports three different E$ sizes (1MB, 4MB, and 8MB). The
+ * number of E$ lines remains constant regardless of the size of the E$
+ * as does the subblock size, however the number of 64-byte subblocks per
+ * line varies depending on the E$ size.
+ *
+ * An E$ tag (for an E$ line) contains an EC_tag field, corresponding to the
+ * high order physical address bits of that E$ line's contents, and 1 to 8
+ * EC_state fields, indicating the state of each subblock. Due to the E$ line
+ * size variance depending on the total size of the E$, the number of bits in
+ * the EC_tag field varies as does the number of subblocks (and EC_state
+ * fields) per E$ line.
+ *
+ * A 1MB E$ has a line size of 64 bytes, containing 1 subblock per line.
+ * A 4MB E$ has a line size of 256 bytes, containing 4 subblocks per line.
+ * An 8MB E$ has a line size of 512 bytes, containing 8 subblocks per line.
+ *
+ * An E$ tag for a particular E$ line can be read via a diagnostic ASI
+ * as a 64-bit value.
+ * Within the E$ tag 64-bit value, the EC_tag field is interpreted as follows:
+ *	- for a 1MB E$, the EC_tag is in bits <43:21> and corresponds
+ *		to physical address bits <42:20> (bits <41:19> for Cheetah+)
+ *	- for a 4MB E$, the EC_tag is in bits <43:23> and corresponds
+ *		to physical address bits <42:22> (bits <41:21> for Cheetah+)
+ *	- for an 8MB E$, the EC_tag is in bits <43:24> and corresponds
+ *		to physical address bits <42:23> (bits <41:22> for Cheetah+)
+ * Within the E$ tag 64-bit value, the EC_state field(s) is(are) interpreted
+ * as follows:
+ *	- for a 1MB E$, EC_state0 is in bits <2:0>
+ *	- for a 4MB E$, EC_state0 is in bits <2:0>, EC_state1 is in
+ *		bits <5:3>, EC_state2 is in bits <8:6>, EC_state3 is
+ *		in bits <11:9>
+ *	- for an 8MB E$, EC_state0 is in bits <2:0>, EC_state1 is in
+ *		bits <5:3>, EC_state2 is in bits <8:6>, EC_state3 is
+ *		in bits <11:9>, EC_state4 is in bits <14:12>, EC_state5
+ *		is in bits <17:15>, EC_state6 is in bits <20:18>,
+ *		EC_state7 is in bits <23:21>
+ * Note that each EC_state field contains a value representing the state
+ * of its corresponding subblock.
+ *
+ */
+/*
+ * Jaguar changes from Cheetah/Cheetah+ Ecache:
+ *
+ * The Jaguar Ecache is similiar to that used for Cheetah/Cheetah+ with a
+ * couple of differences :
+ *	- Jaguar Ecache only comes in 4MB and 8MB versions.
+ *		- 8MB E$ has 2 64 byte subblocks per line.
+ *		- 4MB E$ has 1 64 byte subblock per line.
+ *
+ * An E$ tag for a particular E$ line can be read via a diagnostic ASI
+ * as a 64-bit value.
+ * Within the E$ tag 64-bit value, the EC_tag field is interpreted as follows:
+ *	- for a 4MB E$, the EC_tag is in bits <41:21> and corresponds
+ *		to physical address bits <41:21>
+ *	- for a 8MB E$, the EC_tag is in bits <41:22> and corresponds
+ *		to physical address bits <41:22>
+ *
+ * The Jaguar E$ tag also contains LRU field in bit <42> which must be
+ * masked off when the tag value is being compared to a PA.
+ *
+ * Within the E$ tag 64-bit value, the EC_state field(s) is(are) interpreted
+ * as follows:
+ *	- for 4MB E$, EC_state0 is in bits <2:0>
+ *	- for 8MB E$, EC_state0 is in bits <2:0>, EC_state1 is in bits <5:3>.
+ * Each EC_state field contains a value representing the state of its
+ * corresponding subblock.
+ *
+ * Note that the subblock size and state values are the same for both
+ * Cheetah/Cheetah+ and Jaguar.
+ */
+
+/* Ecache sizes */
+#define	CH_ECACHE_8M_SIZE	0x800000
+#define	CH_ECACHE_4M_SIZE	0x400000
+#define	CH_ECACHE_1M_SIZE	0x100000
+
+#define	PN_L2_SIZE		0x200000
+#define	PN_L2_LINESIZE		64
+#define	PN_L2_ECC_WORDS		2
+#define	PN_L2_NWAYS		4
+#define	PN_L2_SET_SIZE		(PN_L2_SIZE / PN_L2_NWAYS)
+#define	PN_L2_MAX_SET		(PN_L2_SIZE - PN_L2_SET_SIZE)
+#define	PN_L2_DATA_ECC_SEL	0x200000 /* bit 21 selects ECC */
+#define	PN_L2_ECC_LO_REG	0x20 /* bit 5 set for L2 tag access */
+#define	PN_L2_INDEX_MASK	0x7ffc0 /* bits 18:6 */
+#define	PN_L2_WAY_INCR		0x80000	/* l2-ec-way = <20:19> */
+#define	PN_L2_WAY_LIM		INT64_C(0x200000)
+#define	PN_L2_WAY_SHIFT		19
+
+#define	PN_L3_SIZE		0x2000000
+#define	PN_L3_LINESIZE		64
+#define	PN_L3_NWAYS		4
+#define	PN_L3_SET_SIZE		(PN_L3_SIZE / PN_L3_NWAYS)
+#define	PN_L3_MAX_SET		(PN_L3_SIZE - PN_L3_SET_SIZE)
+#define	PN_L3_WAY_SHIFT		23
+#define	PN_L3_TAG_RD_MASK	0x7fffc0	/* ec_tag = PA<22:6>  */
+#define	PN_L3_WAY_INCR		0x800000	/* ec_way = <24:23> */
+#define	PN_L3_WAY_LIM		INT64_C(0x2000000)
+
+/* Pcache Defines */
+#define	PN_PCACHE_ADDR_MASK	0x1c0		/* PC_addr = <8:6> */
+#define	PN_PCACHE_WAY_INCR	0x200		/* PC_way = <10:9> */
+#define	PN_PCACHE_WORD_SHIFT	3		/* PC_dbl_word = <5:3> */
+#define	PN_PCACHE_NWAYS		4
+
+/* Cheetah Ecache is direct-mapped, Cheetah+ can be 2-way or direct-mapped */
+#define	CH_ECACHE_NWAY		1
+#if defined(CHEETAH_PLUS)
+#define	CHP_ECACHE_NWAY		2
+#define	PN_ECACHE_NWAY		4
+#endif	/* CHEETAH_PLUS */
+#if defined(JALAPENO) || defined(SERRANO)
+#define	JP_ECACHE_NWAY		4
+#define	JP_ECACHE_NWAY_SHIFT	2
+#endif /* JALAPENO || SERRANO */
+
+/* Maximum Ecache size */
+#define	CH_ECACHE_MAX_SIZE	CH_ECACHE_8M_SIZE
+
+/* Minimum Ecache line size */
+#define	CH_ECACHE_MIN_LSIZE	64
+
+/* Maximum Ecache line size - 8Mb Ecache has 512 byte linesize */
+#define	CH_ECACHE_MAX_LSIZE	512
+
+/* Size of Ecache data staging register size (see Cheetah PRM 10.7.2) */
+#define	CH_ECACHE_STGREG_SIZE	32
+#define	CH_ECACHE_STGREG_TOTALSIZE	40	/* data regs + ecc */
+
+/* The number of staging registers containing data, for ASI_EC_DATA */
+#define	CH_ECACHE_STGREG_NUM	(CH_ECACHE_STGREG_SIZE / sizeof (uint64_t))
+
+/* Size of Ecache data subblock which has state field in Ecache tag */
+#define	CH_ECACHE_SUBBLK_SIZE	64
+#define	CH_ECACHE_SUBBLK_SHIFT	6
+
+#if defined(JALAPENO) || defined(SERRANO)
+#define	JP_ECACHE_MAX_LSIZE	CH_ECACHE_SUBBLK_SIZE
+#define	JP_ECACHE_MAX_SIZE	0x400000
+#endif /* JALAPENO || SERRANO */
+
+/*
+ * Maximum ecache setsize to support page coloring of heterogenous
+ * cheetah+ cpus. Max ecache setsize is calculated to be the max ecache size
+ * divided by the minimum associativity of the max ecache.
+ *
+ * NOTE: CHP_ECACHE_MAX_SIZE and CHP_ECACHE_MIN_NWAY need to be updated with
+ * new cheetah+ cpus. The maximum setsize may not necessarily be associated with
+ * the max ecache size if the cache associativity is large. If so, MAX_SETSIZE
+ * needs to be updated accordingly.
+ */
+#if defined(CHEETAH_PLUS)
+#define	CHP_ECACHE_MIN_NWAY	1	/* direct-mapped */
+#define	CHP_ECACHE_MAX_SIZE	CH_ECACHE_MAX_SIZE
+#define	CHP_ECACHE_MAX_SETSIZE	(CHP_ECACHE_MAX_SIZE / CHP_ECACHE_MIN_NWAY)
+#endif	/* CHEETAH_PLUS */
+
+/*
+ * Bits to shift EC_tag field of E$ tag to form PA
+ * (See Cheetah PRM 10.7.4, Cheetah+ Delta PRM 10.7)
+ */
+#if defined(JALAPENO) || defined(SERRANO)
+#define	CH_ECTAG_PA_SHIFT	18
+#elif defined(CHEETAH_PLUS)
+#define	CH_ECTAG_PA_SHIFT	2
+#else	/* CHEETAH_PLUS */
+#define	CH_ECTAG_PA_SHIFT	1
+#endif	/* CHEETAH_PLUS */
+#define	PN_L3TAG_PA_SHIFT	1
+#define	PN_L3TAG_PA_MASK	0xfffff000000	/* tag bits[43:24] */
+#define	PN_L2TAG_PA_MASK	0x7fffff80000	/* tag bits[42:19] */
+
+#if defined(JALAPENO) || defined(SERRANO)
+/*
+ * Macros for Jalapeno L2 Cache Tag/State/Parity
+ *
+ * +-----------+--------+--------+----------------------+
+ * |   -       | EC_par |EC_state|  EC_tag = PA[42:18]  |
+ * +-----------+--------+--------+----------------------+
+ *    63:29        28      27:25         24:0
+ */
+/*
+ * Constants representing the complete Jalapeno Ecache tag state:
+ */
+#define	JP_ECSTATE_SIZE		3		/* three bits */
+#define	JP_ECSTATE_MASK		0x7		/* three bit field */
+#define	JP_ECSTATE_INV		0x0		/* invalid */
+#define	JP_ECSTATE_SHR		0x1		/* shared */
+#define	JP_ECSTATE_RES1		0x2		/* reserved */
+#define	JP_ECSTATE_EXL		0x3		/* exclusive */
+#define	JP_ECSTATE_RES2		0x4		/* reserved */
+#define	JP_ECSTATE_OWN		0x5		/* owner */
+#define	JP_ECSTATE_MOD		0x7		/* modified */
+#define	JP_ECSTATE_RES3		0x6		/* reserved */
+#define	JP_ECTAG_STATE_SHIFT	25
+
+#define	CH_ECSTATE_SIZE		JP_ECSTATE_SIZE
+#define	CH_ECSTATE_MASK		JP_ECSTATE_MASK
+#define	CH_ECSTATE_INV		JP_ECSTATE_INV
+#define	CH_ECSTATE_SHR		JP_ECSTATE_SHR
+#define	CH_ECSTATE_EXL		JP_ECSTATE_EXL
+#define	CH_ECSTATE_OWN		JP_ECSTATE_OWN
+#define	CH_ECSTATE_MOD		JP_ECSTATE_MOD
+#define	CH_ECSTATE_RES1		JP_ECSTATE_RES1
+#define	CH_ECSTATE_OWS		JP_ECSTATE_RES3
+#define	CH_ECSTATE_RES2		JP_ECSTATE_RES2
+
+/* Number of subblock states per Ecache line. */
+#define	CH_ECTAG_NSUBBLKS(totalsize)	1
+
+/* Mask for Tag state(s) field, 3 bits per subblock state. */
+#define	CH_ECTAG_STATE_SHIFT(subblk)	JP_ECTAG_STATE_SHIFT
+#define	CH_ECTAG_STATE_MASK(totalsize)			\
+	((uint64_t)(JP_ECSTATE_MASK<<JP_ECTAG_STATE_SHIFT))
+
+/* For a line to be invalid, all of its subblock states must be invalid. */
+#define	CH_ECTAG_LINE_INVALID(totalsize, tag)		\
+	(((tag) & CH_ECTAG_STATE_MASK(totalsize)) == 0)
+
+/* Build address mask for tag physical address bits. */
+#define	CH_ECTAG_PA_MASK(setsize)	P2ALIGN(C_AFAR_PA, (int)(setsize))
+
+/* Get physical address bits from the EC_tag field of an E$ tag */
+#define	CH_ECTAG_TO_PA(setsize, tag)	(((tag) << CH_ECTAG_PA_SHIFT) &	\
+	CH_ECTAG_PA_MASK(setsize))
+
+/* Given a physical address, compute index for subblock tag state. */
+#define	CH_ECTAG_PA_TO_SUBBLK(totalsize, pa)		1
+
+/* Given a physical address and assoc. tag, get the subblock state. */
+#define	CH_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag)			\
+	(((tag) >> JP_ECTAG_STATE_SHIFT) &	JP_ECSTATE_MASK)
+
+#else /* JALAPENO || SERRANO */
+
+/*
+ * Constants representing the complete Cheetah Ecache tag state:
+ */
+#define	CH_ECSTATE_SIZE		3		/* three bits per subblock */
+#define	CH_ECSTATE_MASK		0x7		/* three bit field */
+#define	CH_ECSTATE_INV		0x0		/* invalid */
+#define	CH_ECSTATE_SHR		0x1		/* shared */
+#define	CH_ECSTATE_EXL		0x2		/* exclusive */
+#define	CH_ECSTATE_OWN		0x3		/* owner */
+#define	CH_ECSTATE_MOD		0x4		/* modified */
+#define	CH_ECSTATE_RES1		0x5		/* reserved */
+#define	CH_ECSTATE_OWS		0x6		/* owner/shared */
+#define	CH_ECSTATE_RES2		0x7		/* reserved */
+
+/*
+ * Macros for Cheetah Ecache tags
+ */
+
+/* Number of subblock states per Ecache line. */
+#define	CH_ECTAG_NSUBBLKS(totalsize)	((totalsize) / CH_ECACHE_1M_SIZE)
+
+/* Mask for Tag state(s) field, 3 bits per subblock state. */
+#define	CH_ECTAG_STATE_SHIFT(subblk)	(subblk * CH_ECSTATE_SIZE)
+#define	CH_ECTAG_STATE_MASK(totalsize)			\
+	((uint64_t)					\
+	((1 << (CH_ECTAG_NSUBBLKS(totalsize) * CH_ECSTATE_SIZE)) - 1))
+
+/* For a line to be invalid, all of its subblock states must be invalid. */
+#define	CH_ECTAG_LINE_INVALID(totalsize, tag)		\
+	(((tag) & CH_ECTAG_STATE_MASK(totalsize)) == 0)
+
+/* Build address mask for tag physical address bits. */
+#define	CH_ECTAG_PA_MASK(setsize)	P2ALIGN(C_AFAR_PA, (int)(setsize))
+
+/* Get physical address bits from the EC_tag field of an E$ tag */
+#define	CH_ECTAG_TO_PA(setsize, tag)	(((tag) >> CH_ECTAG_PA_SHIFT) &	\
+	CH_ECTAG_PA_MASK(setsize))
+
+/* Given a physical address, compute index for subblock tag state. */
+#define	CH_ECTAG_PA_TO_SUBBLK(totalsize, pa)		\
+	(((pa) >> CH_ECACHE_SUBBLK_SHIFT) & (CH_ECTAG_NSUBBLKS(totalsize) - 1))
+
+/* Given a physical address and assoc. tag, get the subblock state. */
+#define	CH_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag)			\
+	(((tag) >>							\
+	(CH_ECTAG_PA_TO_SUBBLK(totalsize, pa) * CH_ECSTATE_SIZE)) &	\
+	CH_ECSTATE_MASK)
+#endif /* JALAPENO || SERRANO */
+
+/* Panther only has one EC_State field in the L3 tag */
+#define	PN_L3_LINE_INVALID(tag)		(((tag) & CH_ECSTATE_MASK) == 0)
+
+/* Panther only has one State field in the L2 tag */
+#define	PN_L2_LINE_INVALID(tag)		(((tag) & CH_ECSTATE_MASK) == 0)
+
+/* Get physical address bits from the EC_tag field of an L3$ tag */
+#define	PN_L3TAG_TO_PA(tag)		(((tag) & PN_L3TAG_PA_MASK) >> \
+	PN_L3TAG_PA_SHIFT)
+
+/* Get physical address bits from the tag field of an L2$ tag */
+#define	PN_L2TAG_TO_PA(tag)		((tag) & PN_L2TAG_PA_MASK)
+
+#if defined(JALAPENO) || defined(SERRANO)
+/*
+ * Jalapeno L2 Cache ASI_ECACHE_FLUSH:
+ * +-------+-----------------+--------+---+-----+-------------+------+
+ * |   -   | Port_ID |   -   | EC_Way | 1 |  -  | EC_Tag_Addr |   -  |
+ * +-------+-----------------+--------+---+-----+-------------+------+
+ *  63:41     40:36    35:34    33:32  31  30:18      17:6       5:0
+ */
+
+#define	JP_EC_TO_SET_SIZE_SHIFT		2
+#define	JP_ECACHE_IDX_DISP_FLUSH	INT64_C(0x0000000080000000)
+#define	JP_ECFLUSH_PORTID_SHIFT		36
+#define	JP_ECFLUSH_EC_WAY_SHIFT		32
+#define	JP_EC_TAG_DATA_WAY_SHIFT	JP_ECFLUSH_EC_WAY_SHIFT
+#endif	/* JALAPENO || SERRANO */
+
+/*
+ * Macros for Jaguar Ecache tags
+ */
+
+/* Ecache sizes */
+#define	JG_ECACHE_8M_SIZE	0x800000
+#define	JG_ECACHE_4M_SIZE	0x400000
+
+/* Jaguar E$ tag LRU mask */
+#define	JG_LRU_MASK UINT64_C(0x0000040000000000) /* PA<42> LRU bit */
+
+/*
+ * Note that Jaguar and Cheetah/Cheetah+ have the same subblock state size
+ * so rather than duplicating existing defn's we can use the Cheetah+ versions
+ * in the Jaguar defn's below.
+ */
+/* Number of subblock states per Ecache line. */
+#define	JG_ECTAG_NSUBBLKS(cachesize)	((cachesize) / JG_ECACHE_4M_SIZE)
+
+/* Mask for Tag state(s) field, 3 bits per subblock state. */
+#define	JG_ECTAG_STATE_MASK(totalsize)			\
+	((uint64_t)					\
+	((1 << (JG_ECTAG_NSUBBLKS(totalsize) * CH_ECSTATE_SIZE)) - 1))
+
+/* For a line to be invalid, all of its subblock states must be invalid. */
+#define	JG_ECTAG_LINE_INVALID(totalsize, tag)		\
+	(((tag) & JG_ECTAG_STATE_MASK(totalsize)) == 0)
+
+/* Build address mask for tag physical address bits. */
+#define	JG_ECTAG_PA_MASK(setsize)	P2ALIGN(((~JG_LRU_MASK) & C_AFAR_PA), \
+							(int)(setsize))
+
+/* Get physical address bits from the EC_tag field of an E$ tag */
+#define	JG_ECTAG_TO_PA(setsize, tag)	((tag & JG_ECTAG_PA_MASK(setsize)))
+
+/* Given a physical address, compute index for subblock tag state. */
+#define	JG_ECTAG_PA_TO_SUBBLK(totalsize, pa)		\
+	(((pa) >> CH_ECACHE_SUBBLK_SHIFT) & (JG_ECTAG_NSUBBLKS(totalsize) - 1))
+
+/* Given a physical address and assoc. tag, get the subblock state. */
+#define	JG_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag)			\
+	(((tag) >>							\
+	(JG_ECTAG_PA_TO_SUBBLK(totalsize, pa) * CH_ECSTATE_SIZE)) &	\
+	CH_ECSTATE_MASK)
+
+
+#if defined(CHEETAH_PLUS)
+/*
+ * Cheetah+ Tag ECC Bit and Displacement Flush Bit in Ecache Tag Access.
+ * See Cheetah+ Delta PRM 10.7
+ */
+#define	CHP_ECACHE_IDX_TAG_ECC		INT64_C(0x0000000000800000)
+#define	CHP_ECACHE_IDX_DISP_FLUSH	INT64_C(0x0000000001000000)
+#define	PN_L2_IDX_DISP_FLUSH		INT64_C(0x0000000000800000)
+#define	PN_L3_IDX_DISP_FLUSH		INT64_C(0x0000000004000000)
+#endif	/* CHEETAH_PLUS */
+
+/*
+ * Macros for Cheetah Dcache diagnostic accesses.
+ */
+
+/*
+ * Dcache Index Mask for bits from *AFAR*.  Note that Dcache is virtually
+ * indexed, so only bits [12:5] are valid from the AFAR.  This
+ * means we have to search through the 4 ways + bit 13 (i.e. we have
+ * to try 8 indexes).
+ */
+#define	CH_DCACHE_IDX_MASK		0x01fe0
+#define	CH_DCACHE_IDX_INCR		0x02000
+#define	CH_DCACHE_IDX_LIMIT		0x10000
+#define	CH_DCACHE_NWAY			4
+#define	CH_DCACHE_WAY_MASK		0x0c000
+#define	CH_DCACHE_WAY_SHIFT		14
+#define	CH_DCIDX_TO_WAY(idx)		(((idx) & CH_DCACHE_WAY_MASK) >> \
+						CH_DCACHE_WAY_SHIFT)
+#define	CH_DCTAG_PA_MASK		INT64_C(0x000007ffffffe000)
+#define	CH_DCTAG_PA_SHIFT		12
+#define	CH_DCTAG_VALID_BIT		INT64_C(0x0000000000000001)
+#define	CH_DCTAG_LINE_INVALID(tag)	(((tag) & CH_DCTAG_VALID_BIT) == 0)
+#define	CH_DCIDX_TO_ADDR(idx)		((idx) & CH_DCACHE_IDX_MASK)
+#define	CH_DCTAG_TO_PA(tag)		(((tag) << CH_DCTAG_PA_SHIFT) & \
+					    CH_DCTAG_PA_MASK)
+#define	CH_DCTAG_MATCH(tag, pa)		(!CH_DCTAG_LINE_INVALID(tag) && \
+			    ((pa) & CH_DCTAG_PA_MASK) == CH_DCTAG_TO_PA(tag))
+#define	CH_DCSNTAG_MASK			INT64_C(0x000007ffffffe000)
+#define	CH_DCSNTAG_TO_PA(tag)		((tag << CH_DCTAG_PA_SHIFT) \
+							& CH_DCSNTAG_MASK)
+#define	CH_DCUTAG_TO_UTAG(tag)		((tag) & 0xff)
+#define	CH_DCUTAG_TO_VA(tag)		((tag & 0xff) << 14)
+#define	CH_DCUTAG_IDX_MASK		0x03fe0
+#define	CH_DC_DATA_REG_SIZE		32
+#define	CH_DC_UTAG_MASK			0xff
+#if defined(CHEETAH_PLUS) || defined(JALAPENO) || defined(SERRANO)
+#define	CHP_DCTAG_PARMASK		INT64_C(0x000000007ffffffe)
+#define	CHP_DCSNTAG_PARMASK		INT64_C(0x000000007ffffffe)
+#define	CHP_DCTAG_MASK			INT64_C(0x000003ffffffe000)
+#define	CHP_DCSNTAG_MASK		INT64_C(0x000003ffffffe000)
+#define	CHP_DCWAY_MASK			INT64_C(0x0000000000003fe0)
+#define	CHP_DCUTAG_TO_UTAG(tag)		((tag) & 0xffff)
+#define	CHP_DCPATAG_TO_PA(tag)		((tag << CH_DCTAG_PA_SHIFT) \
+							& CHP_DCTAG_MASK)
+#define	CHP_DCSNTAG_TO_PA(tag)		((tag << CH_DCTAG_PA_SHIFT) \
+							& CHP_DCSNTAG_MASK)
+#define	CHP_DC_IDX(dcp)			((dcp->dc_idx & 0x1fc0) >> 5)
+#define	CHP_DCTAG_PARITY(tag)		(tag & CHP_DC_TAG)
+#define	CHP_DCSNTAG_PARITY(tag)		(tag & CHP_DC_SNTAG)
+#define	CHP_DC_TAG			0x1
+#define	CHP_DC_SNTAG			0x2
+#define	PN_DC_DATA_PARITY_SHIFT    	8
+#define	PN_DC_DATA_PARITY_MASK    	0xff
+#define	PN_DC_DATA_ALL_PARITY_MASK    	0xffffffff
+#endif	/* CHEETAH_PLUS || JALAPENO || SERRANO */
+#define	PN_DC_DATA_PARITY_BIT_SHIFT    	16
+
+/*
+ * Macros for Cheetah Icache diagnostic accesses.
+ */
+
+/*
+ * Icache Index Mask for bits from *AFAR*. Note that the Icache is virtually
+ * indexed for Panther and physically indexed for other CPUs. For Panther,
+ * we obtain an index by looking at bits[12:6] of the AFAR PA and we check
+ * both lines associated with bit 13 = 0 or 1 (total of 8 entries to check).
+ * For non-Panther CPUs we get our index by just looking at bits[12:5] of
+ * the AFAR PA (total of 4 entries to check). The Icache index is also
+ * confusing because we need to shift the virtual address bits left by one
+ * for the index.
+ */
+#define	CH_ICACHE_IDX_MASK		0x01fe0
+#define	PN_ICACHE_IDX_MASK		0x03fc0
+#define	PN_ICACHE_VA_IDX_MASK		0x01fc0
+#define	CH_ICACHE_IDX_SHIFT		1
+#define	CH_ICACHE_IDX_INCR		0x04000
+#define	PN_ICACHE_IDX_INCR		0x08000
+#define	CH_ICACHE_IDX_LIMIT		0x10000
+#define	PN_ICACHE_IDX_LIMIT		0x20000
+#define	CH_ICACHE_NWAY			4
+#define	CH_ICACHE_WAY_MASK		0x0c000
+#define	CH_ICACHE_WAY_SHIFT		14
+#define	PN_ICACHE_WAY_MASK		0x18000
+#define	PN_ICACHE_WAY_SHIFT		15
+#define	CH_ICTAG_PA			0x00
+#define	CH_ICTAG_UTAG			0x08
+#define	CH_ICTAG_UPPER			0x10
+#define	CH_ICTAG_LOWER			0x30
+#define	CH_ICTAG_TMASK			0x3f
+#define	CH_ICPATAG_MASK			INT64_C(0x000007ffffffe000)
+#define	CH_ICPATAG_LBITS		0xff	/* lower 8 bits undefined */
+#define	CH_ICPATAG_SHIFT		5
+#define	CH_ICIDX_TO_WAY(idx)		(((idx) & CH_ICACHE_WAY_MASK) >> \
+						CH_ICACHE_WAY_SHIFT)
+#define	PN_ICIDX_TO_WAY(idx)		(((idx) & PN_ICACHE_WAY_MASK) >> \
+						PN_ICACHE_WAY_SHIFT)
+#define	CH_ICIDX_TO_ADDR(idx)		(((idx) >> CH_ICACHE_IDX_SHIFT) & \
+						CH_ICACHE_IDX_MASK)
+#define	PN_ICIDX_TO_ADDR(idx)		(((idx) >> CH_ICACHE_IDX_SHIFT) & \
+						PN_ICACHE_IDX_MASK)
+#define	CH_ICPATAG_TO_PA(tag)		(((tag) << CH_ICPATAG_SHIFT) & \
+						CH_ICPATAG_MASK)
+#define	CH_ICPATAG_MATCH(tag, pa)	(CH_ICPATAG_TO_PA(tag) == \
+						((pa) & CH_ICPATAG_MASK))
+#define	CH_ICUTAG_MASK			INT64_C(0x00000000001fe000)
+#define	CH_ICUTAG_TO_UTAG(tag)		(((tag) >> 38) & 0xff)
+#define	CH_ICUTAG_TO_VA(tag)		(((tag) >> 25) & CH_ICUTAG_MASK)
+#define	CH_ICSNTAG_MASK			INT64_C(0x000007ffffffe000)
+#define	CH_ICSNTAG_TO_PA(tag)		(((tag) << 5) & CH_ICSNTAG_MASK)
+#define	CH_ICLOWER_VALID		INT64_C(0x0004000000000000)
+#define	CH_ICUPPER_VALID		INT64_C(0x0004000000000000)
+#define	CH_ICLOWER_TO_VPRED(lower)	(((lower) >> 46) & 0xf)
+#define	CH_ICUPPER_TO_VPRED(upper)	(((upper) >> 46) & 0xf)
+#if defined(CHEETAH_PLUS)
+#define	CH_ICTAG_MATCH(icp, pa)		(((icp->ic_lower | icp->ic_upper) & \
+					    CH_ICLOWER_VALID) && \
+					    CH_ICPATAG_MATCH(icp->ic_patag, pa))
+#define	PN_ICUTAG_TO_VA(tag)		((tag >> 24) & PN_ICUTAG_MASK)
+#else	/* CHEETAH_PLUS */
+#define	CH_ICTAG_MATCH(icp, pa)		((icp->ic_lower & CH_ICLOWER_VALID) &&\
+					    CH_ICPATAG_MATCH(icp->ic_patag, pa))
+#define	PN_ICUTAG_TO_VA(tag)		0
+#endif	/* CHEETAH_PLUS */
+
+#define	CH_IC_DATA_REG_SIZE		64
+#define	PN_IC_DATA_REG_SIZE		128
+#if defined(CHEETAH_PLUS) || defined(JALAPENO) || defined(SERRANO)
+#define	CHP_IC_IDX(icp)			((icp->ic_idx & 0x3fc0) >> 6)
+#define	PN_IC_IDX(icp)			((icp->ic_idx & 0x7f80) >> 7)
+#define	CHP_ICPATAG_MASK		INT64_C(0x000003ffffffe000)
+#define	CHP_ICSNTAG_MASK		INT64_C(0x000003ffffffe000)
+#define	CHP_ICUTAG_MASK			INT64_C(0x00000000001fe000)
+#define	PN_ICUTAG_MASK			INT64_C(0x00000000003fc000)
+#define	CHP_ICWAY_MASK			INT64_C(0x0000000000003fe0)
+#define	CHP_ICPATAG_TO_PA(tag)		((tag << 5) & CHP_ICPATAG_MASK)
+#define	CHP_ICSNTAG_TO_PA(tag)		((tag << 5) & CHP_ICSNTAG_MASK)
+#define	CHP_ICUTAG_TO_VA(tag)		((tag >> 25) & CHP_ICUTAG_MASK)
+#define	CHP_ICPATAG_PARMASK		INT64_C(0x0000003fffffff00)
+#define	CHP_ICSNTAG_PARMASK		INT64_C(0x0000003fffffff00)
+
+/*
+ * Cheetah+ Icache data parity masks, see Cheetah+ Delta PRM 7.3
+ * PC-relative instructions have different bits protected by parity.
+ * Predecode bit 7 is not parity protected and indicates if the instruction
+ * is PC-relative or not.
+ */
+#define	CH_ICDATA_PRED_ISPCREL		INT64_C(0x0000008000000000)
+#define	CHP_ICDATA_PCREL_PARMASK	INT64_C(0x0000039ffffff800)
+#define	CHP_ICDATA_NPCREL_PARMASK	INT64_C(0x000003bfffffffff)
+#define	PN_ICDATA_PARITY_BIT_MASK	INT64_C(0x40000000000)
+#define	CHP_ICTAG_PARITY(tag)		(tag & CHP_IC_TAG)
+#define	CHP_ICSNTAG_PARITY(tag)		(tag & CHP_IC_SNTAG)
+#define	CHP_IC_TAG			0x1
+#define	CHP_IC_SNTAG			0x2
+#endif	/* CHEETAH_PLUS || JALAPENO || SERRANO */
+#if defined(CHEETAH_PLUS)
+#define	PN_IPB_TAG_ADDR_LINESIZE	0x40
+#define	PN_IPB_TAG_ADDR_MAX		0x3c0
+#endif	/* CHEETAH_PLUS */
+
+/*
+ * Macros for Pcache diagnostic accesses.
+ */
+#define	CH_PC_WAY_MASK			0x600
+#define	CH_PC_WAY_SHIFT			9
+#define	CH_PCIDX_TO_WAY(idx)		(((idx) & CH_PC_WAY_MASK) >> \
+						CH_PC_WAY_SHIFT)
+#define	CH_PC_DATA_REG_SIZE		64
+#define	CH_PCACHE_NWAY			4
+#define	PN_PC_PARITY_SHIFT		50
+#define	PN_PC_PARITY_MASK		0xff
+#define	PN_PC_PARITY_BITS(status)	\
+	(((status) >> PN_PC_PARITY_SHIFT) & PN_PC_PARITY_MASK)
+#define	CH_PC_IDX_ADR(pcp)		((pcp->pc_idx & 0x1c0) >> 6)
+#define	CH_PCTAG_ADDR_SHIFT		6
+#define	CH_PC_PA_MASK			0x7ffffffffc0
+#define	CH_PCTAG_TO_VA(tag)		((tag) << CH_PCTAG_ADDR_SHIFT)
+#define	CH_PCSTAG_TO_PA(tag)		(((tag) << CH_PCTAG_ADDR_SHIFT) & \
+					    CH_PC_PA_MASK)
+#define	CH_PCTAG_BNK0_VALID_MASK	0x2000000000000000
+#define	CH_PCTAG_BNK1_VALID_MASK	0x1000000000000000
+#define	CH_PCTAG_BNK0_INVALID(tag)	(((tag) & CH_PCTAG_BNK0_VALID_MASK) == \
+					    0)
+#define	CH_PCTAG_BNK1_INVALID(tag)	(((tag) & CH_PCTAG_BNK1_VALID_MASK) == \
+					    0)
+
+/*
+ * CPU Log Out Structure parameters.
+ * This structure is filled in by the Error Trap handlers and captures the
+ * Ecache/Dcache/Icache line(s) associated with the AFAR.
+ * For Cheetah Phase II, this structure is filled in at the TL=0 code.  For
+ * Cheetah Phase III, this will be filled in at the trap handlers.
+ */
+
+/*
+ * We use this to mark the LOGOUT structure as invalid.  Note that
+ * this cannot be a valid AFAR, as AFAR bits outside of [41:5] should always
+ * be zero.
+ */
+#define	LOGOUT_INVALID_U32	0xecc1ecc1
+#define	LOGOUT_INVALID_L32	0xecc1ecc1
+#define	LOGOUT_INVALID		UINT64_C(0xecc1ecc1ecc1ecc1)
+
+/*
+ * Max number of TLs to support for Fast ECC or Cache Parity Errors
+ * at TL>0.  Traps are OK from TL=1-2, at TL>=3, we will Red Mode.
+ */
+#define	CH_ERR_TL1_TLMAX	2
+
+/*
+ * Software traps used by TL>0 handlers.
+ */
+#define	SWTRAP_0		0	/* Used by Fast ECC */
+#define	SWTRAP_1		1	/* Used by Dcache Parity */
+#define	SWTRAP_2		2	/* Used by Icache Parity */
+
+/*
+ * Bit mask defines for various Cheetah Error conditions.
+ */
+#define	CH_ERR_FECC	0x01	/* Data/Event is Fast ECC */
+#define	CH_ERR_IPE	0x02	/* Data/Event is Icache Parity Error */
+#define	CH_ERR_DPE	0x04	/* Data/Event is Dcache Parity Error */
+#define	CH_ERR_PANIC	0x08	/* Fatal error in TL>0 handler */
+#define	CH_ERR_TL	0x10	/* Error occured at TL>0 */
+#define	CH_ERR_ME_SHIFT	   8	/* If multiple errors, shift left newest */
+#define	CH_ERR_ME_FLAGS(x)	((x) >> CH_ERR_ME_SHIFT)
+
+/*
+ * Defines for Bit8 (CH_ERR_TSTATE_IC_ON) and Bit9 (CH_ERR_TSTATE_DC_ON)
+ * in %tstate, which is used to remember D$/I$ state on Fast ECC handler
+ * at TL>0.  Note that DCU_IC=0x1, DCU_DC=0x2.
+ */
+#define	CH_ERR_G2_TO_TSTATE_SHFT	10
+#define	CH_ERR_DCU_TO_TSTATE_SHFT	8
+#define	CH_ERR_TSTATE_IC_ON	(DCU_IC << CH_ERR_DCU_TO_TSTATE_SHFT)
+#define	CH_ERR_TSTATE_DC_ON	(DCU_DC << CH_ERR_DCU_TO_TSTATE_SHFT)
+
+/*
+ * Multiple offset TL>0 handler structure elements
+ */
+#define	CH_ERR_TL1_DATA		(CH_ERR_TL1_LOGOUT + CH_CLO_DATA)
+#define	CH_ERR_TL1_SDW_DATA	(CH_ERR_TL1_LOGOUT + CH_CLO_SDW_DATA)
+#define	CH_ERR_TL1_NEST_CNT	(CH_ERR_TL1_LOGOUT + CH_CLO_NEST_CNT)
+#define	CH_ERR_TL1_AFSR		(CH_ERR_TL1_DATA + CH_CHD_AFSR)
+#define	CH_ERR_TL1_SDW_AFSR	(CH_ERR_TL1_SDW_DATA + CH_CHD_AFSR)
+#define	CH_ERR_TL1_SDW_AFSR_EXT	(CH_ERR_TL1_SDW_DATA + CH_CHD_AFSR_EXT)
+
+/*
+ * Interval for deferred CEEN reenable
+ */
+#define	CPU_CEEN_DELAY_SECS		6
+
+/*
+ * flags for flt_trapped_ce variable
+ */
+#define	CE_CEEN_DEFER		0x1	/* no CEEN reenable in trap handler */
+#define	CE_CEEN_NODEFER		0x2	/* reenable CEEN in handler */
+#define	CE_CEEN_TIMEOUT		0x4	/* CE caught by timeout */
+#define	CE_CEEN_TRAPPED		0x8	/* CE caught by trap */
+
+/*
+ * default value for cpu_ce_not_deferred
+ */
+#if defined(JALAPENO) || defined(SERRANO)
+#define	CPU_CE_NOT_DEFERRED	(C_AFSR_CECC_ERRS & \
+		~(C_AFSR_CE | C_AFSR_FRC | C_AFSR_RCE | C_AFSR_EMC))
+#else /* JALAPENO || SERRANO */
+#define	CPU_CE_NOT_DEFERRED		C_AFSR_CECC_ERRS & \
+					    ~(C_AFSR_CE | C_AFSR_EMC)
+#endif /* JALAPENO || SERRANO */
+
+#define	CPU_CE_NOT_DEFERRED_EXT		C_AFSR_EXT_CECC_ERRS
+
+#if defined(CHEETAH_PLUS)
+
+/*
+ * VA for primary and shadow AFSR/AFAR/AFSR_EXT registers
+ */
+#define	ASI_SHADOW_REG_VA	0x8
+#define	ASI_AFSR_EXT_VA		0x10
+#define	ASI_SHADOW_AFSR_EXT_VA	0x18
+
+/*
+ * Bitmask for keeping track of core parking in ECC error handlers.
+ * We share a register that also saves the DCUCR value so we use
+ * one of the reserved bit positions of the DCUCR register to keep
+ * track of whether or not we have parked our sibling core.
+ */
+#define	PN_PARKED_OTHER_CORE	0x20
+#define	PN_BOTH_CORES_RUNNING	0x3
+
+/*
+ * Panther EMU Activity Status Register Bits.
+ */
+#define	ASI_EMU_ACT_STATUS_VA	0x18
+#define	MCU_ACT_STATUS		INT64_C(0x0000000000000001)
+#define	SIU_ACT_STATUS		INT64_C(0x0000000000000002)
+#endif	/* CHEETAH_PLUS */
+
+#define	ASI_CESR_ID_VA		0x40    /* ASI_CESRD_ID per-core registers */
+
+#define	ASR_DISPATCH_CONTROL		%asr18
+#define	ASR_DISPATCH_CONTROL_BPE	0x20
+
+/*
+ * Max number of E$ sets logged in ch_diag_data structure
+ */
+#define	CHD_EC_DATA_SETS	4	/* max 4 sets of E$ data */
+
+/*
+ * Definitions for Panther TLB parity handling.
+ */
+#define	PN_ITLB_NWAYS		2
+#define	PN_NUM_512_ITLBS	1
+#define	PN_DTLB_NWAYS		2
+#define	PN_NUM_512_DTLBS	2
+#define	PN_SFSR_PARITY_SHIFT	12
+#define	PN_ITLB_PGSZ_SHIFT	22
+#define	PN_ITLB_PGSZ_MASK	(7 << PN_ITLB_PGSZ_SHIFT)
+#define	PN_DTLB_PGSZ0_SHIFT	16
+#define	PN_DTLB_PGSZ0_MASK	(7 << PN_DTLB_PGSZ0_SHIFT)
+#define	PN_DTLB_PGSZ1_SHIFT	19
+#define	PN_DTLB_PGSZ1_MASK	(7 << PN_DTLB_PGSZ1_SHIFT)
+#define	PN_DTLB_PGSZ_MASK	(PN_DTLB_PGSZ1_MASK | PN_DTLB_PGSZ0_MASK)
+#define	PN_DTLB_T512_0		(2 << 16)
+#define	PN_DTLB_T512_1		(3 << 16)
+#define	PN_TLO_INFO_IMMU_SHIFT	14
+#define	PN_TLO_INFO_IMMU	(1 << PN_TLO_INFO_IMMU_SHIFT)
+#define	PN_TLO_INFO_TL1_SHIFT	13
+#define	PN_TLO_INFO_TL1		(1 << PN_TLO_INFO_TL1_SHIFT)
+#define	PN_ITLB_T512		(2 << 16)
+#define	PN_TLB_ACC_IDX_SHIFT	3
+#define	PN_TLB_ACC_WAY_BIT	(1 << 11)
+#define	PN_TLB_DIAGACC_OFFSET	0x40000	/* Diag Acc ASI VA offset */
+/*
+ * tag parity = XOR(Size[2:0],Global,VA[63:21],Context[12:0])
+ * which requires looking at both the tag and the data.
+ */
+#define	PN_TLB_TAG_PARITY_TAG_MASK	0xffffffffffe01fff
+#define	PN_TLB_TAG_PARITY_DATA_MASK	0x6001400000000001
+/* data parity = XOR(NFO,IE,PA[42:13],CP,CV,E,P,W) */
+#define	PN_TLB_DATA_PARITY_DATA_MASK	0x180087ffffffe03e
+
+#ifdef _KERNEL
+
+#ifndef	_ASM
+
+#include <sys/kstat.h>
+
+/*
+ * One Ecache data element, 32 bytes of data, 8 bytes of ECC.
+ * See Cheetah PRM 10.7.2.
+ */
+typedef struct ec_data_elm {
+	uint64_t ec_d8[CH_ECACHE_STGREG_NUM];
+	uint64_t ec_eccd;	/* EC_data_ECC field */
+} ec_data_elm_t;
+
+/*
+ * L2 and L3 cache data captured by cpu log out code.
+ * See Cheetah PRM 10.7.4.
+ */
+typedef struct ch_ec_data {
+	uint64_t ec_logflag;	/* Flag indicates if data was logged */
+	uint64_t ec_idx;	/* Ecache index */
+	uint64_t ec_way;	/* Ecache way */
+	uint64_t ec_tag;	/* Ecache Tag */
+	uint64_t ec_tag_ecc;	/* Ecache Tag ECC (Cheetah+ only) */
+	ec_data_elm_t ec_data[CH_ECACHE_SUBBLK_SIZE/CH_ECACHE_STGREG_SIZE];
+} ch_ec_data_t;
+
+/*
+ * Dcache data captured by cpu log out code and get_dcache_dtag.
+ * See Cheetah PRM 10.6.[1-4].
+ */
+typedef struct ch_dc_data {
+	uint64_t dc_logflag;	/* Flag indicates if data was logged */
+	uint64_t dc_idx;	/* Dcache index */
+	uint64_t dc_way;	/* Dcache way */
+	uint64_t dc_tag;	/* Tag/Valid Fields */
+	uint64_t dc_utag;	/* Microtag */
+	uint64_t dc_sntag;	/* Snoop Tag */
+	uint64_t dc_data[CH_DC_DATA_REG_SIZE/sizeof (uint64_t)]; /* Data */
+	uint64_t dc_pn_data_parity;	/* Data parity bits for Panther */
+} ch_dc_data_t;
+
+/*
+ * Icache data captured by cpu log out code and get_icache_dtag.
+ * See Cheetah PRM 10.4.[1-3].
+ */
+typedef struct ch_ic_data {
+	uint64_t ic_logflag;	/* Flag indicates if data was logged */
+	uint64_t ic_idx;	/* Icache index */
+	uint64_t ic_way;	/* Icache way */
+	uint64_t ic_patag;	/* Physical address tag */
+	uint64_t ic_utag;	/* Microtag */
+	uint64_t ic_upper;	/* Upper valid/predict tag */
+	uint64_t ic_lower;	/* Lower valid/predict tag */
+	uint64_t ic_sntag;	/* Snoop Tag */
+	uint64_t ic_data[PN_IC_DATA_REG_SIZE/sizeof (uint64_t)]; /* Data */
+} ch_ic_data_t;
+
+/*
+ * Pcache data captured by get_pcache_dtag
+ */
+typedef struct ch_pc_data {
+	uint64_t pc_logflag;	/* Flag indicates if data was logged */
+	uint64_t pc_idx;	/* Pcache index */
+	uint64_t pc_way;	/* Pcache way */
+	uint64_t pc_status;	/* Pcache status data */
+	uint64_t pc_tag;	/* Tag/Valid Fields */
+	uint64_t pc_sntag;	/* Snoop Tag */
+	uint64_t pc_data[CH_PC_DATA_REG_SIZE/sizeof (uint64_t)]; /* Data */
+} ch_pc_data_t;
+
+/*
+ * CPU Error State
+ */
+typedef struct ch_cpu_errors {
+	uint64_t afsr;		/* AFSR */
+	uint64_t afar;		/* AFAR */
+	/*
+	 * The following registers don't exist on cheetah
+	 */
+	uint64_t shadow_afsr;	/* Shadow AFSR */
+	uint64_t shadow_afar;	/* Shadow AFAR */
+	uint64_t afsr_ext;	/* AFSR1_EXT */
+	uint64_t shadow_afsr_ext;	/* AFSR2_EXT */
+	uint64_t afar2;		/* AFAR2 - Serrano only */
+} ch_cpu_errors_t;
+
+/*
+ * CPU logout structures.
+ * NOTE: These structures should be the same for Cheetah, Cheetah+,
+ *	 Jaguar, Panther, and Jalapeno since the assembler code relies
+ *	 on one set of offsets. Panther is the only processor that
+ *	 uses the chd_l2_data field since it has both L3 and L2 caches.
+ */
+typedef struct ch_diag_data {
+	uint64_t chd_afar;				/* AFAR */
+	uint64_t chd_afsr;				/* AFSR */
+	uint64_t chd_afsr_ext;				/* AFSR_EXT */
+	uint64_t chd_afar2;			/* AFAR2 - Serrano only */
+	ch_ec_data_t chd_ec_data[CHD_EC_DATA_SETS];	/* Ecache data */
+	ch_ec_data_t chd_l2_data[PN_L2_NWAYS];		/* L2 cache data */
+	ch_dc_data_t chd_dc_data;			/* Dcache data */
+	ch_ic_data_t chd_ic_data;			/* Icache data */
+} ch_diag_data_t;
+
+
+/*
+ * Top level CPU logout structure.
+ * clo_flags is used to hold information such as trap type, trap level,
+ * CEEN value, etc that is needed by the individual trap handlers. Not
+ * all fields in this flag are used by all trap handlers but when they
+ * are used, here's how they are laid out:
+ *
+ * |-------------------------------------------------------|
+ * |        | trap type | trap level |  |UCEEN| |NCEEN|CEEN|
+ * |-------------------------------------------------------|
+ *  63       19       12 11         8      3   2   1    0
+ *
+ * Note that the *CEEN bits correspond exactly to the same bit positions
+ * that are used in the error enable register.
+ */
+typedef struct ch_cpu_logout {
+	uint64_t clo_flags;		/* Information about this trap */
+	uint64_t clo_nest_cnt;		/* To force an upper bound */
+	ch_diag_data_t clo_data;	/* Diag data for primary AFAR */
+	ch_diag_data_t clo_sdw_data;	/* Diag data for shadow AFAR */
+} ch_cpu_logout_t;
+
+typedef struct ch_tte_entry {
+	uint64_t ch_tte_tag;
+	uint64_t ch_tte_data;
+} ch_tte_entry_t;
+
+/*
+ * Top level CPU logout structure for TLB parity errors.
+ *
+ * tlo_logflag  - Flag indicates if data was logged
+ * tlo_info	- Used to keep track of a number of values:
+ *   itlb pgsz	  - Page size of the VA whose lookup in the ITLB caused
+ *		    the exception (from ASI_IMMU_TAG_ACCESS_EXT.)
+ *   dtlb pgsz1	  - Page size of the VA whose lookup in the DTLB T512_1
+ *		    caused the exception (from ASI_DMMU_TAG_ACCESS_EXT.).
+ *   dtlb pgsz0	  - Page size of the VA whose lookup in the DTLB T512_0
+ *		    caused the exception (from ASI_DMMU_TAG_ACCESS_EXT.).
+ *   immu	  - Trap is the result of an ITLB exception if immu == 1.
+ *		    Otherwise, for DTLB exceptions immu == 0.
+ *   tl1	  - Set to 1 if the exception occured at TL>0.
+ *   context	  - Context of the VA whose lookup in the TLB caused the
+ *		    exception (from ASI_[I|D]MMU_TAG_ACCESS.)
+ * |---------------------------------------------------------------------|
+ * |...| itlb pgsz  | dtlb pgsz1 | dtlb pgsz0 |...| immu | tl1 | context |
+ * |---------------------------------------------------------------------|
+ *      24        22 21        19 18        16       14    13   12      0
+ *
+ * tlo_addr	- VA that cause the MMU exception trap.
+ * tlo_pc	- PC where the exception occured.
+ * tlo_itlb_tte	- TTEs that were in the ITLB after the trap at the index
+ *		  specific to the VA and page size in question.
+ * tlo_dtlb_tte	- TTEs that were in the DTLB after the trap at the index
+ *		  specific to the VA and page size in question.
+ */
+typedef struct pn_tlb_logout {
+	uint64_t tlo_logflag;
+	uint64_t tlo_info;
+	uint64_t tlo_addr;
+	uint64_t tlo_pc;
+	ch_tte_entry_t tlo_itlb_tte[PN_ITLB_NWAYS * PN_NUM_512_ITLBS];
+	ch_tte_entry_t tlo_dtlb_tte[PN_DTLB_NWAYS * PN_NUM_512_DTLBS];
+} pn_tlb_logout_t;
+
+#if defined(CPU_IMP_L1_CACHE_PARITY)
+/*
+ * Parity error logging structure.
+ */
+typedef union ch_l1_parity_log {
+	struct {
+		int cpl_way;				/* Faulty line way */
+		int cpl_off;				/* Faulty line offset */
+		int cpl_tag;				/* Faulty tags list */
+		int cpl_lcnt;				/* Faulty cache lines */
+		ch_dc_data_t cpl_dc[CH_DCACHE_NWAY];	/* D$ data nWays */
+		ch_pc_data_t cpl_pc[CH_PCACHE_NWAY];	/* P$ data nWays */
+		int cpl_cache;				/* error in D$ or P$? */
+	} dpe;	/* D$ parity error */
+	struct {
+		int cpl_way;				/* Faulty line way */
+		int cpl_off;				/* Faulty line offset */
+		int cpl_tag;				/* Faulty tags list */
+		int cpl_lcnt;				/* Faulty cache lines */
+		ch_ic_data_t cpl_ic[CH_ICACHE_NWAY];	/* I$ data nWays */
+	} ipe;	/* I$ parity error */
+} ch_l1_parity_log_t;
+
+#endif	/* CPU_IMP_L1_CACHE_PARITY */
+
+/*
+ * Error at TL>0 CPU logout data.
+ *   Needs some extra space to save %g registers and miscellaneous info.
+ */
+typedef struct ch_err_tl1_data {
+	uint64_t ch_err_tl1_g1;		/* Saved %g1 */
+	uint64_t ch_err_tl1_g2;		/* Saved %g2 */
+	uint64_t ch_err_tl1_g3;		/* Saved %g3 */
+	uint64_t ch_err_tl1_g4;		/* Saved %g4 */
+	uint64_t ch_err_tl1_g5;		/* Saved %g5 */
+	uint64_t ch_err_tl1_g6;		/* Saved %g6 */
+	uint64_t ch_err_tl1_g7;		/* Saved %g7 */
+	uint64_t ch_err_tl1_tpc;	/* Trap PC */
+	uint64_t ch_err_tl1_flags;	/* miscellaneous flags */
+	uint64_t ch_err_tl1_tmp;	/* some handlers may use as tmp */
+	ch_cpu_logout_t ch_err_tl1_logout;	/* logout */
+} ch_err_tl1_data_t;
+
+/* Indices into chsm_outstanding and friends */
+#define	CACHE_SCRUBBER_INFO_E	0
+#define	CACHE_SCRUBBER_INFO_D	1
+#define	CACHE_SCRUBBER_INFO_I	2
+
+/* We define 3 scrubbers: E$, D$, and I$ */
+#define	CACHE_SCRUBBER_COUNT	3
+
+/*
+ * The ch_scrub_misc structure contains miscellaneous bookkeeping
+ * items for scrubbing the I$, D$, and E$.
+ *
+ * For a description of the use of chsm_core_state and why it's not needed
+ * on Jaguar, see the comment above cpu_scrub_cpu_setup() in us3_cheetahplus.c.
+ */
+typedef struct ch_scrub_misc {
+	uint32_t	chsm_outstanding[CACHE_SCRUBBER_COUNT];
+						/* outstanding requests */
+	int		chsm_flush_index[CACHE_SCRUBBER_COUNT];
+						/* next line to flush */
+	int		chsm_enable[CACHE_SCRUBBER_COUNT];
+				/* is this scrubber enabled on this core? */
+	int		chsm_ecache_nlines;	/* no. of E$ lines */
+	int		chsm_ecache_busy;	/* keeps track if cpu busy */
+	int		chsm_icache_nlines;	/* no. of I$ lines */
+	int		chsm_core_state;	/* which core the scrubber is */
+						/* running on (Panther only) */
+} ch_scrub_misc_t;
+
+/*
+ * Cheetah module private data structure.  One of these is allocated for
+ * each valid cpu at setup time and is pointed to by the machcpu
+ * "cpu_private" pointer.  For Cheetah, we have the miscellaneous scrubber
+ * variables and cpu log out structures for Fast ECC traps at TL=0,
+ * Disrupting (correctable) traps and Deferred (asynchronous) traps.  For
+ * Disrupting traps only one log out structure is needed because we cannot
+ * get a TL>0 disrupting trap since it obeys IE.  For Deferred traps we
+ * cannot get a TL>0 because we turn off NCEEN during log out capture.  E$
+ * set size (E$ size / nways) is saved here to avoid repeated calculations.
+ * NB: The ch_err_tl1_data_t structures cannot cross a page boundary
+ *      because we use physical addresses to access them.  We ensure this
+ *      by allocating them near the front of cheetah_private_t, which is
+ *      aligned on PAGESIZE (8192) via kmem_cache_create, and by ASSERTing
+ *	sizeof (chpr_tl1_err_data) <= CH_ECACHE_MAX_LSIZE in the
+ *	cpu_init_private routines.
+ * NB:  chpr_icache_size and chpr_icache_linesize need to be at the front
+ *	of cheetah_private_t because putting them after chpr_tl1_err_data
+ *	would make their offsets > 4195.
+ */
+typedef struct cheetah_private {
+	int			chpr_icache_size;
+	int			chpr_icache_linesize;
+	ch_err_tl1_data_t	chpr_tl1_err_data[CH_ERR_TL1_TLMAX];
+	ch_scrub_misc_t		chpr_scrub_misc;
+	int			chpr_ec_set_size;
+	ch_cpu_logout_t		chpr_fecctl0_logout;
+	ch_cpu_logout_t		chpr_cecc_logout;
+	ch_cpu_logout_t		chpr_async_logout;
+	pn_tlb_logout_t		chpr_tlb_logout;
+	uint64_t		chpr_fpras_timestamp[FPRAS_NCOPYOPS];
+	hrtime_t		chpr_ceptnr_seltime;
+	int			chpr_ceptnr_id;
+} cheetah_private_t;
+
+#endif /* _ASM */
+
+#endif /* _KERNEL */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_CHEETAHREGS_H */
diff --git a/usr/src/uts/sun4u/sys/cpr_impl.h b/usr/src/uts/sun4u/sys/cpr_impl.h
new file mode 100644
index 0000000000..37cb2b50fb
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/cpr_impl.h
@@ -0,0 +1,182 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_CPR_IMPL_H
+#define	_SYS_CPR_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+#ifndef _ASM
+
+#include <sys/processor.h>
+#include <sys/machparam.h>
+#include <sys/obpdefs.h>
+#include <sys/vnode.h>
+#include <sys/pte.h>
+
+/*
+ * This file contains machine dependent information for CPR
+ */
+#define	CPR_MACHTYPE_4U		0x3475		/* '4u' */
+
+/*
+ * Information about the pages allocated via prom_retain().
+ * Increase the number of CPR_PROM_RETAIN_CNT if more
+ * prom_retain() are called.
+ */
+#define	CPR_PROM_RETAIN_CNT	1
+#define	CPR_PANICBUF		0	/* prom_retain() for panicbuf */
+
+
+/*
+ * For 2.7 and later releases, sun4u cprboot is an ELF64 binary and must
+ * handle both ILP32 and LP64 kernels; while long and ptr sizes are fixed
+ * at 64-bits for cprboot these sizes are mixed between ILP32/LP64 kernels.
+ * To simplify handling of statefile data, we define fixed-size types for
+ * all sun4u kernels.
+ */
+typedef uint64_t cpr_ptr;
+typedef uint64_t cpr_ext;
+
+struct cpr_map_info {
+	cpr_ptr	virt;
+	cpr_ext	phys;
+	uint_t	size;
+};
+
+
+#define	CPR_MAX_TLB 16
+
+struct sun4u_tlb {
+	tte_t	tte;			/* tte data */
+	cpr_ptr va_tag;			/* virt tag */
+	int	index;			/* tlb index */
+	int	tmp;			/* clear during resume */
+};
+
+typedef struct sun4u_tlb sutlb_t;
+
+
+/*
+ * processor info
+ */
+struct sun4u_cpu_info {
+	dnode_t node;
+	processorid_t cpu_id;
+};
+
+
+/*
+ * This structure defines the fixed-length machine dependent data for
+ * sun4u ILP32 and LP64 systems.  It is followed in the state file by
+ * a variable length section of null-terminated prom forth words:
+ *
+ *    cpr_obp_tte_str	for translating kernel mappings, unix-tte
+ *
+ * The total length (fixed plus variable) of the machine-dependent
+ * section is stored in cpr_machdep_desc.md_size
+ *
+ * WARNING: make sure all CPR_MD_* below match this structure
+ */
+struct cpr_sun4u_machdep {
+	uint32_t ksb;			/* 0x00: kernel stack bias */
+	uint16_t kpstate;		/* 0x04: kernel pstate */
+	uint16_t kwstate;		/* 0x06: kernel wstate */
+	cpr_ptr thrp;			/* 0x08: current thread ptr */
+	cpr_ptr func;			/* 0x10: jumpback virt text addr */
+	cpr_ext qsav_pc;		/* 0x18: qsav pc */
+	cpr_ext qsav_sp;		/* 0x20: qsav sp */
+	int	mmu_ctx_pri;		/* 0x28: primary context */
+	int	mmu_ctx_sec;		/* 0x2c: secondary context */
+	cpr_ptr	tmp_stack;		/* 0x30: base of data page */
+	cpr_ext tmp_stacksize;		/* 0x38: leading area of data page */
+	int	test_mode;		/* 0x40 */
+	int	pad;			/* 0x44 */
+	sutlb_t	dtte[CPR_MAX_TLB];	/* 0x48 */
+	sutlb_t	itte[CPR_MAX_TLB];	/* 0x1c8 */
+	struct	sun4u_cpu_info sci[NCPU]; /* 0x348 */
+};
+typedef struct cpr_sun4u_machdep csu_md_t;
+
+#endif /* _ASM */
+
+
+/*
+ * XXX - these should be generated by a genassym,
+ * but that doesn't work well for shared psm/kernel use
+ */
+#define	CPR_MD_KSB		0x00
+#define	CPR_MD_KPSTATE		0x04
+#define	CPR_MD_KWSTATE		0x06
+#define	CPR_MD_THRP		0x08
+#define	CPR_MD_FUNC		0x10
+#define	CPR_MD_QSAV_PC		0x18
+#define	CPR_MD_QSAV_SP		0x20
+#define	CPR_MD_PRI		0x28
+#define	CPR_MD_SEC		0x2c
+
+
+#ifndef _ASM
+
+#define	CPRBOOT		"-F cprboot"
+
+#define	PN_TO_ADDR(pn)  ((u_longlong_t)(pn) << MMU_PAGESHIFT)
+#define	ADDR_TO_PN(pa)	((pa) >> MMU_PAGESHIFT)
+
+#define	prom_map_plat(addr, pa, size) \
+	if (prom_map(addr, pa, size) == 0) { \
+		errp("PROM_MAP failed: paddr=0x%lx\n", pa); \
+		return (-1); \
+	}
+
+typedef	u_longlong_t	physaddr_t;
+
+extern void i_cpr_machdep_setup(void);
+extern void i_cpr_save_machdep_info(void);
+extern void i_cpr_enable_intr(void);
+extern void i_cpr_set_tbr(void);
+extern void i_cpr_stop_intr(void);
+extern void i_cpr_handle_xc(int);
+extern void i_cpr_resume_setup(void *, csu_md_t *);
+extern int i_cpr_write_machdep(vnode_t *);
+extern int i_cpr_prom_pages(int);
+extern int i_cpr_reuseinit(void);
+extern int i_cpr_reusefini(void);
+extern int i_cpr_check_cprinfo(void);
+extern int i_cpr_reusable_supported(void);
+
+#endif /* _ASM */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_CPR_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/cpu_module.h b/usr/src/uts/sun4u/sys/cpu_module.h
new file mode 100644
index 0000000000..36600011eb
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/cpu_module.h
@@ -0,0 +1,245 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_CPU_MODULE_H
+#define	_SYS_CPU_MODULE_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/pte.h>
+#include <sys/async.h>
+#include <sys/x_call.h>
+#include <sys/conf.h>
+#include <sys/obpdefs.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+#ifdef _KERNEL
+
+/*
+ * The are functions that are expected of the cpu modules.
+ */
+
+extern struct module_ops *moduleops;
+
+struct kdi;
+
+/*
+ * module initialization
+ */
+void	cpu_setup(void);
+void	cpu_kdi_init(struct kdi *);
+
+/*
+ * set CPU implementation details
+ *
+ * mmu_init_mmu_page_sizes changes the mmu_page_sizes variable from
+ *	The default 4 page sizes to 6 page sizes for Panther-only domains,
+ *	and is called from fillsysinfo.c:check_cpus_set at early bootup time.
+ */
+void	cpu_fiximp(dnode_t dnode);
+#pragma weak mmu_init_mmu_page_sizes
+int	mmu_init_mmu_page_sizes(int cinfo);
+
+/*
+ * virtual demap flushes (tlbs & virtual tag caches)
+ */
+void	vtag_flushpage(caddr_t addr, uint_t ctx);
+void	vtag_flushctx(uint_t ctx);
+void	vtag_flushall(void);
+void	vtag_flushpage_tl1(uint64_t addr, uint64_t ctx);
+void	vtag_flush_pgcnt_tl1(uint64_t addr, uint64_t ctx_pgcnt);
+void	vtag_flushctx_tl1(uint64_t ctx, uint64_t dummy);
+void	vtag_flushall_tl1(uint64_t dummy1, uint64_t dummy2);
+
+/*
+ * virtual alias flushes (virtual address caches)
+ */
+void	vac_flushpage(pfn_t pf, int color);
+void	vac_flushpage_tl1(uint64_t pf, uint64_t color);
+void	vac_flushcolor(int color, pfn_t pf);
+void	vac_flushcolor_tl1(uint64_t color, uint64_t dummy);
+
+/*
+ * sending x-calls
+ */
+void	init_mondo(xcfunc_t *func, uint64_t arg1, uint64_t arg2);
+void	send_one_mondo(int cpuid);
+#ifdef _MACHDEP
+void	send_mondo_set(cpuset_t set);
+#endif
+
+/*
+ * Calculate, set optimal dtlb pagesize, for ISM and mpss, to support
+ * cpus with non-fully-associative dtlbs.
+ */
+extern uchar_t *ctx_pgsz_array;
+
+/*
+ * flush instruction cache if needed
+ */
+void	flush_instr_mem(caddr_t addr, size_t len);
+
+/*
+ * flush instruction and data caches
+ */
+void	kdi_flush_caches(void);
+
+/*
+ * take pending fp traps if fpq present
+ * this function is also defined in fpusystm.h
+ */
+void	syncfpu(void);
+
+/*
+ * Cpu-specific error and ecache handling routines
+ */
+void	ce_err(void);
+void	ce_err_tl1(void);
+void	async_err(void);
+void	cpu_flush_ecache(void);
+void	cpu_disable_errors(void);
+/* It could be removed later if prom enables errors */
+void	cpu_enable_errors(void);
+void	cpu_faulted_enter(struct cpu *);
+void	cpu_faulted_exit(struct cpu *);
+void	cpu_ce_count_unum(struct async_flt *ecc, int len, char *unum);
+void	cpu_ce_scrub_mem_err(struct async_flt *, boolean_t);
+void	cpu_ce_log_err(struct async_flt *, errorq_elem_t *);
+void	cpu_ue_log_err(struct async_flt *);
+int	cpu_aflt_size(void);
+void	cpu_async_panic_callb(void);
+void	cpu_check_allcpus(struct async_flt *aflt);
+int	cpu_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp);
+int	cpu_get_mem_unum(int synd_status, ushort_t synd, uint64_t afsr,
+	    uint64_t afar, int cpuid, int flt_in_memory,
+	    ushort_t flt_status, char *buf, int buflen, int *lenp);
+int	cpu_get_mem_unum_aflt(int synd_status, struct async_flt *aflt,
+	    char *buf, int buflen, int *lenp);
+int	cpu_get_mem_name(uint64_t synd, uint64_t *afsr, uint64_t afar,
+	    char *buf, int buflen, int *lenp);
+int	cpu_get_mem_info(uint64_t synd, uint64_t afar,
+	    uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep,
+	    int *segsp, int *banksp, int *mcidp);
+size_t	cpu_get_name_bufsize();
+void	read_ecc_data(struct async_flt *ecc, short verbose, short ce_err);
+/* add clr_datapath to aviod lint warning for ac_test.c temporarily */
+void	clr_datapath(void);
+
+#pragma weak itlb_parity_trap
+void itlb_parity_trap(void);
+
+#pragma weak dtlb_parity_trap
+void dtlb_parity_trap(void);
+
+/*
+ * FMA Protocol and error handling support routines
+ */
+
+void cpu_ereport_post(struct async_flt *);
+void cpu_run_bus_error_handlers(struct async_flt *, int);
+void cpu_errorq_dispatch(char *, void *, size_t, errorq_t *, uint_t);
+
+/*
+ * retrieve information from the specified tlb entry. these functions are
+ * called by "cpr" module
+ */
+void	itlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag);
+void	dtlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag);
+
+/*
+ * this symbol appears as a second label for vtag_flushall
+ * only for cpus that implement DEMAP_ALL_TYPE
+ */
+#pragma	weak demap_all
+
+/*
+ * change cpu speed
+ */
+void	cpu_change_speed(uint64_t divisor, uint64_t arg2);
+
+/*
+ * ecache scrub operations
+ */
+void cpu_init_cache_scrub(void);
+void cpu_idle_ecache_scrub(struct cpu *);
+void cpu_busy_ecache_scrub(struct cpu *);
+
+/*
+ * Cpu private initialize/uninitialize, including ecache scrubber.
+ */
+void	cpu_init_private(struct cpu *);
+void	cpu_uninit_private(struct cpu *);
+
+#pragma weak cpu_mp_init
+void    cpu_mp_init(void);
+
+#pragma weak cpu_feature_init
+void    cpu_feature_init(void);
+
+#pragma weak cpu_error_init
+void	cpu_error_init(int);
+
+/*
+ * clock/tick register operations
+ */
+void	cpu_clearticknpt(void);
+void	cpu_init_tick_freq(void);
+
+/*
+ * stick synchronization
+ */
+void	sticksync_slave(void);
+void	sticksync_master(void);
+
+/*
+ * flags for calling cpu_check_ce
+ */
+#define	SCRUBBER_CEEN_CHECK		0
+#define	TIMEOUT_CEEN_CHECK		1
+
+/*
+ * Check for Correctable Errors that may have occurred
+ * while CEEN was disabled.
+ */
+void cpu_check_ce(int, uint64_t, caddr_t, uint_t);
+
+/* initialize kernel context pgsz codes in DMMU primary context register */
+void mmu_init_kernel_pgsz(struct hat *hat);
+
+/* get large page size for kernel heap */
+size_t mmu_get_kernel_lpsize(size_t value);
+
+#endif /* _KERNEL */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _SYS_CPU_MODULE_H */
diff --git a/usr/src/uts/sun4u/sys/dmfe.h b/usr/src/uts/sun4u/sys/dmfe.h
new file mode 100644
index 0000000000..615a3e23e2
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/dmfe.h
@@ -0,0 +1,392 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_DMFE_H
+#define	_SYS_DMFE_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Chip ID */
+#define	DAVICOM_VENDOR_ID	0x1282
+#define	DEVICE_ID_9100		0x9100
+#define	DEVICE_ID_9132		0x9132
+/* The 9102 and 9102A are distinguished by revision ID */
+#define	DEVICE_ID_9102		0x9102
+#define	DEVICE_ID_9102A		0x9102
+
+/* Streams */
+#define	DMFEHIWAT		32768	/* driver flow control high water */
+#define	DMFELOWAT		4096	/* driver flow control low water */
+#define	DMFEIDNUM		0	/* DMFE Id; zero works */
+
+/* Size/count parameters */
+#define	SROM_SIZE		128
+#define	SETUPBUF_SIZE		192	/* Setup buffer size in bytes */
+#define	MCASTBUF_SIZE		512	/* multicast hash table size in bits */
+#define	HASH_POLY		0x04C11DB6
+#define	HASH_CRC		0xFFFFFFFFU
+#define	SETUPBUF_PHYS		39	/* word offset of station physical */
+					/* address within setup buffer */
+
+
+/*
+ * Tx/Rx descriptor ring entry formats
+ *
+ * These structures are not actually used; they are just here to show
+ * the layout of the descriptor entries used by the DMFE chip hardware
+ * (we do use "sizeof" these structures).  The code uses the #defined
+ * offsets below to access the various members of the descriptors, via
+ * the DDI access functions (remember the DMFE h/w is little-endian).
+ */
+
+struct rx_desc_type {
+	uint32_t	desc0;
+	uint32_t	desc1;
+	uint32_t	buffer1;
+	uint32_t	rd_next;
+};
+
+struct tx_desc_type {
+	uint32_t	desc0;
+	uint32_t	desc1;
+	uint32_t	buffer1;
+	uint32_t	td_next;
+};
+
+/*
+ * Offsets & sizes for tx/rx descriptors, expressed in (d)words
+ */
+#define	DESC0			0
+#define	DESC1			1
+#define	BUFFER1			2
+#define	RD_NEXT			3
+#define	TD_NEXT			3
+#define	DESC_SIZE		4
+
+/*
+ * Receive descriptor description
+ */
+/* desc0 bit definitions */
+#define	RX_OVERFLOW		(1UL<<0)
+#define	RX_CRC			(1UL<<1)
+#define	RX_DRIBBLING		(1UL<<2)
+#define	RX_MII_ERR		(1UL<<3)
+#define	RX_RCV_WD_TO		(1UL<<4)
+#define	RX_FRAME_TYPE		(1UL<<5)
+#define	RX_COLLISION		(1UL<<6)
+#define	RX_FRAME2LONG		(1UL<<7)
+#define	RX_LAST_DESC		(1UL<<8)
+#define	RX_FIRST_DESC		(1UL<<9)
+#define	RX_MULTI_FRAME		(1UL<<10)
+#define	RX_RUNT_FRAME		(1UL<<11)
+#define	RX_LOOP_MODE		(3UL<<12)
+#define	RX_DESC_ERR		(1UL<<14)
+#define	RX_ERR_SUMMARY		(1UL<<15)
+#define	RX_FRAME_LEN		(0x3fffUL<<16)
+#define	RX_FILTER_FAIL		(1UL<<30)
+#define	RX_OWN			(1UL<<31)
+
+/* desc1 bit definitions */
+#define	RX_BUFFER_SIZE		(0x7ff)
+#define	RX_CHAINING		(1UL<<24)
+#define	RX_END_OF_RING		(1UL<<25)
+
+/*
+ * Transmit descriptor description
+ */
+/* desc0 bit definitions */
+#define	TX_DEFERRED		(1UL<<0)
+#define	TX_UNDERFLOW		(1UL<<1)
+#define	TX_LINK_FAIL		(1UL<<2)
+#define	TX_COLL_COUNT		(0xfUL<<3)
+#define	TX_HEARTBEAT_FAIL	(1UL<<7)
+#define	TX_EXCESS_COLL		(1UL<<8)
+#define	TX_LATE_COLL		(1UL<<9)
+#define	TX_NO_CARRIER		(1UL<<10)
+#define	TX_CARRIER_LOSS		(1UL<<11)
+#define	TX_JABBER_TO		(1UL<<14)
+#define	TX_ERR_SUMMARY		(1UL<<15)
+#define	TX_SPARE		(0x7fffUL<<16)
+#define	TX_OWN			(1UL<<31)
+
+/* desc1 bit definitions */
+#define	TX_BUFFER_SIZE1		(0x7ffUL<<0)
+#define	TX_BUFFER_SIZE2		(0x7ffUL<<11)
+#define	TX_FILTER_TYPE0		(1UL<<22)
+#define	TX_DISABLE_PAD		(1UL<<23)
+#define	TX_CHAINING		(1UL<<24)
+#define	TX_END_OF_RING		(1UL<<25)
+#define	TX_CRC_DISABLE		(1UL<<26)
+#define	TX_SETUP_PACKET		(1UL<<27)
+#define	TX_FILTER_TYPE1		(1UL<<28)
+#define	TX_FIRST_DESC		(1UL<<29)
+#define	TX_LAST_DESC		(1UL<<30)
+#define	TX_INT_ON_COMP		(1UL<<31)
+
+
+/* Device-defined PCI config space registers */
+#define	PCI_DMFE_CONF_CFDD	0x40
+#define	CFDD_SNOOZE		(1UL<<30)
+#define	CFDD_SLEEP		(1UL<<31)
+
+
+/* Operating registers in I/O or MEMORY space */
+#define	BUS_MODE_REG		0x00
+#define	TX_POLL_REG		0x08
+#define	RX_POLL_REG		0x10
+#define	RX_BASE_ADDR_REG	0x18
+#define	TX_BASE_ADDR_REG	0x20
+#define	STATUS_REG		0x28
+#define	OPN_MODE_REG		0x30
+#define	INT_MASK_REG		0x38
+#define	MISSED_FRAME_REG	0x40
+#define	ETHER_ROM_REG		0x48
+#define	BOOT_ROM_REG		0x50
+#define	GP_TIMER_REG		0x58
+#define	PHY_STATUS_REG		0x60
+#define	FRAME_ACCESS_REG	0x68
+#define	FRAME_DATA_REG		0x70
+#define	W_J_TIMER_REG		0x78
+
+
+/* Bit descriptions of CSR registers */
+
+/* BUS_MODE_REG, CSR0 */
+#define	SW_RESET		0x00000001
+#define	BURST_SIZE		0		/* unlimited burst length */
+#define	CACHE_ALIGN		(3 << 14)	/* 32 Dwords		*/
+#define	TX_POLL_INTVL		(1 << 17)	/* 200us polling	*/
+#define	READ_MULTIPLE		(1 << 21) 	/* use Memory Read	*/
+						/* Multiple PCI cycles	*/
+
+/* STATUS_REG, CSR5 */
+#define	TX_PKTDONE_INT		0x00000001UL
+#define	TX_STOPPED_INT		0x00000002UL
+#define	TX_ALLDONE_INT		0x00000004UL
+#define	TX_JABBER_INT		0x00000008UL
+#define	TX_RESERVED_INT		0x00000010UL
+#define	TX_UNDERFLOW_INT	0x00000020UL
+
+#define	RX_PKTDONE_INT		0x00000040UL
+#define	RX_UNAVAIL_INT		0x00000080UL
+#define	RX_STOPPED_INT		0x00000100UL
+#define	RX_WATCHDOG_INT		0x00000200UL
+
+#define	TX_EARLY_INT		0x00000400UL
+#define	GP_TIMER_INT		0x00000800UL
+#define	LINK_STATUS_INT		0x00001000UL
+#define	SYSTEM_ERR_INT		0x00002000UL
+#define	RX_EARLY_INT		0x00004000UL
+
+#define	ABNORMAL_SUMMARY_INT	0x00008000UL
+#define	NORMAL_SUMMARY_INT	0x00010000UL
+#define	INT_STATUS_MASK		0x0001ffffUL
+
+#define	RX_PROCESS_STOPPED	0x00000000UL
+#define	RX_PROCESS_FETCH_DESC	0x00020000UL
+#define	RX_PROCESS_WAIT_PKT	0x00040000UL
+#define	RX_PROCESS_STORE_DATA	0x00060000UL
+#define	RX_PROCESS_CLOSE_OWNER	0x00080000UL
+#define	RX_PROCESS_CLOSE_STATUS	0x000a0000UL
+#define	RX_PROCESS_SUSPEND	0x000c0000UL
+#define	RX_PROCESS_PURGE	0x000e0000UL
+#define	RX_PROCESS_STATE_MASK	0x000e0000UL
+#define	TX_PROCESS_STOPPED	0x00000000UL
+#define	TX_PROCESS_FETCH_DESC	0x00100000UL
+#define	TX_PROCESS_FETCH_SETUP	0x00200000UL
+#define	TX_PROCESS_FETCH_DATA	0x00300000UL
+#define	TX_PROCESS_CLOSE_OWNER	0x00400000UL
+#define	TX_PROCESS_WAIT_END	0x00500000UL
+#define	TX_PROCESS_CLOSE_STATUS	0x00600000UL
+#define	TX_PROCESS_SUSPEND	0x00700000UL
+#define	TX_PROCESS_STATE_MASK	0x00700000UL
+#define	SYSTEM_ERR_BITS		0x03800000UL
+#define	SYSTEM_ERR_PARITY	0x00000000UL
+#define	SYSTEM_ERR_M_ABORT	0x00800000UL
+#define	SYSTEM_ERR_T_ABORT	0x01000000UL
+
+#define	RX_PROCESS_STATE(csr5)	(((csr5) & RX_PROCESS_STATE_MASK) >> 17)
+#define	RX_PROCESS_MAX_STATE	7
+#define	TX_PROCESS_STATE(csr5)	(((csr5) & TX_PROCESS_STATE_MASK) >> 20)
+#define	TX_PROCESS_MAX_STATE	7
+
+/* OPN_REG , CSR6 */
+#define	HASH_FILTERING		(1UL<<0)
+#define	START_RECEIVE		(1UL<<1)
+#define	HASH_ONLY		(1UL<<2)
+#define	PASSBAD			(1UL<<3)
+#define	INV_FILTER		(1UL<<4)
+#define	PROMISC_MODE		(1UL<<6)
+#define	PASS_MULTICAST		(1UL<<7)
+#define	FULL_DUPLEX		(1UL<<9)
+#define	LOOPBACK_OFF		(0UL<<10)
+#define	LOOPBACK_INTERNAL	(1UL<<10)
+#define	LOOPBACK_PHY_D		(2UL<<10)
+#define	LOOPBACK_PHY_A		(3UL<<10)
+#define	LOOPBACK_MODE_MASK	(3UL<<10)
+#define	FORCE_COLLISION		(1UL<<12)
+#define	START_TRANSMIT 		(1UL<<13)
+#define	TX_THRESHOLD_LOW	(0UL<<14)
+#define	TX_THRESHOLD_MID	(1UL<<14)
+#define	TX_THRESHOLD_HI		(2UL<<14)
+#define	TX_THRESHOLD_MASK	(3UL<<14)
+#define	ONE_PKT_MODE		(1UL<<16)
+#define	EXT_MII_IF		(1UL<<18)
+#define	START_TX_IMMED		(1UL<<20)
+#define	STORE_AND_FORWARD	(1UL<<21)
+#define	TX_THRESHOLD_MODE	(1UL<<22)
+#define	OPN_25_MB1		(1UL<<25)
+#define	NO_RX_PURGE		(1UL<<29)
+#define	RECEIVEALL		(1UL<<30)
+
+/* INT_MASK_REG , CSR7 */
+/*
+ * Use the values defined for the INT_STATUS_MASK bits (0..16)
+ * of CSR5.  The remaining bits (17..31) are not used.
+ */
+
+/* MISSED_FRAME_REG, CSR8 */
+#define	MISSED_FRAME_MASK	0x00000ffffUL
+#define	MISSED_OVERFLOW		0x000010000UL
+#define	PURGED_PACKET_MASK	0x07ffe0000UL
+#define	PURGED_OVERFLOW		0x080000000UL
+
+/* Serial ROM/MII Register CSR9 */
+#define	SEL_CHIP		0x00000001UL
+#define	SEL_CLK			0x00000002UL
+#define	DATA_IN			0x00000004UL
+#define	DATA_OUT		0x00000008UL
+#define	SER_8_MB1		0x00000300UL
+#define	SEL_XRS			0x00000400UL
+#define	SEL_EEPROM		0x00000800UL
+#define	SEL_BOOTROM		0x00001000UL
+#define	WRITE_OP		0x00002000UL
+#define	READ_OP			0x00004000UL
+#define	SER_15_MB1		0x00008000UL
+
+#define	MII_CLOCK		0x00010000UL
+#define	MII_DATA_OUT		0x00020000UL
+#define	MII_DATA_OUT_SHIFT	17
+#define	MII_READ		0x00040000UL
+#define	MII_TRISTATE		0x00040000UL
+#define	MII_WRITE		0x00000000UL
+#define	MII_DATA_IN		0x00080000UL
+#define	MII_DATA_IN_SHIFT	19
+
+#define	RELOAD_EEPROM		0x00100000UL
+#define	LOADED_EEPROM		0x00200000UL
+
+/* GPR Timer reg, CSR11 */
+#define	GPTIMER_CONT		(1UL<<16)
+
+/* PHY Status reg, CSR12 */
+#define	GPS_LINK_10		0x00000001UL
+#define	GPS_LINK_100		0x00000002UL
+#define	GPS_FULL_DUPLEX		0x00000004UL
+#define	GPS_LINK_STATUS		0x00000008UL
+#define	GPS_RX_LOCK		0x00000010UL
+#define	GPS_SIGNAL_DETECT	0x00000020UL
+#define	GPS_UTP_SIG		0x00000040UL
+#define	GPS_PHY_RESET		0x00000080UL
+#define	GPS_WRITE_ENABLE	0x00000100UL
+
+/* Sample Frame Access reg, CSR13 */
+#define	TX_FIFO_ACCESS		(0x32<<3)
+#define	RX_FIFO_ACCESS		(0x35<<3)
+#define	DIAG_RESET		(0x38<<3)
+
+/* Sample Frame Data reg, CSR14, when CSR13 is set to DIAG_RESET */
+#define	DIAG_TX_FIFO_WRITE_0	0x00000001UL
+#define	DIAG_TX_FIFO_READ_0	0x00000002UL
+#define	DIAG_RX_FIFO_WRITE_0	0x00000004UL
+#define	DIAG_RX_FIFO_READ_0	0x00000008UL
+#define	DIAG_TX_FIFO_WRITE_100	0x00000020UL
+#define	DIAG_RX_FIFO_WRITE_100	0x00000040UL
+
+/* CSR15 */
+#define	TX_JABBER_DISABLE	0x00000001UL
+#define	UNJABBER_INTERVAL	0x00000002UL
+#define	JABBER_CLOCK		0x00000004UL
+#define	WD_TIMER_DISABLE	0x00000010UL
+#define	WD_TIMER_RELEASE	0x00000020UL
+#define	VLAN_ENABLE		0x00000040UL
+#define	PAUSE_STATUS_1		0x00000080UL
+#define	PAUSE_STATUS_2		0x00000200UL
+#define	FLOW_CONTROL		0x00000400UL
+#define	PAUSE_ENABLE_1		0x00000800UL
+#define	PAUSE_ENABLE_2		0x00001000UL
+#define	PAUSE_TX_FFFF		0x00002000UL
+#define	PAUSE_TX_0000		0x00004000UL
+#define	PAUSE_CONDITION		0x00008000UL
+#define	RX_FIFO_THRES_MASK	0x003f0000UL
+#define	RX_EARLY_THRES_MASK	0x01c00000UL
+
+
+/* SROM access definitions */
+#define	HIGH_ADDRESS_BIT	0x00000020UL
+#define	SROM_DELAY		5			/* 5 microseconds */
+
+/* MII access definitions */
+#define	MII_REG_ADDR_SHIFT	18
+#define	MII_PHY_ADDR_SHIFT	23
+#define	MII_DELAY		1			/* 1 microsecond */
+#define	MII_PREAMBLE		0xffffffffUL
+#define	MII_READ_FRAME		0x60000000UL
+#define	MII_WRITE_FRAME		0x50020000UL
+
+
+/* DMFE IOCTLS */
+#define	ND_BASE			('N' << 8)	/* base */
+#define	ND_GET			(ND_BASE + 0)	/* Get a value */
+#define	ND_SET			(ND_BASE + 1)	/* Set a value */
+
+#define	DMFE_ND_GET		ND_GET
+#define	DMFE_ND_SET		ND_SET
+
+#define	DMFEIOC			('G' << 8)
+#define	DMFE_SET_LOOP_MODE	(DMFEIOC|1)
+#define	DMFE_GET_LOOP_MODE	(DMFEIOC|2)
+
+/* argument structure for above */
+typedef struct {
+	int loopback;
+} loopback_t;
+
+#define	DMFE_LOOPBACK_OFF	0
+#define	DMFE_PHY_A_LOOPBACK_ON	1
+#define	DMFE_PHY_D_LOOPBACK_ON	2
+#define	DMFE_INT_LOOPBACK_ON	4
+#define	DMFE_LOOPBACK_MODES	7	/* Bitwise OR of above	*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* _SYS_DMFE_H */
diff --git a/usr/src/uts/sun4u/sys/dmfe_impl.h b/usr/src/uts/sun4u/sys/dmfe_impl.h
new file mode 100644
index 0000000000..ad3cc29045
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/dmfe_impl.h
@@ -0,0 +1,713 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_DMFE_IMPL_H
+#define	_SYS_DMFE_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <sys/types.h>
+#include <sys/stream.h>
+#include <sys/strsun.h>
+#include <sys/stat.h>
+#include <sys/pci.h>
+#include <sys/note.h>
+#include <sys/modctl.h>
+#include <sys/kstat.h>
+#include <sys/ethernet.h>
+#include <sys/dlpi.h>
+#include <sys/devops.h>
+#include <sys/debug.h>
+#include <sys/cyclic.h>
+#include <sys/conf.h>
+
+#include <inet/common.h>
+#include <inet/nd.h>
+#include <inet/mi.h>
+
+#include <sys/dditypes.h>
+#include <sys/ddi.h>
+#include <sys/sunddi.h>
+
+#include <sys/miiregs.h>
+#include <sys/dmfe.h>
+
+/*
+ * The following function *may* be defined in <sys/gld.h>.
+ * If so, the full definitions there will supplement these minimal
+ * versions; otherwise, these will suffice to allow the code to
+ * compile and then we'll test for them at runtime.
+ */
+extern void gld_linkstate();
+extern void gld_recv_tagged();
+#pragma weak    gld_linkstate
+#pragma weak    gld_recv_tagged
+
+#include <sys/gld.h>
+
+/*
+ * Define these symbols if they're not already in <sys/gld.h>
+ */
+#ifndef	GLD_LINKSTATE_UP
+#define	GLD_LINKSTATE_UP	1
+#define	GLD_LINKSTATE_UNKNOWN	0
+#define	GLD_LINKSTATE_DOWN	-1
+#endif	/* GLD_LINKSTATE_UP */
+
+/*
+ * This driver can be compiled with VLAN support (if VLAN_VID_NONE
+ * is defined in <sys/gld.h>).  If not, the definitions is the 'else'
+ * clause will allow the code to compile anyway.
+ */
+#ifdef	VLAN_VID_NONE
+#define	DMFE_MAX_PKT_SIZE	(VTAG_SIZE + ETHERMAX + ETHERFCSL)
+#else
+#define	DMFE_MAX_PKT_SIZE	(ETHERMAX + ETHERFCSL)
+#define	VLAN_VTAG_NONE		0		/* implies "untagged"	*/
+#endif	/* VLAN_VID_NONE */
+
+
+#define	DRIVER_NAME		"dmfe"
+
+/*
+ * Describes the identity of a specific chip
+ */
+typedef struct {
+	uint16_t		vendor;
+	uint16_t		device;
+	uint8_t			revision;
+	uint8_t			spare;
+} chip_id_t;
+
+/*
+ * Describes the state of a descriptor ring
+ *
+ * NOTE: n_free and next_busy are only used for the Tx descriptors
+ * and are not valid on the receive side.
+ */
+typedef struct {
+	uint32_t		n_desc;		/* # of descriptors	    */
+	uint32_t		n_free;		/* # of free descriptors    */
+	uint32_t		next_free;	/* next index to use/check  */
+	uint32_t		next_busy;	/* next index to reclaim    */
+} desc_state_t;
+
+/*
+ * Describes one chunk of allocated DMA-able memory
+ */
+typedef struct {
+	ddi_dma_handle_t	dma_hdl;
+	ddi_acc_handle_t	acc_hdl;
+	size_t			alength;	/* allocated size	*/
+	caddr_t			mem_va;		/* CPU VA of memory	*/
+	uint32_t		spare1;
+	uint32_t		mem_dvma;	/* DVMA addr of memory	*/
+	caddr_t			setup_va;
+	uint32_t		spare2;
+	uint32_t		setup_dvma;
+	int			spare3;
+	int			ncookies;
+} dma_area_t;
+
+/*
+ * Named Data (ND) Parameter Management Structure
+ */
+typedef struct {
+	uint32_t		ndp_info;
+	uint32_t		ndp_min;
+	uint32_t		ndp_max;
+	uint32_t		ndp_val;
+	char			*ndp_name;
+} nd_param_t;
+
+/*
+ * NDD parameter indexes, divided into:
+ *
+ *	read-only parameters describing the link state
+ *	read-write parameters controlling the advertised link capabilities
+ *	read-only parameters describing the device link capabilities
+ *	read-only parameters describing the link-partner's link capabilities
+ */
+enum {
+	PARAM_LINK_STATUS,
+	PARAM_LINK_SPEED,
+	PARAM_LINK_MODE,
+
+	PARAM_ADV_AUTONEG_CAP,
+	PARAM_ADV_100T4_CAP,
+	PARAM_ADV_100FDX_CAP,
+	PARAM_ADV_100HDX_CAP,
+	PARAM_ADV_10FDX_CAP,
+	PARAM_ADV_10HDX_CAP,
+
+	PARAM_BMSR_AUTONEG_CAP,
+	PARAM_BMSR_100T4_CAP,
+	PARAM_BMSR_100FDX_CAP,
+	PARAM_BMSR_100HDX_CAP,
+	PARAM_BMSR_10FDX_CAP,
+	PARAM_BMSR_10HDX_CAP,
+	PARAM_BMSR_REMFAULT,
+
+	PARAM_LP_AUTONEG_CAP,
+	PARAM_LP_100T4_CAP,
+	PARAM_LP_100FDX_CAP,
+	PARAM_LP_100HDX_CAP,
+	PARAM_LP_10FDX_CAP,
+	PARAM_LP_10HDX_CAP,
+	PARAM_LP_REMFAULT,
+
+	PARAM_COUNT
+};
+
+/*
+ * Indexes into standard "mii" kstats, divided into:
+ *
+ *      MII transceiver info
+ *      MII link state
+ *      MII device capabilities
+ *      MII advertised capabilities
+ *      MII link partner capabilities
+ */
+enum {
+	KS_MII_XCVR_ADDR,
+	KS_MII_XCVR_ID,
+	KS_MII_XCVR_INUSE,
+
+	KS_MII_LINK_UP,
+	KS_MII_LINK_DUPLEX,
+
+	KS_MII_CAP_100FDX,
+	KS_MII_CAP_100HDX,
+	KS_MII_CAP_10FDX,
+	KS_MII_CAP_10HDX,
+	KS_MII_CAP_REMFAULT,
+	KS_MII_CAP_AUTONEG,
+
+	KS_MII_ADV_CAP_100FDX,
+	KS_MII_ADV_CAP_100HDX,
+	KS_MII_ADV_CAP_10FDX,
+	KS_MII_ADV_CAP_10HDX,
+	KS_MII_ADV_CAP_REMFAULT,
+	KS_MII_ADV_CAP_AUTONEG,
+
+	KS_MII_LP_CAP_100FDX,
+	KS_MII_LP_CAP_100HDX,
+	KS_MII_LP_CAP_10FDX,
+	KS_MII_LP_CAP_10HDX,
+	KS_MII_LP_CAP_REMFAULT,
+	KS_MII_LP_CAP_AUTONEG,
+
+	KS_MII_COUNT
+};
+
+/*
+ * Indexes into the driver-specific kstats, divided into:
+ *
+ *	cyclic activity
+ *	reasons for waking the factotum
+ *	the factotum's activities
+ *      link state updates
+ *      MII-level register values
+ */
+enum {
+	KS_CYCLIC_RUN,
+
+	KS_TICK_LINK_STATE,
+	KS_TICK_LINK_POLL,
+	KS_LINK_INTERRUPT,
+	KS_TX_STALL,
+	KS_CHIP_ERROR,
+
+	KS_FACTOTUM_RUN,
+	KS_RECOVERY,
+	KS_LINK_CHECK,
+
+	KS_LINK_UP_CNT,
+	KS_LINK_DROP_CNT,
+	KS_LINK_CYCLE_UP_CNT,
+	KS_LINK_CYCLE_DOWN_CNT,
+
+	KS_MIIREG_BMSR,
+	KS_MIIREG_ANAR,
+	KS_MIIREG_ANLPAR,
+	KS_MIIREG_ANER,
+	KS_MIIREG_DSCSR,
+
+	KS_DRV_COUNT
+};
+
+/*
+ * Actual state of the DM9102A chip
+ */
+enum chip_state {
+	CHIP_ERROR = -1,			/* error, need reset	*/
+	CHIP_UNKNOWN,				/* Initial state only	*/
+	CHIP_RESET,				/* reset, need init	*/
+	CHIP_STOPPED,				/* Tx/Rx stopped	*/
+	CHIP_TX_ONLY,				/* Tx (re)started	*/
+	CHIP_TX_RX,				/* Tx & Rx (re)started	*/
+	CHIP_RUNNING				/* with interrupts	*/
+};
+
+/*
+ * Required state according to GLD
+ */
+enum gld_state {
+	GLD_UNKNOWN,
+	GLD_RESET,
+	GLD_STOPPED,
+	GLD_STARTED
+};
+
+/*
+ * Current state of the physical link
+ *
+ *	DOWN		No link established.
+ *	UNKNOWN		Initial state, also indicates "autonegotiating".
+ *	UP		Link established, commuication should be possible.
+ */
+typedef enum {
+	LINK_DOWN = -1,
+	LINK_UNKNOWN = 0,
+	LINK_UP
+} link_state_t;
+
+/*
+ * (Internal) return values from ioctl subroutines
+ */
+enum ioc_reply {
+	IOC_INVAL = -1,				/* bad, NAK with EINVAL	*/
+	IOC_DONE,				/* OK, reply sent	*/
+	IOC_REPLY,				/* OK, just send reply	*/
+	IOC_ACK,				/* OK, just send ACK	*/
+	IOC_RESTART,				/* OK, restart & reply	*/
+	IOC_RESTART_ACK				/* OK, restart & ACK	*/
+};
+
+/*
+ * Per-instance soft-state structure
+ */
+typedef struct {
+	/*
+	 * These fields are set by attach() and unchanged thereafter ...
+	 */
+	dev_info_t		*devinfo;	/* device instance	*/
+	gld_mac_info_t		*macinfo;	/* GLD instance data	*/
+	ddi_acc_handle_t	io_handle;	/* DDI I/O handle	*/
+	caddr_t			io_reg;		/* mapped registers	*/
+
+	uint32_t		debug;		/* per-instance debug	*/
+	uint32_t		progress;	/* attach tracking	*/
+	chip_id_t		chipid;
+	uint8_t			vendor_addr[ETHERADDRL];
+	char			ifname[12];	/* "dmfeXXXX"		*/
+
+	dma_area_t		tx_desc;	/* transmit descriptors	*/
+	dma_area_t		tx_buff;	/* transmit buffers	*/
+	dma_area_t		rx_desc;	/* receive descriptors	*/
+	dma_area_t		rx_buff;	/* receive buffers	*/
+
+	cyclic_id_t		cycid;		/* cyclic callback id	 */
+	ddi_softintr_t		factotum_id;	/* identity of factotum	*/
+	ddi_iblock_cookie_t	iblk;
+
+	/*
+	 * Locks:
+	 *
+	 * <milock> is used only by the MII (PHY) level code, to ensure
+	 *	exclusive access during the bit-twiddling needed to send
+	 *	signals along the MII serial bus.  These operations are
+	 *	--S--L--O--W-- so we keep this lock separate, so that
+	 *	faster operations (e.g. interrupts) aren't delayed by
+	 *	waiting for it.
+	 *
+	 * <oplock> is a general "outer" lock, protecting most r/w data
+	 *	and chip state.  It is also acquired by the interrupt
+	 *	handler.
+	 *
+	 * <rxlock> is used to protect the Rx-side buffers, descriptors,
+	 *	and statistics during a single call to dmfe_getp().
+	 *	This is called from inside the interrupt handler, but
+	 *	<oplock> is not held across this call.
+	 *
+	 * <txlock> is an "inner" lock, and protects only the Tx-side
+	 *	data below and in the ring buffers/descriptors.  The
+	 *	Tx-side code uses only this lock, avoiding contention
+	 *	with the receive-side code.
+	 *
+	 * Any of the locks can be acquired singly, but where multiple
+	 * locks are acquired, they *must* be in the order:
+	 *
+	 *	milock >>> oplock >>> rxlock >>> txlock.
+	 *
+	 * *None* of these locks may be held across calls out to the
+	 * GLD routines gld_recv() or gld_sched(); GLD's <maclock> must
+	 * be regarded as an *outermost* lock in all cases, as it will
+	 * already be held before calling the ioctl() or get_stats()
+	 * entry points - which then have to acquire multiple locks, in
+	 * the order described here.
+	 */
+	kmutex_t		milock[1];
+	kmutex_t		oplock[1];
+	kmutex_t		rxlock[1];
+	kmutex_t		txlock[1];
+
+	/*
+	 * DMFE Extended kstats, protected by <oplock>
+	 */
+	kstat_t			*ksp_mii;
+	kstat_named_t		*knp_mii;
+	kstat_t			*ksp_drv;
+	kstat_named_t		*knp_drv;
+
+	/*
+	 * GLD statistics; the prefix tells which lock each is protected by.
+	 */
+	uint64_t		op_stats_speed;
+	uint32_t		op_stats_duplex;
+	uint32_t		op_stats_media;
+	uint32_t		op_stats_intr;
+
+	uint32_t		rx_stats_errrcv;
+	uint32_t		rx_stats_overflow;
+	uint32_t		rx_stats_short;
+	uint32_t		rx_stats_crc;
+	uint32_t		rx_stats_frame_too_long;
+	uint32_t		rx_stats_mac_rcv_error;
+	uint32_t		rx_stats_frame;
+	uint32_t		rx_stats_missed;
+	uint32_t		rx_stats_norcvbuf;
+
+	uint32_t		tx_stats_errxmt;
+	uint32_t		tx_stats_mac_xmt_error;
+	uint32_t		tx_stats_underflow;
+	uint32_t		tx_stats_xmtlatecoll;
+	uint32_t		tx_stats_nocarrier;
+	uint32_t		tx_stats_excoll;
+	uint32_t		tx_stats_first_coll;
+	uint32_t		tx_stats_multi_coll;
+	uint32_t		tx_stats_collisions;
+	uint32_t		tx_stats_defer;
+
+	/*
+	 * These two sets of desciptors are manipulated during
+	 * packet receive/transmit respectively.
+	 */
+	desc_state_t		rx;		/* describes Rx ring	*/
+	desc_state_t		tx;		/* describes Tx ring	*/
+
+	/*
+	 * Miscellaneous Tx-side variables (protected by txlock)
+	 */
+	uint32_t		tx_pending_tix;	/* tix since reclaim	*/
+
+	/*
+	 * Miscellaneous operating variables (protected by oplock)
+	 */
+	uint32_t		link_poll_tix;	/* tix until link poll	 */
+	uint16_t		factotum_flag;	/* callback pending	 */
+	uint16_t		need_setup;	/* send-setup pending	 */
+	uint32_t		opmode;		/* operating mode shadow */
+	uint32_t		imask;		/* interrupt mask shadow */
+	enum gld_state		gld_state;	/* RESET/STOPPED/STARTED */
+	enum chip_state		chip_state;	/* see above		 */
+
+	/*
+	 * Physical link state data (protected by oplock)
+	 */
+	link_state_t		link_state;	/* See above		*/
+	const char		*link_down_msg;	/* reason for link DOWN	*/
+	const char		*link_up_msg;	/* comment on link UP	*/
+
+	/*
+	 * PHYceiver state data (protected by milock)
+	 */
+	int			phy_addr;	/* should be -1!	*/
+	uint16_t		phy_control;	/* last value written	*/
+	uint16_t		phy_anar_w;	/* last value written	*/
+	uint16_t		phy_anar_r;	/* latest value read	*/
+	uint16_t		phy_anlpar;	/* latest value read	*/
+	uint16_t		phy_aner;
+	uint16_t		phy_dscsr;	/* latest value read	*/
+	uint16_t		phy_bmsr;	/* latest value read	*/
+	uint16_t		rsvd;		/* reserved for future use */
+	uint32_t		phy_bmsr_lbolt;	/* time of BMSR change	*/
+	uint32_t		phy_id; 	/* vendor+device (OUI)	*/
+
+	/*
+	 * Current Ethernet address & multicast map ...
+	 */
+	uint8_t			curr_addr[ETHERADDRL];
+	uint8_t			mcast_refs[MCASTBUF_SIZE];
+	boolean_t		addr_set;
+	boolean_t		update_phy;	/* Need to update_phy? */
+
+	/*
+	 * NDD parameters
+	 */
+	caddr_t			nd_data_p;
+	nd_param_t		nd_params[PARAM_COUNT];
+
+	/*
+	 * Guard element used to check data integrity
+	 */
+	uint64_t		dmfe_guard;
+} dmfe_t;
+
+/*
+ * 'Progress' bit flags ...
+ */
+#define	PROGRESS_CONFIG		0x0001	/* config space initialised	*/
+#define	PROGRESS_NDD		0x0002	/* NDD parameters set up	*/
+#define	PROGRESS_REGS		0x0004	/* registers mapped		*/
+#define	PROGRESS_BUFS		0x0008	/* buffers allocated		*/
+#define	PROGRESS_SOFTINT	0x0010	/* softint registered		*/
+#define	PROGRESS_HWINT		0x0020	/* h/w interrupt registered	*/
+
+/*
+ * Type of transceiver currently in use
+ */
+#define	PHY_TYPE_UNDEFINED	0
+#define	PHY_TYPE_10BASE_MNCHSTR	2
+#define	PHY_TYPE_100BASE_X	4
+
+/*
+ * Shorthand for the NDD parameters
+ */
+#define	param_linkup		nd_params[PARAM_LINK_STATUS].ndp_val
+#define	param_speed		nd_params[PARAM_LINK_SPEED].ndp_val
+#define	param_duplex		nd_params[PARAM_LINK_MODE].ndp_val
+#define	param_autoneg		nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val
+#define	param_anar_100T4	nd_params[PARAM_ADV_100T4_CAP].ndp_val
+#define	param_anar_100fdx	nd_params[PARAM_ADV_100FDX_CAP].ndp_val
+#define	param_anar_100hdx	nd_params[PARAM_ADV_100HDX_CAP].ndp_val
+#define	param_anar_10fdx	nd_params[PARAM_ADV_10FDX_CAP].ndp_val
+#define	param_anar_10hdx	nd_params[PARAM_ADV_10HDX_CAP].ndp_val
+#define	param_bmsr_autoneg	nd_params[PARAM_BMSR_AUTONEG_CAP].ndp_val
+#define	param_bmsr_100T4	nd_params[PARAM_BMSR_100T4_CAP].ndp_val
+#define	param_bmsr_100fdx	nd_params[PARAM_BMSR_100FDX_CAP].ndp_val
+#define	param_bmsr_100hdx	nd_params[PARAM_BMSR_100HDX_CAP].ndp_val
+#define	param_bmsr_10fdx	nd_params[PARAM_BMSR_10FDX_CAP].ndp_val
+#define	param_bmsr_10hdx	nd_params[PARAM_BMSR_10HDX_CAP].ndp_val
+#define	param_bmsr_remfault	nd_params[PARAM_BMSR_REMFAULT].ndp_val
+#define	param_lp_autoneg	nd_params[PARAM_LP_AUTONEG_CAP].ndp_val
+#define	param_lp_100T4		nd_params[PARAM_LP_100T4_CAP].ndp_val
+#define	param_lp_100fdx		nd_params[PARAM_LP_100FDX_CAP].ndp_val
+#define	param_lp_100hdx		nd_params[PARAM_LP_100HDX_CAP].ndp_val
+#define	param_lp_10fdx		nd_params[PARAM_LP_10FDX_CAP].ndp_val
+#define	param_lp_10hdx		nd_params[PARAM_LP_10HDX_CAP].ndp_val
+#define	param_lp_remfault	nd_params[PARAM_LP_REMFAULT].ndp_val
+
+/*
+ * Derive DMFE state from GLD's macinfo or vice versa
+ */
+#define	DMFE_STATE(macinfo)	((dmfe_t *)((macinfo)->gldm_private))
+#define	DMFE_MACINFO(dmfep)	((dmfep)->macinfo)
+
+/*
+ * Sync a DMA area described by a dma_area_t
+ */
+#define	DMA_SYNC(descp, flag)	((void) ddi_dma_sync((descp)->dma_hdl,	\
+					0, (descp)->alength, flag))
+
+/*
+ * Next value of a cyclic index
+ */
+#define	NEXT(index, limit)	((index)+1 < (limit) ? (index)+1 : 0);
+
+/*
+ * Utility Macros
+ */
+#define	U32TOPTR(x)		((void *)(uintptr_t)(uint32_t)(x))
+#define	PTRTOU32(x)		((uint32_t)(uintptr_t)(void *)(x))
+
+/*
+ * Copy an ethernet address
+ */
+#define	ethaddr_copy(src, dst)	bcopy((src), (dst), ETHERADDRL)
+#define	MII_KS_GET(dmfep, id)						\
+	(((dmfep)->knp_mii) ? ((dmfep)->knp_mii)[id].value.ui32 : 0)
+
+#define	MII_KS_SET(dmfep, id, val)					\
+	do {								\
+		if ((dmfep)->knp_mii != NULL)				\
+			((dmfep)->knp_mii)[id].value.ui32 = (val);	\
+		_NOTE(CONSTANTCONDITION)				\
+	} while (0)
+
+#define	MII_KS_INC(dmfep, id)						\
+	do {								\
+		if ((dmfep)->knp_mii != NULL)				\
+			((dmfep)->knp_mii)[id].value.ui32 += 1;		\
+		_NOTE(CONSTANTCONDITION)				\
+	} while (0)
+
+/*
+ * Get/set/increment a (64-bit) driver-private kstat
+ */
+#define	DRV_KS_GET(dmfep, id)						\
+	(((dmfep)->knp_drv) ? ((dmfep)->knp_drv)[id].value.ui64 : 0)
+
+#define	DRV_KS_SET(dmfep, id, val)					\
+	do {								\
+		if ((dmfep)->knp_drv)					\
+			((dmfep)->knp_drv)[id].value.ui64 = (val);	\
+		_NOTE(CONSTANTCONDITION)				\
+	} while (0)
+
+#define	DRV_KS_INC(dmfep, id)						\
+	do {								\
+		if ((dmfep)->knp_drv)					\
+			((dmfep)->knp_drv)[id].value.ui64 += 1;		\
+		_NOTE(CONSTANTCONDITION)				\
+	} while (0)
+
+/*
+ * Bit test macros, returning boolean_t values
+ */
+#define	BIS(w, b)		((w) & (b))
+#define	BIC(w, b)		!BIS(w, b)
+
+#define	DMFE_GUARD		0x1919603003090218
+
+/*
+ * 'Debug' bit flags ...
+ */
+#define	DMFE_DBG_TRACE		0x0001		/* general flow tracing	*/
+#define	DMFE_DBG_REGS		0x0002		/* low-level accesses	*/
+#define	DMFE_DBG_RECV		0x0004		/* receive-side code	*/
+#define	DMFE_DBG_SEND		0x0008		/* packet-send code	*/
+#define	DMFE_DBG_ADDR		0x0010		/* address-setting code	*/
+#define	DMFE_DBG_GLD		0x0020		/* GLD entry points	*/
+#define	DMFE_DBG_FACT		0x0040		/* factotum (softint)	*/
+#define	DMFE_DBG_TICK		0x0080		/* GPT ticker		*/
+#define	DMFE_DBG_INT		0x0100		/* interrupt handler	*/
+#define	DMFE_DBG_STATS		0x0200		/* statistics		*/
+#define	DMFE_DBG_IOCTL		0x0400		/* ioctl/loopback code	*/
+#define	DMFE_DBG_INIT		0x0800		/* initialisation	*/
+#define	DMFE_DBG_MII		0x1000		/* low-level MII/PHY	*/
+#define	DMFE_DBG_LINK		0x2000		/* Link status check	*/
+#define	DMFE_DBG_NDD		0x4000		/* NDD parameters	*/
+
+/*
+ * Debugging ...
+ */
+#ifdef	DEBUG
+#define	DMFEDEBUG		1
+#else
+#define	DMFEDEBUG		0
+#endif
+
+#if	DMFEDEBUG
+
+extern uint32_t dmfe_debug;
+extern void (*dmfe_gdb())(const char *fmt, ...);
+extern void (*dmfe_db(dmfe_t *dmfep))(const char *fmt, ...);
+
+/*
+ * Define DMFE_DBG to be the relevant flag from the set above before
+ * using the DMFE_GDEBUG() or DMFE_DEBUG() macros.  The 'G' versions
+ * look at the Global debug flag word (dmfe_debug); the non-G versions
+ * look in the per-instance data (dmfep->debug) and so require a variable
+ * called 'dmfep' to be in scope (and initialised!)
+ *
+ * You could redefine DMFE_TRC too if you really need two different
+ * flavours of debugging output in the same area of code, but I don't
+ * really recommend it.
+ */
+
+#define	DMFE_TRC		DMFE_DBG_TRACE	/* default 'trace' bit	*/
+
+#define	DMFE_GDEBUG(args)	do {					\
+					if (dmfe_debug & (DMFE_DBG))	\
+						(*dmfe_gdb()) args;	\
+					_NOTE(CONSTANTCONDITION)	\
+				} while (0)
+
+#define	DMFE_GTRACE(args)	do {					\
+					if (dmfe_debug & (DMFE_TRC))	\
+						(*dmfe_gdb()) args;	\
+					_NOTE(CONSTANTCONDITION)	\
+				} while (0)
+
+#define	DMFE_DEBUG(args)	do {					\
+					if (dmfep->debug & (DMFE_DBG))	\
+						(*dmfe_db(dmfep)) args;	\
+					_NOTE(CONSTANTCONDITION)	\
+				} while (0)
+
+#define	DMFE_TRACE(args)	do {					\
+					if (dmfep->debug & (DMFE_TRC))	\
+						(*dmfe_db(dmfep)) args;	\
+					_NOTE(CONSTANTCONDITION)	\
+				} while (0)
+
+#else
+
+#define	DMFE_DEBUG(args)	do ; _NOTE(CONSTANTCONDITION) while (0)
+#define	DMFE_TRACE(args)	do ; _NOTE(CONSTANTCONDITION) while (0)
+#define	DMFE_GDEBUG(args)	do ; _NOTE(CONSTANTCONDITION) while (0)
+#define	DMFE_GTRACE(args)	do ; _NOTE(CONSTANTCONDITION) while (0)
+
+#endif	/* DMFEDEBUG */
+
+
+/*
+ * Inter-source-file linkage ...
+ */
+
+/* dmfe_log.c */
+void dmfe_warning(dmfe_t *dmfep, const char *fmt, ...);
+void dmfe_error(dmfe_t *dmfep, const char *fmt, ...);
+void dmfe_notice(dmfe_t *dmfep, const char *fmt, ...);
+void dmfe_log(dmfe_t *dmfep, const char *fmt, ...);
+void dmfe_log_init(void);
+void dmfe_log_fini(void);
+
+/* dmfe_main.c */
+uint32_t dmfe_chip_get32(dmfe_t *dmfep, off_t offset);
+void dmfe_chip_put32(dmfe_t *dmfep, off_t offset, uint32_t value);
+
+/* dmfe_mii.c */
+boolean_t dmfe_init_phy(dmfe_t *dmfep);
+void dmfe_update_phy(dmfe_t *dmfep);
+boolean_t dmfe_check_link(dmfe_t *dmfep);
+void dmfe_recheck_link(dmfe_t *dmfep, boolean_t ioctl);
+
+/* dmfe_ndd.c */
+int dmfe_nd_init(dmfe_t *dmfep);
+enum ioc_reply dmfe_nd_ioctl(dmfe_t *dmfep, queue_t *wq, mblk_t *mp, int cmd);
+void dmfe_nd_cleanup(dmfe_t *dmfep);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* _SYS_DMFE_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/ecc_kstat.h b/usr/src/uts/sun4u/sys/ecc_kstat.h
new file mode 100644
index 0000000000..55fbe6da9f
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/ecc_kstat.h
@@ -0,0 +1,96 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SYS_ECC_KSTAT_H
+#define	_SYS_ECC_KSTAT_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	KSTAT_CE_UNUM_NAMLEN 60
+
+/*
+ * Using these stats are not reset to zero during system operation.
+ * To determine the number of errors between times "A" and "B" a program
+ * would have to snapshot the kstats and subtract the counts at time "A"
+ * from the counts at time "B".
+ */
+
+/*
+ * Legacy raw kstat: unix:0:ecc-mm-info
+ */
+struct kstat_ecc_mm_info_1 {
+	struct kstat_ecc_mm {
+		char name[KSTAT_CE_UNUM_NAMLEN];
+		uint64_t intermittent_total;
+		uint64_t persistent_total;
+		uint64_t sticky_total;
+	} ecc_mm[1];    /* variable-length array */
+};
+
+/*
+ * Named kstat: mm:(instance):ecc-info
+ */
+struct kstat_ecc_mm_info_2 {
+	struct kstat_named name;
+	struct kstat_named intermittent_total;
+	struct kstat_named persistent_total;
+	struct kstat_named sticky_total;
+};
+
+#define	kstat_ecc_mm_info	kstat_ecc_mm_info_2
+#define	KSTAT_CE_INFO_VER_1	1
+#define	KSTAT_CE_INFO_VER_2	2
+#define	KSTAT_CE_INFO_VER	KSTAT_CE_INFO_VER_2
+
+/*
+ * Clients of this kstat will have to check the version and maintain
+ * compatibility code to handle the previous versions.
+ *
+ * named kstat: unix:0:ecc-info:version
+ *	- the version of the kstats implemented by the running kernel
+ *
+ * named kstat: unix:0:ecc-info:count
+ *	- the current count of valid mm:ecc-info kstats
+ *
+ * named kstat: unix:0:ecc-info:maxcount
+ *	- the maximum number of mm:ecc-info kstats
+ */
+struct ecc_error_info {
+	struct kstat_named version;
+	struct kstat_named maxcount;
+	struct kstat_named count;
+};
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_ECC_KSTAT_H */
diff --git a/usr/src/uts/sun4u/sys/envmon.h b/usr/src/uts/sun4u/sys/envmon.h
new file mode 100644
index 0000000000..209a5cc80a
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/envmon.h
@@ -0,0 +1,236 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2003 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_ENVMON_H
+#define	_SYS_ENVMON_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/ioccom.h>
+
+/*
+ * environmental monitoring ioctls
+ *
+ * there are two types of environmental monitor:
+ * sensors	- these provide a value for the environmental property
+ * indicators	- these provide a status of "within range" or "out of range"
+ *
+ * for any given environmental property, a particular platform is likely
+ * to support either a sensor or an indicator
+ *
+ * a reserved value is used to signify that a particular sensor value is
+ * not available
+ */
+
+/* reserved values to signify "value unavailable" */
+#define	ENVMON_VAL_UNAVAILABLE	((int16_t)(-32768))
+
+/*
+ * The ability of a sensor or indicator to deliver a value is encapsulated
+ * in the sensor_status field.
+ * The following sensor_status bit fields are defined
+ */
+#define	ENVMON_SENSOR_OK	0	/* this one's a value */
+#define	ENVMON_NOT_PRESENT	1
+#define	ENVMON_INACCESSIBLE	2	/* e.g. i2c bus problem */
+
+/*
+ * Some drivers may implement the older lomv interface in addition to
+ * the ioctls defined here. To avoid a clash with values from older
+ * interfaces, ioctls defined here start high in the available range.
+ */
+#define	ENVMON_BASE		200
+
+#define	ENVMONIOCSYSINFO	_IOR('a',  ENVMON_BASE + 0, envmon_sysinfo_t)
+#define	ENVMONIOCVOLTSENSOR	_IOWR('a', ENVMON_BASE + 1, envmon_sensor_t)
+#define	ENVMONIOCAMPSENSOR	_IOWR('a', ENVMON_BASE + 2, envmon_sensor_t)
+#define	ENVMONIOCTEMPSENSOR	_IOWR('a', ENVMON_BASE + 3, envmon_sensor_t)
+#define	ENVMONIOCFAN		_IOWR('a', ENVMON_BASE + 4, envmon_fan_t)
+#define	ENVMONIOCVOLTIND	_IOWR('a', ENVMON_BASE + 5, envmon_indicator_t)
+#define	ENVMONIOCAMPIND		_IOWR('a', ENVMON_BASE + 6, envmon_indicator_t)
+#define	ENVMONIOCTEMPIND	_IOWR('a', ENVMON_BASE + 7, envmon_indicator_t)
+#define	ENVMONIOCFANIND		_IOWR('a', ENVMON_BASE + 8, envmon_indicator_t)
+#define	ENVMONIOCGETLED		_IOWR('a', ENVMON_BASE + 9, envmon_led_info_t)
+#define	ENVMONIOCSETLED		_IOW('a',  ENVMON_BASE + 10, envmon_led_ctl_t)
+#define	ENVMONIOCHPU		_IOWR('a', ENVMON_BASE + 11, envmon_hpu_t)
+#define	ENVMONIOCGETKEYSW	_IOR('a',  ENVMON_BASE + 12, envmon_keysw_pos_t)
+#define	ENVMONIOCGETALARM	\
+		_IOWR('a', ENVMON_BASE + 13, envmon_alarm_info_t)
+#define	ENVMONIOCSETALARM	_IOWR('a', ENVMON_BASE + 14, envmon_alarm_ctl_t)
+
+/* field length for text identifiers */
+#define	ENVMON_MAXNAMELEN	32
+
+typedef struct {
+	char			name[ENVMON_MAXNAMELEN];
+} envmon_handle_t;
+
+/*
+ * Some structures include threshold fields.
+ * Where a particular threshold is not defined for a given sensor,
+ * the reserved value ENVMON_VAL_UNAVAILABLE is returned.
+ */
+typedef struct {
+	int16_t			warning;
+	int16_t			shutdown;
+	int16_t			poweroff;
+} envmon_thresholds_t;
+
+/*
+ * id identifies the fru to be accessed.
+ * next_id returns the id for the next component of the type implied by
+ * the ioctl command. If there are no more frus in this sequence,
+ * next_id is set to an empty string.
+ * If id is set to an empty string on entry, next_id returns the first id.
+ * In this case, sensor_status will be returned as ENVMON_NOT_PRESENT.
+ */
+typedef struct {
+	envmon_handle_t		id;
+	uint16_t		sensor_status;
+	int16_t			value;		/* sensor reading */
+	envmon_thresholds_t	lowthresholds;
+	envmon_thresholds_t	highthresholds;
+	envmon_handle_t		next_id;
+} envmon_sensor_t;
+
+typedef struct {
+	envmon_handle_t	id;
+	uint16_t		sensor_status;
+	uint16_t		condition;	/* 0 = within limits */
+	envmon_handle_t	next_id;
+} envmon_indicator_t;
+
+typedef struct {
+	envmon_handle_t	id;
+	uint16_t		sensor_status;
+	uint16_t		speed;
+	char			units[ENVMON_MAXNAMELEN];
+	envmon_thresholds_t	lowthresholds;
+	envmon_handle_t		next_id;
+} envmon_fan_t;
+
+/*
+ * Values for led_state
+ */
+#define	ENVMON_LED_OFF		0
+#define	ENVMON_LED_ON		1
+#define	ENVMON_LED_BLINKING	2
+#define	ENVMON_LED_FLASHING	3
+
+/*
+ * Values for the hue of the leds
+ */
+#define	ENVMON_LED_CLR_NONE	((int8_t)(-1))
+#define	ENVMON_LED_CLR_ANY	0
+#define	ENVMON_LED_CLR_WHITE	1
+#define	ENVMON_LED_CLR_BLUE	2
+#define	ENVMON_LED_CLR_GREEN	3
+#define	ENVMON_LED_CLR_AMBER	4
+#define	ENVMON_LED_CLR_RED	5
+
+typedef struct {
+	envmon_handle_t		id;
+	uint16_t		sensor_status;
+	int8_t			led_state;
+	int8_t			led_color;
+	envmon_handle_t		next_id;
+} envmon_led_info_t;
+
+typedef struct {
+	envmon_handle_t		id;
+	int8_t			led_state;
+} envmon_led_ctl_t;
+
+/*
+ * Values for alarm_state
+ */
+#define	ENVMON_ALARM_OFF	0
+#define	ENVMON_ALARM_ON		1
+
+typedef struct {
+	envmon_handle_t		id;
+	uint16_t		sensor_status;
+	int8_t			alarm_state;
+	envmon_handle_t		next_id;
+} envmon_alarm_info_t;
+
+typedef struct {
+	envmon_handle_t		id;
+	int8_t			alarm_state;
+} envmon_alarm_ctl_t;
+
+/*
+ * Values for fru_status
+ */
+#define	ENVMON_FRU_NOT_PRESENT	0
+#define	ENVMON_FRU_PRESENT	1
+#define	ENVMON_FRU_FAULT	2
+#define	ENVMON_FRU_DOWNLOAD	3	/* flash update or download active */
+
+typedef struct {
+	envmon_handle_t		id;
+	uint8_t			sensor_status;
+	uint8_t			fru_status;
+	envmon_handle_t		next_id;
+} envmon_hpu_t;
+
+/*
+ * env_sysinto_t is used to return limits on various item types
+ */
+typedef struct {
+	uint16_t	maxVoltSens;	/* max number of voltage sensors */
+	uint16_t	maxVoltInd;	/* max number of voltage indicators */
+	uint16_t	maxAmpSens;	/* max number of current sensors */
+	uint16_t	maxAmpInd;	/* max number of circuit breakers */
+	uint16_t	maxTempSens;	/* max number of temperature sensors */
+	uint16_t	maxTempInd;	/* max number of temp'r indicators */
+	uint16_t	maxFanSens;	/* max number of fan speed sensors */
+	uint16_t	maxFanInd;	/* max number of fan indicators */
+	uint16_t	maxLED;		/* max number of LEDs */
+	uint16_t	maxHPU;		/* max number of Hot Pluggable Units */
+} envmon_sysinfo_t;
+
+/*
+ * envmon_keysw_t is used to return the current value of the
+ * keyswitch (if fitted)
+ */
+typedef enum envmon_keysw_pos {
+	ENVMON_KEYSW_POS_UNKNOWN	= 0,
+	ENVMON_KEYSW_POS_NORMAL,
+	ENVMON_KEYSW_POS_DIAG,
+	ENVMON_KEYSW_POS_LOCKED,
+	ENVMON_KEYSW_POS_OFF
+} envmon_keysw_pos_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_ENVMON_H */
diff --git a/usr/src/uts/sun4u/sys/errclassify.h b/usr/src/uts/sun4u/sys/errclassify.h
new file mode 100644
index 0000000000..0370f2ad17
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/errclassify.h
@@ -0,0 +1,278 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_ERRCLASSIFY_H
+#define	_SYS_ERRCLASSIFY_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifndef	_ASM
+
+#include <sys/errorq.h>
+
+/*
+ * Note that the order in the following must be kept in sync with that
+ * in the sun4u DE cmd_memerr.c and with the cetypes array of us3_common.c
+ */
+typedef enum {
+	/*
+	 * The first byte (256 values) is for type and can be sequential.
+	 */
+	CE_DISP_UNKNOWN,
+	CE_DISP_INTERMITTENT,
+	CE_DISP_POSS_PERS,
+	CE_DISP_PERS,
+	CE_DISP_LEAKY,
+	CE_DISP_POSS_STICKY,
+	CE_DISP_STICKY,
+	/*
+	 * The next byte encodes the next action as a bitmask
+	 */
+	CE_ACT_DONE = 0x100,
+	CE_ACT_LKYCHK = 0x200,
+	CE_ACT_PTNRCHK = 0x400,
+	/*
+	 * Keep this as the last entry.  Not all entries of the type lookup
+	 * table are used and this value is the "uninitialized" pattern.
+	 */
+	CE_DISP_BAD = 0xbadbad1
+} ce_dispact_t;
+
+/*
+ * Extract disposition or action from a ce_dispact_t
+ */
+#define	CE_DISP(dispact) \
+	(dispact & 0xff)
+#define	CE_ACT(dispact) \
+	(dispact & 0xff00)
+
+/*
+ * Short string names for classification types.
+ */
+#define	CE_DISP_DESC_U		"U"
+#define	CE_DISP_DESC_I		"I"
+#define	CE_DISP_DESC_PP		"PP"
+#define	CE_DISP_DESC_P		"P"
+#define	CE_DISP_DESC_L		"L"
+#define	CE_DISP_DESC_PS		"PS"
+#define	CE_DISP_DESC_S		"S"
+
+/*
+ * Various sun4u CPU types use different Ecache state encodings.
+ * For CE classification the following unified scheme is used.
+ */
+#define	EC_STATE_M		0x4
+#define	EC_STATE_O		0x3
+#define	EC_STATE_E		0x2
+#define	EC_STATE_S		0x1
+#define	EC_STATE_I		0x0
+
+/*
+ * Macros to generate the initial CE classification table (in both kernel and
+ * userland).  An array size CE_INITDISPTBL_SIZE of ce_dispact_t should be
+ * defined and passed by name to ECC_INITDISPTBL_POPULATE which will populate
+ * the array slots that are use and set the unused ones to CE_DISP_BAD.
+ *
+ * To perform a lookup use CE_DISPACT passing the name of the same
+ * array and the afarmatch, ecstate, ce1 and ce2 information.
+ *
+ * Other macros defined here should not be used directly.
+ *
+ * CE_INITDISPTBL_INDEX will generate an index as follows:
+ *
+ *	<5>	afar match
+ *	<4:2>	line state
+ *	<1>	ce2 - CE seen on lddphys of scrub algorithm (after writeback)
+ *	<0>	ce1 - CE seen on CASXA of scrub algorithm (before writeback)
+ *
+ * When the afar does not match line state must be zero.
+ */
+#define	CE_INITDISPTBL_SIZE	(1 << 6)
+#define	CE_INITDISPTBL_INDEX(afarmatch, ecstate, ce1, ce2) \
+	((afarmatch) << 5 | (ecstate) << 2 | (ce2) << 1 | (ce1))
+
+#define	CE_DISPACT(array, afarmatch, ecstate, ce1, ce2) \
+	(array[CE_INITDISPTBL_INDEX(afarmatch, ecstate, ce1, ce2)])
+
+#define	CE_INITDISPTBL_POPULATE(a)					\
+{									\
+	int i;								\
+	for (i = 0; i < CE_INITDISPTBL_SIZE; ++i)			\
+		a[i] = CE_DISP_BAD;					\
+/*									\
+ *	   afar  ec	      ce1  ce2	initial disp and next action	\
+ *	  match  state							\
+ */									\
+CE_DISPACT(a, 0, 0,		0, 0) = CE_DISP_UNKNOWN | CE_ACT_DONE; \
+CE_DISPACT(a, 0, 0,		0, 1) = CE_DISP_POSS_STICKY | CE_ACT_PTNRCHK; \
+CE_DISPACT(a, 0, 0,		1, 0) = CE_DISP_POSS_PERS | CE_ACT_LKYCHK; \
+CE_DISPACT(a, 0, 0,		1, 1) = CE_DISP_POSS_STICKY | CE_ACT_PTNRCHK; \
+CE_DISPACT(a, 1, EC_STATE_M,	0, 0) = CE_DISP_UNKNOWN | CE_ACT_DONE; \
+CE_DISPACT(a, 1, EC_STATE_M,	0, 1) = CE_DISP_UNKNOWN | CE_ACT_DONE; \
+CE_DISPACT(a, 1, EC_STATE_M,	1, 0) = CE_DISP_UNKNOWN | CE_ACT_DONE; \
+CE_DISPACT(a, 1, EC_STATE_M,	1, 1) = CE_DISP_POSS_STICKY | CE_ACT_PTNRCHK; \
+CE_DISPACT(a, 1, EC_STATE_O,	0, 0) = CE_DISP_UNKNOWN | CE_ACT_DONE; \
+CE_DISPACT(a, 1, EC_STATE_O,	0, 1) = CE_DISP_UNKNOWN | CE_ACT_DONE; \
+CE_DISPACT(a, 1, EC_STATE_O,	1, 0) = CE_DISP_UNKNOWN | CE_ACT_DONE; \
+CE_DISPACT(a, 1, EC_STATE_O,	1, 1) = CE_DISP_POSS_STICKY | CE_ACT_PTNRCHK; \
+CE_DISPACT(a, 1, EC_STATE_E,	0, 0) = CE_DISP_INTERMITTENT | CE_ACT_DONE; \
+CE_DISPACT(a, 1, EC_STATE_E,	0, 1) = CE_DISP_UNKNOWN | CE_ACT_DONE; \
+CE_DISPACT(a, 1, EC_STATE_E,	1, 0) = CE_DISP_POSS_PERS | CE_ACT_LKYCHK; \
+CE_DISPACT(a, 1, EC_STATE_E,	1, 1) = CE_DISP_POSS_STICKY | CE_ACT_PTNRCHK; \
+CE_DISPACT(a, 1, EC_STATE_S,	0, 0) = CE_DISP_INTERMITTENT | CE_ACT_DONE; \
+CE_DISPACT(a, 1, EC_STATE_S,	0, 1) = CE_DISP_POSS_STICKY | CE_ACT_PTNRCHK; \
+CE_DISPACT(a, 1, EC_STATE_S,	1, 0) = CE_DISP_POSS_PERS | CE_ACT_LKYCHK; \
+CE_DISPACT(a, 1, EC_STATE_S,	1, 1) = CE_DISP_POSS_STICKY | CE_ACT_PTNRCHK; \
+CE_DISPACT(a, 1, EC_STATE_I,	0, 0) = CE_DISP_UNKNOWN | CE_ACT_DONE; \
+CE_DISPACT(a, 1, EC_STATE_I,	0, 1) = CE_DISP_POSS_STICKY | CE_ACT_PTNRCHK; \
+CE_DISPACT(a, 1, EC_STATE_I,	1, 0) = CE_DISP_POSS_PERS | CE_ACT_LKYCHK; \
+CE_DISPACT(a, 1, EC_STATE_I,	1, 1) = CE_DISP_POSS_STICKY | CE_ACT_PTNRCHK; \
+}
+
+#endif	/* !_ASM */
+
+/*
+ * Legacy error type names corresponding to the flt_status bits
+ */
+#define	ERR_TYPE_DESC_INTERMITTENT	"Intermittent"
+#define	ERR_TYPE_DESC_PERSISTENT	"Persistent"
+#define	ERR_TYPE_DESC_STICKY		"Sticky"
+#define	ERR_TYPE_DESC_UNKNOWN		"Unknown"
+
+/*
+ * flt_disp for a CE will record all scrub test data for the extended
+ * classification attempt.
+ *
+ * --------------------------------------------------------------------------
+ * |            | partner |   |          | leaky   | partner | detector     |
+ * | partner id | type    | - | skipcode | results | results | results      |
+ * |63	      32|31     30|   |27      24|23     16|15      8|7            0|
+ * --------------------------------------------------------------------------
+ */
+#define	CE_XDIAG_DTCRMASK		0xffULL
+#define	CE_XDIAG_PTNRSHIFT		8
+#define	CE_XDIAG_PTNRMASK		(0xffULL << CE_XDIAG_PTNRSHIFT)
+#define	CE_XDIAG_LKYSHIFT		16
+#define	CE_XDIAG_LKYMASK		(0xffULL << CE_XDIAG_LKYSHIFT)
+#define	CE_XDIAG_SKIPCODESHIFT		24
+#define	CE_XDIAG_SKIPCODEMASK		(0xfULL << CE_XDIAG_SKIPCODESHIFT)
+#define	CE_XDIAG_PTNRTYPESHIFT		30
+#define	CE_XDIAG_PTNRTYPEMASK		(0x3ULL << CE_XDIAG_PTNRTYPESHIFT)
+#define	CE_XDIAG_PTNRIDSHIFT		32
+
+/*
+ * Given a CE flt_disp set the given field
+ */
+#define	CE_XDIAG_SETPTNRID(disp, id) \
+	((disp) |= (uint64_t)(id) << CE_XDIAG_PTNRIDSHIFT)
+#define	CE_XDIAG_SETPTNRTYPE(disp, type) \
+	((disp) |= (uint64_t)type << CE_XDIAG_PTNRTYPESHIFT)
+#define	CE_XDIAG_SETSKIPCODE(disp, code) \
+	((disp) |= (uint64_t)code << CE_XDIAG_SKIPCODESHIFT)
+#define	CE_XDIAG_SETLKYINFO(disp, result) \
+	((disp) |= (uint64_t)result << CE_XDIAG_LKYSHIFT)
+#define	CE_XDIAG_SETPTNRINFO(disp, result) \
+	((disp) |= (uint64_t)result << CE_XDIAG_PTNRSHIFT)
+#define	CE_XDIAG_SETDTCRINFO(disp, result) \
+	((disp) |= (uint64_t)result)
+
+/*
+ * Given a CE flt_disp extract the requested component
+ */
+#define	CE_XDIAG_DTCRINFO(disp)	((disp) & CE_XDIAG_DTCRMASK)
+#define	CE_XDIAG_PTNRINFO(disp)	(((disp) & CE_XDIAG_PTNRMASK) >> \
+    CE_XDIAG_PTNRSHIFT)
+#define	CE_XDIAG_LKYINFO(disp)	(((disp) & CE_XDIAG_LKYMASK) >> \
+    CE_XDIAG_LKYSHIFT)
+#define	CE_XDIAG_SKIPCODE(disp)	(((disp) & CE_XDIAG_SKIPCODEMASK) >> \
+    CE_XDIAG_SKIPCODESHIFT)
+#define	CE_XDIAG_PTNRTYPE(disp)	(((disp) & CE_XDIAG_PTNRTYPEMASK) >> \
+    CE_XDIAG_PTNRTYPESHIFT)
+#define	CE_XDIAG_PTNRID(disp)	((disp) >> CE_XDIAG_PTNRIDSHIFT)
+
+/*
+ * Format of individual detector/partner/leaky test results.  CE_XDIAG_EXTALG
+ * in the detector case indicates that the extended classification algorithm
+ * has been applied;  common code uses this to distinguish between old and new.
+ * In the partner check and leaky check cases CE_XDIAG_EXTALG is used to
+ * indicate that the given test has run and recorded its results in its
+ * result field.
+ */
+#define	CE_XDIAG_STATE_MASK	0x7	/* Low 3 bits are for MOESI state */
+#define	CE_XDIAG_AFARMATCH	0x08	/* Line at e$ index matched AFAR */
+#define	CE_XDIAG_NOLOGOUT	0x10	/* Logout data unavailable */
+#define	CE_XDIAG_CE1		0x20	/* CE logged on casx during scrub */
+#define	CE_XDIAG_CE2		0x40	/* CE logged on post-scrub reread */
+#define	CE_XDIAG_EXTALG		0x80	/* Extended algorithm applied */
+
+/*
+ * Extract classification information for detector/partner.  Expects
+ * a value from one of CE_XDIAG_{DTCR,PTNR,LKY}_INFO.
+ */
+#define	CE_XDIAG_AFARMATCHED(c)		(((c) & CE_XDIAG_AFARMATCH) != 0)
+#define	CE_XDIAG_LOGOUTVALID(c)		(((c) & CE_XDIAG_NOLOGOUT) == 0)
+#define	CE_XDIAG_CE1SEEN(c)		(((c) & CE_XDIAG_CE1) != 0)
+#define	CE_XDIAG_CE2SEEN(c)		(((c) & CE_XDIAG_CE2) != 0)
+#define	CE_XDIAG_STATE(c)		(CE_XDIAG_AFARMATCHED(c) ? \
+	((c) & CE_XDIAG_STATE_MASK) : 0)
+#define	CE_XDIAG_EXT_ALG_APPLIED(c)	(((c) & CE_XDIAG_EXTALG) != 0)
+
+/*
+ * A leaky or partner test is considered valid if the line was not present
+ * in cache, or was present but Invalid, at the time of the additional scrub.
+ */
+#define	CE_XDIAG_TESTVALID(c) (CE_XDIAG_EXT_ALG_APPLIED(c) && \
+	(!CE_XDIAG_AFARMATCHED(c) || CE_XDIAG_STATE(c) == EC_STATE_I))
+
+/*
+ * Skipcodes - reasons for not applying extended diags; 4 bits
+ */
+#define	CE_XDIAG_SKIP_NOPP		0x1	/* Can't lookup page pointer */
+#define	CE_XDIAG_SKIP_PAGEDET		0x2	/* Page deteriorating/retired */
+#define	CE_XDIAG_SKIP_NOTMEM		0x3	/* AFAR is not memory */
+#define	CE_XDIAG_SKIP_DUPFAIL		0x4	/* errorq recirculate failed */
+#define	CE_XDIAG_SKIP_NOPTNR		0x5	/* no suitable partner avail */
+#define	CE_XDIAG_SKIP_UNIPROC		0x6	/* test needs 2 or more cpus */
+#define	CE_XDIAG_SKIP_ACTBAD		0x7	/* bad action lookup - bug */
+#define	CE_XDIAG_SKIP_NOSCRUB		0x8	/* detector did not scrub */
+
+/*
+ * Partner type information.
+ */
+#define	CE_XDIAG_PTNR_REMOTE	0x0	/* partner in different lgroup */
+#define	CE_XDIAG_PTNR_LOCAL	0x1	/* partner in same lgroup */
+#define	CE_XDIAG_PTNR_SIBLING	0x2	/* partner is a sibling core */
+#define	CE_XDIAG_PTNR_SELF	0x3	/* partnered self */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_ERRCLASSIFY_H */
diff --git a/usr/src/uts/sun4u/sys/fc_plat.h b/usr/src/uts/sun4u/sys/fc_plat.h
new file mode 100644
index 0000000000..4cfd8de931
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/fc_plat.h
@@ -0,0 +1,102 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 1998 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SYS_FC_PLAT_H
+#define	_SYS_FC_PLAT_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/inttypes.h>
+#include <sys/obpdefs.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Platform specific definitions for the fcode interpreter and driver.
+ * Define the cell size for the implementation.
+ *
+ * These definitions are appropriate for SPARC V9.
+ */
+
+/*
+ * The cell size is based on the cell size of the underlying "firmware"
+ * implementation.  NB: FCode is really a 32-bit language, but we still
+ * define our interfaces in terms of the underlying cell size.
+ */
+
+typedef unsigned long long fc_cell_t;
+
+/*
+ * common typedef for phandles accross the interface.
+ */
+typedef uint32_t fc_phandle_t;
+
+/*
+ * Handy macros for converting from an fc_cell_t to an integral type
+ * These are useful because arguments and results are always passed
+ * in an array of fc_cell_t's.
+ */
+
+#define	fc_ptr2cell(p)		((fc_cell_t)((uintptr_t)((void *)(p))))
+#define	fc_int2cell(i)		((fc_cell_t)((int)(i)))
+#define	fc_uint2cell(u)		((fc_cell_t)((unsigned int)(u)))
+#define	fc_uint32_t2cell(u)	((fc_cell_t)((unsigned int)((uint32_t)(u))))
+#define	fc_uint16_t2cell(w)	((fc_cell_t)((unsigned int)((uint16_t)(w))))
+#define	fc_uint8_t2cell(b)	((fc_cell_t)((unsigned int)((uint8_t)(b))))
+#define	fc_size2cell(u)		((fc_cell_t)((size_t)(u)))
+#define	fc_ssize2cell(i)	((fc_cell_t)((ssize_t)(i)))
+#define	fc_phandle2cell(ph)	((fc_cell_t)((unsigned int)((phandle_t)(ph))))
+#define	fc_dnode2cell(d)	((fc_cell_t)((unsigned int)((dnode_t)(d))))
+#define	fc_ull2cell_high(ll)	(0LL)
+#define	fc_ull2cell_low(ll)	((fc_cell_t)(ll))
+#define	fc_uintptr2cell(i)	((fc_cell_t)((uintptr_t)(i)))
+#define	fc_uchar2cell(c)	((fc_cell_t)((unsigned char)(c)))
+#define	fc_ushort2cell(w)	((fc_cell_t)((unsigned short)(w)))
+#define	fc_ihandle2cell(h)	((fc_cell_t)((fc_ihandle_t)(h)))
+
+#define	fc_cell2ptr(p)		((void *)((fc_cell_t)(p)))
+#define	fc_cell2int(i)		((int)((fc_cell_t)(i)))
+#define	fc_cell2uint(u)		((unsigned int)((fc_cell_t)(u)))
+#define	fc_cell2uint32_t(u)	((uint32_t)((fc_cell_t)(u)))
+#define	fc_cell2uint16_t(w)	((uint16_t)((fc_cell_t)(w)))
+#define	fc_cell2uint8_t(b)	((uint8_t)((fc_cell_t)(b)))
+#define	fc_cell2size(u)		((size_t)((fc_cell_t)(u)))
+#define	fc_cell2ssize(i)	((ssize_t)((fc_cell_t)(i)))
+#define	fc_cell2phandle(ph)	((phandle_t)((fc_cell_t)(ph)))
+#define	fc_cell2dnode(d)	((dnode_t)((fc_cell_t)(d)))
+#define	fc_cells2ull(h, l)	((unsigned long long)(fc_cell_t)(l))
+#define	fc_cell2uintptr(i)	((uintptr_t)((fc_cell_t)(i)))
+#define	fc_cell2uchar(c)	((unsigned char)(fc_cell_t)(c))
+#define	fc_cell2ushort(w)	((unsigned short)(fc_cell_t)(w))
+#define	fc_cell2ihandle(h)	((fc_ihandle_t)(fc_cell_t)(h))
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _SYS_FC_PLAT_H */
diff --git a/usr/src/uts/sun4u/sys/fctest.h b/usr/src/uts/sun4u/sys/fctest.h
new file mode 100644
index 0000000000..82067a4a84
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/fctest.h
@@ -0,0 +1,72 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SYS_FCTEST_H
+#define	_SYS_FCTEST_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * /dev/fctest ioctls ... this is not part of the efcode project.
+ * This is a prototype test driver, used to drive the prototype
+ * only, and is not needed with hot-plug hardware and real hot-plug
+ * capable code.
+ */
+
+#define	FCTIOC			(0xfd<<8)
+
+/*
+ * FCT_SET_DEBUG_LVL: 'arg' is an intptr_t.
+ * Set fcode_debug to the value in intptr_t 'arg'.
+ */
+#define	FCT_SET_DEBUG_LVL	(FCTIOC | 1)
+
+/*
+ * FCT_SET_DEVICE: 'arg' is a pointer to a string.  The string
+ * is taken as the pathname of the device to be configured.
+ * The driver attempts to locate the device in the device tree,
+ * and uses the parent of the device as the attachment point.
+ * The device has to exist in the firmware's device tree.
+ */
+#define	FCT_SET_DEVICE		(FCTIOC | 2)
+
+/*
+ * FCT_UNCONFIGURE: 'arg' is ignored. Unconfigures the device
+ * given in the FCT_SET_DEVICE ioctl.
+ */
+#define	FCT_UNCONFIGURE		(FCTIOC | 3)
+#define	FCT_CONFIGURE		(FCTIOC | 4)
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_FCTEST_H */
diff --git a/usr/src/uts/sun4u/sys/fpras_impl.h b/usr/src/uts/sun4u/sys/fpras_impl.h
new file mode 100644
index 0000000000..2de8188451
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/fpras_impl.h
@@ -0,0 +1,336 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_FPRAS_IMPL_H
+#define	_SYS_FPRAS_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/fpras.h>
+
+#if !defined(_ASM)
+#include <sys/types.h>
+#else
+#include <sys/intreg.h>
+#include <sys/errno.h>
+#endif	/* _ASM */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * sun4u/cheetah fpRAS implementation.  Arrays etc will be allocated in sun4u
+ * post_startup() if fpras_implemented is set.  This file may belong at
+ * the cpu level (eg, cheetahregs.h) but most of it should be common
+ * when fpRAS support is added for additional cpu types so we introduce
+ * it at the sun4u level (and set fpras_implemented in cpu_setup).
+ *
+ * If fpRAS is implemented on a sun4u/cpu combination that does not use
+ * an ASR for %stick then the FPRAS_INTERVAL macro will need some
+ * modification.
+ */
+
+/*
+ * Upper bound for check frequency per cpu and per operation.  For example, if
+ * this is 100 then for cpuid N performing a bcopy if that cpu has not
+ * performed a checked bcopy in the the last 1/100th of a second then
+ * we'll check the current operation.  A value of 0 will check every operation.
+ * Modifying fpras_frequency from its default is not recommended.
+ * fpras_interval is computed from fpras_frequency.
+ */
+#if !defined(_ASM)
+extern int fpras_frequency;
+extern int64_t fpras_interval;
+#endif	/* _ASM */
+#define	FPRAS_DEFAULT_FREQUENCY	100
+
+#if !defined(_ASM)
+
+/*
+ * Structure of a check function.  The preamble prepares registers for the
+ * upcoming calculation that is performed in blk0 and blk1.  One of those
+ * blocks will be rewritten as part of an FPRAS_REWRITE operation.  Finally
+ * the result checked in chkresult should be as predetermined, and we should
+ * return zero on success and nonzero on failure.  If an illegal instruction
+ * is encountered in the execution of the check function then we trampoline
+ * to the final three instructions to return a different value.
+ *
+ * Note that the size of this structure is a power of 2 as is the
+ * size of a struct fpras_chkfngrp.  The asm macros below rely on this
+ * in performing bit shifts instead of mulx.
+ */
+struct fpras_chkfn {
+	uint32_t	fpras_preamble[16];
+	uint32_t	fpras_blk0[16];
+	uint32_t	fpras_blk1[16];
+	uint32_t	fpras_chkresult[13];
+	uint32_t	fpras_trampoline[3];
+};
+
+/*
+ * Check function constructed to match a struct fpras_chkfn
+ */
+extern int fpras_chkfn_type1(void);
+
+/*
+ * A group of check functions, one for each operation type.  These will
+ * be the check functions for copy operations on a particular processor.
+ */
+struct fpras_chkfngrp {
+	struct fpras_chkfn fpras_fn[FPRAS_NCOPYOPS];
+};
+
+/*
+ * Where we store check functions for execution.  Indexed by cpuid and
+ * function within that for cacheline friendliness.  Startup code
+ * copies the check function into this array.  The fpRAS mechanism will
+ * rewrite one of fpras_blk0 or fpras_blk1 before calling the check function
+ * for a cpuid & copy function combination.
+ */
+extern struct fpras_chkfngrp *fpras_chkfngrps;
+
+#endif	/* !_ASM */
+
+#if defined(_ASM)
+
+/* BEGIN CSTYLED */
+
+/*
+ * The INTERVAL macro decides whether we will check this copy operation,
+ * based on performing no more than 1 check per cpu & operation in a specified
+ * time interval.  If it decides to abort this check (ie, we have checked
+ * recently) then it returns doex NULL, otherwise doex is the address of the
+ * check function to execute later.  Migration must have been prevented before
+ * calling this macro.  Args:
+ *
+ *	operation (immediate): one of FPRAS_BCOPY etc
+ *	blk (immediate): which block to copy
+ *	doex (register): register in which to return check function address
+ *	tmp1 (register): used for scratch, not preserved
+ *	tmp2 (register): used for scratch, not preserved
+ *	tmp3 (register): used for scratch, not preserved
+ *	tmp4 (register): used for scratch, not preserved
+ *	label: free local numeric label
+ */
+
+#define	FPRAS_INTERVAL(operation, blk, doex, tmp1, tmp2, tmp3, tmp4, label) \
+	sethi	%hi(fpras_interval), tmp1				;\
+	ldx	[tmp1 + %lo(fpras_interval)], tmp1			;\
+	brlz,pn	tmp1, label/**/f	/* not initialized? */		;\
+	  clr	doex							;\
+	sethi	%hi(fpras_disableids), tmp2				;\
+	ld	[tmp2 + %lo(fpras_disableids)], tmp2			;\
+	mov	0x1, tmp3						;\
+	sll	tmp3, operation, tmp3					;\
+	btst	tmp3, tmp2						;\
+	bnz,a,pn %icc, label/**/f	/* disabled for this op? */	;\
+	  nop								;\
+	set	fpras_chkfn_type1, tmp2					;\
+	prefetch [tmp2 + (FPRAS_BLK0 + blk * 64)], #one_read		;\
+	ldn	[THREAD_REG + T_CPU], tmp2				;\
+	ldn	[tmp2 + CPU_PRIVATE], tmp2				;\
+	brz,pn	tmp2, label/**/f	/* early in startup? */		;\
+	  mov	operation, tmp3						;\
+	sll	tmp3, 3, tmp3						;\
+	set	CHPR_FPRAS_TIMESTAMP, tmp4				;\
+	add	tmp2, tmp4, tmp2					;\
+	add	tmp2, tmp3, tmp2	/* keep ptr for update */	;\
+	ldx	[tmp2], tmp3		/* last timestamp */		;\
+	rd	STICK, doex		/* doex is a scratch here */	;\
+	sub	doex, tmp3, tmp4	/* delta since last check */	;\
+	cmp	tmp4, tmp1		/* compare delta to interval */	;\
+	blu,a,pn %xcc, label/**/f					;\
+	  clr	doex							;\
+	stx	doex, [tmp2]		/* updated timestamp */		;\
+	ldn	[THREAD_REG + T_CPU], tmp1				;\
+	ld	[tmp1 + CPU_ID], tmp1					;\
+	sethi	%hi(fpras_chkfngrps), doex				;\
+	ldn	[doex + %lo(fpras_chkfngrps)], doex			;\
+	sll	tmp1, FPRAS_CHKFNGRP_SIZE_SHIFT, tmp1			;\
+	add	doex, tmp1, doex					;\
+	mov	operation, tmp1						;\
+	sll	tmp1, FPRAS_CHKFN_SIZE_SHIFT, tmp1			;\
+	add	doex, tmp1, doex	/* address of check function */	;\
+label:
+
+/*
+ * The REWRITE macro copies an instruction block from fpras_chkfn_type1
+ * into a per-cpu fpras check function.
+ * If doex is NULL it must not attempt any copy, and must leave doex NULL.
+ * CPU migration of this thread must be prevented before we call this macro.
+ * We must have checked for fp in use (and saved state, including the
+ * quadrant of registers indicated by the fpq argument and fp enabled before
+ * using this macro.  Args:
+ *
+ *	blk (immediate): as above
+ *	doex (register): register in which to return check function addr
+ *	[fpq (fp register): frf quadrant to be used (%f0/%f16/%f32/%f48)]
+ *		This is used on type 1 rewrite only - on others the
+ *		quadrant is implicit/hardcoded in the macro name.
+ *	tmp1 (register): used for scratch, not preserved
+ *	label1: free local numeric label
+ *	[label2: free local numeric label]
+ *		This is used in type 2 only.
+ *
+ * Note that the REWRITE macros do not perform a flush instruction -
+ * flush is not necessary on Cheetah derivative processors in which
+ * i$ snoops for invalidations.
+ */
+
+/*
+ * Rewrite type 1 will work with any instruction pattern - it just block
+ * loads and block stores the given block.  A membar after block store
+ * forces the block store to complete before upcoming reuse of the
+ * fpregs in the block;  the block load is blocking on sun4u/cheetah
+ * so no need for a membar after it.
+ */
+
+#define	FPRAS_REWRITE_TYPE1(blk, doex, fpq, tmp1, label)	\
+	brz,pn  doex, label/**/f				;\
+	  sethi	%hi(fpras_chkfn_type1), tmp1			;\
+	add	tmp1, %lo(fpras_chkfn_type1), tmp1		;\
+	add	tmp1, FPRAS_BLK0 + blk * 64, tmp1		;\
+	ldda	[tmp1]ASI_BLK_P, fpq				;\
+	add	doex, FPRAS_BLK0 + blk * 64, tmp1		;\
+	stda	fpq, [tmp1]ASI_BLK_P				;\
+	membar	#Sync						;\
+label:
+
+/*
+ * Rewrite type 2 will only work with instruction blocks that satisfy
+ * this particular repeat pattern.  Note that the frf quadrant to
+ * use is implicit in the macro name and had better match what the
+ * copy function is preserving.
+*
+ * The odd looking repetition in the initial loop is designed to open
+ * up boths paths from prefetch cache to the frf - unrolling the loop
+ * would defeat this.  In addition we perform idempotent faligndata
+ * manipulations using %tick as a randomly aligned address (this only
+ * works for address that aren't doubleword aligned).
+ */
+#define	FPRAS_REWRITE_TYPE2Q1(blk, doex, tmp1, tmp2, label1, label2)	\
+	brz,pn	doex, label1/**/f					;\
+	  mov	0x2, tmp1						;\
+	set	fpras_chkfn_type1, tmp2					;\
+label2:									;\
+	deccc		tmp1						;\
+	ldd		[tmp2 + (FPRAS_BLK0 + blk * 64)], %f4		;\
+	ldd		[tmp2 + (FPRAS_BLK0 + blk * 64) + 8], %f2	;\
+	bnz,a,pt	%icc, label2/**/b				;\
+	  fsrc1		%f4, %f0					;\
+	rdpr		%tick, tmp1					;\
+	fsrc1		%f4, %f8					;\
+	fsrc1		%f2, %f10					;\
+	btst		0x7, tmp1					;\
+	alignaddr	tmp1, %g0, %g0	/* changes %gsr */		;\
+	bz,pn		%icc, label2/**/f				;\
+	  faligndata	%f2, %f4, %f6					;\
+	faligndata	%f0, %f2, %f12					;\
+	alignaddrl	tmp1, %g0, %g0					;\
+	faligndata	%f12, %f6, %f6					;\
+label2:									;\
+	add		doex, FPRAS_BLK0 + blk * 64, tmp1		;\
+	fsrc2		%f8, %f12					;\
+	fsrc1		%f6, %f14					;\
+	stda		%f0, [tmp1]ASI_BLK_P				;\
+	membar		#Sync						;\
+label1:
+
+#define	FPRAS_REWRITE_TYPE2Q2(blk, doex, tmp1, tmp2, label1, label2)	\
+	brz,pn	doex, label1/**/f					;\
+	  mov	0x2, tmp1						;\
+	set	fpras_chkfn_type1, tmp2					;\
+label2:									;\
+	deccc		tmp1						;\
+	ldd		[tmp2 + (FPRAS_BLK0 + blk * 64)], %f20	;\
+	ldd		[tmp2 + (FPRAS_BLK0 + blk * 64) + 8], %f18	;\
+	bnz,a,pt	%icc, label2/**/b				;\
+	  fsrc1		%f20, %f16					;\
+	rdpr		%tick, tmp1					;\
+	fsrc1		%f20, %f24					;\
+	fsrc1		%f18, %f26					;\
+	btst		0x7, tmp1					;\
+	alignaddr	tmp1, %g0, %g0	/* changes %gsr */		;\
+	bz,pn		%icc, label2/**/f				;\
+	  faligndata	%f18, %f20, %f22				;\
+	faligndata	%f16, %f18, %f28				;\
+	alignaddrl	tmp1, %g0, %g0					;\
+	faligndata	%f28, %f22, %f22				;\
+label2:									;\
+	add		doex, FPRAS_BLK0 + blk * 64, tmp1		;\
+	fsrc2		%f24, %f28					;\
+	fsrc1		%f22, %f30					;\
+	stda		%f16, [tmp1]ASI_BLK_P				;\
+	membar		#Sync						;\
+label1:
+
+/*
+ * The CHECK macro takes the 'doex' address of the check function to
+ * execute and jumps to it (if not NULL). If the check function returns
+ * nonzero then the check has failed and the CHECK macro must initiate
+ * an appropriate failure action.  Illegal instruction trap handlers
+ * will also recognise traps in this PC range as fp failures.  Thread
+ * migration must only be reallowed after completion of this check.  The
+ * CHECK macro should be treated as a CALL/JMPL - output registers are
+ * forfeit after using it.  If the call to fpras_failure returns
+ * (it may decide to panic) then invoke lofault handler (which must exist)
+ * to return an error (be sure to use this macro before restoring original
+ * lofault setup in copy functions).  Note that the lofault handler is the
+ * copyops aware proxy handler which will perform other tidy up operations
+ * (unbind, fp state restore) that would normally have been done in the tail
+ * of the copy function.
+ *
+ *	operation (immedidate): as above
+ *	doex (register): doex value returned from the REWRITE
+ *	label: free local numeric label
+ */
+
+#define	FPRAS_CHECK(operation, doex, label)				\
+	brz,pn	doex, label/**/f					;\
+	  nop								;\
+	jmpl	doex, %o7						;\
+	  nop								;\
+	cmp	%o0, FPRAS_OK						;\
+	be	%icc, label/**/f					;\
+	  nop								;\
+	mov	%o0, %o1	/* how detected */			;\
+	call	fpras_failure	/* take failure action */		;\
+	  mov	operation, %o0						;\
+	ldn	[THREAD_REG + T_LOFAULT], doex				;\
+	jmp	doex							;\
+	  mov	EFAULT, %g1						;\
+label:
+
+/* END CSTYLED */
+
+#endif	/* _ASM */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_FPRAS_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/gp2cfg.h b/usr/src/uts/sun4u/sys/gp2cfg.h
new file mode 100644
index 0000000000..eb9b541f55
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/gp2cfg.h
@@ -0,0 +1,132 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2000-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_GP2CFG_H
+#define	_SYS_GP2CFG_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * Header file for the Safari Configurator (gptwocfg).
+ */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/safari_pcd.h>
+#include <sys/fcode.h>
+#include <sys/fcgp2.h>
+
+/*
+ * Interfaces exported by Safari Configurator module, kernel/misc/gp2cfg.
+ */
+
+typedef void *gptwocfg_cookie_t;
+typedef void *gptwocfg_ops_cookie_t;
+typedef uint32_t gptwo_aid_t;
+
+gptwocfg_cookie_t gptwocfg_configure(dev_info_t *, spcd_t *, uint_t);
+gptwocfg_cookie_t gptwocfg_unconfigure(dev_info_t *, gptwo_aid_t);
+int gptwocfg_next_node(gptwocfg_cookie_t, dev_info_t *, dev_info_t **);
+void gptwocfg_save_handle(dev_info_t *, fco_handle_t);
+fco_handle_t gptwocfg_get_handle(dev_info_t *);
+
+
+/*
+ * Prototypes for the platform specific functions.
+ */
+
+#define	GP2CFG_SUCCESS	0x00
+#define	GP2CFG_FAILURE	0x01
+
+struct gptwo_phys_spec {
+	uint_t gptwo_phys_hi;	/* child's address, hi word */
+	uint_t gptwo_phys_low;	/* child's address, low word */
+	uint_t gptwo_size_hi;	/* high word of size field */
+	uint_t gptwo_size_low;	/* low word of size field */
+};
+
+typedef struct gptwo_phys_spec gptwo_regspec_t;
+
+
+#define	GP2_VERSION		0
+
+struct gptwo_new_nodes {
+	uint_t		gptwo_version;
+	uint_t		gptwo_number_of_nodes;
+	dev_info_t	*gptwo_nodes[1];
+		/* actual size is gptwo_number_of_nodes */
+};
+
+typedef struct gptwo_new_nodes gptwo_new_nodes_t;
+
+typedef struct gptwocfg_config {
+	uint_t			gptwo_version;
+	dev_info_t		*gptwo_ap;
+	struct gptwocfg_ops	*gptwo_ops;
+	gptwo_aid_t		gptwo_portid;
+	gptwo_new_nodes_t	*gptwo_nodes;
+	struct gptwocfg_config	*gptwo_next;
+} gptwocfg_config_t;
+
+typedef struct gptwocfg_handle_list {
+	dev_info_t			*dip;
+	fco_handle_t			fco_handle;
+	struct gptwocfg_handle_list	*next;
+} gptwocfg_handle_list_t;
+
+#define	GPTWOCFG_OPS_VERSION	0
+
+typedef struct gptwocfg_ops {
+	int	gptwocfg_version;	/* GPTWOCFG_OPS_VERSION */
+	int	gptwocfg_type;		/* SAFPTYPE_xxx */
+	gptwo_new_nodes_t *(*gptwocfg_configure)
+	    (dev_info_t *ap, spcd_t *pcd, gptwo_aid_t id);
+	dev_info_t *(*gptwocfg_unconfigure)
+	    (dev_info_t *dip);
+} gptwocfg_ops_t;
+
+typedef gptwo_new_nodes_t *gptwo_cfgfunc_t(dev_info_t *, spcd_t *, gptwo_aid_t);
+typedef dev_info_t *gptwo_uncfgfunc_t(dev_info_t *);
+void gptwocfg_register_ops(uint_t, gptwo_cfgfunc_t *, gptwo_uncfgfunc_t *);
+void gptwocfg_unregister_ops(uint_t);
+gptwo_new_nodes_t *gptwocfg_allocate_node_list(int);
+void gptwocfg_free_node_list(gptwo_new_nodes_t *);
+void gptwocfg_devi_attach_to_parent(dev_info_t *);
+
+struct gfc_ops_v {
+	char *svc_name;
+	fc_ops_t *f;
+};
+
+extern struct gfc_ops_v gptwo_pov[];
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_GP2CFG_H */
diff --git a/usr/src/uts/sun4u/sys/gpio_87317.h b/usr/src/uts/sun4u/sys/gpio_87317.h
new file mode 100644
index 0000000000..b3e45249eb
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/gpio_87317.h
@@ -0,0 +1,75 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SYS_GPIO_87317_H
+#define	_SYS_GPIO_87317_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+/* ioctl commands - ioctl(..., int request, ...) */
+#define	GPIO_CMD_SET_BITS	0 /* gpio_reg[bank][offset] |= gpio_data */
+#define	GPIO_CMD_CLR_BITS	1 /* gpio_reg[bank][offset] &= ~gpio_data */
+#define	GPIO_CMD_GET		2 /* gpio_data = gpio_reg[bank][offset] */
+#define	GPIO_CMD_SET		3 /* gpio_reg[bank][offset] = gpio_data */
+
+/* SuperIO gpio bank 0 (gpio_bank=0) register offsets (gpio_offset) */
+#define	GPIO_87317_PORT1_DATA		0	/* port 1 data */
+#define	GPIO_87317_PORT1_DIR		1	/* port 1 direction */
+#define	GPIO_87317_PORT1_OUT		2	/* port 1 output type */
+#define	GPIO_87317_PORT1_CTRL		3	/* port 1 pull-up control */
+#define	GPIO_87317_PORT2_DATA		4	/* port 2 data */
+#define	GPIO_87317_PORT2_DIR		5	/* port 2 direction */
+#define	GPIO_87317_PORT2_OUT		6	/* port 2 output type */
+#define	GPIO_87317_PORT2_CTRL		7	/* port 2 pull-up control */
+
+/* SuperIO gpio bank 1 (gpio_bank=1) register offsets (gpio_offset) */
+#define	GPIO_87317_PORT1_LOCK		0	/* port 1 lock */
+#define	GPIO_87317_PORT1_POLARITY	1	/* port 1 polarity */
+#define	GPIO_87317_PORT1_IN2OUT		2	/* port 1 in to out */
+/* offset 3 is reserved */
+#define	GPIO_87317_PORT3_DATA		4	/* port 3 data */
+#define	GPIO_87317_PORT3_DIR		5	/* port 3 direction */
+#define	GPIO_87317_PORT3_OUT		6	/* port 3 output type */
+#define	GPIO_87317_PORT3_CTRL		7	/* port 3 pull-up control */
+
+/* ioctl operation structure - ioctl(..., void *arg) */
+typedef struct gpio_87317_op_s {
+	int	gpio_bank;	/* identify gpio bank: 0 or 1 */
+	uint8_t	gpio_offset;	/* offset of gpio register: 0-7 */
+	uint8_t	gpio_data;	/* bits to set/clear; or data to read/write */
+} gpio_87317_op_t;
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_GPIO_87317_H */
diff --git a/usr/src/uts/sun4u/sys/gptwo_cpu.h b/usr/src/uts/sun4u/sys/gptwo_cpu.h
new file mode 100644
index 0000000000..5d4b8c80d1
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/gptwo_cpu.h
@@ -0,0 +1,49 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SYS_GPTWO_CPU_H
+#define	_SYS_GPTWO_CPU_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * Header file for the CPU component to the Safari Configurator (gptwo_cpu).
+ */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/safari_pcd.h>
+
+gptwocfg_ops_cookie_t gptwocfg_alloc_cpu_ops(int, int);
+gptwo_new_nodes_t *gptwocfg_configure_cpu(dev_info_t *, spcd_t *, uint_t);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_GPTWO_CPU_H */
diff --git a/usr/src/uts/sun4u/sys/grbeep.h b/usr/src/uts/sun4u/sys/grbeep.h
new file mode 100644
index 0000000000..fab8807050
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/grbeep.h
@@ -0,0 +1,128 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2000-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_GRBEEP_H
+#define	_SYS_GRBEEP_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * grbeep.h : Grover beep driver header file.
+ */
+
+/*
+ * beeper start and stop values
+ */
+#define	GRBEEP_START		0x03
+#define	GRBEEP_STOP		0x00
+
+/*
+ * beeper control register value
+ */
+#define	GRBEEP_CONTROL		0xb6
+
+/*
+ * beeper 8354 input frequency is 1.193 Mhz.
+ * The value to be written in the timer
+ * register is the frequency divisor.
+ * The formula to find freq. divisoer would be
+ *
+ * 	divisor = GRBEEP_INPUT_FREQ / freq
+ *
+ */
+#define	GRBEEP_INPUT_FREQ	1193000
+#define	GRBEEP_DIVISOR_MAX	1193000
+#define	GRBEEP_DIVISOR_MIN	18
+
+/* Mode values */
+#define	GRBEEP_ON		0x01
+#define	GRBEEP_OFF		0x00
+
+typedef volatile struct grbeep_freq_regs {
+
+	/* Frequency divisor register */
+	uint8_t		grbeep_freq_regs_divisor;
+
+	/* Freqquency control register */
+	uint8_t		grbeep_freq_regs_control;
+
+} grbeep_freq_regs_t;
+
+
+/*
+ * Beep driver state structure
+ */
+typedef struct grbeep_state {
+
+	/* Dip of grbeep device */
+	dev_info_t		*grbeep_dip;
+
+	/* Frequency control and frequency divisor registers */
+	grbeep_freq_regs_t	*grbeep_freq_regs;
+
+	/* Frequency control and frequency divisor reg handle */
+	ddi_acc_handle_t	grbeep_freq_regs_handle;
+
+	/* Beep start/stop register */
+	uint8_t			*grbeep_start_stop_reg;
+
+	/* Beep start/stop register handle */
+	ddi_acc_handle_t	grbeep_start_stop_reg_handle;
+
+	/* If beeper is active or not */
+	int			grbeep_mode;
+
+	/* Mutex for fields that are mutually exclusively accessible */
+	kmutex_t		grbeep_mutex;
+
+} grbeep_state_t;
+
+#define	GRBEEP_WRITE_FREQ_CONTROL_REG(val) \
+	ddi_put8(grbeeptr->grbeep_freq_regs_handle, \
+	((uint8_t *)&grbeeptr->grbeep_freq_regs->grbeep_freq_regs_control), \
+		((int8_t)(val)))
+
+#define	GRBEEP_WRITE_FREQ_DIVISOR_REG(val) \
+	ddi_put8(grbeeptr->grbeep_freq_regs_handle, \
+	((uint8_t *)&grbeeptr->grbeep_freq_regs->grbeep_freq_regs_divisor), \
+		((int8_t)(val)))
+
+#define	GRBEEP_WRITE_START_STOP_REG(val) \
+	ddi_put8(grbeeptr->grbeep_start_stop_reg_handle, \
+		((uint8_t *)grbeeptr->grbeep_start_stop_reg), \
+		((int8_t)(val)))
+
+#define	GRBEEP_UNIT(dev)	(getminor((dev)))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_GRBEEP_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/adm1031.h b/usr/src/uts/sun4u/sys/i2c/clients/adm1031.h
new file mode 100644
index 0000000000..3de14cf17a
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/adm1031.h
@@ -0,0 +1,103 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 1999-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_ADM1031_H
+#define	_ADM1031_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * This file contains the commands required to read & write to the internal
+ * registers of ADM1031.
+ */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+
+#define	ADM1031_PVT_BASE_IOCTL		(I2C_PVT_BASE_IOCTL + 10)
+
+#define	ADM1031_MANUAL_MODE		0
+#define	ADM1031_AUTO_MODE		1
+
+/*
+ * Commands to be used to access and modify the control
+ * registers of adm1031.
+ */
+#define	ADM1031_GET_STATUS_1		(ADM1031_PVT_BASE_IOCTL + 1)
+#define	ADM1031_GET_STATUS_2		(ADM1031_PVT_BASE_IOCTL + 2)
+#define	ADM1031_GET_DEVICE_ID		(ADM1031_PVT_BASE_IOCTL + 3)
+#define	ADM1031_GET_CONFIG_1		(ADM1031_PVT_BASE_IOCTL + 4)
+#define	ADM1031_GET_CONFIG_2		(ADM1031_PVT_BASE_IOCTL + 5)
+#define	ADM1031_SET_CONFIG_1		(ADM1031_PVT_BASE_IOCTL + 34)
+#define	ADM1031_SET_CONFIG_2		(ADM1031_PVT_BASE_IOCTL + 35)
+
+
+/*
+ * Commands to be used for all fan nodes.
+ */
+#define	ADM1031_GET_FAN_FEATURE		(ADM1031_PVT_BASE_IOCTL + 6)
+#define	ADM1031_GET_FAN_CONFIG		(ADM1031_PVT_BASE_IOCTL + 8)
+#define	ADM1031_GET_FAN_LOW_LIMIT	(ADM1031_PVT_BASE_IOCTL + 9)
+
+
+#define	ADM1031_SET_FAN_FEATURE		(ADM1031_PVT_BASE_IOCTL + 36)
+#define	ADM1031_SET_FAN_FILTER		(ADM1031_PVT_BASE_IOCTL + 38)
+#define	ADM1031_SET_FAN_LOW_LIMIT	(ADM1031_PVT_BASE_IOCTL + 39)
+
+/*
+ * Commands to be used for all temperature nodes.
+ */
+#define	ADM1031_GET_TEMP_MIN_RANGE	(ADM1031_PVT_BASE_IOCTL + 11)
+#define	ADM1031_GET_EXTD_TEMP_RESL	(ADM1031_PVT_BASE_IOCTL + 14)
+#define	ADM1031_GET_TEMP_OFFSET		(ADM1031_PVT_BASE_IOCTL + 15)
+#define	ADM1031_GET_TEMP_HIGH_LIMIT	(ADM1031_PVT_BASE_IOCTL + 18)
+#define	ADM1031_GET_TEMP_LOW_LIMIT	(ADM1031_PVT_BASE_IOCTL + 21)
+#define	ADM1031_GET_TEMP_THERM_LIMIT	(ADM1031_PVT_BASE_IOCTL + 24)
+
+
+#define	ADM1031_SET_TEMP_MIN_RANGE	(ADM1031_PVT_BASE_IOCTL + 41)
+#define	ADM1031_SET_TEMP_OFFSET		(ADM1031_PVT_BASE_IOCTL + 45)
+#define	ADM1031_SET_TEMP_HIGH_LIMIT	(ADM1031_PVT_BASE_IOCTL + 48)
+#define	ADM1031_SET_TEMP_LOW_LIMIT	(ADM1031_PVT_BASE_IOCTL + 51)
+#define	ADM1031_SET_TEMP_THERM_LIMIT	(ADM1031_PVT_BASE_IOCTL + 54)
+
+
+/*
+ * Commands to be used for accessing and modifying
+ * the internal registers of adm1031.
+ */
+#define	ADM1031_INTERRUPT_WAIT		(ADM1031_PVT_BASE_IOCTL + 27)
+#define	ADM1031_GET_MONITOR_MODE	(ADM1031_PVT_BASE_IOCTL + 28)
+#define	ADM1031_SET_MONITOR_MODE	(ADM1031_PVT_BASE_IOCTL + 29)
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _ADM1031_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/adm1031_impl.h b/usr/src/uts/sun4u/sys/i2c/clients/adm1031_impl.h
new file mode 100644
index 0000000000..16c1ef3ae1
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/adm1031_impl.h
@@ -0,0 +1,162 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 1999-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _ADM1031_IMPL_H
+#define	_ADM1031_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+#define	ADM1031_PIL			4
+#define	ADM1031_MAX_XFER		4
+
+#define	ADM1031_WRITE_COMMAND_BASE	30
+
+
+/* This register has the value of fan speeds */
+#define	ADM1031_FAN_SPEED_INST_REG_1		0x08
+#define	ADM1031_FAN_SPEED_INST_REG_2		0x09
+
+/* This register has the value of temperatures */
+
+#define	ADM1031_LOCAL_TEMP_INST_REG		0x0A
+#define	ADM1031_REMOTE_TEMP_INST_REG_1		0x0B
+#define	ADM1031_REMOTE_TEMP_INST_REG_2		0x0C
+
+
+#define	ADM1031_STAT_1_REG			0x02
+#define	ADM1031_STAT_2_REG			0x03
+#define	ADM1031_DEVICE_ID_REG			0x3D
+#define	ADM1031_CONFIG_REG_1			0x00
+#define	ADM1031_CONFIG_REG_2 			0x01
+#define	ADM1031_FAN_CHAR_1_REG			0x20
+#define	ADM1031_FAN_CHAR_2_REG			0x21
+#define	ADM1031_FAN_SPEED_CONFIG_REG		0x22
+#define	ADM1031_FAN_HIGH_LIMIT_1_REG		0x10
+#define	ADM1031_FAN_HIGH_LIMIT_2_REG		0x11
+#define	ADM1031_LOCAL_TEMP_RANGE_REG		0x24
+#define	ADM1031_REMOTE_TEMP_RANGE_1_REG		0x25
+#define	ADM1031_REMOTE_TEMP_RANGE_2_REG		0x26
+#define	ADM1031_EXTD_TEMP_RESL_REG		0x06
+#define	ADM1031_LOCAL_TEMP_OFFSET_REG		0x0D
+#define	ADM1031_REMOTE_TEMP_OFFSET_1_REG	0x0E
+#define	ADM1031_REMOTE_TEMP_OFFSET_2_REG	0x0F
+#define	ADM1031_LOCAL_TEMP_HIGH_LIMIT_REG	0x14
+#define	ADM1031_REMOTE_TEMP_HIGH_LIMIT_1_REG    0x18
+#define	ADM1031_REMOTE_TEMP_HIGH_LIMIT_2_REG    0x1C
+#define	ADM1031_LOCAL_TEMP_LOW_LIMIT_REG	0x15
+#define	ADM1031_REMOTE_TEMP_LOW_LIMIT_1_REG	0x19
+#define	ADM1031_REMOTE_TEMP_LOW_LIMIT_2_REG	0x1D
+#define	ADM1031_LOCAL_TEMP_THERM_LIMIT_REG	0x16
+#define	ADM1031_REMOTE_TEMP_THERM_LIMIT_1_REG	0x1A
+#define	ADM1031_REMOTE_TEMP_THERM_LIMIT_2_REG	0x1E
+
+
+
+#define	ADM1031_TEMP_CHANS		3
+#define	ADM1031_FAN_SPEED_CHANS		2
+
+#define	ADM1031_TEMPERATURES		0
+#define	ADM1031_FANS			1
+#define	ADM1031_CONTROL			2
+
+
+#define	ADM1031_INST_TO_MINOR(x)	((x << 8) & 0xF00)
+#define	ADM1031_FCN_TO_MINOR(x)		((x << 4) & 0x0F0)
+#define	ADM1031_FCNINST_TO_MINOR(x)	(x & 0x00F)
+#define	ADM1031_MINOR_TO_FCNINST(x)	(0x00F & x)
+#define	ADM1031_MINOR_TO_FCN(x)		((0x0F0 & x) >> 4)
+#define	ADM1031_MINOR_TO_INST(x)	((x & 0xF00) >> 8)
+
+#define	ADM1031_CHECK_FOR_WRITES(x)	 (x > 26)
+
+/*
+ * Maximum speed for a fan is 0xf(100% PWM duty cycle) and minimum is
+ * 0x0(0% PWM duty cycle).
+ */
+#define	ADM1031_CHECK_INVALID_SPEED(x) ((x < 0x00) || (x > 0x0F))
+
+/*
+ * Check if the minor node corresponds with the correct function.
+ */
+#define	ADM1031_CHECK_FAN_CMD(x)	\
+	(((x >= 6) && (x < 11)) || ((x >= 36) && (x < 41)))
+
+#define	ADM1031_CHECK_TEMPERATURE_CMD(x) 	\
+	(((x >= 11) && (x < 27)) || ((x >= 41) && (x < 57)))
+
+#define	ADM1031_CHECK_CONTROL_CMD(x)	\
+	(((x >= 1) && (x < 6)) || ((x >= 34) && (x < 36)))
+
+
+#define	MLSN(x)		(x & 0xf0)
+#define	MMSN(x)		(x & 0x0f)
+
+#define	ADM1031_BUSYFLAG	0x1
+#define	ADM1031_TBUFFLAG	0x2
+#define	ADM1031_REGFLAG		0x4
+#define	ADM1031_MUTEXFLAG	0x8
+#define	ADM1031_INTRFLAG	0x10
+#define	ADM1031_AUTOFLAG	0x80
+
+#define	ADM1031_NODE_TYPE	"ddi_i2c:hardware_monitor"
+
+typedef struct adm1031_cpr_state {
+	uint8_t		config_reg_1;
+	uint8_t		config_reg_2;
+	uint8_t		fan_speed_reg;
+} adm1031_cpr_state_t;
+
+typedef struct adm1031_unit {
+	dev_info_t		*adm1031_dip;
+	i2c_transfer_t		*adm1031_transfer;
+	ddi_iblock_cookie_t	adm1031_icookie;
+	kmutex_t		adm1031_mutex;
+	kcondvar_t		adm1031_cv;
+	kmutex_t		adm1031_imutex;
+	kcondvar_t		adm1031_icv;
+	int			adm1031_cvwaiting;
+	int			adm1031_flags;
+	i2c_client_hdl_t	adm1031_hdl;
+	char			adm1031_name[12];
+	int			adm1031_oflag;
+	adm1031_cpr_state_t	adm1031_cpr_state;
+} adm1031_unit_t;
+
+typedef struct minor_info {
+	char			*minor_name;
+	uchar_t			reg;
+} minor_info;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _ADM1031_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/hpc3130.h b/usr/src/uts/sun4u/sys/i2c/clients/hpc3130.h
new file mode 100644
index 0000000000..95f28c19e7
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/hpc3130.h
@@ -0,0 +1,67 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_HPC3130_H
+#define	_HPC3130_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	HPC3130_IOCTL			('H' << 8)
+
+#define	HPC3130_GET_STATUS		(HPC3130_IOCTL | 0)  /* (uint8_t *) */
+#define	HPC3130_SET_STATUS		(HPC3130_IOCTL | 1)  /* (uint8_t *) */
+#define	HPC3130_GET_CONTROL		(HPC3130_IOCTL | 2)  /* (uint8_t *) */
+#define	HPC3130_SET_CONTROL		(HPC3130_IOCTL | 3)  /* (uint8_t *) */
+#define	HPC3130_GET_EVENT_STATUS	(HPC3130_IOCTL | 4)  /* (uint8_t *) */
+#define	HPC3130_SET_EVENT_STATUS	(HPC3130_IOCTL | 5)  /* (uint8_t *) */
+#define	HPC3130_GET_EVENT_ENABLE	(HPC3130_IOCTL | 6)  /* (uint8_t *) */
+#define	HPC3130_SET_EVENT_ENABLE	(HPC3130_IOCTL | 7)  /* (uint8_t *) */
+#define	HPC3130_GET_GENERAL_CONFIG	(HPC3130_IOCTL | 8)  /* (uint8_t *) */
+#define	HPC3130_SET_GENERAL_CONFIG	(HPC3130_IOCTL | 9)  /* (uint8_t *) */
+#define	HPC3130_GET_INDICATOR_CONTROL	(HPC3130_IOCTL | 10) /* (uint8_t *) */
+#define	HPC3130_SET_INDICATOR_CONTROL	(HPC3130_IOCTL | 11) /* (uint8_t *) */
+#define	HPC3130_ENABLE_SLOT_CONTROL	(HPC3130_IOCTL | 12) /* none */
+#define	HPC3130_DISABLE_SLOT_CONTROL	(HPC3130_IOCTL | 13) /* none */
+
+#define	HPC3130_SLOT_CONTROL_ENABLE	1
+#define	HPC3130_SLOT_CONTROL_DISABLE	0
+
+#define	HPC3130_GENERAL_CONFIG_REG(SLOT)	(0x00 + ((SLOT) * 8))
+#define	HPC3130_HP_STATUS_REG(SLOT)		(0x01 + ((SLOT) * 8))
+#define	HPC3130_HP_CONTROL_REG(SLOT)		(0x02 + ((SLOT) * 8))
+#define	HPC3130_ATTENTION_INDICATOR(SLOT)	(0x03 + ((SLOT) * 8))
+#define	HPC3130_INTERRUPT_STATUS_REG(SLOT)	(0x06 + ((SLOT) * 8))
+#define	HPC3130_INTERRUPT_ENABLE_REG(SLOT)	(0x07 + ((SLOT) * 8))
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _HPC3130_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/hpc3130_impl.h b/usr/src/uts/sun4u/sys/i2c/clients/hpc3130_impl.h
new file mode 100644
index 0000000000..e7091ae525
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/hpc3130_impl.h
@@ -0,0 +1,63 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_HPC3130_IMPL_H
+#define	_HPC3130_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/i2c/clients/i2c_client.h>
+
+struct hpc3130_unit {
+	kmutex_t		hpc3130_mutex;
+	uint8_t			hpc3130_flags;
+	int			hpc3130_oflag;
+	i2c_client_hdl_t	hpc3130_hdl;
+	char			hpc3130_name[24];
+};
+
+#ifdef DEBUG
+
+static int hpc3130debug = 0;
+#define	D1CMN_ERR(ARGS) if (hpc3130debug & 0x1) cmn_err ARGS;
+#define	D2CMN_ERR(ARGS) if (hpc3130debug & 0x2) cmn_err ARGS;
+
+#else
+
+#define	D1CMN_ERR(ARGS)
+#define	D2CMN_ERR(ARGS)
+
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _HPC3130_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/i2c_client.h b/usr/src/uts/sun4u/sys/i2c/clients/i2c_client.h
new file mode 100644
index 0000000000..47149a25bb
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/i2c_client.h
@@ -0,0 +1,114 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 1999-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_I2C_CLIENT_H
+#define	_I2C_CLIENT_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Common IOCTL definitions for client drivers.
+ */
+
+#define	I2C_BASE_IOCTL	('M' << 8)
+
+#define	I2C_GET_PORT		(I2C_BASE_IOCTL | 0)
+#define	I2C_SET_PORT		(I2C_BASE_IOCTL | 1)
+#define	I2C_GET_BIT		(I2C_BASE_IOCTL | 2)
+#define	I2C_SET_BIT		(I2C_BASE_IOCTL | 3)
+#define	I2C_GET_REG		(I2C_BASE_IOCTL | 4)
+#define	I2C_SET_REG		(I2C_BASE_IOCTL | 5)
+#define	I2C_GET_TEMPERATURE	(I2C_BASE_IOCTL | 7)
+#define	I2C_GET_FAN_SPEED	(I2C_BASE_IOCTL | 8)
+#define	I2C_SET_FAN_SPEED	(I2C_BASE_IOCTL | 9)
+#define	I2C_SET_OUTPUT		(I2C_BASE_IOCTL | 10)
+#define	I2C_GET_OUTPUT		(I2C_BASE_IOCTL | 11)
+#define	I2C_GET_INPUT		(I2C_BASE_IOCTL | 12)
+#define	I2C_SET_MODE		(I2C_BASE_IOCTL | 13)
+#define	I2C_GET_MODE		(I2C_BASE_IOCTL | 14)
+
+/*
+ * A private IOCTL definition to be used by clients. The first 128 ioctls
+ * derived by OR'ing with I2C_BASE_IOCTL are common. The next 128
+ * ioctls derived by OR'ing with I2C_PVT_BASE_IOCTL are client private.
+ */
+
+#define	I2C_PVT_BASE_IOCTL	(I2C_BASE_IOCTL + 128)
+
+/*
+ * ARGS for I2C_*_MODE
+ */
+#define	I2C_NORMAL	0
+#define	I2C_DEBUG	1
+
+/*
+ * ARGS for i2c_bit_t direction
+ */
+
+#define	DIR_NO_CHANGE	0
+#define	DIR_OUTPUT	1
+#define	DIR_INPUT	2
+
+
+#define	INST_TO_MINOR(x) (x << 4)
+#define	MINOR_TO_INST(x) ((x & 0xFFFFFFF0) >> 4)
+#define	PORT_TO_MINOR(x)  (x)
+#define	MINOR_TO_PORT(x)  (0x0F & x)
+
+#define	I2C_PORT(x)		(0x00 + x)
+
+typedef struct i2c_port {
+	uint8_t		value;
+	uint8_t		direction;
+	uint8_t		dir_mask;
+} i2c_port_t;
+
+typedef struct i2c_bit {
+	uchar_t		bit_num;
+	boolean_t	bit_value;
+	uint8_t		direction;
+} i2c_bit_t;
+
+typedef struct i2c_reg {
+	uint8_t		reg_num;
+	int32_t		reg_value;
+} i2c_reg_t;
+
+#if defined(_KERNEL)
+
+#include <sys/i2c/misc/i2c_svc.h>
+
+#endif /* _KERNEL */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _I2C_CLIENT_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/i2c_gpio.h b/usr/src/uts/sun4u/sys/i2c/clients/i2c_gpio.h
new file mode 100644
index 0000000000..be945b976a
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/i2c_gpio.h
@@ -0,0 +1,58 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _I2C_GPIO_H
+#define	_I2C_GPIO_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/i2c/clients/i2c_client.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+#define	GPIO_GET_INPUT		(I2C_PVT_BASE_IOCTL + 0)
+#define	GPIO_GET_OUTPUT		(I2C_PVT_BASE_IOCTL + 1)
+#define	GPIO_SET_OUTPUT		(I2C_PVT_BASE_IOCTL + 2)
+#define	GPIO_GET_POLARITY	(I2C_PVT_BASE_IOCTL + 3)
+#define	GPIO_SET_POLARITY	(I2C_PVT_BASE_IOCTL + 4)
+#define	GPIO_GET_CONFIG		(I2C_PVT_BASE_IOCTL + 5)
+#define	GPIO_SET_CONFIG		(I2C_PVT_BASE_IOCTL + 6)
+
+
+typedef struct i2c_gpio {
+	uint32_t	reg_val;
+	uint32_t	reg_mask;
+} i2c_gpio_t;
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _I2C_GPIO_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/ics951601.h b/usr/src/uts/sun4u/sys/i2c/clients/ics951601.h
new file mode 100644
index 0000000000..4f495dc413
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/ics951601.h
@@ -0,0 +1,87 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 1999-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_ICS951601_H
+#define	_ICS951601_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Header file for ICS951601, a general purpose PCI clock generator
+ * and an I2C client.
+ */
+
+/*
+ * Clock numbers needed by the driver to uniquely identify a clock.
+ */
+#define	ICS951601_PCI2B_2	0x580
+#define	ICS951601_PCI2B_1	0x540
+#define	ICS951601_PCI2B_0	0x520
+#define	ICS951601_PCI2A_2	0x480
+#define	ICS951601_PCI2A_1	0x440
+#define	ICS951601_PCI2A_0	0x420
+#define	ICS951601_PCI1B_2	0x410
+#define	ICS951601_PCI1B_1	0x408
+#define	ICS951601_PCI1B_0	0x404
+#define	ICS951601_PCI1A_7	0x380
+#define	ICS951601_PCI1A_6	0x340
+#define	ICS951601_PCI1A_5	0x320
+#define	ICS951601_PCI1A_4	0x310
+#define	ICS951601_PCI1A_3	0x308
+#define	ICS951601_PCI1A_2	0x304
+#define	ICS951601_PCI1A_1	0x302
+#define	ICS951601_PCI1A_0	0x301
+
+/*
+ * The actions which are supported for a given clock.
+ */
+#define	ICS951601_READ_CLOCK		0x1000
+#define	ICS951601_MODIFY_CLOCK		0x2000
+
+/*
+ * The possible values for any clock
+ */
+#define	ICS951601_CLOCK_SET	1
+#define	ICS951601_CLOCK_CLEAR	0
+
+/*
+ * Open and close system calls.
+ *
+ *	0 on success
+ *	-1 on error, errno is set:
+ *	ENXIO	- Device not found or not available
+ *	EBUSY	- The channel is in use by another
+ *	EPERM	- Permission denied - not super user
+ */
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _ICS951601_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/ics951601_impl.h b/usr/src/uts/sun4u/sys/i2c/clients/ics951601_impl.h
new file mode 100644
index 0000000000..a73bcd574e
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/ics951601_impl.h
@@ -0,0 +1,75 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _ICS951601_IMPL_H
+#define	_ICS951601_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/promif.h>
+#define	ICS951601_I2C_WRITE_TRANS_SIZE	0x8
+#define	ICS951601_I2C_READ_TRANS_SIZE	0x7
+
+
+#define	ICS951601_CMD_TO_ACTION(x)	((x) & 0xF000)
+#define	ICS951601_CMD_TO_CLOCKREG(x)	((0x0F00 & (x)) >> 8)
+#define	ICS951601_CMD_TO_CLOCKBIT(x)	((x) & 0x00FF)
+
+/*
+ * Defines for debug printing
+ */
+#define	DPRINTF(print_flag, args)                       \
+    if (ics951601_debug & (print_flag)) { prom_printf args; }
+
+
+#define	ICS951601_BUSYFLAG	0x1
+#define	ICS951601_MINORFLAG	0x2
+#define	ICS951601_TBUFFLAG	0x4
+#define	ICS951601_REGFLAG	0x8
+
+#define	ICS951601_NODE_TYPE	"ddi_i2c:pci_clock_gen"
+
+typedef struct ics951601_unit {
+	dev_info_t		*ics951601_dip;
+	i2c_transfer_t		*ics951601_transfer;
+	i2c_client_hdl_t	ics951601_hdl;
+	kmutex_t		ics951601_mutex;
+	kcondvar_t		ics951601_cv;
+	char			ics951601_name[16];
+	uchar_t			ics951601_cpr_state[8];
+	uint16_t		ics951601_oflag;
+	uint8_t			ics951601_flags;
+} ics951601_unit_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _ICS951601_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/lm75.h b/usr/src/uts/sun4u/sys/i2c/clients/lm75.h
new file mode 100644
index 0000000000..ccfcecc2df
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/lm75.h
@@ -0,0 +1,49 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_LM75_H
+#define	_LM75_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	LM75_IOCTL		('L' << 8)
+
+#define	LM75_GET_HYST			(LM75_IOCTL | 0)  /* (int16_t *) */
+#define	LM75_SET_HYST			(LM75_IOCTL | 1)  /* (int16_t *) */
+#define	LM75_GET_OVERTEMP_SHUTDOWN	(LM75_IOCTL | 2)  /* (int16_t *) */
+#define	LM75_SET_OVERTEMP_SHUTDOWN	(LM75_IOCTL | 3)  /* (int16_t *) */
+#define	LM75_GET_CONFIG			(LM75_IOCTL | 4)  /* (uint8_t *) */
+#define	LM75_SET_CONFIG			(LM75_IOCTL | 5)  /* (uint8_t *) */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _LM75_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/lm75_impl.h b/usr/src/uts/sun4u/sys/i2c/clients/lm75_impl.h
new file mode 100644
index 0000000000..3d5e6eb569
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/lm75_impl.h
@@ -0,0 +1,71 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_LM75_IMPL_H
+#define	_LM75_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	LM75_TEMPERATURE_REG		0x00
+#define	LM75_CONFIGURATION_REG		0x01
+#define	LM75_HYST_REG			0x02
+#define	LM75_OVERTEMP_REG		0x03
+
+#define	LM75_COMP_MASK		0x100
+#define	LM75_COMP_MASK_UPPER	0xff
+
+#include <sys/i2c/clients/i2c_client.h>
+
+struct lm75_unit {
+	kmutex_t		lm75_mutex;
+	uint8_t			lm75_flags;
+	int			lm75_oflag;
+	i2c_client_hdl_t	lm75_hdl;
+	char			lm75_name[24];
+};
+
+#ifdef DEBUG
+
+static int lm75debug = 0;
+#define	D1CMN_ERR(ARGS) if (lm75debug & 0x1) cmn_err ARGS;
+#define	D2CMN_ERR(ARGS) if (lm75debug & 0x2) cmn_err ARGS;
+
+#else
+
+#define	D1CMN_ERR(ARGS)
+#define	D2CMN_ERR(ARGS)
+
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _LM75_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/ltc1427_impl.h b/usr/src/uts/sun4u/sys/i2c/clients/ltc1427_impl.h
new file mode 100644
index 0000000000..2f816656d3
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/ltc1427_impl.h
@@ -0,0 +1,64 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000-2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_LTC1427_IMPL_H
+#define	_LTC1427_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/i2c/clients/i2c_client.h>
+
+struct ltc1427_unit {
+	kmutex_t		ltc1427_mutex;
+	int			ltc1427_oflag;
+	i2c_client_hdl_t	ltc1427_hdl;
+	char			ltc1427_name[24];
+	int32_t			current_value;
+	int8_t			current_set_flag;
+};
+
+#ifdef DEBUG
+
+static int ltc1427debug = 0;
+#define	D1CMN_ERR(ARGS) if (ltc1427debug & 0x1) cmn_err ARGS;
+#define	D2CMN_ERR(ARGS) if (ltc1427debug & 0x2) cmn_err ARGS;
+
+#else
+
+#define	D1CMN_ERR(ARGS)
+#define	D2CMN_ERR(ARGS)
+
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _LTC1427_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/max1617.h b/usr/src/uts/sun4u/sys/i2c/clients/max1617.h
new file mode 100644
index 0000000000..293e178160
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/max1617.h
@@ -0,0 +1,53 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 1999-2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_MAX1617_H
+#define	_MAX1617_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	MAX1617_IOCTL	('A' << 8)
+
+#define	MAX1617_GET_STATUS	(MAX1617_IOCTL |0)
+#define	MAX1617_GET_CONFIG	(MAX1617_IOCTL |1)
+#define	MAX1617_GET_CONV_RATE	(MAX1617_IOCTL |2)
+#define	MAX1617_GET_HIGH_LIMIT	(MAX1617_IOCTL |3)
+#define	MAX1617_GET_LOW_LIMIT	(MAX1617_IOCTL |4)
+#define	MAX1617_SET_CONFIG	(MAX1617_IOCTL |5)
+#define	MAX1617_SET_CONV_RATE	(MAX1617_IOCTL |6)
+#define	MAX1617_SET_HIGH_LIMIT	(MAX1617_IOCTL |7)
+#define	MAX1617_SET_LOW_LIMIT	(MAX1617_IOCTL |8)
+#define	MAX1617_ONE_SHOT_CMD	(MAX1617_IOCTL |9)
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _MAX1617_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/max1617_impl.h b/usr/src/uts/sun4u/sys/i2c/clients/max1617_impl.h
new file mode 100644
index 0000000000..4c759fbdb9
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/max1617_impl.h
@@ -0,0 +1,89 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 1999-2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_MAX1617_IMPL_H
+#define	_MAX1617_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	MAX1617_BUSY	0x01
+
+#define	MAX1617_MAX_REGS		16
+#define	MAX1617_LOCAL_TEMP_REG		0
+#define	MAX1617_REMOTE_TEMP_REG		1
+#define	MAX1617_STATUS_REG		2
+#define	MAX1617_CONFIG_REG		3
+#define	MAX1617_CONV_RATE_REG		4
+#define	MAX1617_LOCALTEMP_HIGH_REG	5
+#define	MAX1617_LOCALTEMP_LOW_REG	6
+#define	MAX1617_REMOTETEMP_HIGH_REG	7
+#define	MAX1617_REMOTETEMP_LOW_REG	8
+
+#define	MAX1617_CONFIG_WR_REG		9
+#define	MAX1617_CONV_RATE_WR_REG	10
+#define	MAX1617_LOCALTEMP_HIGH_WR_REG	11
+#define	MAX1617_LOCALTEMP_LOW_WR_REG	12
+#define	MAX1617_REMOTETEMP_HIGH_WR_REG	13
+#define	MAX1617_REMOTETEMP_LOW_WR_REG	14
+#define	MAX1617_ONE_SHOT_CMD_REG	15
+
+#define	MAX1617_INST_TO_MINOR(x) (x << 4)
+#define	MAX1617_MINOR_TO_INST(x) ((x & 0xFFFFFFF0) >> 4)
+#define	MAX1617_FCN_TO_MINOR(x)  (x)
+#define	MAX1617_MINOR_TO_FCN(x)  (0x0F & x)
+#define	MAX1617_AMB_TEMP 0
+#define	MAX1617_CPU_TEMP 1
+
+#define	MAX1617_NODE_TYPE "ddi_i2c:temperature_sensor"
+
+struct max1617_cpr_state {
+	uint8_t		max1617_config;
+	uint8_t		max1617_conv_rate;
+	int8_t		max1617_lcl_hlimit;
+	int8_t		max1617_lcl_llimit;
+	int8_t		max1617_remote_hlimit;
+	int8_t		max1617_remote_llimit;
+};
+
+struct max1617_unit {
+	kmutex_t	max1617_mutex;
+	uint8_t		max1617_flags;
+	kcondvar_t	max1617_cv;
+	uint16_t	max1617_oflag;
+	i2c_client_hdl_t	max1617_hdl;
+	char		max1617_name[24];
+	struct max1617_cpr_state max1617_cpr_state;
+};
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _MAX1617_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/pca9556_impl.h b/usr/src/uts/sun4u/sys/i2c/clients/pca9556_impl.h
new file mode 100644
index 0000000000..9ec403c111
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/pca9556_impl.h
@@ -0,0 +1,84 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _PCA9556_IMPL_H
+#define	_PCA9556_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/promif.h>
+
+/*
+ * Declarations for debug printing
+ */
+extern int pca9556_debug;
+
+#define	PCA9556_NUM_PORTS	1
+#define	PCA9555_NUM_PORTS	2
+#define	PCA9556_NUM_REG		3
+#define	PCA9556_MAX_REG		6
+
+#define	PCA9556_BUSYFLAG	0x1
+#define	PCA9556_MINORFLAG	0x2
+#define	PCA9556_TBUFFLAG	0x4
+#define	PCA9556_REGFLAG		0x8
+
+#define	PCA9556_INPUT_REG	0x0
+#define	PCA9556_OUTPUT_REG	0x1
+#define	PCA9556_POLARITY_REG	0x2
+#define	PCA9556_CONFIG_REG	0x3
+
+#define	PCA9555_INPUT_REG	0x0
+#define	PCA9555_OUTPUT_REG	0x2
+#define	PCA9555_POLARITY_REG	0x4
+#define	PCA9555_CONFIG_REG	0x6
+
+#define	PCA9556_NODE_TYPE	"ddi_i2c:gpio_device"
+#define	PCA9556_MAX_SIZE	8
+#define	PCA9556_NAME_LEN	16
+
+typedef struct pca9556_unit {
+	dev_info_t		*pca9556_dip;
+	i2c_transfer_t		*pca9556_transfer;
+	kmutex_t		pca9556_mutex;
+	kcondvar_t		pca9556_cv;
+	uint8_t			pca9556_flags;
+	i2c_client_hdl_t	pca9556_hdl;
+	char			pca9556_name[PCA9556_NAME_LEN];
+	uint16_t		pca9556_oflag;
+	uint8_t			pca9556_cpr_state[PCA9556_MAX_REG];
+	boolean_t		pca9555_device;
+} pca9556_unit_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _PCA9556_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/pcf8574_impl.h b/usr/src/uts/sun4u/sys/i2c/clients/pcf8574_impl.h
new file mode 100644
index 0000000000..7b7414a8cd
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/pcf8574_impl.h
@@ -0,0 +1,81 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_PCF8574_IMPL_H
+#define	_PCF8574_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/i2c/clients/i2c_client.h>
+
+/*
+ * PCF8574_BIT_READ_MASK takes in a byte from the device and the bit that
+ * the user wants to read.  I shifts the byte over so that the bit that we
+ * want is in the 1's bit and masks out the rest of the byte.
+ */
+#define	PCF8574_BIT_READ_MASK(byte, bit)	((byte >> bit) & 0x01)
+
+/*
+ * PCF8574_BIT_WRITE_MASK takes in a byte from the device, the bit that the
+ * user wants to read write, and the value that the user wants put into that
+ * bit. It zero's out the bit that we are writing to in the byte and then or's
+ * the value(which was shifted to the bit location we wanted) to fill in only
+ * that bit in the byte
+ */
+#define	PCF8574_BIT_WRITE_MASK(byte, bit, value)\
+				((value << bit) | (byte & (~(0x01 << bit))))
+
+struct pcf8574_unit {
+	kmutex_t		pcf8574_mutex;
+	uint8_t			pcf8574_flags;
+	int			pcf8574_oflag;
+	i2c_client_hdl_t	pcf8574_hdl;
+	char			pcf8574_name[24];
+};
+
+#ifdef DEBUG
+
+static int pcf8574debug = 0;
+#define	D1CMN_ERR(ARGS) if (pcf8574debug & 0x1) cmn_err ARGS;
+#define	D2CMN_ERR(ARGS) if (pcf8574debug & 0x2) cmn_err ARGS;
+
+#else
+
+#define	D1CMN_ERR(ARGS)
+#define	D2CMN_ERR(ARGS)
+
+#endif
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _PCF8574_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/pcf8591.h b/usr/src/uts/sun4u/sys/i2c/clients/pcf8591.h
new file mode 100644
index 0000000000..86c7e5caf2
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/pcf8591.h
@@ -0,0 +1,49 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_PCF8591_H
+#define	_PCF8591_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	PCF8591_IOCTL 		('P' << 8)
+
+#define	PCF8591_SET_IPMODE	(PCF8591_IOCTL | 0)	/* (uchar_t *) */
+
+#define	PCF8591_4SINGLE		0x00
+#define	PCF8591_3DIFF		0x01
+#define	PCF8591_MIXED		0x02
+#define	PCF8591_2DIFF		0x03
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _PCF8591_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/pcf8591_impl.h b/usr/src/uts/sun4u/sys/i2c/clients/pcf8591_impl.h
new file mode 100644
index 0000000000..b32460c66d
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/pcf8591_impl.h
@@ -0,0 +1,67 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_PCF8591_IMPL_H
+#define	_PCF8591_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	PCF8591_ANALOG_OUTPUT_SHIFT	6
+#define	PCF8591_ANALOG_INPUT_SHIFT	4
+#define	PCF8591_AUTOINCR_SHIFT		2
+
+#include <sys/i2c/clients/i2c_client.h>
+
+struct pcf8591_unit {
+	kmutex_t		pcf8591_mutex;
+	uint8_t			pcf8591_flags;
+	int			pcf8591_oflag;
+	i2c_client_hdl_t	pcf8591_hdl;
+	char			pcf8591_name[24];
+};
+
+#ifdef DEBUG
+
+static int pcf8591debug = 0;
+#define	D1CMN_ERR(ARGS) if (pcf8591debug & 0x1) cmn_err ARGS;
+#define	D2CMN_ERR(ARGS) if (pcf8591debug & 0x2) cmn_err ARGS;
+
+#else
+
+#define	D1CMN_ERR(ARGS)
+#define	D2CMN_ERR(ARGS)
+
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _PCF8591_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/pic16f819_impl.h b/usr/src/uts/sun4u/sys/i2c/clients/pic16f819_impl.h
new file mode 100644
index 0000000000..60a1edb4c9
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/pic16f819_impl.h
@@ -0,0 +1,62 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_PIC16F819_IMPL_H
+#define	_PIC16F819_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/i2c/clients/i2c_client.h>
+
+struct pic16f819_unit {
+	kmutex_t		pic16f819_mutex;
+	int			pic16f819_oflag;
+	i2c_client_hdl_t	pic16f819_hdl;
+	char			pic16f819_name[24];
+};
+
+#ifdef DEBUG
+
+static int pic16f819debug = 0;
+#define	D1CMN_ERR(ARGS) if (pic16f819debug & 0x1) cmn_err ARGS;
+#define	D2CMN_ERR(ARGS) if (pic16f819debug & 0x2) cmn_err ARGS;
+
+#else
+
+#define	D1CMN_ERR(ARGS)
+#define	D2CMN_ERR(ARGS)
+
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _PIC16F819_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/pic16f819_reg.h b/usr/src/uts/sun4u/sys/i2c/clients/pic16f819_reg.h
new file mode 100644
index 0000000000..54a6b8ebf0
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/pic16f819_reg.h
@@ -0,0 +1,63 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_PIC16F819_REG_H
+#define	_PIC16F819_REG_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	PIC16F819_FAN_PERIOD_MSB_REGISTER	3
+#define	PIC16F819_FAN_PERIOD_LSB_REGISTER	2
+#define	PIC16F819_STATUS_REGISTER		1
+#define	PIC16F819_COMMAND_REGISTER		0
+#define	PIC16F819_DEBUG_REGISTER		9
+#define	PIC16F819_FAN_STATUS_MASK		0x7
+#define	PIC16F819_FAN_FAULT			0x1
+#define	PIC16F819_FAN_FAULT_CLEAR		0x4
+#define	PIC16F819_SW_AWARE_MODE			0x2
+#define	PIC16F819_FAN_FAULT_LATCHED		0x2
+#define	PIC16F819_FAN_FAILED			0x8
+
+/*
+ * The actual formula is ((CLK_FREQ * 60)/ (tach period * 4)
+ * tach period is multiplied by 4 because we get 4 tach pulses per
+ * revolution.
+ * tach period is the number of clks we count per tach pulse.
+ */
+#define	PIC16F819_FAN_TACH_TO_RPM(tach)	\
+	((327000 * 15)/tach)
+
+#define	MAX_RETRIES_FOR_PIC16F819_REG_READ	5
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _PIC16F819_REG_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/seeprom_impl.h b/usr/src/uts/sun4u/sys/i2c/clients/seeprom_impl.h
new file mode 100644
index 0000000000..5411c3bfe8
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/seeprom_impl.h
@@ -0,0 +1,68 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 1999-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SEEPROM_IMPL_H
+#define	_SEEPROM_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	AT24C64_ADDRSIZE	2
+#define	AT24C64_MEMSIZE		8192
+#define	AT24C64_PAGESIZE	32
+#define	AT24C64_PAGEMASK	(AT24C64_PAGESIZE - 1)
+
+#define	AT34C02_ADDRSIZE	1
+#define	AT34C02_MEMSIZE		256
+#define	AT34C02_PAGESIZE	16
+#define	AT34C02_PAGEMASK	(AT34C02_PAGESIZE - 1)
+
+#define	SEEPROM_BUSY	0x01
+
+#define	SEEPROM_NODE_TYPE	"ddi_i2c:seeprom"
+
+struct seepromunit {
+	kmutex_t	seeprom_mutex;
+	kcondvar_t	seeprom_cv;
+	dev_info_t	*seeprom_dip;
+	int		seeprom_flags;
+	int		seeprom_oflag;
+	int		seeprom_memsize;
+	int		seeprom_addrsize;
+	int		seeprom_pagesize;
+	int		seeprom_pagemask;
+	i2c_client_hdl_t seeprom_hdl;
+	char		seeprom_name[20];
+};
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SEEPROM_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/ssc050.h b/usr/src/uts/sun4u/sys/i2c/clients/ssc050.h
new file mode 100644
index 0000000000..927a1a5e9b
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/ssc050.h
@@ -0,0 +1,44 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SSC050_H
+#define	_SSC050_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	SSC050_FAN_CONTROL_REG(port)		(0x30 + (port * 4))
+
+#define	SSC050_PORT_BIT_REG(port)		(0x80 + (port << 4))
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SSC050_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/ssc100_impl.h b/usr/src/uts/sun4u/sys/i2c/clients/ssc100_impl.h
new file mode 100644
index 0000000000..59dbeacf78
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/ssc100_impl.h
@@ -0,0 +1,85 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SSC100_IMPL_H
+#define	_SSC100_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/i2c/clients/i2c_client.h>
+
+/*
+ * SSC100_BIT_READ_MASK takes in a byte from the device and the bit that
+ * the user wants to read.  I shifts the byte over so that the bit that we
+ * want is in the 1's bit and masks out the rest of the byte.
+ */
+#define	SSC100_BIT_READ_MASK(byte, bit)	((byte >> bit) & 0x01)
+
+/*
+ * SSC100_BIT_WRITE_MASK takes in a byte from the device, the bit that the
+ * user wants to read write, and the value that the user wants put into that
+ * bit. It zero's out the bit that we are writing to in the byte and then or's
+ * the value(which was shifted to the bit location we wanted) to fill in only
+ * that bit in the byte
+ */
+#define	SSC100_BIT_WRITE_MASK(byte, bit, value)\
+				((value << bit) | (byte & (~(0x01 << bit))))
+
+#define	SSC100_SIZE		8192
+#define	SSC100_PAGESIZE		32
+#define	SSC100_PAGEMASK		(SSC100_PAGESIZE - 1)
+
+struct ssc100_unit {
+	kmutex_t		ssc100_mutex;
+	uint8_t			ssc100_flags;
+	int			ssc100_oflag;
+	int			ssc100_size;
+	i2c_client_hdl_t	ssc100_hdl;
+	char			ssc100_name[24];
+};
+
+#ifdef DEBUG
+
+static int ssc100debug = 0;
+#define	D1CMN_ERR(ARGS) if (ssc100debug & 0x1) cmn_err ARGS;
+#define	D2CMN_ERR(ARGS) if (ssc100debug & 0x2) cmn_err ARGS;
+
+#else
+
+#define	D1CMN_ERR(ARGS)
+#define	D2CMN_ERR(ARGS)
+
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SSC100_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/clients/tda8444_impl.h b/usr/src/uts/sun4u/sys/i2c/clients/tda8444_impl.h
new file mode 100644
index 0000000000..f9785fb528
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/clients/tda8444_impl.h
@@ -0,0 +1,81 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _TDA844_IMPL_H
+#define	_TDA844_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/promif.h>
+
+#define	TDA8444_MAX_DACS	16
+#define	TDA8444_CHANS		8
+#define	TDA8444_BUSY		0x01
+#define	TDA8444_SUSPENDED	0x02
+
+#define	TDA8444_REGBASE		0xf0
+
+#define	TDA8444_UNKNOWN_OUT	-1
+#define	TDA8444_MAX_OUT		0x3f
+#define	TDA8444_MIN_OUT		0x0
+
+#define	TDA8444_MINOR_TO_DEVINST(x) ((x & 0xf00) >> 8)
+#define	TDA8444_MINOR_TO_CHANNEL(x) (x & 0x00f)
+
+#define	TDA8444_CHANNEL_TO_MINOR(x) x
+#define	TDA8444_DEVINST_TO_MINOR(x) (x << 8)
+
+#define	TDA8444_NODE_TYPE "ddi_i2c:adio"
+
+/*
+ * Defines for debug printing
+ */
+#define	DPRINTF(print_flag, args)                       \
+    if (tda8444_debug & (print_flag)) { prom_printf args; }
+
+#define	RESUME	0x01
+#define	IO	0x02
+
+struct tda8444_unit {
+	i2c_transfer_t		*tda8444_transfer;
+	kmutex_t		tda8444_mutex;
+	kcondvar_t		tda8444_cv;
+	uint8_t			tda8444_flags;
+	int8_t			tda8444_output[TDA8444_MAX_DACS];
+	i2c_client_hdl_t	tda8444_hdl;
+	char			tda8444_name[12];
+	uint16_t		tda8444_oflag[TDA8444_MAX_DACS];
+};
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _TDA844_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/misc/i2c_svc.h b/usr/src/uts/sun4u/sys/i2c/misc/i2c_svc.h
new file mode 100644
index 0000000000..40bc21b4d1
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/misc/i2c_svc.h
@@ -0,0 +1,105 @@
+
+/*
+ * Copyright (c) 1999 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _I2C_SVC_H
+#define	_I2C_SVC_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * I2C interface return values
+ */
+#define	I2C_SUCCESS	0
+#define	I2C_FAILURE	-1
+#define	I2C_INCOMPLETE  -2
+
+/*
+ * Used for flags in i2c_transfer_alloc()
+ */
+#define	I2C_SLEEP	0x01
+#define	I2C_NOSLEEP	0x02
+
+/*
+ * Version for i2c_transfer_t.i2c_version
+ */
+#define	I2C_XFER_REV	0
+
+/*
+ * Version for i2c_svc_t.i2c_nexus_version
+ */
+#define	I2C_NEXUS_REV	0
+
+
+/*
+ * Valid transfer flags for i2c_transfer.flags
+ */
+#define	I2C_WR		0x01	/* write */
+#define	I2C_RD		0x02	/* read */
+#define	I2C_WR_RD	0x04	/* write then read */
+
+/*
+ * Developer's note: i2c_transfer_copyout is sensitive to
+ * the ordering of i2c_transfer structure fields.  If any fields
+ * are changed, make sure to review i2c_transfer_copyout for
+ * possible changes.
+ *
+ * Fields prefixed with 'I' are input fields passed to the
+ * i2c_transfer function, while those prefixed with 'O'
+ * are returned from the transfer function.
+ */
+typedef struct i2c_transfer {
+	uint16_t		i2c_version; /* I: Set to I2C_XFER_REV_0 */
+	uchar_t			*i2c_wbuf;   /* I: pointer to write buffer */
+	uchar_t			*i2c_rbuf;   /* I: pointer to read buffer */
+	int			i2c_flags;   /* I: description of transfer */
+	uint16_t		i2c_wlen;    /* I: length of write buffer */
+	uint16_t		i2c_rlen;    /* I: length of read buffer */
+	uint16_t		i2c_w_resid; /* O: bytes not written */
+	uint16_t		i2c_r_resid; /* O: bytes not read */
+	int16_t			i2c_result;  /* O: return value */
+} i2c_transfer_t;
+
+typedef struct i2c_client_hdl *i2c_client_hdl_t;
+
+/*
+ * i2c_nexus_reg is passed to the I2C services module
+ * through the i2c_nexus_register() interface by the nexus
+ * driver.  It contains a version plus the pointer to
+ * the functions that I2C services calls.
+ */
+typedef struct i2c_nexus_reg {
+	int	i2c_nexus_version; /* set to I2C_NEXUS_REV_0 */
+	int	(*i2c_nexus_transfer)(dev_info_t *dip, struct i2c_transfer *);
+} i2c_nexus_reg_t;
+
+/*
+ * Interfaces for I2C client drivers
+ */
+int i2c_client_register(dev_info_t *dip, i2c_client_hdl_t *i2c_hdl);
+void i2c_client_unregister(i2c_client_hdl_t i2c_hdl);
+int i2c_transfer(i2c_client_hdl_t i2c_hdl, i2c_transfer_t *i2c_tran);
+int i2c_transfer_alloc(i2c_client_hdl_t i2c_hdl,
+			i2c_transfer_t **i2c,
+			uint16_t wlen,
+			uint16_t rlen,
+			uint_t flags);
+void i2c_transfer_free(i2c_client_hdl_t i2c_hdl, i2c_transfer_t *i2c);
+
+/*
+ * Interfaces for I2C nexus drivers
+ */
+void i2c_nexus_register(dev_info_t *dip, i2c_nexus_reg_t *nexus_reg);
+void i2c_nexus_unregister(dev_info_t *dip);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _I2C_SVC_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/misc/i2c_svc_impl.h b/usr/src/uts/sun4u/sys/i2c/misc/i2c_svc_impl.h
new file mode 100644
index 0000000000..bd97df2fcb
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/misc/i2c_svc_impl.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 1999-2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _I2C_SVC_IMPL_H
+#define	_I2C_SVC_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * i2c_transfer_alloc is a wrapper structure that is used
+ * to store i2c_transfer_t allocation information so that
+ * the caller to i2c_transfer_allocate() can modify the
+ * buffer/size fields and i2c_transfer_free() will still
+ * be able to recover all buffers.
+ */
+typedef struct i2c_transfer_alloc {
+	i2c_transfer_t		i2cw_i2ct;
+	uint32_t		i2cw_size;
+} i2c_transfer_alloc_t;
+
+#define	CHDL(client_hdl) ((i2c_client_hdl_impl_t *)(client_hdl))
+
+/*
+ * i2c_client_hdl_impl is the real implementation of
+ * i2c_client_hdl.
+ */
+typedef struct i2c_client_hdl_impl {
+	dev_info_t	*chdl_dip; /* dip for I2C device */
+	struct i2c_nexus_reg *chdl_nexus_reg;
+} i2c_client_hdl_impl_t;
+
+/*
+ * i2c_nexus_reg_list are the elements of a linked list which
+ * tracks all I2C parents.
+ */
+typedef struct i2c_nexus_reg_list {
+	i2c_nexus_reg_t nexus_reg;
+	dev_info_t	*dip;
+	struct i2c_nexus_reg_list *next;
+} i2c_nexus_reg_list_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _I2C_SVC_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/nexus/i2bsc_impl.h b/usr/src/uts/sun4u/sys/i2c/nexus/i2bsc_impl.h
new file mode 100644
index 0000000000..91c08f9dad
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/nexus/i2bsc_impl.h
@@ -0,0 +1,165 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2002-2003 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _NEXUS_I2BSC_IMPL_H
+#define	_NEXUS_I2BSC_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/modctl.h>
+#include <sys/promif.h>
+#include <sys/lom_ebuscodes.h>
+#include <sys/bscbus.h>
+
+/*
+ * When "#address-cells" is 1, it means we aren't multiplexing i2c busses.  We
+ * therefore mark the bus number to I2BSC_DEFAULT_BUS.
+ */
+#define	I2BSC_DEFAULT_BUS		0
+
+/*
+ * Since i2c transfers are slow and take up lots of time, we limit our i2c
+ * transfer size to an advertised limit, I2BSC_MAX_TRANSFER_SZ bytes.
+ * The value was derived from an EEPROM page size of 32 bytes + 2 bytes to
+ * denote the address offset within the EEPROM.
+ */
+#define	I2BSC_MAX_TRANSFER_SZ		34
+
+/*
+ * Address Space Accessors
+ */
+#define	I2BSC_NEXUS_ADDR(ssp, as, index) \
+	(&((ssp)->bscbus_regs[((as) * 256) + (index)]))
+
+/*
+ * Re-try limit on Accessors was determined empircally.  During a firmware
+ * download (the most heavy use of the comms channel), retries of up to 21
+ * attempts have been seen.  The next power of 2 up is 32; the chosen retry
+ * limit.
+ */
+#define	I2BSC_RETRY_LIMIT		32
+
+/*
+ * During attach processing we need to figure out if the firmware is broken
+ * from the start.  If our re-try strategy is too aggressive we get poor
+ * boot times.  Therefore, the initial broken firmware check done during attach
+ * is given a relatively low retry threshold.
+ */
+#define	I2BSC_SHORT_RETRY_LIMIT		4
+
+
+/*
+ * strace(1M) prints out the debug data once the debug value is set in
+ * the i2bsc.conf file and the debug driver is installed.
+ *
+ * Debug flags
+ *
+ * '@' - Register (@)ccess
+ * 'A' - (A)ttach
+ * 'D' - (D)ettach
+ * 'S' - (S)ession
+ * 'T' - I2C (T)ransfer
+ * 'U' - (U)pload
+ */
+
+/*
+ * Debug tips :
+ *
+ * strace(1M) prints out the debug data.
+ * A nice way to work out the debug value set in i2bsc.conf is to use mdb
+ * Say we want to show 'T' i2c transfer and 'U' upload processing,
+ * you calculate the debug value with the following mdb session :
+ *	# mdb
+ *	> 1<<('T'-'@') | 1<<('U'-'@') = X
+ *	                300000
+ *
+ *      > $q
+ * When you explicitly set "debug=0x300000;" in i2bsc.conf, it causes the
+ * debug driver to log Transfer and upload messages for strace(1M).
+ */
+
+typedef struct i2bsc {
+	uint64_t		debug;		/* debugging turned on */
+	short			majornum;	/* debugging - major number */
+	short			minornum;	/* debugging - minor number */
+
+	int			i2c_proxy_support;
+
+	ddi_device_acc_attr_t	bscbus_attr;	/* bscbus attributes */
+	ddi_acc_handle_t	bscbus_handle;	/* bscbus opaque handle */
+	uint32_t		bscbus_fault;	/* 0 => okay		*/
+
+	/*
+	 * A session is a set of contigious gets/puts marked either as
+	 * successful or failed.
+	 */
+	int			bscbus_session_failure;
+	uint8_t			*bscbus_regs;	/* bscbus register space */
+
+	dev_info_t		*i2bsc_dip;
+	int			i2bsc_attachflags;
+	kmutex_t		i2bsc_imutex;
+	kcondvar_t		i2bsc_icv;
+	int			i2bsc_open;
+	int			i2bsc_busy;
+	int			i2bsc_bus;
+	i2c_transfer_t		*i2bsc_cur_tran;
+	dev_info_t		*i2bsc_cur_dip;
+	char			i2bsc_name[MODMAXNAMELEN];
+} i2bsc_t;
+
+/*
+ * i2c_parent_pvt contains info that is chip specific
+ * and is stored on the child's devinfo parent private data.
+ */
+typedef struct i2bsc_ppvt {
+	int i2bsc_ppvt_bus; /* multiple I2C busses on a single set of */
+			    /* registers.  this tells it what bus to */
+			    /* use  */
+	int i2bsc_ppvt_addr; /* address of I2C device */
+} i2bsc_ppvt_t;
+
+#define	I2BSC_INITIAL_SOFT_SPACE	1
+
+/*
+ * Attach flags
+ */
+#define	SETUP_REGS	0x01
+#define	NEXUS_REGISTER	0x02
+#define	IMUTEX		0x04
+#define	MINOR_NODE	0x08
+#define	FIRMWARE_ALIVE	0x10
+#define	TRANSFER_SZ	0x20
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _NEXUS_I2BSC_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/nexus/pcf8584.h b/usr/src/uts/sun4u/sys/i2c/nexus/pcf8584.h
new file mode 100644
index 0000000000..e65d741ce8
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/nexus/pcf8584.h
@@ -0,0 +1,189 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _PCF8584_H
+#define	_PCF8584_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/promif.h>
+
+/*
+ * S1 control
+ */
+#define	S1_ACK	0x01
+#define	S1_STO	0x02
+#define	S1_STA	0x04
+#define	S1_ENI	0x08
+#define	S1_ES2	0x10
+#define	S1_ES1	0x20
+#define	S1_ESO	0x40
+
+/*
+ * S1 status
+ */
+#define	S1_BBN	0x01
+#define	S1_LAB	0x02
+#define	S1_AAS	0x04
+#define	S1_AD0	0x08
+#define	S1_LRB	0x08
+#define	S1_BER	0x10
+#define	S1_STS	0x20
+
+/*
+ * S1 control/status
+ */
+
+#define	S1_PIN	0x80
+
+/*
+ * This has to be OR'ed in with the address for
+ * I2C read transactions.
+ */
+#define	I2C_READ	0x01
+
+/*
+ * S0 initialization bytes
+ */
+
+#define	S0_OWN 0x55
+#define	S0_CLK 0x1C		/* System clock = 12 MHz, SCL = 90 KHz) */
+
+#define	PCF8584_INIT_WAIT 200000	/* 200 ms */
+#define	DUMMY_ADDR 0x20
+#define	DUMMY_DATA 0x00
+
+#define	MONITOR_ADDRESS	0x0
+
+#define	S1_START	(S1_PIN | S1_ESO | S1_STA | S1_ACK)
+#define	S1_STOP		(S1_PIN | S1_ESO | S1_STO | S1_ACK)
+#define	S1_START2	(S1_ESO | S1_STA | S1_ACK)
+
+/*
+ * printing levels
+ */
+#define	PRT_SELECT	0x01
+#define	PRT_INTR	0x02
+#define	PRT_INIT	0x04
+#define	PRT_TRAN	0x08
+#define	PRT_POLL	0x10
+#define	PRT_BUFFONLY	0x100
+#define	PRT_PROM	0x200
+
+/*
+ * states for the I2C state machine.
+ */
+enum tran_state {
+	TRAN_STATE_NULL,
+	TRAN_STATE_WR,
+	TRAN_STATE_RD,
+	TRAN_STATE_WR_RD,
+	TRAN_STATE_START,
+	TRAN_STATE_DUMMY_DATA,
+	TRAN_STATE_DUMMY_RD
+};
+
+typedef struct pcf8584_regs {
+	uint8_t *pcf8584_regs_s0;
+	uint8_t *pcf8584_regs_s1;
+} pcf8584_regs_t;
+
+typedef struct pcf8584 {
+	dev_info_t		*pcf8584_dip;
+	int			pcf8584_attachflags;
+	kcondvar_t		pcf8584_cv;
+	kmutex_t		pcf8584_imutex;
+	kcondvar_t		pcf8584_icv;
+	ddi_iblock_cookie_t	pcf8584_icookie;
+	int			pcf8584_mode;
+	int			pcf8584_open;
+	int			pcf8584_busy;
+	int			pcf8584_bus;
+	int			pcf8584_cur_status;
+	dev_info_t		*pcf8584_nexus_dip;
+	i2c_transfer_t		*pcf8584_cur_tran;
+	dev_info_t		*pcf8584_cur_dip;
+	pcf8584_regs_t		pcf8584_regs;
+	ddi_acc_handle_t	pcf8584_rhandle;
+	uint8_t			*pcf8584_b_reg;
+	ddi_acc_handle_t	pcf8584_b_rhandle;
+	enum tran_state		pcf8584_tran_state;
+	char			pcf8584_name[12];
+} pcf8584_t;
+
+/*
+ * i2c_parent_pvt contains info that is chip specific
+ * and is stored on the child's devinfo parent private data.
+ */
+typedef struct pcf8584_ppvt {
+	int pcf8584_ppvt_bus; /* xcal's bbc implmentation multiplexes */
+			    /* multiple I2C busses on a single set of */
+			    /* registers.  this tells it what bus to */
+			    /* use  */
+	int pcf8584_ppvt_addr; /* address of I2C device */
+} pcf8584_ppvt_t;
+
+#define	PCF8584_PIL			4
+#define	PCF8584_XFER_TIME		1000
+#define	PCF8584_INTR_OVERHEAD		2000000
+#define	PCF8584_POLL_MODE		1
+#define	PCF8584_INTR_MODE		2
+#define	PCF8584_INITIAL_SOFT_SPACE	4
+
+/*
+ * generic interrupt return values
+ */
+#define	I2C_COMPLETE	2
+#define	I2C_PENDING	3
+
+/*
+ * Transfer status values
+ */
+#define	PCF8584_TRANSFER_NEW	1
+#define	PCF8584_TRANSFER_ON	2
+#define	PCF8584_TRANSFER_OVER	3
+
+/*
+ * Attach flags
+ */
+#define	ADD_INTR	0x01
+#define	ADD_PVT		0x02
+#define	SETUP_REGS	0x04
+#define	NEXUS_REGISTER	0x08
+#define	PROP_CREATE	0x10
+#define	IMUTEX		0x20
+#define	ALLOCATE_PVT	0x40
+#define	MINOR_NODE	0x80
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _PCF8584_H */
diff --git a/usr/src/uts/sun4u/sys/i2c/nexus/smbus.h b/usr/src/uts/sun4u/sys/i2c/nexus/smbus.h
new file mode 100644
index 0000000000..a22e346112
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/i2c/nexus/smbus.h
@@ -0,0 +1,250 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SMBUS_H
+#define	_SMBUS_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/promif.h>
+
+/*
+ * Attach flags
+ */
+#define	SETUP_REGS	0x01
+#define	NEXUS_REGISTER	0x02
+#define	IMUTEX		0x04
+#define	ADD_INTR	0x08
+#define	INTERRUPT_PRI	0x10
+
+/*
+ * Register offsets
+ */
+#define	SMB_STS		0x00
+#define	SMB_TYP		0x01
+#define	STR_PORT	0x02
+#define	DEV_ADDR	0x03
+#define	DEV_DATA0	0x04
+#define	DEV_DATA1	0x05
+#define	BLK_DATA	0x06
+#define	SMB_CMD		0x07
+
+/*
+ * Bit values for SMB_STS (status) register
+ */
+#define	FAILED		0x80
+#define	BUS_ERR		0x40
+#define	DRV_ERR		0x20
+#define	CMD_CMPL	0x10
+#define	HOST_BSY	0x08
+#define	IDLE		0x04
+#define	INDEX		0x04
+#define	TENBITS		0x02
+#define	ALERT		0x01
+
+/*
+ * Bit values for the SMB_TYP (command type) register
+ */
+#define	DEV10B_EN	0x80
+#define	QUICK_CMD	0x00
+#define	SEND_BYTE	0x10
+#define	RCV_BYTE	0x10
+#define	WR_BYTE		0x20
+#define	RD_BYTE		0x20
+#define	WR_WORD		0x30
+#define	RD_WORD		0x30
+#define	WR_BLK		0x40
+#define	RD_BLK		0x40
+#define	PRC_CALL	0x50
+#define	T_OUT		0x08
+#define	KILL		0x04
+
+#define	SMBUS_PIL	4
+
+#define	MAX_BLK_SEND	32
+
+/*
+ * Used to or in bit 0 to be 1 for I2C read address.
+ */
+#define	I2C_READ	0x01
+
+/*
+ * The maximum number of times to retry in event of
+ * a failure.
+ */
+#define	SMBUS_MAX_RETRIES	10
+
+/*
+ * If smbus_put() should make sure the buffer is flushed.
+ */
+#define	SMBUS_FLUSH 0x01
+
+/*
+ * The time in microseconds to wait before the timeout fires
+ * to protect against an interrupt never arriving.
+ */
+#define	INTR_TIMEOUT 100000
+
+/*
+ * Time to wait in microseconds for any transaction before giving up
+ * ie 10 seconds.
+ */
+#define	SMBUS_TRANS_TIMEOUT 10000000
+
+/*
+ * smbus event mode selection. select poll or interrupt mode
+ */
+
+#define	SMBUS_POLL_MODE		1	/* polling mode */
+#define	SMBUS_POLL_TIMEOUT	50000
+					/*
+					 * how long to wait(us) for
+					 * command completion.
+					 */
+#define	SMBUS_POLL_INTERVAL	1
+					/*
+					 * time (us) to wait between
+					 * polls: must be small in comparison
+					 * to the time an an i2c transaction
+					 * takes.
+					 */
+/*
+ * Scale polling retries so that the total timeout is "SMBUS_POLL_TIMEOUT"
+ */
+#define	SMBUS_POLL_MAX_RETRIES	(SMBUS_POLL_TIMEOUT/SMBUS_POLL_INTERVAL)
+
+
+/*
+ * smbus_ppvt_t contains info that is chip specific
+ * and is stored on the child's devinfo parent private data.
+ */
+typedef struct smbus_ppvt {
+	int	smbus_ppvt_addr; /* address of I2C device */
+} smbus_ppvt_t;
+
+typedef struct smbus {
+	dev_info_t		*smbus_dip;
+	int			smbus_attachflags;
+	kmutex_t		smbus_mutex;
+	kmutex_t		smbus_imutex;
+	kcondvar_t		smbus_icv;
+	kcondvar_t		smbus_cv;
+	kcondvar_t		smbus_intr_cv;
+	ddi_iblock_cookie_t	smbus_icookie;
+	int			smbus_busy;
+	int			smbus_wait;
+	int			smbus_bus;
+	i2c_transfer_t		*smbus_cur_tran;
+	dev_info_t		*smbus_cur_dip;
+	char			smbus_name[12];
+	uint8_t			*smbus_regaddr;
+	ddi_acc_handle_t	smbus_rhandle;
+	uint8_t			*smbus_configregaddr;
+	ddi_acc_handle_t	smbus_confighandle;
+	timeout_id_t		smbus_timeout;
+	int		smbus_saved_w_resid;
+	int		smbus_retries;
+	int		smbus_bytes_to_read;
+	int		smbus_poll_complete;
+							/*
+							 * Boolean:true if
+							 * polling is complete
+							 */
+	int		smbus_polling;
+							/*
+							 * Boolean: true if
+							 * driver is polling
+							 */
+	int		smbus_poll_retries;
+								/*
+								 * How many
+								 * times we
+								 * have polled
+								 * the status
+								 * register. Not
+								 * to be
+								 * confused with
+								 * "retries",
+								 * which is how
+								 * many times we
+								 * tried after
+								 * an error
+								 */
+} smbus_t;
+
+#define	PRT_INIT	0x01
+#define	PRT_WR		0x02
+#define	PRT_RD		0x04
+#define	PRT_PUT		0x08
+#define	PRT_GET		0x10
+#define	PRT_ATTACH	0x20
+#define	PRT_INTR	0x40
+#define	PRT_INTR_ERR	0x80
+#define	PRT_TRANS	0x100
+#define	PRT_SPEC	0x200
+#define	PRT_BUFFONLY	0x1000
+#define	PRT_PROM	0x2000
+
+/*
+ * smbus_switch return status
+ */
+#define	SMBUS_PENDING	0x01
+#define	SMBUS_COMPLETE	0x02
+#define	SMBUS_FAILURE	0x03
+
+#define	SMBUS_SUCCESS	0x04
+
+#define	SMBUS_SRC_STATUS	0x48
+#define	SMBUS_SRC_ENA		0x44
+#define	SMBUS_SMI		0x80000
+#define	SMBUS_SMB_INTR_STATUS	0x80000
+
+#define	SMBUS_INTR	"smbus_intr"
+#define	SMBUS_TIMEOUT	"smbus_timeout"
+#define	SMBUS_POLL	"smbus_poll"
+
+#ifdef	DEBUG
+#define	SMBUS_PRINT(a)	smbus_print a
+#else
+#define	SMBUS_PRINT(a)
+#endif
+
+
+/*
+ * Other function delcarations
+ */
+int smbus_transfer(dev_info_t *, i2c_transfer_t *);
+void smbus_print(int flags, const char *fmt, ...);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _SMBUS_H */
diff --git a/usr/src/uts/sun4u/sys/iocache.h b/usr/src/uts/sun4u/sys/iocache.h
new file mode 100644
index 0000000000..65a239821f
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/iocache.h
@@ -0,0 +1,73 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 1991-1994,1997-1998 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _SYS_IOCACHE_H
+#define	_SYS_IOCACHE_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifndef _ASM
+#include <sys/sysiosbus.h>
+#endif
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	OFF_STR_BUF_CTRL_REG	0x2800
+#define	STR_BUF_CTRL_REG_SIZE	(NATURAL_REG_SIZE)
+#define	OFF_STR_BUF_FLUSH_REG	0x2808
+#define	STR_BUF_FLUSH_REG_SIZE	(NATURAL_REG_SIZE)
+#define	OFF_STR_BUF_SYNC_REG	0x2810
+#define	STR_BUF_SYNC_REG_SIZE	(NATURAL_REG_SIZE)
+#define	STR_BUF_PAGE_TAG_DIAG	0x5800
+
+#define	STREAM_BUF_DISABLE	0x0ull
+#define	STREAM_BUF_ENABLE	0x1ull
+#define	STREAM_BUF_DIAG_ENABLE	0x2ull
+#define	IOCACHE_LINE_SIZE_MASK	0x3f		/* 64 byte line size */
+#define	STREAM_BUF_OFF		1		/* All stream bufs off */
+#define	STREAM_BUF_TIMEOUT	2		/* Streaming buf timed out */
+#define	STREAM_CACHE_LINES	16
+
+#define	STR_PG_VALID		0x2ull
+#define	STR_PG_SHIFT		11
+#define	STR_PG_MASK		0x3ffffull
+
+#if defined(_KERNEL) && !defined(_ASM)
+
+extern int stream_buf_init(struct sbus_soft_state *, caddr_t);
+extern int stream_buf_resume_init(struct sbus_soft_state *);
+extern void sync_stream_buf(struct sbus_soft_state *, uint_t, uint_t, int *,
+    uint64_t);
+
+#endif /* _KERNEL && !_ASM */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_IOCACHE_H */
diff --git a/usr/src/uts/sun4u/sys/iommu.h b/usr/src/uts/sun4u/sys/iommu.h
new file mode 100644
index 0000000000..947427280d
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/iommu.h
@@ -0,0 +1,160 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 1991-2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _SYS_IOMMU_H
+#define	_SYS_IOMMU_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#if defined(_KERNEL) && !defined(_ASM)
+#include <sys/sunddi.h>
+#include <sys/sysiosbus.h>
+#include <sys/ddi_impldefs.h>
+#endif /* defined(_KERNEL) && !defined(_ASM) */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifndef _ASM
+/* constants for DVMA */
+/*
+ * It takes an 8byte TSB entry to map i an 8k page, so the conversion
+ * from tsb size to dvma mapping is to multiply by 1000 or 0x400
+ * left shift by 10 does this
+ */
+#define	IOMMU_TSB_TO_RNG	0xa
+#define	IOMMU_TSB_SIZE_8M	0x2000
+#define	IOMMU_TSB_SIZE_16M	0x4000
+#define	IOMMU_TSB_SIZE_32M	0x8000
+#define	IOMMU_TSB_SIZE_64M	0x10000
+#define	IOMMU_TSB_SIZE_128M	0x20000
+#define	IOMMU_TSB_SIZE_256M	0x40000
+#define	IOMMU_TSB_SIZE_512M	0x80000
+#define	IOMMU_TSB_SIZE_1G	0x100000
+
+#define	IOMMU_PAGESIZE		0x2000		/* 8k page */
+#define	IOMMU_PAGEMASK		0x1fff
+#define	IOMMU_PAGEOFFSET	(IOMMU_PAGESIZE - 1)
+#define	IOMMU_N_TTES		(IOMMU_DVMA_RANGE/IOMMU_PAGESIZE)
+#define	IOMMU_TSB_TBL_SIZE	(IOMMU_N_TTES << 3)	/* 8B for each entry */
+#define	IOMMU_PAGESHIFT		13
+
+#define	OFF_IOMMU_CTRL_REG	0x2400
+#define	IOMMU_CTRL_REG_SIZE	(NATURAL_REG_SIZE)
+#define	OFF_TSB_BASE_ADDR	0x2408
+#define	TSB_BASE_ADDR_SIZE	(NATURAL_REG_SIZE)
+#define	OFF_IOMMU_FLUSH_REG	0x2410
+#define	IOMMU_FLUSH_REG		(NATURAL_REG_SIZE)
+#define	OFF_IOMMU_TLB_TAG	0x4580
+#define	OFF_IOMMU_TLB_DATA	0x4600
+
+#define	TSB_SIZE		3		/* 64M of DVMA */
+#define	TSB_SIZE_SHIFT		16
+#define	IOMMU_TLB_ENTRIES	16
+
+#define	IOMMU_DISABLE		0		/* Turns off the IOMMU */
+#define	IOMMU_ENABLE		1		/* Turns on the IOMMU */
+#define	IOMMU_TLB_VALID		0x40000000ull
+#define	IOMMU_DIAG_ENABLE	0x2ull
+
+/*
+ * Bit positions in the TLB entries
+ */
+#define	IOMMU_TLBTAG_WRITABLE	(1 << 21)
+#define	IOMMU_TLBTAB_STREAM	(1 << 20)
+#define	IOMMU_TLBTAG_SIZE	(1 << 19)
+#define	IOMMU_TLBTAG_VA_MASK	0x7ffff	/* 19-bit vpn */
+#define	IOMMU_TLBTAG_VA_SHIFT	13
+
+#define	IOMMU_TLBDATA_VALID	(1 << 30)
+#define	IOMMU_TLBDATA_LOCAL	(1 << 29)
+#define	IOMMU_TLBDATA_CACHEABLE	(1 << 28)
+#define	IOMMU_TLBDATA_PA_MASK	0xfffffff /* 28-bit ppn */
+#define	IOMMU_TLBDATA_PA_SHIFT	13
+
+/*
+ * define IOPTEs
+ */
+#define	IOTTE_PFN_MSK	0x1ffffffe000ull
+#define	IOTTE_CACHE	0x10ull
+#define	IOTTE_WRITE	0x2ull
+#define	IOTTE_STREAM	0x1000000000000000ull
+#define	IOTTE_INTRA	0x800000000000000ull
+#define	IOTTE_64K_PAGE	0x2000000000000000ull
+#endif	/* _ASM */
+#define	IOTTE_VALID	0x8000000000000000ull
+#define	IOTTE_PFN_SHIFT 13
+
+/*
+ * IOMMU pages to bytes, and back (with and without rounding)
+ */
+#define	iommu_ptob(x)	((x) << IOMMU_PAGESHIFT)
+#define	iommu_btop(x)	(((ioaddr_t)(x)) >> IOMMU_PAGESHIFT)
+#define	iommu_btopr(x)	\
+	((((ioaddr_t)(x) + IOMMU_PAGEOFFSET) >> IOMMU_PAGESHIFT))
+
+#if defined(_KERNEL) && !defined(_ASM)
+
+/* sbus nexus private dma mapping structure. */
+struct dma_impl_priv {
+	ddi_dma_impl_t mp;
+	struct sbus_soft_state *softsp;
+	volatile int sync_flag;
+	uint64_t phys_sync_flag;
+};
+
+extern int iommu_init(struct sbus_soft_state *, caddr_t);
+extern int iommu_resume_init(struct sbus_soft_state *);
+extern int iommu_dma_mctl(dev_info_t *, dev_info_t *, ddi_dma_handle_t,
+	enum ddi_dma_ctlops, off_t *, size_t *, caddr_t *, uint_t);
+extern int iommu_dma_map(dev_info_t *, dev_info_t *, struct ddi_dma_req *,
+	ddi_dma_handle_t *);
+extern int iommu_dma_allochdl(dev_info_t *, dev_info_t *, ddi_dma_attr_t *,
+	int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *);
+extern int iommu_dma_freehdl(dev_info_t *, dev_info_t *, ddi_dma_handle_t);
+extern int iommu_dma_bindhdl(dev_info_t *, dev_info_t *, ddi_dma_handle_t,
+	struct ddi_dma_req *, ddi_dma_cookie_t *, uint_t *);
+extern int iommu_dma_unbindhdl(dev_info_t *, dev_info_t *, ddi_dma_handle_t);
+extern int iommu_dma_flush(dev_info_t *, dev_info_t *, ddi_dma_handle_t,
+	off_t, size_t, uint_t);
+extern int iommu_dma_win(dev_info_t *, dev_info_t *, ddi_dma_handle_t,
+	uint_t, off_t *, size_t *, ddi_dma_cookie_t *, uint_t *);
+
+extern void iommu_dvma_kaddr_load(ddi_dma_handle_t h, caddr_t a, uint_t len,
+    uint_t index, ddi_dma_cookie_t *cp);
+
+extern void iommu_dvma_unload(ddi_dma_handle_t h, uint_t objindex, uint_t view);
+
+extern void iommu_dvma_sync(ddi_dma_handle_t h, uint_t objindex, uint_t view);
+
+#endif /* _KERNEL && !_ASM */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_IOMMU_H */
diff --git a/usr/src/uts/sun4u/sys/isadma.h b/usr/src/uts/sun4u/sys/isadma.h
new file mode 100644
index 0000000000..81c4b88d3f
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/isadma.h
@@ -0,0 +1,80 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _SYS_ISADMA_H
+#define	_SYS_ISADMA_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * definition of ebus reg spec entry:
+ */
+typedef struct {
+	uint32_t ebus_addr_hi;
+	uint32_t ebus_addr_low;
+	uint32_t ebus_size;
+} ebus_regspec_t;
+
+/*
+ * driver soft state structure:
+ */
+typedef struct {
+	dev_info_t *isadma_dip;			/* Our dip */
+	ebus_regspec_t *isadma_regp;		/* Our cached registers */
+	int32_t isadma_reglen;			/* reg len */
+	kmutex_t isadma_access_lock;		/* PIO/DMA lock */
+	kcondvar_t isadma_access_cv;		/* cv to prevent PIO's */
+	dev_info_t *isadma_ldip;		/* DMA lock dip */
+	int isadma_want;			/* Want state flag */
+} isadma_devstate_t;
+
+/*
+ * Lower bound and upper bound of DMA address space hole. Registers
+ * in this hole belong to our childs  devices.
+ */
+#define	LO_BOUND	DMAC2_ALLMASK
+#define	HI_BOUND	DMA_0XCNT
+#define	IN_CHILD_SPACE(o)	((o) > LO_BOUND && (o) < HI_BOUND)
+#define	IN_16BIT_SPACE(o)	((((o) >= DMA_0ADR) && (o) <= DMA_3WCNT) || \
+	(((o) >= DMA_4ADR) && ((o) <= DMA_7WCNT)))
+#define	IS_SEQREG(o)		(((o) == DMAC1_CLFF) || ((o) == DMAC2_CLFF))
+#define	HDL_TO_SEQREG_ADDR(h, o) \
+	((((o) >= DMA_0ADR) && ((o) <= DMA_3WCNT)) ? \
+	(h)->ahi_common.ah_addr + DMAC1_CLFF : \
+	(h)->ahi_common.ah_addr + DMAC2_CLFF)
+
+#define	BEGIN_ISADMA(o, v)	((o) == DMAC1_ALLMASK && (v))
+#define	END_ISADMA(o, v)	((o) == DMAC1_ALLMASK && (v) == 0)
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_ISADMA_H */
diff --git a/usr/src/uts/sun4u/sys/jbusppm.h b/usr/src/uts/sun4u/sys/jbusppm.h
new file mode 100644
index 0000000000..c05f86a9fa
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/jbusppm.h
@@ -0,0 +1,77 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_JBUSPPM_H
+#define	_SYS_JBUSPPM_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Driver state structure
+ */
+typedef struct {
+	dev_info_t		*dip;
+	ddi_acc_handle_t	devid_hndl;
+	ddi_acc_handle_t	estar_hndl;
+	uint64_t		*devid_csr;
+	uint64_t		*estar_csr;
+	uint64_t		*j_chng_csr;
+	int			is_master;
+	int			lyropen;		/* ref count */
+} jbppm_unit;
+
+/* offset to JBus Change Initiation Control Register */
+#define	J_CHNG_INITIATION_OFFSET	0x08
+
+/* J_ID[1] set indicates master IO bridge */
+#define	MASTER_IOBRIDGE_BIT		0x040000	/* j_id[1] */
+
+/*
+ * JBus Estar Control Register
+ */
+#define	JBUS_ESTAR_CNTL_32	0x20ULL
+#define	JBUS_ESTAR_CNTL_2	0x2ULL
+#define	JBUS_ESTAR_CNTL_1	0x1ULL
+#define	JBUS_ESTAR_CNTL_MASK (JBUS_ESTAR_CNTL_32 |	\
+    JBUS_ESTAR_CNTL_2 | JBUS_ESTAR_CNTL_1)
+
+/*
+ * JBus Change Initiation Control Register
+ */
+#define	J_CHNG_INITIATION_MASK	0x18ULL		/* Chng_Init[1:0] */
+#define	J_CHNG_START		0x10ULL
+#define	J_CHNG_OCCURED		0x18ULL
+#define	J_CHNG_DELAY_MASK	0x07ULL		/* Chng_Delay[2:0] */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_JBUSPPM_H */
diff --git a/usr/src/uts/sun4u/sys/machasi.h b/usr/src/uts/sun4u/sys/machasi.h
new file mode 100644
index 0000000000..0d87c1d6c7
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/machasi.h
@@ -0,0 +1,122 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_MACHASI_H
+#define	_SYS_MACHASI_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Spitfire ancillary state registers, for asrset_t
+ */
+#define	ASR_GSR	(3)
+
+/*
+ * alternate address space identifiers
+ *
+ * 0x00 - 0x7F are privileged
+ * 0x80 - 0xFF can be used by users
+ */
+
+
+/*
+ * UltraSPARC ASIs
+ */
+#define	ASI_NQUAD_LD		0x24	/* 128-bit atomic load */
+#define	ASI_NQUAD_LD_L		0x2c	/* 128-bit atomic load little */
+
+#define	ASI_QUAD_LDD_PHYS	0x34	/* 128-bit physical atomic load */
+#define	ASI_QUAD_LDD_PHYS_L	0x3C	/* 128-bit phys. atomic load little */
+
+#define	ASI_INTR_DISPATCH_STATUS 0x48	/* interrupt vector dispatch status */
+#define	ASI_INTR_RECEIVE_STATUS	0x49	/* interrupt vector receive status */
+
+#define	ASI_BLK_AIUP		0x70	/* block as if user primary */
+#define	ASI_BLK_AIUS		0x71	/* block as if user secondary */
+
+#define	ASI_SDB_INTR_W		0x77	/* interrupt vector dispatch */
+#define	ASI_SDB_INTR_R		0x7F	/* incoming interrupt vector */
+#define	ASI_INTR_DISPATCH	ASI_SDB_INTR_W
+#define	ASI_INTR_RECEIVE	ASI_SDB_INTR_R
+
+#define	ASI_BLK_AIUPL		0x78	/* block as if user primary little */
+#define	ASI_BLK_AIUSL		0x79	/* block as if user secondary little */
+
+/*
+ * Spitfire asis
+ */
+#define	ASI_LSU			0x45	/* load-store unit control */
+#define	ASI_DC_INVAL		0x42	/* d$ invalidate */
+
+
+#define	ASI_DC_DATA		0x46	/* d$ data */
+#define	ASI_DC_TAG		0x47	/* d$ tag */
+
+#define	ASI_UPA_CONFIG		0x4A	/* upa configuration reg */
+
+#define	ASI_ESTATE_ERR		0x4B	/* estate error enable reg */
+
+#define	ASI_AFSR		0x4C	/* asynchronous fault status */
+#define	ASI_AFAR		0x4D	/* asynchronous fault address */
+
+#define	ASI_IMMU		0x50	/* instruction mmu */
+#define	ASI_IMMU_TSB_8K		0x51	/* immu tsb 8k ptr */
+#define	ASI_IMMU_TSB_64K	0x52	/* immu tsb 64k ptr */
+#define	ASI_DEVICE_SERIAL_ID	0x53	/* device serial id */
+#define	ASI_ITLB_IN		0x54	/* immu tlb data in */
+#define	ASI_ITLB_ACCESS		0x55	/* immu tlb data access */
+#define	ASI_ITLB_TAGREAD	0x56	/* immu tlb tag read */
+#define	ASI_ITLB_DEMAP		0x57	/* immu tlb demap */
+
+#define	ASI_DMMU		0x58	/* data mmu */
+#define	ASI_MMU_CTX		ASI_DMMU
+#define	ASI_DMMU_TSB_8K		0x59	/* dmmu tsb 8k ptr */
+#define	ASI_DMMU_TSB_64K	0x5A	/* dmmu tsb 64k ptr */
+#define	ASI_DMMU_TSB_DIRECT	0x5B	/* dmmu tsb direct ptr */
+#define	ASI_DTLB_IN		0x5C	/* dmmu tlb data in */
+#define	ASI_DTLB_ACCESS		0x5D	/* dmmu tlb data access */
+#define	ASI_DTLB_TAGREAD	0x5E	/* dmmu tlb tag read */
+#define	ASI_DTLB_DEMAP		0x5F	/* dmmu tlb demap */
+
+#define	ASI_IC_DATA		0x66	/* i$ data */
+#define	ASI_IC_TAG		0x67	/* i$ tag */
+#define	ASI_IC_DECODE		0x6E	/* i$ pre-decode */
+#define	ASI_IC_NEXT		0x6F	/* i$ next field */
+
+#define	ASI_EC_W		0x76	/* e$ access write */
+#define	ASI_EC_R		0x7E	/* e$ access read */
+#define	ASI_EC_DIAG		0x4E	/* e$ diagnostic reg */
+					/* PRM calls this ASI_ECACHE_TAG */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_MACHASI_H */
diff --git a/usr/src/uts/sun4u/sys/machclock.h b/usr/src/uts/sun4u/sys/machclock.h
new file mode 100644
index 0000000000..90dda0c282
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/machclock.h
@@ -0,0 +1,116 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_MACHCLOCK_H
+#define	_SYS_MACHCLOCK_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifdef _ASM
+/*
+ * Macro to clear the NPT (non-privileged trap) bit in the %tick/%stick
+ * register.  Uses %g1-%g4.
+ */
+#define	CLEARTICKNPT				\
+	sethi	%hi(cpu_clearticknpt), %g1;	\
+	jmp	%g1 + %lo(cpu_clearticknpt);	\
+	rd	%pc, %g4
+
+#endif /* _ASM */
+
+#if defined(CPU_MODULE)
+
+/*
+ * Constants used to convert hi-res timestamps into nanoseconds
+ * (see <sys/clock.h> file for more information)
+ */
+
+#if defined(CHEETAH) || defined(HUMMINGBIRD)
+
+/*
+ * At least 3.9MHz, for slower %stick-based systems.
+ */
+#define	NSEC_SHIFT	8
+#define	VTRACE_SHIFT	8
+
+#elif defined(SPITFIRE)
+
+/*
+ * At least 62.5 MHz, for faster %tick-based systems.
+ */
+#define	NSEC_SHIFT	4
+#define	VTRACE_SHIFT	4
+
+#else
+#error "Compiling for CPU_MODULE but no CPU specified"
+#endif
+
+#endif /* CPU_MODULE */
+
+#ifndef _ASM
+
+#ifdef	_KERNEL
+
+/*
+ * Hardware watchdog variables and knobs
+ */
+
+#define	CLK_WATCHDOG_DEFAULT	10	/* 10 seconds */
+
+extern int	watchdog_enable;
+extern int	watchdog_available;
+extern int	watchdog_activated;
+extern uint_t	watchdog_timeout_seconds;
+
+/*
+ * tod module name and operations
+ */
+struct tod_ops {
+	timestruc_t	(*tod_get)(void);
+	void		(*tod_set)(timestruc_t);
+	uint_t		(*tod_set_watchdog_timer)(uint_t);
+	uint_t		(*tod_clear_watchdog_timer)(void);
+	void		(*tod_set_power_alarm)(timestruc_t);
+	void		(*tod_clear_power_alarm)(void);
+	uint64_t	(*tod_get_cpufrequency)(void);
+};
+
+extern struct tod_ops	tod_ops;
+extern char		*tod_module_name;
+
+#endif	/* _KERNEL */
+
+#endif	/* _ASM */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* !_SYS_MACHCLOCK_H */
diff --git a/usr/src/uts/sun4u/sys/machcpuvar.h b/usr/src/uts/sun4u/sys/machcpuvar.h
new file mode 100644
index 0000000000..1953374a65
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/machcpuvar.h
@@ -0,0 +1,193 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_MACHCPUVAR_H
+#define	_SYS_MACHCPUVAR_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/intr.h>
+#include <sys/clock.h>
+#include <sys/machparam.h>
+#include <sys/machpcb.h>
+#include <sys/privregs.h>
+#include <sys/machlock.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifndef	_ASM
+
+#include <sys/obpdefs.h>
+#include <sys/async.h>
+#include <sys/fm/protocol.h>
+
+/*
+ * CPU state ptl1_panic save.
+ */
+typedef struct ptl1_trapregs {
+	uint32_t	ptl1_tl;
+	uint32_t	ptl1_tt;
+	uint64_t	ptl1_tstate;
+	uint64_t	ptl1_tpc;
+	uint64_t	ptl1_tnpc;
+} ptl1_trapregs_t;
+
+typedef struct ptl1_regs {
+	ptl1_trapregs_t	ptl1_trap_regs[PTL1_MAXTL];
+	uint64_t	ptl1_g1;
+	uint64_t	ptl1_g2;
+	uint64_t	ptl1_g3;
+	uint64_t	ptl1_g4;
+	uint64_t	ptl1_g5;
+	uint64_t	ptl1_g6;
+	uint64_t	ptl1_g7;
+	uint64_t	ptl1_tick;
+	uint64_t	ptl1_dmmu_sfar;
+	uint64_t	ptl1_dmmu_sfsr;
+	uint64_t	ptl1_dmmu_tag_access;
+	uint64_t	ptl1_immu_sfsr;
+	uint64_t	ptl1_immu_tag_access;
+	struct rwindow	ptl1_rwindow[MAXWIN];
+	uint32_t	ptl1_softint;
+	uint16_t	ptl1_pstate;
+	uint8_t		ptl1_pil;
+	uint8_t		ptl1_cwp;
+	uint8_t		ptl1_wstate;
+	uint8_t		ptl1_otherwin;
+	uint8_t		ptl1_cleanwin;
+	uint8_t		ptl1_cansave;
+	uint8_t		ptl1_canrestore;
+} ptl1_regs_t;
+
+typedef struct ptl1_state {
+	ptl1_regs_t	ptl1_regs;
+	uint32_t	ptl1_entry_count;
+	uintptr_t	ptl1_stktop;
+	ulong_t		ptl1_stk[1];
+} ptl1_state_t;
+
+/*
+ * Machine specific fields of the cpu struct
+ * defined in common/sys/cpuvar.h.
+ */
+struct	machcpu {
+	struct machpcb	*mpcb;
+	uint64_t	mpcb_pa;
+	int		mutex_ready;
+	int		in_prom;
+	int		tl1_hdlr;
+	uint16_t	divisor;	/* Estar %tick clock ratio */
+	uint8_t		intrcnt;	/* number of back-to-back interrupts */
+	u_longlong_t	tmp1;		/* per-cpu tmps */
+	u_longlong_t	tmp2;		/*  used in trap processing */
+
+	struct intr_req intr_pool[INTR_PENDING_MAX];	/* intr pool */
+	struct intr_req *intr_head[PIL_LEVELS];		/* intr que heads */
+	struct intr_req *intr_tail[PIL_LEVELS];		/* intr que tails */
+	int		intr_pool_added;		/* add'l intr pool */
+	boolean_t	poke_cpu_outstanding;
+	/*
+	 * The cpu module allocates a private data structure for the
+	 * E$ data, which is needed for the specific cpu type.
+	 */
+	void		*cpu_private;		/* ptr to cpu private data */
+
+	ptl1_state_t	ptl1_state;
+
+	uint64_t	pil_high_start[HIGH_LEVELS];	/* high-level intrs */
+
+	/*
+	 * intrstat[][] is used to keep track of ticks used at a given pil
+	 * level. intrstat[pil][0] is cumulative and exported via kstats.
+	 * intrstat[pil][1] is used in intr_get_time() and is private.
+	 * 2-dimensional array improves cache locality.
+	 */
+
+	uint64_t	intrstat[PIL_MAX+1][2];
+};
+
+typedef	struct machcpu	machcpu_t;
+
+/*
+ * Macro to access the "cpu private" data structure.
+ */
+#define	CPU_PRIVATE(cp)		((cp)->cpu_m.cpu_private)
+
+/*
+ * The OpenBoot Standalone Interface supplies the kernel with
+ * implementation dependent parameters through the devinfo/property mechanism
+ */
+#define	MAXSYSNAME	20
+
+/*
+ * Used to indicate busy/idle state of a cpu.
+ * msram field will be set with ECACHE_CPU_MIRROR if we are on
+ * mirrored sram module.
+ */
+#define	ECACHE_CPU_IDLE		0x0		/* CPU is idle */
+#define	ECACHE_CPU_BUSY		0x1		/* CPU is busy */
+#define	ECACHE_CPU_MIRROR 	0x2		/* E$ is mirrored */
+#define	ECACHE_CPU_NON_MIRROR	0x3		/* E$ is not mirrored */
+
+/*
+ * A CPU FRU FMRI string minus the unum component.
+ */
+#define	CPU_FRU_FMRI		FM_FMRI_SCHEME_HC":///" \
+    FM_FMRI_LEGACY_HC"="
+
+struct cpu_node {
+	char	name[MAXSYSNAME];
+	char	fru_fmri[sizeof (CPU_FRU_FMRI) + UNUM_NAMLEN];
+	int	implementation;
+	int	version;
+	int	portid;
+	dnode_t	nodeid;
+	uint64_t	clock_freq;
+	uint_t	tick_nsec_scale;
+	union {
+		int	dummy;
+	}	u_info;
+	int	ecache_size;
+	int	ecache_linesize;
+	int	ecache_associativity;
+	int	ecache_setsize;
+	ushort_t	itlb_size;
+	ushort_t	dtlb_size;
+	int	msram;
+	uint64_t	device_id;
+};
+
+extern struct cpu_node cpunodes[];
+
+#endif	/* _ASM */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_MACHCPUVAR_H */
diff --git a/usr/src/uts/sun4u/sys/machintreg.h b/usr/src/uts/sun4u/sys/machintreg.h
new file mode 100644
index 0000000000..2ca8a37b46
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/machintreg.h
@@ -0,0 +1,186 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_MACHINTREG_H
+#define	_SYS_MACHINTREG_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Interrupt Receive Data Registers
+ *	ASI_SDB_INTR_R or ASI_INTR_RECEIVE; ASI 0x7F; VA 0x40, 0x50, 0x60
+ */
+#define	IRDR_0		0x40
+#define	IRDR_1		0x50
+#define	IRDR_2		0x60
+
+#define	UIII_IRDR_0	0x40
+#define	UIII_IRDR_1	0x48
+#define	UIII_IRDR_2	0x50
+#define	UIII_IRDR_3	0x58
+#define	UIII_IRDR_4	0x60
+#define	UIII_IRDR_5	0x68
+#define	UIII_IRDR_6	0x80
+#define	UIII_IRDR_7	0x88
+
+/*
+ * Interrupt Receive Status Register
+ *	ASI_INTR_RECEIVE_STATUS; ASI 0x49; VA 0x0
+ *
+ *	|---------------------------------------------------|
+ *	|    RESERVED (Read as 0)        | BUSY |   PORTID  |
+ *	|--------------------------------|------|-----------|
+ *	 63                             6    5   4         0
+ *
+ */
+#define	IRSR_BUSY	0x20	/* set when there's a vector received */
+#define	IRSR_PID_MASK	0x1F	/* PORTID bit mask <4:0> */
+
+/*
+ * Interrupt Dispatch Data Register
+ *	ASI_SDB_INTR_W or ASI_INTR_DISPATCH; ASI 0x77; VA 0x40, 0x50, 0x60
+ */
+#define	IDDR_0		0x40
+#define	IDDR_1		0x50
+#define	IDDR_2		0x60
+
+#define	UIII_IDDR_0	0x40
+#define	UIII_IDDR_1	0x48
+#define	UIII_IDDR_2	0x50
+#define	UIII_IDDR_3	0x58
+#define	UIII_IDDR_4	0x60
+#define	UIII_IDDR_5	0x68
+#define	UIII_IDDR_6	0x80
+#define	UIII_IDDR_7	0x88
+
+#if defined(JALAPENO) || defined(SERRANO)
+/*
+ * Interrupt Dispatch Command Register
+ *	ASI_INTR_DISPATCH or ASI_SDB_INTR_W; ASI 0x77; VA = PORTID<<14|0x70
+ *
+ *	|------------------------------------------------|
+ *	|    0    | PORTID  & BUSY/NACK   |     0x70     |
+ *	|---------|-----------------------|--------------|
+ *	 63     19 18                   14 13            0
+ */
+#define	IDCR_OFFSET	0x70		/* IDCR VA<13:0> */
+#define	IDCR_PID_SHIFT	14
+#define	IDCR_BN_SHIFT	14		/* JBUS only */
+#define	IDCR_BN_MASK	0x3		/* JBUS only */
+#else /* (JALAPENO || SERRANO) */
+/*
+ * Interrupt Dispatch Command Register
+ *	ASI_INTR_DISPATCH or ASI_SDB_INTR_W; ASI 0x77; VA = PORTID<<14|0x70
+ *
+ *	|------------------------------------------------|
+ *	|    0    | BUSY/NACK |  PORTID   |     0x70     |
+ *	|---------|-----------|-----------|--------------|
+ *	 63     29 28       24 23       14 13            0
+ */
+#define	IDCR_OFFSET	0x70		/* IDCR VA<13:0> */
+#define	IDCR_PID_SHIFT	14
+#define	IDCR_BN_SHIFT	24		/* safari only */
+#endif /* (JALAPENO || SERRANO) */
+
+/*
+ * Interrupt Dispatch Status Register
+ *	ASI_INTR_DISPATCH_STATUS; ASI 0x48; VA 0x0
+ *
+ *	|---------------------------------------------------|
+ *	|     RESERVED (Read as 0)          | NACK  | BUSY  |
+ *	|-----------------------------------|-------|-------|
+ *	 63                               2    1        0   |
+ */
+#define	IDSR_NACK	0x2		/* set if interrupt dispatch failed */
+#define	IDSR_BUSY	0x1		/* set when there's a dispatch */
+
+/*
+ * Safari systems define IDSR as 32 busy/nack pairs
+ */
+#if defined(JALAPENO) || defined(SERRANO)
+#define	IDSR_BN_SETS		4
+#define	CPUID_TO_BN_PAIR(x)	((x) & (IDSR_BN_SETS-1))
+#else /* (JALAPENO || SERRANO) */
+#define	IDSR_BN_SETS		32
+#endif /* (JALAPENO || SERRANO) */
+#define	IDSR_NACK_BIT(i)	((uint64_t)IDSR_NACK << (2 * (i)))
+#define	IDSR_BUSY_BIT(i)	((uint64_t)IDSR_BUSY << (2 * (i)))
+#define	IDSR_NACK_TO_BUSY(n)	((n) >> 1)
+#define	IDSR_BUSY_TO_NACK(n)	((n) << 1)
+#define	IDSR_NACK_IDX(bit)	(((bit) - 1) / 2)
+#define	IDSR_BUSY_IDX(bit)	((bit) / 2)
+
+/*
+ * Interrupt Number Register
+ *	Every interrupt source has a register associated with it
+ *
+ *	|---------------------------------------------------|
+ *	|INT_EN |  PORTID  |RESERVED (Read as 0)| INT_NUMBER|
+ *	|       |          |                    | IGN | INO |
+ *	|-------|----------|--------------------|-----|-----|
+ *	|  31    30      26 25                11 10  6 5   0
+ */
+#define	INR_EN_SHIFT	31
+#define	INR_PID_SHIFT	26
+#define	INR_PID_MASK	(IRSR_PID_MASK << (INR_PID_SHIFT))
+#ifdef	_STARFIRE
+/*
+ * Starfire interrupt group number is 7 bits
+ * Starfire's IGN (inter group #) is not the same as upaid
+ */
+#define	IGN_SIZE	7		/* Interrupt Group Number bit size */
+#define	UPAID_TO_IGN(upaid) ((((upaid & 0x3C) >> 1) | (upaid & 0x1)) |	\
+				(((upaid & 0x2) << 4) |			\
+				((upaid & 0x40) ^ 0x40)))
+#else
+/*
+ * IGN_SIZE can be defined in a platform's makefile. If it is not defined,
+ * use a default of 5.
+ */
+#ifndef IGN_SIZE
+#define	IGN_SIZE	5		/* Interrupt Group Number bit size */
+#endif
+#define	UPAID_TO_IGN(upaid) (upaid)
+#endif	/* _STARFIRE */
+
+#define	IR_CPU_CLEAR	0x4		/* clear pending register for cpu */
+#define	IR_MASK_OFFSET	0x4
+#define	IR_SET_ITR	0x10
+#define	IR_SOFT_INT(n)	(0x000010000 << (n))
+#define	IR_SOFT_INT4	IR_SOFT_INT(4)	/* r/w - software level 4 interrupt */
+#define	IR_CPU_SOFTINT	0x8		/* set soft interrupt for cpu */
+#define	IR_CLEAR_OFFSET	0x8
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_MACHINTREG_H */
diff --git a/usr/src/uts/sun4u/sys/machparam.h b/usr/src/uts/sun4u/sys/machparam.h
new file mode 100644
index 0000000000..da0ece4207
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/machparam.h
@@ -0,0 +1,336 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+/*	Copyright (c) 1988 AT&T	*/
+/*	All Rights Reserved	*/
+
+#ifndef _SYS_MACHPARAM_H
+#define	_SYS_MACHPARAM_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifndef _ASM
+#define	ADDRESS_C(c)    c ## ul
+#else   /* _ASM */
+#define	ADDRESS_C(c)    (c)
+#endif	/* _ASM */
+
+/*
+ * Machine dependent parameters and limits - sun4u version.
+ */
+
+/*
+ * Define the VAC symbol (etc.) if we could run on a machine
+ * which has a Virtual Address Cache
+ *
+ * This stuff gotta go.
+ */
+#define	VAC			/* support virtual addressed caches */
+
+/*
+ * The maximum possible number of UPA devices in a system.
+ * MAX_UPA maybe defined in a platform's makefile.
+ */
+#ifdef	_STARFIRE
+/*
+ * We have a 7 bit id space for UPA devices in Xfire
+ */
+#define	MAX_UPA			128
+#else
+#ifndef MAX_UPA
+#define	MAX_UPA			32
+#endif
+#endif	/* _STARFIRE */
+
+/*
+ * Maximum cpuid value that we support.  NCPU can be defined in a platform's
+ * makefile.
+ */
+#if	(defined(_STARFIRE) && !defined(lint))
+#define	NCPU	64
+#else
+#ifndef NCPU
+#define	NCPU	32
+#endif
+#endif	/* _STARFIRE && !lint */
+
+/*
+ * Maximum number of processors that we support.  With CMP processors, the
+ * portid may not be equal to cpuid.  MAX_CPU_CHIPID can be defined in a
+ * platform's makefile.
+ */
+#ifndef	MAX_CPU_CHIPID
+#define	MAX_CPU_CHIPID	NCPU
+#endif
+
+/*
+ * Define the FPU symbol if we could run on a machine with an external
+ * FPU (i.e. not integrated with the normal machine state like the vax).
+ *
+ * The fpu is defined in the architecture manual, and the kernel hides
+ * its absence if it is not present, that's pretty integrated, no?
+ */
+
+/*
+ * MMU_PAGES* describes the physical page size used by the mapping hardware.
+ * PAGES* describes the logical page size used by the system.
+ */
+#define	MMU_PAGE_SIZES		6	/* max sun4u mmu-supported page sizes */
+#define	DEFAULT_MMU_PAGE_SIZES	4	/* default sun4u supported page sizes */
+
+/*
+ * XXX make sure the MMU_PAGESHIFT definition here is
+ * consistent with the one in param.h
+ */
+#define	MMU_PAGESHIFT		13
+#define	MMU_PAGESIZE		(1<<MMU_PAGESHIFT)
+#define	MMU_PAGEOFFSET		(MMU_PAGESIZE - 1)
+#define	MMU_PAGEMASK		(~MMU_PAGEOFFSET)
+
+#define	MMU_PAGESHIFT64K	16
+#define	MMU_PAGESIZE64K		(1 << MMU_PAGESHIFT64K)
+#define	MMU_PAGEOFFSET64K	(MMU_PAGESIZE64K - 1)
+#define	MMU_PAGEMASK64K		(~MMU_PAGEOFFSET64K)
+
+#define	MMU_PAGESHIFT512K	19
+#define	MMU_PAGESIZE512K	(1 << MMU_PAGESHIFT512K)
+#define	MMU_PAGEOFFSET512K	(MMU_PAGESIZE512K - 1)
+#define	MMU_PAGEMASK512K	(~MMU_PAGEOFFSET512K)
+
+#define	MMU_PAGESHIFT4M		22
+#define	MMU_PAGESIZE4M		(1 << MMU_PAGESHIFT4M)
+#define	MMU_PAGEOFFSET4M	(MMU_PAGESIZE4M - 1)
+#define	MMU_PAGEMASK4M		(~MMU_PAGEOFFSET4M)
+
+#define	MMU_PAGESHIFT32M	25
+#define	MMU_PAGESIZE32M		(1 << MMU_PAGESHIFT32M)
+#define	MMU_PAGEOFFSET32M	(MMU_PAGESIZE32M - 1)
+#define	MMU_PAGEMASK32M		(~MMU_PAGEOFFSET32M)
+
+#define	MMU_PAGESHIFT256M	28
+#define	MMU_PAGESIZE256M	(1 << MMU_PAGESHIFT256M)
+#define	MMU_PAGEOFFSET256M	(MMU_PAGESIZE256M - 1)
+#define	MMU_PAGEMASK256M	(~MMU_PAGEOFFSET256M)
+
+#define	PAGESHIFT	13
+#define	PAGESIZE	(1<<PAGESHIFT)
+#define	PAGEOFFSET	(PAGESIZE - 1)
+#define	PAGEMASK	(~PAGEOFFSET)
+
+/*
+ * DATA_ALIGN is used to define the alignment of the Unix data segment.
+ */
+#define	DATA_ALIGN	ADDRESS_C(0x2000)
+
+/*
+ * DEFAULT KERNEL THREAD stack size.
+ */
+
+#define	DEFAULTSTKSZ	(3*PAGESIZE)
+
+/*
+ * DEFAULT initial thread stack size.
+ */
+#define	T0STKSZ		(2 * DEFAULTSTKSZ)
+
+/*
+ * KERNELBASE is the virtual address which
+ * the kernel text/data mapping starts in all contexts.
+ */
+#define	KERNELBASE	ADDRESS_C(0x01000000)
+
+/*
+ * Define the userlimits
+ */
+
+#define	USERLIMIT	ADDRESS_C(0xFFFFFFFF80000000)
+#define	USERLIMIT32	ADDRESS_C(0xFFC00000)
+
+/*
+ * Define SEGKPBASE, start of the segkp segment.
+ */
+
+#define	SEGKPBASE	ADDRESS_C(0x2a100000000)
+
+/*
+ * Define SEGMAPBASE, start of the segmap segment.
+ */
+
+#define	SEGMAPBASE	ADDRESS_C(0x2a750000000)
+
+/*
+ * SYSBASE is the virtual address which the kernel allocated memory
+ * mapping starts in all contexts.  SYSLIMIT is the end of the Sysbase segment.
+ */
+
+#define	SYSBASE		ADDRESS_C(0x30000000000)
+#define	SYSLIMIT	ADDRESS_C(0x70000000000)
+#define	SYSBASE32	ADDRESS_C(0x70000000)
+#define	SYSLIMIT32	ADDRESS_C(0x80000000)
+
+/*
+ * MEMSCRUBBASE is the base virtual address for the memory scrubber
+ * to read large pages.  It MUST be 4MB page aligned.
+ */
+
+#define	MEMSCRUBBASE	0x2a000000000
+
+/*
+ * Define the kernel address space range allocated to Open Firmware
+ */
+#define	OFW_START_ADDR	0xf0000000
+#define	OFW_END_ADDR	0xffffffff
+
+/*
+ * ARGSBASE is the base virtual address of the range which
+ * the kernel uses to map the arguments for exec.
+ */
+#define	ARGSBASE	(MEMSCRUBBASE - NCARGS)
+
+/*
+ * PPMAPBASE is the base virtual address of the range which
+ * the kernel uses to quickly map pages for operations such
+ * as ppcopy, pagecopy, pagezero, and pagesum.
+ */
+#define	PPMAPSIZE	(512 * 1024)
+#define	PPMAPBASE	(ARGSBASE - PPMAPSIZE)
+
+#define	MAXPP_SLOTS	ADDRESS_C(16)
+#define	PPMAP_FAST_SIZE	(MAXPP_SLOTS * PAGESIZE * NCPU)
+#define	PPMAP_FAST_BASE	(PPMAPBASE - PPMAP_FAST_SIZE)
+
+/*
+ * PIOMAPBASE is the base virtual address at which programmable I/O registers
+ * are mapped.  This allows such memory -- which may induce side effects when
+ * read -- to be cordoned off from the system at-large.
+ */
+#define	PIOMAPSIZE	(1024 * 1024 * 1024 * (uintptr_t)5)
+#define	PIOMAPBASE	(PPMAP_FAST_BASE - PIOMAPSIZE)
+
+/*
+ * Allocate space for kernel modules on nucleus pages
+ */
+#define	MODDATA	1024 * 256
+
+/*
+ * On systems with <MODTEXT_SM_SIZE MB available physical memory,
+ * cap the in-nucleus module text to MODTEXT_SM_CAP bytes.  The
+ * cap must be a multiple of the base page size.  Also see startup.c.
+ */
+#define	MODTEXT_SM_CAP		(0x200000)		/* bytes */
+#define	MODTEXT_SM_SIZE		(256)			/* MB */
+
+/*
+ * The heap has a region allocated from it specifically for module text that
+ * cannot fit on the nucleus page.  This region -- which starts at address
+ * HEAPTEXT_BASE and runs for HEAPTEXT_SIZE bytes -- has virtual holes
+ * punched in it: for every HEAPTEXT_MAPPED bytes of available virtual, there
+ * is a virtual hole of size HEAPTEXT_UNMAPPED bytes sitting beneath it.  This
+ * assures that any text address is within HEAPTEXT_MAPPED of an unmapped
+ * region.  The unmapped regions themselves are managed with the routines
+ * kobj_texthole_alloc() and kobj_texthole_free().
+ */
+#define	HEAPTEXT_SIZE		(128 * 1024 * 1024)	/* bytes */
+#define	HEAPTEXT_OVERSIZE	(64 * 1024 * 1024)	/* bytes */
+#define	HEAPTEXT_BASE		(SYSLIMIT32 - HEAPTEXT_SIZE)
+#define	HEAPTEXT_MAPPED		(2 * 1024 * 1024)
+#define	HEAPTEXT_UNMAPPED	(2 * 1024 * 1024)
+
+#define	HEAPTEXT_NARENAS	\
+	(HEAPTEXT_SIZE / (HEAPTEXT_MAPPED + HEAPTEXT_UNMAPPED) + 2)
+
+/*
+ * Preallocate an area for setting up the user stack during
+ * the exec(). This way we have a faster allocator and also
+ * make sure the stack is always VAC aligned correctly. see
+ * get_arg_base() in startup.c.
+ */
+#define	ARG_SLOT_SIZE	(0x8000)
+#define	ARG_SLOT_SHIFT	(15)
+#define	N_ARG_SLOT	(0x80)
+
+#define	NARG_BASE	(PIOMAPBASE - (ARG_SLOT_SIZE * N_ARG_SLOT))
+
+/*
+ * ktextseg+kvalloc should not use space beyond KERNEL_LIMIT32.
+ */
+
+/*
+ * For 64-bit kernels, rename KERNEL_LIMIT to KERNEL_LIMIT32 to more accurately
+ * reflect the fact that it's actually the limit for 32-bit kernel virtual
+ * addresses.
+ */
+#define	KERNEL_LIMIT32	(SYSBASE32)
+
+#define	PFN_TO_BUSTYPE(pfn)	(((pfn) >> 19) & 0x1FF)
+#define	BUSTYPE_TO_PFN(btype, pfn)			\
+	(((btype) << 19) | ((pfn) & 0x7FFFF))
+#define	IO_BUSTYPE(pfn)	((PFN_TO_BUSTYPE(pfn) & 0x100) >> 8)
+
+#ifdef	_STARFIRE
+#define	PFN_TO_UPAID(pfn)	BUSTYPE_TO_UPAID(PFN_TO_BUSTYPE(pfn))
+#else
+#define	PFN_TO_UPAID(pfn)	(((pfn) >> 20) & 0x1F)
+#endif	/* _STARFIRE */
+
+/*
+ * Defines used for the ptl1_panic parameter, which is passed to the
+ * ptl1_panic assembly routine in %g1.  These #defines have string
+ * names defined in sun4u/os/mach_cpu_states.c which should be kept up to
+ * date if new #defines are added.
+ */
+#define	PTL1_BAD_DEBUG		0
+#define	PTL1_BAD_WTRAP		1
+#define	PTL1_BAD_KMISS		2
+#define	PTL1_BAD_KPROT_FAULT	3
+#define	PTL1_BAD_ISM		4
+#define	PTL1_BAD_MMUTRAP	5
+#define	PTL1_BAD_TRAP		6
+#define	PTL1_BAD_FPTRAP		7
+#define	PTL1_BAD_INTR_REQ	8
+#define	PTL1_BAD_TRACE_PTR	9
+#define	PTL1_BAD_STACK		10
+#define	PTL1_BAD_DTRACE_FLAGS	11
+#define	PTL1_BAD_CTX_STEAL	12
+#define	PTL1_BAD_ECC		13
+
+/*
+ * Defines used for ptl1 related data structs.
+ */
+#define	PTL1_MAXTL		4
+#define	PTL1_DEBUG_TRAP		0x7C
+#define	PTL1_SSIZE		1024	/* minimum stack size */
+#define	CPU_ALLOC_SIZE		MMU_PAGESIZE
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_MACHPARAM_H */
diff --git a/usr/src/uts/sun4u/sys/machsystm.h b/usr/src/uts/sun4u/sys/machsystm.h
new file mode 100644
index 0000000000..f69d2a6f1e
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/machsystm.h
@@ -0,0 +1,431 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_MACHSYSTM_H
+#define	_SYS_MACHSYSTM_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * Numerous platform-dependent interfaces that don't seem to belong
+ * in any other header file.
+ *
+ * This file should not be included by code that purports to be
+ * platform-independent.
+ */
+
+#ifndef _ASM
+#include <sys/types.h>
+#include <sys/scb.h>
+#include <sys/varargs.h>
+#include <sys/machparam.h>
+#include <sys/thread.h>
+#include <vm/seg_enum.h>
+#include <sys/processor.h>
+#include <sys/sunddi.h>
+#include <sys/memlist.h>
+#include <sys/async.h>
+#include <sys/errorq.h>
+#endif /* _ASM */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef _KERNEL
+
+#ifndef _ASM
+/*
+ * The following enum types determine how interrupts are distributed
+ * on a sun4u system.
+ */
+enum intr_policies {
+	/*
+	 * Target interrupt at the CPU running the add_intrspec
+	 * thread. Also used to target all interrupts at the panicing
+	 * CPU.
+	 */
+	INTR_CURRENT_CPU = 0,
+
+	/*
+	 * Target all interrupts at the boot cpu
+	 */
+	INTR_BOOT_CPU,
+
+	/*
+	 * Flat distribution of all interrupts
+	 */
+	INTR_FLAT_DIST,
+
+	/*
+	 * Weighted distribution of all interrupts
+	 */
+	INTR_WEIGHTED_DIST
+};
+
+
+/*
+ * Structure that defines the interrupt distribution list. It contains
+ * enough info about the interrupt so that it can callback the parent
+ * nexus driver and retarget the interrupt to a different CPU.
+ */
+struct intr_dist {
+	struct intr_dist *next;	/* link to next in list */
+	void (*func)(void *);	/* Callback function */
+	void *arg;		/* Nexus parent callback arg 1 */
+};
+
+/*
+ * Miscellaneous cpu_state changes
+ */
+extern void power_down(const char *);
+extern void do_shutdown(void);
+
+/*
+ * Number of seconds until power is shut off
+ */
+extern int thermal_powerdown_delay;
+
+
+/*
+ * prom-related
+ */
+extern int obpdebug;
+extern int forthdebug_supported;
+extern uint_t tba_taken_over;
+extern void forthdebug_init(void);
+extern void init_vx_handler(void);
+extern void kern_preprom(void);
+extern void kern_postprom(void);
+
+/*
+ * externally (debugger or prom) initiated panic
+ */
+extern struct regs sync_reg_buf;
+extern uint64_t sync_tt;
+extern void sync_handler(void);
+
+/*
+ * Trap-related
+ */
+struct regs;
+extern void trap(struct regs *rp, caddr_t addr, uint32_t type,
+    uint32_t mmu_fsr);
+extern void *get_tba(void);
+extern void *set_tba(void *);
+extern caddr_t set_trap_table(void);
+extern struct scb trap_table;
+
+struct trap_info {
+	struct regs *trap_regs;
+	uint_t	trap_type;
+	caddr_t trap_addr;
+	uint_t	trap_mmu_fsr;
+};
+
+/*
+ * misc. primitives
+ */
+extern void debug_flush_windows(void);
+extern void flush_windows(void);
+extern int getprocessorid(void);
+extern void reestablish_curthread(void);
+
+extern void stphys(uint64_t physaddr, int value);
+extern int ldphys(uint64_t physaddr);
+extern void stdphys(uint64_t physaddr, uint64_t value);
+extern uint64_t lddphys(uint64_t physaddr);
+
+extern void stphysio(u_longlong_t physaddr, uint_t value);
+extern uint_t ldphysio(u_longlong_t physaddr);
+extern void sthphysio(u_longlong_t physaddr, ushort_t value);
+extern ushort_t ldhphysio(u_longlong_t physaddr);
+extern void stbphysio(u_longlong_t physaddr, uchar_t value);
+extern uchar_t ldbphysio(u_longlong_t physaddr);
+extern void stdphysio(u_longlong_t physaddr, u_longlong_t value);
+extern u_longlong_t lddphysio(u_longlong_t physaddr);
+
+extern int pf_is_dmacapable(pfn_t);
+
+extern int dip_to_cpu_id(dev_info_t *dip, processorid_t *cpu_id);
+
+extern void set_cmp_error_steering(void);
+
+/*
+ * SPARCv9 %ver register and field definitions
+ */
+
+#define	ULTRA_VER_MANUF(x)	((x) >> 48)
+#define	ULTRA_VER_IMPL(x)	(((x) >> 32) & 0xFFFF)
+#define	ULTRA_VER_MASK(x)	(((x) >> 24) & 0xFF)
+
+extern uint64_t ultra_getver(void);
+
+/*
+ * bootup-time
+ */
+extern int ncpunode;
+extern int niobus;
+
+extern void segnf_init(void);
+extern void kern_setup1(void);
+extern void startup(void);
+extern void post_startup(void);
+extern void install_va_to_tte(void);
+extern void setwstate(uint_t);
+extern void create_va_to_tte(void);
+extern int memscrub_init(void);
+
+extern void kcpc_hw_init(void);
+extern void kcpc_hw_startup_cpu(ushort_t);
+extern int kcpc_hw_load_pcbe(void);
+
+/*
+ * Interrupts
+ */
+struct cpu;
+extern struct cpu cpu0;
+extern size_t intr_add_pools;
+extern struct intr_req *intr_add_head;
+extern struct intr_req *intr_add_tail;
+extern struct scb *set_tbr(struct scb *);
+
+extern void init_intr_threads(struct cpu *);
+extern uint_t disable_vec_intr(void);
+extern void enable_vec_intr(uint_t);
+extern void setintrenable(int);
+
+extern void intr_dist_add(void (*f)(void *), void *);
+extern void intr_dist_rem(void (*f)(void *), void *);
+extern void intr_dist_add_weighted(void (*f)(void *, int32_t, int32_t), void *);
+extern void intr_dist_rem_weighted(void (*f)(void *, int32_t, int32_t), void *);
+
+extern uint32_t intr_dist_cpuid(void);
+
+void intr_dist_cpuid_add_device_weight(uint32_t cpuid, dev_info_t *dip,
+		int32_t weight);
+void intr_dist_cpuid_rem_device_weight(uint32_t cpuid, dev_info_t *dip);
+
+extern void intr_redist_all_cpus(void);
+extern void intr_redist_all_cpus_shutdown(void);
+
+extern void send_dirint(int, int);
+extern void setsoftint(uint_t);
+extern void setsoftint_tl1(uint64_t, uint64_t);
+extern void siron(void);
+extern uint64_t getidsr(void);
+extern void intr_enqueue_req(uint_t pil, uint32_t inum);
+extern void intr_dequeue_req(uint_t pil, uint32_t inum);
+extern void wr_clr_softint(uint_t);
+
+/*
+ * Time- and %tick-related
+ */
+extern hrtime_t rdtick(void);
+extern void tick_write_delta(uint64_t);
+extern void tickcmpr_set(uint64_t);
+extern void tickcmpr_reset(void);
+extern void tickcmpr_disable(void);
+extern int tickcmpr_disabled(void);
+extern uint32_t cbe_level14_inum;
+
+/*
+ * Caches
+ */
+extern int vac;
+extern int cache;
+extern int use_mp;
+extern uint_t vac_mask;
+extern uint64_t ecache_flushaddr;
+extern int dcache_size;		/* Maximum dcache size */
+extern int dcache_linesize;	/* Minimum dcache linesize */
+extern int icache_size;		/* Maximum icache size */
+extern int icache_linesize;	/* Minimum icache linesize */
+extern int ecache_alignsize;	/* Maximum ecache linesize for struct align */
+extern int ecache_size;		/* Maximum ecache size */
+extern int ecache_associativity;	/* ecache associativity */
+extern int ecache_setsize;	/* Maximum ecache setsize possible */
+extern int cpu_setsize;		/* Maximum ecache setsize of configured cpus */
+
+/*
+ * VM
+ */
+extern int do_pg_coloring;
+extern int do_virtual_coloring;
+extern int use_page_coloring;
+extern int use_virtual_coloring;
+extern uint_t vac_colors_mask;
+
+extern void ndata_alloc_init(struct memlist *, uintptr_t, uintptr_t);
+extern void *ndata_alloc(struct memlist *, size_t, size_t);
+extern void *ndata_extra_base(struct memlist *, size_t);
+extern size_t ndata_maxsize(struct memlist *);
+extern size_t ndata_spare(struct memlist *, size_t, size_t);
+extern int ndata_alloc_cpus(struct memlist *);
+extern int ndata_alloc_page_freelists(struct memlist *, int);
+extern int ndata_alloc_dmv(struct memlist *);
+extern int ndata_alloc_tsbs(struct memlist *, pgcnt_t);
+extern int ndata_alloc_hat(struct memlist *, pgcnt_t, pgcnt_t);
+extern caddr_t alloc_page_freelists(int, caddr_t, int);
+extern caddr_t alloc_hme_buckets(caddr_t, int);
+extern size_t page_ctrs_sz(void);
+extern caddr_t page_ctrs_alloc(caddr_t);
+extern void page_freelist_coalesce_all(int);
+extern void ppmapinit(void);
+extern void hwblkpagecopy(const void *, void *);
+extern void hw_pa_bcopy32(uint64_t, uint64_t);
+
+extern int pp_slots;
+extern int pp_consistent_coloring;
+
+/*
+ * ppcopy/hwblkpagecopy interaction.  See ppage.c.
+ */
+#define	PPAGE_STORE_VCOLORING	0x1 /* use vcolors to maintain consistency */
+#define	PPAGE_LOAD_VCOLORING	0x2 /* use vcolors to maintain consistency */
+#define	PPAGE_STORES_POLLUTE	0x4 /* stores pollute VAC */
+#define	PPAGE_LOADS_POLLUTE	0x8 /* loads pollute VAC */
+
+/*
+ * VIS-accelerated copy/zero
+ */
+extern int use_hw_bcopy;
+extern uint_t hw_copy_limit_1;
+extern uint_t hw_copy_limit_2;
+extern uint_t hw_copy_limit_4;
+extern uint_t hw_copy_limit_8;
+extern int use_hw_bzero;
+
+#ifdef CHEETAH
+#define	VIS_COPY_THRESHOLD 256
+#else
+#define	VIS_COPY_THRESHOLD 900
+#endif
+
+/*
+ * MP
+ */
+extern void idle_other_cpus(void);
+extern void resume_other_cpus(void);
+extern void stop_other_cpus(void);
+extern void idle_stop_xcall(void);
+extern void set_idle_cpu(int);
+extern void unset_idle_cpu(int);
+extern void mp_cpu_quiesce(struct cpu *);
+
+/*
+ * Error handling
+ */
+extern void set_error_enable(uint64_t neer);
+extern void set_error_enable_tl1(uint64_t neer, uint64_t action);
+extern uint64_t get_error_enable(void);
+extern void get_asyncflt(uint64_t *afsr);
+extern void set_asyncflt(uint64_t afsr);
+extern void get_asyncaddr(uint64_t *afar);
+extern void scrubphys(uint64_t paddr, int ecache_size);
+extern void clearphys(uint64_t paddr, int ecache_size, int ecache_linesize);
+extern void flushecacheline(uint64_t paddr, int ecache_size);
+extern int ce_scrub_xdiag_recirc(struct async_flt *, errorq_t *,
+    errorq_elem_t *, size_t);
+extern char *flt_to_error_type(struct async_flt *);
+
+/*
+ * Panic at TL > 0
+ */
+extern uint64_t cpu_pa[];
+extern void ptl1_init_cpu(struct cpu *);
+
+/*
+ * Defines for DR interfaces
+ */
+#define	DEVI_BRANCH_CHILD	0x01	/* Walk immediate children of root  */
+#define	DEVI_BRANCH_CONFIGURE	0x02	/* Configure branch after create    */
+#define	DEVI_BRANCH_DESTROY	0x04	/* Destroy branch after unconfigure */
+#define	DEVI_BRANCH_EVENT	0x08	/* Post NDI event		    */
+#define	DEVI_BRANCH_PROM	0x10	/* Branches derived from PROM nodes */
+#define	DEVI_BRANCH_SID		0x20	/* SID node branches		    */
+#define	DEVI_BRANCH_ROOT	0x40	/* Node is the root of a branch	    */
+
+typedef struct devi_branch {
+	void		*arg;
+	void		(*devi_branch_callback)(dev_info_t *, void *, uint_t);
+	int		type;
+	union {
+		int	(*prom_branch_select)(dnode_t, void *, uint_t);
+		int	(*sid_branch_create)(dev_info_t *, void *, uint_t);
+	} create;
+} devi_branch_t;
+
+
+/*
+ * Prototypes which really belongs to sunddi.c, and should be moved to
+ * sunddi.c if there is another platform using these calls.
+ */
+extern int e_ddi_branch_create(dev_info_t *pdip, devi_branch_t *bp,
+    dev_info_t **dipp, uint_t flags);
+extern int e_ddi_branch_configure(dev_info_t *rdip, dev_info_t **dipp,
+    uint_t flags);
+extern int e_ddi_branch_unconfigure(dev_info_t *rdip, dev_info_t **dipp,
+    uint_t flags);
+extern int e_ddi_branch_destroy(dev_info_t *rdip, dev_info_t **dipp,
+    uint_t flags);
+extern void e_ddi_branch_hold(dev_info_t *rdip);
+extern void e_ddi_branch_rele(dev_info_t *rdip);
+extern int e_ddi_branch_held(dev_info_t *rdip);
+extern int e_ddi_branch_referenced(dev_info_t *rdip,
+    int (*cb)(dev_info_t *dip, void *, uint_t), void *arg);
+
+/*
+ * Constants which define the "hole" in the 64-bit sfmmu address space.
+ * These are set to specific values by the CPU module code.
+ */
+extern caddr_t	hole_start, hole_end;
+
+/* kpm mapping window */
+extern size_t	kpm_size;
+extern uchar_t	kpm_size_shift;
+extern caddr_t	kpm_vbase;
+
+#define	INVALID_VADDR(a)	(((a) >= hole_start && (a) < hole_end))
+
+extern void adjust_hw_copy_limits(int);
+
+#endif /* _ASM */
+
+/*
+ * Actions for set_error_enable_tl1
+ */
+#define	EER_SET_ABSOLUTE	0x0
+#define	EER_SET_SETBITS		0x1
+#define	EER_SET_CLRBITS		0x2
+
+#endif /* _KERNEL */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* _SYS_MACHSYSTM_H */
diff --git a/usr/src/uts/sun4u/sys/machthread.h b/usr/src/uts/sun4u/sys/machthread.h
new file mode 100644
index 0000000000..4716485fbd
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/machthread.h
@@ -0,0 +1,155 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_MACHTHREAD_H
+#define	_SYS_MACHTHREAD_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/asi.h>
+#include <sys/sun4asi.h>
+#include <sys/machasi.h>
+#include <sys/bitmap.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifdef	_ASM
+
+#define	THREAD_REG	%g7		/* pointer to current thread data */
+
+/*
+ * Get the processor implementation from the version register.
+ */
+#define	GET_CPU_IMPL(out)		\
+	rdpr	%ver,	out;		\
+	srlx	out, 32, out;		\
+	sll	out, 16, out;		\
+	srl	out, 16, out;
+
+#ifdef	_STARFIRE
+/*
+ * CPU_INDEX(r, scr)
+ * Returns cpu id in r.
+ * On Starfire, this is read from the Port Controller's Port ID
+ * register in local space.
+ *
+ * Need to load the 64 bit address of the PC's PortID reg
+ * using only one register. Kludge the 41 bits address constant to
+ * be 32bits by shifting it 12 bits to the right first.
+ */
+#define	LOCAL_PC_PORTID_ADDR_SRL12 0x1FFF4000
+#define	PC_PORT_ID 0xD0
+
+#define	CPU_INDEX(r, scr)			\
+	rdpr	%pstate, scr;			\
+	andn	scr, PSTATE_IE | PSTATE_AM, r;	\
+	wrpr	r, 0, %pstate;			\
+	set	LOCAL_PC_PORTID_ADDR_SRL12, r;  \
+	sllx    r, 12, r;                       \
+	or	r, PC_PORT_ID, r;		\
+	lduwa	[r]ASI_IO, r;			\
+	wrpr	scr, 0, %pstate
+
+#else /* _STARFIRE */
+
+/*
+ * UPA supports up to 32 devices while Safari supports up to
+ * 1024 devices (utilizing the SSM protocol). Based upon the
+ * value of NCPU, a 5- or 10-bit mask will be needed for
+ * extracting the cpu id.
+ */
+#if NCPU > 32
+#define	CPU_MASK	0x3ff
+#else
+#define	CPU_MASK	0x1f
+#endif	/* NCPU > 32 */
+
+/*
+ * CPU_INDEX(r, scr)
+ * Returns cpu id in r.
+ * For UPA based systems, the cpu id corresponds to the mid field in
+ * the UPA config register. For Safari based machines, the cpu id
+ * corresponds to the aid field in the Safari config register.
+ *
+ * XXX - scr reg is not used here.
+ */
+#define	CPU_INDEX(r, scr)		\
+	ldxa	[%g0]ASI_UPA_CONFIG, r;	\
+	srlx	r, 17, r;		\
+	and	r, CPU_MASK, r
+
+#endif	/* _STARFIRE */
+
+/*
+ * Given a cpu id extract the appropriate word
+ * in the cpuset mask for this cpu id.
+ */
+#if CPUSET_SIZE > CLONGSIZE
+#define	CPU_INDEXTOSET(base, index, scr)	\
+	srl	index, BT_ULSHIFT, scr;		\
+	and	index, BT_ULMASK, index;	\
+	sll	scr, CLONGSHIFT, scr;		\
+	add	base, scr, base
+#else
+#define	CPU_INDEXTOSET(base, index, scr)
+#endif	/* CPUSET_SIZE */
+
+
+/*
+ * Assembly macro to find address of the current CPU.
+ * Used when coming in from a user trap - cannot use THREAD_REG.
+ * Args are destination register and one scratch register.
+ */
+#define	CPU_ADDR(reg, scr) 		\
+	.global	cpu;			\
+	CPU_INDEX(scr, reg);		\
+	sll	scr, CPTRSHIFT, scr;	\
+	set	cpu, reg;		\
+	ldn	[reg + scr], reg
+
+#define	CINT64SHIFT	3
+
+/*
+ * Assembly macro to find the physical address of the current CPU.
+ * All memory references using VA must be limited to nucleus
+ * memory to avoid any MMU side effect.
+ */
+#define	CPU_PADDR(reg, scr)				\
+	.global cpu_pa;					\
+	CPU_INDEX(scr, reg);				\
+	sll	scr, CINT64SHIFT, scr;			\
+	set	cpu_pa, reg;				\
+	ldx	[reg + scr], reg
+
+#endif	/* _ASM */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_MACHTHREAD_H */
diff --git a/usr/src/uts/sun4u/sys/mc-us3.h b/usr/src/uts/sun4u/sys/mc-us3.h
new file mode 100644
index 0000000000..c2a78a1504
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/mc-us3.h
@@ -0,0 +1,174 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_MC_US3_H
+#define	_SYS_MC_US3_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#if defined(_KERNEL)
+
+#define	NBANKS	4
+#define	NDGRPS	2
+#define	NDIMMS	4
+#define	MAX_DEVLEN	8
+#define	TRANSFER_SIZE	64
+
+#ifndef	_ASM
+
+struct mc_soft_state {
+	dev_info_t *dip;	/* dev info of myself */
+	int portid;
+	int size;
+	void *memlayoutp;
+	volatile uchar_t *mc_base; /* Mapped base address of MC registers */
+};
+
+struct dimm_info {
+	char	label[NDGRPS * NDIMMS][MAX_DEVLEN];	/* dimm lable */
+	char	sym_flag;	/* 1: symmetric 0: asymmetric */
+	char	data[1];
+};
+
+struct pin_info {
+	uchar_t	dimmtable[144];
+	uchar_t	pintable[576];
+};
+
+/* This struct is included at the following structs to set up list */
+typedef struct mc_dlist {
+	struct mc_dlist *next;
+	struct mc_dlist *prev;
+	int id;
+} mc_dlist_t;
+
+/* unique segment id */
+struct seg_info {
+	mc_dlist_t seg_node;
+	int nbanks;		/* The number of banks at this segment */
+	uint32_t ifactor;	/* Max interleave factor at this segment */
+	uint64_t base;
+	uint64_t size;		/* memory size per segment */
+	struct bank_info *hb_inseg;	/* first bank at this segment */
+	struct bank_info *tb_inseg;	/* last bank at this segment */
+};
+
+/* id = mc_id * nbanks + bank_no */
+struct bank_info {
+	mc_dlist_t bank_node;
+	int local_id;		/* unique local bank id per segment */
+	int seg_id;		/* unique segment id */
+	int devgrp_id;		/* unique device group id */
+	ushort_t valid;		/* valid flag per logic bank */
+	ushort_t uk;		/* Upper Mask field to mask match 4 PA[37:26] */
+	uint_t um;		/* Upper Match field to match PA[42:26] */
+	uchar_t lk;		/* Lower Mask field to mask match 4 PA[9:6] */
+	uchar_t lm;		/* Lower Match field to match PA[9:6] */
+	uint64_t size;		/* memory size per logical bank */
+	struct bank_info *n_inseg; /* next bank at the same segment */
+	struct bank_info *p_inseg; /* previous bank at the same segment */
+	struct dimm_info *dimminfop;
+};
+
+/* id = mc_id * ndevgrps + devgrp_no */
+struct dgrp_info {
+	mc_dlist_t dgrp_node;
+	int ndevices;	/* The number of available devices on this dev group */
+	uint64_t size;	/* memory size per physical dimm group */
+	int deviceids[NDIMMS];	/* 4 dimms per group on excalibur */
+};
+
+/* id = id of dgrp_info * ndevices + device_no */
+struct device_info {
+	mc_dlist_t dev_node;
+	char label[MAX_DEVLEN];
+	uint64_t size;		/* memory size per physical dimm */
+};
+
+/* id = portid */
+struct mctrl_info {
+	mc_dlist_t mctrl_node;
+	int ndevgrps;		/* The number of dimm groups */
+	int devgrpids[NDGRPS];
+};
+
+extern int (*p2get_mem_unum)(int, uint64_t, char *, int, int *);
+extern int (*p2get_mem_info)(int, uint64_t, uint64_t *, uint64_t *,
+    uint64_t *, int *, int *, int *);
+extern int plat_add_mem_unum_label(char *, int, int, int);
+
+uint64_t get_mcr(int);
+
+#ifdef	DEBUG
+
+#include <sys/promif.h>
+
+/* useful debugging level of DPRINTF */
+#define	MC_ATTACH_DEBUG	0x00000001
+#define	MC_DETACH_DEBUG	0x00000002
+#define	MC_CMD_DEBUG	0x00000004
+#define	MC_REG_DEBUG	0x00000008
+#define	MC_GUNUM_DEBUG	0x00000010
+#define	MC_CNSTRC_DEBUG	0x00000020
+#define	MC_DESTRC_DEBUG	0x00000040
+#define	MC_LIST_DEBUG	0x00000080
+
+static uint_t mc_debug = 0;
+
+#define	_PRINTF prom_printf
+#define	DPRINTF(flag, args)	if (mc_debug & flag) _PRINTF args;
+#else
+#define	DPRINTF(flag, args)
+
+#endif /* DEBUG */
+
+#endif	/* !_ASM */
+
+/* Memory Address Decoding Registers */
+#define	ASI_MCU_CTRL	0x72
+#define	REGOFFSET	8
+#define	MADR0OFFSET	0x10
+
+/* Mask and shift constants for Memory Address Decoding */
+#define	MADR_UPA_MASK	0x7fffc000000LL		/* 17 bits */
+#define	MADR_LPA_MASK	0x000000003c0LL		/* 4 bits */
+#define	MADR_LK_MASK	0x0000003c000LL		/* 4 bits */
+
+#define	MADR_UPA_SHIFT	26
+#define	MADR_LPA_SHIFT	6
+#define	MADR_LK_SHIFT	14
+
+#endif	/* _KERNEL */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_MC_US3_H */
diff --git a/usr/src/uts/sun4u/sys/mc-us3i.h b/usr/src/uts/sun4u/sys/mc-us3i.h
new file mode 100644
index 0000000000..28e9d9acf8
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/mc-us3i.h
@@ -0,0 +1,226 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_MC_US3I_H
+#define	_SYS_MC_US3I_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#if defined(_KERNEL)
+
+#define	NDGRPS_PER_MC		2		/* max dimm groups per mctrl */
+#define	NDIMMS_PER_DGRP		2		/* max dimms in a group/pair */
+#define	NLOGBANKS_PER_DGRP	2		/* max logical banks per grp */
+#define	NLOGBANKS_PER_MC	16		/* max logical banks per mc */
+#define	NLOGBANKS_PER_SEG	16		/* max logical banks per seg */
+#define	MAX_DEVLEN		8
+#define	TRANSFER_SIZE		64
+
+#define	MC_SELECT_MASK		0x3000000000LL	/* upto 4 MCs at 64GB boundry */
+#define	MC_SELECT_SHIFT		36
+#define	DIMM_PAIR_SELECT_MASK	0x200000000LL	/* at 8GB boundry */
+#define	DIMM_PAIR_SELECT_SHIFT	33
+#define	LOG_BANK_SELECT_MASK	0x100000000LL	/* at 4GB boundry */
+#define	LOG_BANK_SELECT_SHIFT	32
+#define	XOR_DEVICE_SELECT_MASK	0x200000LL	/* at 2MB boundry */
+#define	XOR_DEVICE_SELECT_SHIFT	21
+#define	XOR_BANK_SELECT_MASK	0x100000LL	/* at 1MB boundry */
+#define	XOR_BANK_SELECT_SHIFT	20
+
+#define	MC_SIZE_MAX		0x1000000000LL	/* 64GB */
+#define	DGRP_SIZE_MAX		0x200000000LL	/*  8GB */
+#define	BANK_SIZE_MAX		0x100000000LL	/*  4GB */
+
+#define	MC_BASE(id)		(id * MC_SIZE_MAX)
+#define	DGRP_BASE(id)		((id & (NDGRPS_PER_MC - 1)) * DGRP_SIZE_MAX)
+#define	LOGBANK_BASE(id)	((id & (NLOGBANKS_PER_SEG - 1)) * BANK_SIZE_MAX)
+
+#define	ADDR_GEN_128Mb_X8_ROW_0	14
+#define	ADDR_GEN_512Mb_X8_ROW_0	15
+
+#ifndef	_ASM
+
+struct mc_soft_state {
+	dev_info_t	*dip;	/* dev info of myself */
+	int		portid;
+	int		mcr_read_ok;
+	uint64_t	mcreg1;
+	int		reglen;
+	void		*reg;
+	int		memlayoutlen;
+	void		*memlayoutp;
+};
+
+struct memory_reg_info {
+	uint64_t base;
+	uint64_t size;
+};
+
+struct dimm_info {
+	char	label[NDGRPS_PER_MC * NDIMMS_PER_DGRP][MAX_DEVLEN];
+	char	table_width;	/* 1: symmetric 0: asymmetric */
+	char	data[1];
+};
+
+struct pin_info {
+	uchar_t	dimmtable[18];
+	uchar_t	pintable[144];
+};
+
+/* This struct is included at the following structs to set up list */
+typedef struct mc_dlist {
+	struct mc_dlist *next;
+	struct mc_dlist *prev;
+	int id;
+} mc_dlist_t;
+
+/* unique segment id */
+struct seg_info {
+	mc_dlist_t seg_node;
+	int nbanks;		/* The number of banks at this segment */
+	uint32_t ifactor;	/* Max interleave factor at this segment */
+	uint64_t base;
+	uint64_t size;		/* memory size per segment */
+	struct bank_info *head;	/* first bank at this segment */
+	struct bank_info *tail;	/* last bank at this segment */
+};
+
+/* id = mc_id * nbanks + bank_no */
+struct bank_info {
+	mc_dlist_t bank_node;
+	int local_id;		/* unique local bank id per segment */
+	int seg_id;		/* unique segment id */
+	int devgrp_id;		/* unique device group id */
+	uint64_t mask;		/* If (Physical Address & MASK) == MATCH */
+	uint64_t match;		/* Physic Address is located at this bank. */
+	uint64_t base;		/* base address of the logical bank */
+	uint64_t size;		/* memory size per logical bank */
+	struct bank_info *next; /* next bank at the same segment */
+};
+
+/* id = id of dgrp_info * ndevices + device_no */
+struct device_info {
+	mc_dlist_t dev_node;
+	char label[MAX_DEVLEN];
+	uint64_t size;		/* memory size per physical dimm */
+};
+
+/* id = mc_id * ndevgrps + devgrp_no */
+struct dgrp_info {
+	mc_dlist_t dgrp_node;
+	int ndevices;		/* number of physical dimms - always a pair */
+	int nlogbanks;		/* number of logical banks - single or dual */
+	int base_device;	/* base density - 128Mb, 256Mb, 512Mb or 1Gb */
+	int part_type;		/* part type - x4, x8 */
+	uint64_t base;		/* physical memory base of the dev group */
+	uint64_t size;		/* total memory size of the dev group */
+	int deviceids[NDIMMS_PER_DGRP];	/* 2 dimms per group on Jalapeno */
+};
+
+/* id = portid */
+struct mctrl_info {
+	mc_dlist_t mctrl_node;
+	int ndevgrps;		/* The number of dimm groups */
+	int devgrpids[NDGRPS_PER_MC];
+	struct dimm_info *dimminfop;
+};
+
+extern int (*p2get_mem_unum)(int, uint64_t, char *, int, int *);
+extern int (*p2get_mem_info)(int, uint64_t, uint64_t *, uint64_t *,
+    uint64_t *, int *, int *, int *);
+extern int plat_add_mem_unum_label(char *, int, int, int);
+
+uint64_t get_mcr(int);
+
+/* #ifdef	DEBUG */
+
+#include <sys/promif.h>
+
+/* useful debugging level of DPRINTF */
+#define	MC_ATTACH_DEBUG	0x00000001
+#define	MC_DETACH_DEBUG	0x00000002
+#define	MC_CMD_DEBUG	0x00000004
+#define	MC_REG_DEBUG	0x00000008
+#define	MC_GUNUM_DEBUG	0x00000010
+#define	MC_CNSTRC_DEBUG	0x00000020
+#define	MC_DESTRC_DEBUG	0x00000040
+#define	MC_LIST_DEBUG	0x00000080
+
+
+#define	_PRINTF printf
+#define	DPRINTF(flag, args)	if (mc_debug & flag) _PRINTF args;
+#else
+#define	DPRINTF(flag, args)
+
+/* #endif  DEBUG */
+
+#endif	/* !_ASM */
+
+/* Memory Control Registers */
+#define	ASI_MCU_CTRL		0x72
+#define	MCREG1OFFSET		0x00
+
+/* Mask and shift constants for Memory Control Register I */
+#define	MCREG1_DIMM2_BANK3	0x8000000000000000ULL	/* bit 63 */
+#define	MCREG1_DIMM1_BANK1	0x4000000000000000ULL	/* bit 62 */
+#define	MCREG1_DIMM2_BANK2	0x2000000000000000ULL	/* bit 61 */
+#define	MCREG1_DIMM1_BANK0	0x1000000000000000ULL	/* bit 60 */
+
+#define	MCREG1_XOR_ENABLE	0x10000000000LL		/* bit 40 */
+#define	MCREG1_ADDRGEN2_MASK	0xE000000000LL		/* bits 39:37 */
+#define	MCREG1_ADDRGEN2_SHIFT	37
+#define	MCREG1_ADDRGEN1_MASK	0x1C00000000LL		/* bits 36:34 */
+#define	MCREG1_ADDRGEN1_SHIFT	34
+#define	BASE_DEVICE_128Mb	0
+#define	BASE_DEVICE_256Mb	1
+#define	BASE_DEVICE_512Mb	2
+#define	BASE_DEVICE_1Gb		3
+
+#define	MCREG1_INTERLEAVE_MASK			0x1800000LL	/* bits 24:23 */
+#define	MCREG1_INTERLEAVE_SHIFT			23
+#define	INTERLEAVE_DISABLE			0
+#define	INTERLEAVE_INTEXT_SAME_DIMM_PAIR	1
+#define	INTERLEAVE_INTERNAL			2
+#define	INTERLEAVE_INTEXT_BOTH_DIMM_PAIR	3
+
+#define	MCREG1_X4DIMM2_MASK	0x200000LL		/* bit 21 */
+#define	MCREG1_X4DIMM2_SHIFT	21
+#define	MCREG1_X4DIMM1_MASK	0x100000LL		/* bit 20 */
+#define	MCREG1_X4DIMM1_SHIFT	20
+#define	PART_TYPE_X4		1
+#define	PART_TYPE_X8		0
+
+#endif	/* _KERNEL */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_MC_US3I_H */
diff --git a/usr/src/uts/sun4u/sys/mc.h b/usr/src/uts/sun4u/sys/mc.h
new file mode 100644
index 0000000000..005ae16467
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/mc.h
@@ -0,0 +1,137 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_MC_H
+#define	_SYS_MC_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Interface of Memory Controller driver
+ *
+ * Logical view: memory -> segment -> bank -> device group -> device
+ * physical view: mc -> device group -> device
+ *
+ * MCIOC_MEM, MCIOC_SEG, MCIOC_CTRLCONF, MCIOC_CONTROL are
+ * associated with various length struct. If given number is less than the
+ * number in kernel, kernel will update the number and return EINVAL so that
+ * user could allocate enough space for the struct and fill the right number
+ * of ids at the struct.
+ *
+ * All varaiable number ids will be paired, global and local. Global id is
+ * unique in the same object list and local id is only unique to
+ * its upper layer. For instance, one memory module group has N memory modules.
+ * local ids of this memory module group is from 0 to N - 1, but global id
+ * is unique in all memory modules. So global id will be the key in the list
+ * and pass it to driver to search. Local id will be returned to user
+ * application via ioctl.
+ */
+
+#define	MCIOC		('M' << 8)
+#define	MCIOC_MEMCONF	(MCIOC|8)
+#define	MCIOC_MEM	(MCIOC|9)
+#define	MCIOC_SEG	(MCIOC|10)
+#define	MCIOC_BANK	(MCIOC|11)
+#define	MCIOC_DEVGRP	(MCIOC|12)
+#define	MCIOC_CTRLCONF	(MCIOC|13)
+#define	MCIOC_CONTROL	(MCIOC|14)
+#define	MCIOC_ECFLUSH	(MCIOC|15)
+
+/*
+ * libdevinfo property name for exporting the Memory Address
+ * Decode Registers for each Logical bank. An array of [NBANK]
+ * uint64_t's is created for each memory-controller node.
+ */
+#define	MEM_CFG_PROP_NAME	"logical-bank-ma-regs"
+
+struct mc_ids {
+	int	globalid;
+	int	localid;
+};
+
+/*
+ * Enabled memory controller is able to get memory-layout property, and
+ * it could be with or without memory.
+ */
+struct mc_memconf {
+	int nmcs;	/* The number of enabled memory controllers */
+	int nsegments;	/* The number of memory segments */
+	int nbanks;	/* The max. number of banks per segment */
+	int ndevgrps;	/* The max. number of device groups per mc */
+	int ndevs;	/* The max. number of devices per device group */
+	int len_dev;	/* The length of device label */
+	int xfer_size;	/* Data transfer size in CPU cache line */
+};
+
+struct mc_memory {
+	uint64_t size;		/* size of physical memory */
+	int nsegments;		/* The number of memory segments */
+	struct mc_ids segmentids[1]; /* segment ids for next iteration */
+};
+
+struct mc_segment {
+	int id;			/* unique segment id */
+	int ifactor;		/* interleave factor for this segment */
+	uint64_t base;		/* starting physical address */
+	uint64_t size;		/* in bytes */
+	int nbanks;		/* The number of banks at this segment */
+	struct mc_ids bankids[1]; /* logical bank ids for next iteration */
+};
+
+struct mc_bank {
+	int id;			/* unique id for logic bank */
+	struct mc_ids devgrpid;	/* Only one device group id per logical bank */
+	uint64_t mask;		/* If (Physic Address & MASK) == MATCH, */
+	uint64_t match;		/* Physic Address is located at this bank. */
+	uint64_t size;		/* memory size per logical bank */
+};
+
+struct mc_ctrlconf {
+	int nmcs;		/* The number of enabled memory controllers */
+	struct mc_ids mcids[1];	/* mc ids for next iteration */
+};
+
+struct mc_control {
+	int id;			/* unique id for memory controllers */
+	int ndevgrps;		/* The number of device groups on this mc */
+	struct mc_ids devgrpids[1]; /* device group ids for next iteration */
+};
+
+struct mc_devgrp {
+	int id;		/* unique id for device groups */
+	int ndevices;	/* The number of available devices on this dev group */
+	uint64_t size;	/* memory size per physical dimm group */
+};
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_MC_H */
diff --git a/usr/src/uts/sun4u/sys/mmu.h b/usr/src/uts/sun4u/sys/mmu.h
new file mode 100644
index 0000000000..a43bbfb58c
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/mmu.h
@@ -0,0 +1,223 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_MMU_H
+#define	_SYS_MMU_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Definitions for the SOFT MMU
+ */
+
+#define	FAST_IMMU_MISS_TT	0x64
+#define	FAST_DMMU_MISS_TT	0x68
+#define	FAST_PROT_TT		0x6c
+
+/*
+ * Constants defining alternate spaces
+ * and register layouts within them,
+ * and a few other interesting assembly constants.
+ */
+
+/*
+ * vaddr offsets of various registers
+ */
+#define	MMU_TTARGET		0x00 /* TSB tag target */
+#define	MMU_PCONTEXT		0x08 /* primary context number */
+#define	MMU_SCONTEXT		0x10 /* secondary context number */
+#define	MMU_SFSR		0x18 /* sync fault status reg */
+#define	MMU_SFAR		0x20 /* sync fault addr reg */
+#define	MMU_TSB			0x28 /* tsb base and config */
+#define	MMU_TAG_ACCESS		0x30 /* tlb tag access */
+#define	MMU_VAW			0x38 /* virtual watchpoint */
+#define	MMU_PAW			0x40 /* physical watchpoint */
+#define	MMU_TSB_PX		0x48 /* i/d tsb primary extension reg */
+#define	MMU_TSB_SX		0x50 /* d tsb secondary extension reg */
+#define	MMU_TSB_NX		0x58 /* i/d tsb nucleus extension reg */
+#define	MMU_TAG_ACCESS_EXT	0x60 /* tlb tag access extension reg */
+
+
+
+/*
+ * Synchronous Fault Status Register Layout
+ *
+ * IMMU and DMMU maintain their own SFSR Register
+ * ______________________________________________________________________
+ * |   Reserved   |  ASI | Reserved | FT | E | Cntx | PRIV | W | OW | FV|
+ * |--------------|------|----------|----|---|------|------|---|----|---|
+ *  63		24 23  16 15	  14 13 7  6  5	   4	3    2	  1   0
+ *
+ */
+#define	SFSR_FV		0x00000001	/* fault valid */
+#define	SFSR_OW		0x00000002	/* overwrite */
+#define	SFSR_W		0x00000004	/* data write */
+#define	SFSR_PR		0x00000008	/* privilege mode */
+#define	SFSR_CTX	0x00000030	/* context id */
+#define	SFSR_E		0x00000040	/* side-effect */
+#define	SFSR_FT		0x00003F80	/* fault type mask */
+#define	SFSR_ASI	0x00FF0000	/* ASI */
+
+/*
+ * Definition of FT (Fault Type) bit field of sfsr.
+ */
+#define	FT_NONE		0x00
+#define	FT_PRIV		0x01		/* privilege violation */
+#define	FT_SPEC_LD	0x02		/* speculative ld to e page */
+#define	FT_ATOMIC_NC	0x04		/* atomic to nc page */
+#define	FT_ILL_ALT	0x08		/* illegal lda/sta */
+#define	FT_NFO		0x10		/* normal access to nfo page */
+#define	FT_RANGE	0x20		/* dmmu or immu address out of range */
+#define	FT_RANGE_REG	0x40		/* jump to reg out of range */
+#define	SFSR_FT_SHIFT	7	/* amt. to shift right to get flt type */
+#define	X_FAULT_TYPE(x)	(((x) & SFSR_FT) >> SFSR_FT_SHIFT)
+
+/*
+ * Defines for CT (ConText id) bit field of sfsr.
+ */
+#define	CT_PRIMARY	0x0	/* primary */
+#define	CT_SECONDARY	0x1	/* secondary */
+#define	CT_NUCLEUS	0x2	/* nucleus */
+#define	SFSR_CT_SHIFT	4
+
+#define	SFSR_ASI_SHIFT	16
+
+/*
+ * MMU TAG TARGET register Layout
+ *
+ * +-----+---------+------+-------------------------+
+ * | 000 | context |  --  | virtual address [63:22] |
+ * +-----+---------+------+-------------------------+
+ *  63 61 60	 48 47	42 41			   0
+ */
+#define	TTARGET_CTX_SHIFT	48
+#define	TTARGET_VA_SHIFT	22
+
+/*
+ * MMU TAG ACCESS register Layout
+ *
+ * +-------------------------+------------------+
+ * | virtual address [63:13] |  context [12:0]  |
+ * +-------------------------+------------------+
+ *  63			  13	12		0
+ */
+#define	TAGACC_CTX_MASK		0x1FFF
+#define	TAGACC_SHIFT		13
+#define	TAGACC_VADDR_MASK	(~TAGACC_CTX_MASK)
+#define	TAGACC_CTX_LSHIFT	(64 - TAGACC_SHIFT)
+
+/*
+ * MMU DEMAP Register Layout
+ *
+ * +-------------------------+------+------+---------+-----+
+ * | virtual address [63:13] | rsvd | type | context |  0  |
+ * +-------------------------+------+------+---------+-----+
+ *  63			   13 12   8  7   6   5	    4 3   0
+ */
+#define	DEMAP_PRIMARY		(CT_PRIMARY << SFSR_CT_SHIFT)
+#define	DEMAP_SECOND		(CT_SECONDARY << SFSR_CT_SHIFT)
+#define	DEMAP_NUCLEUS		(CT_NUCLEUS << SFSR_CT_SHIFT)
+#define	DEMAP_TYPE_SHIFT	6
+#define	DEMAP_PAGE_TYPE		(0 << DEMAP_TYPE_SHIFT)
+#define	DEMAP_CTX_TYPE		(1 << DEMAP_TYPE_SHIFT)
+#define	DEMAP_ALL_TYPE		(2 << DEMAP_TYPE_SHIFT)
+
+/*
+ * TLB DATA ACCESS Address Layout
+ *
+ * +-------------+---------------+---+
+ * +   Not used	 |   tlb entry	 | 0 |
+ * +-------------+---------------+---+
+ *  63		9 8		3 2  0
+ */
+#define	DTACC_SHIFT	0x3
+#define	DTACC_INC	0x8
+
+/*
+ * TSB Register Layout
+ *
+ * split will always be 0.  It will not be supported by software.
+ *
+ * +----------------------+-------+-----+-------+
+ * +  tsb_base va [63:13] | split |  -  |  size |
+ * +----------------------+-------+-----+-------+
+ *  63			13   12	    11 3 2	0
+ */
+#define	TSBBASE_SHIFT		13
+#define	TSB_SZ_MASK		0x7
+
+/*
+ * MMU TAG READ register Layout
+ *
+ * +-------------------------+------------------+
+ * | virtual address [63:13] |  context [12:0]  |
+ * +-------------------------+------------------+
+ *  63			  13	12		0
+ */
+#define	TAGREAD_CTX_MASK	0x1FFF
+#define	TAGREAD_SHIFT		13
+#define	TAGREAD_VADDR_MASK	(~TAGREAD_CTX_MASK)
+
+/*
+ * MMU TAG ACCESS EXTENSION register Layout
+ *
+ * DTLB only
+ * +-----+-------+-------+-----+
+ * |  -  | pgsz1 | pgsz0 |  -  |
+ * +-----+-------+-------+-----+
+ *  63    21   19 18   16 15  0
+ */
+#define	TAGACCEXT_SHIFT		16
+#define	TAGACCEXT_MKSZPAIR(SZ1, SZ0)	(((SZ1) << 3) | (SZ0))
+
+/*
+ * MMU PRIMARY/SECONDARY CONTEXT register
+ */
+#define	CTXREG_CTX_MASK		0x1FFF
+#define	CTXREG_EXT_SHIFT	16
+#define	CTXREG_NEXT_SHIFT	58
+
+/*
+ * The kernel always runs in KCONTEXT, and no user mappings
+ * are ever valid in it (so any user access pagefaults).
+ */
+#define	KCONTEXT	0
+
+/*
+ * FLUSH_ADDR is used in the flush instruction to guarantee stores to mmu
+ * registers complete.  It is selected so it won't miss in the tlb.
+ */
+#define	FLUSH_ADDR	(KERNELBASE + 2 * MMU_PAGESIZE4M)
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _SYS_MMU_H */
diff --git a/usr/src/uts/sun4u/sys/pci/db21554_config.h b/usr/src/uts/sun4u/sys/pci/db21554_config.h
new file mode 100644
index 0000000000..66c6edbfec
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/db21554_config.h
@@ -0,0 +1,280 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 1999 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SYS_DB21554_CONFIG_H
+#define	_SYS_DB21554_CONFIG_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/types.h>
+#include <sys/pci.h>
+
+#define	DB_PCONF_PRI_HDR_OFF		0x00 /* primary offset on primary */
+#define	DB_PCONF_SEC_HDR_OFF		0x40 /* secondary offset on sec */
+#define	DB_SCONF_PRI_HDR_OFF		0x40 /* primary offset on sec */
+#define	DB_SCONF_SEC_HDR_OFF		0x00 /* secondary offset on sec */
+#define	DB_CONF_REGS			0x80 /* configuration regs after hdrs */
+#define	DB_SCONF_HDR_OFF		0x40 /* second config hdr offset */
+
+/*
+ * Some register definitions for configuration header.
+ */
+#define	DB_PCONF_MEM_CSR		PCI_CONF_BASE0
+#define	DB_PCONF_IO_CSR			PCI_CONF_BASE1
+#define	DB_PCONF_DS_IO_MEM1		PCI_CONF_BASE2
+#define	DB_PCONF_DS_MEM2		PCI_CONF_BASE3
+#define	DB_PCONF_DS_MEM3		PCI_CONF_BASE4
+#define	DB_PCONF_DS_UMEM3		PCI_CONF_BASE5
+#define	DB_PCONF_EXP_ROM		PCI_CONF_ROM
+#define	DB_PCONF_US_IO_MEM0		DB_PCONF_SEC_HDR_OFF+PCI_CONF_BASE2
+#define	DB_PCONF_US_MEM1		DB_PCONF_SEC_HDR_OFF+PCI_CONF_BASE3
+#define	DB_PCONF_US_MEM2		DB_PCONF_SEC_HDR_OFF+PCI_CONF_BASE4
+
+#define	DB_SCONF_MEM_CSR		PCI_CONF_BASE0
+#define	DB_SCONF_IO_CSR			PCI_CONF_BASE1
+#define	DB_SCONF_US_IO_MEM0		PCI_CONF_BASE2
+#define	DB_SCONF_US_MEM1		PCI_CONF_BASE3
+#define	DB_SCONF_US_MEM2		PCI_CONF_BASE4
+#define	DB_SCONF_DS_IO_MEM1		DB_SCONF_PRI_HDR_OFF+PCI_CONF_BASE2
+#define	DB_SCONF_DS_MEM2		DB_SCONF_PRI_HDR_OFF+PCI_CONF_BASE3
+#define	DB_SCONF_DS_MEM3		DB_PCONF_PRI_HDR_OFF+PCI_CONF_BASE4
+#define	DB_SCONF_DS_UMEM3		DB_PCONF_PRI_HDR_OFF+PCI_CONF_BASE5
+
+#define	DB_IO_BIT			0x00000001
+
+/* register definitions in configuration space after primary/sec. header */
+
+#define	DB_CONF_DS_CONF_ADDR		0x80 /* downstream config address */
+#define	DB_CONF_DS_CONF_DATA		0x84 /* downstream config data */
+#define	DB_CONF_US_CONF_ADDR		0x88 /* upstream config address */
+#define	DB_CONF_US_CONF_DATA		0x8C /* upstream config data */
+#define	DB_CONF_CONF_OWN		0x90 /* config own bits - word reg */
+#define	DB_CONF8_DS_CONF_OWN		0x90 /* config own bits - byte reg */
+#define	DB_CONF8_US_CONF_OWN		0x91 /* config own bits - byte reg */
+#define	DB_CONF_CONF_CSR		0x92 /* config control status - word */
+#define	DB_CONF8_DS_CONF_CSR		0x92 /* config DS CSR - byte reg */
+#define	DB_CONF8_US_CONF_CSR		0x93 /* config US CSR - byte reg */
+#define	DB_CONF_DS_MEM0_TR_BASE		0x94 /* DS memory 0 translated base */
+#define	DB_CONF_DS_IO_MEM1_TR_BASE	0x98 /* DS IO or mem 1 trans base */
+#define	DB_CONF_DS_MEM2_TR_BASE		0x9C /* DS memory 2 translated base */
+#define	DB_CONF_DS_MEM3_TR_BASE		0xA0 /* DS memory 3 translated base */
+#define	DB_CONF_US_IO_MEM0_TR_BASE	0xA4 /* DS IO or mem0 trans base */
+#define	DB_CONF_US_MEM1_TR_BASE		0xA8 /* US memory 1 translated base */
+#define	DB_CONF_DS_MEM0_SETUP		0xAC /* DS memory 0 setup */
+#define	DB_CONF_DS_IO_MEM1_SETUP	0xB0 /* DS IO or memory 1 setup */
+#define	DB_CONF_DS_MEM2_SETUP		0xB4 /* DS memory 2 setup */
+#define	DB_CONF_DS_MEM3_SETUP		0xB8 /* DS memory 3 setup */
+#define	DB_CONF_DS_UP32_MEM3_SETUP	0xBC /* Upper 32bits DS mem3 setup */
+#define	DB_CONF_PRIM_EXP_ROM_SETUP	0xC0 /* Primary Expansion ROM setup */
+#define	DB_CONF_US_IO_MEM0_SETUP	0xC4 /* Upstream IO or memory 0 setup */
+#define	DB_CONF_US_MEM1_SETUP		0xC8 /* upstream memory 1 setup */
+#define	DB_CONF_CHIP_CTRL0		0xCC /* chip control 0 */
+#define	DB_CONF_CHIP_CTRL1		0xCE /* chip control 1 */
+#define	DB_CONF_STATUS			0xD0 /* chip status */
+#define	DB_CONF_ARBITER_CTRL		0xD2 /* Arbiter control */
+#define	DB_CONF_PRIM_SERR_DISABLES	0xD4 /* primary SERR# disables */
+#define	DB_CONF_SEC_SERR_DISABLES	0xD5 /* Secondary SERR# disables */
+#define	DB_CONF_RESET_CTRL		0xD8 /* Reset Control */
+#define	DB_CONF_CAP_ID_1		0xDC /* Capabilities ID */
+#define	DB_CONF_NEXT_ITEM_PTR_1		0xDD /* Next Item Pointer */
+#define	DB_CONF_PM_CAP			0xDE /* Power Management Capabilities */
+#define	DB_CONF_PM_CSR			0xE0 /* Power Management CSR */
+#define	DB_CONF_PM_CSR_BSE		0xE2 /* PMCSR Bridge Support Exts */
+#define	DB_CONF_PM_DATA			0xE3 /* Power Management data */
+#define	DB_CONF_CAP_ID_2		0xE4 /* Capabilities ID */
+#define	DB_CONF_NEXT_ITEM_PTR_2		0xE5 /* Next Item Pointer */
+#define	DB_CONF_VPD_ADDRESS		0xE6 /* VPD Address */
+#define	DB_CONF_VPD_DATA		0xE8 /* VPD Data */
+#define	DB_CONF_CAP_ID_3		0xEC /* Capabilities ID */
+#define	DB_CONF_NEXT_ITEM_PTR_3		0xED /* Next Item Pointer */
+#define	DB_CONF_HS_CSR			0xEE /* Hotswap control status */
+
+#define	DB_VENDOR_ID		0x1011
+#define	DB_DEVICE_ID		0x46
+#define	DB_INVAL_VEND		0xffff
+
+/* configuration own register bits : Register offset 0x90-91 */
+#define	DS_CONF_OWN		0x0001 /* master owns DSconfig address/data */
+#define	US_CONF_OWN		0x0100 /* master owns USconfig address/data */
+/* the following is a 8-bit register version definition. */
+#define	DS8_CONF_OWN		0x01
+#define	US8_CONF_OWN		0x01
+
+/* configuration control status register bits: Register offset 0x92-93 */
+#define	DS_OWN_STAT		0x0001 /* downstream config own status */
+#define	DS_ENABLE		0x0002 /* enable downstream config cycles */
+#define	US_OWN_STAT		0x0100 /* upstream config own status */
+#define	US_ENABLE		0x0200 /* enable upstream config cycles */
+
+/* chip control 0 register bits: Register Offset 0xcc-cd */
+#define	DELAYED_TRANS_ORDER	0x0040 /* delayed transaction order control */
+#define	SERR_FWD		0x0080 /* forward SERR# from sec to prim */
+#define	PLOCKOUT		0x0400 /* primary lockout set */
+#define	SEC_CLK_DIS		0x0800 /* disable secondary clock */
+
+/* chip control 1 register bits: Register Offset 0xce-cf */
+#define	P_PW_THRESHOLD		0x0001
+#define	S_PW_THRESHOLD		0x0002
+#define	P_DREAD_THRESHOLD_MASK	0x000C
+#define	S_DREAD_THRESHOLD_MASK	0x0030
+#define	DREAD_THRESHOLD_VALBITS	0x3
+
+#define	US_MEM2_DISABLE		0x0000 /* disable USmem2 BAR */
+#define	PAGESIZE_256		0x0100
+#define	PAGESIZE_512		0x0200
+#define	PAGESIZE_1K		0x0300
+#define	PAGESIZE_2K		0x0400
+#define	PAGESIZE_4K		0x0500
+#define	PAGESIZE_8K		0x0600
+#define	PAGESIZE_16K		0x0700
+#define	PAGESIZE_32K		0x0800
+#define	PAGESIZE_64K		0x0900
+#define	PAGESIZE_128K		0x0A00
+#define	PAGESIZE_256K		0x0B00
+#define	PAGESIZE_512K		0x0C00
+#define	PAGESIZE_1M		0x0D00
+#define	PAGESIZE_2M		0x0E00
+#define	PAGESIZE_4M		0x0F00
+
+#define	GET_PAGESIZE(chip_ctrl1)	(((chip_ctrl1) & 0x0F00) >> 8)
+
+/* chip reset control register bits : Register Offset 0xd8-db */
+#define	RESET_CTRL_RST_SEC	0x01 /* reset secondary */
+#define	RESET_CTRL_RST		0x02 /* reset chip */
+#define	RESET_CTRL_LSTAT	0x08 /* when set, l_stat is high */
+
+/* chip status register bits : Register Offset 0xd0-d1 */
+#define	DS_DEL_MTO		0x0001 /* DS delayed master TO */
+#define	DS_DEL_RD_DISCARD	0x0002 /* DS delayed read discard */
+#define	DS_DEL_WR_DISCARD	0x0004 /* DS delayed write discard */
+#define	DS_POST_WRDATA_DISCA	0x0008
+#define	US_DEL_MTO		0x0100 /* US delayed trans master TO */
+#define	US_DEL_RD_DISCARD	0x0200 /* US delayed trans.read disc */
+#define	US_DEL_WR_DISCARD	0x0400 /* US delayed trans.writ disc */
+#define	US_POST_WRDATA_DISCA	0x0800
+
+#define	DB_PCI_REG_ADDR(bus, device, function, reg) \
+	(((bus) & 0xff) << 16) | (((device & 0x1f)) << 11) \
+		    | (((function) & 0x7) << 8) | ((reg) & 0xff)
+
+/* form a type 0 configuration address */
+#define	DB_PCI_REG_ADDR_TYPE0(bus, device, function, reg) \
+	(((1 << (device & 0x1f)) << 11) \
+		    | (((function) & 0x7) << 8) | \
+		    ((reg) & 0xfc))
+
+/* form a type 1 configuration address */
+#define	DB_PCI_REG_ADDR_TYPE1(bus, device, function, reg) \
+	((((bus) & 0xff) << 16) | (((device & 0x1f)) << 11) \
+		    | (((function) & 0x7) << 8) | ((reg) & 0xfc))
+
+
+#define	DB_ENABLE_PCI_CONF_CYCLE_TYPE0	0
+#define	DB_ENABLE_PCI_CONF_CYCLE_TYPE1	1
+
+/*
+ * add local address offsets and get the right config address double
+ * word aligned type 0 format addresses.
+ */
+#define	DB_PCI_CONF_CYCLE_TYPE0_ADDR(conf_addr) \
+	(((conf_addr) & 0xfffffffc) | DB_ENABLE_PCI_CONF_CYCLE_TYPE0)
+
+/*
+ * add local address offsets and get the right config address double
+ * word aligned type 1 format addresses.
+ */
+#define	DB_PCI_CONF_CYCLE_TYPE1_ADDR(conf_addr) \
+	(((conf_addr)  & 0xfffffffc) | DB_ENABLE_PCI_CONF_CYCLE_TYPE1)
+
+#define	PCI_HDR_SIZE	64
+
+typedef struct db_pci_header {
+	uint16_t 	venid;
+	uint16_t	devid;
+	uint16_t	command;
+	uint16_t	status;
+	uint8_t		revid;
+	uint8_t		pif;
+	uint8_t		subclass;
+	uint8_t		class;
+	uint8_t		cacheline;
+	uint8_t		lat;
+	uint8_t		hdr_type;
+	uint8_t		bist;
+	uint32_t	bar0;
+	uint32_t	bar1;
+	uint32_t	bar2;
+	uint32_t	bar3;
+	uint32_t	bar4;
+	uint32_t	bar5;
+	uint32_t	cardbus_cisp;
+	uint16_t 	sub_venid;
+	uint16_t 	sub_devid;
+	uint32_t	exprom_bar;
+	uint32_t	res1;
+	uint32_t	res2;
+	uint8_t		int_line;
+	uint8_t		int_pin;
+	uint8_t		min_gnt;
+	uint8_t		max_lat;
+} db_pci_header_t;
+
+typedef struct db_conf_regs {
+	uint32_t	ds_mem0_tr_base; /* DS memory 0 translated base */
+	uint32_t	ds_io_mem1_tr_base; /* DS IO or memory1 trans base */
+	uint32_t	ds_mem2_tr_base; /* DS memory 2 trans base */
+	uint32_t	ds_mem3_tr_base; /* DS memory 3 trans base */
+	uint32_t	us_io_mem0_tr_base; /* US IO or memory0 trans base */
+	uint32_t	us_mem1_tr_base; /* US memory 1 translated base */
+	uint32_t	ds_mem0_setup_reg; /* DS memory 0 setup reg */
+	uint32_t	ds_io_mem1_setup_reg; /* DS IO or memory1 setup reg */
+	uint32_t	ds_mem2_setup_reg; /* DS memory 2 setup reg */
+	uint64_t	ds_mem3_setup_reg; /* DS memory 3 setup reg */
+	uint32_t	p_exp_rom_setup; /* primary expansion ROM setup reg */
+	uint32_t	us_io_mem0_setup_reg; /* US IO or memory 0 setup reg */
+	uint32_t	us_mem1_setup_reg; /* US memory 1 setup reg */
+	ushort_t	chip_control0;	/* chip control 0 */
+	ushort_t	chip_control1;	/* chip control 1 */
+	ushort_t	chip_status;	/* chip status */
+	ushort_t	arb_control;	/* arbiter control */
+	uchar_t		p_serr_disables; /* primary SERR# disables */
+	uchar_t		s_serr_disables; /* secondary SERR# disables */
+	ushort_t	config_csr;	/* configuration control and status */
+	uint32_t	reset_control;	/* reset control */
+	ushort_t	pm_cap;		/* power management capabilities reg */
+	ushort_t	pm_csr;		/* power management control status */
+	uint8_t		hs_csr;		/* hotswap control status */
+} db_conf_regs_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_DB21554_CONFIG_H */
diff --git a/usr/src/uts/sun4u/sys/pci/db21554_csr.h b/usr/src/uts/sun4u/sys/pci/db21554_csr.h
new file mode 100644
index 0000000000..5e03a9c3b6
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/db21554_csr.h
@@ -0,0 +1,115 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 1999 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SYS_DB21554_CSR_H
+#define	_SYS_DB21554_CSR_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* CSR Register Offset  definitions */
+#define	DB_CSR_DS_CONF_ADDR		0x000	/* DownStream config addres */
+#define	DB_CSR_DS_CONF_DATA		0x004	/* downstream config data */
+#define	DB_CSR_US_CONF_ADDR		0x008	/* UpStream config address */
+#define	DB_CSR_US_CONF_DATA		0x00C	/* UpStream config data */
+#define	DB_CSR_CONF_OWN			0x010   /* config own bits - word reg */
+#define	DB_CSR8_DS_CONF_OWN		0x010   /* config own bits - byte reg */
+#define	DB_CSR8_US_CONF_OWN		0x011   /* config own bits - byte reg */
+#define	DB_CSR_CONF_CSR			0x012   /* config ctrl/status - word */
+#define	DB_CSR8_DS_CONF_CSR		0x012   /* DS config csr - byte */
+#define	DB_CSR8_US_CONF_CSR		0x013   /* US config csr - byte */
+#define	DB_CSR_DS_IO_ADDR		0x014	/* DS io address */
+#define	DB_CSR_DS_IO_DATA		0x018	/* DS io data */
+#define	DB_CSR_US_IO_ADDR		0x01C	/* US io address */
+#define	DB_CSR_US_IO_DATA		0x020	/* US io data */
+#define	DB_CSR_IO_OWN			0x024	/* IO Own bits - word reg */
+#define	DB_CSR8_DS_IO_OWN		0x024	/* DS IO Own bits - byte reg */
+#define	DB_CSR8_US_IO_OWN		0x025	/* DS IO Own bits - byte reg */
+#define	DB_CSR_IO_CSR			0x026	/* IO csr  - word reg */
+#define	DB_CSR8_DS_IO_CSR		0x026	/* DS IO csr - byte reg */
+#define	DB_CSR8_US_IO_CSR		0x027	/* US IO csr - byte reg */
+#define	DB_CSR_LUT_OFFSET		0x028	/* Lookup Table offset */
+#define	DB_CSR_LUT_DATA			0x02C	/* LookUp Table Data */
+
+#define	DB_CSR_I2O_OB_PL_STATUS		0x030	/* I2O outbound postlist stat */
+#define	DB_CSR_I2O_OB_PL_INTR_MASK	0x034	/* I2O outbound postlistImask */
+#define	DB_CSR_I2O_IB_PL_STATUS		0x038	/* I2O inbound postlist stat */
+#define	DB_CSR_I2O_IB_PL_INTR_MASK	0x03C	/* I2O inbound postlist Imask */
+
+#define	DB_CSR_CHIP_STATUS_CSR		0x082	/* chip status CSR */
+#define	DB_CSR_CHIP_SET_IRQ_MASK	0x084	/* chip set IRQ mask */
+#define	DB_CSR_CHIP_CLR_IRQ_MASK	0x086	/* chip clear IRQ mask */
+#define	DB_CSR_US_PAGEBOUND_IRQ0	0x088	/* US page boundary IRQ 0 */
+#define	DB_CSR_US_PAGEBOUND_IRQ1	0x08C	/* US page boundary IRQ 1 */
+#define	DB_CSR_US_PAGEBOUND_IRQ_MASK0	0x090	/* US page boundary IRQ mask0 */
+#define	DB_CSR_US_PAGEBOUND_IRQ_MASK1	0x094	/* US page boundary IRQ mask1 */
+#define	DB_CSR_PRIM_CLR_IRQ		0x098	/* Primary Clear IRQ */
+#define	DB_CSR_SEC_CLR_IRQ		0x09A	/* Secondary Clear IRQ */
+#define	DB_CSR_PRIM_SET_IRQ		0x09C	/* Primary Set IRQ */
+#define	DB_CSR_SEC_SET_IRQ		0x09E	/* Secondary Set IRQ */
+#define	DB_CSR_PRIM_CLR_IRQ_MASK	0x0A0	/* Primary Clear IRQ Mask */
+#define	DB_CSR_SEC_CLR_IRQ_MASK		0x0A2	/* Secondary Clear IRQ Mask */
+#define	DB_CSR_PRIM_SET_IRQ_MASK	0x0A4	/* Primary Set IRQ Mask */
+#define	DB_CSR_SEC_SET_IRQ_MASK		0x0A6	/* Secondary Set IRQ Mask */
+#define	DB_CSR_SCRATCHPAD_0		0x0A8	/* Scratchpad 0 */
+#define	DB_CSR_SCRATCHPAD_1		0x0AC	/* Scratchpad 1 */
+#define	DB_CSR_SCRATCHPAD_2		0x0B0	/* Scratchpad 2 */
+#define	DB_CSR_SCRATCHPAD_3		0x0B4	/* Scratchpad 3 */
+#define	DB_CSR_SCRATCHPAD_4		0x0B8	/* Scratchpad 4 */
+#define	DB_CSR_SCRATCHPAD_5		0x0BC	/* Scratchpad 5 */
+#define	DB_CSR_SCRATCHPAD_6		0x0C0	/* Scratchpad 6 */
+#define	DB_CSR_SCRATCHPAD_7		0x0C4	/* Scratchpad 7 */
+#define	DB_CSR_ROM_SETUP		0x0C8	/* ROM setup register */
+#define	DB_CSR_ROM_DATA			0x0CA	/* ROM Data register */
+#define	DB_CSR_ROM_ADDR			0x0CC	/* ROM Address register */
+#define	DB_CSR_ROM_CTRL			0x0CF	/* ROM control */
+#define	DB_CSR_US_MEM2_LUT		0x100	/* US Memory 2 Lookup Table */
+
+/* Configuration Own Bits register definition */
+#define	DS_IO_OWN			0x0001
+#define	US_IO_OWN			0x0100
+/* the following is a 8bit register bit definitions for IO own */
+#define	DS8_IO_OWN			0x01
+#define	US8_IO_OWN			0x01
+
+/* IO control status register bits: Register offset 0x26-27 */
+#define	IO_DS_OWN_STAT 0x0001  /* downstream config own status */
+#define	IO_DS_ENABLE   0x0002  /* enable downstream config cycles */
+#define	IO_US_OWN_STAT 0x0100  /* upstream config own status */
+#define	IO_US_ENABLE   0x0200  /* enable upstream config cycles */
+
+typedef volatile struct us_mem2_tbl {
+	uchar_t		unimpl[256];		/* currently unimplemented */
+} us_mem2_tbl_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_DB21554_CSR_H */
diff --git a/usr/src/uts/sun4u/sys/pci/db21554_ctrl.h b/usr/src/uts/sun4u/sys/pci/db21554_ctrl.h
new file mode 100644
index 0000000000..8bd802c822
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/db21554_ctrl.h
@@ -0,0 +1,167 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_DB21554_CTRL_H
+#define	_SYS_DB21554_CTRL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* definitions for device state */
+#define	DB_SECONDARY_NEXUS	0x80000000	/* secondary towards host */
+#define	DB_PRIMARY_NEXUS	0x40000000	/* primary towards host */
+#define	DB_ATTACHED		0x00000001	/* driver attached */
+#define	DB_SUSPENDED		0x00100000
+#define	DB_DEBUG_MODE_ON	0x01000000
+
+#define	DB_PCI_CONF_RNUMBER	0
+#define	DB_PCI_CONF_OFFSET	0
+#define	DB_CSR_MEMBAR_RNUMBER	1
+#define	DB_CSR_MEM_OFFSET	0
+#define	DB_CSR_SIZE		0x1000	/* 4K CSR space */
+#define	DB_CSR_IOBAR_RNUMBER	2
+#define	DB_CSR_IO_OFFSET	0
+#define	DB_PCI_TIMEOUT		10000	/* 10 ms */
+#define	DB_PCI_WAIT_MS		0
+#define	DB_CONF_FAILURE		-1
+
+#define	DB_PIF_SECONDARY_TO_HOST	0x80
+#define	DB_PIF_PRIMARY_TO_HOST		0x40
+
+/*
+ * The following definition could have been inherited from sys/pci/pci_var.h
+ * but that runs into including many other dependent files which are
+ * host-pci nexus specific. So declaring our own bus_range structure makes
+ * it lot easier and simpler. This is ok as bus-range format is in the
+ * pci bindings.
+ */
+typedef struct bus_range {
+	uint32_t lo;
+	uint32_t hi;
+} db_pci_bus_range_t;
+
+/*
+ * the  following definition is used to save the state of all PCI children
+ * under us.
+ */
+typedef struct db_cfg_state {
+	dev_info_t *dip;
+	uchar_t cache_line_size;
+	uchar_t latency_timer;
+	uchar_t header_type;
+	uchar_t sec_latency_timer;
+	ushort_t command;
+	ushort_t bridge_control;
+} db_cfg_state_t;
+
+/* the main control structure of our device */
+typedef struct db_ctrl {
+	dev_info_t	*dip;
+	uint32_t	dev_state;	/* device state */
+	caddr_t		csr_mem;	/* pointer to CSR map in memory space */
+	caddr_t		csr_io;		/* pointer to CSR map in IO space */
+	caddr_t		conf_io;	/* pointer to Conf indirect map */
+
+	/* our bus range information */
+	db_pci_bus_range_t	range;
+
+	/* any device tuning parameters here. */
+	uint16_t	p_command;
+	uint16_t	s_command;
+	int8_t		p_latency_timer;
+	int8_t		p_cache_line_size;
+	int8_t		s_latency_timer;
+	int8_t		s_cache_line_size;
+	int8_t		p_pwrite_threshold;
+	int8_t		s_pwrite_threshold;
+	int8_t		p_dread_threshold;
+	int8_t		s_dread_threshold;
+	int8_t		delayed_trans_order;
+	int8_t		serr_fwd_enable;
+
+	/* for child initialization */
+	uint8_t		latency_timer;
+	uint8_t		cache_line_size;
+
+	/* error holders */
+	uint32_t	db_pci_err_count; /* indirect cycle timeout count */
+#ifdef DEBUG
+	uint32_t	db_pci_max_wait_count; /* indirect cycle wait count */
+#endif
+	/* cpr related. */
+	uint_t config_state_index;
+	db_cfg_state_t *db_config_state_p;
+
+	/* all map handles below */
+	ddi_acc_handle_t csr_mem_handle;    /* CSR memory handle */
+	ddi_acc_handle_t csr_io_handle;    /* CSR IO handle */
+	ddi_acc_handle_t conf_handle;    /* config space handle */
+	ddi_iblock_cookie_t	i_block_cookie;	/* interrupt cookie */
+	kmutex_t		db_busown;	/* bus config own mutex */
+	kmutex_t db_mutex;
+	uint_t db_soft_state;
+#define	DB_SOFT_STATE_CLOSED		0x00
+#define	DB_SOFT_STATE_OPEN		0x01
+#define	DB_SOFT_STATE_OPEN_EXCL		0x02
+	int fm_cap;
+	ddi_iblock_cookie_t fm_ibc;
+}db_ctrl_t;
+
+typedef struct db_acc_cfg_addr {
+	uchar_t c_busnum;		/* bus number */
+	uchar_t c_devnum;		/* device number */
+	uchar_t c_funcnum;		/* function number */
+	uchar_t c_fill;			/* reserve field */
+} db_acc_cfg_addr_t;
+
+typedef struct db_acc_pvt {
+	db_acc_cfg_addr_t	dev_addr;	/* pci device address */
+	uint32_t	*addr;	/* upstream/downstream config addr */
+	uint32_t	*data;	/* upstream/downstream config data */
+	uint8_t		*bus_own;	/* reg to check if bus owned */
+	uint8_t		*bus_release;	/* reg to check if bus released */
+	uint8_t		mask;		/* bitmask for upstream/downstream */
+	ushort_t	access_mode;	/* access through IO or Config */
+	db_ctrl_t	*dbp;
+	ddi_acc_handle_t handle;	/* handle for bus access DDI calls */
+} db_acc_pvt_t;
+
+/* We can use the following modes for generating indirect PCI transcations */
+#define	DB_IO_MAP_DIRECT		1 /* memory mapped IO */
+#define	DB_IO_MAP_INDIRECT		2 /* indirect map IO */
+#define	DB_CONF_MAP_INDIRECT_CONF	4 /* access config via config regs */
+#define	DB_CONF_MAP_INDIRECT_IO		8 /* access config via IO regs */
+#define	DB_PCI_CONF_CYCLE_TYPE0		0x100	/* type 0 conf cycle */
+#define	DB_PCI_CONF_CYCLE_TYPE1		0x200	/* type 1 conf cycle */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_DB21554_CTRL_H */
diff --git a/usr/src/uts/sun4u/sys/pci/db21554_debug.h b/usr/src/uts/sun4u/sys/pci/db21554_debug.h
new file mode 100644
index 0000000000..5cfeae27bc
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/db21554_debug.h
@@ -0,0 +1,131 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_DB21554_DEBUG_H
+#define	_SYS_DB21554_DEBUG_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#if defined(DEBUG)
+
+/* driver modload functions */
+#define	DB_INIT			0x10
+#define	DB_FINI			0x11
+#define	DB_INFO			0x12
+#define	DB_GETINFO		0x13
+/* driver initialization functions */
+#define	DB_INIT_FUNCS		0x100
+#define	DB_ATTACH		0x100
+#define	DB_DETACH		0x101
+
+/* driver child initialization functions */
+#define	DB_CTLOPS		0x1000
+#define	DB_INITCHILD		0x1001
+#define	DB_REMOVECHILD		0x1002
+#define	DB_INTR_OPS		0x1003
+
+/* child driver services invoked during runtime */
+#define	DB_PCI_MAP		0x10000
+
+/* CPR functions */
+#define	DB_SAVE_CONF_REGS	0x100000
+#define	DB_REST_CONF_REGS	0x100001
+
+/* interrupt function */
+#define	DB_INTR			0x1000000
+
+/* application call functions */
+#define	DB_OPEN			0x10000000
+#define	DB_CLOSE		0x10000001
+#define	DB_IOCTL		0x10000002
+
+/* DVMA functions */
+#define	DB_DVMA			0x100000000
+
+/* Function types, to be assigned to db_debug_funcs variable below. */
+#define	DB_MODLOAD_FUNCS	0x10
+#define	DB_CHILD_FUNCS		0x1000
+#define	DB_PCI_MEM_FUNCS	0x10000
+#define	DB_CPR_FUNCS		0x100000
+#define	DB_INTR_FUNCS		0x1000000
+#define	DB_APPL_FUNCS		0x10000000
+#define	DB_DVMA_FUNCS		0x100000000
+
+/*
+ * db_debug_funcs indicates the function types from which the debug messages
+ * are to be displayed.
+ * For example: Set db_debug_funcs = DB_CHILD_FUNCS | DB_PCI_MEM_FUNCS;
+ * to display debug statements in memory map function (DB_PCI_MEM_FUNCS) and
+ * child driver initialization function (DB_CHILD_FUNCS).
+ *
+ * See above for a list of all function types that can be assigned.
+ */
+static uint64_t	db_debug_funcs = 0;
+
+/*
+ * the following flag can be used to the first argument of db_debug
+ * when dip information need not be displayed along with the actual
+ * function debug message. By default it is always displayed.
+ */
+#define	DB_DONT_DISPLAY_DIP	0x1000000000000000
+
+#define	DB_DEBUG0(func_id, dip, fmt)	\
+	db_debug(func_id, dip, fmt, 0, 0, 0, 0, 0);
+#define	DB_DEBUG1(func_id, dip, fmt, a1)	\
+	db_debug(func_id, dip, fmt, (uintptr_t)(a1), 0, 0, 0, 0);
+#define	DB_DEBUG2(func_id, dip, fmt, a1, a2)	\
+	db_debug(func_id, dip, fmt, (uintptr_t)(a1), (uintptr_t)(a2), 0, 0, 0);
+#define	DB_DEBUG3(func_id, dip, fmt, a1, a2, a3)	\
+	db_debug(func_id, dip, fmt, (uintptr_t)(a1),	\
+		(uintptr_t)(a2), (uintptr_t)(a3), 0, 0);
+#define	DB_DEBUG4(func_id, dip, fmt, a1, a2, a3, a4)	\
+	db_debug(func_id, dip, fmt, (uintptr_t)(a1),	\
+		(uintptr_t)(a2), (uintptr_t)(a3), \
+		(uintptr_t)(a4), 0);
+#define	DB_DEBUG5(func_id, dip, fmt, a1, a2, a3, a4, a5)	\
+	db_debug(func_id, dip, fmt, (uintptr_t)(a1),	\
+		(uintptr_t)(a2), (uintptr_t)(a3), \
+		(uintptr_t)(a4), (uintptr_t)(a5));
+
+#else
+
+#define	DB_DEBUG0(func_id, dip, fmt)
+#define	DB_DEBUG1(func_id, dip, fmt, a1)
+#define	DB_DEBUG2(func_id, dip, fmt, a1, a2)
+#define	DB_DEBUG3(func_id, dip, fmt, a1, a2, a3)
+#define	DB_DEBUG4(func_id, dip, fmt, a1, a2, a3, a4)
+#define	DB_DEBUG5(func_id, dip, fmt, a1, a2, a3, a4, a5)
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_DB21554_DEBUG_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_axq.h b/usr/src/uts/sun4u/sys/pci/pci_axq.h
new file mode 100644
index 0000000000..b10d06d208
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_axq.h
@@ -0,0 +1,65 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SYS_PCI_AXQ_H
+#define	_SYS_PCI_AXQ_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/types.h>
+#include <sys/atomic.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	PIO_LIMIT_ENTER(p)	{ \
+				int n;\
+				for (;;) {\
+					do {\
+						n = p->pbm_pio_counter;\
+					} while (n <= 0);\
+					if (atomic_add_32_nv(\
+					    (uint_t *)&p->pbm_pio_counter, -1)\
+					    == (n - 1))\
+						break;\
+					atomic_add_32(\
+					    (uint_t *)&p->pbm_pio_counter, 1);\
+				}\
+				}
+
+
+
+#define	PIO_LIMIT_EXIT(p)	atomic_add_32((uint_t *)&p->pbm_pio_counter, 1);
+
+extern void pci_axq_setup(ddi_map_req_t *mp, pbm_t *pbm_p);
+extern void pci_axq_pio_limit(pbm_t *pbm_p);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_AXQ_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_cb.h b/usr/src/uts/sun4u/sys/pci/pci_cb.h
new file mode 100644
index 0000000000..6907fc3b4f
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_cb.h
@@ -0,0 +1,104 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_CB_H
+#define	_SYS_PCI_CB_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef uint16_t cb_nid_t;
+enum cb_nintr_index {
+	CBNINTR_PBM = 0,		/* all		not shared */
+	CBNINTR_PBM66 = 0,		/* all		not shared */
+	CBNINTR_PBM33 = 0,		/* all		not shared */
+	CBNINTR_UE = 1,			/* all		shared	   */
+	CBNINTR_CE = 2,			/* all		shared	   */
+	CBNINTR_POWER_FAIL	= 3,	/* psycho	shared	   */
+	CBNINTR_POWER_BUTTON	= 3,	/* sabre	N/A	   */
+	CBNINTR_PME_HB		= 3,	/* hummingbird	N/A	   */
+	CBNINTR_BUS_ERROR	= 3,	/* schizo	shared	   */
+	CBNINTR_THERMAL 	= 4,	/* psycho	shared	   */
+	CBNINTR_PME		= 4,	/* schizo	not shared */
+	CBNINTR_CDMA		= 4,	/* schizo	not shared */
+	CBNINTR_PWR_MANAGE	= 5,	/* psycho	shared	   */
+	CBNINTR_MAX			/* count	coding	   */
+};
+
+/*
+ * control block soft state structure:
+ *
+ * Each pci node contains shares a control block structure with its peer
+ * node.  The control block node contains csr and id registers for chip
+ * and acts as a "catch all" for other functionality that does not cleanly
+ * fall into other functional blocks.  This block is also used to handle
+ * software workarounds for known hardware bugs in different chip revs.
+ */
+typedef struct cb cb_t;
+struct cb {
+	pci_common_t *cb_pci_cmn_p;
+	cb_nid_t cb_node_id;
+	pci_ign_t cb_ign;		/* 1st-attached-side interrupt grp#  */
+
+	kmutex_t cb_intr_lock;		/* guards add/rem intr and intr dist */
+	uint32_t cb_no_of_inos;		/* # of actual inos, including PBM   */
+	uint32_t cb_inos[CBNINTR_MAX];	/* subset of pci_p->pci_inos array   */
+
+	uint64_t cb_base_pa;		/* PA of schizo CSR bank, 2nd "reg"  */
+	uint64_t cb_icbase_pa;		/* PA of tomatillo IChip register    */
+					/* bank, 4th "reg" entry */
+	uint64_t cb_map_pa;		/* 1st-attached-side map reg base PA */
+	uint64_t cb_clr_pa;		/* 1st-attached-side clr reg base PA */
+	uint64_t cb_obsta_pa;		/* 1st-attached-side sta reg base PA */
+
+	uint64_t *cb_imr_save;
+
+#ifdef _STARFIRE
+	caddr_t cb_ittrans_cookie;	/* intr tgt translation */
+#endif
+};
+
+#define	CB_INO_TO_MONDO(cb_p, ino)	((cb_p)->cb_ign << PCI_INO_BITS | (ino))
+#define	CB_MONDO_TO_XMONDO(cb_p, mondo) /* local mondo to global mondo */ \
+	((cb_p)->cb_node_id << (PCI_IGN_BITS + PCI_INO_BITS) | (mondo))
+
+extern void cb_create(pci_t *pci_p);
+extern void cb_destroy(pci_t *pci_p);
+extern void cb_suspend(cb_t *cb_p);
+extern void cb_resume(cb_t *cb_p);
+extern void cb_enable_nintr(pci_t *pci_p, enum cb_nintr_index idx);
+extern void cb_disable_nintr(cb_t *cb_p, enum cb_nintr_index idx, int wait);
+extern void cb_clear_nintr(cb_t *cb_p, enum cb_nintr_index idx);
+extern void cb_intr_dist(void *arg);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_CB_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_chip.h b/usr/src/uts/sun4u/sys/pci/pci_chip.h
new file mode 100644
index 0000000000..303ce2aa33
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_chip.h
@@ -0,0 +1,124 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_CHIP_H
+#define	_SYS_PCI_CHIP_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+extern void pci_post_init_child(pci_t *pci_p, dev_info_t *child);
+extern void pci_post_uninit_child(pci_t *pci_p);
+
+extern int pci_obj_setup(pci_t *pci_p);
+extern void pci_obj_destroy(pci_t *pci_p);
+extern void pci_obj_resume(pci_t *pci_p);
+extern void pci_obj_suspend(pci_t *pci_p);
+
+extern void pci_kstat_init(void);
+extern void pci_kstat_fini(void);
+
+extern void pci_add_pci_kstat(pci_t *pci_p);
+extern void pci_rem_pci_kstat(pci_t *pci_p);
+
+extern void pci_add_upstream_kstat(pci_t *pci_p);
+
+extern void pci_fix_ranges(pci_ranges_t *rng_p, int rng_entries);
+extern int map_pci_registers(pci_t *pci_p, dev_info_t *dip);
+
+extern uint_t pbm_disable_pci_errors(pbm_t *pbm_p);
+extern uintptr_t get_pbm_reg_base(pci_t *pci_p);
+
+extern uint32_t ib_map_reg_get_cpu(volatile uint64_t reg);
+extern uint64_t *ib_intr_map_reg_addr(ib_t *ib_p, ib_ino_t ino);
+extern uint64_t *ib_clear_intr_reg_addr(ib_t *ib_p, ib_ino_t ino);
+extern void pci_pbm_intr_dist(pbm_t *pbm_p);
+
+extern void pci_cb_setup(pci_t *pci_p);
+extern void pci_cb_teardown(pci_t *pci_p);
+extern int cb_register_intr(pci_t *pci_p);
+extern void cb_enable_intr(pci_t *pci_p);
+extern uint64_t cb_ino_to_map_pa(cb_t *cb_p, ib_ino_t ino);
+extern uint64_t cb_ino_to_clr_pa(cb_t *cb_p, ib_ino_t ino);
+extern int cb_remove_xintr(pci_t *pci_p, dev_info_t *dip, dev_info_t *rdip,
+		ib_ino_t ino, ib_mondo_t mondo);
+extern uint32_t pci_xlate_intr(dev_info_t *dip, dev_info_t *rdip,
+		ib_t *ib_p, uint32_t intr);
+extern uint32_t pci_intr_dist_cpuid(ib_t *ib_p, ib_ino_info_t *ino_p);
+
+extern void pci_ecc_setup(ecc_t *ecc_p);
+extern ushort_t pci_ecc_get_synd(uint64_t afsr);
+
+extern uintptr_t pci_iommu_setup(iommu_t *iommu_p);
+extern void pci_iommu_teardown(iommu_t *iommu_p);
+extern void pci_iommu_config(iommu_t *iommu_p, uint64_t iommu_ctl,
+		uint64_t cfgpa);
+
+extern dvma_context_t pci_iommu_get_dvma_context(iommu_t *iommu_p,
+		dvma_addr_t dvma_pg_index);
+extern void pci_iommu_free_dvma_context(iommu_t *iommu_p, dvma_context_t ctx);
+
+extern void pci_pbm_setup(pbm_t *pbm_p);
+extern void pci_pbm_teardown(pbm_t *pbm_p);
+extern void pci_pbm_dma_sync(pbm_t *pbm_p, ib_ino_t ino);
+
+extern uint64_t pci_sc_configure(pci_t *pci_p);
+extern void pci_sc_setup(sc_t *sc_p);
+extern int pci_sc_ctx_inv(dev_info_t *dip, sc_t *sc_p, ddi_dma_impl_t *mp);
+
+extern uintptr_t pci_ib_setup(ib_t *ib_p);
+extern int pci_get_numproxy(dev_info_t *dip);
+
+extern int pci_ecc_add_intr(pci_t *pci_p, int inum, ecc_intr_info_t *eii_p);
+extern void pci_ecc_rem_intr(pci_t *pci_p, int inum, ecc_intr_info_t *eii_p);
+
+extern int pci_pbm_err_handler(dev_info_t *dip, ddi_fm_error_t *derr,
+		const void *impl_data, int caller);
+extern void pci_ecc_classify(uint64_t err, ecc_errstate_t *ecc_err_p);
+extern int pci_pbm_classify(pbm_errstate_t *pbm_err_p);
+extern void pci_format_addr(dev_info_t *dip, uint64_t *afar, uint64_t afsr);
+extern int pci_check_error(pci_t *pci_p);
+
+extern int pci_pbm_add_intr(pci_t *pci_p);
+extern void pci_pbm_rem_intr(pci_t *pci_p);
+
+extern void pci_pbm_suspend(pci_t *pci_p);
+extern void pci_pbm_resume(pci_t *pci_p);
+
+extern int pci_bus_quiesce(pci_t *pci_p, dev_info_t *dip, void *arg);
+extern int pci_bus_unquiesce(pci_t *pci_p, dev_info_t *dip, void *arg);
+
+extern void pci_vmem_free(iommu_t *iommu_p, ddi_dma_impl_t *mp,
+		void *dvma_addr, size_t npages);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_CHIP_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_counters.h b/usr/src/uts/sun4u/sys/pci/pci_counters.h
new file mode 100644
index 0000000000..11af0df5ab
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_counters.h
@@ -0,0 +1,79 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SYS_PCI_COUNTERS_H
+#define	_SYS_PCI_COUNTERS_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	NUM_OF_PICS	2
+
+/*
+ * used to build array of event-names and pcr-mask values
+ */
+typedef struct pci_kev_mask {
+	char *event_name;
+	uint64_t pcr_mask;
+} pci_kev_mask_t;
+
+typedef struct pci_ksinfo {
+	uint8_t	pic_no_evs;	/* number of events */
+	uint8_t	pic_shift[NUM_OF_PICS];
+	kstat_t	*pic_name_ksp[NUM_OF_PICS];
+} pci_ksinfo_t;
+
+typedef struct pci_cntr_addr {
+	uint64_t	*pcr_addr;
+	uint64_t	*pic_addr;
+} pci_cntr_addr_t;
+
+typedef struct pci_cntr_pa {
+	uint64_t	pcr_pa;
+	uint64_t	pic_pa;
+} pci_cntr_pa_t;
+
+extern void pci_create_name_kstat(char *, pci_ksinfo_t *, pci_kev_mask_t *);
+extern void pci_delete_name_kstat(pci_ksinfo_t *);
+
+extern kstat_t *pci_create_cntr_kstat(pci_t *, char *, int,
+	int (*update)(kstat_t *, int), void *);
+
+extern int pci_cntr_kstat_update(kstat_t *, int);
+extern int pci_cntr_kstat_pa_update(kstat_t *, int);
+
+extern void pci_kstat_create(pci_t *);
+extern void pci_kstat_destroy(pci_t *);
+extern void pci_rem_upstream_kstat(pci_t *);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_COUNTERS_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_debug.h b/usr/src/uts/sun4u/sys/pci/pci_debug.h
new file mode 100644
index 0000000000..5f34af26c8
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_debug.h
@@ -0,0 +1,126 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_DEBUG_H
+#define	_SYS_PCI_DEBUG_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef struct pci_debug_flag_to_string {
+	uint64_t flag;
+	char *string;
+} pci_debug_flag_to_string_t;
+
+#if defined(DEBUG)
+#define	DBG_ATTACH		0x1ull
+#define	DBG_DETACH		0x2ull
+
+#define	DBG_MAP			0x4ull
+#define	DBG_RSV1		0x10ull
+#define	DBG_A_INTX		0x20ull
+#define	DBG_R_INTX		0x40ull
+#define	DBG_INIT_CLD		0x80ull
+
+#define	DBG_CTLOPS		0x100ull
+#define	DBG_INTR		0x200ull
+#define	DBG_ERR_INTR		0x400ull
+#define	DBG_BUS_FAULT		0x800ull
+
+#define	DBG_DMA_ALLOCH		0x10000ull
+#define	DBG_DMA_FREEH		0x20000ull
+#define	DBG_DMA_BINDH		0x40000ull
+#define	DBG_DMA_UNBINDH		0x80000ull
+
+#define	DBG_DMA_MAP		0x100000ull
+#define	DBG_CHK_MOD		0x200000ull
+#define	DBG_BYPASS		0x400000ull
+#define	DBG_IOMMU		0x800000ull
+
+#define	DBG_DMA_WIN		0x1000000ull
+#define	DBG_MAP_WIN		0x2000000ull
+#define	DBG_UNMAP_WIN		0x4000000ull
+#define	DBG_DMA_CTL		0x8000000ull
+
+#define	DBG_DMA_SYNC		0x10000000ull
+#define	DBG_DMA_SYNC_PBM	0x20000000ull
+#define	DBG_FAST_DVMA		0x40000000ull
+
+#define	DBG_SC			(0x10ull << 32)
+#define	DBG_IB			(0x20ull << 32)
+#define	DBG_CB			(0x40ull << 32)
+#define	DBG_PBM			(0x80ull << 32)
+
+#define	DBG_CONT		(0x100ull << 32)
+
+#define	DBG_OPEN		(0x1000ull << 32)
+#define	DBG_CLOSE		(0x2000ull << 32)
+#define	DBG_IOCTL		(0x4000ull << 32)
+#define	DBG_PWR			(0x8000ull << 32)
+
+#define	DBG_RELOC		(0x10000ull << 32)
+#define	DBG_TOOLS		(0x40000ull << 32)
+#define	DBG_PHYS_ACC		(0x80000ull << 32)
+
+
+
+#define	DEBUG0(flag, dip, fmt)	\
+	pci_debug(flag, dip, fmt, 0, 0, 0, 0, 0);
+#define	DEBUG1(flag, dip, fmt, a1)	\
+	pci_debug(flag, dip, fmt, (uintptr_t)(a1), 0, 0, 0, 0);
+#define	DEBUG2(flag, dip, fmt, a1, a2)	\
+	pci_debug(flag, dip, fmt, (uintptr_t)(a1), (uintptr_t)(a2), 0, 0, 0);
+#define	DEBUG3(flag, dip, fmt, a1, a2, a3)	\
+	pci_debug(flag, dip, fmt, (uintptr_t)(a1),	\
+		(uintptr_t)(a2), (uintptr_t)(a3), 0, 0);
+#define	DEBUG4(flag, dip, fmt, a1, a2, a3, a4)	\
+	pci_debug(flag, dip, fmt, (uintptr_t)(a1),	\
+		(uintptr_t)(a2), (uintptr_t)(a3), \
+		(uintptr_t)(a4), 0);
+#define	DEBUG5(flag, dip, fmt, a1, a2, a3, a4, a5)	\
+	pci_debug(flag, dip, fmt, (uintptr_t)(a1),	\
+		(uintptr_t)(a2), (uintptr_t)(a3), \
+		(uintptr_t)(a4), (uintptr_t)(a5));
+
+extern void pci_debug(uint64_t, dev_info_t *, char *,
+			uintptr_t, uintptr_t, uintptr_t, uintptr_t, uintptr_t);
+#else
+#define	DEBUG0(flag, dip, fmt)
+#define	DEBUG1(flag, dip, fmt, a1)
+#define	DEBUG2(flag, dip, fmt, a1, a2)
+#define	DEBUG3(flag, dip, fmt, a1, a2, a3)
+#define	DEBUG4(flag, dip, fmt, a1, a2, a3, a4)
+#define	DEBUG5(flag, dip, fmt, a1, a2, a3, a4, a5)
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_DEBUG_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_dma.h b/usr/src/uts/sun4u/sys/pci/pci_dma.h
new file mode 100644
index 0000000000..0917dd86fb
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_dma.h
@@ -0,0 +1,296 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_DMA_H
+#define	_SYS_PCI_DMA_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef	pfn_t iopfn_t;
+#define	MAKE_DMA_COOKIE(cp, address, size)	\
+	{					\
+		(cp)->dmac_notused = 0;		\
+		(cp)->dmac_type = 0;		\
+		(cp)->dmac_laddress = (address);	\
+		(cp)->dmac_size = (size);	\
+	}
+
+#define	HAS_REDZONE(mp)	(((mp)->dmai_rflags & DDI_DMA_REDZONE) ? 1 : 0)
+
+typedef struct pci_dma_hdl {
+	ddi_dma_impl_t	pdh_ddi_hdl;
+	ddi_dma_attr_t	pdh_attr_dev;
+	uint64_t	pdh_sync_buf_pa;
+} pci_dma_hdl_t;
+
+struct pci_dma_impl { /* forthdebug only, keep in sync with ddi_dma_impl_t */
+	ulong_t		dmai_mapping;
+	uint_t		dmai_size;
+	off_t		dmai_offset;
+	uint_t		dmai_minxfer;
+	uint_t		dmai_burstsizes;
+	uint_t		dmai_ndvmapages;
+	uint_t		dmai_roffset;
+	uint_t		dmai_rflags;
+	uint_t		dmai_flags;
+	uint_t		dmai_nwin;
+	uint_t		dmai_winsize;
+	caddr_t		dmai_tte_fdvma;
+	void		*dmai_pfnlst;
+	uint_t		*dmai_pfn0;
+	void		*dmai_winlst;
+	dev_info_t	*dmai_rdip;
+	ddi_dma_obj_t	dmai_object;
+	ddi_dma_attr_t	dmai_attr_aug;
+	ddi_dma_cookie_t *dmai_cookie;
+
+	int		(*dmai_fault_check)(struct ddi_dma_impl *handle);
+	void		(*dmai_fault_notify)(struct ddi_dma_impl *handle);
+	int		dmai_fault;
+
+	ddi_dma_attr_t	pdh_attr_dev;
+	uint64_t	pdh_sync_buf_pa;
+};
+
+/*
+ * flags for overloading dmai_inuse field of the dma request
+ * structure:
+ */
+#define	dmai_flags		dmai_inuse
+#define	dmai_tte		dmai_nexus_private
+#define	dmai_fdvma		dmai_nexus_private
+#define	dmai_pfnlst		dmai_iopte
+#define	dmai_winlst		dmai_minfo
+#define	dmai_pfn0		dmai_sbi
+#define	dmai_roffset		dmai_pool
+
+#define	MP_PFN0(mp)		((iopfn_t)(mp)->dmai_pfn0)
+#define	WINLST(mp)		((pci_dma_win_t *)(mp)->dmai_winlst)
+#define	DEV_ATTR(mp)		(&((pci_dma_hdl_t *)(mp))->pdh_attr_dev)
+#define	SYNC_BUF_PA(mp)		(((pci_dma_hdl_t *)(mp))->pdh_sync_buf_pa)
+#define	SET_DMAATTR(p, lo, hi, nocross, cntmax)	\
+	(p)->dma_attr_addr_lo	= (lo); \
+	(p)->dma_attr_addr_hi	= (hi); \
+	(p)->dma_attr_seg	= (nocross); \
+	(p)->dma_attr_count_max	= (cntmax);
+
+#define	SET_DMAALIGN(p, align) \
+	(p)->dma_attr_align = (align);
+
+#define	DMAI_FLAGS_INUSE	0x1
+#define	DMAI_FLAGS_BYPASSREQ	0x2
+#define	DMAI_FLAGS_PEER_ONLY	0x4
+#define	DMAI_FLAGS_NOCTX	0x8
+#define	DMAI_FLAGS_DVMA		0x10
+#define	DMAI_FLAGS_BYPASS	0x20
+#define	DMAI_FLAGS_PEER_TO_PEER	0x40
+#define	DMAI_FLAGS_DMA		(DMAI_FLAGS_BYPASS | DMAI_FLAGS_PEER_TO_PEER)
+#define	DMAI_FLAGS_DMA_TYPE	(DMAI_FLAGS_DMA | DMAI_FLAGS_DVMA)
+#define	DMAI_FLAGS_CONTEXT	0x100
+#define	DMAI_FLAGS_FASTTRACK	0x200
+#define	DMAI_FLAGS_VMEMCACHE	0x400
+#define	DMAI_FLAGS_PGPFN	0x800
+#define	DMAI_FLAGS_NOSYSLIMIT	0x1000
+#define	DMAI_FLAGS_NOFASTLIMIT	0x2000
+#define	DMAI_FLAGS_NOSYNC	0x4000
+#define	DMAI_FLAGS_RELOC	0x8000
+#define	DMAI_FLAGS_MAPPED	0x10000
+#define	DMAI_FLAGS_PRESERVE	(DMAI_FLAGS_PEER_ONLY | DMAI_FLAGS_BYPASSREQ | \
+	DMAI_FLAGS_NOSYSLIMIT | DMAI_FLAGS_NOFASTLIMIT | DMAI_FLAGS_NOCTX)
+
+#define	HAS_NOFASTLIMIT(mp)	((mp)->dmai_flags & DMAI_FLAGS_NOFASTLIMIT)
+#define	HAS_NOSYSLIMIT(mp)	((mp)->dmai_flags & DMAI_FLAGS_NOSYSLIMIT)
+#define	PCI_DMA_ISPEERONLY(mp)	((mp)->dmai_flags & DMAI_FLAGS_PEER_ONLY)
+#define	PCI_DMA_ISPGPFN(mp)	((mp)->dmai_flags & DMAI_FLAGS_PGPFN)
+#define	PCI_DMA_TYPE(mp)	((mp)->dmai_flags & DMAI_FLAGS_DMA_TYPE)
+#define	PCI_DMA_ISDVMA(mp)	(PCI_DMA_TYPE(mp) == DMAI_FLAGS_DVMA)
+#define	PCI_DMA_ISBYPASS(mp)	(PCI_DMA_TYPE(mp) == DMAI_FLAGS_BYPASS)
+#define	PCI_DMA_ISPTP(mp)	(PCI_DMA_TYPE(mp) == DMAI_FLAGS_PEER_TO_PEER)
+#define	PCI_DMA_CANFAST(mp)	(((mp)->dmai_ndvmapages + HAS_REDZONE(mp) \
+		<= pci_dvma_page_cache_clustsz) && HAS_NOFASTLIMIT(mp))
+#define	PCI_DMA_WINNPGS(mp)	IOMMU_BTOP((mp)->dmai_winsize)
+#define	PCI_DMA_CANCACHE(mp)	(!HAS_REDZONE(mp) && \
+		(PCI_DMA_WINNPGS(mp) == 1) && HAS_NOSYSLIMIT(mp))
+#define	PCI_DMA_CANRELOC(mp)	((mp)->dmai_flags & DMAI_FLAGS_RELOC)
+#define	PCI_DMA_ISMAPPED(mp)	((mp)->dmai_flags & DMAI_FLAGS_MAPPED)
+
+#define	PCI_SYNC_FLAG_SZSHIFT	6
+#define	PCI_SYNC_FLAG_SIZE	(1 << PCI_SYNC_FLAG_SZSHIFT)
+#define	PCI_SYNC_FLAG_FAILED	1
+#define	PCI_SYNC_FLAG_LOCKED	2
+
+#define	PCI_DMA_SYNC_DDI_FLAGS	((1 << 16) - 1)	/* Look for only DDI flags  */
+#define	PCI_DMA_SYNC_EXT	(1 << 30)	/* enable/disable extension */
+#define	PCI_DMA_SYNC_UNBIND	(1 << 28)	/* internal: part of unbind */
+#define	PCI_DMA_SYNC_BAR	(1 << 26)	/* wait for all posted sync  */
+#define	PCI_DMA_SYNC_POST	(1 << 25)	/* post request and return   */
+#define	PCI_DMA_SYNC_PRIVATE	(1 << 24)	/* alloc private sync buffer */
+#define	PCI_DMA_SYNC_DURING	(1 << 22)	/* sync in-progress dma */
+#define	PCI_DMA_SYNC_BEFORE	(1 << 21)	/* before read or write */
+#define	PCI_DMA_SYNC_AFTER	(1 << 20)	/* after read or write  */
+#define	PCI_DMA_SYNC_WRITE	(1 << 17)	/* data from device to mem */
+#define	PCI_DMA_SYNC_READ	(1 << 16)	/* data from memory to dev */
+
+#define	PCI_FLOW_ID_TO_PA(flow_p, flow_id) \
+	((flow_p)->flow_buf_pa + ((flow_id) << PCI_SYNC_FLAG_SZSHIFT))
+
+#define	DEV_NOFASTLIMIT(lo, hi, fastlo, fasthi, align_pg) \
+	(((lo) <= (fastlo)) && ((hi) >= (fasthi)) && \
+	((align_pg) <= pci_dvma_page_cache_clustsz))
+
+#define	DEV_NOSYSLIMIT(lo, hi, syslo, syshi, align_pg) \
+	(((lo) <= (syslo)) && ((hi) >= (syshi)) && (align_pg == 1))
+
+#define	PCI_DMA_NOCTX(rdip) (!pci_use_contexts || (pci_ctx_no_active_flush && \
+	ddi_prop_exists(DDI_DEV_T_ANY, rdip, \
+		DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, "active-dma-flush")))
+#define	PCI_DMA_USECTX(mp)	(!(mp->dmai_flags & DMAI_FLAGS_NOCTX))
+
+#define	PCI_DMA_BYPASS_PREFIX(mp, pfn) \
+	(PCI_DMA_ISBYPASS(mp) ? COMMON_IOMMU_BYPASS_BASE | \
+	(pf_is_memory(pfn) ? 0 : COMMON_IOMMU_BYPASS_NONCACHE) : 0)
+#define	PCI_DMA_BADPTP(pfn, attrp) \
+	((IOMMU_PTOB(pfn) < attrp->dma_attr_addr_lo) || \
+	(IOMMU_PTOB(pfn) > attrp->dma_attr_addr_hi))
+#define	PCI_DMA_CURWIN(mp) \
+	(((mp)->dmai_offset + (mp)->dmai_roffset) / (mp)->dmai_winsize)
+
+#ifdef PCI_DMA_PROF
+
+/* collect fast track failure statistics */
+#define	PCI_DVMA_FASTTRAK_PROF(mp) { \
+if ((mp->dmai_ndvmapages + HAS_REDZONE(mp)) > pci_dvma_page_cache_clustsz) \
+	pci_dvmaft_npages++; \
+else if (!HAS_NOFASTLIMIT(mp)) \
+	pci_dvmaft_limit++; \
+}
+
+#else /* !PCI_DMA_PROF */
+
+#define	PCI_DVMA_FASTTRAK_PROF(mp)
+
+#endif	/* PCI_DMA_PROF */
+
+typedef struct pci_dma_win {
+	struct pci_dma_win *win_next;
+	uint32_t win_ncookies;
+	uint32_t win_curseg;
+	uint64_t win_size;
+	uint64_t win_offset;
+	/* cookie table: sizeof (ddi_dma_cookie_t) * win_ncookies */
+} pci_dma_win_t;
+
+/* dvma debug records */
+struct dvma_rec {
+	char *dvma_addr;
+	uint_t len;
+	ddi_dma_impl_t *mp;
+	struct dvma_rec *next;
+};
+
+typedef struct pbm pbm_t;
+extern int pci_dma_sync(dev_info_t *dip, dev_info_t *rdip,
+	ddi_dma_handle_t handle, off_t off, size_t len, uint32_t sync_flags);
+
+extern int pci_dma_win(dev_info_t *dip, dev_info_t *rdip,
+	ddi_dma_handle_t handle, uint_t win, off_t *offp,
+	size_t *lenp, ddi_dma_cookie_t *cookiep, uint_t *ccountp);
+
+extern ddi_dma_impl_t *pci_dma_allocmp(dev_info_t *dip, dev_info_t *rdip,
+	int (*waitfp)(caddr_t), caddr_t arg);
+extern void pci_dma_freemp(ddi_dma_impl_t *mp);
+extern void pci_dma_freepfn(ddi_dma_impl_t *mp);
+extern ddi_dma_impl_t *pci_dma_lmts2hdl(dev_info_t *dip, dev_info_t *rdip,
+	iommu_t *iommu_p, ddi_dma_req_t *dmareq);
+extern int pci_dma_attr2hdl(pci_t *pci_p, ddi_dma_impl_t *mp);
+extern uint32_t pci_dma_consist_check(uint32_t req_flags, pbm_t *pbm_p);
+extern int pci_dma_type(pci_t *pci_p, ddi_dma_req_t *req, ddi_dma_impl_t *mp);
+extern int pci_dma_pfn(pci_t *pci_p, ddi_dma_req_t *req, ddi_dma_impl_t *mp);
+extern int pci_dvma_win(pci_t *pci_p, ddi_dma_req_t *r, ddi_dma_impl_t *mp);
+extern void pci_dma_freewin(ddi_dma_impl_t *mp);
+extern int pci_dvma_map_fast(iommu_t *iommu_p, ddi_dma_impl_t *mp);
+extern int pci_dvma_map(ddi_dma_impl_t *mp, ddi_dma_req_t *dmareq,
+	iommu_t *iommu_p);
+extern void pci_dvma_unmap(iommu_t *iommu_p, ddi_dma_impl_t *mp);
+extern void pci_dma_sync_unmap(dev_info_t *dip, dev_info_t *rdip,
+	ddi_dma_impl_t *mp);
+extern int pci_dma_physwin(pci_t *pci_p, ddi_dma_req_t *dmareq,
+	ddi_dma_impl_t *mp);
+extern int pci_dvma_ctl(dev_info_t *dip, dev_info_t *rdip,
+	ddi_dma_impl_t *mp, enum ddi_dma_ctlops cmd, off_t *offp,
+	size_t *lenp, caddr_t *objp, uint_t cache_flags);
+extern int pci_dma_ctl(dev_info_t *dip, dev_info_t *rdip,
+	ddi_dma_impl_t *mp, enum ddi_dma_ctlops cmd, off_t *offp,
+	size_t *lenp, caddr_t *objp, uint_t cache_flags);
+extern void pci_vmem_do_free(iommu_t *iommu_p, void *base_addr, size_t npages,
+	int vmemcache);
+
+#define	PCI_GET_MP_NCOOKIES(mp)		((mp)->dmai_ncookies)
+#define	PCI_SET_MP_NCOOKIES(mp, nc)	((mp)->dmai_ncookies = (nc))
+#define	PCI_GET_MP_PFN1_ADDR(mp)	(((iopfn_t *)(mp)->dmai_pfnlst) + 1)
+
+#define	PCI_GET_MP_TTE(tte) \
+	(((uint64_t)(tte) >> 5) << (32 + 5) | ((uint32_t)(tte)) & 0x12)
+#define	PCI_SAVE_MP_TTE(mp, tte)	\
+	(mp)->dmai_tte = (caddr_t)(HI32(tte) | ((tte) & 0x12))
+
+#define	PCI_GET_MP_PFN1(mp, page_no) (((iopfn_t *)(mp)->dmai_pfnlst)[page_no])
+#define	PCI_GET_MP_PFN(mp, page_no)	((mp)->dmai_ndvmapages == 1 ? \
+	(iopfn_t)(mp)->dmai_pfnlst : PCI_GET_MP_PFN1(mp, page_no))
+
+#define	PCI_SET_MP_PFN(mp, page_no, pfn) { \
+	if ((mp)->dmai_ndvmapages == 1) { \
+		ASSERT(!((page_no) || (mp)->dmai_pfnlst)); \
+		(mp)->dmai_pfnlst = (void *)(pfn); \
+	} else \
+		((iopfn_t *)(mp)->dmai_pfnlst)[page_no] = (iopfn_t)(pfn); \
+}
+#define	PCI_SET_MP_PFN1(mp, page_no, pfn) { \
+	((iopfn_t *)(mp)->dmai_pfnlst)[page_no] = (pfn); \
+}
+
+#define	GET_TTE_TEMPLATE(mp) MAKE_TTE_TEMPLATE(PCI_GET_MP_PFN((mp), 0), (mp))
+
+extern int pci_dma_freehdl(dev_info_t *dip, dev_info_t *rdip,
+	ddi_dma_handle_t handle);
+
+int pci_dma_handle_clean(dev_info_t *rdip, ddi_dma_handle_t handle);
+
+#if defined(DEBUG)
+extern void dump_dma_handle(uint64_t flag, dev_info_t *dip, ddi_dma_impl_t *hp);
+#else
+#define	dump_dma_handle(flag, dip, hp)
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_DMA_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_ecc.h b/usr/src/uts/sun4u/sys/pci/pci_ecc.h
new file mode 100644
index 0000000000..66ffb8b165
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_ecc.h
@@ -0,0 +1,89 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_ECC_H
+#define	_SYS_PCI_ECC_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/errorq.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef struct ecc_intr_info {
+	struct ecc *ecc_p;
+
+	int ecc_type;			/* CBNINTR_UE or CBNINTR_CE */
+
+	/*
+	 * ECC status registers.
+	 */
+	uint64_t ecc_afsr_pa;
+	uint64_t ecc_afar_pa;
+
+	/*
+	 * Implementation-specific masks & shift values.
+	 */
+	uint64_t ecc_errpndg_mask;	/* 0 if not applicable. */
+	uint64_t ecc_offset_mask;
+	uint_t ecc_offset_shift;
+	uint_t ecc_size_log2;
+} ecc_intr_info_t;
+
+typedef struct ecc {
+	pci_common_t *ecc_pci_cmn_p;
+
+	/*
+	 * ECC control and status registers:
+	 */
+	volatile uint64_t ecc_csr_pa;
+
+	/*
+	 * Information specific to error type.
+	 */
+	struct ecc_intr_info ecc_ue;
+	struct ecc_intr_info ecc_ce;
+	timeout_id_t ecc_to_id;
+} ecc_t;
+
+extern void ecc_create(pci_t *pci_p);
+extern int ecc_register_intr(pci_t *pci_p);
+extern void ecc_destroy(pci_t *pci_p);
+extern void ecc_configure(pci_t *pci_p);
+extern void ecc_enable_intr(pci_t *pci_p);
+extern void ecc_disable_wait(ecc_t *ecc_p);
+extern uint_t ecc_disable_nowait(ecc_t *ecc_p);
+extern uint_t ecc_intr(caddr_t a);
+extern int ecc_err_handler(ecc_errstate_t *ecc_err_p);
+extern void ecc_err_drain(void *, ecc_errstate_t *, errorq_elem_t *);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_ECC_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_fdvma.h b/usr/src/uts/sun4u/sys/pci/pci_fdvma.h
new file mode 100644
index 0000000000..19bc607392
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_fdvma.h
@@ -0,0 +1,46 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_FDVMA_H
+#define	_SYS_PCI_FDVMA_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef struct fast_dvma fdvma_t;
+
+extern int pci_fdvma_reserve(dev_info_t *dip, dev_info_t *rdip, pci_t *pci_p,
+	struct ddi_dma_req *dmareq, ddi_dma_handle_t *handlep);
+extern int pci_fdvma_release(dev_info_t *dip, pci_t *pci_p, ddi_dma_impl_t *mp);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_FDVMA_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_fm.h b/usr/src/uts/sun4u/sys/pci/pci_fm.h
new file mode 100644
index 0000000000..f365240a45
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_fm.h
@@ -0,0 +1,233 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_PCI_FM_H
+#define	_PCI_FM_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/ddifm.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifdef _KERNEL
+
+#define	PBM_PRIMARY		1
+#define	PBM_SECONDARY		0
+#define	PBM_NONFATAL		0
+#define	PBM_FATAL		1
+#define	CB_NONFATAL		0
+#define	CB_FATAL		1
+#define	FM_LOG_PCI		0
+#define	FM_LOG_PBM		1
+#define	PCI_SIDEA		0
+#define	PCI_SIDEB		1
+#define	ECC_MAX_ERRS		6
+#define	TARGET_MAX_ERRS		6
+
+/*
+ * Since pci_pbm_err_handler() is called by various interrupt/trap/callback
+ * handlers, it is necessary for it to know where it is being called from.
+ * Below are the flags passed to pci_pbm_err_handler() to give it knowledge
+ * of it's caller.
+ */
+#define	PCI_TRAP_CALL		0x0
+#define	PCI_CB_CALL		0x1
+#define	PCI_INTR_CALL		0x2
+#define	PCI_BUS_EXIT_CALL	0x3
+#define	PCI_ECC_CALL		0x4
+
+#define	PCIX_ERROR_SUBCLASS	"pcix"
+#define	PCIX_SECONDARY		"s-"
+#define	PCIX_STAT		"pcix-stat"
+#define	PCIX_PFAR		"pcix-pfar"
+
+extern errorq_t *pci_ecc_queue;		/* per-system ecc handling queue */
+extern errorq_t *pci_target_queue;	/* per-system target handling queue */
+
+/*
+ * region where schizo pio ecc error was detected
+ */
+typedef enum {
+	SCH_REG_UPA,
+	SCH_REG_PCIA_REG,
+	SCH_REG_PCIA_MEM,
+	SCH_REG_PCIA_CFGIO,
+	SCH_REG_PCIB_REG,
+	SCH_REG_PCIB_MEM,
+	SCH_REG_PCIB_CFGIO,
+	SCH_REG_SAFARI_REGS
+} ecc_region_t;
+
+typedef struct pbm_fm_err {
+	char *pbm_err_class;
+	uint64_t pbm_reg_bit;
+	int pbm_pri;
+	int pbm_flag;
+	char *pbm_terr_class;
+} pbm_fm_err_t;
+
+typedef struct pci_target_err {
+	uint64_t tgt_err_addr;
+	uint64_t tgt_err_ena;
+	uint64_t tgt_pci_addr;
+	uint32_t tgt_pci_space;
+	dev_info_t *tgt_dip;
+	char *tgt_err_class;
+	char *tgt_bridge_type;
+} pci_target_err_t;
+
+typedef struct ecc_format {
+	ecc_region_t ecc_region;
+	uint64_t ecc_space;
+	int ecc_side;
+} ecc_format_t;
+
+typedef struct cb_fm_err {
+	char *cb_err_class;
+	uint64_t cb_reg_bit;
+	int cb_fatal;
+} cb_fm_err_t;
+
+typedef struct ecc_fm_err {
+	char *ecc_err_class;
+	uint64_t ecc_reg_bit;
+	int ecc_type;
+	int ecc_pri;
+	uint64_t ecc_region_bits;
+	int ecc_region;
+	int ecc_flag;
+} ecc_fm_err_t;
+
+/*
+ * iommu errstate used to store iommu specific registers
+ */
+struct iommu_errstate {
+	uint64_t iommu_stat;
+	uint64_t iommu_tfar;
+};
+
+struct pci_errstate {
+	char *pci_err_class;
+	uint16_t pci_cfg_stat;
+	uint16_t pci_cfg_comm;
+	uint64_t pci_pa;
+};
+
+/*
+ * pbm errstate use to encompass the state for all errors
+ * detected by the pci block
+ */
+struct pbm_errstate {
+	char *pbm_err_class;
+	int pbm_pri;
+	int pbm_log;
+	uint32_t pbm_err;
+	uint32_t pbm_multi;
+	char *pbm_bridge_type;
+	uint64_t pbm_ctl_stat;
+	uint64_t pbm_afsr;
+	uint64_t pbm_afar;
+	uint64_t pbm_va_log;
+	uint64_t pbm_err_sl;
+	iommu_errstate_t pbm_iommu;
+	uint64_t pbm_pcix_stat;
+	uint32_t pbm_pcix_pfar;
+	pci_errstate_t pbm_pci;
+	char *pbm_terr_class;
+};
+
+/*
+ * ecc errstate used to store all state captured,
+ * upon detection of an ecc error.
+ */
+struct ecc_errstate {
+	char *ecc_bridge_type;
+	ecc_t *ecc_p;
+	uint64_t ecc_afsr;
+	uint64_t ecc_afar;
+	uint64_t ecc_offset;
+	uint64_t ecc_dev_id;
+	uint64_t ecc_dw_offset;
+	struct async_flt ecc_aflt;
+	ecc_intr_info_t ecc_ii_p;
+	uint64_t ecc_ctrl;
+	int ecc_pri;
+	ecc_region_t ecc_region;
+	char ecc_unum[UNUM_NAMLEN];
+	uint64_t ecc_ena;
+	uint64_t ecc_err_addr;
+	char *ecc_err_type;
+	int ecc_pg_ret;
+	nvlist_t *ecc_fmri;
+	int ecc_caller;
+};
+
+/*
+ * control block error state
+ */
+struct cb_errstate {
+	char *cb_err_class;
+	char *cb_bridge_type;
+	uint64_t cb_csr;
+	uint64_t cb_err;
+	uint64_t cb_intr;
+	uint64_t cb_elog;
+	uint64_t cb_ecc;
+	uint64_t cb_pcr;
+	uint64_t cb_ue_afsr;
+	uint64_t cb_ue_afar;
+	uint64_t cb_ce_afsr;
+	uint64_t cb_ce_afar;
+	uint64_t cb_first_elog;
+	uint64_t cb_first_eaddr;
+	uint64_t cb_leaf_status;
+	pbm_errstate_t cb_pbm[2];
+};
+
+extern int pci_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap,
+		ddi_iblock_cookie_t *ibc);
+extern void pci_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle);
+extern void pci_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle);
+extern void pbm_ereport_post(dev_info_t *dip, uint64_t ena,
+		pbm_errstate_t *pbm_err);
+extern void pci_fm_acc_setup(ddi_map_req_t *mp, dev_info_t *rdip);
+extern int pci_handle_lookup(dev_info_t *dip, int type, uint64_t fme_ena,
+		void *afar);
+extern void pci_fmri_create(dev_info_t *dip, pci_common_t *cmn_p);
+extern void pci_fm_create(pci_t *pci_p);
+extern void pci_fm_destroy(pci_t *pci_p);
+extern int pci_err_callback(dev_info_t *dip, ddi_fm_error_t *derr,
+		const void *impl_data);
+#endif /* _KERNEL */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _PCI_FM_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_ib.h b/usr/src/uts/sun4u/sys/pci/pci_ib.h
new file mode 100644
index 0000000000..707e1354fb
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_ib.h
@@ -0,0 +1,222 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_IB_H
+#define	_SYS_PCI_IB_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/ddi_subrdefs.h>
+
+typedef uint8_t ib_ino_t;
+typedef uint16_t ib_mondo_t;
+typedef struct ib_ino_info ib_ino_info_t;
+typedef uint8_t device_num_t;
+typedef uint8_t interrupt_t;
+
+/*
+ * interrupt block soft state structure:
+ *
+ * Each pci node may share an interrupt block structure with its peer
+ * node or have its own private interrupt block structure.
+ */
+typedef struct ib ib_t;
+struct ib {
+
+	pci_t *ib_pci_p;	/* link back to pci soft state */
+	pci_ign_t ib_ign;	/* interrupt group # */
+
+	/*
+	 * PCI slot and onboard I/O interrupt mapping register blocks addresses:
+	 */
+	uintptr_t ib_slot_intr_map_regs;
+#define	ib_intr_map_regs	ib_slot_intr_map_regs
+	uintptr_t ib_obio_intr_map_regs;
+
+	/*
+	 * PCI slot and onboard I/O clear interrupt register block addresses:
+	 */
+	uintptr_t ib_slot_clear_intr_regs;
+	uintptr_t ib_obio_clear_intr_regs;
+
+	/*
+	 * UPA expansion slot interrupt mapping register addresses:
+	 */
+	volatile uint64_t *ib_upa_imr[2];
+	uint64_t ib_upa_imr_state[2];
+
+	/*
+	 * Interrupt retry register address:
+	 */
+	volatile uint64_t *ib_intr_retry_timer_reg;
+
+	/*
+	 * PCI slot and onboard I/O interrupt state diag register addresses:
+	 */
+	volatile uint64_t *ib_slot_intr_state_diag_reg;
+	volatile uint64_t *ib_obio_intr_state_diag_reg;
+
+	uint_t ib_max_ino;			/* largest supported INO */
+	ib_ino_info_t *ib_ino_lst;		/* ino link list */
+	kmutex_t ib_ino_lst_mutex;		/* mutex for ino link list */
+	kmutex_t ib_intr_lock;			/* lock for internal intr  */
+	uint16_t ib_map_reg_counters[8];	/* counters for shared map */
+						/* registers */
+};
+
+#define	PCI_PULSE_INO	0x80000000
+#define	PSYCHO_MAX_INO	0x3f
+#define	SCHIZO_MAX_INO	0x37
+#define	PCI_INO_BITS	6			/* INO#s are 6 bits long */
+#define	PCI_IGN_BITS	5			/* IGN#s are 5 bits long */
+
+/*
+ * The following structure represents an interrupt entry for an INO.
+ */
+typedef struct ih {
+	dev_info_t *ih_dip;		/* devinfo structure */
+	uint32_t ih_inum;		/* interrupt number for this device */
+	uint_t	ih_intr_state;		/* Only used for fixed interrupts */
+	uint_t (*ih_handler)();		/* interrupt handler */
+	caddr_t ih_handler_arg1;	/* interrupt handler argument #1 */
+	caddr_t ih_handler_arg2;	/* interrupt handler argument #2 */
+	ddi_acc_handle_t ih_config_handle; /* config space reg map handle */
+	struct ih *ih_next;		/* next entry in list */
+	uint64_t ih_ticks;		/* ticks spent in this handler */
+	uint64_t ih_nsec;		/* nsec spent in this handler */
+	kstat_t *ih_ksp;
+	struct ib_ino_info *ih_ino_p;	/* only for use by kstat */
+} ih_t;
+
+/* Only used for fixed or legacy interrupts */
+#define	PCI_INTR_STATE_DISABLE	0	/* disabled */
+#define	PCI_INTR_STATE_ENABLE	1	/* enabled */
+
+/*
+ * ino structure : one per each psycho slot ino with interrupt registered
+ */
+struct ib_ino_info {
+	ib_ino_t ino_ino;		/* INO number - 8 bit */
+	uint8_t ino_slot_no;		/* PCI slot number 0-8 */
+	uint16_t ino_ih_size;		/* size of the pci intrspec list */
+	struct ib_ino_info *ino_next;
+	ih_t *ino_ih_head;		/* intr spec (part of ppd) list head */
+	ih_t *ino_ih_tail;		/* intr spec (part of ppd) list tail */
+	ih_t *ino_ih_start;		/* starting point in intr spec list  */
+	ib_t *ino_ib_p;			/* link back to interrupt block state */
+	volatile uint64_t *ino_clr_reg;	/* ino interrupt clear register */
+	volatile uint64_t *ino_map_reg;	/* ino interrupt mapping register */
+	uint64_t ino_map_reg_save;	/* = *ino_map_reg if saved */
+	uint32_t ino_pil;		/* PIL for this ino */
+	volatile uint_t ino_unclaimed;	/* number of unclaimed interrupts */
+	clock_t ino_spurintr_begin;	/* begin time of spurious intr series */
+	int ino_established;		/* ino has been associated with a cpu */
+	uint32_t ino_cpuid;		/* cpu that ino is targeting */
+	int32_t ino_intr_weight;	/* intr weight of devices sharing ino */
+};
+
+#define	IB_INTR_WAIT	1		/* wait for interrupt completion */
+#define	IB_INTR_NOWAIT	0		/* already handling intr, no wait */
+
+#define	IB2CB(ib_p)	((ib_p)->ib_pci_p->pci_cb_p)
+
+#define	IB_MONDO_TO_INO(mondo)		((ib_ino_t)((mondo) & 0x3f))
+#define	IB_INO_INTR_ON(reg_p)		*(reg_p) |= COMMON_INTR_MAP_REG_VALID
+#define	IB_INO_INTR_OFF(reg_p)		*(reg_p) &= ~COMMON_INTR_MAP_REG_VALID
+#define	IB_INO_INTR_RESET(reg_p)	*(reg_p) = 0ull
+#define	IB_INO_INTR_STATE_REG(ib_p, ino) ((ino) & 0x20 ? \
+	ib_p->ib_obio_intr_state_diag_reg : ib_p->ib_slot_intr_state_diag_reg)
+#define	IB_INO_INTR_PENDING(reg_p, ino) \
+	(((*(reg_p) >> (((ino) & 0x1f) << 1)) & COMMON_CLEAR_INTR_REG_MASK) == \
+	COMMON_CLEAR_INTR_REG_PENDING)
+#define	IB_INO_INTR_CLEAR(reg_p)	*(reg_p) = COMMON_CLEAR_INTR_REG_IDLE
+#define	IB_INO_INTR_TRIG(reg_p)	*(reg_p) = COMMON_CLEAR_INTR_REG_RECEIVED
+#define	IB_INO_INTR_PEND(reg_p)		*(reg_p) = COMMON_CLEAR_INTR_REG_PENDING
+#define	IB_INO_INTR_ISON(imr)		((imr) >> 31)
+#define	IB_IMR2MONDO(imr) \
+	((imr) & (COMMON_INTR_MAP_REG_IGN | COMMON_INTR_MAP_REG_INO))
+
+#define	IB_IS_OBIO_INO(ino) (ino & 0x20)
+
+#ifdef _STARFIRE
+/*
+ * returns a uniq ino per interrupt mapping register
+ * For on board devices, inos are not shared. But for plugin devices,
+ * return the 1st ino of the 4 that are sharing the same mapping register.
+ */
+#define	IB_GET_MAPREG_INO(ino)	\
+	((volatile uint64_t *)((ino & 0x20) ? ino : ((ino >> 2) << 2)))
+#endif /* _STARFIRE */
+
+#define	IB_IGN_TO_MONDO(ign, ino)	(((ign) << PCI_INO_BITS) | (ino))
+#define	IB_INO_TO_MONDO(ib_p, ino)	IB_IGN_TO_MONDO((ib_p)->ib_ign, ino)
+
+extern void ib_create(pci_t *pci_p);
+extern void ib_destroy(pci_t *pci_p);
+extern void ib_configure(ib_t *ib_p);
+extern uint64_t ib_get_map_reg(ib_mondo_t mondo, uint32_t cpu_id);
+extern void ib_intr_enable(pci_t *pci_p, ib_ino_t ino);
+extern void ib_intr_disable(ib_t *ib_p, ib_ino_t ino, int wait);
+extern void ib_nintr_clear(ib_t *ib_p, ib_ino_t ino);
+extern void ib_suspend(ib_t *ib_p);
+extern void ib_resume(ib_t *ib_p);
+
+extern ib_ino_info_t *ib_locate_ino(ib_t *ib_p, ib_ino_t ino_num);
+extern ib_ino_info_t *ib_new_ino(ib_t *ib_p, ib_ino_t ino_num, ih_t *ih_p);
+extern void ib_delete_ino(ib_t *ib_p, ib_ino_info_t *ino_p);
+extern void ib_free_ino_all(ib_t *ib_p);
+extern int ib_update_intr_state(pci_t *pci_p, dev_info_t *rdip,
+    ddi_intr_handle_impl_t *hdlp, uint_t new_intr_state);
+extern void ib_ino_add_intr(pci_t *pci_p, ib_ino_info_t *ino_p, ih_t *ih_p);
+extern void ib_ino_rem_intr(pci_t *pci_p, ib_ino_info_t *ino_p, ih_t *ih_p);
+extern ih_t *ib_ino_locate_intr(ib_ino_info_t *ino_p, dev_info_t *dip,
+    uint32_t inum);
+extern ih_t *ib_alloc_ih(dev_info_t *dip, uint32_t inum,
+    uint_t (*int_handler)(caddr_t int_handler_arg1, caddr_t int_handler_arg2),
+    caddr_t int_handler_arg1, caddr_t int_handler_arg2);
+extern void ib_free_ih(ih_t *ih_p);
+extern void ib_ino_map_reg_share(ib_t *ib_p, ib_ino_t ino,
+	ib_ino_info_t *ino_p);
+extern int ib_ino_map_reg_unshare(ib_t *ib_p, ib_ino_t ino,
+	ib_ino_info_t *ino_p);
+extern uint32_t ib_register_intr(ib_t *ib_p, ib_mondo_t mondo, uint_t pil,
+	uint_t (*handler)(caddr_t arg), caddr_t arg);
+extern void ib_unregister_intr(ib_mondo_t mondo);
+extern void ib_intr_dist_nintr(ib_t *ib_p, ib_ino_t ino,
+	volatile uint64_t *imr_p);
+extern void ib_intr_dist_all(void *arg, int32_t max_weight, int32_t weight);
+
+extern int pci_pil[];
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_IB_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_intr.h b/usr/src/uts/sun4u/sys/pci/pci_intr.h
new file mode 100644
index 0000000000..17d3ec31c0
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_intr.h
@@ -0,0 +1,56 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_INTR_H
+#define	_SYS_PCI_INTR_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef struct pci_class_val {
+	uint32_t class_code;
+	uint32_t class_mask;
+	uint32_t class_val;
+} pci_class_val_t;
+
+extern dev_info_t *get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip);
+extern uint32_t pci_class_to_pil(dev_info_t *rdip);
+extern int32_t pci_class_to_intr_weight(dev_info_t *rdip);
+extern int pci_add_intr(dev_info_t *dip, dev_info_t *rdip,
+	ddi_intr_handle_impl_t *hdlp);
+extern int pci_remove_intr(dev_info_t *dip, dev_info_t *rdip,
+	ddi_intr_handle_impl_t *hdlp);
+extern uint_t pci_intr_wrapper(caddr_t arg);
+extern void pci_intr_teardown(pci_t *pci_p);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_INTR_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_iommu.h b/usr/src/uts/sun4u/sys/pci/pci_iommu.h
new file mode 100644
index 0000000000..0286e311ca
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_iommu.h
@@ -0,0 +1,258 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_PCI_IOMMU_H
+#define	_SYS_PCI_IOMMU_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/vmem.h>
+
+typedef uint64_t dvma_addr_t;
+typedef uint64_t dma_bypass_addr_t;
+typedef uint64_t dma_peer_addr_t;
+typedef uint16_t dvma_context_t;
+typedef uint64_t window_t;
+
+/*
+ * The following typedef's represents the types for DMA transactions
+ * and corresponding DMA addresses supported by psycho/schizo.
+ */
+typedef enum { IOMMU_XLATE, IOMMU_BYPASS, PCI_PEER_TO_PEER } iommu_dma_t;
+
+/*
+ * The following macros define the iommu page size and related operations.
+ */
+#define	IOMMU_PAGE_SHIFT	13
+#define	IOMMU_PAGE_SIZE		(1 << IOMMU_PAGE_SHIFT)
+#define	IOMMU_PAGE_MASK		~(IOMMU_PAGE_SIZE - 1)
+#define	IOMMU_PAGE_OFFSET	(IOMMU_PAGE_SIZE - 1)
+#define	IOMMU_PTOB(x)		(((uint64_t)(x)) << IOMMU_PAGE_SHIFT)
+#define	IOMMU_BTOP(x)		((x) >> IOMMU_PAGE_SHIFT)
+#define	IOMMU_BTOPR(x)		IOMMU_BTOP((x) + IOMMU_PAGE_OFFSET)
+
+/*
+ * control register decoding
+ */
+/* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */
+#define	IOMMU_CTL_TO_TSBSIZE(ctl)	((ctl) >> 16)
+#define	IOMMU_TSBSIZE_TO_TSBENTRIES(s)	((1 << (s)) << (13 - 3))
+#define	IOMMU_DARWIN_BOGUS_TSBSIZE	7
+
+/*
+ * boiler plate for tte (everything except the pfn)
+ */
+#define	MAKE_TTE_TEMPLATE(pfn, mp) (COMMON_IOMMU_TTE_V | \
+	(pf_is_memory(pfn) ? COMMON_IOMMU_TTE_C : 0) | \
+	((mp->dmai_rflags & DDI_DMA_READ) ? COMMON_IOMMU_TTE_W : 0) | \
+	((mp->dmai_rflags & DDI_DMA_CONSISTENT) ? 0 : COMMON_IOMMU_TTE_S))
+#define	TTE_IS_INVALID(tte)	(((tte) & COMMON_IOMMU_TTE_V) == 0x0ull)
+
+/*
+ * The following macros define the address ranges supported for DVMA
+ * and iommu bypass transfers.
+ */
+#define	COMMON_IOMMU_BYPASS_BASE	0xFFFC000000000000ull
+#define	COMMON_IOMMU_BYPASS_END		0xFFFC00FFFFFFFFFFull
+
+/*
+ * For iommu bypass addresses, bit 43 specifies cacheability.
+ */
+#define	COMMON_IOMMU_BYPASS_NONCACHE	0x0000080000000000ull
+
+/*
+ * Generic iommu definitions and types:
+ */
+#define	IOMMU_TLB_ENTRIES		16
+
+/*
+ * The following macros are for loading and unloading iotte
+ * entries.
+ */
+#define	COMMON_IOMMU_TTE_SIZE		8
+#define	COMMON_IOMMU_TTE_V		0x8000000000000000ull
+#define	COMMON_IOMMU_TTE_S		0x1000000000000000ull
+#define	COMMON_IOMMU_TTE_C		0x0000000000000010ull
+#define	COMMON_IOMMU_TTE_W		0x0000000000000002ull
+#define	COMMON_IOMMU_INVALID_TTE	0x0000000000000000ull
+
+/*
+ * Tomatillo's micro TLB bug. errata #82
+ */
+typedef struct dvma_unbind_req {
+	uint32_t	dur_base;
+	uint_t		dur_npg;
+	uint_t		dur_flags; /* = dmai_flags & DMAI_FLAGS_VMEMCACHE */
+} dvma_unbind_req_t;
+
+/*
+ * iommu block soft state structure:
+ *
+ * Each pci node may share an iommu block structure with its peer
+ * node of have its own private iommu block structure.
+ */
+typedef struct iommu iommu_t;
+struct iommu {
+
+	pci_t *iommu_pci_p;	/* link back to pci soft state */
+	int iommu_inst;		/* ddi_get_instance(iommu_pci_p->pci_dip) */
+
+	volatile uint64_t *iommu_ctrl_reg;
+	volatile uint64_t *iommu_tsb_base_addr_reg;
+	volatile uint64_t *iommu_flush_page_reg;
+	volatile uint64_t *iommu_flush_ctx_reg;	/* schizo only */
+	volatile uint64_t *iommu_tfar_reg; /* tomatillo only */
+
+	/*
+	 * virtual and physical addresses and size of the iommu tsb:
+	 */
+	uint64_t *iommu_tsb_vaddr;
+	uint64_t iommu_tsb_paddr;
+	uint_t iommu_tsb_entries;
+	uint_t iommu_tsb_size;
+
+	/*
+	 * address ranges of dvma space:
+	 */
+	dvma_addr_t iommu_dvma_base;
+	dvma_addr_t iommu_dvma_end;
+	dvma_addr_t iommu_dvma_fast_end;
+	dvma_addr_t dvma_base_pg;	/* = IOMMU_BTOP(iommu_dvma_base) */
+	dvma_addr_t dvma_end_pg;	/* = IOMMU_BTOP(iommu_dvma_end) */
+
+	/*
+	 * address ranges of dma bypass space:
+	 */
+	dma_bypass_addr_t iommu_dma_bypass_base;
+	dma_bypass_addr_t iommu_dma_bypass_end;
+
+	/*
+	 * virtual memory map and callback id for dvma space:
+	 */
+	vmem_t *iommu_dvma_map;
+	uintptr_t iommu_dvma_clid;
+
+	/*
+	 * fields for fast dvma interfaces:
+	 */
+	ulong_t iommu_dvma_reserve;
+
+	/*
+	 * dvma fast track page cache byte map
+	 */
+	uint8_t *iommu_dvma_cache_locks;
+	uint_t iommu_dvma_addr_scan_start;
+
+	/*
+	 * dvma context bitmap
+	 */
+	uint64_t *iommu_ctx_bitmap;
+
+	/*
+	 * dvma debug
+	 */
+	kmutex_t dvma_debug_lock;
+	uint32_t dvma_alloc_rec_index;
+	uint32_t dvma_free_rec_index;
+	uint32_t dvma_active_count;
+
+	struct dvma_rec *dvma_alloc_rec;
+	struct dvma_rec *dvma_free_rec;
+	struct dvma_rec *dvma_active_list;
+
+	/*
+	 * tomatillo's micro TLB bug. errata #82
+	 */
+	dvma_unbind_req_t *iommu_mtlb_req_p;	/* unbind requests */
+	uint32_t	iommu_mtlb_maxpgs;	/* GC threshold */
+	uint32_t	iommu_mtlb_npgs;	/* total page count */
+	uint32_t	iommu_mtlb_nreq;	/* total request count */
+	kmutex_t	iommu_mtlb_lock;
+};
+
+typedef struct pci_dvma_range_prop {
+	uint32_t dvma_base;
+	uint32_t dvma_len;
+} pci_dvma_range_prop_t;
+
+#define	IOMMU_PAGE_INDEX(iommu_p, dvma_pg) ((dvma_pg) - (iommu_p)->dvma_base_pg)
+#define	IOMMU_PAGE_FLUSH(iommu_p, dvma_pg) \
+	*(iommu_p)->iommu_flush_page_reg = IOMMU_PTOB(dvma_pg)
+#define	IOMMU_UNLOAD_TTE(iommu_p, pg_index) \
+	(iommu_p)->iommu_tsb_vaddr[pg_index] = COMMON_IOMMU_INVALID_TTE
+#define	IOMMU_PAGE_TTEPA(iommu_p, dvma_pg) \
+	((iommu_p)->iommu_tsb_paddr + (IOMMU_PAGE_INDEX(iommu_p, dvma_pg) << 3))
+
+#define	IOMMU_CONTEXT_BITS 12
+#define	IOMMU_CTX_MASK		((1 << IOMMU_CONTEXT_BITS) - 1)
+#define	IOMMU_TTE_CTX_SHIFT	47
+#define	IOMMU_CTX2TTE(ctx) (((uint64_t)(ctx)) << IOMMU_TTE_CTX_SHIFT)
+#define	IOMMU_TTE2CTX(tte) \
+		(((tte) >> (IOMMU_TTE_CTX_SHIFT - 32)) & IOMMU_CTX_MASK)
+#define	MP2CTX(mp)	IOMMU_TTE2CTX((uint32_t)(mp)->dmai_tte)
+
+/* dvma debug */
+#define	DVMA_DBG_ON(iommu_p)  \
+	((1ull << (iommu_p)->iommu_inst) & pci_dvma_debug_on)
+#define	DVMA_DBG_OFF(iommu_p) \
+	((1ull << (iommu_p)->iommu_inst) & pci_dvma_debug_off)
+
+extern void pci_dvma_debug_fini(iommu_t *iommu_p);
+extern void pci_dvma_alloc_debug(iommu_t *iommu_p, char *address, uint_t len,
+	ddi_dma_impl_t *mp);
+extern void pci_dvma_free_debug(iommu_t *iommu_p, char *address, uint_t len,
+	ddi_dma_impl_t *mp);
+
+/* dvma routines */
+extern void iommu_map_pages(iommu_t *iommu_p, ddi_dma_impl_t *mp,
+			dvma_addr_t dvma_pg, size_t npages, size_t pfn_index);
+extern void iommu_unmap_pages(iommu_t *iommu_p, dvma_addr_t dvma_pg,
+			uint_t npages);
+extern void iommu_remap_pages(iommu_t *iommu_p, ddi_dma_impl_t *mp,
+			dvma_addr_t dvma_pg, size_t npages, size_t pfn_index);
+extern void iommu_map_window(iommu_t *iommu_p,
+			ddi_dma_impl_t *mp, window_t window);
+extern void iommu_unmap_window(iommu_t *iommu_p, ddi_dma_impl_t *mp);
+
+/* iommu initialization routines */
+extern void iommu_configure(iommu_t *iommu_p);
+extern void iommu_create(pci_t *pci_p);
+extern void iommu_destroy(pci_t *pci_p);
+extern uint_t iommu_tsb_size_encode(uint_t tsb_bytes);
+
+/* TSB allocate/free */
+extern int pci_alloc_tsb(pci_t *pci_p);
+extern void pci_free_tsb(pci_t *pci_p);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_IOMMU_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_nexus.h b/usr/src/uts/sun4u/sys/pci/pci_nexus.h
new file mode 100644
index 0000000000..9d984bd99e
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_nexus.h
@@ -0,0 +1,62 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 1994-2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SYS_PCI_NEXUS_H
+#define	_SYS_PCI_NEXUS_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef struct pci_ispec pci_ispec_t;
+
+struct pci_ispec {
+	struct intrspec ispec;		/* interrupt pri/pil, vec/ino, func */
+	dev_info_t *pci_ispec_dip;	/* interrupt parent dip */
+	uint32_t pci_ispec_intr;	/* dev "interrupts" prop or imap */
+					/* lookup result storage for UPA */
+					/* intr */
+	void *pci_ispec_arg;		/* interrupt handler argument */
+	ddi_acc_handle_t pci_ispec_hdl;	/* map hdl to dev PCI config space */
+	pci_ispec_t *pci_ispec_next;	/* per ino link list */
+};
+
+enum pci_fault_ops { FAULT_LOG, FAULT_RESET, FAULT_POKEFLT, FAULT_POKEFINI };
+
+struct pci_fault_handle {
+	dev_info_t *fh_dip;		/* device registered fault handler */
+	int (*fh_f)();			/* fault handler function */
+	void *fh_arg;			/* argument for fault handler */
+	struct pci_fault_handle *fh_next;
+};
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_NEXUS_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_obj.h b/usr/src/uts/sun4u/sys/pci/pci_obj.h
new file mode 100644
index 0000000000..358ccd132d
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_obj.h
@@ -0,0 +1,67 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_OBJ_H
+#define	_SYS_PCI_OBJ_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/pci.h>
+#include <sys/pci_intr_lib.h>
+#include <sys/pci/pci_nexus.h>
+#include <sys/pci/pci_types.h>
+#include <sys/pci/pci_iommu.h>
+#include <sys/pci/pci_space.h>
+#include <sys/pci/pci_dma.h>	/* macros use perf counters in pci_space.h */
+#include <sys/pci/pci_sc.h>	/* needs pci_iommu.h */
+#include <sys/pci/pci_fdvma.h>
+#include <sys/pci/pci_ib.h>
+#include <sys/pci/pci_cb.h>
+#include <sys/pci/pci_ecc.h>
+#include <sys/pci/pci_pbm.h>
+#include <sys/pci/pci_intr.h>	/* needs pci_ib.h */
+#include <sys/pci/pci_counters.h>
+#include <sys/pci/pci_var.h>
+#include <sys/pci/pci_util.h>
+#include <sys/pci/pci_regs.h>
+#include <sys/pci/pci_debug.h>
+#include <sys/pci/pci_fm.h>	/* needs pci_var.h */
+#include <sys/pci/pci_chip.h>	/* collection of chip specific interface */
+#include <sys/pci/pci_reloc.h>
+#ifdef PCI_DMA_TEST
+#include <sys/pci/pci_test.h>
+#endif
+#include <sys/pci/pci_axq.h>
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_OBJ_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_pbm.h b/usr/src/uts/sun4u/sys/pci/pci_pbm.h
new file mode 100644
index 0000000000..27fe99bcba
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_pbm.h
@@ -0,0 +1,187 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_PBM_H
+#define	_SYS_PCI_PBM_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/types.h>
+#include <sys/dditypes.h>
+#include <sys/ontrap.h>
+#include <sys/callb.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * The following structure represents the pci configuration header
+ * for a psycho or schizo PBM.
+ */
+typedef struct config_header config_header_t;
+struct config_header {
+	volatile uint16_t ch_vendor_id;
+	volatile uint16_t ch_device_id;
+	volatile uint16_t ch_command_reg;
+	volatile uint16_t ch_status_reg;
+	volatile uint8_t ch_revision_id_reg;
+	volatile uint8_t ch_programming_if_code_reg;
+	volatile uint8_t ch_sub_class_reg;
+	volatile uint8_t ch_base_class_reg;
+	volatile uint8_t ch_cache_line_size_reg;
+	volatile uint8_t ch_latency_timer_reg;
+	volatile uint8_t ch_header_type_reg;
+};
+
+typedef enum { PBM_SPEED_33MHZ, PBM_SPEED_66MHZ } pbm_speed_t;
+
+/*
+ * Bit fields of ch_status_reg for cmn_err's %b
+ */
+#define	PCI_STATUS_BITS "\020\
+\11signaled-parity-error\
+\14signaled-target-abort\
+\15received-target-abort\
+\16received-master-abort\
+\17signaled-system-error\
+\20detected-parity-error"
+
+/*
+ * pbm block soft state structure:
+ *
+ * Each pci node has its own private pbm block structure.
+ */
+struct pbm {
+	pci_t *pbm_pci_p;	/* link back to pci soft state */
+	pbm_speed_t pbm_speed;	/* PCI bus speed (33 or 66 Mhz) */
+
+	/*
+	 * PBM control and error registers:
+	 */
+	volatile uint64_t *pbm_ctrl_reg;
+	volatile uint64_t *pbm_async_flt_status_reg;
+	volatile uint64_t *pbm_async_flt_addr_reg;
+	volatile uint64_t *pbm_diag_reg;
+	volatile uint64_t *pbm_estar_reg;
+	volatile uint64_t *pbm_pcix_err_stat_reg;
+	volatile uint64_t *pbm_pci_ped_ctrl;
+
+	/*
+	 * PCI configuration header block for the PBM:
+	 */
+	config_header_t *pbm_config_header;
+
+	/*
+	 * Memory address range on this PBM used to determine DMA on this pbm
+	 */
+	iopfn_t pbm_base_pfn;
+	iopfn_t pbm_last_pfn;
+
+	/*
+	 * pbm Interrupt Mapping Register save area
+	 */
+	uint64_t pbm_imr_save;
+
+	/* To save CDMA interrupt state across CPR */
+	uint64_t pbm_cdma_imr_save;
+
+	/*
+	 * pbm error interrupt priority:
+	 */
+	ddi_iblock_cookie_t pbm_iblock_cookie;
+
+	/*
+	 * Consistent Mode DMA Sync
+	 */
+	uint64_t pbm_sync_reg_pa;	/* pending reg for xmits/tomatillo */
+	ib_ino_t pbm_sync_ino;
+
+	volatile uint32_t pbm_cdma_flag;
+
+	/*
+	 * DMA sync lock to serialize access to sync hardware.
+	 * Used for schizo (>= 2.3) and xmits. Tomatillo does not require
+	 * serialization.
+	 */
+	kmutex_t pbm_sync_mutex;
+
+	/*
+	 * support for ddi_poke:
+	 */
+	on_trap_data_t *pbm_ontrap_data;
+
+	kmutex_t pbm_pokefault_mutex;
+
+	/*
+	 * Support for cautious IO accesses
+	 */
+	ddi_acc_handle_t pbm_excl_handle;
+
+	/*
+	 * Support for PCI bus quiesce/unquiesce
+	 */
+	uint64_t pbm_saved_ctrl_reg;
+	uint_t pbm_quiesce_count;
+	callb_id_t pbm_panic_cb_id;
+	callb_id_t pbm_debug_cb_id;
+	uint64_t pbm_anychild_cfgpa;
+
+	/*
+	 * Sun Fire 15k PIO limiting semaphore
+	 */
+	uint32_t pbm_pio_limit;
+	volatile uint32_t pbm_pio_counter;
+
+#define	PBM_NAMESTR_BUFLEN 	64
+	/* driver name & instance */
+	char pbm_nameinst_str[PBM_NAMESTR_BUFLEN];
+
+	/* nodename & node_addr */
+	char *pbm_nameaddr_str;
+};
+
+/*
+ * forward declarations (object creation and destruction):
+ */
+
+extern void pbm_create(pci_t *pci_p);
+extern void pbm_destroy(pci_t *pci_p);
+extern void pbm_configure(pbm_t *pbm_p);
+extern void pbm_clear_error(pbm_t *pbm_p);
+extern void pbm_enable_intr(pbm_t *pbm_p);
+extern void pbm_suspend(pbm_t *pbm_p);
+extern void pbm_resume(pbm_t *pbm_p);
+extern void pbm_intr_dist(void *arg);
+extern int pbm_register_intr(pbm_t *pbm_p);
+extern int pbm_afsr_report(dev_info_t *dip, uint64_t fme_ena,
+		pbm_errstate_t *pbm_err_p);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_PBM_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_pwr.h b/usr/src/uts/sun4u/sys/pci/pci_pwr.h
new file mode 100644
index 0000000000..729166a220
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_pwr.h
@@ -0,0 +1,165 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_PCI_PWR_H
+#define	_SYS_PCI_PWR_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/epm.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * An element of this structure type is allocated for
+ * each PCI child to track power info.
+ */
+typedef struct pci_pwr_chld {
+	dev_info_t		*dip;	/* node this struct represents */
+	int			dev_cap;
+					/* The clock capability the device */
+					/* reports it  can operate. */
+	int			bus_speed;
+					/* the speed of the bus for this */
+					/* device during E* */
+	struct pci_pwr_chld	*next;	/* link to next item on list */
+	int			flags;	/* State for entire device */
+	int			*comp_pwr; /* state for each component */
+	int			num_comps; /* size of comp_pwr */
+	int			u01;	/* # comps in UNKNOWN, D0, D1 */
+} pci_pwr_chld_t;
+
+/*
+ * For each PCI nexus instance that is PM capable, it will have
+ * the following structure allocated.
+ */
+typedef struct pci_pwr {
+	/*
+	 * cpr and power management support:
+	 */
+	kmutex_t	pwr_mutex;
+	int		current_lvl; /* power level of bus */
+	dev_info_t	*pwr_dip;	/* dip of nexus */
+	pci_pwr_chld_t	*pwr_info;	/* linked list of children */
+	int		pwr_flags;	/* power management flags */
+	int		pwr_fp;		/* # requiring full power */
+	int		pwr_uk;		/* # at unknown PM state */
+	int		pwr_d0;		/* # at d0 PM state */
+	int		pwr_d1;		/* # at d1 PM state */
+	int		pwr_d2;		/* # at d2 PM state */
+	int		pwr_d3;		/* # at d3 PM state */
+
+} pci_pwr_t;
+
+#define	PCI_CLK_SETTLE_TIME	10000 /* settle time before PCI operation */
+
+/*
+ * ret this if unable to det slot speed while in slow mode
+ */
+#define	INVALID_BUS_SPEED	-1
+
+/*
+ * XXX Number of components for dip.  This needs to be provided by DDI.
+ */
+#define	PM_NUMCMPTS(dip)	(DEVI(dip)->devi_pm_num_components)
+
+/*
+ * Label for component 0
+ */
+#define	PCI_PM_COMP_0	0
+
+/*
+ * Bus levels returned by pci_pwr_new_lvl(). In addition to
+ * PM_LEVEL_B[0-3], a level is needed for variable clock
+ * mode.  These levels MUST correspond to the levels specified
+ * in the pm-components property.
+ */
+#define	PM_LEVEL_DYN	1
+#define	PM_LEVEL_B3	0
+#define	PM_LEVEL_B2	1
+#define	PM_LEVEL_B1	2
+#define	PM_LEVEL_B0	3
+
+/*
+ * PCI clock speeds for slow mode (expressed in KHz)
+ */
+#define	PCI_1MHZ	1000
+#define	PCI_4MHZ	(4 * PCI_1MHZ)
+
+/*
+ * Bit values for struct pci_pwr.pwr_flags
+ */
+#define	PCI_PWR_PARKING		0x01 /* Need to re-enable parking */
+#define	PCI_PWR_SLOW_CAPABLE	0x02 /* HW supports reduced clock speeds */
+#define	PCI_PWR_B1_CAPABLE	0x04 /* HW supports B1 state */
+#define	PCI_PWR_B2_CAPABLE	0x08 /* HW supports B2 state */
+#define	PCI_PWR_B3_CAPABLE	0x10 /* HW supports B3 state */
+#define	PCI_PWR_COMP_BUSY	0x20 /* component set busy */
+
+/*
+ * State flags for each device (struct pci_pwr_chld.flags)
+ */
+#define	PWR_FP_HOLD		0x01	/* pwr_fp counted for this dev */
+
+/*
+ * Arbitrary level that pci_pwr_chld.comp_pwr is initialized
+ */
+#define	PM_LEVEL_NOLEVEL	-2
+
+#define	PM_CAPABLE(pwr_p)	(pwr_p != NULL)
+#define	SLOW_CAPABLE(pwr_p)	((pwr_p->pwr_flags &\
+				PCI_PWR_SLOW_CAPABLE) ==\
+				PCI_PWR_SLOW_CAPABLE)
+
+/*
+ * Binary prop used by suspend/resume if it saved config regs
+ */
+#define	NEXUS_SAVED "nexus-saved-config-regs"
+
+extern void pci_pwr_component_busy(pci_pwr_t *pwr_p);
+extern void pci_pwr_component_idle(pci_pwr_t *pwr_p);
+extern int pci_pwr_current_lvl(pci_pwr_t *pwr_p);
+extern int pci_pwr_new_lvl(pci_pwr_t *pwr_p);
+extern int pci_pwr_ops(pci_pwr_t *pwr_p, dev_info_t *dip, void *impl_arg,
+    pm_bus_power_op_t op, void *arg, void *result);
+extern pci_pwr_chld_t *pci_pwr_get_info(pci_pwr_t *pwr_p, dev_info_t *);
+extern void pci_pwr_create_info(pci_pwr_t *pwr_p, dev_info_t *);
+extern void pci_pwr_rm_info(pci_pwr_t *pwr_p, dev_info_t *);
+extern void pci_pwr_add_components(pci_pwr_t *pwr_p, dev_info_t *dip,
+    pci_pwr_chld_t *p);
+extern void pci_pwr_resume(dev_info_t *dip, pci_pwr_t *pwr_p);
+extern void pci_pwr_suspend(dev_info_t *dip, pci_pwr_t *pwr_p);
+extern void pci_pwr_component_busy(pci_pwr_t *p);
+extern void pci_pwr_component_idle(pci_pwr_t *p);
+extern void pci_pwr_change(pci_pwr_t *pwr_p, int current, int new);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_PWR_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_regs.h b/usr/src/uts/sun4u/sys/pci/pci_regs.h
new file mode 100644
index 0000000000..3adb0d7408
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_regs.h
@@ -0,0 +1,175 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 1991-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_PCI_REGS_H
+#define	_SYS_PCI_REGS_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Offsets of registers in the interrupt block:
+ */
+
+#define	COMMON_IB_UPA0_INTR_MAP_REG_OFFSET	0x6000
+#define	COMMON_IB_UPA1_INTR_MAP_REG_OFFSET	0x8000
+#define	COMMON_IB_SLOT_INTR_STATE_DIAG_REG	0xA800
+#define	COMMON_IB_OBIO_INTR_STATE_DIAG_REG	0xA808
+#define	COMMON_IB_SLOT_CLEAR_INTR_REG_OFFSET	0x1400
+#define	COMMON_IB_INTR_RETRY_TIMER_OFFSET	0x1A00
+
+/*
+ * Offsets of registers in the ECC block:
+ */
+#define	COMMON_ECC_CSR_OFFSET			0x20
+#define	COMMON_UE_AFSR_OFFSET			0x30
+#define	COMMON_UE_AFAR_OFFSET			0x38
+#define	COMMON_CE_AFSR_OFFSET			0x40
+#define	COMMON_CE_AFAR_OFFSET			0x48
+
+/*
+ * Offsets of registers in the iommu block:
+ */
+#define	COMMON_IOMMU_CTRL_REG_OFFSET		0x00000200
+#define	COMMON_IOMMU_TSB_BASE_ADDR_REG_OFFSET	0x00000208
+#define	COMMON_IOMMU_FLUSH_PAGE_REG_OFFSET	0x00000210
+
+#define	COMMON_IOMMU_TLB_TAG_DIAG_ACC_OFFSET	0x0000A580
+#define	COMMON_IOMMU_TLB_DATA_DIAG_ACC_OFFSET	0x0000A600
+
+/*
+ * (psycho and schizo) control register bit definitions:
+ */
+#define	COMMON_CB_CONTROL_STATUS_IGN		0x0007c00000000000ull
+#define	COMMON_CB_CONTROL_STATUS_IGN_SHIFT	46
+#define	COMMON_CB_CONTROL_STATUS_APCKEN		0x0000000000000008ull
+#define	COMMON_CB_CONTROL_STATUS_APERR		0x0000000000000004ull
+#define	COMMON_CB_CONTROL_STATUS_IAP		0x0000000000000002ull
+
+/*
+ * (psycho and schizo) interrupt mapping register bit definitions:
+ */
+#define	COMMON_INTR_MAP_REG_VALID		0x0000000080000000ull
+#define	COMMON_INTR_MAP_REG_TID			0x000000007C000000ull
+#define	COMMON_INTR_MAP_REG_IGN			0x00000000000007C0ull
+#define	COMMON_INTR_MAP_REG_INO			0x000000000000003full
+#define	COMMON_INTR_MAP_REG_TID_SHIFT		26
+#define	COMMON_INTR_MAP_REG_IGN_SHIFT		6
+
+/*
+ * psycho clear interrupt register bit definitions:
+ */
+#define	COMMON_CLEAR_INTR_REG_MASK		0x0000000000000003ull
+#define	COMMON_CLEAR_INTR_REG_IDLE		0x0000000000000000ull
+#define	COMMON_CLEAR_INTR_REG_RECEIVED		0x0000000000000001ull
+#define	COMMON_CLEAR_INTR_REG_RSVD		0x0000000000000002ull
+#define	COMMON_CLEAR_INTR_REG_PENDING		0x0000000000000003ull
+
+/*
+ * psycho and schizo ECC control register bit definitions:
+ */
+#define	COMMON_ECC_CTRL_ECC_EN			0x8000000000000000ull
+#define	COMMON_ECC_CTRL_UE_INTEN		0x4000000000000000ull
+#define	COMMON_ECC_CTRL_CE_INTEN		0x2000000000000000ull
+
+/*
+ * sabre ECC UE AFSR bit definitions:
+ */
+#define	SABRE_UE_AFSR_SDTE_SHIFT		57
+#define	SABRE_UE_AFSR_PDTE_SHIFT		56
+#define	SABRE_UE_ARSR_DTE_MASK			0x0000000000000003ull
+#define	SABRE_UE_AFSR_E_SDTE			0x2
+#define	SABRE_UE_AFSR_E_PDTE			0x1
+
+/*
+ * psycho and schizo ECC UE AFSR bit definitions:
+ */
+#define	COMMON_ECC_UE_AFSR_PE_SHIFT		61
+#define	COMMON_ECC_UE_AFSR_SE_SHIFT		58
+#define	COMMON_ECC_UE_AFSR_E_MASK		0x0000000000000007ull
+#define	COMMON_ECC_UE_AFSR_E_PIO		0x0000000000000004ull
+#define	COMMON_ECC_UE_AFSR_E_DRD		0x0000000000000002ull
+#define	COMMON_ECC_UE_AFSR_E_DWR		0x0000000000000001ull
+
+/*
+ * psycho and schizo ECC CE AFSR bit definitions:
+ */
+#define	COMMON_ECC_CE_AFSR_PE_SHIFT		61
+#define	COMMON_ECC_CE_AFSR_SE_SHIFT		58
+#define	COMMON_ECC_CE_AFSR_E_MASK		0x0000000000000007ull
+#define	COMMON_ECC_CE_AFSR_E_PIO		0x0000000000000004ull
+#define	COMMON_ECC_CE_AFSR_E_DRD		0x0000000000000002ull
+#define	COMMON_ECC_CE_AFSR_E_DWR		0x0000000000000001ull
+
+/*
+ * psycho and schizo pci control register bits:
+ */
+#define	COMMON_PCI_CTRL_SBH_ERR			0x0000000800000000ull
+#define	COMMON_PCI_CTRL_SERR			0x0000000400000000ull
+#define	COMMON_PCI_CTRL_SPEED			0x0000000200000000ull
+
+/*
+ * psycho and schizo PCI diagnostic register bit definitions:
+ */
+#define	COMMON_PCI_DIAG_DIS_RETRY		0x0000000000000040ull
+#define	COMMON_PCI_DIAG_DIS_INTSYNC		0x0000000000000020ull
+
+/*
+ * psycho and schizo IOMMU control register bit definitions:
+ */
+#define	COMMON_IOMMU_CTRL_ENABLE	0x0000000000000001ull
+#define	COMMON_IOMMU_CTRL_DIAG_ENABLE	0x0000000000000002ull
+#define	COMMON_IOMMU_CTRL_TSB_SZ_SHIFT	16
+#define	COMMON_IOMMU_CTRL_TBW_SZ_SHIFT	2
+#define	COMMON_IOMMU_CTRL_LCK_ENABLE	0x0000000000800000ull
+
+/*
+ * psycho and schizo streaming cache control register bit definitions:
+ */
+#define	COMMON_SC_CTRL_ENABLE		0x0000000000000001ull
+#define	COMMON_SC_CTRL_DIAG_ENABLE	0x0000000000000002ull
+#define	COMMON_SC_CTRL_RR__DISABLE	0x0000000000000004ull
+#define	COMMON_SC_CTRL_LRU_LE		0x0000000000000008ull
+
+/*
+ * offsets of PCI address spaces from base address:
+ */
+#define	PCI_CONFIG			0x001000000ull
+#define	PCI_A_IO			0x002000000ull
+#define	PCI_B_IO			0x002010000ull
+#define	PCI_A_MEMORY			0x100000000ull
+#define	PCI_B_MEMORY			0x180000000ull
+#define	PCI_IO_SIZE			0x000010000ull
+#define	PCI_MEM_SIZE			0x080000000ull
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_REGS_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_reloc.h b/usr/src/uts/sun4u/sys/pci/pci_reloc.h
new file mode 100644
index 0000000000..c2cf4bfd2d
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_reloc.h
@@ -0,0 +1,59 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_RELOC_H
+#define	_SYS_PCI_RELOC_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+extern int pci_dvma_remap_enabled;
+extern kthread_t *pci_reloc_thread;
+extern kmutex_t pci_reloc_mutex;
+extern kcondvar_t pci_reloc_cv;
+extern int pci_reloc_presuspend;
+extern int pci_reloc_suspend;
+
+extern void pci_reloc_init();
+extern void pci_reloc_fini();
+
+extern int pci_dvma_remap(dev_info_t *, dev_info_t *, ddi_dma_impl_t *,
+	off_t, size_t);
+extern void pci_dvma_unregister_callbacks(pci_t *, ddi_dma_impl_t *);
+
+extern void pci_fdvma_remap(ddi_dma_impl_t *, caddr_t, dvma_addr_t,
+	size_t, size_t, pfn_t);
+extern void pci_fdvma_unregister_callbacks(pci_t *, fdvma_t *,
+	ddi_dma_impl_t *, uint_t);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_RELOC_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_sc.h b/usr/src/uts/sun4u/sys/pci/pci_sc.h
new file mode 100644
index 0000000000..8c66f65717
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_sc.h
@@ -0,0 +1,97 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_SC_H
+#define	_SYS_PCI_SC_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * streaming cache (sc) block soft state structure:
+ *
+ * Each pci node contains has its own private sc block structure.
+ */
+typedef struct sc sc_t;
+struct sc {
+
+	pci_t *sc_pci_p;	/* link back to pci soft state */
+
+	/*
+	 * control registers (psycho and schizo):
+	 */
+	volatile uint64_t *sc_ctrl_reg;
+	volatile uint64_t *sc_invl_reg;
+	volatile uint64_t *sc_sync_reg;
+	uint64_t sc_sync_reg_pa;
+
+	/*
+	 * control registers (schizo only):
+	 */
+	volatile uint64_t *sc_ctx_invl_reg;
+	volatile uint64_t *sc_ctx_match_reg;
+
+	/*
+	 * diagnostic access registers:
+	 */
+	volatile uint64_t *sc_data_diag_acc;
+	volatile uint64_t *sc_tag_diag_acc;
+	volatile uint64_t *sc_ltag_diag_acc;
+
+	/*
+	 * Sync flag and its associated buffer.
+	 */
+	caddr_t sc_sync_flag_base;
+	volatile uint64_t *sc_sync_flag_vaddr;
+	uint64_t sc_sync_flag_pa;
+
+	kmutex_t sc_sync_mutex;		/* mutex for flush/sync register */
+};
+
+#define	PCI_SBUF_ENTRIES	16	/* number of i/o cache lines */
+#define	PCI_SBUF_LINE_SIZE	64	/* size of i/o cache line */
+
+#define	PCI_CACHE_LINE_SIZE	(PCI_SBUF_LINE_SIZE / 4)
+
+extern void sc_create(pci_t *pci_p);
+extern void sc_destroy(pci_t *pci_p);
+extern void sc_configure(sc_t *sc_p);
+
+/*
+ * The most significant bit (63) of each context match register.
+ */
+#define	SC_CMR_DIRTY_BIT	1
+#define	SC_ENTRIES		16
+#define	SC_ENT_SHIFT		(64 - SC_ENTRIES)
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_SC_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_simba.h b/usr/src/uts/sun4u/sys/pci/pci_simba.h
new file mode 100644
index 0000000000..621c921b19
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_simba.h
@@ -0,0 +1,179 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 1994-1998 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SYS_PCI_SIMBA_H
+#define	_SYS_PCI_SIMBA_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * This files contains info specific to Simba (pci to pci bridge)
+ * The rest of info common to simba and DecNet are in "pci.h"
+ */
+
+/*
+ * Simba configuration space registers.
+ */
+#define	PCI_BCNF_SECSTATUS		0x1e	/* secondary status */
+
+/*
+ * Simba device specific registers.
+ */
+#define	PCI_BCNF_MATER_RETRY_LIMIT	0xc0	/* primary master retry limit */
+#define	PCI_BCNF_DMA_AFSR		0xc8	/* dma afsr */
+#define	PCI_BCNF_DMA_AFAR		0xd0	/* dma afar */
+#define	PCI_BCNF_PIOTGT_RTY_LIMIT	0xd8	/* pio target retry limit */
+#define	PCI_BCNF_PIOTGT_LATE_TIMER	0xd9	/* pio target retry limit */
+#define	PCI_BCNF_DMATGT_RTY_LIMIT	0xda	/* dma target retry limit */
+#define	PCI_BCNF_DMATGT_LATE_TIMER	0xdb	/* dma target retry limit */
+#define	PCI_BCNF_TGT_RETRY_LIMIT	0xdc	/* primary master retry limit */
+#define	PCI_BCNF_SECBRIDGE_CTL		0xdd	/* secondary bridge control */
+#define	PCI_BCNF_ADDR_MAP		0xdf	/* address map */
+
+/*
+ * Psycho compatible registers.
+ */
+#define	PCI_BCNF_CTL_STAT		0xe0	/* control-status */
+#define	PCI_BCNF_PIO_AFSR		0xe8	/* pio afsr */
+#define	PCI_BCNF_PIO_AFAR		0xf0	/* pio afar */
+
+/*
+ * Simba device specific registers.
+ */
+#define	PCI_BCNF_DIAGNOSTICS		0xf8	/* diagnostics */
+
+
+/*
+ * primary/secondary timer reg mask(addrs = 0x0d/0x1b).
+ */
+#define	PCI_LATENCY_TMR_LO		0x7	/* read only part, 0x0 */
+#define	PCI_LATENCY_TMR_HI		0xf8	/* programable part */
+
+/*
+ * PCI secondary status register bits.
+ * All bit definitions are the same as primary status register,
+ * but the meaning of bit 14 relates to secondary bus.
+ */
+
+
+/*
+ * Secondary control bit defines(addrs = 0xdd).
+ */
+#define	PCI_SEC_CNTL_PIO_PREF		0x1	/* prefetch dma reads as pio */
+#define	PCI_SEC_CNTL_CONVT_MRM		0x2	/* convert mem multiple read */
+
+/*
+ * Psycho ctrl/status reg bit defines(addrs = 0xe0).
+ */
+#define	PCI_PSYCHO_SLOT_ENAM_MASK	0xf	/* slot arbiter enable mask */
+#define	PCI_PSYCHO_SEC_ERRINIT_ENAB	0x100	/* 1=forward SERR to primary */
+#define	PCI_PSYCHO_WAKEUP_ENAB		0x200   /* not used, reads as 0 */
+#define	PCI_PSYCHO_SBH_INT_ENAB		0x400   /* not used, reads as 0 */
+#define	PCI_PSYCHO_SLOT_PRIORITY	0xf0000 /* slot arb priority mask */
+#define	PCI_PSYCHO_CPU_PRIORITY		0x100000 /* pio arb priority (simba) */
+#define	PCI_PSYCHO_PBUS_PARK_ENAB	0x200000 /* pci bus parking enable */
+#define	PCI_PSYCHO_INTER_ARB_ENAB	0x100000000 /* enable internal arb */
+#define	PCI_PSYCHO_PCI_SPEED		0x200000000 /* not used, reads as 0 */
+#define	PCI_PSYCHO_PCI_SYS_ERROR	0x800000000 /* set, if err on 2ndary */
+#define	PCI_PSYCHO_PCI_SBH_ERROR	0x1000000000 /* not used, reads as 0 */
+
+/*
+ * Psycho AFSR reg bit defines(addrs = 0xe8).
+ */
+#define	PCI_PSYCHO_ERR_NUM		0xff		/* error index number */
+#define	PCI_PSYCHO_MID_MASK		(0x1f<<25)	/* mid mask, reads 0 */
+#define	PCI_PSYCHO_BLK			(1<<31)		/* block, reads 0 */
+#define	PCI_PSYCHO_BYTE_MASK		(0xffff<<32)	/* byte mask, reads 0 */
+#define	PCI_PSYCHO_SEC_APERR		(1<<54)    	/* 2ndary adr par err */
+#define	PCI_PSYCHO_PRI_APERR		(1<<55)		/* pri addr par err */
+#define	PCI_PSYCHO_SEC_PERR		(1<<56)		/* 2nd data par err */
+#define	PCI_PSYCHO_SEC_RTRY_ERR		(1<<57)		/* 2nd retry err */
+#define	PCI_PSYCHO_SEC_TA_ERR		(1<<58)		/* 2nd tgt abort err */
+#define	PCI_PSYCHO_SEC_MA_ERR		(1<<59)		/* 2nd mstr abort err */
+#define	PCI_PSYCHO_PRI_PERR		(1<<60)		/* pri data par error */
+#define	PCI_PSYCHO_PRI_RTRY_ERR		(1<<61)		/* pri retry error */
+#define	PCI_PSYCHO_PRI_TA_ERR		(1<<62)		/* mstr tgt abort err */
+#define	PCI_PSYCHO_PRI_MA_ERR		(1<<63)		/* mstr mstr abrt err */
+
+
+/*
+ * notice: In Simba, AFAR will log statring address of transaction with error
+ *		The byte offset will be logged in [7:0] of AFSR.
+ */
+
+/*
+ * Diagnostics reg bit defines(size=d word)(addrs = 0xf8).
+ */
+#define	PCI_DIAG_IDMA_WDATA_PAR		0x1	/* invert dma wr data parity */
+#define	PCI_DIAG_IDMA_RDATA_PAR		0x2	/* invert dma rd data parity */
+#define	PCI_DIAG_IDMA_ADDR_PAR		0x4	/* invert dma addr parity */
+#define	PCI_DIAG_IPIO_WDATA_PAR		0x10	/* invert pio wr data parity */
+#define	PCI_DIAG_IPIO_RDATA_PAR		0x20	/* invert pio rd data parity */
+#define	PCI_DIAG_IPIO_ADDR_PAR		0x40	/* invert pio addr parity */
+
+/*
+ * usefull defines.
+ */
+#define	PCI_UNLIMITED_RETRY		0x0	/* unlimitted retry */
+#define	PCI_UNLIMITED_LATENCY		0x0	/* unlimitted latency */
+
+/*
+ * vendor & device id for simba.
+ */
+#define	PCI_SIMBA_VENID		0x108e  /* vendor id for simba */
+#define	PCI_SIMBA_DEVID		0x5000  /* device id for simba */
+
+/*
+ * programming interface for simba.
+ */
+#define	PCI_SIMBA_PRI			0x0	/*  prog interface for simba */
+
+/*
+ * master/secondary latency timer value.
+ */
+#define	PCI_LATENCY_TIMER_VAL		0x28	/* timer value for simba */
+
+/*
+ * primary bus number for simba.
+ */
+#define	PCI_BCNF_PRIBUS_NUM		0x0	/* primary bus # for simba */
+
+/*
+ * secondary bus number for simba.
+ */
+#define	PCI_BCNF_SECBUS_NUM_ONE		0x1	/* secondary bus number one */
+#define	PCI_BCNF_SECBUS_NUM_TWO		0x2	/* secondary bus number two */
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_SIMBA_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_space.h b/usr/src/uts/sun4u/sys/pci/pci_space.h
new file mode 100644
index 0000000000..ccaca6d0ee
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_space.h
@@ -0,0 +1,164 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_SPACE_H
+#define	_SYS_PCI_SPACE_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	PCI_SPURINTR_MSG_DEFAULT -1ull
+
+extern uint_t tomatillo_disallow_bypass;
+
+extern uint_t pci_interrupt_priorities_property;
+extern uint_t pci_config_space_size_zero;
+extern int pci_pbm_dma_sync_wait;
+extern int pci_dvma_sync_before_unmap;
+extern int pci_sync_lock;
+extern int tomatillo_store_store_wrka;
+extern uint_t tm_mtlb_maxpgs;
+extern uint_t tm_mtlb_gc;
+extern uint_t tm_mtlb_gc_manual;
+extern uint32_t pci_spurintr_duration;
+extern uint64_t pci_spurintr_msgs;
+
+
+extern ushort_t pci_command_default;
+extern uint_t pci_set_latency_timer_register;
+extern uint_t pci_set_cache_line_size_register;
+
+#ifdef DEBUG
+extern uint64_t pci_debug_flags;
+extern uint_t pci_warn_pp0;
+#endif
+extern uint_t pci_disable_pass1_workarounds;
+extern uint_t pci_disable_pass2_workarounds;
+extern uint_t pci_disable_pass3_workarounds;
+extern uint_t pci_disable_plus_workarounds;
+extern uint_t pci_disable_default_workarounds;
+extern uint_t ecc_error_intr_enable;
+extern uint_t pci_sbh_error_intr_enable;
+extern uint_t pci_mmu_error_intr_enable;
+extern uint_t pci_stream_buf_enable;
+extern uint_t pci_stream_buf_exists;
+extern uint_t pci_rerun_disable;
+extern uint_t pci_enable_periodic_loopback_dma;
+extern uint_t pci_enable_retry_arb;
+
+extern uint_t pci_bus_parking_enable;
+extern uint_t pci_error_intr_enable;
+extern uint_t pci_retry_disable;
+extern uint_t pci_retry_enable;
+extern uint_t pci_dwsync_disable;
+extern uint_t pci_intsync_disable;
+extern uint_t pci_b_arb_enable;
+extern uint_t pci_a_arb_enable;
+extern uint_t pci_ecc_afsr_retries;
+
+extern uint_t pci_intr_retry_intv;
+extern uint8_t pci_latency_timer;
+extern uint_t pci_panic_on_sbh_errors;
+extern uint_t pci_panic_on_fatal_errors;
+extern uint_t pci_thermal_intr_fatal;
+extern uint_t pci_buserr_interrupt;
+extern uint_t pci_set_dto_value;
+extern uint_t pci_dto_value;
+extern uint_t pci_lock_sbuf;
+extern uint_t pci_use_contexts;
+extern uint_t pci_sc_use_contexts;
+extern uint_t pci_context_minpages;
+extern uint_t pci_ctx_flush_warn;
+extern uint_t pci_ctx_unsuccess_count;
+extern uint_t pci_ctx_no_active_flush;
+extern uint_t pci_ctx_no_compat;
+
+extern uint_t pci_check_all_handlers;
+extern uint_t pci_unclaimed_intr_max;
+extern ulong_t pci_iommu_dvma_end;
+extern uint_t pci_lock_tlb;
+
+extern uint64_t pci_dvma_debug_on;
+extern uint64_t pci_dvma_debug_off;
+extern uint32_t pci_dvma_debug_rec;
+extern uint_t pci_dvma_page_cache_entries;
+extern uint_t pci_dvma_page_cache_clustsz;
+#ifdef PCI_DMA_PROF
+extern uint_t pci_dvmaft_npages;
+extern uint_t pci_dvmaft_limit;
+extern uint_t pci_dvmaft_free;
+extern uint_t pci_dvmaft_success;
+extern uint_t pci_dvmaft_exhaust;
+extern uint_t pci_dvma_vmem_alloc;
+extern uint_t pci_dvma_vmem_xalloc;
+extern uint_t pci_dvma_vmem_free;
+extern uint_t pci_dvma_vmem_xfree;
+#endif
+extern uint_t pci_disable_fdvma;
+
+extern uint_t pci_iommu_ctx_lock_failure;
+extern uint_t pci_preserve_iommu_tsb;
+
+extern uint64_t pci_perr_enable;
+extern uint64_t pci_serr_enable;
+extern uint64_t pci_perr_fatal;
+extern uint64_t pci_serr_fatal;
+extern hrtime_t pci_intrpend_timeout;
+extern hrtime_t pci_sync_buf_timeout;
+extern hrtime_t pci_cdma_intr_timeout;
+extern uint32_t pci_cdma_intr_count;
+
+extern uint32_t pci_dto_fault_warn;
+extern uint64_t pci_dto_intr_enable;
+extern uint64_t pci_dto_count;
+extern uint64_t pci_errtrig_pa;
+
+extern uintptr_t pci_kmem_clid;
+extern uint_t pci_intr_dma_sync;
+extern uint_t pci_xmits_sc_max_prf;
+extern uint64_t xmits_error_intr_enable;
+extern uint_t xmits_perr_recov_int_enable;
+extern uint_t xmits_max_transactions;
+extern uint_t xmits_max_read_bytes;
+
+extern int pci_dvma_remap_enabled;
+extern kthread_t *pci_reloc_thread;
+extern kmutex_t pci_reloc_mutex;
+extern kcondvar_t pci_reloc_cv;
+extern int pci_reloc_presuspend;
+extern int pci_reloc_suspend;
+extern id_t pci_dvma_cbid;
+extern id_t pci_fast_dvma_cbid;
+extern int pci_dma_panic_on_leak;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_SPACE_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_tools_impl.h b/usr/src/uts/sun4u/sys/pci/pci_tools_impl.h
new file mode 100644
index 0000000000..ca2e57659c
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_tools_impl.h
@@ -0,0 +1,53 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_PCI_TOOLS_IMPL_H
+#define	_SYS_PCI_TOOLS_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * PCI Space definitions.
+ */
+#define	PCI_CONFIG_RANGE_BANK	(PCI_REG_ADDR_G(PCI_ADDR_CONFIG))
+#define	PCI_IO_RANGE_BANK	(PCI_REG_ADDR_G(PCI_ADDR_IO))
+#define	PCI_MEM_RANGE_BANK	(PCI_REG_ADDR_G(PCI_ADDR_MEM32))
+#define	PCI_MEM64_RANGE_BANK	(PCI_REG_ADDR_G(PCI_ADDR_MEM64))
+
+/*
+ * Number of interrupts supported per PCI bus.
+ */
+#define	PCI_MAX_INO		0x3f
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_TOOLS_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_types.h b/usr/src/uts/sun4u/sys/pci/pci_types.h
new file mode 100644
index 0000000000..c2d1617e7b
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_types.h
@@ -0,0 +1,62 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_TYPES_H
+#define	_SYS_PCI_TYPES_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	HI32(x) ((uint32_t)(((uint64_t)(x)) >> 32))
+#define	LO32(x) ((uint32_t)(x))
+#define	NAMEINST(dip)	ddi_driver_name(dip), ddi_get_instance(dip)
+#define	NAMEADDR(dip)	ddi_node_name(dip), ddi_get_name_addr(dip)
+
+typedef uint16_t pci_ign_t;
+typedef struct pci pci_t;
+typedef struct pci_common pci_common_t;
+typedef struct pci_errstate pci_errstate_t;
+typedef struct iommu_errstate iommu_errstate_t;
+typedef struct ecc_errstate ecc_errstate_t;
+typedef struct pbm_errstate pbm_errstate_t;
+typedef struct cb_errstate cb_errstate_t;
+
+/*
+ * external global function prototypes
+ */
+extern int pf_is_memory(pfn_t);
+extern void do_shutdown();
+extern void power_down();
+extern void set_intr_mapping_reg(int, uint64_t *, int);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_TYPES_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_util.h b/usr/src/uts/sun4u/sys/pci/pci_util.h
new file mode 100644
index 0000000000..261ff46d1b
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_util.h
@@ -0,0 +1,64 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_UTIL_H
+#define	_SYS_PCI_UTIL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+extern int init_child(pci_t *pci_p, dev_info_t *child);
+extern int uninit_child(pci_t *pci_p, dev_info_t *child);
+extern int report_dev(dev_info_t *dip);
+extern int get_pci_properties(pci_t *pci_p, dev_info_t *dip);
+extern void free_pci_properties(pci_t *pci_p);
+extern void unmap_pci_registers(pci_t *pci_p);
+extern void fault_init(pci_t *pci_p);
+extern void fault_fini(pci_t *pci_p);
+extern int pci_log_cfg_err(dev_info_t *dip, ushort_t status_reg, char *err_msg);
+extern int pci_get_portid(dev_info_t *dip);
+
+/* bus map routines */
+extern int pci_reloc_reg(dev_info_t *dip, dev_info_t *rdip, pci_t *pci_p,
+	pci_regspec_t *pci_rp);
+extern int pci_xlate_reg(pci_t *pci_p, pci_regspec_t *pci_rp,
+	struct regspec *new_rp);
+
+/* bus add intrspec */
+extern uint_t get_nreg_set(dev_info_t *child);
+extern uint_t get_nintr(dev_info_t *child);
+extern uint64_t pci_get_cfg_pabase(pci_t *pci_p);
+extern int pci_cfg_report(dev_info_t *, ddi_fm_error_t *, pci_errstate_t *,
+	int, uint32_t);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_UTIL_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pci_var.h b/usr/src/uts/sun4u/sys/pci/pci_var.h
new file mode 100644
index 0000000000..441576db0e
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pci_var.h
@@ -0,0 +1,280 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_PCI_VAR_H
+#define	_SYS_PCI_VAR_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * The following typedef is used to represent a
+ * 1275 "bus-range" property of a PCI Bus node.
+ */
+typedef struct bus_range {
+	uint32_t lo;
+	uint32_t hi;
+} pci_bus_range_t;
+
+/*
+ * The following typedef is used to represent a
+ * 1275 "reg" property of a PCI nexus.
+ */
+typedef struct pci_nexus_regspec {
+	uint64_t phys_addr;
+	uint64_t size;
+} pci_nexus_regspec_t;
+
+/*
+ * The following typedef is used to represent an entry in the "ranges"
+ * property of a device node.
+ */
+typedef struct ranges {
+	uint32_t child_high;
+	uint32_t child_mid;
+	uint32_t child_low;
+	uint32_t parent_high;
+	uint32_t parent_low;
+	uint32_t size_high;
+	uint32_t size_low;
+} pci_ranges_t;
+
+typedef enum { PSYCHO, SCHIZO } pci_bridge_t;
+typedef enum { A, B } pci_side_t;
+typedef enum { PCI_NEW, PCI_ATTACHED, PCI_DETACHED, PCI_SUSPENDED } pci_state_t;
+typedef enum { PCI_PBM_OBJ, PCI_ECC_OBJ, PCI_CB_OBJ } pci_obj_t;
+typedef enum { PCI_OBJ_INTR_ADD, PCI_OBJ_INTR_REMOVE } pci_obj_op_t;
+
+#define	PCI_ATTACH_RETCODE(obj, op, err) \
+	((err) ? (obj) << 8 | (op) << 4 | (err) & 0xf : DDI_SUCCESS)
+
+#define	PCI_OTHER_SIDE(side) ((side) ^ 1)
+
+/*
+ * the sequence of the chip_type appearance is significant. There are code
+ * depending on it: CHIP_TYPE(pci_p) < PCI_CHIP_SCHIZO.
+ */
+typedef enum {
+	PCI_CHIP_UNIDENTIFIED = 0,
+
+	PCI_CHIP_PSYCHO = 1,
+	PCI_CHIP_SABRE,
+	PCI_CHIP_HUMMINGBIRD,
+
+	PCI_CHIP_SCHIZO = 0x11,
+	PCI_CHIP_XMITS,
+	PCI_CHIP_TOMATILLO
+} pci_chip_id_t;
+
+/*
+ * [msb]				[lsb]
+ * 0x00 <chip_type> <version#> <module-revision#>
+ */
+#define	CHIP_ID(t, v, m) 	(((t) << 16) | ((v) << 8) | (m))
+#define	ID_CHIP_TYPE(id) 	((id) >> 16)
+#define	PCI_CHIP_ID(pci_p) 	((pci_p)->pci_common_p->pci_chip_id)
+#define	CHIP_TYPE(pci_p) 	ID_CHIP_TYPE(PCI_CHIP_ID(pci_p))
+#define	CHIP_REV(pci_p)		(PCI_CHIP_ID(pci_p) & 0xFF)
+#define	CHIP_VER(pci_p)		((PCI_CHIP_ID(pci_p) >> 8) & 0xFF)
+#define	CB_CHIP_TYPE(cb_p) 	((cb_p)->cb_pci_cmn_p->pci_chip_id >> 16)
+
+/*
+ * pci common soft state structure:
+ *
+ * Each psycho or schizo is represented by a pair of pci nodes in the
+ * device tree.  A single pci common soft state is allocated for each
+ * pair.  The UPA (Safari) bus id of the psycho (schizo) is used for
+ * the instance number.  The attach routine uses the existance of a
+ * pci common soft state structure to determine if one node from the
+ * pair has been attached.
+ */
+struct pci_common {
+	uint_t pci_common_id;
+
+	/* pointers & counters to facilitate attach/detach & suspend/resume */
+	ushort_t pci_common_refcnt;	/* # of sides suspended + attached */
+	ushort_t pci_common_attachcnt;	/* # of sides attached */
+	uint16_t pci_common_tsb_cookie;	/* IOMMU TSB allocation */
+	pci_t *pci_p[2];		/* pci soft states of both sides */
+
+	uint32_t pci_chip_id;		/* Bus bridge chip identification */
+
+	/* Links to functional blocks potentially shared between pci nodes */
+	iommu_t *pci_common_iommu_p;
+	cb_t *pci_common_cb_p;
+	ib_t *pci_common_ib_p;
+	ecc_t *pci_common_ecc_p;
+
+	/*
+	 * Performance counters kstat.
+	 */
+	pci_cntr_pa_t	pci_cmn_uks_pa;
+	kstat_t	*pci_common_uksp;	/* ptr to upstream kstat */
+	kmutex_t pci_fm_mutex;		/* per chip error handling mutex */
+};
+
+/*
+ * pci soft state structure:
+ *
+ * Each pci node has a pci soft state structure.
+ */
+struct pci {
+	/*
+	 * State flags and mutex:
+	 */
+	pci_state_t pci_state;
+	uint_t pci_soft_state;
+#define	PCI_SOFT_STATE_OPEN		0x01
+#define	PCI_SOFT_STATE_OPEN_EXCL	0x02
+#define	PCI_SOFT_STATE_CLOSED		0x04
+	uint_t pci_open_count;
+	uint16_t pci_tsb_cookie;	/* IOMMU TSB allocation */
+	kmutex_t pci_mutex;
+
+	/*
+	 * Links to other state structures:
+	 */
+	pci_common_t *pci_common_p;	/* pointer common soft state */
+	dev_info_t *pci_dip;		/* devinfo structure */
+	ib_t *pci_ib_p;			/* interrupt block */
+	cb_t *pci_cb_p;			/* control block */
+	pbm_t *pci_pbm_p;		/* PBM block */
+	iommu_t	*pci_iommu_p;		/* IOMMU block */
+	sc_t *pci_sc_p;			/* streaming cache block */
+	ecc_t *pci_ecc_p;		/* ECC error block */
+
+	/*
+	 * other state info:
+	 */
+	uint_t pci_id;			/* UPA (or Safari) device id */
+	pci_side_t pci_side;
+
+	/*
+	 * pci device node properties:
+	 */
+	pci_bus_range_t pci_bus_range;	/* "bus-range" */
+	pci_ranges_t *pci_ranges;	/* "ranges" data & length */
+	int pci_ranges_length;
+	uint32_t *pci_inos;		/* inos from "interrupts" prop */
+	int pci_inos_len;		/* "interrupts" length */
+	int pci_numproxy;		/* upa interrupt proxies */
+	int pci_thermal_interrupt;	/* node has thermal interrupt */
+
+	/*
+	 * register mapping:
+	 */
+	caddr_t pci_address[4];
+	ddi_acc_handle_t pci_ac[4];
+
+	/* Interrupt support */
+	int intr_map_size;
+	struct intr_map *intr_map;
+	struct intr_map_mask *intr_map_mask;
+
+	/* performance counters */
+	pci_cntr_addr_t	pci_ks_addr;
+	kstat_t	*pci_ksp;
+
+	/* Hotplug information */
+
+	boolean_t	hotplug_capable;
+
+	/* Fault Management support */
+	int pci_fm_cap;
+	ddi_iblock_cookie_t pci_fm_ibc;
+};
+
+/*
+ * PSYCHO and PBM soft state macros:
+ */
+#define	get_pci_soft_state(i)	\
+	((pci_t *)ddi_get_soft_state(per_pci_state, (i)))
+
+#define	alloc_pci_soft_state(i)	\
+	ddi_soft_state_zalloc(per_pci_state, (i))
+
+#define	free_pci_soft_state(i)	\
+	ddi_soft_state_free(per_pci_state, (i))
+
+#define	get_pci_common_soft_state(i)	\
+	((pci_common_t *)ddi_get_soft_state(per_pci_common_state, (i)))
+
+#define	alloc_pci_common_soft_state(i)	\
+	ddi_soft_state_zalloc(per_pci_common_state, (i))
+
+#define	free_pci_common_soft_state(i)	\
+	ddi_soft_state_free(per_pci_common_state, (i))
+
+#define	DEV_TO_SOFTSTATE(dev)	((pci_t *)ddi_get_soft_state(per_pci_state, \
+	PCIHP_AP_MINOR_NUM_TO_INSTANCE(getminor(dev))))
+
+extern void *per_pci_state;		/* per-pbm soft state pointer */
+extern void *per_pci_common_state;	/* per-psycho soft state pointer */
+extern kmutex_t pci_global_mutex;	/* attach/detach common struct lock */
+extern kmutex_t dvma_active_list_mutex;
+
+/*
+ * function prototypes for bus ops routines:
+ */
+extern int
+pci_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
+	off_t offset, off_t len, caddr_t *addrp);
+extern int
+pci_dma_setup(dev_info_t *dip, dev_info_t *rdip,
+	ddi_dma_req_t *dmareq, ddi_dma_handle_t *handlep);
+extern int
+pci_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp,
+	int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep);
+extern int
+pci_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip,
+	ddi_dma_handle_t handle, ddi_dma_req_t *dmareq,
+	ddi_dma_cookie_t *cookiep, uint_t *ccountp);
+extern int
+pci_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip,
+	ddi_dma_handle_t handle);
+extern int
+pci_dma_flush(dev_info_t *dip, dev_info_t *rdip,
+	ddi_dma_handle_t handle, off_t off, size_t len,
+	uint_t cache_flags);
+extern int
+pci_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
+	enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp,
+	uint_t cache_flags);
+extern int
+pci_ctlops(dev_info_t *dip, dev_info_t *rdip,
+	ddi_ctl_enum_t op, void *arg, void *result);
+extern int
+pci_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
+	ddi_intr_handle_impl_t *handle, void *result);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_VAR_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pcipsy.h b/usr/src/uts/sun4u/sys/pci/pcipsy.h
new file mode 100644
index 0000000000..e46c147f48
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pcipsy.h
@@ -0,0 +1,181 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_PCIPSY_H
+#define	_SYS_PCIPSY_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Performance counters information.
+ */
+#define	PSYCHO_SHIFT_PIC0	8
+#define	PSYCHO_SHIFT_PIC1	0
+
+/*
+ * Psycho-specific register offsets & bit field positions.
+ */
+
+/*
+ * Offsets of global registers:
+ */
+#define	PSYCHO_CB_DEVICE_ID_REG_OFFSET		0x00000000
+#define	PSYCHO_CB_CONTROL_STATUS_REG_OFFSET	0x00000010
+
+/*
+ * psycho performance counters offsets.
+ */
+#define	PSYCHO_PERF_PCR_OFFSET			0x00000100
+#define	PSYCHO_PERF_PIC_OFFSET			0x00000108
+
+/*
+ * Offsets of registers in the interrupt block:
+ */
+#define	PSYCHO_IB_SLOT_INTR_MAP_REG_OFFSET	0x00000C00
+#define	PSYCHO_IB_OBIO_INTR_MAP_REG_OFFSET	0x00001000
+#define	PSYCHO_IB_OBIO_CLEAR_INTR_REG_OFFSET	0x00001800
+
+/*
+ * Offsets of registers in the PBM block:
+ */
+#define	PSYCHO_PCI_PBM_REG_BASE			0x00002000
+#define	PSYCHO_PCI_CTRL_REG_OFFSET		0x00000000
+#define	PSYCHO_PCI_ASYNC_FLT_STATUS_REG_OFFSET	0x00000010
+#define	PSYCHO_PCI_ASYNC_FLT_ADDR_REG_OFFSET	0x00000018
+#define	PSYCHO_PCI_DIAG_REG_OFFSET		0x00000020
+
+/*
+ * Offsets of registers in the streaming cache block:
+ */
+#define	PSYCHO_SC_CTRL_REG_OFFSET		0x00000800
+#define	PSYCHO_SC_INVL_REG_OFFSET		0x00000808
+#define	PSYCHO_SC_SYNC_REG_OFFSET		0x00000810
+#define	PSYCHO_SC_A_DATA_DIAG_OFFSET		0x0000b000
+#define	PSYCHO_SC_A_TAG_DIAG_OFFSET		0x0000b800
+#define	PSYCHO_SC_A_LTAG_DIAG_OFFSET		0x0000b900
+#define	PSYCHO_SC_B_DATA_DIAG_OFFSET		0x0000c000
+#define	PSYCHO_SC_B_TAG_DIAG_OFFSET		0x0000c800
+#define	PSYCHO_SC_B_LTAG_DIAG_OFFSET		0x0000c900
+
+/*
+ * Address space offsets and sizes:
+ */
+#define	PSYCHO_PCI_CONFIG			0x001000000ull
+#define	PSYCHO_PCI_A_IO				0x002000000ull
+#define	PSYCHO_PCI_B_IO				0x002010000ull
+#define	PSYCHO_PCI_A_MEMORY			0x100000000ull
+#define	PSYCHO_PCI_B_MEMORY			0x180000000ull
+#define	PSYCHO_PCI_IO_SIZE			0x000010000ull
+#define	PSYCHO_PCI_MEM_SIZE			0x080000000ull
+
+/*
+ * psycho control register bit definitions:
+ */
+#define	PSYCHO_CB_CONTROL_STATUS_MODE		0x0000000000000001ull
+#define	PSYCHO_CB_CONTROL_STATUS_IMPL		0xf000000000000000ull
+#define	PSYCHO_CB_CONTROL_STATUS_IMPL_SHIFT	60
+#define	PSYCHO_CB_CONTROL_STATUS_VER		0x0f00000000000000ull
+#define	PSYCHO_CB_CONTROL_STATUS_VER_SHIFT	56
+
+/*
+ * psycho ECC UE AFSR bit definitions:
+ */
+#define	PSYCHO_ECC_UE_AFSR_BYTEMASK		0x0000ffff00000000ull
+#define	PSYCHO_ECC_UE_AFSR_BYTEMASK_SHIFT	32
+#define	PSYCHO_ECC_UE_AFSR_DW_OFFSET		0x00000000e0000000ull
+#define	PSYCHO_ECC_UE_AFSR_DW_OFFSET_SHIFT	29
+#define	PSYCHO_ECC_UE_AFSR_ID			0x000000001f000000ull
+#define	PSYCHO_ECC_UE_AFSR_ID_SHIFT		24
+#define	PSYCHO_ECC_UE_AFSR_BLK			0x0000000000800000ull
+
+/*
+ * psycho ECC CE AFSR bit definitions:
+ */
+#define	PSYCHO_ECC_CE_AFSR_SYND			0x00ff000000000000ull
+#define	PSYCHO_ECC_CE_AFSR_SYND_SHIFT		48
+#define	PSYCHO_ECC_CE_AFSR_BYTEMASK		0x0000ffff00000000ull
+#define	PSYCHO_ECC_CE_AFSR_BYTEMASK_SHIFT	32
+#define	PSYCHO_ECC_CE_AFSR_DW_OFFSET		0x00000000e0000000ull
+#define	PSYCHO_ECC_CE_AFSR_DW_OFFSET_SHIFT	29
+#define	PSYCHO_ECC_CE_AFSR_UPA_MID		0x000000001f000000ull
+#define	PSYCHO_ECC_CE_AFSR_UPA_MID_SHIFT	24
+#define	PSYCHO_ECC_CE_AFSR_BLK			0x0000000000800000ull
+
+/*
+ * psycho pci control register bits:
+ */
+#define	PSYCHO_PCI_CTRL_ARB_PARK		0x0000000000200000ull
+#define	PSYCHO_PCI_CTRL_SBH_INT_EN		0x0000000000000400ull
+#define	PSYCHO_PCI_CTRL_WAKEUP_EN		0x0000000000000200ull
+#define	PSYCHO_PCI_CTRL_ERR_INT_EN		0x0000000000000100ull
+#define	PSYCHO_PCI_CTRL_ARB_EN_MASK		0x000000000000000full
+
+/*
+ * psycho PCI asynchronous fault status register bit definitions:
+ */
+#define	PSYCHO_PCI_AFSR_PE_SHIFT		60
+#define	PSYCHO_PCI_AFSR_SE_SHIFT		56
+#define	PSYCHO_PCI_AFSR_E_MA			0x0000000000000008ull
+#define	PSYCHO_PCI_AFSR_E_TA			0x0000000000000004ull
+#define	PSYCHO_PCI_AFSR_E_RTRY			0x0000000000000002ull
+#define	PSYCHO_PCI_AFSR_E_PERR			0x0000000000000001ull
+#define	PSYCHO_PCI_AFSR_E_MASK			0x000000000000000full
+#define	PSYCHO_PCI_AFSR_BYTEMASK		0x0000ffff00000000ull
+#define	PSYCHO_PCI_AFSR_BYTEMASK_SHIFT		32
+#define	PSYCHO_PCI_AFSR_BLK			0x0000000080000000ull
+#define	PSYCHO_PCI_AFSR_MID			0x000000003e000000ull
+#define	PSYCHO_PCI_AFSR_MID_SHIFT		25
+
+/*
+ * psycho PCI diagnostic register bit definitions:
+ */
+#define	PSYCHO_PCI_DIAG_DIS_DWSYNC		0x0000000000000010ull
+
+#define	PBM_AFSR_TO_PRIERR(afsr)	\
+	(afsr >> PSYCHO_PCI_AFSR_PE_SHIFT & PSYCHO_PCI_AFSR_E_MASK)
+#define	PBM_AFSR_TO_SECERR(afsr)	\
+	(afsr >> PSYCHO_PCI_AFSR_SE_SHIFT & PSYCHO_PCI_AFSR_E_MASK)
+#define	PBM_AFSR_TO_BYTEMASK(afsr)	\
+	((afsr & PSYCHO_PCI_AFSR_BYTEMASK) >> PSYCHO_PCI_AFSR_BYTEMASK_SHIFT)
+
+#define	PCI_BRIDGE_TYPE(cmn_p) PCI_PSYCHO
+/*
+ * for sabre
+ */
+#define	DMA_WRITE_SYNC_REG			0x1C20
+
+extern uint_t cb_thermal_intr(caddr_t a);
+
+#define	PCI_ID_TO_IGN(pci_id)		((pci_ign_t)UPAID_TO_IGN(pci_id))
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCIPSY_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pcisch.h b/usr/src/uts/sun4u/sys/pci/pcisch.h
new file mode 100644
index 0000000000..58c6b799ed
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pcisch.h
@@ -0,0 +1,548 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_PCISCH_H
+#define	_SYS_PCISCH_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Performance counters information.
+ */
+#define	SCHIZO_SHIFT_PIC0	4
+#define	SCHIZO_SHIFT_PIC1	11
+
+/*
+ * Schizo-specific register offsets & bit field positions.
+ */
+
+/*
+ * [msb]				[lsb]
+ * 0x00 <chip_type> <version#> <module-revision#>
+ */
+#define	SCHIZO_VER_10		CHIP_ID(PCI_CHIP_SCHIZO, 0x00, 0x00)
+#define	SCHIZO_VER_20		CHIP_ID(PCI_CHIP_SCHIZO, 0x02, 0x00)
+#define	SCHIZO_VER_21		CHIP_ID(PCI_CHIP_SCHIZO, 0x03, 0x00)
+#define	SCHIZO_VER_22		CHIP_ID(PCI_CHIP_SCHIZO, 0x04, 0x00)
+#define	SCHIZO_VER_23		CHIP_ID(PCI_CHIP_SCHIZO, 0x05, 0x00)
+#define	SCHIZO_VER_24		CHIP_ID(PCI_CHIP_SCHIZO, 0x06, 0x00)
+#define	SCHIZO_VER_25		CHIP_ID(PCI_CHIP_SCHIZO, 0x07, 0x00)
+#define	XMITS_VER_10		CHIP_ID(PCI_CHIP_XMITS, 0x05, 0x01)
+#define	XMITS_VER_21		CHIP_ID(PCI_CHIP_XMITS, 0x05, 0x03)
+#define	XMITS_VER_30		CHIP_ID(PCI_CHIP_XMITS, 0x05, 0x04)
+#define	TOMATILLO_VER_10	CHIP_ID(PCI_CHIP_TOMATILLO, 0x00, 0x00)
+#define	TOMATILLO_VER_20	CHIP_ID(PCI_CHIP_TOMATILLO, 0x01, 0x00)
+#define	TOMATILLO_VER_21	CHIP_ID(PCI_CHIP_TOMATILLO, 0x02, 0x00)
+#define	TOMATILLO_VER_22	CHIP_ID(PCI_CHIP_TOMATILLO, 0x03, 0x00)
+#define	TOMATILLO_VER_23	CHIP_ID(PCI_CHIP_TOMATILLO, 0x04, 0x00)
+#define	TOMATILLO_VER_24	CHIP_ID(PCI_CHIP_TOMATILLO, 0X05, 0X00)
+
+/*
+ * Offsets of Control Block registers ("reg" property 2nd entry)
+ */
+#define	SCHIZO_CB_CSR_OFFSET			0x0	/* reg 1 */
+#define	SCHIZO_CB_ERRCTRL_OFFSET		0x8
+#define	SCHIZO_CB_INTCTRL_OFFSET		0x10
+#define	SCHIZO_CB_ERRLOG_OFFSET			0x18
+#define	SCHIZO_CB_ECCCTRL_OFFSET		0x20
+#define	SCHIZO_CB_UEAFSR_OFFSET			0x30
+#define	SCHIZO_CB_UEAFAR_OFFSET			0x38
+#define	SCHIZO_CB_CEAFSR_OFFSET			0x40
+#define	SCHIZO_CB_CEAFAR_OFFSET			0x48
+#define	SCHIZO_CB_ESTRCTRL_OFFSET		0x50
+#define	XMITS_CB_SOFT_PAUSE_OFFSET		0x58
+#define	XMITS_CB_IO_LOOPBACK_CONTROL_OFFSET	0x60
+#define	XMITS_CB_SAF_PED_CONTROL_OFFSET		0x68
+#define	XMITS_CB_SAF_PED_LOG_OFFSET		0x70
+#define	XMITS_CB_SAF_PAR_INJECT_IMM_OFFSET	0x78
+#define	XMITS_CB_SAF_PAR_INJECT_1_OFFSET	0x80
+#define	XMITS_CB_SAF_PAR_INJECT_0_OFFSET	0x88
+#define	XMITS_CB_FIRST_ERROR_LOG		0x90
+#define	XMITS_CB_FIRST_ERROR_ADDR		0x98
+#define	XMITS_CB_PCI_LEAF_STATUS		0xA0
+
+/*
+ * Tomatillo only bits in IOMMU control registers.
+ */
+#define	TOMATILLO_IOMMU_SEG_DISP_SHIFT		4
+#define	TOMATILLO_IOMMU_TSB_MAX			7
+#define	TOMATIILO_IOMMU_ERR_REG_SHIFT		24
+#define	TOMATILLO_IOMMU_ERRSTS_SHIFT		25
+#define	TOMATILLO_IOMMU_ERR			(1ull << 24)
+#define	TOMATILLO_IOMMU_ERRSTS			(3ull << 25)
+#define	TOMATILLO_IOMMU_ERR_ILLTSBTBW		(1ull << 27)
+#define	TOMATILLO_IOMMU_ERR_BAD_VA		(1ull << 28)
+
+#define	TOMATILLO_IOMMU_PROTECTION_ERR		0x0
+#define	TOMATILLO_IOMMU_INVALID_ERR		0x1
+#define	TOMATILLO_IOMMU_TIMEOUT_ERR		0x2
+#define	TOMATILLO_IOMMU_ECC_ERR			0x3
+
+/*
+ * Offsets of performance monitoring registers.
+ */
+#define	SCHIZO_PERF_PCI_PCR_OFFSET		0x00000100
+#define	SCHIZO_PERF_PCI_PIC_OFFSET		0x00000108
+#define	SCHIZO_PERF_PCI_ICD_OFFSET		0x00000110
+#define	SCHIZO_PERF_SAF_PCR_OFFSET		0x00007000
+#define	SCHIZO_PERF_SAF_PIC_OFFSET		0x00007008
+
+/*
+ * Offsets of registers in the PBM block:
+ */
+#define	SCHIZO_PCI_CTRL_REG_OFFSET		0x2000
+#define	SCHIZO_PCI_ASYNC_FLT_STATUS_REG_OFFSET	0x2010
+#define	SCHIZO_PCI_ASYNC_FLT_ADDR_REG_OFFSET	0x2018
+#define	SCHIZO_PCI_DIAG_REG_OFFSET		0x2020
+#define	SCHIZO_PCI_ESTAR_REG_OFFSET		0x2028
+#define	TOMATILLO_TGT_ADDR_SPACE_OFFSET		0x2490
+#define	TOMATILLO_TGT_ERR_VALOG_OFFSET		0x2498
+
+#define	XMITS10_PCI_X_ERROR_STATUS_REG_OFFSET	0x2030
+#define	XMITS10_PCI_X_DIAG_REG_OFFSET		0x2038
+#define	XMITS_PCI_X_ERROR_STATUS_REG_OFFSET	0x2300
+#define	XMITS_PCI_X_DIAG_REG_OFFSET		0x2308
+#define	XMITS_PARITY_DETECT_REG_OFFSET		0x2040
+#define	XMITS_PARITY_LOG_REG_OFFSET		0x2048
+#define	XMITS_PARITY_INJECT_REG_OFFSET		0x2050
+#define	XMITS_PARITY_INJECT_1_REG_OFFSET	0x2058
+#define	XMITS_PARITY_INJECT_0_REG_OFFSET	0x2060
+
+/*
+ * Offsets of IO Cache Registers:
+ */
+#define	TOMATILLO_IOC_CSR_OFF			0x2248
+#define	TOMATILLO_IOC_TAG_OFF			0x2250
+#define	TOMATIILO_IOC_DAT_OFF			0x2290
+
+/*
+ * Offsets of registers in the iommu block:
+ */
+#define	SCHIZO_IOMMU_FLUSH_CTX_REG_OFFSET	0x00000218
+#define	TOMATILLO_IOMMU_ERR_TFAR_OFFSET		0x0220
+
+/*
+ * Offsets of registers in the streaming cache block:
+ */
+#define	SCHIZO_SC_CTRL_REG_OFFSET		0x00002800
+#define	SCHIZO_SC_INVL_REG_OFFSET		0x00002808
+#define	SCHIZO_SC_SYNC_REG_OFFSET		0x00002810
+#define	SCHIZO_SC_CTX_INVL_REG_OFFSET		0x00002818
+#define	SCHIZO_SC_CTX_MATCH_REG_OFFSET		0x00010000
+#define	SCHIZO_SC_DATA_DIAG_OFFSET		0x0000b000
+#define	SCHIZO_SC_TAG_DIAG_OFFSET		0x0000ba00
+#define	SCHIZO_SC_LTAG_DIAG_OFFSET		0x0000bb00
+
+/*
+ * MAX_PRF when enabled will always prefetch the max of 8
+ * prefetches if possible.
+ */
+#define	XMITS_SC_MAX_PRF			(0x1ull << 7)
+
+/*
+ * Offsets of registers in the PCI Idle Check Diagnostics Register.
+ */
+#define	SCHIZO_PERF_PCI_ICD_DMAW_PARITY_INT_ENABLE	0x4000
+#define	SCHIZO_PERF_PCI_ICD_PCI_2_0_COMPATIBLE		0x8000
+
+/*
+ * Offsets of registers in the interrupt block:
+ */
+#define	SCHIZO_IB_SLOT_INTR_MAP_REG_OFFSET	0x1100
+#define	SCHIZO_IB_INTR_MAP_REG_OFFSET		0x1000
+#define	SCHIZO_IB_CLEAR_INTR_REG_OFFSET		0x1400
+#define	SCHIZO_PBM_DMA_SYNC_REG_OFFSET		0x1A08
+#define	PBM_DMA_SYNC_COMP_REG_OFFSET		0x1A10
+#define	PBM_DMA_SYNC_PEND_REG_OFFSET		0x1A18
+
+/*
+ * Address space offsets and sizes:
+ */
+#define	SCHIZO_SIZE				0x0000800000000000ull
+
+/*
+ * Schizo-specific fields of interrupt mapping register:
+ */
+#define	SCHIZO_INTR_MAP_REG_NID			0x0000000003E00000ull
+#define	SCHIZO_INTR_MAP_REG_NID_SHIFT		21
+
+/*
+ * schizo ECC UE AFSR bit definitions:
+ */
+#define	SCHIZO_ECC_UE_AFSR_ERRPNDG		0x0300000000000000ull
+#define	SCHIZO_ECC_UE_AFSR_MASK			0x000003ff00000000ull
+#define	SCHIZO_ECC_UE_AFSR_MASK_SHIFT		32
+#define	SCHIZO_ECC_UE_AFSR_QW_OFFSET		0x00000000C0000000ull
+#define	SCHIZO_ECC_UE_AFSR_QW_OFFSET_SHIFT	30
+#define	SCHIZO_ECC_UE_AFSR_AGENT_MID		0x000000001f000000ull
+#define	SCHIZO_ECC_UE_AFSR_AGENT_MID_SHIFT	24
+#define	SCHIZO_ECC_UE_AFSR_PARTIAL		0x0000000000800000ull
+#define	SCHIZO_ECC_UE_AFSR_OWNED_IN		0x0000000000400000ull
+#define	SCHIZO_ECC_UE_AFSR_MTAG_SYND		0x00000000000f0000ull
+#define	SCHIZO_ECC_UE_AFSR_MTAG_SYND_SHIFT	16
+#define	SCHIZO_ECC_UE_AFSR_MTAG			0x000000000000e000ull
+#define	SCHIZO_ECC_UE_AFSR_MTAG_SHIFT		13
+#define	SCHIZO_ECC_UE_AFSR_SYND			0x00000000000001ffull
+#define	SCHIZO_ECC_UE_AFSR_SYND_SHIFT		0
+
+/*
+ * schizo ECC CE AFSR bit definitions:
+ */
+#define	SCHIZO_ECC_CE_AFSR_ERRPNDG		0x0300000000000000ull
+#define	SCHIZO_ECC_CE_AFSR_MASK			0x000003ff00000000ull
+#define	SCHIZO_ECC_CE_AFSR_MASK_SHIFT		32
+#define	SCHIZO_ECC_CE_AFSR_QW_OFFSET		0x00000000C0000000ull
+#define	SCHIZO_ECC_CE_AFSR_QW_OFFSET_SHIFT	30
+#define	SCHIZO_ECC_CE_AFSR_AGENT_MID		0x000000001f000000ull
+#define	SCHIZO_ECC_CE_AFSR_AGENT_MID_SHIFT	24
+#define	SCHIZO_ECC_CE_AFSR_PARTIAL		0x0000000000800000ull
+#define	SCHIZO_ECC_CE_AFSR_OWNED_IN		0x0000000000400000ull
+#define	SCHIZO_ECC_CE_AFSR_MTAG_SYND		0x00000000000f0000ull
+#define	SCHIZO_ECC_CE_AFSR_MTAG_SYND_SHIFT	16
+#define	SCHIZO_ECC_CE_AFSR_MTAG			0x000000000000e000ull
+#define	SCHIZO_ECC_CE_AFSR_MTAG_SHIFT		13
+#define	SCHIZO_ECC_CE_AFSR_SYND			0x00000000000001ffull
+#define	SCHIZO_ECC_CE_AFSR_SYND_SHIFT		0
+
+/*
+ * schizo ECC UE/CE AFAR bit definitions:
+ */
+#define	SCHIZO_ECC_AFAR_IO_TXN			0x0000080000000000ull
+#define	SCHIZO_ECC_AFAR_PIOW_MASK		0x0000078000000000ull
+#define	SCHIZO_ECC_AFAR_PIOW_UPA64S		0x0000078000000000ull
+#define	SCHIZO_ECC_AFAR_PIOW_NL_REG		0x0000040000000000ull
+#define	SCHIZO_ECC_AFAR_PIOW_NL			0x0000050000000000ull
+#define	SCHIZO_ECC_AFAR_PIOW_NL_ALT		0x0000051000000000ull
+#define	SCHIZO_ECC_AFAR_PIOW_PCIA_REG		0x0000020000000000ull
+#define	SCHIZO_ECC_AFAR_PIOW_PCIA_MEM		0x0000030000000000ull
+#define	SCHIZO_ECC_AFAR_PIOW_PCIA_CFGIO		0x0000031000000000ull
+#define	SCHIZO_ECC_AFAR_PIOW_PCIB_REG		0x0000000000000000ull
+#define	SCHIZO_ECC_AFAR_PIOW_PCIB_MEM		0x0000010000000000ull
+#define	SCHIZO_ECC_AFAR_PIOW_PCIB_CFGIO		0x0000011000000000ull
+#define	SCHIZO_ECC_AFAR_PIOW_SAFARI_REGS	0x0000060000000000ull
+#define	SCHIZO_ECC_AFAR_PIOW_ADDR_MASK		0x0000000fffffffffull
+#define	SCHIZO_ECC_AFAR_ADDR_MASK		0x000007ffffffffffull
+
+/*
+ * schizo pci control register bits:
+ */
+#define	SCHIZO_PCI_CTRL_BUS_UNUSABLE		(1ull << 63)
+#define	TOMATILLO_PCI_CTRL_PCI_DTO_ERR		(1ull << 62)
+#define	TOMATILLO_PCI_CTRL_DTO_INT_EN		(1ull << 61)
+#define	SCHIZO_PCI_CTRL_ERR_SLOT_LOCK		(1ull << 51)
+#define	SCHIZO_PCI_CTRL_ERR_SLOT		(7ull << 48)
+#define	SCHIZO_PCI_CTRL_ERR_SLOT_SHIFT		48
+#define	SCHIZO_PCI_CTRL_PCI_TTO_ERR		(1ull << 38)
+#define	SCHIZO_PCI_CTRL_PCI_RTRY_ERR		(1ull << 37)
+#define	SCHIZO_PCI_CTRL_PCI_MMU_ERR		(1ull << 36)
+#define	TOMATILLO_PCI_CTRL_PEN_RD_MLTPL		(1ull << 30)
+#define	TOMATILLO_PCI_CTRL_PEN_RD_ONE		(1ull << 29)
+#define	TOMATILLO_PCI_CTRL_PEN_RD_LINE		(1ull << 28)
+#define	TOMATILLO_PCI_CTRL_FRC_TRGT_ABRT	(1ull << 27)
+#define	TOMATILLO_PCI_CTRL_FRC_TRGT_RTRY	(1ull << 26)
+#define	SCHIZO_PCI_CTRL_PTO			(3ull << 24)
+#define	SCHIZO_PCI_CTRL_PTO_SHIFT		24
+#define	TOMATILLO_PCI_CTRL_TRGT_RW_STL_WT	(3ull << 21)
+#define	TOMATILLO_PCI_CTRL_TRGT_RW_STL_WT_SHIFT	21
+#define	SCHIZO_PCI_CTRL_MMU_INT_EN		(1ull << 19)
+#define	SCHIZO_PCI_CTRL_SBH_INT_EN		(1ull << 18)
+#define	SCHIZO_PCI_CTRL_ERR_INT_EN		(1ull << 17)
+#define	SCHIZO_PCI_CTRL_ARB_PARK		(1ull << 16)
+#define	SCHIZO_PCI_CTRL_RST			(1ull << 8)
+#define	SCHIZO_PCI_CTRL_ARB_EN_MASK		0xffull
+
+#define	XMITS10_PCI_CTRL_ARB_EN_MASK		0x0full
+#define	XMITS_PCI_CTRL_X_MODE			(0x1ull << 32)
+#define	XMITS_PCI_CTRL_X_ERRINT_EN		(0x1ull << 20)
+#define	XMITS_PCI_CTRL_DMA_WR_PERR		(0x1ull << 51)
+
+/*
+ * schizo PCI asynchronous fault status register bit definitions:
+ */
+#define	SCHIZO_PCI_AFSR_PE_SHIFT		58
+#define	SCHIZO_PCI_AFSR_SE_SHIFT		52
+#define	SCHIZO_PCI_AFSR_E_MA			0x0000000000000020ull
+#define	SCHIZO_PCI_AFSR_E_TA			0x0000000000000010ull
+#define	SCHIZO_PCI_AFSR_E_RTRY			0x0000000000000008ull
+#define	SCHIZO_PCI_AFSR_E_PERR			0x0000000000000004ull
+#define	SCHIZO_PCI_AFSR_E_TTO			0x0000000000000002ull
+#define	SCHIZO_PCI_AFSR_E_UNUSABLE		0x0000000000000001ull
+#define	SCHIZO_PCI_AFSR_E_MASK			0x000000000000003full
+#define	SCHIZO_PCI_AFSR_DWORDMASK		0x0000030000000000ull
+#define	SCHIZO_PCI_AFSR_DWORDMASK_SHIFT		40
+#define	SCHIZO_PCI_AFSR_BYTEMASK		0x000000ff00000000ull
+#define	SCHIZO_PCI_AFSR_BYTEMASK_SHIFT		32
+#define	SCHIZO_PCI_AFSR_BLK			0x0000000080000000ull
+#define	SCHIZO_PCI_AFSR_CONF_SPACE		0x0000000040000000ull
+#define	SCHIZO_PCI_AFSR_MEM_SPACE		0x0000000020000000ull
+#define	SCHIZO_PCI_AFSR_IO_SPACE		0x0000000010000000ull
+
+/* Schizo/Xmits control block Safari Error log bits */
+#define	SCHIZO_CB_ELOG_BAD_CMD			(0x1ull << 62)
+#define	SCHIZO_CB_ELOG_SSM_DIS			(0x1ull << 61)
+#define	SCHIZO_CB_ELOG_BAD_CMD_PCIA		(0x1ull << 60)
+#define	SCHIZO_CB_ELOG_BAD_CMD_PCIB		(0x1ull << 59)
+#define	XMITS_CB_ELOG_PAR_ERR_INT_PCIB		(0x1ull << 19)
+#define	XMITS_CB_ELOG_PAR_ERR_INT_PCIA		(0x1ull << 18)
+#define	XMITS_CB_ELOG_PAR_ERR_INT_SAF		(0x1ull << 17)
+#define	XMITS_CB_ELOG_PLL_ERR_PCIB		(0x1ull << 16)
+#define	XMITS_CB_ELOG_PLL_ERR_PCIA		(0x1ull << 15)
+#define	XMITS_CB_ELOG_PLL_ERR_SAF		(0x1ull << 14)
+#define	SCHIZO_CB_ELOG_CPU1_PAR_SINGLE		(0x1ull << 13)
+#define	SCHIZO_CB_ELOG_CPU1_PAR_BIDI		(0x1ull << 12)
+#define	SCHIZO_CB_ELOG_CPU0_PAR_SINGLE		(0x1ull << 11)
+#define	SCHIZO_CB_ELOG_CPU0_PAR_BIDI		(0x1ull << 10)
+#define	SCHIZO_CB_ELOG_SAF_CIQ_TO		(0x1ull << 9)
+#define	SCHIZO_CB_ELOG_SAF_LPQ_TO		(0x1ull << 8)
+#define	SCHIZO_CB_ELOG_SAF_SFPQ_TO		(0x1ull << 7)
+#define	SCHIZO_CB_ELOG_SAF_UFPQ_TO		(0x1ull << 6)
+#define	SCHIZO_CB_ELOG_ADDR_PAR_ERR		(0x1ull << 5)
+#define	SCHIZO_CB_ELOG_UNMAP_ERR		(0x1ull << 4)
+#define	SCHIZO_CB_ELOG_BUS_ERR			(0x1ull << 2)
+#define	SCHIZO_CB_ELOG_TO_ERR			(0x1ull << 1)
+#define	SCHIZO_CB_ELOG_DSTAT_ERR		0x1ull
+
+/* Used for the tomatillo micro tlb bug. errata #82 */
+#define	SCHIZO_VPN_MASK			((1 << 19) - 1)
+
+/* Tomatillo control block JBUS error log bits */
+#define	TOMATILLO_CB_ELOG_SNOOP_ERR_GR		(0x1ull << 21)
+#define	TOMATILLO_CB_ELOG_SNOOP_ERR_PCI		(0x1ull << 20)
+#define	TOMATILLO_CB_ELOG_SNOOP_ERR_RD		(0x1ull << 19)
+#define	TOMATILLO_CB_ELOG_SNOOP_ERR_RDS		(0x1ull << 17)
+#define	TOMATILLO_CB_ELOG_SNOOP_ERR_RDSA	(0x1ull << 16)
+#define	TOMATILLO_CB_ELOG_SNOOP_ERR_OWN		(0x1ull << 15)
+#define	TOMATILLO_CB_ELOG_SNOOP_ERR_RDO		(0x1ull << 14)
+#define	TOMATILLO_CB_ELOG_WR_DATA_PAR_ERR	(0x1ull << 13)
+#define	TOMATILLO_CB_ELOG_CTL_PAR_ERR		(0x1ull << 12)
+#define	TOMATILLO_CB_ELOG_SNOOP_ERR		(0x1ull << 11)
+#define	TOMATILLO_CB_ELOG_ILL_BYTE_EN		(0x1ull << 10)
+#define	TOMATILLO_CB_ELOG_ILL_COH_IN		(0x1ull << 8)
+#define	TOMATILLO_CB_ELOG_RD_DATA_PAR_ERR	(0x1ull << 6)
+#define	TOMATILLO_CB_ELOG_TO_EXP_ERR		(0x1ull << 3)
+
+/* Tomatillo control block JBUS control/status bits */
+#define	TOMATILLO_CB_CSR_CTRL_PERR_GEN		(0x1ull << 29)
+
+#define	XMITS_PCI_X_AFSR_P_SC_ERR		(0x1ull << 51)
+#define	XMITS_PCI_X_AFSR_S_SC_ERR		(0x1ull << 50)
+
+#define	XMITS_PCIX_MSG_CLASS_MASK		0xf00
+#define	XMITS_PCIX_MSG_INDEX_MASK		0xff
+#define	XMITS_PCIX_MSG_MASK	\
+		(XMITS_PCIX_MSG_CLASS_MASK | XMITS_PCIX_MSG_INDEX_MASK)
+
+#define	XMITS_PCI_X_P_MSG_SHIFT			16
+#define	XMITS_PCI_X_S_MSG_SHIFT			4
+
+#define	PBM_AFSR_TO_PRIERR(afsr)	\
+	(afsr >> SCHIZO_PCI_AFSR_PE_SHIFT & SCHIZO_PCI_AFSR_E_MASK)
+#define	PBM_AFSR_TO_SECERR(afsr)	\
+	(afsr >> SCHIZO_PCI_AFSR_SE_SHIFT & SCHIZO_PCI_AFSR_E_MASK)
+#define	PBM_AFSR_TO_BYTEMASK(afsr)	\
+	((afsr & SCHIZO_PCI_AFSR_BYTEMASK) >> SCHIZO_PCI_AFSR_BYTEMASK_SHIFT)
+#define	PBM_AFSR_TO_DWORDMASK(afsr)	\
+	((afsr & SCHIZO_PCI_AFSR_DWORDMASK) >>	\
+		SCHIZO_PCI_AFSR_DWORDMASK_SHIFT)
+
+/*
+ * XMITS PCI-X Diagnostic Register bit definitions
+ */
+#define	XMITS_PCI_X_DIAG_DIS_FAIR		(0x1ull << 19)
+#define	XMITS_PCI_X_DIAG_CRCQ_VALID		(0x1ull << 18)
+#define	XMITS_PCI_X_DIAG_SRCQ_VALID_SHIFT	10
+#define	XMITS_PCI_X_DIAG_SRCQ_ONE		(0x1ull << 9)
+#define	XMITS_PCI_X_DIAG_CRCQ_FLUSH		(0x1ull << 8)
+#define	XMITS_PCI_X_DIAG_SRCQ_FLUSH_SHIFT	0
+
+#define	XMITS_PCI_X_DIAG_SRCQ_MASK		0xff
+
+/*
+ * XMITS PCI-X Error Status Register bit definitions
+ */
+
+#define	XMITS_PCI_X_STATUS_PE_SHIFT		58
+#define	XMITS_PCI_X_STATUS_SE_SHIFT		50
+#define	XMITS_PCI_X_STATUS_E_MASK		0x3f
+#define	XMITS_PCI_X_STATUS_PFAR_MASK		0xffffffff
+#define	XMITS_PCIX_STAT_SC_DSCRD		0x20ull
+#define	XMITS_PCIX_STAT_SC_TTO			0x10ull
+#define	XMITS_PCIX_STAT_SMMU			0x8ull
+#define	XMITS_PCIX_STAT_SDSTAT			0x4ull
+#define	XMITS_PCIX_STAT_CMMU			0x2ull
+#define	XMITS_PCIX_STAT_CDSTAT			0x1ull
+#define	XMITS_PCIX_STAT_SERR_ON_PERR		(1ull << 32)
+#define	XMITS_PCIX_STAT_PERR_RECOV_INT_EN	(1ull << 33)
+#define	XMITS_PCIX_STAT_PERR_RECOV_INT		(1ull << 34)
+
+/*
+ * PCI-X Message Classes and Indexes
+ */
+#define	PCIX_CLASS_WRITE_COMPLETION		0x000
+#define	PCIX_WRITE_COMPLETION_NORMAL		0x00
+
+#define	PCIX_CLASS_BRIDGE			0x100
+#define	PCIX_BRIDGE_MASTER_ABORT		0x00
+#define	PCIX_BRIDGE_TARGET_ABORT		0x01
+#define	PCIX_BRIDGE_WRITE_DATA_PARITY		0x02
+
+#define	PCIX_CLASS_CPLT				0x200
+#define	PCIX_CPLT_OUT_OF_RANGE			0x00
+#define	PCIX_CPLT_SPLIT_WRITE_DATA		0x01
+#define	XMITS_CPLT_NO_ERROR			0x80
+#define	XMITS_CPLT_STREAM_DSTAT			0x81
+#define	XMITS_CPLT_STREAM_MMU			0x82
+#define	XMITS_CPLT_CONSIST_DSTAT		0x85
+#define	XMITS_CPLT_CONSIST_MMU			0x86
+
+#define	PCIX_NO_CLASS				0x999
+#define	PCIX_MULTI_ERR	1
+#define	PCIX_SINGLE_ERR	0
+
+#define	PBM_PCIX_TO_PRIERR(pcix_stat)   \
+	(pcix_stat >> XMITS_PCI_X_STATUS_PE_SHIFT & XMITS_PCI_X_STATUS_E_MASK)
+#define	PBM_PCIX_TO_SECERR(pcix_stat)   \
+	(pcix_stat >> XMITS_PCI_X_STATUS_SE_SHIFT & XMITS_PCI_X_STATUS_E_MASK)
+#define	PBM_AFSR_TO_PRISPLIT(afsr)      \
+	((afsr >> XMITS_PCI_X_P_MSG_SHIFT) & XMITS_PCIX_MSG_MASK)
+#define	PBM_AFSR_TO_SECSPLIT(afsr)      \
+	((afsr >> XMITS_PCI_X_S_MSG_SHIFT) & XMITS_PCIX_MSG_MASK)
+
+#define	PCIX_ERRREG_OFFSET (XMITS_PCI_X_ERROR_STATUS_REG_OFFSET -\
+		SCHIZO_PCI_CTRL_REG_OFFSET)
+
+/*
+ * Nested message structure to allow for storing all the PCI-X
+ * split completion messages in tabular form.
+ */
+typedef struct pcix_err_msg_rec {
+	uint32_t msg_key;
+	char	*msg_class;
+	char    *msg_str;
+} pcix_err_msg_rec_t;
+
+typedef struct pcix_err_tbl {
+	uint32_t err_class;
+	uint32_t err_rec_num;
+	pcix_err_msg_rec_t *err_msg_tbl;
+} pcix_err_tbl_t;
+
+
+/*
+ * Tomatillo IO Cache CSR bit definitions:
+ */
+
+#define	TOMATILLO_WRT_PEN		(1ull << 19)
+#define	TOMATILLO_NC_PEN_RD_MLTPL	(1ull << 18)
+#define	TOMATILLO_NC_PEN_RD_ONE		(1ull << 17)
+#define	TOMATILLO_NC_PEN_RD_LINE	(1ull << 16)
+#define	TOMATILLO_PLEN_RD_MTLPL		(3ull << 14)
+#define	TOMATILLO_PLEN_RD_ONE		(3ull << 12)
+#define	TOMATILLO_PLEN_RD_LINE		(3ull << 10)
+#define	TOMATILLO_POFFSET_SHIFT		3
+#define	TOMATILLO_POFFSET		(0x7full << TOMATILLO_POFFSET_SHIFT)
+#define	TOMATILLO_C_PEN_RD_MLTPL	(1ull << 2)
+#define	TOMATILLO_C_PEN_RD_ONE		(1ull << 1)
+#define	TOMATILLO_C_PEN_RD_LINE		(1ull << 0)
+
+/*
+ * schizo PCI diagnostic register bit definitions:
+ */
+#define	SCHIZO_PCI_DIAG_DIS_RTRY_ARB		0x0000000000000080ull
+
+/*
+ * schizo IOMMU TLB TAG diagnostic register bits
+ */
+#define	TLBTAG_CONTEXT_SHIFT		25
+#define	TLBTAG_ERRSTAT_SHIFT		23
+#define	TLBTAG_CONTEXT_BITS		(0xfffull << TLBTAG_CONTEXT_SHIFT)
+#define	TLBTAG_ERRSTAT_BITS		(0x3ull << TLBTAG_ERRSTAT_SHIFT)
+#define	TLBTAG_ERR_BIT			(0x1ull << 22)
+#define	TLBTAG_WRITABLE_BIT		(0x1ull << 21)
+#define	TLBTAG_STREAM_BIT		(0x1ull << 20)
+#define	TLBTAG_PGSIZE_BIT		(0x1ull << 19)
+#define	TLBTAG_PCIVPN_BITS		0x7ffffull
+
+#define	TLBTAG_ERRSTAT_PROT		0
+#define	TLBTAG_ERRSTAT_INVALID		1
+#define	TLBTAG_ERRSTAT_TIMEOUT		2
+#define	TLBTAG_ERRSTAT_ECCUE		3
+
+/*
+ * schizo IOMMU TLB Data RAM diagnostic register bits
+ */
+#define	TLBDATA_VALID_BIT			(0x1ull << 32)
+#define	TLBDATA_CACHE_BIT			(0x1ull << 30)
+#define	TLBDATA_MEMPA_BITS			((0x1ull << 30) - 1)
+
+extern uint_t cb_buserr_intr(caddr_t a);
+
+/*
+ * pbm_cdma_flag(schizo only): consistent dma sync handshake
+ */
+#define	PBM_CDMA_DONE	0xcc /* arbitrary pattern set by interrupt handler */
+#define	PBM_CDMA_PEND	0x55 /* arbitrary pattern set by sync requester */
+#define	PBM_CDMA_INO_BASE	0x35    /* ino can be used for cdma sync */
+
+/*
+ * Estar control bit for schizo estar reg
+ */
+#define	SCHIZO_PCI_CTRL_BUS_SPEED		0x0000000000000001ull
+
+#define	PCI_CMN_ID(chip_type, id) \
+	((chip_type) == PCI_CHIP_TOMATILLO ? ((id) >> 1) << 1 : (id))
+#define	PCI_ID_TO_IGN(pci_id)		((pci_ign_t)((pci_id) & 0x1f))
+#define	PCI_ID_TO_NODEID(pci_id)	((cb_nid_t)((pci_id) >> PCI_IGN_BITS))
+
+#define	PCI_BRIDGE_TYPE(cmn_p) \
+	(((cmn_p->pci_chip_id >> 16) == PCI_CHIP_SCHIZO) ? PCI_SCHIZO : \
+	((cmn_p->pci_chip_id >> 16) == PCI_CHIP_TOMATILLO) ? PCI_TOMATILLO : \
+	((cmn_p->pci_chip_id >> 16) == PCI_CHIP_XMITS) ? PCI_XMITS : "")
+/*
+ * Tomatillo only
+ */
+#define	NBIGN(ib_p)			((ib_p)->ib_ign ^ 1)
+#define	IB_INO_TO_NBMONDO(ib_p, ino)	IB_IGN_TO_MONDO(NBIGN(ib_p), ino)
+
+/*
+ * Mask to tell which PCI Side we are on
+ */
+#define	PCI_SIDE_ADDR_MASK			0x100000ull
+
+/*
+ * Offset from Schizo Base of Schizo CSR Base
+ */
+#define	PBM_CTRL_OFFSET				0x410000ull
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCISCH_H */
diff --git a/usr/src/uts/sun4u/sys/pci/pcisch_asm.h b/usr/src/uts/sun4u/sys/pci/pcisch_asm.h
new file mode 100644
index 0000000000..09c4655f73
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pci/pcisch_asm.h
@@ -0,0 +1,42 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2003 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PCI_ASM_H
+#define	_SYS_PCI_ASM_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+extern void tomatillo_store_store_order();
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PCI_ASM_H */
diff --git a/usr/src/uts/sun4u/sys/pic16f747.h b/usr/src/uts/sun4u/sys/pic16f747.h
new file mode 100644
index 0000000000..cc05cc5ece
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pic16f747.h
@@ -0,0 +1,128 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _PIC16f747_H
+#define	_PIC16f747_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * PIC Registers
+ */
+#define	RF_COMMAND	0x00
+#define	RF_STATUS	0x01
+#define	RF_IND_DATA	0x40
+#define	RF_IND_ADDR	0x41
+#define	RF_ENV_S0	0x80
+#define	RF_ENV_S1	0x81
+#define	RF_TPM_S0	0xC0
+#define	RF_TPM_S1	0xC1
+
+/*
+ * PIC Registers from Indirect Address/Data
+ */
+#define	RF_FAN0_PERIOD	0x00
+#define	RF_FAN1_PERIOD	0x01
+#define	RF_FAN2_PERIOD	0x02
+#define	RF_FAN3_PERIOD	0x03
+#define	RF_FAN4_PERIOD	0x04
+#define	RF_LOCAL_TEMP	0x06
+#define	RF_REMOTE1_TEMP	0x07
+#define	RF_REMOTE2_TEMP	0x08
+#define	RF_REMOTE3_TEMP	0x09
+#define	RF_LM95221_TEMP	0x0A
+#define	RF_FIRE_TEMP	0x0B
+#define	RF_LSI1064_TEMP	0x0C
+#define	RF_FRONT_TEMP	0x0D
+#define	RF_FAN_STATUS	0x0E
+#define	RF_VCORE0	0x0F
+#define	RF_VCORE1	0x10
+
+/*
+ * Bitmasks for RF_STATUS register
+ */
+#define	ST_FFAULT		0x01	/* fan failure has occurred */
+#define	ST_ENV_BUSY		0x02	/* environmental bus is busy */
+#define	ST_STALE_ADT_DATA	0x04	/* ADT7462 data currently invalid */
+#define	ST_STALE_LM_DATA	0x08	/* LM95221 data currently invalid */
+#define	ST_FW_VERSION		0xF0	/* firmware version number */
+
+/*
+ * Bitmasks for RF_COMMAND values
+ */
+#define	CMD_TO_ESTAR		0x01
+#define	CMD_PIC_RESET		0x80
+
+/* Number of fans/sensors */
+#define	MAX_PIC_NODES		16
+#define	N_FANS			5
+#define	N_SENSORS		8
+#define	N_PIC_NODES		(N_FANS+N_SENSORS+1)
+
+/*
+ * PIC devices' node name and register offset
+ */
+#define	PICDEV_NODE_TYPE	"pic_client:env-monitor"
+typedef struct minor_node_info {
+	char		*minor_name;	/* node name */
+	uint8_t		reg_offset;	/* indirect register offset */
+	uint8_t		ff_shift;	/* fan fault shift (only for fans) */
+} minor_node_info;
+
+/*
+ * PIC device minor numbers are constructed as <inst_9-12>:<unit_0-8>
+ */
+#define	PIC_INST_TO_MINOR(x)	(((x) << 8) & 0x0F00)
+#define	PIC_UNIT_TO_MINOR(x)	((x) & 0xFF)
+#define	PIC_MINOR_TO_UNIT(x)	((x) & 0xFF)
+#define	PIC_MINOR_TO_INST(x)	(((x)>> 8) & 0xF)
+
+/*
+ * PIC ioctl commands
+ */
+#define	PICIOC	('X'<<8)
+#define	PIC_GET_TEMPERATURE	(PICIOC|1)
+#define	PIC_GET_FAN_SPEED	(PICIOC|2)
+#define	PIC_SET_FAN_SPEED	(PICIOC|3)
+#define	PIC_GET_STATUS		(PICIOC|4)
+#define	PIC_GET_FAN_STATUS	(PICIOC|5)
+#define	PIC_SET_ESTAR_MODE	(PICIOC|6)
+
+/*
+ * Miscellaneous
+ */
+#define	MAX_PIC_INSTANCES	4
+#define	MAX_RETRIES		10
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _PIC16f747_H */
diff --git a/usr/src/uts/sun4u/sys/plat_ecc_unum.h b/usr/src/uts/sun4u/sys/plat_ecc_unum.h
new file mode 100644
index 0000000000..aad92eb665
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/plat_ecc_unum.h
@@ -0,0 +1,473 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PLAT_ECC_NUM_H
+#define	_SYS_PLAT_ECC_NUM_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/int_types.h>
+#include <sys/cheetahregs.h>
+#include <sys/cpuvar.h>
+#include <sys/dditypes.h>
+#include <sys/ddipropdefs.h>
+#include <sys/ddi_impldefs.h>
+#include <sys/sunddi.h>
+#include <sys/platform_module.h>
+#include <sys/errno.h>
+#include <sys/conf.h>
+#include <sys/cmn_err.h>
+#include <sys/sysmacros.h>
+
+
+/*
+ * This file contains the common definitions used by the platform
+ * unum ecc logging.
+ */
+
+typedef enum {
+	PLAT_ECC_ERROR_MESSAGE,
+	PLAT_ECC_INDICTMENT_MESSAGE,
+	PLAT_ECC_ERROR2_MESSAGE,
+	PLAT_ECC_INDICTMENT2_MESSAGE,
+	PLAT_ECC_CAPABILITY_MESSAGE
+} plat_ecc_message_type_t;
+
+/* Platform-specific function for sending mailbox message */
+extern int plat_send_ecc_mailbox_msg(plat_ecc_message_type_t, void *);
+
+/* For figuring out unique CPU id */
+extern int plat_make_fru_cpuid(int, int, int);
+
+/* For figuring out board number for given CPU id */
+extern int plat_make_fru_boardnum(int);
+
+/* For initializing the taskqs */
+extern void plat_ecc_init(void);
+
+/* For setting the capability value */
+extern void plat_ecc_capability_sc_set(uint32_t cap);
+
+/* For sending a capability message to the SC */
+extern int plat_ecc_capability_send(void);
+
+/*
+ * The following variables enable and disable the fruid message logging on SC.
+ * ecc_log_fruid_enable can be set in /etc/system or via mdb.  A value
+ * of 1 is default, and indicates the messages are sent.  A value of 0
+ * indicates that the messages are not sent.
+ */
+extern int ecc_log_fruid_enable;
+
+#define	ECC_FRUID_ENABLE_DEFAULT	1
+
+#define	PLAT_ECC_JNUMBER_LENGTH	60
+typedef struct plat_ecc_error_data {
+	uint8_t		version;	/* Starting with 1 */
+	uint8_t		error_code;	/* Error Code */
+	uint16_t	proc_num;	/* Processor Number of */
+					/* CPU in error */
+	uint8_t		bank_no;	/* 0 or 1 */
+	uint8_t		ecache_dimm_no;	/* 0 to 3 */
+	uint8_t		error_type;	/* single, two, three, quad */
+					/* or multiple bit error status */
+	uint8_t		databit_type;	/* Identify the databit type: */
+					/* MTAG, ECC, MTAGECC or Data */
+	uint8_t		databit_no;	/* Failed Databit number */
+	uint8_t		node_no;	/* Wildcat node number */
+	uint16_t	detecting_proc;	/* Processor detecting the ECC error */
+	char		Jnumber[60];	/* Jnumber of the Dimm or Ecache */
+} plat_ecc_error_data_t;
+
+#define	PLAT_ECC_VERSION	2
+#define	PLAT_ERROR_CODE_UNK	0x0	/* Unknown */
+#define	PLAT_ERROR_CODE_CE	0x1	/* Correctable ECC error */
+#define	PLAT_ERROR_CODE_UE	0x2	/* Uncorrectable ECC error */
+#define	PLAT_ERROR_CODE_EDC	0x3	/* Correctable ECC error from E$ */
+#define	PLAT_ERROR_CODE_EDU	0x4	/* Uncorrectable ECC error from E$ */
+#define	PLAT_ERROR_CODE_WDC	0x5	/* Correctable E$ write-back ECC */
+#define	PLAT_ERROR_CODE_WDU	0x6	/* Uncorrectable E$ write-back ECC */
+#define	PLAT_ERROR_CODE_CPC	0x7	/* Copy-out correctable ECC error */
+#define	PLAT_ERROR_CODE_CPU	0x8	/* Copy-out uncorrectable ECC error */
+#define	PLAT_ERROR_CODE_UCC	0x9	/* SW handled correctable ECC */
+#define	PLAT_ERROR_CODE_UCU	0xa	/* SW handled uncorrectable ECC */
+#define	PLAT_ERROR_CODE_EMC	0xb	/* Correctable MTAG ECC error */
+#define	PLAT_ERROR_CODE_EMU	0xc	/* Uncorrectable MTAG ECC error */
+
+#define	PLAT_ERROR_TYPE_UNK	0x0	/* Unknown */
+#define	PLAT_ERROR_TYPE_SINGLE	0x1	/* Single bit error */
+#define	PLAT_ERROR_TYPE_M2	0x2	/* Double bit error */
+#define	PLAT_ERROR_TYPE_M3	0x3	/* Triple bit error */
+#define	PLAT_ERROR_TYPE_M4	0x4	/* Quad bit error */
+#define	PLAT_ERROR_TYPE_M	0x5	/* Multiple bit error */
+
+#define	PLAT_BIT_TYPE_MULTI	0x0	/* Error is 2 or more bits */
+#define	PLAT_BIT_TYPE_MTAG_D	0x1	/* MTAG data error */
+#define	PLAT_BIT_TYPE_MTAG_E	0x2	/* MTAG ECC error */
+#define	PLAT_BIT_TYPE_ECC	0x3	/* ECC error */
+#define	PLAT_BIT_TYPE_DATA	0x4	/* Data error */
+
+/*
+ * Based on "UltraSPARC-III Programmer's Reference Manual", these values are
+ * obtained when you use the syndrom bits from the AFSR to index into the
+ * ECC syndroms table.  See cheetah.c for more details on the definitions
+ * of C0, C1, C2, ... C8, MT0, MT1, ... M3, M4 ... etc.
+ */
+
+#define	ECC_SYND_DATA_BEGIN	0
+#define	ECC_SYND_DATA_LENGTH	127	/* data bits 0-127 */
+#define	ECC_SYND_ECC_BEGIN	(ECC_SYND_DATA_BEGIN + ECC_SYND_DATA_LENGTH)
+#define	ECC_SYND_ECC_LENGTH	9	/* ECC bits C0 - C* */
+#define	ECC_SYND_MTAG_BEGIN	(ECC_SYND_ECC_BEGIN + ECC_SYND_ECC_LENGTH)
+#define	ECC_SYND_MTAG_LENGTH	3	/* MTAG DATA bits MT0, MT1, MT3 */
+#define	ECC_SYND_MECC_BEGIN	(ECC_SYND_MTAG_BEGIN + ECC_SYND_MTAG_LENGTH)
+#define	ECC_SYND_MECC_LENGTH	4	/* MTAG ECC bits MTC0 - MTC3 */
+#define	ECC_SYND_M2	144
+#define	ECC_SYND_M3	145
+#define	ECC_SYND_M4	146
+#define	ECC_SYND_M	147
+
+enum plat_ecc_type {PLAT_ECC_UNKNOWN, PLAT_ECC_MEMORY, PLAT_ECC_ECACHE };
+
+typedef struct plat_ecc_msg_hdr {
+	uint8_t		emh_major_ver;
+	uint8_t		emh_minor_ver;
+	uint16_t	emh_msg_type;
+	uint16_t	emh_msg_length;
+	uint16_t	emh_future0;	/* pad */
+} plat_ecc_msg_hdr_t;
+
+extern uint16_t ecc_error2_mailbox_flags;
+
+#define	PLAT_ECC_ERROR2_SEND_L2_XXC		0x0001
+#define	PLAT_ECC_ERROR2_SEND_L2_XXU		0x0002
+#define	PLAT_ECC_ERROR2_SEND_L3_XXC		0x0004
+#define	PLAT_ECC_ERROR2_SEND_L3_XXU		0x0008
+#define	PLAT_ECC_ERROR2_SEND_MEM_ERRS		0x0010
+#define	PLAT_ECC_ERROR2_SEND_BUS_ERRS		0x0020
+#define	PLAT_ECC_ERROR2_SEND_L2_TAG_ERRS	0x0040
+#define	PLAT_ECC_ERROR2_SEND_L3_TAG_ERRS	0x0080
+#define	PLAT_ECC_ERROR2_SEND_L1_PARITY		0x0100
+#define	PLAT_ECC_ERROR2_SEND_TLB_PARITY		0x0200
+#define	PLAT_ECC_ERROR2_SEND_IV_ERRS		0x0400
+#define	PLAT_ECC_ERROR2_SEND_MTAG_XXC		0x0800
+#define	PLAT_ECC_ERROR2_SEND_IV_MTAG_XXC	0x1000
+#define	PLAT_ECC_ERROR2_SEND_PCACHE		0x2000
+
+/* default value for ecc_error2_mailbox_flags */
+#define	PLAT_ECC_ERROR2_SEND_DEFAULT		0x3fff
+
+typedef struct plat_ecc_error2_data {
+	plat_ecc_msg_hdr_t	ee2d_header;	/* Header info */
+	uint8_t		ee2d_type;		/* PLAT_ECC_ERROR2_* */
+	uint8_t		ee2d_afar_status;	/* AFLT_STAT_* (see async.h) */
+	uint8_t		ee2d_synd_status;	/* AFLT_STAT_* (see async.h) */
+	uint8_t		ee2d_bank_number;	/* 0 or 1 */
+	uint16_t	ee2d_detecting_proc;	/* Proc that detected error */
+	uint16_t	ee2d_jnumber;		/* J# of the part in error */
+	uint16_t	ee2d_owning_proc;	/* Proc that controls memory */
+	uint16_t	ee2d_future1;		/* pad */
+	uint32_t	ee2d_cpu_impl;		/* Proc type */
+	uint64_t	ee2d_afsr;		/* AFSR */
+	uint64_t	ee2d_sdw_afsr;		/* Shadow AFSR */
+	uint64_t	ee2d_afsr_ext;		/* Extended AFSR */
+	uint64_t	ee2d_sdw_afsr_ext;	/* Shadow extended AFSR */
+	uint64_t	ee2d_afar;		/* AFAR */
+	uint64_t	ee2d_sdw_afar;		/* Shadow AFAR */
+	uint64_t	ee2d_timestamp;		/* Time stamp */
+} plat_ecc_error2_data_t;
+
+#define	ee2d_major_version	ee2d_header.emh_major_ver
+#define	ee2d_minor_version	ee2d_header.emh_minor_ver
+#define	ee2d_msg_type		ee2d_header.emh_msg_type
+#define	ee2d_msg_length		ee2d_header.emh_msg_length
+
+#define	PLAT_ECC_ERROR2_VERSION_MAJOR		1
+#define	PLAT_ECC_ERROR2_VERSION_MINOR		1
+
+/* Values for ee2d_type */
+#define	PLAT_ECC_ERROR2_NONE			0x00
+#define	PLAT_ECC_ERROR2_L2_CE			0x01
+#define	PLAT_ECC_ERROR2_L2_UE			0x02
+#define	PLAT_ECC_ERROR2_L3_CE			0x03
+#define	PLAT_ECC_ERROR2_L3_UE			0x04
+#define	PLAT_ECC_ERROR2_CE			0x05
+#define	PLAT_ECC_ERROR2_UE			0x06
+#define	PLAT_ECC_ERROR2_DUE			0x07
+#define	PLAT_ECC_ERROR2_TO			0x08
+#define	PLAT_ECC_ERROR2_BERR			0x09
+#define	PLAT_ECC_ERROR2_DTO			0x0a
+#define	PLAT_ECC_ERROR2_DBERR			0x0b
+#define	PLAT_ECC_ERROR2_L2_TSCE			0x0c
+#define	PLAT_ECC_ERROR2_L2_THCE			0x0d
+#define	PLAT_ECC_ERROR2_L3_TSCE			0x0e /* Unused */
+#define	PLAT_ECC_ERROR2_L3_THCE			0x0f
+#define	PLAT_ECC_ERROR2_DPE			0x10
+#define	PLAT_ECC_ERROR2_IPE			0x11
+#define	PLAT_ECC_ERROR2_ITLB			0x12
+#define	PLAT_ECC_ERROR2_DTLB			0x13
+#define	PLAT_ECC_ERROR2_IVU			0x14
+#define	PLAT_ECC_ERROR2_IVC			0x15
+#define	PLAT_ECC_ERROR2_EMC			0x16
+#define	PLAT_ECC_ERROR2_IMC			0x17
+#define	PLAT_ECC_ERROR2_L3_MECC			0x18
+#define	PLAT_ECC_ERROR2_PCACHE			0x19
+
+#define	PLAT_ECC_ERROR2_NUMVALS			0x1a
+
+typedef struct plat_ecc_ch_async_flt {
+	int		ecaf_synd_status; /* AFLT_STAT_* (see async.h) */
+	int		ecaf_afar_status; /* AFLT_STAT_* (see async.h) */
+	uint64_t	ecaf_sdw_afar;
+	uint64_t	ecaf_sdw_afsr;
+	uint64_t	ecaf_afsr_ext;
+	uint64_t	ecaf_sdw_afsr_ext;
+} plat_ecc_ch_async_flt_t;
+
+/*
+ * The following structures/#defines are used to notify the SC
+ * of DIMMs that fail the leaky bucket algorithm, E$ that experience
+ * multiple correctable errors and fail the serd algorithm, and
+ * E$ that experience any non-fatal uncorrectable error.
+ */
+
+extern uint8_t ecc_indictment_mailbox_disable;
+
+/* The message is OK */
+#define	PLAT_ECC_INDICTMENT_OK		0x00
+
+/* Send the message, but don't trust it */
+#define	PLAT_ECC_INDICTMENT_SUSPECT	0x01
+
+/* Don't send message */
+#define	PLAT_ECC_INDICTMENT_NO_SEND	0x02
+
+extern uint8_t ecc_indictment_mailbox_flags;
+
+/* DIMM indictments for CEs */
+#define	PLAT_ECC_SEND_DIMM_INDICT		0x01
+
+/* E$ indictments for UCC, WDC, CPC, EDC */
+#define	PLAT_ECC_SEND_ECACHE_XXC_INDICT		0x02
+
+/* E$ indictments for UCU, WDU, CPU, EDU */
+#define	PLAT_ECC_SEND_ECACHE_XXU_INDICT		0x04
+
+/* Default value for ecc_indictment_mailbox_flags */
+#define	PLAT_ECC_SEND_DEFAULT_INDICT	(PLAT_ECC_SEND_ECACHE_XXC_INDICT |\
+					PLAT_ECC_SEND_ECACHE_XXU_INDICT)
+
+/*
+ * WARNING: The plat_ecc_indictment_data_t struct size can be no bigger than
+ * 128 bytes.  The union will fill out the structure to the correct size -
+ * the string space used in solaris_version will fill out the rest of the
+ * structure.
+ *
+ * Any changes made to this structure in the future should ensure that the
+ * structure does not go over 128 bytes.
+ */
+
+#define	PLAT_ECC_INDICT_SIZE	128
+
+typedef struct {
+	uint8_t 	version;		/* Starting with 1 */
+	uint8_t 	indictment_type;	/* see below for values */
+	uint8_t 	indictment_uncertain;
+				/* Value of ecc_indictment_mailbox_disable */
+	uint8_t 	board_num;		/* board number of dimm/E$ */
+	uint16_t	detecting_proc;		/* Processor Number of CPU */
+						/* reporting error */
+	uint16_t	syndrome;		/* syndrome of last error */
+	uint16_t	jnumber;		/* Jnumber of dimm/E$ */
+	uint16_t	future[7];		/* For future use */
+	uint64_t	afsr;			/* AFSR of last error */
+	uint64_t	afar;			/* AFAR of last error */
+	char    	solaris_version[1];
+						/* Solaris version string */
+} plat_ecc_indict_msg_contents_t;
+
+typedef union {
+	plat_ecc_indict_msg_contents_t	msg_contents;
+	uint8_t				filler[PLAT_ECC_INDICT_SIZE];
+} plat_ecc_indictment_data_t;
+
+#define	PLAT_ECC_VERSION_LENGTH		(PLAT_ECC_INDICT_SIZE - \
+		offsetof(plat_ecc_indict_msg_contents_t, solaris_version))
+
+#define	PLAT_ECC_INDICTMENT_VERSION	1
+
+/*
+ * Values for indictment_type.  For Panther, E$ refers to
+ * the L3$.  For previous procs, E$ refers to the L2$.
+ */
+#define	PLAT_ECC_INDICT_NONE			0x00
+#define	PLAT_ECC_INDICT_DIMM			0x01
+#define	PLAT_ECC_INDICT_ECACHE_CORRECTABLES	0x02
+#define	PLAT_ECC_INDICT_ECACHE_UNCORRECTABLE	0x03
+
+
+/*
+ * These values are used to set the state of msg_status
+ *
+ * 0 - No message in transit
+ * 1 - taskq thread dispatched, dispatching thread waiting for signal
+ * 2 - dispatched thread completed sending message
+ * 3 - dispatching thread received interrupt, not waiting for signal
+ */
+#define	PLAT_ECC_NO_MSG_ACTIVE		0
+#define	PLAT_ECC_TASK_DISPATCHED	1
+#define	PLAT_ECC_MSG_SENT		2
+#define	PLAT_ECC_INTERRUPT_RECEIVED	3
+
+/*
+ * Min and max sizes of plat_ecc_taskq
+ */
+#define	PLAT_ECC_TASKQ_MIN	2
+#define	PLAT_ECC_TASKQ_MAX	8
+
+extern uint16_t ecc_indictment2_mailbox_flags;
+
+
+#define	PLAT_ECC_SEND_INDICT2_L2_XXU		0x0001
+#define	PLAT_ECC_SEND_INDICT2_L2_XXC_SERD	0x0002
+#define	PLAT_ECC_SEND_INDICT2_L2_TAG_SERD	0x0004
+#define	PLAT_ECC_SEND_INDICT2_L3_XXU		0x0008
+#define	PLAT_ECC_SEND_INDICT2_L3_XXC_SERD	0x0010
+#define	PLAT_ECC_SEND_INDICT2_L3_TAG_SERD	0x0020
+#define	PLAT_ECC_SEND_INDICT2_L1_SERD		0x0040
+#define	PLAT_ECC_SEND_INDICT2_TLB_SERD		0x0080
+#define	PLAT_ECC_SEND_INDICT2_FPU		0x0100
+#define	PLAT_ECC_SEND_INDICT2_PCACHE_SERD	0x0200
+
+#define	PLAT_ECC_SEND_INDICT2_DEFAULT		0x03ff
+
+typedef struct plat_ecc_indictment2_data {
+	plat_ecc_msg_hdr_t	ei2d_header;	/* Header info */
+	uint8_t		ei2d_type;		/* PLAT_ECC_INDICT2_* */
+	uint8_t		ei2d_uncertain;		/* See indictment_uncertain */
+	uint8_t		ei2d_board_num;		/* Board number of dimm */
+	uint8_t		ei2d_future1;		/* pad */
+	uint16_t	ei2d_arraigned_proc;	/* Proc number */
+	uint16_t	ei2d_jnumber;		/* Jnumber */
+	uint32_t	ei2d_cpu_impl;		/* Proc type */
+	uint32_t	ei2d_future2;		/* pad */
+	uint64_t	ei2d_timestamp;		/* Time stamp */
+} plat_ecc_indictment2_data_t;
+
+#define	ei2d_major_version	ei2d_header.emh_major_ver
+#define	ei2d_minor_version	ei2d_header.emh_minor_ver
+#define	ei2d_msg_type		ei2d_header.emh_msg_type
+#define	ei2d_msg_length		ei2d_header.emh_msg_length
+
+#define	PLAT_ECC_INDICT2_MAJOR_VERSION	1
+#define	PLAT_ECC_INDICT2_MINOR_VERSION	1
+
+/*
+ * Values for ei2d_type
+ */
+
+#define	PLAT_ECC_INDICT2_NONE			0x00
+#define	PLAT_ECC_INDICT2_L2_UE			0x01
+#define	PLAT_ECC_INDICT2_L2_SERD		0x02
+#define	PLAT_ECC_INDICT2_L2_TAG_SERD		0x03
+#define	PLAT_ECC_INDICT2_L3_UE			0x04
+#define	PLAT_ECC_INDICT2_L3_SERD		0x05
+#define	PLAT_ECC_INDICT2_L3_TAG_SERD		0x06
+#define	PLAT_ECC_INDICT2_DCACHE_SERD		0x07
+#define	PLAT_ECC_INDICT2_ICACHE_SERD		0x08
+#define	PLAT_ECC_INDICT2_ITLB_SERD		0x09
+#define	PLAT_ECC_INDICT2_DTLB_SERD		0x0a
+#define	PLAT_ECC_INDICT2_FPU			0x0b
+#define	PLAT_ECC_INDICT2_PCACHE_SERD		0x0c
+
+#define	PLAT_ECC_INDICT2_NUMVALS		0x0d
+
+/*
+ * The following structure maps the indictment reason to its
+ * corresponding type.
+ */
+typedef struct plat_ecc_bl_map {
+	char	*ebm_reason;	/* Indictment reason */
+	int	ebm_type;	/* Indictment type */
+} plat_ecc_bl_map_t;
+
+/*
+ * This message is used to exchange the capability of the SC and Domain
+ * so that both entities can adjust their behavior as appropriate.
+ * Also the Solaris version is sent from the Domain along with the
+ * capability bitmap.
+ */
+typedef struct plat_capability_data {
+	plat_ecc_msg_hdr_t	capd_header;	/* Header info */
+	uint32_t	capd_capability;	/* Capability bitmap */
+	uint32_t	capd_future1;		/* pad */
+	uint64_t	capd_future2;		/* pad */
+	char		capd_solaris_version[1];
+						/* Solaris version string ptr */
+} plat_capability_data_t;
+
+#define	capd_major_version	capd_header.emh_major_ver
+#define	capd_minor_version	capd_header.emh_minor_ver
+#define	capd_msg_type		capd_header.emh_msg_type
+#define	capd_msg_length		capd_header.emh_msg_length
+
+#define	PLAT_ECC_CAP_VERSION_MAJOR	1
+#define	PLAT_ECC_CAP_VERSION_MINOR	1
+
+#define	PLAT_ECC_CAPABILITY_ERROR		0x01
+#define	PLAT_ECC_CAPABILITY_INDICT		0x02
+#define	PLAT_ECC_CAPABILITY_ERROR2		0x04
+#define	PLAT_ECC_CAPABILITY_INDICT2		0x08
+#define	PLAT_ECC_CAPABILITY_FMA			0x10
+#define	PLAT_ECC_CAPABILITY_EREPORTS		0x20
+
+#define	PLAT_ECC_CAPABILITY_DOMAIN_DEFAULT	0x1f
+#define	PLAT_ECC_CAPABILITY_SC_DEFAULT		0x03
+
+extern uint32_t plat_ecc_capability_map_domain;
+extern uint32_t plat_ecc_capability_map_sc;
+
+/*
+ * The following structure is a wrapper around the all messages. The
+ * extra members are used for communicating between two threads.
+ */
+typedef struct plat_ecc_message {
+	plat_ecc_message_type_t		ecc_msg_type;
+	uint32_t			ecc_msg_status;
+	uint32_t			ecc_msg_ret;
+	uint32_t			ecc_msg_len;
+	void *				ecc_msg_data;
+} plat_ecc_message_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PLAT_ECC_NUM_H */
diff --git a/usr/src/uts/sun4u/sys/pmubus.h b/usr/src/uts/sun4u/sys/pmubus.h
new file mode 100644
index 0000000000..c82eb623dc
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pmubus.h
@@ -0,0 +1,95 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2000-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_PMUBUS_H
+#define	_SYS_PMUBUS_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+/*
+ * definition of pmubus reg spec entry:
+ */
+typedef struct {
+	uint32_t reg_addr_hi;
+	uint32_t reg_addr_lo;
+	uint32_t reg_size;
+} pmubus_obpregspec_t;
+
+typedef struct {
+	uint64_t reg_addr;
+	uint32_t reg_size;
+} pmubus_regspec_t;
+
+
+typedef struct {
+	uint64_t rng_child;
+	uint32_t rng_parent_hi;
+	uint32_t rng_parent_mid;
+	uint32_t rng_parent_low;
+	uint32_t rng_size;
+} pmu_rangespec_t;
+
+
+/*
+ * driver soft state structure:
+ */
+typedef struct {
+	dev_info_t *pmubus_dip;
+	pci_regspec_t *pmubus_regp;
+	int pmubus_reglen;
+	ddi_acc_handle_t pmubus_reghdl;
+	pmu_rangespec_t *pmubus_rangep;
+	int pmubus_rnglen;
+	int pmubus_nranges;
+	kmutex_t pmubus_reg_access_lock;
+} pmubus_devstate_t;
+
+/* Flags for specifying the type of register space. */
+#define	MAPREQ_SHARED_REG	0x1
+#define	MAPREQ_SHARED_BITS	0x2
+
+#define	MAPPING_SHARED_BITS_MASK	0x8000000000000000ull
+
+#define	PMUBUS_REGOFFSET	0xff
+
+typedef struct {
+	pmubus_devstate_t *mapreq_softsp;
+	unsigned long mapreq_flags;
+	uint64_t mapreq_addr;
+	size_t mapreq_size;
+	uint64_t mapreq_mask;
+} pmubus_mapreq_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PMUBUS_H */
diff --git a/usr/src/uts/sun4u/sys/ppmvar.h b/usr/src/uts/sun4u/sys/ppmvar.h
new file mode 100644
index 0000000000..9b5a2ae1ae
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/ppmvar.h
@@ -0,0 +1,378 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_PPMVAR_H
+#define	_SYS_PPMVAR_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/epm.h>
+#include <sys/sunldi.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+typedef struct ppm_unit {
+	dev_info_t	*dip;		/* node dev info */
+	kmutex_t	lock;		/* global driver lock */
+	uint_t		states;		/* driver states */
+	timeout_id_t	led_tid;	/* timeout id for LED */
+} ppm_unit_t;
+
+/*
+ * driver states
+ */
+#define	PPM_STATE_SUSPENDED	0x1	/* driver is suspended */
+
+/*
+ * Check for domain operational
+ */
+#define	PPM_DOMAIN_UP(domp)	(!(domp->dflags & PPMD_OFFLINE))
+
+/*
+ * LED constants
+ */
+#define	PPM_LED_PULSE		(drv_usectohz(250000))	/* 0.25 seconds */
+#define	PPM_LEDON_INTERVAL	(1 * PPM_LED_PULSE)
+#define	PPM_LEDOFF_INTERVAL	(8 * PPM_LED_PULSE)
+#define	PPM_LEDON		1	/* (s10) */
+#define	PPM_LEDOFF		0	/* (s10) */
+
+/*
+ * internal form of "ppm.conf" data
+ */
+struct ppm_db {
+	struct ppm_db	*next;
+	char		*name;		/* device name */
+	int		plen;		/* strlen before wildcard(s10) */
+	int		wccnt;		/* upto 2 '*' allowed */
+	int		wcpos[2];	/* '*' location in pathname */
+};
+typedef struct ppm_db ppm_db_t;
+
+struct ppm_cdata {
+	char *name;			/* property name */
+	char **strings;			/* string array */
+	uint_t cnt;			/* property count */
+};
+
+/*
+ * ppm device info
+ */
+struct ppm_dev {
+	struct ppm_dev	*next;
+	struct ppm_domain *domp;
+	dev_info_t	*dip;
+	char		*path;		/* OBP device pathname */
+	int		cmpt;		/* component number */
+	int		rplvl;		/* last requested power level */
+	int		level;		/* actual current power level */
+	int		lowest;		/* lowest power level for device */
+	int		highest;	/* highest power level for device */
+	uint_t		flags;
+};
+typedef struct ppm_dev ppm_dev_t;
+
+/*
+ * ppm_dev.flags field
+ */
+#define	PPMDEV_PCI66_D2		0x1	/* device support D2 at pci 66mhz */
+#define	PPMDEV_PCI_PROP_CLKPM	0x2	/* clock can be power managed */
+#define	PPM_PM_POWEROP		0x10	/* power level change, initiated  */
+					/* from PM is in progress.	  */
+#define	PPM_PHC_WHILE_SET_POWER 0x20	/* power level of a device is	  */
+					/* changed through		  */
+					/* pm_power_has_changed path	  */
+					/* while power level change,	  */
+					/* initiated from PM is in	  */
+					/* progress.			  */
+
+
+/*
+ * per domain record of device _ever_ managed by ppm
+ */
+struct ppm_owned {
+	struct ppm_owned *next;
+	char	*path;		/* device pathname */
+	int	initializing;	/* initializing  flag */
+};
+typedef struct ppm_owned ppm_owned_t;
+
+
+/*
+ * domain control data structure -
+ *   when you need to do an op for a domain, look up the op in the
+ *   cmd member of the struct, and then perform the method on the
+ *   path using iowr cmd with the args specified in val or val and
+ *   mask or the speed index.
+ */
+struct ppm_dc {
+	struct ppm_dc	*next;
+	ldi_handle_t	lh;	/* layered (ldi) handle			*/
+	char	*path;		/* control device prom pathname		*/
+	uint_t	cmd;		/* search key: op to be performed	*/
+	uint_t	method;		/* control method / union selector	*/
+				/* one of PPMDC_KIO, PPMDC_I2CKIO,	*/
+				/* PPMDC_CPUSPEEDKIO			*/
+
+	union {
+		/* In each sub struct in union, the first three fields	*/
+		/* must be .iord, .iowr and .val and in such order.	*/
+		/* The .method field above selects a union sub struct	*/
+		/* for a particular .cmd operation.			*/
+		/* The association between .method and .cmd is platform	*/
+		/* specific, therefore described in ppm.conf file.	*/
+
+		/* PPMDC_KIO: simple KIO 				*/
+		struct m_kio {
+			uint_t	iord;	/* IOCTL read cmd		*/
+			uint_t	iowr;	/* IOCTL write cmd		*/
+			uint_t	val;	/* ioctl arg			*/
+			uint_t	delay;	/* total delay before this 	*/
+					/* operation can be carried out	*/
+			uint_t	post_delay; /* post delay, if any	*/
+		} kio;
+
+		/* PPMDC_I2CKIO: KIO requires 'arg' as struct i2c_gpio	*/
+		/*    (defined in i2c_client.h)				*/
+		struct m_i2ckio {
+			uint_t	iord;	/* IOCTL read cmd		*/
+			uint_t	iowr;	/* IOCTL write cmd 		*/
+			uint_t	val;	/* register content		*/
+			uint_t	mask;	/* mask to select relevant bits	*/
+					/* of register content		*/
+			uint_t	delay;	/* total delay before this 	*/
+					/* operation can be carried out	*/
+			uint_t	post_delay; /* post delay, if any	*/
+		} i2c;
+
+		/* PPMDC_CPUSPEEDKIO, PPMDC_VCORE: cpu estar related	*/
+		/* simple KIO						*/
+		struct m_cpu {
+			uint_t	iord;	/* IOCTL read cmd 		*/
+			uint_t	iowr;	/* IOCTL write cmd 		*/
+			int	val;	/* new register value		*/
+			uint_t	speeds;	/* number of speeds cpu supports */
+			uint_t	delay;	/* microseconds post op delay	*/
+		} cpu;
+	} m_un;
+};
+typedef struct ppm_dc ppm_dc_t;
+
+/*
+ * ppm_dc.cmd field -
+ */
+#define	PPMDC_CPU_NEXT		2
+#define	PPMDC_PRE_CHNG		3
+#define	PPMDC_CPU_GO		4
+#define	PPMDC_POST_CHNG		5
+#define	PPMDC_FET_ON		6
+#define	PPMDC_FET_OFF		7
+#define	PPMDC_LED_ON		8
+#define	PPMDC_LED_OFF		9
+#define	PPMDC_CLK_ON		10
+#define	PPMDC_CLK_OFF		11
+#define	PPMDC_PRE_PWR_OFF	12
+#define	PPMDC_PRE_PWR_ON	13
+#define	PPMDC_POST_PWR_ON	14
+#define	PPMDC_PWR_OFF		15
+#define	PPMDC_PWR_ON		16
+#define	PPMDC_RESET_OFF		17
+#define	PPMDC_RESET_ON		18
+
+/*
+ * ppm_dc.method field - select union element
+ */
+#define	PPMDC_KIO  		1	/* simple ioctl with val as arg	*/
+#define	PPMDC_CPUSPEEDKIO	2	/* ioctl with speed index arg	*/
+#define	PPMDC_VCORE		3	/* CPU Vcore change operation */
+#define	PPMDC_I2CKIO		4	/* ioctl with i2c_gpio_t as arg	*/
+
+/*
+ * devices that are powered by the same source
+ * are grouped by this struct as a "power domain"
+ */
+struct ppm_domain {
+	char		*name;		/* domain name */
+	int		dflags;		/* domain flags */
+	int		pwr_cnt;	/* number of powered up devices */
+	ppm_db_t	*conflist;	/* all devices from ppm.conf file */
+	ppm_dev_t	*devlist;	/* current attached devices */
+	char		*propname;	/* domain property name */
+	kmutex_t	lock;		/* domain lock */
+	int		refcnt;		/* domain lock ref count */
+	int		model;		/* pm model, CPU, FET or LED	*/
+	int		status;		/* domain specific status */
+	ppm_dc_t	*dc;		/* domain control method */
+	ppm_owned_t	*owned;		/* list of ever owned devices */
+	struct ppm_domain	*next;	/* a linked list */
+	clock_t		last_off_time;	/* last time domain was off	*/
+
+};
+typedef struct ppm_domain ppm_domain_t;
+
+
+/*
+ * ppm_domain.model field -
+ */
+#define	PPMD_CPU		1	/* cpu PM model */
+#define	PPMD_FET		2	/* power FET pm model */
+#define	PPMD_LED		3	/* LED pm model */
+#define	PPMD_PCI		4	/* PCI pm model */
+#define	PPMD_PCI_PROP		5	/* PCI_PROP pm model */
+#define	PPMD_PCIE		6	/* PCI Express pm model */
+
+#define	PPMD_IS_PCI(model) \
+	((model) == PPMD_PCI || (model) == PPMD_PCI_PROP)
+
+/*
+ * ppm_domain.status field -
+ */
+#define	PPMD_OFF		0x0	/* FET/LED/PCI clock: off */
+#define	PPMD_ON			0x1	/* FET/LED/PCI clock: on */
+
+/*
+ * ppm_domain.dflags field -
+ */
+#define	PPMD_LOCK_ONE		0x1
+#define	PPMD_LOCK_ALL		0x4
+#define	PPMD_PCI33MHZ		0x1000	/* 33mhz PCI slot */
+#define	PPMD_PCI66MHZ		0x2000	/* 66mhz PCI slot */
+#define	PPMD_INITCHILD_CLKON	0x4000	/* clk turned on in init_child */
+#define	PPMD_OFFLINE		0x10000	/* domain is not functional */
+
+/*
+ * XXppm driver-specific routines called from common code (s10)
+ */
+struct ppm_funcs {
+	void	(*dev_init)(ppm_dev_t *);
+	void	(*dev_fini)(ppm_dev_t *);
+	void	(*iocset)(uint8_t);
+	uint8_t	(*iocget)(void);
+};
+
+extern ppm_domain_t	*ppm_domain_p;
+extern void		*ppm_statep;
+extern int		ppm_inst;
+extern ppm_domain_t *ppm_domains[];	/* (s10) */
+extern struct ppm_funcs ppmf;		/* (s10) */
+
+extern void		ppm_dev_init(ppm_dev_t *);
+extern void		ppm_dev_fini(ppm_dev_t *);
+extern int		ppm_create_db(dev_info_t *);
+extern int		ppm_claim_dev(dev_info_t *);
+extern void		ppm_rem_dev(dev_info_t *);
+extern ppm_dev_t	*ppm_get_dev(dev_info_t *, ppm_domain_t *);
+extern void		ppm_init_cb(dev_info_t *);
+extern int		ppm_init_lyr(ppm_dc_t *, dev_info_t *);
+extern ppm_domain_t	*ppm_lookup_dev(dev_info_t *);
+extern ppm_domain_t	*ppm_lookup_domain(char *);
+extern ppm_dc_t		*ppm_lookup_dc(ppm_domain_t *, int);
+extern ppm_dc_t		*ppm_lookup_hndl(int, ppm_dc_t *);
+extern ppm_domain_t	*ppm_get_domain_by_dev(const char *);
+extern boolean_t	ppm_none_else_holds_power(ppm_domain_t *);
+extern ppm_owned_t	*ppm_add_owned(dev_info_t *, ppm_domain_t *);
+extern void		ppm_lock_one(ppm_dev_t *, power_req_t *, int *);
+extern void		ppm_lock_all(ppm_domain_t *, power_req_t *, int *);
+
+#define	PPM_GET_PRIVATE(dip) \
+    DEVI(dip)->devi_pm_ppm_private
+#define	PPM_SET_PRIVATE(dip, datap) \
+    DEVI(dip)->devi_pm_ppm_private = datap
+
+#define	PPM_LOCK_DOMAIN(domp) {			\
+	if (!MUTEX_HELD(&(domp)->lock))		\
+		mutex_enter(&(domp)->lock);	\
+	(domp)->refcnt++;			\
+}
+
+#define	PPM_UNLOCK_DOMAIN(domp) {		\
+	ASSERT(MUTEX_HELD(&(domp)->lock) &&	\
+		(domp)->refcnt > 0);		\
+	if (--(domp)->refcnt == 0)		\
+		mutex_exit(&(domp)->lock);	\
+}
+
+/*
+ * debug support
+ */
+#ifdef DEBUG
+#include <sys/promif.h>
+
+extern char	*ppm_get_ctlstr(int, uint_t);
+extern void	ppm_print_dc(struct ppm_dc *);
+
+extern uint_t ppm_debug;
+
+#define	D_CREATEDB	0x00000001
+#define	D_CLAIMDEV	0x00000002
+#define	D_ADDDEV	0x00000004
+#define	D_REMDEV	0x00000008
+#define	D_LOWEST	0x00000010
+#define	D_SETLVL	0x00000020
+#define	D_GPIO		0x00000040
+#define	D_CPU		0x00000080
+#define	D_FET		0x00000100
+#define	D_PCIUPA	0x00000200
+#define	D_1394		0x00000400
+#define	D_CTLOPS1	0x00000800
+#define	D_CTLOPS2	0x00001000
+#define	D_SOME		0x00002000
+#define	D_LOCKS		0x00004000
+#define	D_IOCTL		0x00008000
+#define	D_ATTACH	0x00010000
+#define	D_DETACH	0x00020000
+#define	D_OPEN		0x00040000
+#define	D_CLOSE		0x00080000
+#define	D_INIT		0x00100000
+#define	D_FINI		0x00200000
+#define	D_ERROR		0x00400000
+#define	D_SETPWR	0x00800000
+#define	D_LED		0x01000000
+#define	D_PCI		0x02000000
+#define	D_PPMDC		0x04000000
+#define	D_CPR		0x08000000
+
+#define	PPMD(level, arglist) {			\
+	if (ppm_debug & (level)) {		\
+		pm_log arglist;			\
+	}					\
+}
+/* (s10) */
+#define	DPRINTF		PPMD
+
+#else	/* DEBUG */
+#define	PPMD(level, arglist)
+#define	DPRINTF(flag, args)	/* (s10) */
+#endif	/* DEBUG */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_PPMVAR_H */
diff --git a/usr/src/uts/sun4u/sys/prom_plat.h b/usr/src/uts/sun4u/sys/prom_plat.h
new file mode 100644
index 0000000000..9a63803111
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/prom_plat.h
@@ -0,0 +1,293 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_PROM_PLAT_H
+#define	_SYS_PROM_PLAT_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/feature_tests.h>
+#include <sys/cpuvar.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#if !defined(_LONGLONG_TYPE)
+#error "This header won't work without long long support"
+#endif
+
+/*
+ * This file contains external platform-specific promif interface definitions.
+ * There may be none.  This file is included by reference in <sys/promif.h>
+ *
+ * This version of the file is for the IEEE 1275-1994 compliant sun4u prom.
+ */
+
+/*
+ * Memory allocation plus memory/mmu interfaces:
+ *
+ * Routines with fine-grained memory and MMU control are platform-dependent.
+ *
+ * MMU node virtualized "mode" arguments and results for Spitfire MMU:
+ *
+ * The default virtualized "mode" for client program mappings created
+ * by the firmware is as follows:
+ *
+ * G (global)		Clear
+ * L (locked)		Clear
+ * W (write)		Set
+ * R (read - soft)	Set (Prom is not required to implement soft bits)
+ * X (exec - soft)	Set (Prom is not required to implement soft bits)
+ * CV,CP (Cacheable)	Set if memory page, Clear if IO page
+ * E (side effects)	Clear if memory page; Set if IO page
+ * IE (Invert endian.)	Clear
+ *
+ * The following fields are initialized as follows in the TTE-data for any
+ * mappings created by the firmware on behalf of the client program:
+ *
+ * P (Priviledged)	Set
+ * V (Valid)		Set
+ * NFO (No Fault Only)	Clear
+ * Context		0
+ * Soft bits		< private to the firmware implementation >
+ *
+ * Page size of Prom mappings are typically 8k, "modify" cannot change
+ * page sizes. Mappings created by "map" are 8k pages.
+ *
+ * If the virtualized "mode" is -1, the defaults as shown above are used,
+ * otherwise the virtualized "mode" is set (and returned) based on the
+ * following virtualized "mode" abstractions. The mmu node "translations"
+ * property contains the actual tte-data, not the virtualized "mode".
+ *
+ * Note that client programs may not create locked mappings by setting
+ * the LOCKED bit. There are Spitfire specific client interfaces to create
+ * and remove locked mappings. (SUNW,{i,d}tlb-load).
+ * The LOCKED bit is defined here since it may be returned by the
+ * "translate" method.
+ *
+ * The PROM is not required to implement the Read and eXecute soft bits,
+ * and is not required to track them for the client program. They may be
+ * set on calls to "map" and "modfify" and may be ignored by the firmware,
+ * and are not necessarily returned from "translate".
+ *
+ * The TTE soft bits are private to the firmware.  No assumptions may
+ * be made regarding the contents of the TTE soft bits.
+ *
+ * Changing a mapping from cacheable to non-cacheable implies a flush
+ * or invalidate operation, if necessary.
+ *
+ * NB: The "map" MMU node method should NOT be used to create IO device
+ * mappings. The correct way to do this is to call the device's parent
+ * "map-in" method using the CALL-METHOD client interface service.
+ */
+
+#define	PROM_MMU_MODE_DEFAULT	((int)-1)	/* Default "mode", see above */
+
+/*
+ * NB: These are not implemented in PROM version P1.0 ...
+ */
+#define	PROM_MMU_MODE_WRITE	0x0001	/* Translation is Writable */
+#define	PROM_MMU_MODE_READ	0x0002	/* Soft: Readable, See above */
+#define	PROM_MMU_MODE_EXEC	0x0004	/* Soft: eXecutable, See above */
+#define	PROM_MMU_MODE_RWX_MASK	0x0007	/* Mask for R-W-X bits */
+
+#define	PROM_MMU_MODE_LOCKED	0x0010	/* Read-only: Locked; see above */
+#define	PROM_MMU_MODE_CACHED	0x0020	/* Set means both CV,CP bits */
+#define	PROM_MMU_MODE_EFFECTS	0x0040	/* side Effects bit in MMU */
+#define	PROM_MMU_MODE_GLOBAL	0x0080	/* Global bit */
+#define	PROM_MMU_MODE_INVERT	0x0100	/* Invert Endianness */
+
+/*
+ * resource allocation group: OBP only. (mapping functions are platform
+ * dependent because they use physical address arguments.)
+ */
+extern	caddr_t		prom_map(caddr_t virthint,
+			    unsigned long long physaddr, uint_t size);
+
+/*
+ * prom_alloc is platform dependent and has historical semantics
+ * associated with the align argument and the return value.
+ * prom_malloc is the generic memory allocator.
+ */
+extern	caddr_t		prom_malloc(caddr_t virt, size_t size, uint_t align);
+
+extern	caddr_t		prom_allocate_virt(uint_t align, size_t size);
+extern	caddr_t		prom_claim_virt(size_t size, caddr_t virt);
+extern	void		prom_free_virt(size_t size, caddr_t virt);
+
+extern	int		prom_allocate_phys(size_t size, uint_t align,
+			    unsigned long long *physaddr);
+extern	int		prom_claim_phys(size_t size,
+			    unsigned long long physaddr);
+extern	void		prom_free_phys(size_t size,
+			    unsigned long long physaddr);
+
+extern	int		prom_map_phys(int mode, size_t size, caddr_t virt,
+			    unsigned long long physaddr);
+extern	void		prom_unmap_phys(size_t size, caddr_t virt);
+extern	void		prom_unmap_virt(size_t size, caddr_t virt);
+
+/*
+ * prom_retain allocates or returns retained physical memory
+ * identified by the arguments of name string "id", "size" and "align".
+ */
+extern	int		prom_retain(char *id, size_t size, uint_t align,
+			    unsigned long long *physaddr);
+
+/*
+ * prom_translate_virt returns the physical address and virtualized "mode"
+ * for the given virtual address. After the call, if *valid is non-zero,
+ * a mapping to 'virt' exists and the physical address and virtualized
+ * "mode" were returned to the caller.
+ */
+extern	int		prom_translate_virt(caddr_t virt, int *valid,
+			    unsigned long long *physaddr, int *mode);
+
+/*
+ * prom_modify_mapping changes the "mode" of an existing mapping or
+ * repeated mappings. virt is the virtual address whose "mode" is to
+ * be changed; size is some multiple of the fundamental pagesize.
+ * This method cannot be used to change the pagesize of an MMU mapping,
+ * nor can it be used to Lock a translation into the i or d tlb.
+ */
+extern	int	prom_modify_mapping(caddr_t virt, size_t size, int mode);
+
+/*
+ * Client interfaces for managing the {i,d}tlb handoff to client programs.
+ */
+extern	int		prom_itlb_load(int index,
+			    unsigned long long tte_data, caddr_t virt);
+
+extern	int		prom_dtlb_load(int index,
+			    unsigned long long tte_data, caddr_t virt);
+
+/*
+ * Administrative group: OBP only and SMCC platform specific.
+ * XXX: IDPROM related stuff should be replaced with specific data-oriented
+ * XXX: functions.
+ */
+
+extern	int		prom_heartbeat(int msecs);
+extern	int		prom_get_unum(int syn_code, unsigned long long physaddr,
+				char *buf, uint_t buflen, int *ustrlen);
+extern	int		prom_serengeti_get_ecacheunum(int cpuid,
+				unsigned long long physaddr, char *buf,
+				uint_t buflen, int *ustrlen);
+
+extern	int		prom_getidprom(caddr_t addr, int size);
+extern	int		prom_getmacaddr(ihandle_t hd, caddr_t ea);
+
+/*
+ * CPU Control Group: MP's only.
+ */
+extern	int		prom_startcpu(dnode_t node, caddr_t pc, int arg);
+extern	int		prom_startcpu_bycpuid(int cpuid, caddr_t pc, int arg);
+extern	int		prom_stopcpu_bycpuid(int);
+extern	int		prom_sunfire_cpu_off(void);	/* SunFire only */
+extern	int		prom_wakeupcpu(dnode_t node);
+extern	int		prom_serengeti_wakeupcpu(dnode_t node);
+extern	int		prom_hotaddcpu(int cpuid);
+extern	int		prom_hotremovecpu(int cpuid);
+extern	void		promsafe_pause_cpus(void);
+extern	void		promsafe_xc_attention(cpuset_t cpuset);
+extern	int		prom_serengeti_cpu_off(dnode_t node);
+
+/*
+ * Set trap table
+ */
+extern	void		prom_set_traptable(void *tba_addr);
+
+/*
+ * Power-off
+ */
+extern	void		prom_power_off(void);
+
+/*
+ * sunfire attach/detach
+ */
+extern	int		prom_sunfire_attach_board(uint_t board);
+extern	int		prom_sunfire_detach_board(uint_t board);
+
+/*
+ * Serengeti console switch
+ */
+extern	char		*prom_serengeti_set_console_input(char *new_value);
+
+/*
+ * Serengeti attach/detach
+ */
+extern	int		prom_serengeti_attach_board(uint_t node, uint_t board);
+extern	int		prom_serengeti_detach_board(uint_t node, uint_t board);
+extern	int		prom_serengeti_tunnel_switch(uint_t node, uint_t board);
+
+/*
+ * Starcat-specific routines
+ */
+extern	int		prom_starcat_switch_tunnel(uint_t portid,
+			    uint_t msgtype);
+extern	int		prom_starcat_iosram_read(uint32_t key, uint32_t offset,
+			    uint32_t len, caddr_t buf);
+extern	int		prom_starcat_iosram_write(uint32_t key, uint32_t offset,
+			    uint32_t len, caddr_t buf);
+
+/*
+ * Starfire-specific routines
+ */
+extern	int		prom_starfire_add_brd(uint_t cpuid);
+extern	int		prom_starfire_rm_brd(uint_t brdnum);
+extern	void		prom_starfire_add_cpu(uint_t cpuid);
+extern	void		prom_starfire_rm_cpu(uint_t cpuid);
+extern	int		prom_starfire_move_cpu0(uint_t cpuid);
+extern	void		prom_starfire_init_console(uint_t cpuid);
+
+/*
+ * The client program implementation is required to provide a wrapper
+ * to the client handler, for the 32 bit client program to 64 bit cell-sized
+ * client interface handler (switch stack, etc.).  This function is not
+ * to be used externally!
+ */
+
+extern	int		client_handler(void *cif_handler, void *arg_array);
+
+/*
+ * The 'format' of the "translations" property in the 'mmu' node ...
+ */
+
+struct translation {
+	uint32_t virt_hi;	/* upper 32 bits of vaddr */
+	uint32_t virt_lo;	/* lower 32 bits of vaddr */
+	uint32_t size_hi;	/* upper 32 bits of size in bytes */
+	uint32_t size_lo;	/* lower 32 bits of size in bytes */
+	uint32_t tte_hi;	/* higher 32 bites of tte */
+	uint32_t tte_lo;	/* lower 32 bits of tte */
+};
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _SYS_PROM_PLAT_H */
diff --git a/usr/src/uts/sun4u/sys/pte.h b/usr/src/uts/sun4u/sys/pte.h
new file mode 100644
index 0000000000..157f566725
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/pte.h
@@ -0,0 +1,356 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_PTE_H
+#define	_SYS_PTE_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifndef _ASM
+#include <sys/types.h>
+#endif /* _ASM */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifndef _ASM
+/*
+ * The tte struct is a 64 bit data type.  Since we currently plan to
+ * use a V8 compiler all manipulations in C will be done using the bit fields
+ * or as 2 integers.  In assembly code we will deal with it as a double (using
+ * ldx and stx).  The structure is defined to force a double alignment.
+ * Note that USIIi uses bits <47:40> for diag, and <49:48> are reserved.
+ */
+typedef union {
+	struct tte {
+		uint32_t	v:1;		/* 1=valid mapping */
+		uint32_t	sz:2;		/* 0=8k 1=64k 2=512k 3=4m */
+		uint32_t	nfo:1;		/* 1=no-fault access only */
+
+		uint32_t	ie:1;		/* 1=invert endianness */
+		uint32_t	hmenum:3;	/* sw - # of hment in hme_blk */
+
+		uint32_t	lckcnt:6;	/* sw - tte lock ref cnt */
+		uint32_t	rsv:1;		/* */
+		uint32_t	sz2:1;		/* Panther sz2[48] */
+		uint32_t	diag:5;		/* See USII Note above. */
+		uint32_t	pahi:11;	/* pa[42:32] */
+		uint32_t	palo:19;	/* pa[31:13] */
+		uint32_t	soft1:1;	/* sw bits - unused */
+
+		uint32_t	suspend:1;	/* sw bits - suspended */
+		uint32_t	ref:1;		/* sw - reference */
+		uint32_t	wr_perm:1;	/* sw - write permission */
+		uint32_t	no_sync:1;	/* sw - ghost unload */
+
+		uint32_t	exec_perm:1;	/* sw - execute permission */
+		uint32_t	l:1;		/* 1=lock in tlb */
+		uint32_t	cp:1;		/* 1=cache in ecache, icache */
+		uint32_t	cv:1;		/* 1=cache in dcache */
+
+		uint32_t	e:1;		/* 1=side effect */
+		uint32_t	p:1;		/* 1=privilege required */
+		uint32_t	w:1;		/* 1=writes allowed */
+		uint32_t	g:1;		/* 1=any context matches */
+	} tte_bit;
+	struct {
+		int32_t		inthi;
+		uint32_t	intlo;
+	} tte_int;
+	uint64_t		ll;
+} tte_t;
+
+#define	tte_val 	tte_bit.v		/* use < 0 check in asm */
+#define	tte_size	tte_bit.sz
+#define	tte_size2	tte_bit.sz2
+#define	tte_nfo		tte_bit.nfo
+#define	tte_ie		tte_bit.ie		/* XXX? */
+#define	tte_hmenum	tte_bit.hmenum
+#define	tte_lckcnt	tte_bit.lckcnt
+#define	tte_pahi	tte_bit.pahi
+#define	tte_palo	tte_bit.palo
+#define	tte_suspend	tte_bit.suspend
+#define	tte_ref		tte_bit.ref
+#define	tte_wr_perm	tte_bit.wr_perm
+#define	tte_no_sync	tte_bit.no_sync
+#define	tte_exec_perm	tte_bit.exec_perm
+#define	tte_lock	tte_bit.l
+#define	tte_cp		tte_bit.cp
+#define	tte_cv		tte_bit.cv
+#define	tte_se		tte_bit.e
+#define	tte_priv	tte_bit.p
+#define	tte_hwwr	tte_bit.w
+#define	tte_glb		tte_bit.g
+
+#define	tte_inthi	tte_int.inthi
+#define	tte_intlo	tte_int.intlo
+
+#endif /* !_ASM */
+
+/*
+ * Defines for valid, sz, sz2 fields in tte.
+ * The TTE_CSZ macro combines the sz and sz2 fields.
+ */
+#define	TTE8K			0x0
+#define	TTE64K			0x1
+#define	TTE512K			0x2
+#define	TTE4M			0x3
+#define	TTE32M			0x4
+#define	TTE256M			0x5
+#define	TTESZ_VALID		0x4
+
+#define	TTE_SZ_SHFT_INT		29
+#define	TTE_SZ_SHFT		32+29
+#define	TTE_SZ_BITS		0x3
+
+#define	TTE_SZ2_SHFT_INT	14
+#define	TTE_SZ2_SHFT		32+14
+#define	TTE_SZ2_BITS		0x4
+#define	TTE_CSZ_BITS		0x7
+#define	TTE_CSZ(ttep)	(((ttep)->tte_size2 << 2) | ((ttep)->tte_size))
+
+/*
+ * the tte lock cnt now lives in the hme blk and is 16 bits long. See
+ * comments in hme_blk declaration.
+ */
+#define	MAX_TTE_LCKCNT		(0x10000 - 1)
+
+#define	TTE_BSZS_SHIFT(sz)	((sz) * 3)
+#define	TTEBYTES(sz)		(MMU_PAGESIZE << TTE_BSZS_SHIFT(sz))
+#define	TTEPAGES(sz)		(1 << TTE_BSZS_SHIFT(sz))
+#define	TTE_PAGE_SHIFT(sz)	(MMU_PAGESHIFT + TTE_BSZS_SHIFT(sz))
+#define	TTE_PAGE_OFFSET(sz)	(TTEBYTES(sz) - 1)
+#define	TTE_PAGEMASK(sz)	(~TTE_PAGE_OFFSET(sz))
+#define	TTE_PFNMASK(sz)		(~(TTE_PAGE_OFFSET(sz) >> MMU_PAGESHIFT))
+
+#define	TTE_PA_LSHIFT		21	/* used to do sllx on tte to get pa */
+
+#ifndef _ASM
+
+#define	TTE_PASHIFT		19	/* used to manage pahi and palo */
+#define	TTE_PALOMASK		((1 << TTE_PASHIFT) -1)
+/* PFN is defined as bits [40-13] of the physical address */
+#define	TTE_TO_TTEPFN(ttep)						\
+	((((ttep)->tte_pahi << TTE_PASHIFT) | (ttep)->tte_palo) &	\
+	TTE_PFNMASK(TTE_CSZ(ttep)))
+/*
+ * This define adds the vaddr page offset to obtain a correct pfn
+ */
+#define	TTE_TO_PFN(vaddr, ttep)						\
+	(sfmmu_ttetopfn(ttep, vaddr))
+
+#define	PFN_TO_TTE(entry, pfn) {		\
+	entry.tte_pahi = pfn >> TTE_PASHIFT;	\
+	entry.tte_palo = pfn & TTE_PALOMASK;	\
+	}
+
+#endif /* !_ASM */
+
+/*
+ * The tte defines are separated into integers because the compiler doesn't
+ * support 64bit defines.
+ */
+/* Defines for tte using inthi */
+#define	TTE_VALID_INT			0x80000000
+#define	TTE_NFO_INT			0x10000000
+#define	TTE_NFO_SHIFT			0x3	/* makes for an easy check */
+#define	TTE_IE_INT			0x08000000
+
+/* Defines for tte using intlo */
+#define	TTE_SUSPEND_SHIFT		0
+#define	TTE_SUSPEND			0x00000800
+#define	TTE_REF_INT			0x00000400
+#define	TTE_WRPRM_INT			0x00000200
+#define	TTE_NOSYNC_INT			0x00000100
+#define	TTE_EXECPRM_INT			0x00000080
+#define	TTE_LCK_INT			0x00000040
+#define	TTE_CP_INT			0x00000020
+#define	TTE_CV_INT			0x00000010
+#define	TTE_SIDEFF_INT			0x00000008
+#define	TTE_PRIV_INT			0x00000004
+#define	TTE_HWWR_INT			0x00000002
+#define	TTE_GLB_INT			0x00000001
+
+#define	TTE_PROT_INT			(TTE_WRPRM_INT | TTE_PRIV_INT)
+
+/*
+ * Define to clear the high-order 2 bits of the 43-bit PA in a tte.  The
+ * Spitfire tte has PFN in [40-13] and uses [42-41] as part of Diag bits.
+ */
+#define	TTE_SPITFIRE_PFNHI_CLEAR	0x3
+#define	TTE_SPITFIRE_PFNHI_SHIFT	32+9
+
+#ifndef ASM
+
+/* Defines to help build ttes using inthi */
+#define	TTE_SZ_INT(sz)	\
+	((sz & TTE_SZ_BITS) << TTE_SZ_SHFT_INT) | \
+	((sz & TTE_SZ2_BITS) << TTE_SZ2_SHFT_INT)
+#define	TTE_HMENUM_INT(hmenum)		((hmenum) << 24)
+/* XXX PFN is defined as bits [40-13] of the physical address */
+#define	TTE_PFN_INTHI(pfn)		((pfn) >> TTE_PASHIFT)
+#define	TTE_VALID_CHECK(attr)	\
+	(((attr) & PROT_ALL) ? TTE_VALID_INT : 0)
+#define	TTE_IE_CHECK(attr)	\
+	(((attr) & HAT_STRUCTURE_LE) ? TTE_IE_INT : 0)
+#define	TTE_NFO_CHECK(attr)	\
+	(((attr) & HAT_NOFAULT) ? TTE_NFO_INT : 0)
+
+/* Defines to help build ttes using intlo */
+#define	TTE_PFN_INTLO(pfn)		(((pfn) & TTE_PALOMASK) << 13)
+#define	TTE_WRPRM_CHECK(attr)	 \
+	(((attr) & PROT_WRITE) ? TTE_WRPRM_INT : 0)
+#define	TTE_EXECPRM_CHECK(attr)	 \
+	(((attr) & PROT_EXEC) ? TTE_EXECPRM_INT : 0)
+#define	TTE_NOSYNC_CHECK(attr)	 \
+	(((attr) & HAT_NOSYNC) ? TTE_NOSYNC_INT : 0)
+#define	TTE_CP_CHECK(attr)	\
+	(((attr) & SFMMU_UNCACHEPTTE) ? 0: TTE_CP_INT)
+#define	TTE_CV_CHECK(attr)	\
+	(((attr) & SFMMU_UNCACHEVTTE) ? 0: TTE_CV_INT)
+#define	TTE_SE_CHECK(attr)	\
+	(((attr) & SFMMU_SIDEFFECT) ? TTE_SIDEFF_INT : 0)
+#define	TTE_PRIV_CHECK(attr)	\
+	(((attr) & PROT_USER) ? 0 : TTE_PRIV_INT)
+
+#define	MAKE_TTEATTR_INTHI(attr)				\
+	(TTE_VALID_CHECK(attr) | TTE_NFO_CHECK(attr) | TTE_IE_CHECK(attr))
+
+#define	MAKE_TTE_INTHI(pfn, attr, sz, hmenum)			\
+	(MAKE_TTEATTR_INTHI(attr) | TTE_SZ_INT(sz) |		\
+	TTE_HMENUM_INT(hmenum) | TTE_PFN_INTHI(pfn))
+
+#define	MAKE_TTEATTR_INTLO(attr)					\
+	(TTE_WRPRM_CHECK(attr) | TTE_NOSYNC_CHECK(attr) |		\
+	TTE_CP_CHECK(attr) | TTE_CV_CHECK(attr) | TTE_SE_CHECK(attr) |	\
+	TTE_PRIV_CHECK(attr) | TTE_EXECPRM_CHECK(attr))
+
+#define	MAKE_TTE_INTLO(pfn, attr, sz, hmenum)				\
+	(TTE_PFN_INTLO(pfn) | TTE_REF_INT | MAKE_TTEATTR_INTLO(attr))
+
+#define	TTEINTHI_ATTR	(TTE_VALID_INT | TTE_IE_INT | TTE_NFO_INT)
+
+#define	TTEINTLO_ATTR							\
+	(TTE_WRPRM_INT | TTE_NOSYNC_INT | TTE_CP_INT | TTE_CV_INT |	\
+	TTE_SIDEFF_INT | TTE_PRIV_INT | TTE_EXECPRM_INT)
+
+#define	MAKE_TTE_MASK(ttep)			\
+	{					\
+		(ttep)->tte_bit.v = 1;		\
+		(ttep)->tte_bit.sz = 3;		\
+		(ttep)->tte_bit.nfo = 1;	\
+		(ttep)->tte_bit.ie = 1;		\
+		(ttep)->tte_bit.pahi = 0x3ff;	\
+		(ttep)->tte_bit.palo = 0x7ffff;	\
+		(ttep)->tte_bit.l = 1;		\
+		(ttep)->tte_bit.cp = 1;		\
+		(ttep)->tte_bit.cv = 1;		\
+		(ttep)->tte_bit.e = 1;		\
+		(ttep)->tte_bit.p = 1;		\
+		(ttep)->tte_bit.w = 1;		\
+		(ttep)->tte_bit.g = 1;		\
+	}
+
+/*
+ * Defines to check/set TTE bits.
+ */
+#define	TTE_IS_VALID(ttep)	((ttep)->tte_inthi < 0)
+#define	TTE_SET_INVALID(ttep)	((ttep)->tte_val = 0)
+#define	TTE_IS_8K(ttep)		(TTE_CSZ(ttep) == TTE8K)
+#define	TTE_IS_WRITABLE(ttep)	((ttep)->tte_wr_perm)
+#define	TTE_IS_EXECUTABLE(ttep)	((ttep)->tte_exec_perm)
+#define	TTE_IS_PRIVILEGED(ttep)	((ttep)->tte_priv)
+#define	TTE_IS_NOSYNC(ttep)	((ttep)->tte_no_sync)
+#define	TTE_IS_LOCKED(ttep)	((ttep)->tte_lock)
+#define	TTE_IS_GLOBAL(ttep)	((ttep)->tte_glb)
+#define	TTE_IS_SIDEFFECT(ttep)	((ttep)->tte_se)
+#define	TTE_IS_NFO(ttep)	((ttep)->tte_nfo)
+
+#define	TTE_IS_REF(ttep)	((ttep)->tte_ref)
+#define	TTE_IS_MOD(ttep)	((ttep)->tte_hwwr)
+#define	TTE_IS_IE(ttep)		((ttep)->tte_ie)
+#define	TTE_SET_SUSPEND(ttep)	((ttep)->tte_suspend = 1)
+#define	TTE_CLR_SUSPEND(ttep)	((ttep)->tte_suspend = 0)
+#define	TTE_IS_SUSPEND(ttep)	((ttep)->tte_suspend)
+#define	TTE_SET_REF(ttep)	((ttep)->tte_ref = 1)
+#define	TTE_CLR_REF(ttep)	((ttep)->tte_ref = 0)
+#define	TTE_SET_LOCKED(ttep)	((ttep)->tte_lock = 1)
+#define	TTE_CLR_LOCKED(ttep)	((ttep)->tte_lock = 0)
+#define	TTE_SET_MOD(ttep)	((ttep)->tte_hwwr = 1)
+#define	TTE_CLR_MOD(ttep)	((ttep)->tte_hwwr = 0)
+#define	TTE_SET_RM(ttep)						\
+	(((ttep)->tte_intlo) = (ttep)->tte_intlo | TTE_HWWR_INT | TTE_REF_INT)
+#define	TTE_CLR_RM(ttep)						\
+	(((ttep)->tte_intlo) = (ttep)->tte_intlo &			\
+	~(TTE_HWWR_INT | TTE_REF_INT))
+
+#define	TTE_SET_WRT(ttep)	((ttep)->tte_wr_perm = 1)
+#define	TTE_CLR_WRT(ttep)	((ttep)->tte_wr_perm = 0)
+#define	TTE_SET_EXEC(ttep)	((ttep)->tte_exec_perm = 1)
+#define	TTE_CLR_EXEC(ttep)	((ttep)->tte_exec_perm = 0)
+#define	TTE_SET_PRIV(ttep)	((ttep)->tte_priv = 1)
+#define	TTE_CLR_PRIV(ttep)	((ttep)->tte_priv = 0)
+
+#define	TTE_IS_VCACHEABLE(ttep)		((ttep)->tte_cv)
+#define	TTE_SET_VCACHEABLE(ttep)	((ttep)->tte_cv = 1)
+#define	TTE_CLR_VCACHEABLE(ttep)	((ttep)->tte_cv = 0)
+#define	TTE_IS_PCACHEABLE(ttep)		((ttep)->tte_cp)
+#define	TTE_SET_PCACHEABLE(ttep)	((ttep)->tte_cp = 1)
+#define	TTE_CLR_PCACHEABLE(ttep)	((ttep)->tte_cp = 0)
+
+
+#define	KPM_TTE_VCACHED(tte64, pfn, tte_sz)				\
+	tte64 = (((uint64_t)(TTE_VALID_INT |				\
+	    (tte_sz) << TTE_SZ_SHFT_INT)) << 32) |			\
+	    (((pfn) >> TTE_BSZS_SHIFT(tte_sz)) <<			\
+	    (TTE_BSZS_SHIFT(tte_sz) + MMU_PAGESHIFT)) |			\
+	    (TTE_CP_INT | TTE_CV_INT | TTE_PRIV_INT | TTE_HWWR_INT)
+
+#define	KPM_TTE_VUNCACHED(tte64, pfn, tte_sz)				\
+	tte64 = (((uint64_t)(TTE_VALID_INT |				\
+	    (tte_sz) << TTE_SZ_SHFT_INT)) << 32) |			\
+	    (((pfn) >> TTE_BSZS_SHIFT(tte_sz)) <<			\
+	    (TTE_BSZS_SHIFT(tte_sz) + MMU_PAGESHIFT)) |			\
+	    (TTE_CP_INT | TTE_PRIV_INT | TTE_HWWR_INT)
+
+/*
+ * This define provides a generic method to set and clear multiple tte flags.
+ * A bitmask of all flags to be affected is passed in "flags" and a bitmask
+ * of the new values is passed in "newflags".
+ */
+#define	TTE_SET_LOFLAGS(ttep, flags, newflags)				\
+	((ttep)->tte_intlo = ((ttep)->tte_intlo & ~(flags)) | (newflags))
+
+#define	TTE_GET_LOFLAGS(ttep, flags)	((ttep)->tte_intlo & flags)
+
+#endif /* !_ASM */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* !_SYS_PTE_H */
diff --git a/usr/src/uts/sun4u/sys/rmc_comm_dp.h b/usr/src/uts/sun4u/sys/rmc_comm_dp.h
new file mode 100644
index 0000000000..6450d43012
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/rmc_comm_dp.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright 2001-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_RMC_COMM_DP_H
+#define	_SYS_RMC_COMM_DP_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+
+#include <sys/rmc_comm_lproto.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * buffer size (used for tx/rx operations)
+ */
+#define	DP_BUFFER_SIZE	2048
+
+/*
+ * Number of tx/rx buffers. there are 2 (static) buffers: receive buffer and
+ * send buffer. These buffers are basically used by the protocol to packetize
+ * a message to be sent OR to collect data received from the serial device.
+ * Currently, we just need two for send and receive operations respectively
+ * since there is only one request/response session per time (i.e. a new
+ * session is not started until the previous one has not finished)
+ */
+#define	DP_BUFFER_COUNT		2
+
+#define	DP_TX_BUFFER		0
+#define	DP_RX_BUFFER		1
+
+/*
+ * Tx/Rx buffers.
+ */
+typedef struct dp_buffer {
+	boolean_t in_use;
+	uint8_t buf[DP_BUFFER_SIZE];
+} dp_buffer_t;
+
+/*
+ * Data structure used to collect data from the serial device and to
+ * assemble protocol packets
+ */
+
+/*
+ * The possible states the message receiver can be in:
+ */
+#define	WAITING_FOR_SYNC	0
+#define	WAITING_FOR_SYNC_ESC	1
+#define	WAITING_FOR_HDR		2
+#define	RECEIVING_HDR		3
+#define	RECEIVING_HDR_ESC	4
+#define	RECEIVING_BODY		5
+#define	RECEIVING_BODY_ESC	6
+#define	N_RX_STATES		7
+
+/*
+ * This is the structure passed between the message receiver state routines.
+ * It keeps track of all the state of a message that is in the process of
+ * being received.
+ */
+typedef struct dp_packet {
+	uint8_t rx_state;	/* Current state of receive engine. */
+	uint8_t *inbuf;		/* Input characters to be processed. */
+	int16_t inbuflen;	/* Number of input characters. */
+	uint8_t *buf;		/* Buffer used to receive current message. */
+	int16_t bufpos;		/* Position in buffer. */
+	int16_t full_length;	/* Full length of this message. */
+} dp_packet_t;
+
+
+/*
+ * message data structure used to send/receive data
+ */
+typedef struct dp_message {
+
+	uint8_t   msg_type;	/* message type */
+	uint8_t  *msg_buf;	/* message buffer */
+	uint16_t  msg_bufsiz;	/* size of the buffer */
+	int16_t   msg_msglen;	/* message length */
+
+} dp_message_t;
+
+/*
+ * structure used by the protocol to send (and, eventually re-send...)
+ * messages to the remote side. It keeps the status of the data transfer
+ * (message sent, reply received, etc.). It is also used to match
+ * request/response
+ */
+
+typedef struct dp_req_resp {
+
+	uint8_t		flags;		/* status of the data transfer */
+
+#define	MSG_ERROR 	0x01
+#define	MSG_SENT 	0x02
+#define	MSG_ACKED 	0x04
+#define	MSG_REPLY_RXED	0x08
+#define	MSG_NAKED	0x10
+#define	MSG_RESET	0x20
+#define	MSG_SENT_BP	0x40
+#define	MSG_RXED_BP	0x80
+
+	uint8_t		error_status;   /* error code */
+
+	uint8_t		retries_left;   /* number of retries left */
+
+	kcondvar_t  	cv_wait_reply[1];	/* cv variable used to signal */
+						/* threads waiting for a */
+						/* reply */
+
+	dp_message_t	request;	/* request buffer */
+
+	dp_message_t	response;	/* response buffer */
+
+} dp_req_resp_t;
+
+
+/*
+ * interrupt handler prototype (asynchronous messages notification)
+ */
+typedef uint_t (*rmc_comm_intrfunc_t)(caddr_t);
+
+/*
+ * data structure used to deal with asynchronous notification (requests)
+ * from the remote side
+ */
+typedef struct dp_msg_intr {
+
+	rmc_comm_intrfunc_t	intr_handler;	/* interrupt handler */
+
+	ddi_softintr_t		intr_id;	/* soft intr. id */
+
+	uint8_t			intr_msg_type;	/* message type */
+
+	caddr_t			intr_arg;	/* message buffer containing */
+						/* the expected message type */
+
+	kmutex_t		*intr_lock;	/* for state flag below */
+	uint_t			*intr_state;	/* interrupt handler state */
+
+} dp_msg_intr_t;
+
+/*
+ * data protocol structure
+ */
+
+typedef struct rmc_comm_dp_state {
+
+	/*
+	 * data protcol mutex (initialized using <dp_iblk>)
+	 */
+	kmutex_t		dp_mutex[1];
+	ddi_iblock_cookie_t	dp_iblk;
+
+	boolean_t	data_link_ok;	/* tells whether the data link has */
+					/* has been established */
+
+	boolean_t	pending_request;	/* tells if a request is */
+						/* already being processed */
+
+	uint8_t		last_tx_seqid;	/* sequence ID of last message */
+					/* transmitted */
+	uint8_t		last_rx_seqid;  /* sequence ID of last message */
+					/* received */
+	uint8_t		last_rx_ack;    /* last message acknowledged by */
+					/* remote side */
+
+	timeout_id_t	timer_link_setup;	/* timer used to set up the */
+						/* data link at regular */
+						/* intervals when the link is */
+						/* down */
+	timeout_id_t	timer_delay_ack;	/* timer used to wait a 'bit' */
+						/* before acknowledging a */
+						/* received message. In the */
+						/* meantime a request can be */
+						/* sent from this side and, */
+						/* hence, acnowledge that */
+						/* message */
+
+	kcondvar_t	cv_ok_to_send[1];	/* cv variable used to wait */
+						/* until it is possible to */
+						/* send the request (no */
+						/* pending request */
+
+	dp_packet_t	dp_packet;		/* used to assemble protocol */
+						/* packet from data received */
+						/* from the serial device */
+
+	dp_req_resp_t	req_resp;		/* request/response data */
+						/* structure */
+
+	dp_msg_intr_t	msg_intr;		/* messages for which layered */
+						/* drivers have registered */
+						/* for an async notification */
+						/* (soft.intr.) */
+
+	dp_buffer_t	dp_buffers[DP_BUFFER_COUNT]; /* protocol buffer  */
+						/* pool used for    */
+						/* tx/rx operations */
+
+	/* statistical information */
+
+	uint16_t	reset_cnt;
+	uint16_t	nak_cnt;
+	uint16_t	start_cnt;
+	uint16_t	stack_cnt;
+	uint16_t	retries_cnt;
+	uint16_t	crcerr_cnt;
+
+} rmc_comm_dp_state_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_RMC_COMM_DP_H */
diff --git a/usr/src/uts/sun4u/sys/rmc_comm_drvintf.h b/usr/src/uts/sun4u/sys/rmc_comm_drvintf.h
new file mode 100644
index 0000000000..9960b9a60c
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/rmc_comm_drvintf.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2001-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_RMC_COMM_DRVINTF_H
+#define	_SYS_RMC_COMM_DRVINTF_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+
+#include <sys/rmc_comm_hproto.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * this struct is used by client programs to request message services:
+ */
+typedef struct rmc_comm_msg {
+
+	uint8_t	msg_type;	/* message type */
+	int16_t	msg_len;	/* size of the message buffer */
+	int16_t	msg_bytes;	/* number of bytes returned */
+	caddr_t	msg_buf;	/* message buffer */
+
+} rmc_comm_msg_t;
+
+
+/* list of error codes for RMC comm */
+
+#define	RCNOERR		(0)	/* cmd sent, reply/ACK received */
+#define	RCENOSOFTSTATE	(-1)	/* invalid/NULL soft state structure */
+#define	RCENODATALINK	(-2)	/* data link down */
+#define	RCENOMEM	(-3)	/* no memory */
+#define	RCECANTRESEND	(-4)	/* resend failed */
+#define	RCEMAXRETRIES	(-5)	/* maximum number of retries exceeded */
+#define	RCETIMEOUT	(-6)	/* timeout error */
+#define	RCEINVCMD	(-7)	/* invalid data protocol command */
+#define	RCEINVARG	(-8)	/* invalid argument(s) */
+#define	RCECANTREGINTR	(-9)	/* interrupt handler registration failure */
+#define	RCEALREADYREG	(-10)	/* interrupt handler already registered */
+#define	RCEREPTOOBIG	(-11)	/* reply message too big */
+#define	RCEGENERIC	(-15)	/* generic error */
+
+/*
+ * possible value for the 'state' variable provided by the driver
+ * (registration for an asynchronous message notification -
+ * see rmc_comm_reg_intr). The state variable tells whether the driver
+ * interrupt handler is currently processing an asynchronous notification or
+ * not.
+ */
+
+#define	RMC_COMM_INTR_IDLE	0x01
+#define	RMC_COMM_INTR_RUNNING	0x02
+
+
+/*
+ * structure used to store a request (only one per time!) that is delivered
+ * later. Some leaf driver (TOD for instance) cannot wait for the completion
+ * of the trasmission of a request message so they calls a specific interface
+ * (rmc_comm_request_nowait) which stores the request in this structure and
+ * signals a thread to deliver the request asynchronously.
+ */
+typedef struct rmc_comm_drvintf_state {
+
+	kt_did_t	dreq_tid;
+	kmutex_t	dreq_mutex[1];
+	kcondvar_t	dreq_sig_cv[1];
+	uint8_t		dreq_state;
+	rmc_comm_msg_t	dreq_request;
+	char		dreq_request_buf[ DP_MAX_MSGLEN ];
+
+} rmc_comm_drvintf_state_t;
+
+/*
+ * possible value for dreq_state field
+ */
+enum rmc_comm_dreq_state {
+	RMC_COMM_DREQ_ST_NOTSTARTED = 0,
+	RMC_COMM_DREQ_ST_READY,
+	RMC_COMM_DREQ_ST_WAIT,
+	RMC_COMM_DREQ_ST_PROCESS,
+	RMC_COMM_DREQ_ST_EXIT
+};
+
+/*
+ * default timeout value for requests sent from the thread
+ */
+#define	RMC_COMM_DREQ_DEFAULT_TIME	10000
+
+/*
+ * flag which tells if a request has to be sent even if a pending request is
+ * in process. This flag must only be used when trying to send a request in
+ * critical condition (while the system is shutting down for instance and the
+ * CPU signature has to be sent). Otherwise, the request is stored in a
+ * temporary location and delivered by a thread.
+ */
+
+#define	RMC_COMM_DREQ_URGENT		0x01
+
+
+/* function prototypes (interface to the drivers) */
+
+int rmc_comm_request_response(rmc_comm_msg_t *, rmc_comm_msg_t *, uint32_t);
+int rmc_comm_request_nowait(rmc_comm_msg_t *, uint8_t);
+int rmc_comm_request_response_bp(rmc_comm_msg_t *, rmc_comm_msg_t *, uint32_t);
+int rmc_comm_reg_intr(uint8_t, rmc_comm_intrfunc_t, rmc_comm_msg_t *, uint_t *,
+			kmutex_t *);
+int rmc_comm_unreg_intr(uint8_t, rmc_comm_intrfunc_t);
+int rmc_comm_send_srecord_bp(caddr_t, int, rmc_comm_msg_t *, uint32_t);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_RMC_COMM_DRVINTF_H */
diff --git a/usr/src/uts/sun4u/sys/rmc_comm_hproto.h b/usr/src/uts/sun4u/sys/rmc_comm_hproto.h
new file mode 100644
index 0000000000..218fc1154b
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/rmc_comm_hproto.h
@@ -0,0 +1,909 @@
+/*
+ * Copyright 2001-2003 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_RMC_COMM_HPROTO_H
+#define	_SYS_RMC_COMM_HPROTO_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * data types used in the data protocol fields
+ */
+
+typedef unsigned char rsci8;
+typedef unsigned short rsci16;
+
+typedef short rscis16;
+
+#ifdef _LP64
+typedef unsigned int rsci32;
+typedef unsigned long rsci64;
+#else
+typedef unsigned long rsci32;
+typedef unsigned long long rsci64;
+#endif
+
+/*
+ * handle definition. Handles are used in the high-level data protocol
+ * to identify FRU, sensors (temperature, voltage), and so on.
+ */
+
+typedef rsci16 dp_handle_t;
+
+#define	DP_NULL_HANDLE		0xffff
+
+#define	DP_MAX_HANDLE_NAME	32
+
+#define	DP_NULL_MSG		0x00
+
+/*
+ * Supported message types and associated data types:
+ */
+
+#define	DP_RESET_RSC		0x7A
+
+#define	DP_RESET_RSC_R		0x5A
+
+#define	DP_UPDATE_FLASH		0x66
+
+#define	DP_UPDATE_FLASH_R	0x46
+typedef struct dp_update_flash_r {
+	rsci32	status;		/* completion code */
+} dp_update_flash_r_t;
+
+#define	DP_RUN_TEST		0x74
+typedef struct dp_run_test {
+	rsci32	testno;		/* test number to run; see below. */
+	rsci32	param_len;	/* # bytes in test parameter data. */
+} dp_run_test_t;
+/* followed by test parameters; see individual tests below. */
+
+#define	DP_RUN_TEST_R		0x54
+typedef struct dp_run_test_r {
+	rsci32	status;		/* 0 = test passed, otherwise see failure */
+				/* codes below. */
+	rsci32	idatalen;	/* # items in input data array */
+	rsci32	odatalen;	/* # items in output data array */
+#define	DP_MAX_RUN_TEST_DATALEN (DP_MAX_MSGLEN-32)/2
+	rsci8	idata[DP_MAX_RUN_TEST_DATALEN];	/* input data array */
+	rsci8	odata[DP_MAX_RUN_TEST_DATALEN];	/* output data array */
+} dp_run_test_r_t;
+
+#define	RSC_TEST_PASSED		0
+#define	RSC_TEST_SW_FAILURE	1
+#define	RSC_TEST_BAD_DATA	2
+#define	RSC_TEST_NO_RESPONSE	3
+#define	RSC_TEST_BAD_CRC	4
+#define	RSC_TEST_BAD_PARAMS	5
+#define	RSC_TEST_NO_DEVICE	6
+#define	RSC_TEST_DEV_SETUP_FAIL	7
+#define	RSC_TEST_MEM_ALLOC_FAIL	8
+#define	RSC_TEST_ENET_ADDR_FAIL	9
+#define	RSC_TEST_DEV_INFO_FAIL	10
+#define	RSC_TEST_NYI		255
+
+#define	DP_RSC_STATUS		0x73
+
+#define	DP_RSC_STATUS_R		0x53
+typedef struct dp_rsc_status_r {
+/* The first six fields here must not be changed to ensure that they  */
+/* are the same in all versions of RSC, most notably when compared to */
+/* 1.x. New fields must be added to the end of the structure. */
+	rsci16	main_rev_major;
+	rsci16	main_rev_minor;
+	rsci16	bootmon_rev_major;
+	rsci16	bootmon_rev_minor;
+	rsci16	post_status;
+	rsci16	nusers;		/* number of users currently logged in to */
+				/* CLI.  */
+/* Any new fields in the structure may be added after this point ONLY! */
+	rsci16	release_rev_major;
+	rsci16	release_rev_minor;
+	rsci16	release_rev_micro;
+	rsci16	main_rev_micro;
+	rsci16	bootmon_rev_micro;
+	rsci16	hardware_rev;
+
+	rsci32 bm_cksum;
+	rsci8  rsc_build;
+	char creationDate[256];
+	rsci32 fw_cksum;
+	rsci32 sys_mem;
+	rsci32 nvram_version;
+
+} dp_rsc_status_r_t;
+
+#define	DP_SET_CFGVAR		0x76
+typedef struct dp_set_cfgvar {
+	rsci32	hidden;		/* boolean */
+} dp_set_cfgvar_t;
+
+/* Data is variable name & new value as zero-terminated ascii strings. */
+
+#define	DP_SET_CFGVAR_R		0x56
+typedef struct dp_set_cfgvar_r {
+	rsci32	status;		/* completion code */
+} dp_set_cfgvar_r_t;
+
+#define	DP_GET_CFGVAR		0x67
+/* Data is variable name as zero-terminated ascii string. */
+
+#define	DP_GET_CFGVAR_R		0x47
+typedef struct dp_get_cfgvar_r {
+	rsci32	status;		/* completion code */
+} dp_get_cfgvar_r_t;
+/* followed by value of variable as a zero-terminated ascii string. */
+
+#define	DP_GET_CFGVAR_NAME	0x6E
+/*
+ * Data is variable name as zero-terminated ascii string.  A zero-length
+ * string means 'return the name of the "first" variable.'
+ */
+
+#define	DP_GET_CFGVAR_NAME_R	0x4E
+typedef struct dp_get_cfgvar_name_r {
+	rsci32	status;		/* completion code */
+} dp_get_cfgvar_name_r_t;
+/* followed by name of "next" variable as a zero-terminated ascii string. */
+
+#define	DP_SET_DATE_TIME		0x64
+#define	DP_SET_DATE_TIME_IGNORE_FIELD	0xFFFF
+typedef struct dp_set_date_time {
+	rsci32	year;		/* Full year, IE 1997 */
+	rsci32	month;		/* 1 = Jan, 2 = Feb, etc. */
+	rsci32	day;		/* Day of the month, 1 to 31. */
+	rsci32	hour;		/* 0 to 23 */
+	rsci32	minute;		/* 0 to 59 */
+	rsci32	second;		/* 0 to 59 */
+} dp_set_date_time_t;
+
+#define	DP_SET_DATE_TIME_R	0x44
+typedef struct dp_set_date_time_r {
+	rsci32	status;		/* 0 - succes, non-zero - fail. */
+} dp_set_date_time_r_t;
+
+#define	DP_GET_DATE_TIME	0x65
+#define	DP_GET_DATE_TIME_R	0x45
+typedef struct dp_get_date_time_r {
+	rsci32	status;		/* completion code */
+	rsci32	current_datetime; /* in Unix format */
+} dp_get_date_time_r_t;
+/* followed by the date represented as a zero-terminated ascii string. */
+
+
+#define	DP_SEND_ALERT		0x61
+typedef struct dp_send_alert {
+	rsci32	critical; /* boolean */
+} dp_send_alert_t;
+
+#define	DP_SEND_ALERT_R		0x41
+typedef struct dp_send_alert_r {
+	rsci32	status;		/* completion code */
+} dp_send_alert_r_t;
+
+#define	DP_GET_TEMP		0x78
+
+#define	DP_GET_TEMP_R		0x58
+typedef struct dp_get_temp_r {
+	rsci32	status;
+	rsci32	current_temp;
+} dp_get_temp_r_t;
+
+#define	DP_GET_SDP_VERSION	0x7B
+
+#define	DP_GET_SDP_VERSION_R	0x5B
+typedef struct dp_get_sdp_version_r {
+	rsci32	version;
+} dp_get_sdp_version_r_t;
+
+#define	DP_GET_TOD_CLOCK	0x7C
+
+#define	DP_GET_TOD_CLOCK_R	0x5C
+typedef struct dp_get_tod_clock_r {
+	rsci32	current_tod;
+} dp_get_tod_clock_r_t;
+
+#define	DP_MAX_LOGSIZE		(DP_MAX_MSGLEN-24)
+
+#define	DP_GET_EVENT_LOG	0x7D
+
+#define	DP_GET_EVENT_LOG_R	0x5D
+typedef struct dp_get_event_log_r {
+	rsci32	entry_count;
+	rsci8	data[DP_MAX_LOGSIZE];
+} dp_get_event_log_r_t;
+
+typedef struct dp_event_log_entry {
+	rsci32	eventTime;
+	rsci32	eventId;
+	rsci32	paramLen;
+	char	param[256];
+} dp_event_log_entry_t;
+
+#define	DP_GET_PCMCIA_INFO	0x7E
+
+#define	DP_GET_PCMCIA_INFO_R	0x5E
+typedef struct dp_get_pcmcia_info_r {
+	rsci32	card_present;	/* true=present, false=no card */
+	rsci32	idInfoLen;
+	rsci8	idInfo[256];
+} dp_get_pcmcia_info_r_t;
+
+
+#define	DP_USER_MAX		16
+#define	DP_USER_NAME_SIZE	16
+
+/* User sub-commands */
+#define	DP_USER_CMD_ADD		0x1
+#define	DP_USER_CMD_DEL		0x2
+#define	DP_USER_CMD_SHOW	0x3
+#define	DP_USER_CMD_PASSWORD	0x4
+#define	DP_USER_CMD_PERM	0x5
+
+/*
+ * The following fields are used to set the user permissions.
+ * Each must be represented as a single bit in the parm field.
+ */
+#define	DP_USER_PERM_C		0x1
+#define	DP_USER_PERM_U		0x2
+#define	DP_USER_PERM_A		0x4
+#define	DP_USER_PERM_R		0x8
+
+/*
+ * values for parm for CMD_SHOW.  Anything other than 0 will show
+ * the user # up to and including DP_USER_MAX
+ */
+#define	DP_USER_SHOW_USERNAME	0x0
+
+/* Error values for status */
+#define	DP_ERR_USER_FULL	0x1  /* No free user slots */
+#define	DP_ERR_USER_NONE	0x2  /* User does not exist */
+#define	DP_ERR_USER_BAD		0x3  /* Malformed username */
+#define	DP_ERR_USER_NACT	0x4  /* user # not activated */
+#define	DP_ERR_USER_THERE	0x5  /* user already registered */
+#define	DP_ERR_USER_PASSWD	0x6  /* invalid password */
+#define	DP_ERR_USER_WARNING	0x7  /* Malformed username warning */
+#define	DP_ERR_USER_NYI		0xFD /* Not yet implemented */
+#define	DP_ERR_USER_UNDEF	0xFE /* Undefine error */
+#define	DP_ERR_USER_CMD		0xFF /* Invalid Command */
+
+#define	DP_USER_ADM		0x50
+/*
+ * The parm field is used by the permission command to set specific
+ *  permissions.  The parm field is also used by the show command to
+ * indicate if the user name is specified or not.
+ */
+typedef struct dp_user_adm {
+	rsci32	command;
+	rsci32	parm;
+} dp_user_adm_t;
+/*
+ * followed by zero-terminated ascii strings.  All user commands
+ * are followed by the username. The password command is also
+ * followed by the password.
+ */
+
+#define	DP_USER_ADM_R		0x51
+/*
+ * the response field is used to return the user permissions
+ * for the user permissions command. The response is also used
+ * to echo back the user selection for the show command.
+ */
+typedef struct dp_user_adm_r {
+	rsci32	status;		/* completion code */
+	rsci32  command;	/* echo back adm command */
+	rsci32	response;
+} dp_user_adm_r_t;
+/* followed by a zero-terminated ascii string for the show command.  */
+
+
+#define	DP_MODEM_PASS		0
+#define	DP_MODEM_FAIL		-1
+
+/* Commands used for rscadm modem_setup */
+#define	DP_MODEM_CONNECT	0x30
+#define	DP_MODEM_CONNECT_R	0x31
+typedef struct dp_modem_connect_r {
+	rsci32	status;
+} dp_modem_connect_r_t;
+
+/* There is no reponse to a modem_data command */
+/* The modem data command goes in both directions */
+#define	DP_MODEM_DATA		0x32
+/* followed by a zero-terminated ascii string */
+
+#define	DP_MODEM_DISCONNECT	0x34
+#define	DP_MODEM_DISCONNECT_R	0x35
+typedef struct dp_modem_disconnect_r {
+	rsci32	status;
+} dp_modem_disconnect_r_t;
+
+
+#define	DP_GET_TICKCNT		0x22
+#define	DP_GET_TICKCNT_R	0x23
+typedef struct dp_get_tickcnt_r {
+	rsci32	upper;		/* MSW of 64 bit tick count */
+	rsci32	lower;		/* LSW of 64 bit tick count */
+} dp_get_tickcnt_r_t;
+
+
+#define	DP_SET_DEFAULT_CFG	0x72
+
+#define	DP_SET_DEFAULT_CFG_R	0x52
+typedef struct dp_set_default_cfg_r {
+	rsci32	status;
+} dp_set_default_cfg_r_t;
+
+
+#define	DP_GET_NETWORK_CFG	0x59
+
+#define	DP_GET_NETWORK_CFG_R	0x79
+typedef struct dp_get_network_cfg_r {
+	rsci32	status;
+	char	ipMode[7];
+	char	ipAddr[16];
+	char	ipMask[16];
+	char	ipGateway[16];
+	char	ethAddr[18];
+	char	ipDHCPServer[16];
+} dp_get_network_cfg_r_t;
+
+
+/*
+ * Parameters for DP_RUN_TEST message:
+ */
+
+/*
+ * Test routines need to know what the low-level protocol sync
+ * character is.
+ */
+
+#define	RSC_TEST_SERIAL		0
+typedef struct rsc_serial_test {
+	rsci32	testtype;
+#define	RSC_SERIAL_TTYC_LB	0
+#define	RSC_SERIAL_TTYC_LB_OFF	1
+#define	RSC_SERIAL_TTYD_LB	2
+#define	RSC_SERIAL_TTYD_LB_OFF	3
+#define	RSC_SERIAL_TTYCD_LB	4
+#define	RSC_SERIAL_TTYCD_LB_OFF	5
+#define	RSC_SERIAL_TTYU_INT_LB	6
+#define	RSC_SERIAL_TTYU_EXT_LB	7
+	rsci32	baud;
+	rsci32	passes;
+	rsci32	datalen;
+	rsci8	data[DP_MAX_MSGLEN-32];
+} rsc_serial_test_t;
+
+#define	RSC_TEST_ENET		1
+typedef struct rsc_enet_test {
+	rsci32	testtype;
+#define	RSC_ENET_INT_LB		0
+#define	RSC_ENET_EXT_LB		1
+#define	RSC_ENET_PING		2
+#define	RSC_ENET_INT_PHY_LB	3
+	rsci8	ip_addr[4];
+	rsci32	passes;
+	rsci32	datalen;
+	rsci8	data[DP_MAX_MSGLEN-32];
+} rsc_enet_test_t;
+
+#define	RSC_TEST_FLASH_CRC	2
+typedef struct rsc_flash_crcs_r {
+	rsci32	boot_crc;
+	rsci32	main_crc;
+} rsc_flash_crcs_r_t;
+
+#define	RSC_TEST_SEEPROM_CRC	3
+typedef struct rsc_seeprom_crcs_r {
+	rsci32	hdr_crc;
+	rsci32	main_crc;
+} rsc_seeprom_crcs_r_t;
+
+#define	RSC_TEST_FRU_SEEPROM_CRC 4
+typedef struct rsc_fru_crcs_r {
+	rsci32	ro_hdr_crc;
+	rsci32	seg_sd_crc;
+} rsc_fru_crcs_r_t;
+
+
+/*
+ * new commands definitions
+ */
+
+#define	DP_GET_SYSINFO		0x20
+
+#define	DP_GET_SYSINFO_R	0x21
+typedef struct dp_get_sysinfo_r {
+	rsci8 maxTemp;		/* max number of temperature sensors */
+	rsci8 maxFan;		/* max number of FANs */
+	rsci8 maxPSU;		/* max number of PSUs slot */
+	rsci8 maxLED;		/* max number of LEDs */
+	rsci8 maxVolt;		/* max number of voltage sensors */
+	rsci8 maxFRU;		/* max number of FRUs (field replac. unit)  */
+	rsci8 maxCircuitBrks;	/* max number of circuit breakers */
+	rsci8 keyswitch;	/* key switch setting value */
+} dp_get_sysinfo_r_t;
+
+
+#define	DP_GET_TEMPERATURES	0x24
+typedef struct dp_get_temperatures {
+	dp_handle_t handle;	/* handle of a temperature sensor */
+				/* or <null handle> (0xffff) */
+} dp_get_temperatures_t;
+
+/* Data is variable name & new value as zero-terminated ascii strings. */
+
+#define	DP_GET_TEMPERATURES_R	0x25
+typedef rscis16		dp_tempr_t;
+
+enum sensor_status {
+	DP_SENSOR_DATA_AVAILABLE = 0,
+	DP_SENSOR_DATA_UNAVAILABLE,
+	DP_SENSOR_NOT_PRESENT
+};
+
+typedef struct dp_tempr_status {
+	dp_handle_t	handle;
+	rsci8		sensor_status; 	/* tells whether the reading is */
+					/* available or not */
+	dp_tempr_t	value;	/* temperature value (celsius). */
+
+	dp_tempr_t 	low_warning;
+	dp_tempr_t 	low_soft_shutdown;
+	dp_tempr_t 	low_hard_shutdown;
+	dp_tempr_t 	high_warning;
+	dp_tempr_t 	high_soft_shutdown;
+	dp_tempr_t 	high_hard_shutdown;
+
+} dp_tempr_status_t;
+
+typedef struct dp_get_temperatures_r {
+	rsci8			num_temps;
+	dp_tempr_status_t	temp_status[1];
+
+} dp_get_temperatures_r_t;
+
+
+#define	DP_GET_FAN_STATUS	0x26
+typedef struct dp_get_fan_status {
+	dp_handle_t handle;	/* handle of a temperature sensor */
+				/* or <null handle> (0xffff) */
+} dp_get_fan_status_t;
+
+#define	DP_GET_FAN_STATUS_R	0x27
+
+typedef struct dp_fan_status {
+	dp_handle_t	handle;
+	rsci8		sensor_status; 	/* tells whether the reading is */
+					/* available or not */
+	rsci8 		flag;
+
+#define	DP_FAN_PRESENCE		0x01	/* FAN presence (bit set=FAN present) */
+#define	DP_FAN_SPEED_VAL_UNIT	0x02	/* speed unit	(bit set=relative, */
+					/*		bit clear=RPM) */
+#define	DP_FAN_STATUS		0x04	/* FAN status (bit set=error) */
+
+	rsci16		speed;	/* FAN speed. */
+	rsci16		minspeed; /* minimum FAN speed warning threshold */
+
+} dp_fan_status_t;
+
+typedef struct dp_get_fan_status_r {
+	rsci8		num_fans;
+	dp_fan_status_t	fan_status[1];
+
+} dp_get_fan_status_r_t;
+
+
+#define	DP_GET_PSU_STATUS	0x28
+typedef struct dp_get_psu_status {
+	dp_handle_t handle;	/* handle of a temperature sensor */
+				/* or <null handle> (0xffff) */
+} dp_get_psu_status_t;
+
+#define	DP_GET_PSU_STATUS_R	0x29
+typedef struct dp_psu_status {
+	dp_handle_t	handle;
+	rsci8		sensor_status; 	/* tells whether the reading is */
+					/* available or not */
+	rsci16 		mask;		/* flag bit mask (feature presence) */
+	rsci16 		flag;		/* status bits */
+
+#define	DP_PSU_PRESENCE			0x0001	/* PSU presence  */
+#define	DP_PSU_OUTPUT_STATUS		0x0002	/* output status */
+#define	DP_PSU_INPUT_STATUS		0x0004	/* input status */
+#define	DP_PSU_SEC_INPUT_STATUS		0x0008	/* secondary input status */
+#define	DP_PSU_OVERTEMP_FAULT		0x0010	/* over temperature fault */
+#define	DP_PSU_FAN_FAULT    		0x0020	/* FAN fault */
+#define	DP_PSU_FAIL_STATUS		0x0040	/* PSU generic fault */
+#define	DP_PSU_OUTPUT_VLO_STATUS	0x0080	/* output under voltage */
+#define	DP_PSU_OUTPUT_VHI_STATUS	0x0100	/* output over voltage */
+#define	DP_PSU_OUTPUT_AHI_STATUS	0x0200	/* output over current */
+#define	DP_PSU_ALERT_STATUS		0x0400	/* PSU alert indication */
+#define	DP_PSU_PDCT_FAN			0x0800	/* predicted fan fail */
+#define	DP_PSU_NR_WARNING		0x1000	/* non-redundancy condition */
+
+			/* presence: 	bit clear=not present */
+			/*		bit set=present */
+			/* status:	bit clear=ok */
+			/*		bit set=generic fault */
+} dp_psu_status_t;
+
+typedef struct dp_get_psu_status_r {
+
+	rsci8		num_psus;
+	dp_psu_status_t	psu_status[1];
+
+} dp_get_psu_status_r_t;
+
+#define	DP_GET_FRU_STATUS	0x2A
+typedef struct dp_get_fru_status {
+	dp_handle_t handle;	/* handle of a hot pluggable unit */
+				/* or <null handle> (0xffff)	  */
+} dp_get_fru_status_t;
+
+
+#define	DP_GET_FRU_STATUS_R	0x2B
+typedef struct dp_fru_status {
+
+	dp_handle_t	handle;
+	rsci8		sensor_status; 	/* tells whether the reading is */
+					/* available or not */
+	rsci8		presence;	/* 1=FRU present */
+	rsci8		status;
+
+} dp_fru_status_t;
+
+enum dp_fru_status_type {
+	DP_FRU_STATUS_OK = 1,
+	DP_FRU_STATUS_FAILED,
+	DP_FRU_STATUS_BLACKLISTED,
+	DP_FRU_STATUS_UNKNOWN
+};
+
+typedef struct dp_get_fru_status_r {
+	rsci8		num_frus;
+	dp_fru_status_t	fru_status[1];
+
+} dp_get_fru_status_r_t;
+
+/*
+ * DP_GET_DEVICE(_R) command is used to discover I2C devices dynamically
+ * (used by SunVTS)
+ */
+#define	DP_GET_DEVICE		0x2C
+
+typedef struct dp_get_device {
+	dp_handle_t	handle;	/* handle of a device or */
+				/* <null handle>(0xffff) */
+} dp_get_device_t;
+
+#define	DP_GET_DEVICE_R		0x2D
+
+#define	DP_MAX_DEVICE_TYPE_NAME	32
+
+typedef struct dp_device {
+	dp_handle_t	handle;
+	rsci8		presence;	/* 0 is not present, 1 is present */
+	char		device_type[DP_MAX_DEVICE_TYPE_NAME];
+} dp_device_t;
+
+typedef struct dp_get_device_r {
+	rsci8		num_devices;
+	dp_device_t	device[1];
+} dp_get_device_r_t;
+
+
+#define	DP_SET_CPU_SIGNATURE	0x33
+
+typedef struct dp_set_cpu_signature {
+	int		cpu_id;		/* see PSARC 2000/205 for more */
+	ushort_t	sig; 		/* information on the value/meaning */
+	uchar_t		states;		/* of these fields */
+	uchar_t		sub_state;
+
+} dp_cpu_signature_t;
+
+
+#define	DP_SET_CPU_NODENAME	0x38
+
+#define	DP_MAX_NODENAME		256
+
+typedef struct dp_set_nodename {
+	char		nodename[DP_MAX_NODENAME];
+} dp_set_nodename_t;
+
+
+#define	DP_GET_LED_STATE	0x3C
+
+typedef struct dp_get_led_state {
+	dp_handle_t handle;	/* handle of a hot pluggable unit */
+				/* or <null handle> (0xffff) */
+} dp_get_led_state_t;
+
+#define	DP_GET_LED_STATE_R	0x3D
+
+typedef struct dp_led_state {
+	dp_handle_t	handle;
+	rsci8		sensor_status; 	/* tells whether the reading is */
+					/* available or not */
+	rsci8		state;
+	rsci8		colour;
+} dp_led_state_t;
+
+typedef struct dp_get_led_state_r {
+	rsci8		num_leds;
+	dp_led_state_t	led_state[1];
+} dp_get_led_state_r_t;
+
+/* LED states */
+
+enum dp_led_states {
+	DP_LED_OFF = 0,
+	DP_LED_ON,
+	DP_LED_FLASHING,
+	DP_LED_BLINKING
+};
+
+enum dp_led_colours {
+	DP_LED_COLOUR_NONE = -1,
+	DP_LED_COLOUR_ANY,
+	DP_LED_COLOUR_WHITE,
+	DP_LED_COLOUR_BLUE,
+	DP_LED_COLOUR_GREEN,
+	DP_LED_COLOUR_AMBER
+};
+
+
+#define	DP_SET_LED_STATE	0x3E
+
+typedef struct dp_set_led_state {
+	dp_handle_t	handle;		/* handle of a LED */
+	rsci8		state;
+} dp_set_led_state_t;
+
+#define	DP_SET_LED_STATE_R	0x3F
+typedef struct dp_set_led_state_r {
+	rsci8		status;
+} dp_set_led_state_r_t;
+
+enum dp_set_led_status {
+	DP_SET_LED_OK = 0,
+	DP_SET_LED_INVALID_HANDLE,
+	DP_SET_LED_ERROR
+};
+
+
+#define	DP_GET_ALARM_STATE	0x68
+
+typedef struct dp_get_alarm_state {
+	dp_handle_t handle;	/* handle of an alarm relay */
+				/* or <null handle> (0xffff) */
+} dp_get_alarm_state_t;
+
+#define	DP_GET_ALARM_STATE_R	0x69
+
+typedef struct dp_alarm_state {
+	dp_handle_t	handle;
+	rsci8		sensor_status; 	/* tells whether the reading is */
+					/* available or not */
+	rsci8		state;
+} dp_alarm_state_t;
+
+typedef struct dp_get_alarm_state_r {
+	rsci8		num_alarms;
+	dp_alarm_state_t	alarm_state[1];
+} dp_get_alarm_state_r_t;
+
+/* ALARM states */
+
+enum dp_alarm_states {
+	DP_ALARM_OFF = 0,
+	DP_ALARM_ON
+};
+
+#define	DP_SET_ALARM_STATE	0x6A
+
+typedef struct dp_set_alarm_state {
+	dp_handle_t	handle;		/* handle of a ALARM */
+	rsci8		state;
+} dp_set_alarm_state_t;
+
+#define	DP_SET_ALARM_STATE_R	0x6B
+typedef struct dp_set_alarm_state_r {
+	rsci8		status;
+} dp_set_alarm_state_r_t;
+
+enum dp_set_alarm_status {
+	DP_SET_ALARM_OK = 0,
+	DP_SET_ALARM_INVALID_HANDLE,
+	DP_SET_ALARM_ERROR
+};
+
+
+#define	DP_GET_VOLTS		0x42
+
+typedef struct dp_get_volts {
+	dp_handle_t	handle;		/* handle of a voltage sensor */
+} dp_get_volts_t;
+
+#define	DP_GET_VOLTS_R		0x43
+
+typedef rscis16		dp_volt_reading_t;	/* unit in mV */
+
+typedef struct dp_volt_status {
+	dp_handle_t		handle;
+	rsci8			sensor_status; 	/* tells whether the reading */
+						/* is available or not */
+	rsci8			status;		/* 0=ok, 1=error */
+	dp_volt_reading_t	reading;	/* value in mV. */
+	dp_volt_reading_t	low_warning;
+	dp_volt_reading_t	low_soft_shutdown;
+	dp_volt_reading_t	low_hard_shutdown;
+	dp_volt_reading_t	high_warning;
+	dp_volt_reading_t	high_soft_shutdown;
+	dp_volt_reading_t	high_hard_shutdown;
+
+} dp_volt_status_t;
+
+typedef struct dp_get_volts_r {
+	rsci8			num_volts;
+	dp_volt_status_t	volt_status[1];
+
+} dp_get_volts_r_t;
+
+
+#define	DP_GET_CIRCUIT_BRKS	0x62
+
+typedef struct dp_get_circuit_brks {
+	dp_handle_t handle;	/* handle of a circuit breaker */
+				/* or <null handle> (0xffff) */
+} dp_get_circuit_brks_t;
+
+#define	DP_GET_CIRCUIT_BRKS_R	0x63
+
+typedef struct dp_circuit_brk_status {
+	dp_handle_t	handle;
+	rsci8		sensor_status; 	/* tells whether the reading is */
+					/* available or not */
+	rsci8		status;		/* 0=ok, 1=error */
+
+} dp_circuit_brk_status_t;
+
+typedef struct dp_get_circuit_brks_r {
+	rsci8			num_circuit_brks;
+	dp_circuit_brk_status_t	circuit_brk_status[1];
+
+} dp_get_circuit_brks_r_t;
+
+
+#define	DP_SET_HOST_WATCHDOG	0x48
+
+typedef struct dp_set_host_watchdog {
+	rsci8	enable;		/* 0=enable watchdog, 1=disable watchdog */
+} dp_set_host_watchdog_t;
+
+
+#define	DP_GET_HANDLE_NAME	0x4A
+
+typedef struct dp_get_handle_name {
+	dp_handle_t	handle;
+} dp_get_handle_name_t;
+
+#define	DP_GET_HANDLE_NAME_R	0x4B
+
+typedef struct dp_get_handle_name_r {
+	dp_handle_t	handle;
+	char 		name[DP_MAX_HANDLE_NAME];
+} dp_get_handle_name_r_t;
+
+
+#define	DP_GET_HANDLE		0x4C
+
+typedef struct dp_get_handle {
+	char 		name[DP_MAX_HANDLE_NAME];
+} dp_get_handle_t;
+
+#define	DP_GET_HANDLE_R		0x4D
+
+typedef struct dp_get_handle_r {
+	dp_handle_t 	handle;
+} dp_get_handle_r_t;
+
+
+#define	DP_RMC_EVENTS		0x57
+
+typedef rsci16	dp_event_t;
+
+/*
+ * list of events
+ */
+
+enum rmc_events {
+	RMC_INIT_EVENT	= 0x01,
+	RMC_HPU_EVENT,
+	RMC_ENV_EVENT,
+	RMC_KEYSWITCH_EVENT,
+	RMC_LOG_EVENT
+};
+
+/*
+ * event data structures
+ */
+enum rmc_hpu_events {
+	RMC_HPU_INSERT_EVENT	= 0x20,
+	RMC_HPU_REMOVE_EVENT,
+	RMC_HPU_HWERROR_EVENT
+};
+
+typedef struct dp_hpu_event {
+	dp_handle_t	hpu_hdl;
+	dp_event_t	sub_event;
+
+} dp_hpu_event_t;
+
+
+enum rmc_env_events {
+	RMC_ENV_WARNING_THRESHOLD_EVENT = 0x31,
+	RMC_ENV_SHUTDOWN_THRESHOLD_EVENT,
+	RMC_ENV_FAULT_EVENT,
+	RMC_ENV_OK_EVENT
+};
+
+typedef struct dp_env_event {
+	dp_handle_t	env_hdl;
+	dp_event_t	sub_event;
+
+} dp_env_event_t;
+
+
+enum rmc_keyswitch_pos {
+	RMC_KEYSWITCH_POS_UNKNOWN	= 0x00,
+	RMC_KEYSWITCH_POS_NORMAL,
+	RMC_KEYSWITCH_POS_DIAG,
+	RMC_KEYSWITCH_POS_LOCKED,
+	RMC_KEYSWITCH_POS_OFF
+};
+
+typedef struct dp_keyswitch_event {
+	rsci8	key_position;
+} dp_keyswitch_event_t;
+
+
+typedef struct dp_rmclog_event {
+	int	log_record_size;
+	rsci8	log_record[DP_MAX_LOGSIZE];
+} dp_rmclog_event_t;
+
+typedef union dp_event_info {
+	dp_hpu_event_t		ev_hpunot;
+	dp_env_event_t		ev_envnot;
+	dp_keyswitch_event_t	ev_keysw;
+	dp_rmclog_event_t	ev_rmclog;
+} dp_event_info_t;
+
+typedef struct dp_event_notification {
+	dp_event_t	event;
+	rsci32		event_seqno; 	/* event sequence number */
+	rsci32		timestamp;	/* timestamp of the event */
+	dp_event_info_t	event_info;	/* event information */
+} dp_event_notification_t;
+
+#define	DP_RMC_EVENTS_R		0x5F
+
+typedef struct dp_event_notification_r {
+	rsci32		event_seqno; 	/* event sequence number */
+} dp_event_notification_r_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_RMC_COMM_HPROTO_H */
diff --git a/usr/src/uts/sun4u/sys/rmc_comm_lproto.h b/usr/src/uts/sun4u/sys/rmc_comm_lproto.h
new file mode 100644
index 0000000000..3ec2a2b01d
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/rmc_comm_lproto.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2001-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_RMC_COMM_LPROTO_H
+#define	_SYS_RMC_COMM_LPROTO_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	SYNC_CHAR	0x80
+#define	ESC_CHAR	0x81
+
+/* Maximum message length */
+
+#define	DP_MAX_MSGLEN	1024
+
+/*
+ * Tunables.
+ */
+
+/* Number of times a transmitted message will be retried. */
+#define	TX_RETRIES	10
+
+/* Amount of time between transmit retries in ms, currently 500ms. */
+#define	TX_RETRY_TIME	500L
+
+/* minimum waiting time for a reply (milliseconds) */
+#define	DP_MIN_TIMEOUT	200L
+
+/*
+ * timeout (in ms) for (re)trying to establish the protocol data link
+ */
+#define	DELAY_DP_SETUP		10
+#define	RETRY_DP_SETUP		5000
+
+/*
+ * Data protocol message structure.  Note that this is the in-memory
+ * version; when a data protocol message is transmitted it goes
+ * through a translation to assist the receiving side in determining
+ * message boundaries robustly.
+ */
+typedef struct dp_header {
+
+	uint8_t  pad;		/* This pad byte is never transmitted nor */
+				/* received, it is solely to make the */
+				/* structure elements line up in memory. */
+	uint8_t  type;		/* The message type-see below for valid types */
+	uint16_t length;	/* Length of the whole message. */
+	uint8_t  txnum;		/* Sequence number of this message. */
+	uint8_t  rxnum;		/* Highest sequence number received. */
+				/* (AKA piggy-backed acknowledgement). */
+	uint16_t crc;		/* CRC-16 Checksum of header. */
+
+} dp_header_t;
+
+/*
+ * Macros for dealing with sequence id's.
+ */
+
+/* Given a sequence id, calculate the next one. */
+#define	NEXT_SEQID(a)		(((a) + 1) % 0x100)
+
+/* Given a sequence id, calculate the previous one. */
+#define	PREV_SEQID(a)		(((a) == 0) ? 0xff : (a)-1)
+
+/* Do these sequence ID's follow each other? */
+#define	IS_NEXT_SEQID(a, b)	((b) == NEXT_SEQID(a))
+
+/* What to initialize sequence ID counters to. */
+#define	INITIAL_SEQID		0xFF
+
+/*
+ * Macros for interpreting message types.
+ */
+#define	IS_NUMBERED_MSG(t)	(((t) & 0x80) == 0x00)
+#define	IS_UNNUMBERED_MSG(t)	(((t) & 0xC0) == 0x80)
+#define	IS_BOOT_MSG(t)		(((t) & 0xE0) == 0xC0)
+
+/*
+ * Un-numbered messages.
+ */
+
+#define	DP_CTL_START		0x88
+
+#define	DP_CTL_STACK		0x89
+
+#define	DP_CTL_RESPOND		0x8A
+
+#define	DP_CTL_ACK		0x8B
+
+#define	DP_CTL_NAK		0x8C
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_RMC_COMM_LPROTO_H */
diff --git a/usr/src/uts/sun4u/sys/safari_pcd.h b/usr/src/uts/sun4u/sys/safari_pcd.h
new file mode 100644
index 0000000000..0b0c0b0c5b
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/safari_pcd.h
@@ -0,0 +1,119 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 1999-2003 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_SAFARI_PCD_H
+#define	_SYS_SAFARI_PCD_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * This file contains definitions of the structure spcd_t, Port Configuration
+ * Descriptor, which is part of the information handed off to OBP and
+ * the OS by POST in the "golden" I/O SRAM.
+ * It is very similar in function to, and borrows heavily from, the spd
+ */
+
+#include <sys/types.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	MAX_BANKS_PER_PORT	4	/* Physical and Logical */
+#define	MAX_DIMMS_PER_PORT	8
+#define	IOBUS_PER_PORT		2
+#define	IOCARD_PER_BUS		4
+#define	LINKS_PER_PORT		5
+#define	UPADEV_PER_PORT		2
+#define	AGENTS_PER_PORT		2
+
+#define	PCD_VERSION 1
+#define	PCD_MAGIC ('P'<<24 |'C'<<16 |'D'<<8 | 0)
+
+
+	/* Types of Safari ports */
+#define	SAFPTYPE_NULL	0
+#define	SAFPTYPE_CPU	1
+#define	SAFPTYPE_sPCI	2
+#define	SAFPTYPE_cPCI	3
+#define	SAFPTYPE_WCI	4
+#define	SAFPTYPE_PCIX	5
+
+	/*
+	 * RSV stands for Resource Status Value.
+	 * These are the values used in all cases where the status of
+	 * a resource is maintained in a byte element of a structure.
+	 * These are ordered in terms of preserving interesting information
+	 * in POST displays where all configurations are displayed in a
+	 * single value.
+	 */
+
+typedef uint8_t	spcdrsv_t;
+
+#define	SPCD_RSV_PASS	0x1		/* Passed some sort of test */
+#define	SPCD_RSV_FAIL	0xff
+
+typedef struct {
+	uint32_t	spcd_magic;	/* PCD_MAGIC */
+	uint8_t		spcd_version;	/* structure version: PCD_VERSION */
+	uint64_t	spcd_ver_reg;	/* port version register */
+	uint16_t	spcd_afreq;	/* actual operating frequency Mhz */
+
+	uint8_t		spcd_ptype;	/* port type. See SAFPTYPE_ below */
+	uint8_t		spcd_cache;	/* external cache size (MByte?) */
+	spcdrsv_t	spcd_prsv;	/* The entire port status */
+	spcdrsv_t	spcd_agent[AGENTS_PER_PORT];
+	uint16_t	spcd_cpuid[AGENTS_PER_PORT];
+
+		/* for ports with UPA device */
+	spcdrsv_t	spcd_upadev[UPADEV_PER_PORT];
+
+		/* for ports with IO buses */
+	spcdrsv_t	spcd_iobus_rsv[IOBUS_PER_PORT];
+		/* status of each IO card on port */
+	spcdrsv_t	spcd_iocard_rsv[IOBUS_PER_PORT][IOCARD_PER_BUS];
+
+		/* for ports with WIC links */
+	spcdrsv_t	spcd_wic_links[LINKS_PER_PORT];
+		/* status of each WIC link on port */
+
+	uint32_t	memory_layout_size;	/* size of memory-layout */
+	uint8_t		*memory_layout;		/* ptr to memory-layout data */
+
+	char		*sprd_bank_rsv[MAX_BANKS_PER_PORT];
+		/* status of each bank */
+	char		*sprd_dimm[MAX_DIMMS_PER_PORT];
+		/* status of each dimm */
+	char		*sprd_ecache_dimm_label[MAX_DIMMS_PER_PORT];
+		/* labels for ecache dimms */
+
+} spcd_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _SYS_SAFARI_PCD_H */
diff --git a/usr/src/uts/sun4u/sys/sbbcio.h b/usr/src/uts/sun4u/sys/sbbcio.h
new file mode 100644
index 0000000000..68246a5971
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/sbbcio.h
@@ -0,0 +1,53 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 1999-2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SYS_SBBCIO_H
+#define	_SYS_SBBCIO_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	SBBC_IOC		('s' << 8)
+
+#define	SBBC_SBBCREG_WR		_IOWR('s', 2, struct ssc_sbbc_regio)
+#define	SBBC_SBBCREG_RD		_IOWR('s', 7, struct ssc_sbbc_regio)
+
+/* offset 0x000000 to 0x07FFFF - read write sbbc internal registers */
+struct ssc_sbbc_regio {
+	uint32_t offset;	/* provided by SSC application SW */
+	uint32_t len;		/* provided by SSC application SW */
+	uint32_t value;		/* provided by SSC application SW */
+	uint32_t retval;	/* return value provided by driver */
+};
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_SBBCIO_H */
diff --git a/usr/src/uts/sun4u/sys/sbbcreg.h b/usr/src/uts/sun4u/sys/sbbcreg.h
new file mode 100644
index 0000000000..4966d1379d
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/sbbcreg.h
@@ -0,0 +1,331 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 1999-2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SYS_SBBCREG_H
+#define	_SYS_SBBCREG_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Register definitions for SBBC, a PCI device.
+ */
+#define	SBBC_SC_MODE	0x00000020
+
+typedef struct pad12 {
+	uint32_t pad[3];
+}pad12_t;
+
+/*
+ * SBBC registers.
+ */
+struct sbbc_regs_map {
+	uint32_t devid;			/* 0x0.0000 All, device ID */
+	pad12_t  pada;
+	uint32_t devtemp;		/* 0x0.0010 All */
+	pad12_t  padb;
+	uint32_t incon_scratch;		/* 0x0.0020 All */
+	pad12_t  padc;
+	uint32_t incon_tstl1;		/* 0x0.0030 AR and SDC */
+	pad12_t  padd;
+	uint32_t incon_tsterr;		/* 0x0.0040 AR and SDC */
+	pad12_t  pade;
+	uint32_t device_conf;		/* 0x0.0050 All, device configuration */
+	pad12_t  padf;
+	uint32_t device_rstcntl;	/* 0x0.0060 SBBC,AR,dev reset control */
+	pad12_t  padg;
+	uint32_t device_rststat;	/* 0x0.0070 All, device reset status */
+	pad12_t  padh;
+	uint32_t device_errstat;	/* 0x0.0080 SBBC, device reset */
+	pad12_t  padi;
+	uint32_t device_errcntl;	/* 0x0.0090 SBBC,device error control */
+	pad12_t  padj;
+	uint32_t jtag_cntl;		/* 0x0.00a0 SBBC and SDC,JTAG control */
+	pad12_t  padk;
+	uint32_t jtag_cmd;		/* 0x0.00b0 SBBC and SDC,JTAG command */
+	pad12_t  padl;
+	uint32_t i2c_addrcmd;		/* 0x0.00c0 SBBC,I2C addr and command */
+	pad12_t  padm;
+	uint32_t i2c_data;		/* 0x0.00d0 SBBC, I2C data */
+	pad12_t  padn;
+	uint32_t pci_errstat;		/* 0x0.00e0 SBBC, PCI error status */
+	pad12_t  pad2[45];
+	uint32_t consbus_conf;		/* 0x0.0300 All */
+	pad12_t  pado;
+	uint32_t consbus_erraddr;	/* 0x0.0310 SBBC */
+	pad12_t  padp;
+	uint32_t consbus_errack;	/* 0x0.0320 SBBC */
+	pad12_t  pad4[18];
+	uint32_t pad5;
+	uint32_t consbus_port0_err;	/* 0x0.0400 All */
+	pad12_t  pad6[19];
+	uint32_t pad7[2];
+	uint32_t consbus_part_dom_err;	/* 0x0.04f0 SBBC and CBH */
+	pad12_t  pad8[235];
+	uint32_t pad8a[2];
+	uint32_t sbbc_synch;		/* 0x0.1000 SBBC */
+	pad12_t  padq[20];
+	uint32_t padqa[3];
+	uint32_t dev_access_tim0;	/* 0x0.1100 SBBC */
+	pad12_t  padr;
+	uint32_t dev_access_tim1;	/* 0x0.1110 SBBC */
+	pad12_t  pads;
+	uint32_t dev_access_tim2;	/* 0x0.1120 SBBC */
+	pad12_t  padt;
+	uint32_t dev_access_tim3;	/* 0x0.1130 SBBC */
+	pad12_t  padu;
+	uint32_t dev_access_tim4;	/* 0x0.1140 SBBC */
+	pad12_t  padv;
+	uint32_t dev_access_tim5;	/* 0x0.1150 SBBC */
+	pad12_t  pad9[14];
+	uint32_t pad9a[1];
+	uint32_t spare_in_out;		/* 0x0.1200 SBBC */
+	pad12_t  pad10[127];
+	uint32_t pad10a[2];
+	uint32_t monitor_cntl;		/* 0x0.1800 SBBC */
+	pad12_t  pad11[170];
+	uint32_t pad11a[1];
+	uint32_t port_intr_gen0;	/* 0x0.2000 SBBC */
+	pad12_t  padw;
+	uint32_t port_intr_gen1;	/* 0x0.2010 SBBC */
+	pad12_t  padx;
+	uint32_t syscntlr_intr_gen;	/* 0x0.2020 SBBC */
+	pad12_t  pad12[61];
+	uint32_t sys_intr_status;	/* 0x0.2300 SBBC */
+	pad12_t  pady;
+	uint32_t sys_intr_enable;	/* 0x0.2310 SBBC */
+	pad12_t  padz;
+	uint32_t pci_intr_status;	/* 0x0.2320 SBBC */
+	pad12_t  padaa;
+	uint32_t pci_intr_enable;	/* 0x0.2330 SBBC */
+	pad12_t  pad13[614];
+	uint32_t pad13a[1];
+	uint32_t pci_to_consbus_map;	/* 0x0.4000 SBBC */
+	pad12_t  padab;
+	uint32_t consbus_to_pci_map;	/* 0x0.4010 SBBC */
+};
+
+
+/*
+ * SSC DEV presence registers
+ */
+struct ssc_devpresence_regs_map {
+	uint8_t devpres_reg0;
+	uint8_t devpres_reg1;
+	uint8_t devpres_reg2;
+	uint8_t devpres_reg3;
+	uint8_t devpres_reg4;
+	uint8_t devpres_reg5;
+	uint8_t devpres_reg6;
+	uint8_t devpres_reg7;
+	uint8_t devpres_reg8;
+	uint8_t devpres_reg9;
+	uint8_t devpres_rega;
+	uint8_t devpres_regb;
+};
+
+/*
+ * EChip
+ * 0088.0000 - 0089.FFFF
+ */
+struct ssc_echip_regs {
+	uint8_t offset[0x20000];
+};
+
+/*
+ * Device Presence
+ * 008A.0000 - 008B.FFFF
+ */
+struct ssc_devpresence_regs {
+	uint8_t offset[0x20000];
+};
+
+/*
+ * I2C Mux
+ * 008C.0000 - 008D.FFFF
+ */
+struct ssc_i2cmux_regs {
+	uint8_t offset[0x20000];
+};
+
+/*
+ * Error Interrupts Status and Control
+ * 008E.0000 - 008F.FFFF
+ */
+struct ssc_errintr_statcntl_regs {
+	uint8_t offset[0x20000];
+};
+
+/*
+ * Console Bus Window
+ * 0400.0000 - 07FF.FFFF
+ */
+struct ssc_console_bus {
+	uint8_t offset[0x4000000];
+};
+
+/*
+ * SSC EILD registers
+ */
+struct ssc_eild_reg_map {
+	uint8_t darb_intr;
+	uint8_t darb_intr_mask;
+	uint8_t sbbc_cons_err;
+	uint8_t sbbc_cons_err_mask;
+	uint8_t pwr_supply;
+};
+
+/*
+ * PCI SBBC slave mapping
+ */
+struct pci_sbbc {
+	uint8_t fprom[0x800000];	/* FPROM */
+	struct sbbc_regs_map sbbc_internal_regs;	/* sbbc registers */
+	uint8_t dontcare[0x7BFEC];	/* non-sbbc registers */
+	struct ssc_echip_regs echip_regs;
+	struct ssc_devpresence_regs devpres_regs;
+	struct ssc_i2cmux_regs i2cmux_regs;
+	struct ssc_errintr_statcntl_regs errintr_scntl_regs;
+	uint8_t sram[0x100000];
+	uint8_t reserved[0x3600000];
+	struct ssc_console_bus consbus;
+};
+
+
+/*
+ * SBBC registers.
+ */
+struct sbbc_common_devregs {
+	uint32_t devid;			/* All, device ID */
+	uint32_t devtemp;		/* All */
+	uint32_t incon_scratch;		/* All */
+	uint32_t incon_tstl1;		/* AR and SDC */
+	uint32_t incon_tsterr;		/* AR and SDC */
+	uint32_t device_conf;		/* All, device configuration */
+	uint32_t device_rstcntl;	/* SBBC and AR, dev reset control */
+	uint32_t device_rststat;	/* All, device reset status */
+	uint32_t device_errstat;	/* SBBC, device reset */
+	uint32_t device_errcntl;	/* SBBC, device error control */
+	uint32_t jtag_cntl;		/* SBBC and SDC, JTAG control */
+	uint32_t jtag_cmd;		/* SBBC and SDC, JTAG command */
+	uint32_t i2c_addrcmd;		/* SBBC, I2C address and command */
+	uint32_t i2c_data;		/* SBBC, I2C data */
+	uint32_t pci_errstat;		/* SBBC, PCI error status */
+	uint32_t domain_conf;		/* CBH */
+	uint32_t safari_port0_conf;	/* AR and SDC */
+	uint32_t safari_port1_conf;	/* AR and SDC */
+	uint32_t safari_port2_conf;	/* AR and SDC */
+	uint32_t safari_port3_conf;	/* AR and SDC */
+	uint32_t safari_port4_conf;	/* AR and SDC */
+	uint32_t safari_port5_conf;	/* AR and SDC */
+	uint32_t safari_port6_conf;	/* AR and SDC */
+	uint32_t safari_port7_conf;	/* AR and SDC */
+	uint32_t safari_port8_conf;	/* AR and SDC */
+	uint32_t safari_port9_conf;	/* AR and SDC */
+	uint32_t safari_port0_err;	/* AR and SDC */
+	uint32_t safari_port1_err;	/* AR and SDC */
+	uint32_t safari_port2_err;	/* AR and SDC */
+	uint32_t safari_port3_err;	/* AR and SDC */
+	uint32_t safari_port4_err;	/* AR and SDC */
+	uint32_t safari_port5_err;	/* AR and SDC */
+	uint32_t safari_port6_err;	/* AR and SDC */
+	uint32_t safari_port7_err;	/* AR and SDC */
+	uint32_t safari_port8_err;	/* AR and SDC */
+	uint32_t safari_port9_err;	/* AR and SDC */
+	uint32_t consbus_conf;		/* All */
+	uint32_t consbus_erraddr;	/* SBBC */
+	uint32_t consbus_errack;	/* SBBC */
+	uint32_t consbus_errinj0;	/* CBH */
+	uint32_t consbus_errinj1;	/* CBH */
+	uint32_t consbus_port0_err;	/* All */
+	uint32_t consbus_port1_err;	/* SDC and CBH */
+	uint32_t consbus_port2_err;	/* SDC and CBH */
+	uint32_t consbus_port3_err;	/* SDC and CBH */
+	uint32_t consbus_port4_err;	/* SDC and CBH */
+	uint32_t consbus_port5_err;	/* CBH */
+	uint32_t consbus_port6_err;	/* CBH */
+	uint32_t consbus_port7_err;	/* CBH */
+	uint32_t consbus_port8_err;	/* CBH */
+	uint32_t consbus_port9_err;	/* CBH */
+	uint32_t consbus_porta_err;	/* CBH */
+	uint32_t consbus_portb_err;	/* CBH */
+	uint32_t consbus_portc_err;	/* CBH */
+	uint32_t consbus_portd_err;	/* CBH */
+	uint32_t consbus_porte_err;	/* CBH */
+	uint32_t consbus_part_dom_err;	/* SBBC and CBH */
+	uint32_t sbbc_synch;		/* SBBC */
+	uint32_t dev_access_tim0;	/* SBBC */
+	uint32_t dev_access_tim1;	/* SBBC */
+	uint32_t dev_access_tim2;	/* SBBC */
+	uint32_t dev_access_tim3;	/* SBBC */
+	uint32_t dev_access_tim4;	/* SBBC */
+	uint32_t dev_access_tim5;	/* SBBC */
+	uint32_t spare_in_out;		/* SBBC */
+	uint32_t monitor_cntl;		/* SBBC */
+	uint32_t port_intr_gen0;	/* SBBC */
+	uint32_t port_intr_gen1;	/* SBBC */
+	uint32_t syscntlr_intr_gen;	/* SBBC */
+	uint32_t sys_intr_status;	/* SBBC */
+	uint32_t sys_intr_enable;	/* SBBC */
+	uint32_t pci_intr_status;	/* SBBC */
+	uint32_t pci_intr_enable;	/* SBBC */
+	uint32_t pci_to_consbus_map;	/* SBBC */
+	uint32_t consbus_to_pci_map;	/* SBBC */
+	uint32_t scm_consbus_addrmap;	/* CBH */
+	uint32_t ar_slot0_trans_cnt;	/* AR */
+	uint32_t ar_slot1_trans_cnt;	/* AR */
+	uint32_t ar_slot2_trans_cnt;	/* AR */
+	uint32_t ar_slot3_trans_cnt;	/* AR */
+	uint32_t ar_slot4_trans_cnt;	/* AR */
+	uint32_t ar_slot5_trans_cnt;	/* AR */
+	uint32_t ar_slot6_trans_cnt;	/* AR */
+	uint32_t ar_slot7_trans_cnt;	/* AR */
+	uint32_t ar_slot8_trans_cnt;	/* AR */
+	uint32_t ar_slot9_trans_cnt;	/* AR */
+	uint32_t ar_trans_cnt_oflow;	/* AR */
+	uint32_t ar_trans_cnt_uflow;	/* AR */
+	uint32_t ar_l1l1_conf;		/* AR */
+	uint32_t lock_step_err;		/* AR and SDC */
+	uint32_t l2_check_err;		/* AR and SDC */
+	uint32_t incon_tstl1_slave;	/* AR */
+	uint32_t incon_tstl2_slave;	/* AR and SDC */
+	uint32_t ecc_status;		/* SDC */
+	uint32_t event_counter0;	/* SDC */
+	uint32_t event_counter1;	/* SDC */
+	uint32_t event_counter2;	/* SDC */
+	uint32_t monitor_counter_cntl;	/* AR and SDC */
+	uint32_t ar_transid_match;	/* AR */
+};
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_SBBCREG_H */
diff --git a/usr/src/uts/sun4u/sys/sbbcvar.h b/usr/src/uts/sun4u/sys/sbbcvar.h
new file mode 100644
index 0000000000..d73dd526ea
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/sbbcvar.h
@@ -0,0 +1,225 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_SBBCVAR_H
+#define	_SYS_SBBCVAR_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef struct sbbc_intr_map {
+	uint32_t sbbc_phys_hi;
+	uint32_t sbbc_phys_mid;
+	uint32_t sbbc_phys_low;
+	uint32_t sbbc_intr;
+	uint32_t intr_ctlr_nodeid;
+	uint32_t ino;
+}sbbc_intr_map_t;
+
+struct sbbc_intr_map_mask {
+	uint32_t sbbc_phys_hi;
+	uint32_t sbbc_phys_mid;
+	uint32_t sbbc_phys_low;
+	uint32_t sbbc_intr;
+};
+
+/* sbbc intrspec for initializing its children. */
+struct sbbc_intrspec {
+	struct intrspec intr_spec;
+	dev_info_t *dip;		/* Interrupt parent dip */
+	uint32_t intr;			/* for lookup */
+};
+
+/*
+ * definition of sbbc child reg spec entry:
+ */
+typedef struct {
+	uint32_t addr_hi;
+	uint32_t addr_low;
+	uint32_t size;
+} sbbc_child_regspec_t;
+
+/* SBBC range entry */
+typedef struct sbbc_pci_rangespec {
+	uint32_t sbbc_phys_hi;		/* Child hi range address */
+	uint32_t sbbc_phys_low;		/* Child low range address */
+	uint32_t pci_phys_hi;		/* Parent hi rng addr */
+	uint32_t pci_phys_mid;		/* Parent mid rng addr */
+	uint32_t pci_phys_low;		/* Parent low rng addr */
+	uint32_t rng_size;		/* Range size */
+} sbbc_pci_rangespec_t;
+
+typedef int procid_t;
+
+/* Max. SBBC devices/children */
+#define	MAX_SBBC_DEVICES	3
+
+/* Only used for fixed or legacy interrupts */
+#define	SBBC_INTR_STATE_DISABLE	0	/* disabled */
+#define	SBBC_INTR_STATE_ENABLE	1	/* enabled */
+
+typedef struct sbbc_child_intr {
+	char *name;
+	uint_t inum;
+	uint_t status;
+	uint_t (*intr_handler)();
+	caddr_t arg1;
+	caddr_t	arg2;
+} sbbc_child_intr_t;
+
+typedef struct sbbcsoft {
+	int instance;
+	int oflag;
+	uint_t myinumber;
+	dev_info_t *dip;			/* device information */
+	pci_regspec_t *reg;
+	int nreg;
+	sbbc_pci_rangespec_t *rangep;
+	int range_cnt;
+	int range_len;
+	struct pci_sbbc *pci_sbbc_map;		/* sbbc registers and devices */
+	ddi_acc_handle_t pci_sbbc_map_handle;
+	ddi_iblock_cookie_t sbbc_iblock_cookie; /* interrupt block cookie */
+	kmutex_t sbbc_intr_mutex;		/* lock for interrupts */
+	sbbc_child_intr_t *child_intr[MAX_SBBC_DEVICES]; /* intr per device */
+	boolean_t suspended;			/* TRUE if driver suspended */
+	kmutex_t umutex;			/* lock for this structure */
+} sbbcsoft_t;
+
+#define	TRUE		1
+#define	FALSE		0
+
+
+#if defined(DEBUG)
+
+#define	SBBC_DBG_ATTACH		0x1
+#define	SBBC_DBG_DETACH		0x2
+#define	SBBC_DBG_CTLOPS		0x4
+#define	SBBC_DBG_INITCHILD	0x8
+#define	SBBC_DBG_UNINITCHILD	0x10
+#define	SBBC_DBG_BUSMAP		0x20
+#define	SBBC_DBG_INTR		0x40
+#define	SBBC_DBG_PCICONF	0x80
+#define	SBBC_DBG_MAPRANGES	0x100
+#define	SBBC_DBG_PROPERTIES	0x200
+#define	SBBC_DBG_OPEN		0x400
+#define	SBBC_DBG_CLOSE		0x800
+#define	SBBC_DBG_IOCTL		0x1000
+#define	SBBC_DBG_INTROPS	0x2000
+
+
+#define	SBBC_DBG0(flag, dip, fmt) \
+	sbbc_dbg(flag, dip, fmt, 0, 0, 0, 0, 0);
+#define	SBBC_DBG1(flag, dip, fmt, a1) \
+	sbbc_dbg(flag, dip, fmt, (uintptr_t)(a1), 0, 0, 0, 0);
+#define	SBBC_DBG2(flag, dip, fmt, a1, a2) \
+	sbbc_dbg(flag, dip, fmt, (uintptr_t)(a1), (uintptr_t)(a2), 0, 0, 0);
+#define	SBBC_DBG3(flag, dip, fmt, a1, a2, a3) \
+	sbbc_dbg(flag, dip, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \
+		(uintptr_t)(a3), 0, 0);
+#define	SBBC_DBG4(flag, dip, fmt, a1, a2, a3, a4) \
+	sbbc_dbg(flag, dip, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \
+		(uintptr_t)(a3), (uintptr_t)(a4), 0);
+#define	SBBC_DBG5(flag, dip, fmt, a1, a2, a3, a4, a5) \
+	sbbc_dbg(flag, dip, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \
+		(uintptr_t)(a3), (uintptr_t)(a4), (uintptr_t)(a5));
+
+#else /* DEBUG */
+
+#define	SBBC_DBG0(flag, dip, fmt)
+#define	SBBC_DBG1(flag, dip, fmt, a1)
+#define	SBBC_DBG2(flag, dip, fmt, a1, a2)
+#define	SBBC_DBG3(flag, dip, fmt, a1, a2, a3)
+#define	SBBC_DBG4(flag, dip, fmt, a1, a2, a3, a4)
+#define	SBBC_DBG5(flag, dip, fmt, a1, a2, a3, a4, a5)
+
+#endif /* DEBUG */
+
+/* debugging flags */
+/*
+ * To enable tracing, uncomment this line:
+ * #define	SBBC_TRACE	1
+ */
+
+#if defined(SBBC_TRACE)
+
+#ifndef NSBBCTRACE
+#define	NSBBCTRACE	1024
+#endif
+
+struct sbbctrace {
+	int count;
+	int function;		/* address of function */
+	int trace_action;	/* descriptive 4 characters */
+	int object;		/* object operated on */
+};
+
+/*
+ * For debugging, allocate space for the trace buffer
+ */
+
+extern struct sbbctrace sbbctrace_buffer[];
+extern struct sbbctrace *sbbctrace_ptr;
+extern int sbbctrace_count;
+
+#define	SBBCTRACEINIT() {				\
+	if (sbbctrace_ptr == NULL)		\
+		sbbctrace_ptr = sbbctrace_buffer; \
+	}
+
+#define	LOCK_TRACE()	(uint_t)ddi_enter_critical()
+#define	UNLOCK_TRACE(x)	ddi_exit_critical((uint_t)x)
+
+#define	SBBCTRACE(func, act, obj) {		\
+	int __s = LOCK_TRACE();			\
+	int *_p = &sbbctrace_ptr->count;	\
+	*_p++ = ++sbbctrace_count;		\
+	*_p++ = (int)(func);			\
+	*_p++ = (int)(act);			\
+	*_p++ = (int)(obj);			\
+	if ((struct sbbctrace *)(void *)_p >= &sbbctrace_buffer[NSBBCTRACE])\
+		sbbctrace_ptr = sbbctrace_buffer; \
+	else					\
+		sbbctrace_ptr = (struct sbbctrace *)(void *)_p; \
+	UNLOCK_TRACE(__s);			\
+	}
+
+#else	/* !SBBC_TRACE */
+
+/* If no tracing, define no-ops */
+#define	SBBCTRACEINIT()
+#define	SBBCTRACE(a, b, c)
+
+#endif	/* !SBBC_TRACE */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_SBBCVAR_H */
diff --git a/usr/src/uts/sun4u/sys/sbd.h b/usr/src/uts/sun4u/sys/sbd.h
new file mode 100644
index 0000000000..0ec8c2e5b8
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/sbd.h
@@ -0,0 +1,124 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2002-2003 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SBD_H
+#define	_SBD_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/dditypes.h>
+/*
+ * SBD LOWER STRUCTURES AND INTERFACES
+ */
+
+typedef uint32_t	sbd_flags_t;
+
+/*
+ * Flag definitions
+ */
+#define	SBDP_IOCTL_FLAG_FORCE	0x1
+
+typedef struct {
+	int		size;	/* length of the options */
+	char		*copts;	/* pointer to the platform options */
+} sbdp_opts_t;
+
+typedef struct {
+	sbd_error_t	*h_err;		/* error reporting from lower layer */
+	int		h_board;	/* board number */
+	int		h_wnode;	/* node ID */
+	sbd_flags_t	h_flags;
+	sbdp_opts_t	*h_opts;	/* points to the platform options */
+} sbdp_handle_t;
+
+/* struct for device name to type mapping */
+typedef struct {
+	char		*s_devname;	/* OBP name */
+	char		*s_obp_type;	/* OBP type */
+	sbd_comp_type_t	s_dnodetype;	/* SBD type */
+} sbd_devattr_t;
+
+typedef struct {
+	dnode_t		dnodeid;
+	uint64_t	*basepa;
+} sbd_basephys_t;
+
+typedef struct {
+	dev_t		h_dev;		/* dev_t of opened device */
+	int		h_cmd;		/* ioctl argument */
+	int		h_mode;
+	intptr_t	h_iap;	/* points to kernel copy of ioargs */
+} sbdp_ioctl_arg_t;
+
+
+struct sbd_mem_unit;		/* forward decl */
+
+int sbdp_setup_instance(caddr_t arg);
+int sbdp_teardown_instance(caddr_t arg);
+int sbdp_assign_board(sbdp_handle_t *hp);
+int sbdp_connect_board(sbdp_handle_t *hp);
+int sbdp_disconnect_board(sbdp_handle_t *hp);
+int sbdp_get_board_num(sbdp_handle_t *hp, dev_info_t *dip);
+int sbdp_get_board_status(sbdp_handle_t *, sbd_stat_t *);
+int sbdp_cancel_component_release(sbdp_handle_t *hp);
+processorid_t sbdp_get_cpuid(sbdp_handle_t *hp, dev_info_t *dip);
+int sbdp_connect_cpu(sbdp_handle_t *, dev_info_t *, processorid_t);
+int sbdp_disconnect_cpu(sbdp_handle_t *, dev_info_t *, processorid_t);
+sbd_devattr_t  *sbdp_get_devattr(void);
+int sbdp_get_mem_alignment(sbdp_handle_t *hp, dev_info_t *dip, uint64_t *align);
+struct memlist *sbdp_get_memlist(sbdp_handle_t *hp, dev_info_t *dip);
+int sbdp_del_memlist(sbdp_handle_t *hp, struct memlist *mlist);
+int sbdp_get_unit_num(sbdp_handle_t *hp, dev_info_t *dip);
+int sbdp_portid_to_cpu_unit(int cmp, int core);
+int sbdp_move_memory(sbdp_handle_t *, int t_bd);
+int sbdp_mem_add_span(sbdp_handle_t *hp, uint64_t address, uint64_t size);
+int sbdp_get_mem_size(sbdp_handle_t *hp);
+int sbdp_mem_del_span(sbdp_handle_t *hp, uint64_t address, uint64_t size);
+int sbdp_poweroff_board(sbdp_handle_t *hp);
+int sbdp_poweron_board(sbdp_handle_t *hp);
+int sbdp_release_component(sbdp_handle_t *hp, dev_info_t *dip);
+int sbdp_test_board(sbdp_handle_t *hp, sbdp_opts_t *opts);
+int sbdp_unassign_board(sbdp_handle_t *hp);
+int sbdphw_disable_memctrl(sbdp_handle_t *hp, dev_info_t *dip);
+int sbdphw_enable_memctrl(sbdp_handle_t *hp, dev_info_t *dip);
+int sbdphw_get_base_physaddr(sbdp_handle_t *hp, dev_info_t *dip, uint64_t *pa);
+int sbdp_isbootproc(processorid_t cpuid);
+int sbdp_ioctl(sbdp_handle_t *, sbdp_ioctl_arg_t *);
+int sbdp_isinterleaved(sbdp_handle_t *, dev_info_t *);
+void sbdp_check_devices(dev_info_t *, int *refcount, sbd_error_t *);
+int sbdp_dr_avail(void);
+
+extern int sbdp_cpu_get_impl(sbdp_handle_t *hp, dev_info_t *dip);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SBD_H */
diff --git a/usr/src/uts/sun4u/sys/sbd_error.h b/usr/src/uts/sun4u/sys/sbd_error.h
new file mode 100644
index 0000000000..71d5789747
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/sbd_error.h
@@ -0,0 +1,96 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2000-2003 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_SBD_ERROR_H
+#define	_SYS_SBD_ERROR_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	SBD_TEST_BOARD_PSEUDO_ERR	1
+#define	SBD_ASSIGN_BOARD_PSEUDO_ERR	2
+#define	SBD_UNASSIGN_BOARD_PSEUDO_ERR	3
+#define	SBD_POWERON_BOARD_PSEUDO_ERR	4
+#define	SBD_POWEROFF_BOARD_PSEUDO_ERR	5
+#define	SBD_PROBE_BOARD_PSEUDO_ERR	6
+#define	SBD_DEPROBE_BOARD_PSEUDO_ERR	7
+#define	SBD_CONNECT_BOARD_PSEUDO_ERR	8
+#define	SBD_DISCONNECT_BOARD_PSEUDO_ERR	9
+#define	SBD_OFFLINE_CPU_PSEUDO_ERR	10
+#define	SBD_ONLINE_CPU_PSEUDO_ERR	11
+#define	SBD_POWEROFF_CPU_PSEUDO_ERR	12
+#define	SBD_POWERON_CPU_PSEUDO_ERR	13
+
+#ifdef DEBUG
+/* comment out the next line to turn off compilation of error injection */
+#define	SBD_DEBUG_ERRS
+
+#ifdef SBD_DEBUG_ERRS
+
+extern void sbd_inject_err(int error, sbderror_t *ep, int Errno, int ecode,
+	char *src);
+
+#define	SBD_DBG_ERRNO	0x00000001
+#define	SBD_DBG_CODE	0x00000002
+#define	SBD_DBG_RSC	0x00000004
+#define	SBD_DBG_ALL	0x0000000f
+
+#define	PR_ERR_ALL	if (sbd_print_errs & SBD_DBG_ALL)	printf
+#define	PR_ERR_ERRNO	if (sbd_print_errs & SBD_DBG_ERRNO)	printf
+#define	PR_ERR_ECODE	if (sbd_print_errs & SBD_DBG_CODE)	printf
+#define	PR_ERR_RSC	if (sbd_print_errs & SBD_DBG_RSC)	printf
+
+#define	SBD_INJECT_ERR	sbd_inject_err
+
+
+
+#else	/* SBD_DEBUG_ERRS */
+
+#define	SBD_INJECT_ERR
+#define	PR_ERR_ALL		if (0) printf
+#define	SBD_DBG_CODE	PR_ERR_ALL
+#define	SBD_DBG_ALL	PR_ERR_ALL
+
+#endif	/* SBD_DEBUG_ERRS */
+
+#else	/* DEBUG */
+
+#define	SBD_INJECT_ERR
+#define	PR_ERR_ALL		if (0) printf
+#define	PR_ERR_ERRNO		PR_ERR_ALL
+#define	PR_ERR_ECODE		PR_ERR_ALL
+#define	PR_ERR_RSC		PR_ERR_ALL
+
+#endif	/* DEBUG */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_SBD_ERROR_H */
diff --git a/usr/src/uts/sun4u/sys/sbd_io.h b/usr/src/uts/sun4u/sys/sbd_io.h
new file mode 100644
index 0000000000..5d80e74b87
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/sbd_io.h
@@ -0,0 +1,58 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _SYS_SBD_IO_H
+#define	_SYS_SBD_IO_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * All definitions for sbd io should go here
+ */
+
+void		sbd_attach_io(sbd_handle_t *, sbderror_t *, dev_info_t *, int);
+void		sbd_detach_io(sbd_handle_t *, sbderror_t *, dev_info_t *, int);
+int		sbd_check_io_refs(sbd_handle_t *, sbd_devlist_t *, int);
+int		sbd_check_io_attached(dev_info_t *, void *);
+int		sbd_io_status(sbd_handle_t *, sbd_devset_t, sbd_dev_stat_t *);
+void		sbd_init_io_unit(sbd_board_t *sbp, int);
+int		sbd_pre_detach_io(sbd_handle_t *, sbd_devlist_t *, int);
+int		sbd_post_detach_io(sbd_handle_t *, sbd_devlist_t *, int);
+int		sbd_pre_attach_io(sbd_handle_t *, sbd_devlist_t *, int);
+int		sbd_post_attach_io(sbd_handle_t *, sbd_devlist_t *, int);
+int		sbd_io_cnt(sbd_handle_t *, sbd_devset_t);
+int		sbd_pre_release_io(sbd_handle_t *, sbd_devlist_t *, int);
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _SYS_SBD_IO_H */
diff --git a/usr/src/uts/sun4u/sys/sbd_ioctl.h b/usr/src/uts/sun4u/sys/sbd_ioctl.h
new file mode 100644
index 0000000000..6826e28e9f
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/sbd_ioctl.h
@@ -0,0 +1,584 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SBD_IOCTL_H
+#define	_SBD_IOCTL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/types.h>
+#include <sys/obpdefs.h>
+#include <sys/processor.h>
+#include <sys/param.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+	SBD_COMP_NONE,
+	SBD_COMP_CPU,
+	SBD_COMP_MEM,
+	SBD_COMP_IO,
+	SBD_COMP_CMP,
+	SBD_COMP_UNKNOWN
+} sbd_comp_type_t;
+
+typedef enum {
+	SBD_STAT_NONE = 0,
+	SBD_STAT_EMPTY,
+	SBD_STAT_DISCONNECTED,
+	SBD_STAT_CONNECTED,
+	SBD_STAT_UNCONFIGURED,
+	SBD_STAT_CONFIGURED
+} sbd_state_t;
+
+typedef enum {
+	SBD_COND_UNKNOWN = 0,
+	SBD_COND_OK,
+	SBD_COND_FAILING,
+	SBD_COND_FAILED,
+	SBD_COND_UNUSABLE
+} sbd_cond_t;
+
+typedef	int	sbd_busy_t;
+
+#define	SBD_MAX_UNSAFE		16
+#define	SBD_TYPE_LEN		12
+#define	SBD_NULL_UNIT		-1
+
+typedef struct {
+	sbd_comp_type_t	c_type;
+	int		c_unit;
+	char		c_name[OBP_MAXPROPNAME];
+} sbd_comp_id_t;
+
+typedef struct {
+	sbd_comp_id_t	c_id;
+	sbd_state_t	c_ostate;
+	sbd_cond_t	c_cond;
+	sbd_busy_t	c_busy;
+	uint_t		c_sflags;
+	time_t		c_time;
+} sbd_cm_stat_t;
+
+#define	ci_type		c_id.c_type
+#define	ci_unit		c_id.c_unit
+#define	ci_name		c_id.c_name
+
+typedef struct {
+	sbd_cm_stat_t	cs_cm;
+	int		cs_isbootproc;
+	processorid_t	cs_cpuid;
+	int		cs_speed;
+	int		cs_ecache;
+} sbd_cpu_stat_t;
+
+#define	cs_type		cs_cm.ci_type
+#define	cs_unit		cs_cm.ci_unit
+#define	cs_name		cs_cm.ci_name
+#define	cs_ostate	cs_cm.c_ostate
+#define	cs_cond		cs_cm.c_cond
+#define	cs_busy		cs_cm.c_busy
+#define	cs_suspend	cs_cm.c_sflags
+#define	cs_time		cs_cm.c_time
+
+typedef struct {
+	sbd_cm_stat_t	ms_cm;
+	int		ms_interleave;
+	pfn_t		ms_basepfn;
+	pgcnt_t		ms_totpages;
+	pgcnt_t		ms_detpages;
+	pgcnt_t		ms_pageslost;
+	pgcnt_t		ms_managed_pages;
+	pgcnt_t		ms_noreloc_pages;
+	pgcnt_t		ms_noreloc_first;
+	pgcnt_t		ms_noreloc_last;
+	int		ms_cage_enabled;
+	int		ms_peer_is_target;	/* else peer is source */
+	char		ms_peer_ap_id[MAXPATHLEN];	/* board's AP name */
+} sbd_mem_stat_t;
+
+#define	ms_type		ms_cm.ci_type
+#define	ms_unit		ms_cm.ci_unit
+#define	ms_name		ms_cm.ci_name
+#define	ms_ostate	ms_cm.c_ostate
+#define	ms_cond		ms_cm.c_cond
+#define	ms_busy		ms_cm.c_busy
+#define	ms_suspend	ms_cm.c_sflags
+#define	ms_time		ms_cm.c_time
+
+typedef struct {
+	sbd_cm_stat_t	is_cm;
+	int		is_referenced;
+	int		is_unsafe_count;
+	int		is_unsafe_list[SBD_MAX_UNSAFE];
+	char		is_pathname[MAXPATHLEN];
+} sbd_io_stat_t;
+
+#define	is_type		is_cm.ci_type
+#define	is_unit		is_cm.ci_unit
+#define	is_name		is_cm.ci_name
+#define	is_ostate	is_cm.c_ostate
+#define	is_cond		is_cm.c_cond
+#define	is_busy		is_cm.c_busy
+#define	is_suspend	is_cm.c_sflags
+#define	is_time		is_cm.c_time
+
+#define	SBD_MAX_CORES_PER_CMP	2
+
+typedef struct {
+	sbd_cm_stat_t	ps_cm;
+	processorid_t	ps_cpuid[SBD_MAX_CORES_PER_CMP];
+	int		ps_ncores;
+	int		ps_speed;
+	int		ps_ecache;
+} sbd_cmp_stat_t;
+
+#define	ps_type		ps_cm.ci_type
+#define	ps_unit		ps_cm.ci_unit
+#define	ps_name		ps_cm.ci_name
+#define	ps_ostate	ps_cm.c_ostate
+#define	ps_cond		ps_cm.c_cond
+#define	ps_busy		ps_cm.c_busy
+#define	ps_suspend	ps_cm.c_sflags
+#define	ps_time		ps_cm.c_time
+
+typedef union {
+	sbd_cm_stat_t	d_cm;
+	sbd_cpu_stat_t	d_cpu;
+	sbd_mem_stat_t	d_mem;
+	sbd_io_stat_t	d_io;
+	sbd_cmp_stat_t	d_cmp;
+} sbd_dev_stat_t;
+
+#define	ds_type		d_cm.ci_type
+#define	ds_unit		d_cm.ci_unit
+#define	ds_name		d_cm.ci_name
+#define	ds_ostate	d_cm.c_ostate
+#define	ds_cond		d_cm.c_cond
+#define	ds_busy		d_cm.c_busy
+#define	ds_suspend	d_cm.c_sflags
+#define	ds_time		d_cm.c_time
+
+#define	SBD_MAX_INFO	64
+
+typedef struct {
+	int		s_board;
+	char		s_type[SBD_TYPE_LEN];
+	char		s_info[SBD_MAX_INFO];
+	sbd_state_t	s_rstate;
+	sbd_state_t	s_ostate;
+	sbd_cond_t	s_cond;
+	sbd_busy_t	s_busy;
+	time_t		s_time;
+	uint_t		s_power:1;
+	uint_t		s_assigned:1;
+	uint_t		s_platopts;
+	int		s_nstat;
+	sbd_dev_stat_t	s_stat[1];
+} sbd_stat_t;
+
+typedef struct {
+	sbd_comp_id_t	c_id;
+	uint_t		c_flags;
+	int		c_len;
+	caddr_t		c_opts;
+} sbd_cm_cmd_t;
+
+typedef struct {
+	sbd_cm_cmd_t	g_cm;
+	int		g_ncm;
+} sbd_getncm_cmd_t;
+
+typedef struct {
+	sbd_cm_cmd_t	s_cm;
+	int		s_nbytes;
+	caddr_t		s_statp;
+} sbd_stat_cmd_t;
+
+typedef union {
+	sbd_cm_cmd_t		cmd_cm;
+	sbd_getncm_cmd_t	cmd_getncm;
+	sbd_stat_cmd_t		cmd_stat;
+} sbd_cmd_t;
+
+typedef struct {
+	int		e_code;
+	char		e_rsc[MAXPATHLEN];
+} sbd_error_t;
+
+typedef struct {
+	sbd_cmd_t	i_cmd;
+	sbd_error_t	i_err;
+} sbd_ioctl_arg_t;
+
+typedef struct {
+	int		t_base;
+	int		t_bnd;
+	char		**t_text;
+} sbd_etab_t;
+
+#define	i_flags		i_cmd.cmd_cm.c_flags
+#define	i_len		i_cmd.cmd_cm.c_len
+#define	i_opts		i_cmd.cmd_cm.c_opts
+#define	ic_type		i_cmd.cmd_cm.ci_type
+#define	ic_name		i_cmd.cmd_cm.ci_name
+#define	ic_unit		i_cmd.cmd_cm.ci_unit
+#define	ie_code		i_err.e_code
+#define	ie_rsc		i_err.e_rsc
+
+#define	_SBD_IOC		(('D' << 16) | ('R' << 8))
+
+#define	SBD_CMD_ASSIGN		(_SBD_IOC | 0x01)
+#define	SBD_CMD_UNASSIGN	(_SBD_IOC | 0x02)
+#define	SBD_CMD_POWERON		(_SBD_IOC | 0x03)
+#define	SBD_CMD_POWEROFF	(_SBD_IOC | 0x04)
+#define	SBD_CMD_TEST		(_SBD_IOC | 0x05)
+#define	SBD_CMD_CONNECT		(_SBD_IOC | 0x06)
+#define	SBD_CMD_CONFIGURE	(_SBD_IOC | 0x07)
+#define	SBD_CMD_UNCONFIGURE	(_SBD_IOC | 0x08)
+#define	SBD_CMD_DISCONNECT	(_SBD_IOC | 0x09)
+#define	SBD_CMD_STATUS		(_SBD_IOC | 0x0a)
+#define	SBD_CMD_GETNCM		(_SBD_IOC | 0x0b)
+#define	SBD_CMD_PASSTHRU	(_SBD_IOC | 0x0c)
+
+#define	SBD_CHECK_SUSPEND(cmd, c_sflags) \
+		(((c_sflags) >> (((cmd) & 0xf) - 1)) & 0x01)
+
+#define	SBD_SET_SUSPEND(cmd, c_sflags) \
+		((c_sflags) |= (0x01 << (((cmd) & 0xf) - 1)))
+
+#define	SBD_CHECK_PLATOPTS(cmd, c_platopts) \
+		(((c_platopts) >> (((cmd) & 0xf) - 1)) & 0x01)
+
+#define	SBD_SET_PLATOPTS(cmd, c_platopts) \
+		((c_platopts) &= ~(0x01 << (((cmd) & 0xf) - 1)))
+
+#define	SBD_FLAG_FORCE		0x1
+#define	SBD_FLAG_ALLCMP		0x2
+#define	SBD_FLAG_QUIESCE_OKAY	0x4
+
+#if defined(_SYSCALL32)
+
+typedef struct {
+	int32_t		c_type;
+	int32_t		c_unit;
+	char		c_name[OBP_MAXPROPNAME];
+} sbd_comp_id32_t;
+
+typedef struct {
+	sbd_comp_id32_t	c_id;
+	int32_t		c_ostate;
+	int32_t		c_cond;
+	int32_t		c_busy;
+	uint32_t	c_sflags;
+	time32_t	c_time;
+} sbd_cm_stat32_t;
+
+typedef struct {
+	sbd_cm_stat32_t	cs_cm;
+	int32_t		cs_isbootproc;
+	int32_t		cs_cpuid;
+	int32_t		cs_speed;
+	int32_t		cs_ecache;
+} sbd_cpu_stat32_t;
+
+typedef struct {
+	sbd_cm_stat32_t	ms_cm;
+	int32_t		ms_interleave;
+	uint32_t	ms_basepfn;
+	uint32_t	ms_totpages;
+	uint32_t	ms_detpages;
+	int32_t		ms_pageslost;
+	uint32_t	ms_managed_pages;
+	uint32_t	ms_noreloc_pages;
+	uint32_t	ms_noreloc_first;
+	uint32_t	ms_noreloc_last;
+	int32_t		ms_cage_enabled;
+	int32_t		ms_peer_is_target;
+	char		ms_peer_ap_id[MAXPATHLEN];
+} sbd_mem_stat32_t;
+
+typedef struct {
+	sbd_cm_stat32_t	is_cm;
+	int32_t		is_referenced;
+	int32_t		is_unsafe_count;
+	int32_t		is_unsafe_list[SBD_MAX_UNSAFE];
+	char		is_pathname[MAXPATHLEN];
+} sbd_io_stat32_t;
+
+typedef struct {
+	sbd_cm_stat32_t	ps_cm;
+	int32_t		ps_cpuid[SBD_MAX_CORES_PER_CMP];
+	int32_t		ps_ncores;
+	int32_t		ps_speed;
+	int32_t		ps_ecache;
+} sbd_cmp_stat32_t;
+
+typedef union {
+	sbd_cm_stat32_t		d_cm;
+	sbd_cpu_stat32_t	d_cpu;
+	sbd_mem_stat32_t	d_mem;
+	sbd_io_stat32_t		d_io;
+	sbd_cmp_stat32_t	d_cmp;
+} sbd_dev_stat32_t;
+
+typedef struct {
+	int32_t			s_board;
+	char			s_type[SBD_TYPE_LEN];
+	char			s_info[SBD_MAX_INFO];
+	int32_t			s_rstate;
+	int32_t			s_ostate;
+	int32_t			s_cond;
+	int32_t			s_busy;
+	time32_t		s_time;
+	uint32_t		s_power:1;
+	uint32_t		s_assigned:1;
+	uint32_t		s_platopts;
+	int32_t			s_nstat;
+	sbd_dev_stat32_t	s_stat[1];
+} sbd_stat32_t;
+
+typedef struct {
+	int32_t			e_code;
+	char			e_rsc[MAXPATHLEN];
+} sbd_error32_t;
+
+typedef struct {
+	sbd_comp_id32_t		c_id;
+	uint32_t		c_flags;
+	int32_t			c_len;
+	caddr32_t		c_opts;
+} sbd_cm_cmd32_t;
+
+typedef struct {
+	sbd_cm_cmd32_t	g_cm;
+	int32_t		g_ncm;
+} sbd_getncm_cmd32_t;
+
+typedef struct {
+	sbd_cm_cmd32_t	s_cm;
+	int32_t		s_nbytes;
+	caddr32_t	s_statp;
+} sbd_stat_cmd32_t;
+
+typedef union {
+	sbd_cm_cmd32_t		cmd_cm;
+	sbd_getncm_cmd32_t	cmd_getncm;
+	sbd_stat_cmd32_t	cmd_stat;
+} sbd_cmd32_t;
+
+typedef struct {
+	sbd_cmd32_t		i_cmd;
+	sbd_error32_t		i_err;
+} sbd_ioctl_arg32_t;
+
+typedef struct {
+	int32_t			t_base;
+	int32_t			t_bnd;
+	char			**t_text;
+} sbd_etab32_t;
+
+#endif	/* _SYSCALL32 */
+
+/* Common error codes */
+
+#define	ESBD_NOERROR		0	/* no error */
+#define	ESBD_INTERNAL		1	/* Internal error */
+#define	ESBD_NOMEM		2	/* Insufficient memory */
+#define	ESBD_PROTO		3	/* Protocol error */
+#define	ESBD_BUSY		4	/* Device busy */
+#define	ESBD_NODEV		5	/* No such device */
+#define	ESBD_ALREADY		6	/* Operation already in progress */
+#define	ESBD_IO			7	/* I/O error */
+#define	ESBD_FAULT		8	/* Bad address */
+#define	ESBD_EMPTY_BD		9	/* No device(s) on board */
+#define	ESBD_INVAL		10	/* Invalid argument */
+#define	ESBD_STATE		11	/* Invalid state transition */
+#define	ESBD_FATAL_STATE	12	/* Device in fatal state */
+#define	ESBD_OUTSTANDING	13	/* Outstanding error */
+#define	ESBD_SUSPEND		14	/* Device failed to suspend */
+#define	ESBD_RESUME		15	/* Device failed to resume */
+#define	ESBD_UTHREAD		16	/* Cannot stop user thread */
+#define	ESBD_RTTHREAD		17	/* Cannot quiesce realtime thread */
+#define	ESBD_KTHREAD		18	/* Cannot stop kernel thread  */
+#define	ESBD_OFFLINE		19	/* Failed to off-line */
+#define	ESBD_ONLINE		20	/* Failed to on-line */
+#define	ESBD_CPUSTART		21	/* Failed to start CPU */
+#define	ESBD_CPUSTOP		22	/* Failed to stop CPU */
+#define	ESBD_INVAL_COMP		23	/* Invalid component type */
+#define	ESBD_KCAGE_OFF		24	/* Kernel cage is disabled */
+#define	ESBD_NO_TARGET		25	/* No available memory target */
+#define	ESBD_HW_PROGRAM		26	/* Hardware programming error */
+#define	ESBD_MEM_NOTVIABLE	27	/* VM viability test failed */
+#define	ESBD_MEM_REFUSED	28	/* Memory operation refused */
+#define	ESBD_MEM_NONRELOC	29	/* Non-relocatable pages in span */
+#define	ESBD_MEM_CANCELLED	30	/* Memory operation cancelled */
+#define	ESBD_MEMFAIL		31	/* Memory operation failed */
+#define	ESBD_MEMONLINE		32	/* Can't unconfig cpu if mem online */
+#define	ESBD_QUIESCE_REQD	33
+	/* Operator confirmation for quiesce is required */
+#define	ESBD_MEMINTLV		34
+	/* Memory is interleaved across boards */
+#define	ESBD_CPUONLINE		35
+	/* Can't config memory if not all cpus are online */
+#define	ESBD_UNSAFE		36	/* Unsafe driver present */
+#define	ESBD_INVAL_OPT		37	/* option invalid */
+
+/* Starcat error codes */
+
+#define	ESTC_NONE		1000	/* No error */
+#define	ESTC_GETPROP		1001	/* Cannot read property value */
+#define	ESTC_BNUM		1002	/* Invalid board number */
+#define	ESTC_CONFIGBUSY		1003
+	/* Cannot proceed; Board is configured or busy */
+#define	ESTC_PROBE		1004	/* Solaris failed to probe */
+#define	ESTC_DEPROBE		1005	/* Solaris failed to deprobe */
+#define	ESTC_MOVESIGB		1006	/* Firmware move-cpu0 failed */
+#define	ESTC_SUPPORT		1007	/* Operation not supported */
+#define	ESTC_DRVFAIL		1008	/* Device driver failure */
+#define	ESTC_UNKPTCMD		1012	/* Unrecognized platform command */
+#define	ESTC_NOTID		1013
+	/* drmach parameter is not a valid ID */
+#define	ESTC_INAPPROP		1014
+	/* drmach parameter is inappropriate for operation */
+#define	ESTC_INTERNAL		1015	/* Unexpected internal condition */
+#define	ESTC_MBXRQST		1016
+	/* Mailbox framework failure: outgoing */
+#define	ESTC_MBXRPLY		1017
+	/* Mailbox framework failure: incoming */
+#define	ESTC_NOACL		1018	/* Board is not in domain ACL */
+#define	ESTC_NOT_ASSIGNED	1019	/* Board is not assigned to domain */
+#define	ESTC_NOT_ACTIVE		1020	/* Board is not active */
+#define	ESTC_EMPTY_SLOT		1021	/* Slot is empty */
+#define	ESTC_POWER_OFF		1022	/* Board is powered off */
+#define	ESTC_TEST_IN_PROGRESS	1023	/* Board is already being tested */
+#define	ESTC_TESTING_BUSY	1024
+	/* Wait: All SC test resources are in use */
+#define	ESTC_TEST_REQUIRED	1025	/* Board requires test prior to use */
+#define	ESTC_TEST_ABORTED	1026	/* Board test has been aborted */
+#define	ESTC_MBOX_UNKNOWN	1027
+	/* Unknown error type received from SC */
+#define	ESTC_TEST_STATUS_UNKNOWN	1028
+	/* Test completed with unknown status */
+#define	ESTC_TEST_RESULT_UNKNOWN	1029
+	/* Unknown test result returned by SC */
+#define	ESTC_TEST_FAILED	1030
+	/* SMS hpost reported error, see POST log for details */
+#define	ESTC_UNAVAILABLE	1031	/* Slot is unavailable to the domain */
+#define	ESTC_NZ_LPA		1032	/* Nonzero LPA not yet supported */
+#define	ESTC_IOSWITCH		1033
+	/* Cannot unconfigure I/O board: tunnel switch failed */
+#define	ESTC_IOCAGE_NO_CPU_AVAIL	1034
+	/* No CPU available for I/O cage test. */
+#define	ESTC_SMS_ERR_RECOVERABLE	1035
+	/* SMS reported recoverable error: check SMS status and Retry */
+#define	ESTC_SMS_ERR_UNRECOVERABLE	1036
+	/* SMS reported unrecoverable error: Board is Unusable */
+#define	ESTC_NWSWITCH		1037
+	/* Cannot unconfigure I/O board: network switch failed */
+
+/* Starfire error codes */
+
+#define	ESTF_NONE		2000	/* No error */
+#define	ESTF_GETPROP		2001	/* Cannot read property value */
+#define	ESTF_GETPROPLEN		2002	/* Cannot determine property length */
+#define	ESTF_BNUM		2003	/* Invalid board number */
+#define	ESTF_CONFIGBUSY		2004
+	/* Cannot proceed; Board is configured or busy */
+#define	ESTF_NOCPUID		2005	/* No CPU specified for connect */
+#define	ESTF_PROBE		2006	/* Firmware probe failed */
+#define	ESTF_DEPROBE		2007	/* Firmware deprobe failed */
+#define	ESTF_MOVESIGB		2008	/* Firmware move-cpu0 failed */
+#define	ESTF_JUGGLE		2009	/* Cannot move SIGB assignment */
+#define	ESTF_HASSIGB		2010
+	/* Cannot disconnect CPU; SIGB is currently assigned */
+#define	ESTF_SUPPORT		2011	/* Operation not supported */
+#define	ESTF_DRVFAIL		2012	/* Device driver failure */
+#define	ESTF_SETCPUVAL		2013
+	/* Must specify a CPU on the given board */
+#define	ESTF_NODEV		2014	/* No such device */
+#define	ESTF_INTERBOARD		2015
+	/* Memory configured with inter-board interleaving */
+#define	ESTF_UNKPTCMD		2016	/* Unrecognized platform command */
+#define	ESTF_NOTID		2017	/* drmach parameter is not a valid ID */
+#define	ESTF_INAPPROP		2018
+	/* drmach parameter is inappropriate for operation */
+#define	ESTF_INTERNAL		2019	/* Unexpected internal condition */
+
+/* Daktari error codes */
+
+#define	EDAK_NONE		3000	/* no error */
+#define	EDAK_INTERNAL		3001	/* Internal error */
+#define	EDAK_NOFRUINFO		3002	/* Didn't receive fru info */
+#define	EDAK_NONDR_BOARD	3003
+	/* DR is not supported on this board type */
+#define	EDAK_POWERON		3004	/* Power on request failed */
+#define	EDAK_POWEROK		3005	/* Failed to power on */
+#define	EDAK_INTERRUPTED	3006	/* Operation interrupted */
+#define	EDAK_BOARDINIT		3007	/* Board initialization failed */
+#define	EDAK_CPUINIT		3008	/* CPU intialization failed */
+#define	EDAK_MEMFAIL		3009	/* Memory operation failed */
+
+/* Serengeti error codes */
+
+#define	ESGT_NONE		4000	/* no error */
+#define	ESGT_INTERNAL		4001	/* Internal error */
+#define	ESGT_INVAL		4002	/* Invalid argument */
+#define	ESGT_MEMFAIL		4003	/* Memory operation failed */
+#define	ESGT_PROBE		4004	/* Board probe failed */
+#define	ESGT_DEPROBE		4005	/* Board deprobe failed */
+#define	ESGT_JUGGLE_BOOTPROC	4006	/* Failed to juggle bootproc */
+#define	ESGT_NOT_CPUTYPE	4007	/* Not a cpu device */
+#define	ESGT_NO_DEV_TYPE	4008	/* Cannot find device type */
+#define	ESGT_BAD_PORTID		4009	/* Bad port id */
+#define	ESGT_RESUME		4010	/* Failed to resume device */
+#define	ESGT_SUSPEND		4011	/* Failed to suspend device */
+#define	ESGT_KTHREAD		4012	/* failed to stop kernel thd */
+#define	ESGT_UNSAFE		4013	/* unsafe */
+#define	ESGT_RTTHREAD		4014	/* real time threads */
+#define	ESGT_UTHREAD		4015	/* failed to stop user thd */
+#define	ESGT_PROM_ATTACH	4016	/* prom failed attach board */
+#define	ESGT_PROM_DETACH	4017	/* prom failed detach board */
+#define	ESGT_SC_ERR		4018	/* sc return a failure */
+#define	ESGT_GET_BOARD_STAT	4019	/* Failed to obtain board information */
+#define	ESGT_WAKEUPCPU		4020	/* Failed to wake up cpu */
+#define	ESGT_STOPCPU		4021	/* Failed to stop cpu */
+/* Serengeti SC return codes */
+#define	ESGT_HW_FAIL		4022	/* Hardware Failure */
+#define	ESGT_BD_ACCESS		4023	/* Board access denied */
+#define	ESGT_STALE_CMP		4024	/* Stale components */
+#define	ESGT_STALE_OBJ		4025	/* Stale objects */
+#define	ESGT_NO_SEPROM_SPACE	4026	/* No SEPROM space */
+#define	ESGT_NOT_SUPP		4027	/* Operation not supported */
+#define	ESGT_NO_MEM		4028	/* No Memory */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SBD_IOCTL_H */
diff --git a/usr/src/uts/sun4u/sys/sbdpriv.h b/usr/src/uts/sun4u/sys/sbdpriv.h
new file mode 100644
index 0000000000..4f15ebb8c7
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/sbdpriv.h
@@ -0,0 +1,753 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_SBDPRIV_H
+#define	_SYS_SBDPRIV_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/processor.h>
+#include <sys/obpdefs.h>
+#include <sys/memlist.h>
+#include <sys/sbd_ioctl.h>
+#include <sys/mem_config.h>
+#include <sys/sbd.h>
+#ifdef DEBUG
+#include <sys/promif.h>
+#endif
+
+
+/*
+ * This structure passes the information when the caller requests to
+ * reserve a portion of unconfigured memory. It is also used to release
+ * previously reserved memory
+ */
+struct sbd_mres {
+	uint64_t	new_base_pa;	/* new base addr for physintalled */
+	uint64_t	reserved_pa;	/* addr of the reserved mem */
+	uint64_t	size;		/* size of the reserved chunk. */
+};
+
+int sbd_memory_reserve(dev_info_t *, uint64_t, struct sbd_mres *);
+int sbd_memory_release(dev_info_t *, uint64_t, struct sbd_mres *);
+
+/*	This error type is used inside sbd only */
+typedef struct {
+	int	e_errno;
+	int	e_code;
+	char	e_rsc[MAXPATHLEN];
+} sbderror_t;
+
+#include <sys/sbd.h>
+#include <sys/sbd_error.h>
+
+typedef enum {
+	SBD_STATE_EMPTY = 0,
+	SBD_STATE_OCCUPIED,
+	SBD_STATE_CONNECTED,
+	SBD_STATE_UNCONFIGURED,
+	SBD_STATE_PARTIAL,
+	SBD_STATE_CONFIGURED,
+	SBD_STATE_RELEASE,
+	SBD_STATE_UNREFERENCED,
+	SBD_STATE_FATAL,
+	SBD_STATE_MAX
+} sbd_istate_t;
+
+typedef struct {
+	sbderror_t	*errp;
+	sbd_flags_t	flags;
+} sbd_treeinfo_t;
+
+/*
+ * generic flags (sbd_handle.h_flags)
+ */
+#define	SBD_FLAG_DEVI_FORCE	0x00000001
+
+/* mirror of SBD_FLAG_FORCE from sbd_ioctl.h */
+#define	SBD_IOCTL_FLAG_FORCE	0x00000004
+
+#define	SBD_USER_FLAG_MASK	0x0000ffff
+
+#define	SBD_KERN_FLAG_MASK	0xffff0000	/* no flags in use */
+
+/*
+ * Translation macros for sbd->sbdp flags
+ */
+#define	SBD_2_SBDP_FLAGS(f) (((f) & SBD_IOCTL_FLAG_FORCE) ? \
+				SBDP_IOCTL_FLAG_FORCE : 0)
+
+typedef struct sbd_handle {
+	void 		*h_sbd;
+	sbderror_t	*h_err;
+	dev_t		h_dev;		/* dev_t of opened device */
+	int		h_cmd;		/* ioctl argument */
+	int		h_mode;		/* device open mode */
+	sbd_flags_t	h_flags;
+	sbd_ioctl_arg_t	*h_iap;		/* points to kernel copy of ioargs */
+	sbdp_opts_t	h_opts;		/* points to the platform options */
+} sbd_handle_t;
+
+#define	SBD_HD2ERR(hd)		((hd)->h_err)
+#define	SBD_GET_ERR(ep)		((ep)->e_code)
+#define	SBD_SET_ERR(ep, ec)	((ep)->e_code = (ec))
+#define	SBD_GET_ERRNO(ep)	((ep)->e_errno)
+#define	SBD_SET_ERRNO(ep, en)	((ep)->e_errno = (en))
+#define	SBD_GET_ERRSTR(ep)	((ep)->e_rsc)
+
+#define	SBD_SET_ERRSTR(ep, es)	\
+{ \
+	if ((es) && (*(es) != '\0')) \
+		(void) strncpy((ep)->e_rsc, (es), MAXPATHLEN); \
+}
+
+#define	SBD_SET_IOCTL_ERR(ierr, code, rsc) \
+{ \
+	(ierr)->e_code = (int)(code); \
+	if ((rsc) && (*(rsc) != '\0')) \
+		bcopy((caddr_t)(rsc), \
+			(caddr_t)(ierr)->e_rsc, \
+			sizeof ((ierr)->e_rsc)); \
+}
+
+#define	SBD_FREE_ERR(ep) \
+	((ep)->e_rsc[0] = '\0')
+
+#define	SBD_GET_PERR(spe, ep) \
+	(ep)->e_errno = EIO; \
+	(ep)->e_code = (spe)->e_code; \
+	if (*((spe)->e_rsc) != '\0') \
+		bcopy((caddr_t)((spe)->e_rsc), \
+			(caddr_t)((ep))->e_rsc, \
+			sizeof (((ep))->e_rsc));
+
+/*
+ * dev_t is shared by PIM and PSM layers.
+ *
+ * Format = 31......16,15.......0
+ *	    |   PIM   |   PSM   |
+ */
+#define	_SBD_DEVPIM_SHIFT	16
+#define	_SBD_DEVPIM_MASK		0xffff
+#define	_SBD_DEVPSM_MASK		0xffff
+
+#define	SBD_GET_MINOR2INST(d)	(((d) >> _SBD_DEVPIM_SHIFT) & _SBD_DEVPIM_MASK)
+#define	SBD_MAKE_MINOR(i, m) \
+			((((i) & _SBD_DEVPIM_MASK) << _SBD_DEVPIM_SHIFT) | \
+			((m) & _SBD_DEVPSM_MASK))
+
+#define	GETSTRUCT(t, n) \
+		((t *)kmem_zalloc((size_t)(n) * sizeof (t), KM_SLEEP))
+#define	FREESTRUCT(p, t, n) \
+		(kmem_free((caddr_t)(p), sizeof (t) * (size_t)(n)))
+
+#define	GET_SOFTC(i)		ddi_get_soft_state(sbd_g.softsp, (i))
+#define	ALLOC_SOFTC(i)		ddi_soft_state_zalloc(sbd_g.softsp, (i))
+#define	FREE_SOFTC(i)		ddi_soft_state_free(sbd_g.softsp, (i))
+
+/*
+ * Per instance soft-state structure.
+ */
+typedef struct sbd_softstate {
+	void		*sbd_boardlist;
+	int		max_boards;
+	int		wnode;
+} sbd_softstate_t;
+
+/*
+ * dr Global data elements
+ */
+typedef struct {
+	sbd_softstate_t	*softsp;	/* pointer to initialize soft state */
+} sbd_global;
+
+typedef struct {
+	sbderror_t	dv_error;
+	dev_info_t	*dv_dip;
+} sbd_devlist_t;
+
+extern int	plat_max_io_units_per_board();
+extern int	plat_max_cmp_units_per_board();
+extern int	plat_max_cpu_units_per_board();
+extern int	plat_max_mem_units_per_board();
+#define	MAX_IO_UNITS_PER_BOARD		plat_max_io_units_per_board()
+#define	MAX_CMP_UNITS_PER_BOARD		plat_max_cmp_units_per_board()
+#define	MAX_CPU_UNITS_PER_BOARD		plat_max_cpu_units_per_board()
+#define	MAX_MEM_UNITS_PER_BOARD		plat_max_mem_units_per_board()
+#define	SBD_MAX_UNITS_PER_BOARD		8
+/* If any of the max units exceeds 5, this must be adjusted	*/
+
+#define	SBD_MAX_INSTANCES		16
+
+#define	SBD_NUM_STATES		((int)SBD_STATE_MAX)
+
+#ifdef DEBUG
+#define	SBD_DEVICE_TRANSITION(sb, nt, un, st) \
+{ \
+	int	_ostate, _nstate; \
+	_ostate = (int)((sb)->sb_dev[NIX(nt)][un].u_common.sbdev_state); \
+	_nstate = (int)(st); \
+	PR_STATE("BOARD %d (%s.%d) STATE: %s(%d) -> %s(%d)\n", \
+		(sb)->sb_num, \
+		sbd_ct_str[nt], (un), \
+		sbd_state_str[_ostate], _ostate, \
+		sbd_state_str[_nstate], _nstate); \
+	(void) drv_getparm(TIME, \
+	(void *)&(sb)->sb_dev[NIX(nt)][un].u_common.sbdev_time); \
+	(sb)->sb_dev[NIX(nt)][un].u_common.sbdev_state = (st); \
+	(sb)->sb_dev[NIX(nt)][un].u_common.sbdev_ostate = ostate_cvt(st); \
+	send_event = 1; \
+}
+#define	SBD_BOARD_TRANSITION(sb, st) \
+{ \
+	PR_STATE("BOARD %d STATE: %s(%d) -> %s(%d)\n", \
+		(sb)->sb_num, \
+		sbd_state_str[(int)(sb)->sb_state], (int)(sb)->sb_state, \
+		sbd_state_str[(int)(st)], (int)(st)); \
+	(sb)->sb_pstate = (sb)->sb_state; \
+	(sb)->sb_state = (st); \
+	send_event = 1; \
+}
+#else /* DEBUG */
+#define	SBD_DEVICE_TRANSITION(sb, nt, un, st) \
+{ \
+	(sb)->sb_dev[NIX(nt)][un].u_common.sbdev_state = (st); \
+	(sb)->sb_dev[NIX(nt)][un].u_common.sbdev_ostate = ostate_cvt(st); \
+	(void) drv_getparm(TIME, \
+		(void *)&(sb)->sb_dev[NIX(nt)][un].u_common.sbdev_time); \
+	send_event = 1; \
+}
+#define	SBD_BOARD_TRANSITION(sb, st) \
+		((sb)->sb_pstate = (sb)->sb_state, (sb)->sb_state = (st),  \
+		send_event = 1)
+#endif /* DEBUG */
+
+#define	SBD_DEVICE_STATE(sb, nt, un) \
+		((sb)->sb_dev[NIX(nt)][un].u_common.sbdev_state)
+#define	SBD_BOARD_STATE(sb) \
+		((sb)->sb_state)
+#define	SBD_BOARD_PSTATE(sb) \
+		((sb)->sb_pstate)
+
+typedef uint32_t sbd_devset_t;
+
+/*
+ * sbd_priv_handle_t MUST appear first.
+ */
+typedef struct sbd_priv_handle {
+	sbd_handle_t		sh_handle;
+	void			*sh_arg;	/* raw ioctl arg */
+	sbd_devset_t		sh_devset;	/* based on h_dev */
+	sbd_devset_t		sh_orig_devset;	/* what client requested */
+	sbderror_t		sh_err;
+	struct sbd_priv_handle	*sh_next;
+} sbd_priv_handle_t;
+
+#define	SBD_MAXNUM_NT		3
+#define	NIX(t)			(((t) == SBD_COMP_CPU) ? 0 : \
+				((t) == SBD_COMP_MEM) ? 1 : \
+				((t) == SBD_COMP_IO) ? 2 : \
+				((t) == SBD_COMP_CMP) ? 0 : SBD_MAXNUM_NT)
+
+#define	SBD_NUM_MC_PER_BOARD	4
+
+
+typedef struct sbd_common_unit {
+	sbd_istate_t		sbdev_state;
+	sbd_cond_t		sbdev_cond;
+	sbd_state_t		sbdev_ostate;
+	time_t			sbdev_time;
+	int			sbdev_busy;
+	void			*sbdev_sbp;
+	int			sbdev_unum;
+	sbd_comp_type_t		sbdev_type;
+	dev_info_t		*sbdev_dip;
+} sbd_common_unit_t;
+
+typedef struct sbd_mem_unit {
+	sbd_common_unit_t	sbm_cm;
+	sbd_istate_t		sbm_state;	/* mem-unit state */
+	uint_t			sbm_flags;
+	pfn_t			sbm_basepfn;
+	pgcnt_t			sbm_npages;
+	pgcnt_t			sbm_pageslost;
+	/*
+	 * The following fields are used during
+	 * the memory detach process only. sbm_mlist
+	 * will be used to store the board memlist
+	 * following a detach. The memlist will be
+	 * used to re-attach the board when configuring
+	 * the unit directly after an unconfigure.
+	 */
+	struct sbd_mem_unit	*sbm_peer;
+	struct memlist		*sbm_mlist;
+	struct memlist		*sbm_del_mlist;
+	memhandle_t		sbm_memhandle;
+	pfn_t			sbm_alignment_mask;
+	pfn_t			sbm_slice_offset;
+	/*
+	 * The following field is used to support the
+	 * representation of all memory controllers on
+	 * a board with one sbd_mem_unit_t.
+	 */
+	dev_info_t		*sbm_dip[SBD_NUM_MC_PER_BOARD];
+	/*
+	 * The following field determines if the memory on this board
+	 * is part of an interleave across boards
+	 */
+	int			sbm_interleave;
+} sbd_mem_unit_t;
+
+/*
+ * Currently only maintain state information for individual
+ * components.
+ */
+typedef struct sbd_cpu_unit {
+	sbd_common_unit_t	sbc_cm;		/* cpu-unit state */
+	processorid_t		sbc_cpu_id;
+	cpu_flag_t		sbc_cpu_flags;
+	ushort_t		sbc_pad1;
+	int			sbc_cpu_impl;
+	int			sbc_speed;
+	int			sbc_ecache;
+} sbd_cpu_unit_t;
+
+typedef struct sbd_io_unit {
+	sbd_common_unit_t	sbi_cm;		/* io-unit state */
+} sbd_io_unit_t;
+
+typedef union {
+	sbd_common_unit_t	u_common;
+	sbd_mem_unit_t		_mu;
+	sbd_cpu_unit_t		_cu;
+	sbd_io_unit_t		_iu;
+} sbd_dev_unit_t;
+
+typedef struct {
+	sbd_priv_handle_t	*sb_handle;
+	int			sb_ref;		/* # of handle references */
+	int			sb_num;		/* board number */
+	void			*sb_softsp;	/* pointer to soft state */
+	dev_info_t		*sb_topdip;	/* top devinfo of instance */
+	sbd_istate_t		sb_state;	/* (current) board state */
+	sbd_istate_t		sb_pstate;	/* previous board state */
+	sbd_cond_t		sb_cond;	/* condition		*/
+	sbd_state_t		sb_rstate;	/* receptacle state	*/
+	sbd_state_t		sb_ostate;	/* occupant state	*/
+		/*
+		 * 0=CPU, 1=MEM, 2=IO, 3=NULL
+		 */
+	dev_info_t		**sb_devlist[SBD_MAXNUM_NT + 1];
+
+	sbd_devset_t	sb_dev_present;		/* present mask */
+	sbd_devset_t	sb_dev_attached;	/* attached mask */
+	sbd_devset_t	sb_dev_released;	/* released mask */
+	sbd_devset_t	sb_dev_unreferenced;	/* unreferenced mask */
+	sbd_dev_unit_t	*sb_dev[SBD_MAXNUM_NT];
+
+	char		*sb_cpupath[SBD_MAX_UNITS_PER_BOARD];
+	char		*sb_mempath[SBD_MAX_UNITS_PER_BOARD];
+	char		*sb_iopath[SBD_MAX_UNITS_PER_BOARD];
+
+	int		sb_ndev;		/* number of devs */
+	int		sb_errno;		/* store errno */
+	int		sb_busy;		/* drain in progress */
+	int		sb_assigned;
+	int		sb_flags;
+	kmutex_t	sb_flags_mutex;		/* mutex to protect flags */
+	int		sb_wnode;
+	int		sb_memaccess_ok;
+	sbd_stat_t	sb_stat;		/* cached board status */
+	processorid_t	sb_cpuid;		/* for starfire connect */
+	time_t		sb_time;		/* time of last board op */
+	kmutex_t	sb_mutex;
+	kmutex_t	sb_slock;		/* status - unconfig, discon */
+} sbd_board_t;
+
+/* definitions for sb_flags */
+#define	SBD_BOARD_STATUS_CACHED	1
+
+#define	SBD_GET_BOARD_MEMUNIT(sb, un) \
+			(&((sb)->sb_dev[NIX(SBD_COMP_MEM)][un]._mu))
+#define	SBD_GET_BOARD_CPUUNIT(sb, un) \
+			(&((sb)->sb_dev[NIX(SBD_COMP_CPU)][un]._cu))
+#define	SBD_GET_BOARD_IOUNIT(sb, un) \
+			(&((sb)->sb_dev[NIX(SBD_COMP_IO)][un]._iu))
+
+typedef ushort_t	boardset_t;	/* assumes 16 boards max */
+
+#define	BOARDSET(b)		((boardset_t)(1 << (b)))
+#define	BOARD_IN_SET(bs, b)	(((bs) & BOARDSET(b)) != 0)
+#define	BOARD_ADD(bs, b)	((bs) |= BOARDSET(b))
+#define	BOARD_DEL(bs, b)	((bs) &= ~BOARDSET(b))
+
+/*
+ * Format of sbd_devset_t bit masks:
+ *
+ *	32		   16        8    4    0
+ *	|....|....|...I|IIII|....|...M|CCCC|CCCC|
+ * 1 = indicates respective component present/attached.
+ * I = I/O, M = Memory, C = CPU.
+ */
+#define	DEVSET_ANYUNIT		(-1)
+#define	_NT2DEVPOS(t, u)	((NIX(t) << 3) + (u))
+#define	_DEVSET_MASK		0x001f01ff
+#define	_CMP_DEVSET_MASK	0x11
+#define	DEVSET(t, u) \
+	(((u) == DEVSET_ANYUNIT) ? \
+	    (sbd_devset_t)((0xff << _NT2DEVPOS((t), 0)) & _DEVSET_MASK) : \
+	(((t) == SBD_COMP_CMP) ? \
+	    (sbd_devset_t)(_CMP_DEVSET_MASK << _NT2DEVPOS((t), (u))) : \
+	(sbd_devset_t)(1 << _NT2DEVPOS((t), (u)))))
+
+#define	DEVSET_IN_SET(ds, t, u)	(((ds) & DEVSET((t), (u))) != 0)
+#define	DEVSET_ADD(ds, t, u)	((ds) |= DEVSET((t), (u)))
+#define	DEVSET_DEL(ds, t, u)	((ds) &= ~DEVSET((t), (u)))
+#define	DEVSET_GET_UNITSET(ds, t) \
+	(((ds) & DEVSET((t), DEVSET_ANYUNIT)) >> _NT2DEVPOS((t), 0))
+/*
+ * Ops for sbd_board_t.sb_dev_present
+ */
+#define	SBD_DEV_IS_PRESENT(bp, nt, un) \
+			DEVSET_IN_SET((bp)->sb_dev_present, (nt), (un))
+#define	SBD_DEV_SET_PRESENT(bp, nt, un) \
+			DEVSET_ADD((bp)->sb_dev_present, (nt), (un))
+#define	SBD_DEV_CLR_PRESENT(bp, nt, un) \
+			DEVSET_DEL((bp)->sb_dev_present, (nt), (un))
+/*
+ * Ops for sbd_board_t.sb_dev_attached
+ */
+#define	SBD_DEV_IS_ATTACHED(bp, nt, un) \
+			DEVSET_IN_SET((bp)->sb_dev_attached, (nt), (un))
+#define	SBD_DEV_SET_ATTACHED(bp, nt, un) \
+			DEVSET_ADD((bp)->sb_dev_attached, (nt), (un))
+#define	SBD_DEV_CLR_ATTACHED(bp, nt, un) \
+			DEVSET_DEL((bp)->sb_dev_attached, (nt), (un))
+/*
+ * Ops for sbd_board_t.sb_dev_released
+ */
+#define	SBD_DEV_IS_RELEASED(bp, nt, un) \
+			DEVSET_IN_SET((bp)->sb_dev_released, (nt), (un))
+#define	SBD_DEV_SET_RELEASED(bp, nt, un) \
+			DEVSET_ADD((bp)->sb_dev_released, (nt), (un))
+#define	SBD_DEV_CLR_RELEASED(bp, nt, un) \
+			DEVSET_DEL((bp)->sb_dev_released, (nt), (un))
+/*
+ * Ops for sbd_board_t.sb_dev_unreferenced
+ */
+#define	SBD_DEV_IS_UNREFERENCED(bp, nt, un) \
+			DEVSET_IN_SET((bp)->sb_dev_unreferenced, (nt), (un))
+#define	SBD_DEV_SET_UNREFERENCED(bp, nt, un) \
+			DEVSET_ADD((bp)->sb_dev_unreferenced, (nt), (un))
+#define	SBD_DEV_CLR_UNREFERENCED(bp, nt, un) \
+			DEVSET_DEL((bp)->sb_dev_unreferenced, (nt), (un))
+
+#define	SBD_DEVS_PRESENT(bp) \
+			((bp)->sb_dev_present)
+#define	SBD_DEVS_ATTACHED(bp) \
+			((bp)->sb_dev_attached)
+#define	SBD_DEVS_RELEASED(bp) \
+			((bp)->sb_dev_released)
+#define	SBD_DEVS_UNREFERENCED(bp) \
+			((bp)->sb_dev_unreferenced)
+#define	SBD_DEVS_UNATTACHED(bp) \
+			((bp)->sb_dev_present & ~(bp)->sb_dev_attached)
+#define	SBD_DEVS_CONFIGURE(bp, devs) \
+			((bp)->sb_dev_attached = (devs))
+#define	SBD_DEVS_DISCONNECT(bp, devs) \
+			((bp)->sb_dev_present &= ~(devs))
+#define	SBD_DEVS_CANCEL(bp, devs) \
+			((bp)->sb_dev_released &= ~(devs), \
+			(bp)->sb_dev_unreferenced &= ~(devs))
+
+/*
+ * return values from sbd_cancel_cpu
+ */
+#define	SBD_CPUERR_NONE		0
+#define	SBD_CPUERR_RECOVERABLE	-1
+#define	SBD_CPUERR_FATAL	-2
+
+/*
+ * sbd_board_t.sbmem[].sbm_flags
+ */
+#define	SBD_MFLAG_RESERVED	0x01	/* mem unit reserved for delete */
+#define	SBD_MFLAG_SOURCE	0x02	/* source brd of copy/rename op */
+#define	SBD_MFLAG_TARGET	0x04	/* board selected as target */
+#define	SBD_MFLAG_MEMUPSIZE	0x08	/* move from big to small board */
+#define	SBD_MFLAG_MEMDOWNSIZE	0x10	/* move from small to big board */
+#define	SBD_MFLAG_MEMRESIZE	0x18	/* move to different size board */
+#define	SBD_MFLAG_RELOWNER	0x20	/* memory release (delete) owner */
+#define	SBD_MFLAG_RELDONE	0x40
+
+typedef struct {
+	int	sfio_cmd;
+	void	*sfio_arg;
+} sbd_ioctl_t;
+
+/*
+ * 32bit support for sbd_ioctl_t.
+ */
+typedef struct {
+	int32_t		sfio_cmd;
+	uint32_t	sfio_arg;
+} sbd_ioctl32_t;
+
+/*
+ * PSM-DR layers are only allowed to use lower 16 bits of dev_t.
+ * B    - bottom 4 bits are for the slot number.
+ * D    - device type chosen (0 = indicates all devices in slot).
+ * U	- unit number if specific device type chosen.
+ * X    - not used.
+ *
+ * Upper      Lower
+ * XXXXUUUUDDDDBBBB
+ *
+ * Note that this format only allows attachment points to
+ * either represent all the units on a board or one particular
+ * unit.  A more general specification would permit any combination
+ * of specific units and types to be represented by individual
+ * attachment points.
+ */
+#define	SBD_DEV_SLOTMASK	0x000f
+/*
+ * These device level definitions are primarily for unit testing.
+ */
+#define	SBD_DEV_UNITMASK	0x0f00
+#define	SBD_DEV_UNITSHIFT	8
+#define	SBD_DEV_CPU		0x0010
+#define	SBD_DEV_MEM		0x0020
+#define	SBD_DEV_IO		0x0040
+#define	SBD_DEV_TYPEMASK	(SBD_DEV_CPU | SBD_DEV_MEM | SBD_DEV_IO)
+#define	SBD_DEV_TYPESHIFT	4
+
+/*
+ * Slot, Instance, and Minor number Macro definitions
+ */
+#define	SLOT2DEV(s)		((s) & SBD_DEV_SLOTMASK)
+#define	SBDGETSLOT(unit)	((unit) & SBD_DEV_SLOTMASK)
+/*
+ * The following is primarily for unit testing.
+ */
+#define	ALLCPU2DEV(s)		(SBD_DEV_CPU | SLOT2DEV(s))
+#define	ALLMEM2DEV(s)		(SBD_DEV_MEM | SLOT2DEV(s))
+#define	ALLIO2DEV(s)		(SBD_DEV_IO | SLOT2DEV(s))
+#define	_UNIT2DEV(u)		(((u) << SBD_DEV_UNITSHIFT) & \
+					SBD_DEV_UNITMASK)
+#define	CPUUNIT2DEV(s, c)	(_UNIT2DEV(c) | ALLCPU2DEV(s))
+#define	MEMUNIT2DEV(s, m)	(_UNIT2DEV(m) | ALLMEM2DEV(s))
+#define	IOUNIT2DEV(s, i)	(_UNIT2DEV(i) | ALLIO2DEV(s))
+
+#define	DEV_IS_ALLUNIT(d)	(((d) & SBD_DEV_UNITMASK) == 0)
+#define	_DEV_IS_ALLTYPE(d)	(((d) & SBD_DEV_TYPEMASK) == 0)
+#define	DEV_IS_ALLBOARD(d)	(DEV_IS_ALLUNIT(d) && _DEV_IS_ALLTYPE(d))
+#define	DEV_IS_CPU(d)		((d) & SBD_DEV_CPU)
+#define	DEV_IS_MEM(d)		((d) & SBD_DEV_MEM)
+#define	DEV_IS_IO(d)		((d) & SBD_DEV_IO)
+#define	DEV_IS_ALLCPU(d)	(DEV_IS_ALLUNIT(d) && DEV_IS_CPU(d))
+#define	DEV_IS_ALLMEM(d)	(DEV_IS_ALLUNIT(d) && DEV_IS_MEM(d))
+#define	DEV_IS_ALLIO(d)		(DEV_IS_ALLUNIT(d) && DEV_IS_IO(d))
+#define	DEV2UNIT(d) \
+		((((d) & SBD_DEV_UNITMASK) >> SBD_DEV_UNITSHIFT) - 1)
+#define	DEV2NT(d) \
+		(DEV_IS_MEM(d) ? SBD_COMP_MEM : \
+		DEV_IS_CPU(d) ? SBD_COMP_CPU : \
+		DEV_IS_IO(d) ? SBD_COMP_IO : SBD_COMP_UNKNOWN)
+
+/*
+ * Macros to cast between PIM and PSM layers of the following
+ * structures:
+ *	board_t		<-> sbd_board_t
+ *	sbd_handle_t	<-> sbd_priv_handle_t
+ *	sbderror_t	<-> sbderror_t
+ *	slot		-> board_t
+ *	slot		-> sbd_board_t
+ *	sbd_board_t	-> sbd_handle_t
+ *	sbd_handle	-> sbderror_t
+ */
+#define	SBDH2BD(bd)		((sbd_board_t *)(bd))
+
+#define	HD2MACHHD(hd)		((sbd_priv_handle_t *)(hd))
+#define	MACHHD2HD(mhd)		((sbd_handle_t *)&((mhd)->sh_handle))
+
+#define	ERR2MACHERR(err)	((sbderror_t *)(err))
+#define	MACHERR2ERR(merr)	((sbderror_t *)(merr))
+
+#define	BSLOT2MACHBD(b)		(&(sbd_boardlist[b]))
+#define	BSLOT2BD(slot)		MACHBD2BD(BSLOT2MACHBD(slot))
+
+#define	MACHBD2HD(sbp)		MACHHD2HD((sbp)->sb_handle)
+
+#define	HD2MACHERR(hd)		ERR2MACHERR(SBD_HD2ERR(hd))
+
+#define	MACHSRHD2HD(srh)	((srh)->sr_dr_handlep)
+
+/*
+ * CMP Specific Helpers
+ */
+#define	MAX_CORES_PER_CMP		2
+#define	SBD_CMP_CORE_UNUM(cmp, core)	((cmp + (core * 512))
+#define	SBD_CMP_NUM(unum)		(unum & 0x3)
+
+/*
+ * Some stuff to assist in debug.
+ */
+#ifdef DEBUG
+#define	SBD_DBG_STATE	0x00000001
+#define	SBD_DBG_QR	0x00000002
+#define	SBD_DBG_CPU	0x00000004
+#define	SBD_DBG_MEM	0x00000008
+#define	SBD_DBG_IO	0x00000010
+#define	SBD_DBG_HW	0x00000020
+#define	SBD_DBG_BYP	0x00000040
+
+#define	PR_ALL		if (sbd_debug)			printf
+#define	PR_STATE	if (sbd_debug & SBD_DBG_STATE)	printf
+#define	PR_QR		if (sbd_debug & SBD_DBG_QR)	prom_printf
+#define	PR_CPU		if (sbd_debug & SBD_DBG_CPU)	printf
+#define	PR_MEM		if (sbd_debug & SBD_DBG_MEM)	printf
+#define	PR_IO		if (sbd_debug & SBD_DBG_IO)	printf
+#define	PR_HW		if (sbd_debug & SBD_DBG_HW)	printf
+#define	PR_BYP		if (sbd_debug & SBD_DBG_BYP)	prom_printf
+
+#define	SBD_MEMLIST_DUMP(ml)	memlist_dump(ml)
+
+extern uint_t	sbd_debug;
+#else /* DEBUG */
+#define	PR_ALL		if (0) printf
+#define	PR_STATE	PR_ALL
+#define	PR_QR		PR_ALL
+#define	PR_CPU		PR_ALL
+#define	PR_MEM		PR_ALL
+#define	PR_IO		PR_ALL
+#define	PR_HW		PR_ALL
+#define	PR_BYP		PR_ALL
+
+#define	SBD_MEMLIST_DUMP(ml)
+#endif /* DEBUG */
+extern char	*sbd_state_str[];
+extern char	*sbd_ct_str[];
+
+/*
+ * event flag
+ */
+extern char send_event;
+
+/*
+ * IMPORTANT:
+ * The following two defines are also coded into OBP, so if they
+ * need to change here, don't forget to change OBP also.
+ */
+#define	SBD_OBP_PROBE_GOOD	0
+#define	SBD_OBP_PROBE_BAD	1
+
+extern int		sbd_setup_instance(int, dev_info_t *, int, int,
+				caddr_t);
+extern int		sbd_teardown_instance(int, caddr_t);
+extern int		sbd_ioctl(dev_t dev, int cmd, intptr_t arg, int mode,
+				char *event);
+
+extern sbd_comp_type_t	sbd_cm_type(char *name);
+extern sbd_state_t	ostate_cvt(sbd_istate_t state);
+extern void		sbd_cpu_set_prop(sbd_cpu_unit_t *cp, dev_info_t *dip);
+extern int		sbd_cpu_flags(sbd_handle_t *hp, sbd_devset_t devset,
+				sbd_dev_stat_t *dsp);
+extern int		sbd_disconnect_cpu(sbd_handle_t *hp, int unit);
+extern int		sbd_connect_cpu(sbd_board_t *sbp, int unit);
+extern int		sbd_disconnect_mem(sbd_handle_t *hp, int unit);
+
+extern int		sbd_pre_detach_mem(sbd_handle_t *hp,
+				sbd_devlist_t *devlist, int devnum);
+extern int		sbd_post_attach_mem(sbd_handle_t *,
+				sbd_devlist_t *, int);
+extern int		sbd_post_detach_mem(sbd_handle_t *,
+				sbd_devlist_t *, int);
+extern int		sbd_post_attach_cpu(sbd_handle_t *hp,
+					sbd_devlist_t *devlist, int devnum);
+extern int		sbd_pre_release_cpu(sbd_handle_t *hp,
+					sbd_devlist_t *devlist, int devnum);
+extern int		sbd_pre_detach_cpu(sbd_handle_t *hp,
+					sbd_devlist_t *devlist, int devnum);
+extern int		sbd_post_detach_cpu(sbd_handle_t *hp,
+					sbd_devlist_t *devlist, int devnum);
+extern int		sbd_pre_attach_mem(sbd_handle_t *hp,
+					sbd_devlist_t *devlist, int devnum);
+extern int		sbd_pre_release_mem(sbd_handle_t *hp,
+					sbd_devlist_t *devlist, int devnum);
+extern int		sbd_disconnect_io(sbd_handle_t *hp, int unit);
+extern void		sbd_check_devices(dev_info_t *dip, int *refcount,
+					sbd_handle_t *handle);
+extern struct memlist	*sbd_get_memlist(sbd_mem_unit_t *mp, sbderror_t *ep);
+extern void		sbd_init_mem_unit(sbd_board_t *sbp, int unit,
+					sbderror_t *ep);
+extern void		sbd_release_mem_done(sbd_handle_t *hp, int unit);
+extern void		sbd_release_cleanup(sbd_handle_t *hp);
+extern int		sbd_cancel_cpu(sbd_handle_t *hp, int unit);
+extern void		sbd_init_err(sbderror_t *ep);
+extern int		sbd_cancel_mem(sbd_handle_t *hp, int unit);
+extern sbd_comp_type_t	sbd_get_devtype(sbd_handle_t *hp, dev_info_t *dip);
+extern int		sbd_get_board(dev_info_t *dip);
+extern int		sfhw_get_base_physaddr(dev_info_t *dip,
+					uint64_t *basepa);
+extern int		sbd_pre_attach_cpu(sbd_handle_t *hp,
+					sbd_devlist_t *devlist, int devnum);
+extern int		sbd_move_memory(sbd_handle_t *hp, sbd_board_t
+				*s_bp, sbd_board_t *t_bp);
+extern void		memlist_delete(struct memlist *mlist);
+extern struct memlist	*memlist_dup(struct memlist *mlist);
+extern void		memlist_dump(struct memlist *mlist);
+extern int		memlist_intersect(struct memlist *alist,
+					struct memlist *blist);
+extern int		sbd_juggle_bootproc(sbd_handle_t *hp,
+					processorid_t cpuid);
+
+extern sbd_cond_t	sbd_get_comp_cond(dev_info_t *);
+void			sbd_attach_mem(sbd_handle_t *hp, sbderror_t *ep);
+int			sbd_release_mem(sbd_handle_t *hp, dev_info_t *dip,
+					int unit);
+
+int			sbd_get_memhandle(sbd_handle_t *hp, dev_info_t *dip,
+					memhandle_t *mhp);
+int			sbd_detach_memory(sbd_handle_t *hp, sbderror_t *ep,
+					sbd_mem_unit_t *s_mp, int unit);
+void			sbd_release_memory_done(void *arg, int error);
+int			sbd_set_err_in_hdl(sbd_handle_t *hp, sbderror_t *ep);
+sbdp_handle_t		*sbd_get_sbdp_handle(sbd_board_t *sbp,
+					sbd_handle_t *hp);
+void			sbd_release_sbdp_handle(sbdp_handle_t *hp);
+void			sbd_reset_error_sbdph(sbdp_handle_t *hp);
+extern int		sbd_is_cmp_child(dev_info_t *dip);
+
+typedef const char *const fn_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _SYS_SBDPRIV_H */
diff --git a/usr/src/uts/sun4u/sys/smc_commands.h b/usr/src/uts/sun4u/sys/smc_commands.h
new file mode 100644
index 0000000000..1b6aea9cf9
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/smc_commands.h
@@ -0,0 +1,265 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_SMC_COMMANDS_H
+#define	_SYS_SMC_COMMANDS_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* Address of BMC on IPMB */
+#define	BMC_IPMB_ADDR	0x20
+#define	SMC_CPCI_SLOT0_ADDR	0xB0
+#define	SMC_CPCI_SLOT_ADDR(X)	(SMC_CPCI_SLOT0_ADDR + \
+		2 * ((X) - 1))
+
+typedef struct ctsmc_code_ent {
+	uint8_t code;
+	char	*name;
+} ctsmc_code_ent_t;
+
+/*
+ * Definition of Network Function Codes
+ */
+typedef enum {
+	SMC_NETFN_CHASSIS_REQ = 0x0,
+	SMC_NETFN_CHASSIS_RSP = 0x1,
+	SMC_NETFN_BRIDGE_REQ = 0x2,
+	SMC_NETFN_BRIDGE_RSP = 0x3,
+	SMC_NETFN_SENSOR_REQ = 0x4,
+	SMC_NETFN_SENSOR_RSP = 0x5,
+	SMC_NETFN_APP_REQ = 0x6,
+	SMC_NETFN_APP_RSP = 0x7,
+	SMC_NETFN_FIRMWARE_REQ = 0x8,
+	SMC_NETFN_FIRMWARE_RSP = 0x9,
+	SMC_NETFN_STORAGE_REQ = 0xA,
+	SMC_NETFN_STORAGE_RSP = 0xB
+} smc_netfn_t;
+
+/*
+ * Definition of Completion codes
+ */
+typedef enum {
+	SMC_CC_SUCCESS	 = 0x00,
+	SMC_CC_NODE_BUSY = 0xC0,
+	SMC_CC_INVALID_COMMAND = 0xC1,
+	SMC_CC_INVALID_COMMAND_ON_LUN = 0xC2,
+	SMC_CC_TIMEOUT = 0xC3,
+	SMC_CC_RESOURCE_NOTAVAIL = 0xC4,
+	SMC_CC_RESERVATION = 0xC5,
+	SMC_CC_REQ_TRUNC = 0xC6,
+	SMC_CC_REQLEN_NOTVALID = 0xC7,
+	SMC_CC_REQLEN_EXCEED = 0xC8,
+	SMC_CC_PARAM_OUT_OF_RANGE = 0xC9,
+	SMC_CC_REQUEST_BYTES_FAILED = 0xCA,
+	SMC_CC_NOT_PRESENT = 0xCB,
+	SMC_CC_INVALID_FIELD = 0xCC,
+	SMC_CC_ILLEGAL_COMMAND = 0xCD,
+	SMC_CC_RESPONSE_FAILED = 0xCE,
+	SMC_CC_DUPLICATE_REQUEST = 0xCF,
+	SMC_CC_SDR_UPDATE_MODE = 0xD0,
+	SMC_CC_FIRMWARE_UPDATE_MODE = 0xD1,
+	SMC_CC_INIT_IN_PROGRESS = 0xD2,
+	SMC_CC_UNSPECIFIED_ERROR = 0xFF
+} smc_cc_t;
+
+typedef enum {
+	SMC_BMC_LUN,
+	SMC_OEM1_LUN,
+	SMC_SMS_LUN,
+	SMC_OEM2_LUN
+} smc_lun_t;
+
+/*
+ * App command codes for commands/event notifications etc.
+ */
+typedef enum {
+	SMC_GET_DEVICE_ID = 0x01,
+	SMC_COLD_RESET = 0x02,
+	SMC_WARM_RESET = 0x03,
+	SMC_GET_SELFTEST_RESULTS = 0x04,
+	SMC_MANUFACTURING_TEST_ON = 0x05,
+	SMC_SET_ACPI_POWER_STATE = 0x06,
+	SMC_GET_ACPI_POWER_STATE = 0x07,
+	SMC_GET_DEVICE_GUID = 0x08,
+	SMC_RESET_WATCHDOG_TIMER = 0x22,
+	SMC_EXPIRED_WATCHDOG_NOTIF = 0x23,	/* Sent by driver */
+	SMC_SET_WATCHDOG_TIMER = 0x24,
+	SMC_GET_WATCHDOG_TIMER = 0x25,
+	SMC_SET_GLOBAL_ENABLES = 0x2E,
+	SMC_GET_GLOBAL_ENABLES = 0x2F,
+	SMC_CLEAR_MESSAGE_FLAGS = 0x30,
+	SMC_GET_MESSAGE_FLAGS = 0x31,
+	SMC_ENABLE_MESSAGE_CHANNEL_RECEIVE = 0x32,
+	SMC_GET_MESSAGE = 0x33,
+	SMC_SEND_MESSAGE = 0x34,
+	SMC_READ_EVENT_MSG_BUFFER = 0x35,
+	SMC_SEND_TO_EVENT_MSG_BUFFER = 0x36,	/* Changed from IPMI */
+	SMC_MASTER_WR_RD_I2C = 0x52,
+	SMC_GET_GEOGRAPHICAL_ADDRESS = 0x55,
+	SMC_GET_BACKPLANE_TYPE = 0x57,
+	SMC_SELECT_MEMORY_DEVICE = 0x60,
+	SMC_READ_SELECTED_MEMORY_DEVICE = 0x61,
+	SMC_READ_MEMORY_DEVICE = 0x62,
+	SMC_WRITE_SELECTED_MEMORY_DEVICE = 0x63,
+	SMC_WRITE_MEMORY_DEVICE = 0x64,
+	SMC_ERASE_SELECTED_MEMORY_DEVICE = 0x65,
+	SMC_LOCK_UNLOCK_SELECTED_MEMORY = 0x66,
+	SMC_COMPUTE_CRC16_OF_SELECTED_MEMORY_DEVICE = 0x67,
+	SMC_COMPUTE_CRC16_OF_MEMORY_DEVICE = 0x68,
+	SMC_FILL_MEMORY_DEVICE = 0x6a,
+	SMC_QUERY_FIRMWARE_VERSION = 0x6f,
+	SMC_RESET_DEVICE = 0x70,
+	SMC_GET_ROLE_INFO = 0x71,
+	SMC_GET_FLASH_AND_BOOT_VERSION = 0x72,
+	SMC_GET_LOCAL_HA_SIGNAL_STATUS = 0x73,
+	SMC_SELECT_HA_HOTSWAP_MODE = 0x80,
+	SMC_GET_HA_HOTSWAP_SIGNAL_STATE = 0x81,
+	SMC_SET_HA_HOTSWAP_SIGNAL_STATE = 0x82,
+	SMC_NOTIFY_SMC_OF_HOST_HEALTH = 0x83,
+	SMC_TURN_ON_OFF_BLUE_LED = 0x84,
+	SMC_GET_EXECUTION_STATE = 0x85,
+	SMC_GET_SMC_UPTIME = 0x86,
+	SMC_ENUM_NOTIF = 0x87,
+	SMC_IPMI_RESPONSE_NOTIF = 0x88,
+	SMC_SET_INTERFACE_TIMEOUT = 0x89,
+	SMC_GET_INTERFACE_TIMEOUT = 0x8A,
+	SMC_SMC_LOCAL_EVENT_NOTIF = 0x8B,
+	SMC_GET_DEVICE_TABLE_DATA = 0x8C,
+	SMC_IPMI_MASTER_WR_RD_I2C = 0x90,
+	SMC_GET_SMC_SELF_TEST_RESULT = 0xA0,
+	SMC_READ_SMC_PLD_REGISTER = 0xA1,
+	SMC_WRITE_SMC_PLD_REGISTER = 0xA2,
+	SMC_SET_ROLE = 0xC0,
+	SMC_SET_CPCI_INTMASK = 0xC1,
+	SMC_GET_CPCI_INTMASK = 0xC2,
+	SMC_EEPROM_WRITE = 0xC3,
+	SMC_EEPROM_READ = 0xC4,
+	SMC_SET_STATE = 0xDE,
+	SMC_GET_STATE = 0xDF,
+	SMC_SET_DHCP_CLIENT_ID = 0xE1,
+	SMC_GET_DHCP_CLIENT_ID = 0xE2,
+	SMC_DEV_SDR_REPOSITORY_RESERVE = 0xE3,
+	SMC_FRU_INVENTORY_AREA_INFO_GET = 0xE4,
+	SMC_SET_BANNER = 0xE5,
+	SMC_GET_BANNER = 0xE6,
+	SMC_SEND_ASYNC_SEL_CMD_TO_HOST = 0xE7,
+	SMC_MASTER_WR_RD_I2C_2 = 0xE9,
+	SMC_GET_BUFFER_BLOCK_ALLOC_TABLE = 0xEA,
+	SMC_GET_BUFFER_ALLOC_TABLE = 0xEB,
+	SMC_GET_SFRS = 0xEC,
+	SMC_GET_PORT_VALUE = 0xED,
+	SMC_GET_BUFFER_DATA = 0xEE,
+	SMC_GET_PCB_DATA = 0xEF,
+	SMC_GET_PCB_BLOCK_ALLOC_TABLE = 0xF0,
+	SMC_GET_PCB_TABLE = 0xF1,
+	SMC_DEVICE_SDR_INFO_GET = 0xF2,
+	SMC_DEVICE_SDR_GET = 0xF3,
+	SMC_SENSOR_EVENT_ENABLE_GET = 0xF4,
+	SMC_SENSOR_EVENT_ENABLE_SET = 0xF5,
+	SMC_GET_CONFIG_BLOCK = 0xF8,
+	SMC_SET_CONFIG_BLOCK = 0xF9,
+	SMC_SET_VOLTAGE = 0xFB,
+	SMC_SENSOR_READING_GET = 0xFC,
+	SMC_SENSOR_THRESHOLD_GET = 0xFD,
+	SMC_SENSOR_THRESHOLD_SET = 0xFE,
+	SMC_CND_OF_CMD_MARKER = 0xFF
+} smc_app_command_t;
+
+typedef enum {
+	SMC_GET_CHASSIS_STATUS = 0x01,
+	SMC_CHASSIS_CONTROL = 0x02,
+	SMC_GET_POH_COUNTER = 0x0F
+} smc_chassis_command_t;
+
+typedef enum {
+	SMC_SET_EVENT_RECEIVER = 0x00,
+	SMC_GET_EVENT_RECEIVER = 0x01,
+	SMC_PLATFORM_EVENT_MESSAGE = 0x02
+} smc_event_command_t;
+
+typedef enum {
+	SMC_GET_SEL_INFO = 0x40,
+	SMC_GET_SEL_ALLOCATION_INFO = 0x41,
+	SMC_RESERVE_SEL = 0x42,
+	SMC_GET_SEL_ENTRY = 0x43,
+	SMC_ADD_SEL_ENTRY = 0x44,
+	SMC_PARTIAL_ADD_SEL_ENTRY = 0x45,
+	SMC_DELETE_SEL_ENTRY = 0x46,
+	SMC_CLEAR_SEL = 0x47,
+	SMC_GET_SEL_TIME = 0x48,
+	SMC_SET_SEL_TIME = 0x49
+} smc_sel_command_t;
+
+typedef enum {
+	SMC_GET_SDR_REPOSITORY_INFO = 0x20,
+	SMC_GET_SDR_REPOSITORY_ALLOCATION_INFO = 0x21,
+	SMC_RESERVE_SDR_REPOSITORY = 0x22,
+	SMC_GET_SDR = 0x23,
+	SMC_ADD_SDR = 0x24,
+	SMC_PARTIAL_ADD_SDR = 0x25,
+	SMC_DELETE_SDR = 0x26,
+	SMC_CLEAR_SDR_REPOSITORY = 0x27,
+	SMC_GET_SDR_REPOSITORY_TIME = 0x28,
+	SMC_SET_SDR_REPOSITORY_TIME = 0x29,
+	SMC_ENTER_SDR_REPOSITORY_UPDATE_MODE = 0x2A,
+	SMC_EXIT_SDR_REPOSITORY_UPDATE_MODE = 0x2B,
+	SMC_RUN_INITIALIZATION_AGENT = 0x2C
+} smc_sdr_repository_command_t;
+
+typedef enum {
+	SMC_GET_FRU_INVENTORY_AREA_INFO = 0x10,
+	SMC_READ_FRU_INVENTORY_DATA = 0x11,
+	SMC_WRITE_FRU_INVENTORY_DATA = 0x12
+} smc_fru_inventory_device_command_t;
+
+typedef enum {
+	SMC_GET_DEVICE_SDR_INFO = 0x20,
+	SMC_GET_DEVICE_SDR = 0x21,
+	SMC_RESERVE_DEVICE_SDR_REPOSITORY = 0x22,
+	SMC_GET_SENSOR_READING_FACTORS = 0x23,
+	SMC_SET_SENSOR_HYSTERESIS = 0x24,
+	SMC_GET_SENSOR_HYSTERESIS = 0x25,
+	SMC_SET_SENSOR_THRESHOLD = 0x26,
+	SMC_GET_SENSOR_THRESHOLD = 0x27,
+	SMC_SET_SENSOR_EVENT_ENABLE = 0x28,
+	SMC_GET_SENSOR_EVENT_ENABLE = 0x29,
+	SMC_REARM_SENSOR_EVENTS = 0x2A,
+	SMC_GET_SENSOR_EVENT_STATUS = 0x2B,
+	/* RESERVED */
+	SMC_GET_SENSOR_READING = 0x2D,
+	SMC_SET_SENSOR_TYPE = 0x2E,
+	SMC_GET_SENSOR_TYPE = 0x2F
+} smc_sensor_device_command_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_SMC_COMMANDS_H */
diff --git a/usr/src/uts/sun4u/sys/smc_if.h b/usr/src/uts/sun4u/sys/smc_if.h
new file mode 100644
index 0000000000..8c35afe05a
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/smc_if.h
@@ -0,0 +1,151 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_SMC_IF_H
+#define	_SYS_SMC_IF_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	_SCIOC	('s' << 8)
+
+/*
+ * SMC Driver IOCTL
+ */
+#define	SCIOC_MSG_SPEC		(_SCIOC | 0x04)
+#define	SCIOC_RESERVE_SEQN	(_SCIOC | 0x05)
+#define	SCIOC_FREE_SEQN		(_SCIOC | 0x06)
+#define	SCIOC_SEND_SYNC_CMD	(_SCIOC | 0x07)
+
+/*
+ * IOCTLs to facilitate debugging
+ */
+#define	SCIOC_ECHO_ON_REQ	(_SCIOC | 0x08)
+#define	SCIOC_ECHO_OFF_REQ	(_SCIOC | 0x09)
+
+/*
+ * A response message can be sent from any application
+ * to simulate a condition of watchdog expiry or receiving
+ * async messages
+ */
+#define	SCIOC_ASYNC_SIM		(_SCIOC | 0x0A)
+
+#define	SC_SUCCESS	0
+#define	SC_FAILURE	1
+
+/*
+ * structure definitions
+ */
+typedef struct {
+	uint8_t	msg_id;
+	uint8_t	cmd;
+	uint8_t	len;
+} sc_reqhdr_t;
+
+typedef struct {
+	uint8_t	msg_id;
+	uint8_t	cmd;		/* Will be 0 is non-SMC response, e.g. wdog */
+	uint8_t	len;		/* Length of message, including header */
+	uint8_t	cc;			/* if non-SMC, contains MSG type */
+} sc_rsphdr_t;
+
+#define	SC_SEND_HEADER	(sizeof (sc_reqhdr_t))
+#define	SC_RECV_HEADER	(sizeof (sc_rsphdr_t))
+
+#define	SC_MSG_MAX_SIZE	0x3E
+#define	SC_SEND_DSIZE	(SC_MSG_MAX_SIZE - SC_SEND_HEADER)
+#define	SC_RECV_DSIZE	(SC_MSG_MAX_SIZE - SC_RECV_HEADER)
+
+#define	SMC_CMD_FAILED	-1
+
+typedef enum {
+	SC_ATTR_SHARED,
+	SC_ATTR_EXCLUSIVE,
+	SC_ATTR_CLEAR,
+	SC_ATTR_CLEARALL
+} sc_cmd_attr_t;
+
+#define	MAX_CMDS	16
+
+typedef struct {
+	uint8_t attribute;
+	uint8_t args[MAX_CMDS];
+} sc_cmdspec_t;
+
+#define	SC_CMDSPEC_ATTR(CMDSPEC)	((CMDSPEC).attribute)
+#define	SC_CMDSPEC_ARGS(CMDSPEC)	((CMDSPEC).args)
+
+/*
+ * Entire SMC Request Message sent down-stream
+ */
+typedef struct {
+	sc_reqhdr_t hdr;
+	uchar_t		data[SC_SEND_DSIZE];
+} sc_reqmsg_t;
+
+/*
+ * Entire SMC Response Message forwarded up-stream
+ */
+typedef struct {
+	sc_rsphdr_t 	hdr;
+	uchar_t			data[SC_RECV_DSIZE];
+} sc_rspmsg_t;
+
+#define	SC_MSG_HDR(msg)		((msg)->hdr)
+
+#define	SC_SEND_DLENGTH(msg)	(SC_MSG_HDR(msg).len)
+#define	SC_RECV_DLENGTH(msg)	(SC_MSG_HDR(msg).len)
+
+#define	SC_MSG_ID(msg)		(SC_MSG_HDR(msg).msg_id)
+#define	SC_MSG_CMD(msg)		(SC_MSG_HDR(msg).cmd)
+#define	SC_MSG_LEN(msg)		(SC_MSG_HDR(msg).len)
+#define	SC_MSG_CC(msg)		(SC_MSG_HDR(msg).cc)
+#define	SC_MSG_DATA(msg)	((msg)->data)
+
+/*
+ * IPMB sequence number request structure. Application can
+ * reserve a block of sequence numbers for communicating
+ * with each destination
+ */
+#define	SC_SEQ_SZ	16
+typedef struct {
+	uint8_t	d_addr;	/* Destination micro-controller addr */
+	int8_t	n_seqn;	/* Number of seq# requested, max 16, -1 => free all */
+	uint8_t	seq_numbers[SC_SEQ_SZ];	/* Placeholder for seq# */
+} sc_seqdesc_t;
+
+#define	SC_SEQN_DADDR(SEQDESC)		((SEQDESC).d_addr)
+#define	SC_SEQN_COUNT(SEQDESC)		((SEQDESC).n_seqn)
+#define	SC_SEQN_NUMBERS(SEQDESC)	((SEQDESC).seq_numbers)
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_SMC_IF_H */
diff --git a/usr/src/uts/sun4u/sys/spitregs.h b/usr/src/uts/sun4u/sys/spitregs.h
new file mode 100644
index 0000000000..492990c720
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/spitregs.h
@@ -0,0 +1,359 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_SPITREGS_H
+#define	_SYS_SPITREGS_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * This file is cpu dependent.
+ */
+
+#ifdef _STARFIRE
+/*
+ * Starfire's cpu upaids are not the same
+ * as cpuids.
+ * XXX - our obp took the liberty of
+ * converting cpu upaids into cpuids when
+ * presenting it as upa-portid property.
+ */
+#define	CPUID_TO_UPAID(upaid)	(((upaid & 0x3C) << 1) |	\
+				((upaid & 0x40) >> 4) |		\
+				(upaid &0x3))
+#else
+/*
+ * The mid is the same as the cpu id.
+ * We might want to change this later
+ */
+#define	CPUID_TO_UPAID(cpuid)	(cpuid)
+#endif	/* _STARFIRE */
+
+/*
+ * LSU Control Register
+ *
+ * +------+----+----+----+----+----+----+-----+------+----+----+----+---+
+ * | Resv | PM | VM | PR | PW | VR | VW | Rsv |  FM  | DM | IM | DC | IC|
+ * +------+----+----+----+----+----+----+-----+------+----+----+----+---+
+ *  63  41   33   25   24   23	 22   21   20  19   4	3    2	  1   0
+ *
+ */
+
+#define	LSU_IC		0x00000000001	/* icache enable */
+#define	LSU_DC		0x00000000002	/* dcache enable */
+#define	LSU_IM		0x00000000004	/* immu enable */
+#define	LSU_DM		0x00000000008	/* dmmu enable */
+#define	LSU_FM		0x000000FFFF0	/* parity mask */
+#define	LSU_VW		0x00000200000	/* virtual watchpoint write enable */
+#define	LSU_VR		0x00000400000	/* virtual watchpoint read enable */
+#define	LSU_PW		0x00000800000	/* physical watchpoint write enable */
+#define	LSU_PR		0x00001000000	/* physical watchpoint read enable */
+#define	LSU_VM		0x001fe000000	/* virtual watchpoint byte mask */
+#define	LSU_PM		0x1fe00000000	/* physical watch point byte mask */
+
+#define	LSU_VM_SHIFT	25
+#define	LSU_PM_SHIFT	33
+
+/*
+ * Defines for the different types of dcache_flush
+ * it is stored in dflush_type
+ */
+#define	FLUSHALL_TYPE	0x0		/* blasts all cache lines */
+#define	FLUSHMATCH_TYPE	0x1		/* flush entire cache but check each */
+					/* each line for a match */
+#define	FLUSHPAGE_TYPE	0x2		/* flush only one page and check */
+					/* each line for a match */
+
+/*
+ * D-Cache Tag Data Register
+ *
+ * +----------+--------+----------+
+ * | Reserved | DC_Tag | DC_Valid |
+ * +----------+--------+----------+
+ *  63	    30 29    2	1	 0
+ *
+ */
+#define	ICACHE_FLUSHSZ	0x20	/* one line in i$ */
+#define	DC_PTAG_SHIFT	34
+#define	DC_LINE_SHIFT	30
+#define	SF_DC_VBIT_SHIFT 2
+#define	SF_DC_VBIT_MASK	0x3
+#define	IC_LINE_SHIFT	3
+#define	IC_LINE		512
+#define	INDEX_BIT_SHIFT	13
+
+/*
+ * Definitions of sun4u cpu implementations as specified in version register
+ */
+#define	SPITFIRE_IMPL	0x10
+#define	IS_SPITFIRE(impl)	((impl) == SPITFIRE_IMPL)
+#define	SPITFIRE_MAJOR_VERSION(rev)	(((rev) >> 4) & 0xf)
+#define	SPITFIRE_MINOR_VERSION(rev)	((rev) & 0xf)
+
+#define	BLACKBIRD_IMPL	0x11
+#define	IS_BLACKBIRD(impl)	((impl) == BLACKBIRD_IMPL)
+#define	BLACKBIRD_MAJOR_VERSION(rev)	(((rev) >> 4) & 0xf)
+#define	BLACKBIRD_MINOR_VERSION(rev)	((rev) & 0xf)
+
+#define	SABRE_IMPL	0x12
+#define	HUMMBRD_IMPL	0x13
+
+/*
+ * Bits of Spitfire Asynchronous Fault Status Register
+ */
+#define	P_AFSR_STICKY	0x00000001FFF00000ULL /* mask for all sticky bits */
+#define	P_AFSR_ERRS	0x000000001EE00000ULL /* mask for remaining errors */
+#define	P_AFSR_ME	0x0000000100000000ULL /* errors > 1, same type!=CE */
+#define	P_AFSR_PRIV	0x0000000080000000ULL /* priv/supervisor access */
+#define	P_AFSR_ISAP	0x0000000040000000ULL /* incoming system addr. parity */
+#define	P_AFSR_ETP	0x0000000020000000ULL /* ecache tag parity */
+#define	P_AFSR_IVUE	0x0000000010000000ULL /* interrupt vector with UE */
+#define	P_AFSR_TO	0x0000000008000000ULL /* bus timeout */
+#define	P_AFSR_BERR	0x0000000004000000ULL /* bus error */
+#define	P_AFSR_LDP	0x0000000002000000ULL /* data parity error from SDB */
+#define	P_AFSR_CP	0x0000000001000000ULL /* copyout parity error */
+#define	P_AFSR_WP	0x0000000000800000ULL /* writeback ecache data parity */
+#define	P_AFSR_EDP	0x0000000000400000ULL /* ecache data parity */
+#define	P_AFSR_UE	0x0000000000200000ULL /* uncorrectable ECC error */
+#define	P_AFSR_CE	0x0000000000100000ULL /* correctable ECC error */
+#define	P_AFSR_ETS	0x00000000000F0000ULL /* cache tag parity syndrome */
+#define	P_AFSR_P_SYND	0x000000000000FFFFULL /* data parity syndrome */
+
+/*
+ * All error types
+ */
+#define	S_AFSR_ALL_ERRS	(P_AFSR_STICKY & ~P_AFSR_PRIV)
+
+/*
+ * Shifts for Spitfire Asynchronous Fault Status Register
+ */
+#define	P_AFSR_D_SIZE_SHIFT	(57)
+#define	P_AFSR_CP_SHIFT		(24)
+#define	P_AFSR_ETS_SHIFT	(16)
+
+/*
+ * AFSR error bits for AFT Level 1 messages (uncorrected + parity + BERR + TO)
+ */
+#define	P_AFSR_LEVEL1   (P_AFSR_UE | P_AFSR_EDP | P_AFSR_WP | P_AFSR_CP |\
+			P_AFSR_LDP | P_AFSR_BERR | P_AFSR_TO)
+
+/*
+ * Bits of Spitfire Asynchronous Fault Status Register
+ */
+#define	S_AFSR_MASK	0x00000001FFFFFFFFULL /* <33:0>: valid AFSR bits */
+
+/*
+ * Bits of Spitfire Asynchronous Fault Address Register
+ * The Sabre AFAR includes more bits since it only has a UDBH, no UDBL
+ */
+#define	S_AFAR_PA	0x000001FFFFFFFFF0ULL /* PA<40:4>: physical address */
+#define	SABRE_AFAR_PA	0x000001FFFFFFFFF8ULL /* PA<40:3>: physical address */
+
+/*
+ * Bits of Spitfire/Sabre/Hummingbird Error Enable Registers
+ */
+#define	EER_EPEN	0x00000000000000010ULL /* enable ETP, EDP, WP, CP */
+#define	EER_UEEN	0x00000000000000008ULL /* enable UE */
+#define	EER_ISAPEN	0x00000000000000004ULL /* enable ISAP */
+#define	EER_NCEEN	0x00000000000000002ULL /* enable the other errors */
+#define	EER_CEEN	0x00000000000000001ULL /* enable CE */
+#define	EER_DISABLE	0x00000000000000000ULL /* no errors enabled */
+#define	EER_ECC_DISABLE	(EER_EPEN|EER_UEEN|EER_ISAPEN)
+#define	EER_CE_DISABLE	(EER_EPEN|EER_UEEN|EER_ISAPEN|EER_NCEEN)
+#define	EER_ENABLE	(EER_EPEN|EER_UEEN|EER_ISAPEN|EER_NCEEN|EER_CEEN)
+
+/*
+ * Bits and vaddrs of Spitfire Datapath Error Registers
+ */
+#define	P_DER_UE	0x00000000000000200ULL	/* UE has occurred */
+#define	P_DER_CE	0x00000000000000100ULL	/* CE has occurred */
+#define	P_DER_E_SYND	0x000000000000000FFULL	/* SYND<7:0>: ECC syndrome */
+#define	P_DER_H		0x0			/* datapath error reg upper */
+#define	P_DER_L		0x18			/* datapath error reg upper */
+
+/*
+ * Bits of Spitfire Datapath Control Register
+ */
+#define	P_DCR_VER	0x000001E00		/* datapath version */
+#define	P_DCR_F_MODE	0x000000100		/* send FCB<7:0> */
+#define	P_DCR_FCB	0x0000000FF		/* ECC check bits to force */
+#define	P_DCR_H		0x20			/* datapath control reg upper */
+#define	P_DCR_L		0x38			/* datapath control reg lower */
+
+/*
+ * Bits and shifts for the Spitfire (S), Sabre (SB) and Hummingbird (HB)
+ * Ecache tag data
+ */
+#define	S_ECTAG_MASK	0x000000000003FFFFFULL	/* spitfire ecache tag mask */
+#define	SB_ECTAG_MASK	0x00000000000000FFFULL	/* sabre ecache tag mask */
+#define	HB_ECTAG_MASK	0x0000000000000FFFFULL	/* hbird ecache tag mask */
+#define	S_ECSTATE_MASK	0x00000000001C00000ULL	/* spitfire tag state mask */
+#define	SB_ECSTATE_MASK 0x0000000000000C000ULL	/* sabre tag state mask */
+#define	HB_ECSTATE_MASK 0x00000000000030000ULL	/* hbird tag state mask */
+#define	S_ECPAR_MASK	0x0000000001E000000ULL	/* spitfire tag parity mask */
+#define	SB_ECPAR_MASK	0x00000000000030000ULL	/* sabre tag parity mask */
+#define	HB_ECPAR_MASK	0x00000000000300000ULL	/* hbird tag parity mask */
+#define	S_ECTAG_SHIFT		19		/* spitfire ecache tag shift */
+#define	SB_ECTAG_SHIFT		18		/* sabre ecache tag shift */
+#define	HB_ECTAG_SHIFT		16		/* hbird ecache tag shift */
+#define	S_ECSTATE_SHIFT		22		/* spitfire tag state shift */
+#define	SB_ECSTATE_SHIFT	14		/* sabre tag state shift */
+#define	HB_ECSTATE_SHIFT	16		/* hbird tag state shift */
+#define	S_ECPAR_SHIFT		25		/* spitfire tag parity shift */
+#define	SB_ECPAR_SHIFT		16		/* sabre tag parity shift */
+#define	HB_ECPAR_SHIFT		20		/* hbird tag parity shift */
+#define	S_ECACHE_MAX_LSIZE	64		/* E$ line size */
+
+/*
+ * Constants representing the complete Spitfire (S), Sabre (SB) and Hummingbird
+ * (HB) tag state:
+ */
+#define	S_ECSTATE_SHR		0x1		/* shared */
+#define	S_ECSTATE_EXL		0x3		/* exclusive */
+#define	S_ECSTATE_OWN		0x5		/* owner */
+#define	S_ECSTATE_MOD		0x7		/* modified */
+#define	SB_ECSTATE_EXL		0x2		/* exclusive */
+#define	SB_ECSTATE_MOD		0x3		/* modified */
+#define	HB_ECSTATE_EXL		0x2		/* exclusive */
+#define	HB_ECSTATE_MOD		0x3		/* modified */
+
+/*
+ * Constants representing the individual Spitfire (S), Sabre (SB) and
+ * Hummingbird (HB) state bits:
+ */
+#define	S_ECSTATE_VALID		0x1		/* line is valid */
+#define	S_ECSTATE_DIRTY		0x4		/* line is dirty */
+#define	SB_ECSTATE_VALID	0x2		/* line is valid */
+#define	SB_ECSTATE_DIRTY	0x1		/* line is dirty */
+#define	HB_ECSTATE_VALID	0x2		/* line is valid */
+#define	HB_ECSTATE_DIRTY	0x1		/* line is dirty */
+
+/*
+ * Constants representing the individual Spitfire (S), Sabre (SB) and
+ * Hummingbird (HB) state parity and address parity bits:
+ */
+#define	S_ECSTATE_PARITY	0x8		/* tag state parity bit */
+#define	S_EC_PARITY		0xF		/* all parity bits */
+#define	SB_ECSTATE_PARITY	0x2		/* tag state parity bit */
+#define	SB_EC_PARITY		0x3		/* all parity bits */
+#define	HB_ECSTATE_PARITY	0x2		/* tag state parity bit */
+#define	HB_EC_PARITY		0x3		/* all parity bits */
+
+#ifdef HUMMINGBIRD
+
+#define	HB_ESTAR_MODE		INT64_C(0x1FE0000F080)	/* estar mode reg */
+#define	HB_MEM_CNTRL0		INT64_C(0x1FE0000F010)	/* mem control0 reg */
+#define	HB_REFRESH_COUNT_MASK	0x7F00			/* mc0<14:8>: ref cnt */
+#define	HB_REFRESH_COUNT_SHIFT	8			/* bits to shift */
+#define	HB_REFRESH_INTERVAL	INT64_C(7800)		/* 7800 nsecs memory */
+							/* refresh interval */
+							/* works for all DIMM */
+							/* same value as OBP */
+#define	HB_REFRESH_CLOCKS_PER_COUNT	INT64_C(64)	/* cpu clks per count */
+#define	HB_SELF_REFRESH_MASK	0x10000			/* mc0<16>: self ref */
+#define	HB_SELF_REFRESH_SHIFT	16			/* bits to shift */
+#define	HB_SELF_REFRESH_DISABLE	0			/* disable self ref */
+#define	HB_SELF_REFRESH_ENABLE	1			/* enable self ref */
+
+#define	HB_ECLK_1	INT64_C(0x0000000000000000) 	/* 1/1 clock */
+#define	HB_ECLK_2	INT64_C(0x0000000000000001) 	/* 1/2 clock */
+#define	HB_ECLK_4	INT64_C(0x0000000000000003) 	/* 1/4 clock */
+#define	HB_ECLK_6	INT64_C(0x0000000000000002) 	/* 1/6 clock */
+#define	HB_ECLK_8	INT64_C(0x0000000000000004) 	/* 1/8 clock */
+#define	HB_ECLK_MASK	(HB_ECLK_1|HB_ECLK_2|HB_ECLK_4|HB_ECLK_6|HB_ECLK_8)
+
+
+/*
+ * UPA Configuration Register
+ *
+ * +--------------+----+------+------+----------+------+-------------+
+ * |     Resv     | RR |  DM  | ELIM |   PCON   | MID  |     PCAP    |
+ * +--------------+----+------+------+----------+------+-------------+
+ *  63          39  38  37..36 35..33 32......22 21..17 16..........0
+ *
+ */
+
+#define	HB_UPA_DMAP_DATA_BIT	36	/* loads and stores direct mapped */
+#define	HB_UPA_DMAP_INSTR_BIT	37	/* instruction misses direct mapped */
+#define	HB_UPA_RR_BIT		38	/* reset rand generator */
+
+#endif /* HUMMINGBIRD */
+
+/*
+ * The minimum size needed to ensure consistency on a virtually address
+ * cache.  Computed by taking the largest virtually indexed cache and dividing
+ * by its associativity.
+ */
+#define	S_VAC_SIZE	0x4000
+
+#ifdef _KERNEL
+
+#ifndef _ASM
+#include <sys/kstat.h>
+
+void	get_udb_errors(uint64_t *udbh, uint64_t *udbl);
+
+/*
+ * The scrub_misc structure contains miscellaneous bookeepping items for
+ * scrubbing the E$.
+ *
+ * Counter of outstanding E$ scrub requests. The counter for a given CPU id
+ * is atomically incremented and decremented _only_  on that CPU,
+ * to avoid cacheline ownership bouncing.
+ */
+
+typedef struct spitfire_scrub_misc {
+	uint32_t	ec_scrub_outstanding;	/* outstanding reqs */
+	int		ecache_flush_index;	/* offset into E$ for flush */
+	int		ecache_busy;		/* keeps track if cpu busy */
+	int		ecache_nlines;		/* no. of E$ lines */
+	int		ecache_mirror;		/* E$ is mirrored */
+	kstat_t		*ecache_ksp;		/* ptr to the kstat */
+} spitfire_scrub_misc_t;
+
+/*
+ * Spitfire module private data structure. One of these is allocated for each
+ * valid cpu at setup time and is pointed to by the machcpu "cpu_private"
+ * pointer.
+ */
+typedef struct spitfire_private {
+	spitfire_scrub_misc_t	sfpr_scrub_misc;
+	uint64_t		sfpr_scrub_afsr;
+} spitfire_private_t;
+
+#endif /* !_ASM */
+
+#endif /* _KERNEL */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_SPITREGS_H */
diff --git a/usr/src/uts/sun4u/sys/starfire.h b/usr/src/uts/sun4u/sys/starfire.h
new file mode 100644
index 0000000000..038f0b3c0e
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/starfire.h
@@ -0,0 +1,248 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 1996-2000 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_STARFIRE_H
+#define	_STARFIRE_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* I/O space definitions */
+#define	STARFIRE_IO_BASE 0x10000000000ULL
+
+/* UPA Port Space (UPS) definitions */
+#define	STARFIRE_UPS_MID_SHIFT 33	/* MID is 7 bits */
+#define	STARFIRE_UPS_BRD_SHIFT 36
+#define	STARFIRE_UPS_BUS_SHIFT 6
+
+/* Starfire Interconnect Space (IS) definitions */
+#define	STARFIRE_IS_MC_BASE	0x10e80000000ULL /* MC Register Space */
+
+
+/* Port Specific Interconnect Space (PSI) */
+#define	STARFIRE_PSI_BASE \
+		0x100f8000000ULL	/* put mid in [39:33] */
+#define	STARFIRE_PSI_PCREG_OFF \
+		0x4000000ULL		/* PSI offset for PC regs */
+#define	STARFIRE_BRD_TO_PSI(board) \
+		(STARFIRE_PSI_BASE | \
+			(((uint64_t)board) << STARFIRE_UPS_BRD_SHIFT))
+
+
+/* Starfire BootBus Space (BS) definitions */
+#define	STARFIRE_PSI_BS_BASE \
+		STARFIRE_PSI_BASE	/* BS at start of PSI Space */
+
+#define	STARFIRE_UPAID2PSI_BS(upaid) \
+		(STARFIRE_PSI_BS_BASE | \
+		((u_longlong_t)STARFIRE_UPAID2HWMID(upaid) << \
+			STARFIRE_UPS_MID_SHIFT))
+
+#define	STARFIRE_DEV2UPAID(b, p, i) \
+		((((i) & 0x1) << 6) | \
+		(((b) & 0xf) << 2) | \
+		((p) & 0x3))
+
+/* Starfire Port Controller Register offsets */
+#define	STARFIRE_PC_CONF		0x000000UL /* Configuration Reg */
+#define	STARFIRE_PC_COMP_ID		0x000010UL /* Component ID Reg */
+#define	STARFIRE_PC_BUS_CONF		0x000020UL /* Bus Configuration Reg */
+#define	STARFIRE_PC_TO_HOLD_CONF	0x000030UL /* Timeout/Hold Config Reg */
+#define	STARFIRE_PC_CIC_WRITE_DATA	0x000040UL /* CIC Write Data Reg */
+#define	STARFIRE_PC_FORCE_PARITY_ERR	0x000050UL /* Force Parity Err Reg */
+#define	STARFIRE_PC_ERR_0_MASK		0x000060UL /* Err 0 Mask Reg */
+#define	STARFIRE_PC_ERR_1_MASK		0x000070UL /* Err 1 Mask Reg */
+#define	STARFIRE_PC_ERR_0		0x000080UL /* Err 0 Reg */
+#define	STARFIRE_PC_ERR_1		0x000090UL /* Err 1 Reg */
+#define	STARFIRE_PC_ERR_DATA_SRC	0x0000a0UL /* Err Data Src Reg */
+#define	STARFIRE_PC_ERR_DATA_LOW	0x0000b0UL /* Err Data Lower Reg */
+#define	STARFIRE_PC_ERR_DATA_HI		0x0000c0UL /* Err Data Upper Reg */
+#define	STARFIRE_PC_PORT_ID		0x0000d0UL
+#define	STARFIRE_PC_PERF_COUNT_0	0x0000e0UL
+#define	STARFIRE_PC_PERF_COUNT_1	0x0000f0UL
+#define	STARFIRE_PC_PERF_COUNT_CNTRL	0x000100UL
+#define	STARFIRE_PC_BLOCK		0x0001c0UL /* 512 Byte scr area */
+#define	STARFIRE_PC_INT_MAP		0x000200UL /* 32 regs 00.0200-00.03f0 */
+#define	STARFIRE_PC_MADR		0x000400UL /* 16 regs 00.0400-00.04f0 */
+
+/* Starfire PC definitions/macros */
+#define	STARFIRE_PC_MADR_BOARD_SHIFT	4
+#define	STARFIRE_PC_MADR_ADDR(bb, rb, p) \
+		(STARFIRE_BRD_TO_PSI(bb) | \
+		((uint64_t)(p) << STARFIRE_UPS_MID_SHIFT) | \
+		((uint64_t)(rb) << STARFIRE_PC_MADR_BOARD_SHIFT) | \
+		STARFIRE_PSI_PCREG_OFF | \
+		STARFIRE_PC_MADR)
+
+/* Starfire BB (BootBus) definitions/macros */
+#define	STARFIRE_BB_SYSRESET_CNTRL	0x800000ULL
+#define	STARFIRE_BB_PAUSE_FLUSH		0x800016ULL
+
+#define	STARFIRE_BB_PC_PAUSE(i)		((uchar_t)(1 << (i)))
+#define	STARFIRE_BB_PC_FLUSH(i)		((uchar_t)(1 << ((i)+2)))
+#define	STARFIRE_BB_PC_IDLE(i)		((uchar_t)(1 << ((i)+4)))
+
+#define	STARFIRE_BB_SYSRESET(i)		((uchar_t)(1 << (i)))
+
+#define	STARFIRE_BB_PC_ADDR(bb, p, io) \
+		(STARFIRE_UPAID2PSI_BS(STARFIRE_DEV2UPAID((bb), (p), (io))) | \
+		STARFIRE_BB_PAUSE_FLUSH)
+#define	STARFIRE_BB_RESET_ADDR(bb, p) \
+		(STARFIRE_UPAID2PSI_BS(STARFIRE_DEV2UPAID((bb), (p), 0)) | \
+		STARFIRE_BB_SYSRESET_CNTRL)
+
+/* Starfire Memory Controller Register offsets */
+#define	STARFIRE_MC_ASR			0x000400U	/* Addr Select Reg */
+#define	STARFIRE_MC_DIMMTYPE		0x00c800U	/* DIMM Type Code Reg */
+#define	STARFIRE_MC_IDLE		0x00cc00U	/* Idle MC Reg */
+
+/* Starfire MC definitions/macros */
+#define	STARFIRE_MC_MEM_PRESENT_MASK	0x80000000U
+#define	STARFIRE_MC_MEM_BASEADDR_MASK	0x7fff0000U
+#define	STARFIRE_MC_IDLE_MASK		0x00008000U
+#define	STARFIRE_MC_MASK_MASK		0x00007f00U
+#define	STARFIRE_MC_DIMMSIZE_MASK	0x0000001fU
+#define	STARFIRE_MC_INTERLEAVE_MASK	0x00000001U
+#define	STARFIRE_MC_MASK_SHIFT		18
+#define	STARFIRE_MC_BASE_SHIFT		10
+#define	STARFIRE_MC_ADDR_HIBITS		0x1fe00000000ULL
+#define	STARFIRE_MC_ASR_ADDR(reg)	((reg) | (uint64_t)STARFIRE_MC_ASR)
+#define	STARFIRE_MC_IDLE_ADDR(reg)	((reg) | (uint64_t)STARFIRE_MC_IDLE)
+#define	STARFIRE_MC_DIMMTYPE_ADDR(reg)	((reg) | (uint64_t)STARFIRE_MC_DIMMTYPE)
+#define	STARFIRE_MC_ASR_ADDR_BOARD(b) \
+		(((uint64_t)(b) << STARFIRE_UPS_BRD_SHIFT) | \
+		STARFIRE_IS_MC_BASE | \
+		(uint64_t)STARFIRE_MC_ASR)
+
+/*
+ * Memory boards on Starfire are aligned on 8GB
+ * boundaries, i.e. the physical address space
+ * is not physically contiguous.
+ */
+#define	STARFIRE_MC_MEMBOARD_SHIFT	33
+#define	STARFIRE_MC_MEMBOARD_ALIGNMENT	\
+		(UINT64_C(1) << STARFIRE_MC_MEMBOARD_SHIFT)
+
+/*
+ * Starfire has a special regspec for the "reg" property of the
+ * mem-unit node since this node is homegrown.
+ */
+struct sf_memunit_regspec {
+	uint_t	regspec_addr_hi;
+	uint_t	regspec_addr_lo;
+	uint_t	regspec_size_hi;
+	uint_t	regspec_size_lo;
+};
+
+/*
+ * Conversion macros
+ */
+
+/*
+ * Starfire hardware version of the upaid (commonly known as
+ * HWMID) is different from the software version (also known as upaid).
+ *  HW version BBBBIPp   == SW version IBBBBPp
+ */
+#define	STARFIRE_UPAID2HWMID(upaid) (((upaid & 0x3C) << 1) | \
+				((upaid & 0x40) >> 4) | (upaid & 0x3))
+
+
+/* Xfire UPA ID to UPA Port Specific Space */
+#define	STARFIRE_UPAID2UPS(upaid) \
+		(((u_longlong_t)STARFIRE_UPAID2HWMID(upaid) << \
+				STARFIRE_UPS_MID_SHIFT) | STARFIRE_IO_BASE)
+
+/*
+ * Macro to convert our 7 bits HW MID to 7 bits SW MID
+ * That is "BBBBIPp" to "IBBBBPp".
+ */
+#define	STARFIRE_HWMID2SWMID(mid) ((mid & 0x3) | ((mid & 0x78) >> 1) | \
+					((mid & 0x4) << 4))
+
+/*
+ * Macro to convert our 7 bits UPAid to Sun's 5 bit HW Interrupt
+ * group number required in some hardware registers (sysios).
+ * That is "IBBBBPp" to "BBBBp", where "BBBB" is the board number,
+ * "IP" is the PC id and "p" is the port number.
+ */
+#define	STARFIRE_UPAID2HWIGN(upaid) \
+		(((upaid & 0x3C) >> 1) | (upaid & 0x1))
+
+/*
+ * Macro to convert our UPAid to a 7 bit Starfire version of the
+ * interrupt group number. This so-called IGN is part of
+ * the interrupt vector number read by the CPU serving this interrupt.
+ * Thanks to the warp minds of our hardware guys, it is in this
+ * convoluted weird format. Note that the interrupt vector number is
+ * then used to index into the interrupt dispatch table to get its
+ * interrupt handler.
+ * Convert "IBBBBPp" to "XPBBBBp" where "BBBB" is the 4bit board #,
+ * "IP" is the 2 bit PC id, "p" is the port # and "X" is ~I.
+ */
+#define	STARFIRE_UPAID2IGN(upaid)  (STARFIRE_UPAID2HWIGN(upaid) | \
+			((upaid & 0x2) << 4) |  \
+			((upaid & 0x40) ^ 0x40))
+
+/*
+ * Starfire platform specific routines currently only defined
+ * in starfire.c and referenced by DR.
+ */
+extern int	plat_max_boards();
+extern int	plat_max_cpu_units_per_board();
+extern int	plat_max_mem_units_per_board();
+extern int	plat_max_io_units_per_board();
+
+/*
+ * Starfire platform specific interrupt translation routines
+ */
+extern void pc_ittrans_init(int, caddr_t *);
+extern void pc_ittrans_uninit(caddr_t);
+extern int pc_translate_tgtid(caddr_t, int, volatile uint64_t *);
+extern void pc_ittrans_cleanup(caddr_t, volatile uint64_t *);
+
+/*
+ * Maximum number of system boards supported in a Starfire.
+ */
+#define	STARFIRE_MAX_BOARDS	16
+
+/*
+ * We reserve some "fake" DMV values for Starfire IDN.  These are treated
+ * as hardware interrupt numbers, but they don't correspond to an actual UPA
+ * port; they can thus be allocated as "well-known" numbers for IDN purposes.
+ */
+#define	STARFIRE_DMV_EXTRA	4
+#define	STARFIRE_DMV_HWINT	(MAX_UPA+STARFIRE_DMV_EXTRA)
+#define	STARFIRE_DMV_IDN_BASE	(MAX_UPA)
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _STARFIRE_H */
diff --git a/usr/src/uts/sun4u/sys/sudev.h b/usr/src/uts/sun4u/sys/sudev.h
new file mode 100644
index 0000000000..2effc7528e
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/sudev.h
@@ -0,0 +1,400 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*	Copyright (c) 1990, 1991 UNIX System Laboratories, Inc.	*/
+/*	Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T	*/
+/*	  All Rights Reserved 	*/
+
+/*
+ * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_SUDEV_H
+#define	_SYS_SUDEV_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <sys/tty.h>
+#include <sys/ksynch.h>
+#include <sys/dditypes.h>
+#include <sys/types.h>
+#include <sys/kstat.h>
+
+/*
+ * Definitions for INS8250 / 16550  chips
+ */
+
+/* defined as offsets from the data register */
+#define	DAT		0 	/* receive/transmit data */
+#define	ICR		1  	/* interrupt control register */
+#define	ISR		2   	/* interrupt status register */
+#define	LCR		3   	/* line control register */
+#define	MCR		4   	/* modem control register */
+#define	LSR		5   	/* line status register */
+#define	MSR		6   	/* modem status register */
+#define	DLL		0   	/* divisor latch (lsb) */
+#define	DLH		1   	/* divisor latch (msb) */
+#define	FIFOR		ISR	/* FIFO register for 16550 */
+#define	OUTB(offset, value)	ddi_put8(asy->asy_handle, \
+				    asy->asy_ioaddr+offset, value)
+#define	INB(offset)	ddi_get8(asy->asy_handle, asy->asy_ioaddr+offset)
+
+/*
+ * INTEL 8210-A/B & 16450/16550 Registers Structure.
+ */
+
+/* Line Control Register */
+#define	WLS0		0x01	/* word length select bit 0 */
+#define	WLS1		0x02	/* word length select bit 2 */
+#define	STB		0x04	/* number of stop bits */
+#define	PEN		0x08	/* parity enable */
+#define	EPS		0x10	/* even parity select */
+#define	SETBREAK 	0x40	/* break key */
+#define	DLAB		0x80	/* divisor latch access bit */
+#define	RXLEN   	0x03   	/* # of data bits per received/xmitted char */
+#define	STOP1   	0x00
+#define	STOP2   	0x04
+#define	PAREN   	0x08
+#define	PAREVN  	0x10
+#define	PARMARK 	0x20
+#define	SNDBRK  	0x40
+
+
+#define	BITS5		0x00	/* 5 bits per char */
+#define	BITS6		0x01	/* 6 bits per char */
+#define	BITS7		0x02	/* 7 bits per char */
+#define	BITS8		0x03	/* 8 bits per char */
+
+/* baud rate definitions */
+#define	ASY110		1047	/* 110 baud rate for serial console */
+#define	ASY150		768	/* 150 baud rate for serial console */
+#define	ASY300		384	/* 300 baud rate for serial console */
+#define	ASY600		192	/* 600 baud rate for serial console */
+#define	ASY1200		96	/* 1200 baud rate for serial console */
+#define	ASY2400		48	/* 2400 baud rate for serial console */
+#define	ASY4800		24	/* 4800 baud rate for serial console */
+#define	ASY9600		12	/* 9600 baud rate for serial console */
+
+/* Line Status Register */
+#define	RCA		0x01	/* data ready */
+#define	OVRRUN		0x02	/* overrun error */
+#define	PARERR		0x04	/* parity error */
+#define	FRMERR		0x08	/* framing error */
+#define	BRKDET  	0x10	/* a break has arrived */
+#define	XHRE		0x20	/* tx hold reg is now empty */
+#define	XSRE		0x40	/* tx shift reg is now empty */
+#define	RFBE		0x80	/* rx FIFO Buffer error */
+
+/* Interrupt Id Regisger */
+#define	MSTATUS		0x00	/* modem status changed */
+#define	NOINTERRUPT	0x01	/* no interrupt pending */
+#define	TxRDY		0x02	/* Transmitter Holding Register Empty */
+#define	RxRDY		0x04	/* Receiver Data Available */
+#define	FFTMOUT 	0x0c	/* FIFO timeout - 16550AF */
+#define	RSTATUS 	0x06	/* Receiver Line Status */
+
+/* Interrupt Enable Register */
+#define	RIEN		0x01	/* Received Data Ready */
+#define	TIEN		0x02	/* Tx Hold Register Empty */
+#define	SIEN		0x04	/* Receiver Line Status */
+#define	MIEN		0x08	/* Modem Status */
+
+/* Modem Control Register */
+#define	DTR		0x01	/* Data Terminal Ready */
+#define	RTS		0x02	/* Request To Send */
+#define	OUT1		0x04	/* Aux output - not used */
+#define	OUT2		0x08	/* dis/enable int per INO on ALI1535D+ */
+#define	ASY_LOOP	0x10	/* loopback for diagnostics */
+
+/* Modem Status Register */
+#define	DCTS		0x01	/* Delta Clear To Send */
+#define	DDSR		0x02	/* Delta Data Set Ready */
+#define	DRI		0x04	/* Trail Edge Ring Indicator */
+#define	DDCD		0x08	/* Delta Data Carrier Detect */
+#define	CTS		0x10	/* Clear To Send */
+#define	DSR		0x20	/* Data Set Ready */
+#define	RI		0x40	/* Ring Indicator */
+#define	DCD		0x80	/* Data Carrier Detect */
+
+#define	DELTAS(x)	((x)&(DCTS|DDSR|DRI|DDCD))
+#define	STATES(x)	((x)(CTS|DSR|RI|DCD))
+
+/* flags for FCR (FIFO Control register) */
+#define	FIFO_OFF	0x00	/* fifo disabled */
+#define	FIFO_ON		0x01	/* fifo enabled */
+#define	FIFOEN		0x8f	/* fifo enabled, w/ 8 byte trigger */
+#define	FIFORCLR	0x8b	/* Clear receiver FIFO only */
+
+#define	FIFORXFLSH	0x02	/* flush receiver FIFO */
+#define	FIFOTXFLSH	0x04	/* flush transmitter FIFO */
+#define	FIFODMA		0x08	/* DMA mode 1 */
+#define	FIFO_TRIG_1	0x00	/* 1 byte trigger level */
+#define	FIFO_TRIG_4	0x40	/* 4 byte trigger level */
+#define	FIFO_TRIG_8	0x80	/* 8 byte trigger level */
+#define	FIFO_TRIG_14	0xC0	/* 14 byte trigger level */
+
+/*
+ * Defines for ioctl calls (VP/ix)
+ */
+
+#define	AIOC		('A'<<8)
+#define	AIOCINTTYPE	(AIOC|60)	/* set interrupt type */
+#define	AIOCDOSMODE	(AIOC|61)	/* set DOS mode */
+#define	AIOCNONDOSMODE	(AIOC|62)	/* reset DOS mode */
+#define	AIOCSERIALOUT	(AIOC|63)	/* serial device data write */
+#define	AIOCSERIALIN	(AIOC|64)	/* serial device data read */
+#define	AIOCSETSS	(AIOC|65)	/* set start/stop chars */
+#define	AIOCINFO	(AIOC|66)	/* tell usr what device we are */
+
+/* Ioctl alternate names used by VP/ix */
+#define	VPC_SERIAL_DOS		AIOCDOSMODE
+#define	VPC_SERIAL_NONDOS	AIOCNONDOSMODE
+#define	VPC_SERIAL_INFO		AIOCINFO
+#define	VPC_SERIAL_OUT		AIOCSERIALOUT
+#define	VPC_SERIAL_IN		AIOCSERIALIN
+
+/* Serial in/out requests */
+#define	SO_DIVLLSB	1
+#define	SO_DIVLMSB	2
+#define	SO_LCR		3
+#define	SO_MCR		4
+#define	SI_MSR		1
+#define	SIO_MASK(elem)		(1<<((elem)-1))
+
+#define	OVERRUN		040000
+#define	FRERROR		020000
+#define	PERROR		010000
+#define	S_ERRORS	(PERROR|OVERRUN|FRERROR)
+
+/*
+ * Ring buffer and async line management definitions.
+ */
+#define	RINGBITS	16		/* # of bits in ring ptrs */
+#define	RINGSIZE	(1<<RINGBITS)   /* size of ring */
+#define	RINGMASK	(RINGSIZE-1)
+#define	RINGFRAC	12		/* fraction of ring to force flush */
+
+#define	RING_INIT(ap)  ((ap)->async_rput = (ap)->async_rget = 0)
+#define	RING_CNT(ap)   (((ap)->async_rput - (ap)->async_rget) & RINGMASK)
+#define	RING_FRAC(ap)  ((int)RING_CNT(ap) >= (int)(RINGSIZE/RINGFRAC))
+#define	RING_POK(ap, n) ((int)RING_CNT(ap) < (int)(RINGSIZE-(n)))
+#define	RING_PUT(ap, c) \
+	((ap)->async_ring[(ap)->async_rput++ & RINGMASK] =  (uchar_t)(c))
+#define	RING_UNPUT(ap) ((ap)->async_rput--)
+#define	RING_GOK(ap, n) ((int)RING_CNT(ap) >= (int)(n))
+#define	RING_GET(ap)   ((ap)->async_ring[(ap)->async_rget++ & RINGMASK])
+#define	RING_EAT(ap, n) ((ap)->async_rget += (n))
+#define	RING_MARK(ap, c, s) \
+	((ap)->async_ring[(ap)->async_rput++ & RINGMASK] = ((uchar_t)(c)|(s)))
+#define	RING_UNMARK(ap) \
+	((ap)->async_ring[((ap)->async_rget) & RINGMASK] &= ~S_ERRORS)
+#define	RING_ERR(ap, c) \
+	((ap)->async_ring[((ap)->async_rget) & RINGMASK] & (c))
+
+/*
+ * Serial kstats structure and macro to increment an individual kstat
+ */
+struct serial_kstats {
+		kstat_named_t	ringover;	/* ring buffer overflow */
+		kstat_named_t	siloover;	/* silo overflow */
+};
+
+#define	INC64_KSTAT(asy, stat) (asy)->kstats.stat.value.ui64++;
+
+/*
+ * Hardware channel common data. One structure per port.
+ * Each of the fields in this structure is required to be protected by a
+ * mutex lock at the highest priority at which it can be altered.
+ * The asy_flags, and asy_next fields can be altered by interrupt
+ * handling code that must be protected by the mutex whose handle is
+ * stored in asy_excl_hi.  All others can be protected by the asy_excl
+ * mutex, which is lower priority and adaptive.
+ */
+struct asycom {
+	int		asy_flags;	/* random flags  */
+					/* protected by asy_excl_hi lock */
+	uint_t		asy_hwtype;	/* HW type: ASY82510, etc. */
+	uint_t		asy_use_fifo;	/* HW FIFO use it or not ?? */
+	uint_t		asy_fifo_buf;	/* With FIFO = 16, otherwise = 1 */
+	uchar_t		*asy_ioaddr;	/* i/o address of ASY port */
+	uint_t		asy_vect;	/* IRQ number */
+	boolean_t	suspended;	/* TRUE if driver suspended */
+	caddr_t		asy_priv;	/* protocol private data */
+	dev_info_t	*asy_dip;	/* dev_info */
+	long		asy_unit;	/* which port */
+	ddi_iblock_cookie_t asy_iblock;
+	kmutex_t	*asy_excl;	/* asy adaptive mutex */
+	kmutex_t	*asy_excl_hi;	/* asy spinlock mutex */
+	ddi_acc_handle_t asy_handle;    /* ddi_get/put handle */
+	ushort_t	asy_rsc_console;	/* RSC console port */
+	ushort_t	asy_rsc_control;	/* RSC control port */
+	ushort_t	asy_lom_console;	/* LOM console port */
+	uint_t		asy_xmit_count;	/* Count the no of xmits in one intr */
+	uint_t		asy_out_of_band_xmit; /* Out of band xmission */
+	uint_t		asy_rx_count;	/* No. of bytes rx'eved in one intr */
+	uchar_t		asy_device_type; /* Currently used for this device */
+	uchar_t		asy_trig_level;	/* Receive FIFO trig level */
+	kmutex_t	*asy_soft_lock;	/* soft lock for gaurding softpend. */
+	int		asysoftpend;	/* Flag indicating soft int pending. */
+	ddi_softintr_t asy_softintr_id;
+	ddi_iblock_cookie_t asy_soft_iblock;
+	int		asy_baud_divisor_factor; /* for different chips */
+	int		asy_ocflags; /* old cflags used in asy_program() */
+	uint_t		asy_cached_msr; /* a cache for the MSR register */
+	int		asy_speed_cap; /* maximum baud rate */
+	kstat_t		*sukstat;	/* ptr to serial kstats */
+	struct serial_kstats kstats;	/* serial kstats structure */
+	boolean_t	inperim;	/* in streams q perimeter */
+};
+
+/*
+ * Asychronous protocol private data structure for ASY.
+ * Each of the fields in the structure is required to be protected by
+ * the lower priority lock except the fields that are set only at
+ * base level but cleared (with out lock) at interrupt level.
+ */
+struct asyncline {
+	int		async_flags;	/* random flags */
+	kcondvar_t	async_flags_cv; /* condition variable for flags */
+	dev_t		async_dev;	/* device major/minor numbers */
+	mblk_t		*async_xmitblk;	/* transmit: active msg block */
+	struct asycom	*async_common;	/* device common data */
+	tty_common_t 	async_ttycommon; /* tty driver common data */
+	bufcall_id_t	async_wbufcid;	/* id for pending write-side bufcall */
+	timeout_id_t	async_polltid;	/* softint poll timeout id */
+
+	/*
+	 * The following fields are protected by the asy_excl_hi lock.
+	 * Some, such as async_flowc, are set only at the base level and
+	 * cleared (without the lock) only by the interrupt level.
+	 */
+	uchar_t		*async_optr;	/* output pointer */
+	int		async_ocnt;	/* output count */
+	uint_t		async_rput;	/* producing pointer for input */
+	uint_t		async_rget;	/* consuming pointer for input */
+	uchar_t		async_flowc;	/* flow control char to send */
+
+	/*
+	 * Each character stuffed into the ring has two bytes associated
+	 * with it.  The first byte is used to indicate special conditions
+	 * and the second byte is the actual data.  The ring buffer
+	 * needs to be defined as ushort_t to accomodate this.
+	 */
+	ushort_t	async_ring[RINGSIZE];
+
+	short		async_break;	/* break count */
+
+	union {
+		struct {
+			uchar_t _hw;	/* overrun (hw) */
+			uchar_t _sw;	/* overrun (sw) */
+		} _a;
+		ushort_t uover_overrun;
+	} async_uover;
+#define	async_overrun		async_uover._a.uover_overrun
+#define	async_hw_overrun	async_uover._a._hw
+#define	async_sw_overrun	async_uover._a._sw
+	short		async_ext;	/* modem status change count */
+	short		async_work;	/* work to do flag */
+	uchar_t		async_queue_full; /* Streams Queue Full */
+	uchar_t		async_ringbuf_overflow; /* when ring buffer overflows */
+	timeout_id_t	async_timer;	/* close drain progress timer */
+};
+
+/* definitions for async_flags field */
+#define	ASYNC_EXCL_OPEN	 0x10000000	/* exclusive open */
+#define	ASYNC_WOPEN	 0x00000001	/* waiting for open to complete */
+#define	ASYNC_ISOPEN	 0x00000002	/* open is complete */
+#define	ASYNC_OUT	 0x00000004	/* line being used for dialout */
+#define	ASYNC_CARR_ON	 0x00000008	/* carrier on last time we looked */
+#define	ASYNC_STOPPED	 0x00000010	/* output is stopped */
+#define	ASYNC_DELAY	 0x00000020	/* waiting for delay to finish */
+#define	ASYNC_BREAK	 0x00000040	/* waiting for break to finish */
+#define	ASYNC_BUSY	 0x00000080	/* waiting for transmission to finish */
+#define	ASYNC_DRAINING	 0x00000100	/* waiting for output to drain */
+#define	ASYNC_SERVICEIMM 0x00000200	/* queue soft interrupt as soon as */
+#define	ASYNC_HW_IN_FLOW 0x00000400	/* input flow control in effect */
+#define	ASYNC_HW_OUT_FLW 0x00000800	/* output flow control in effect */
+#define	ASYNC_PROGRESS	 0x00001000	/* made progress on output effort */
+#define	ASYNC_CLOSING	 0x00002000	/* closing the stream */
+
+/* asy_hwtype definitions */
+#define	ASY82510	0x1
+#define	ASY16550AF	0x2
+#define	ASY8250		0x3		/* 8250 or 16450 or 16550 */
+
+/* definitions for asy_flags field */
+#define	ASY_NEEDSOFT	0x00000001
+#define	ASY_DOINGSOFT	0x00000002
+#define	ASY_PPS		0x00000004
+#define	ASY_PPS_EDGE	0x00000008
+#define	ASY_IGNORE_CD	0x00000040
+
+/*
+ * Different devices this driver supports and what it is used to drive
+ * currently
+ */
+#define	ASY_KEYBOARD 	0x01
+#define	ASY_MOUSE	0x02
+#define	ASY_SERIAL	0x03
+
+/*
+ * RSC_DEVICE defines the bit in the minor device number that specifies
+ * the tty line is to be used for console/controlling a RSC device.
+ */
+#define	RSC_DEVICE	(1 << (NBITSMINOR32 - 4))
+
+/*
+ * OUTLINE defines the high-order flag bit in the minor device number that
+ * controls use of a tty line for dialin and dialout simultaneously.
+ */
+#define	OUTLINE		(1 << (NBITSMINOR32 - 1))
+#define	UNIT(x)		(getminor(x) & ~(OUTLINE | RSC_DEVICE))
+
+/* suggested number of soft state instances */
+#define	SU_INITIAL_SOFT_ITEMS	0x02
+
+/*
+ * ASYSETSOFT macro to pend a soft interrupt if one isn't already pending.
+ */
+
+#define	ASYSETSOFT(asy)	{		\
+	if (mutex_tryenter(asy->asy_soft_lock)) {	\
+		asy->asy_flags |= ASY_NEEDSOFT;	\
+		if (!asy->asysoftpend) {		\
+			asy->asysoftpend = 1;	\
+			mutex_exit(asy->asy_soft_lock);\
+			ddi_trigger_softintr(asy->asy_softintr_id);\
+		} else					\
+			mutex_exit(asy->asy_soft_lock);\
+	}						\
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* _SYS_SUDEV_H */
diff --git a/usr/src/uts/sun4u/sys/sysioerr.h b/usr/src/uts/sun4u/sys/sysioerr.h
new file mode 100644
index 0000000000..98518f1f68
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/sysioerr.h
@@ -0,0 +1,202 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 1991-1999 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_SYS_SYSIOERR_H
+#define	_SYS_SYSIOERR_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Sbus error interrupt priorities
+ */
+#define	SBUS_UE_PIL		12
+#define	SBUS_CE_PIL		11
+#define	SBUS_ERR_PIL		12
+#define	SBUS_THERMAL_PIL	9
+#define	SBUS_PF_PIL		12
+#define	SBUS_PM_PIL		12
+
+/*
+ * Bits of Sun5 SYSIO Control/Status Register
+ */
+#define	SYSIO_IMPL	0xF000000000000000ULL /* implementation number */
+#define	SYSIO_VER	0x0F00000000000000ULL /* revision number */
+#define	SYSIO_MID	0x00F8000000000000ULL /* UPA mid for SYSIO */
+#define	SYSIO_INTGN	0x0007C00000000000ULL /* interrupt group number */
+#define	SYSIO_APCKEN	0x0000000000000008ULL /* address parity check enable */
+#define	SYSIO_APERR	0x0000000000000004ULL /* system address parity error */
+#define	SYSIO_IAP	0x0000000000000002ULL /* invert UPA address parity */
+#define	SYSIO_MODE	0x0000000000000001ULL /* speed of SYSIO clock */
+
+/*
+ * Bits of Sun5 SBus ECC Control Register
+ */
+#define	SECR_ECC_EN	0x8000000000000000ULL /* enable ECC checking */
+#define	SECR_UE_INTEN	0x4000000000000000ULL /* enable UE_INT interrupt */
+#define	SECR_CE_INTEN	0x2000000000000000ULL /* enable CE_INT interrupt */
+
+/*
+ * Bits of Sun5 SBus UE Asynchronous Fault Status Register
+ */
+#define	SB_UE_AFSR_P_PIO 0x8000000000000000ULL /* primary UE, PIO access */
+#define	SB_UE_AFSR_P_DRD 0x4000000000000000ULL /* primary UE, DVMA read */
+#define	SB_UE_AFSR_P_DWR 0x2000000000000000ULL /* primary UE, DVMA write */
+#define	SB_UE_AFSR_P	 0xE000000000000000ULL /* primary UE */
+#define	SB_UE_AFSR_S_PIO 0x1000000000000000ULL /* secondary UE, PIO access */
+#define	SB_UE_AFSR_S_DRD 0x0800000000000000ULL /* secondary UE, DVMA read */
+#define	SB_UE_AFSR_S_DWR 0x0400000000000000ULL /* secondary UE, DVMA write */
+#define	SB_UE_AFSR_S	 0x1C00000000000000ULL /* secondary UE */
+#define	SB_UE_AFSR_OFF   0x0000E00000000000ULL /* offset of dword w/pri. UE */
+#define	SB_UE_AFSR_SIZE  0x00001C0000000000ULL /* 2**size of bad transfer */
+#define	SB_UE_AFSR_MID   0x000003E000000000ULL /* master ID for pri. error */
+#define	SB_UE_AFSR_ISAP	 0x0000001000000000ULL /* system parity error */
+
+/*
+ * Shifts for SBus Sysio UE Asynchronous Fault Status Register
+ */
+#define	SB_UE_DW_SHIFT		(45)
+#define	SB_UE_SIZE_SHIFT	(42)
+#define	SB_UE_MID_SHIFT		(37)
+
+/*
+ * Bits of Fusion Desktop SBus UE Asynchronous Fault Address Register
+ */
+#define	SB_UE_AFAR_PA	0x000001FFFFFFFFFF    /* PA<40:0>: physical address */
+
+/*
+ * Bits of Sun5 SBus CE Asynchronous Fault Status Register
+ */
+#define	SB_CE_AFSR_P_PIO 0x8000000000000000ULL /* primary CE, PIO access */
+#define	SB_CE_AFSR_P_DRD 0x4000000000000000ULL /* primary CE, DVMA read */
+#define	SB_CE_AFSR_P_DWR 0x2000000000000000ULL /* primary CE, DVMA write */
+#define	SB_CE_AFSR_P	 0xE000000000000000ULL /* primary CE */
+#define	SB_CE_AFSR_S_PIO 0x1000000000000000ULL /* secondary CE, PIO access */
+#define	SB_CE_AFSR_S_DRD 0x0800000000000000ULL /* secondary CE, DVMA read */
+#define	SB_CE_AFSR_S_DWR 0x0400000000000000ULL /* secondary CE, DVMA write */
+#define	SB_CE_AFSR_S	 0x1C00000000000000ULL /* secondary CE */
+#define	SB_CE_AFSR_SYND  0x00FF000000000000ULL /* CE syndrome bits */
+#define	SB_CE_AFSR_OFF   0x0000E00000000000ULL /* offset of dword w/pri. CE */
+#define	SB_CE_AFSR_SIZE	 0x00001C0000000000ULL /* 2**size of failed transfer */
+#define	SB_CE_AFSR_MID	 0x000003E000000000ULL /* master ID for primary error */
+
+/*
+ * Shifts for Sun5 SBus CE Asynchronous Fault Status Register
+ */
+#define	SB_CE_SYND_SHIFT	(48)
+#define	SB_CE_OFFSET_SHIFT	(45)
+#define	SB_CE_SIZE_SHIFT	(42)
+#define	SB_CE_MID_SHIFT		(37)
+
+/*
+ * Bits of Sun5 Fusion Desktop SBus CE Asynchronous Fault Address Register
+ * Note: Fusion Desktop does not support E_SYND2.
+ */
+#define	SB_CE_E_SYND2	0xFF00000000000000ULL /* syndrome of prim. CE */
+#define	SB_CE_AFAR_PA	0x000001FFFFFFFFFFULL /* PA<40:0>: physical address */
+
+/*
+ * Shift for Sun5 SBus CE Asynchronous Fault Address Register
+ */
+#define	SB_CE_SYND2_SHIFT	(56)
+
+/*
+ * Bits of Sun5 SBus Control and Status Register
+ * See Fusion Desktop System Spec. Table 3-63 for details on slots 13-15
+ */
+#define	SB_CSR_IMPL	 0xF000000000000000ULL /* host adapter impl. number */
+#define	SB_CSR_REV	 0x0F00000000000000ULL /* host adapter rev. number */
+#define	SB_CSR_DPERR_S14 0x0020000000000000ULL /* SBus slot 14 aka Happy Meal */
+#define	SB_CSR_DPERR_S13 0x0010000000000000ULL /* SBus slot 13 aka APC */
+#define	SB_CSR_DPERR_S3  0x0008000000000000ULL /* SBus slot 3 DVMA parity err */
+#define	SB_CSR_DPERR_S2  0x0004000000000000ULL /* SBus slot 2 DVMA parity err */
+#define	SB_CSR_DPERR_S1  0x0002000000000000ULL /* SBus slot 1 DVMA parity err */
+#define	SB_CSR_DPERR_S0  0x0001000000000000ULL /* SBus slot 0 DVMA parity err */
+#define	SB_CSR_PIO_PERRS 0x00007F0000000000ULL /* SBus parity errors */
+#define	SB_CSR_PPERR_S15 0x0000400000000000ULL /* SBus slot 15 aka slavio */
+#define	SB_CSR_PPERR_S14 0x0000200000000000ULL /* SBus slot 14 aka Happy Meal */
+#define	SB_CSR_PPERR_S13 0x0000100000000000ULL /* SBus slot 13 aka APC */
+#define	SB_CSR_PPERR_S3  0x0000080000000000ULL /* SBus slot 3 PIO parity err */
+#define	SB_CSR_PPERR_S2  0x0000040000000000ULL /* SBus slot 2 PIO parity err */
+#define	SB_CSR_PPERR_S1  0x0000020000000000ULL /* SBus slot 1 PIO parity err */
+#define	SB_CSR_PPERR_S0  0x0000010000000000ULL /* SBus slot 0 PIO parity err */
+#define	SB_CSR_FAST_SBUS 0x0000000000000400ULL /* shorten PIO access latency */
+#define	SB_CSR_WAKEUP_EN 0x0000000000000200ULL /* power-management bit */
+#define	SB_CSR_ERRINT_EN 0x0000000000000100ULL /* enable intr. for SBus errs */
+#define	SB_CSR_ARBEN_MAC 0x0000000000000020ULL /* enable DVMA for Macio */
+#define	SB_CSR_ARBEN_APC 0x0000000000000010ULL /* enable DVMA for APC */
+#define	SB_CSR_ARBEN_SLT 0x000000000000000FULL /* enable DVMA for SBus slots */
+
+/*
+ * Shifts for Sun5 SBus Control and Status Register
+ */
+#define	SB_CSR_IMPL_SHIFT	(60)
+#define	SB_CSR_REV_SHIFT	(56)
+#define	SB_CSR_DVMA_PERR_SHIFT	(48)
+#define	SB_CSR_PIO_PERR_SHIFT	(40)
+
+/*
+ * Bits of Sun5 SBus Asynchronous Fault Status Register
+ */
+#define	SB_AFSR_P_ERRS	0xE000000000000000ULL /* primary errors */
+#define	SB_AFSR_P_LE	0x8000000000000000ULL /* primary LATE_ERR */
+#define	SB_AFSR_P_TO	0x4000000000000000ULL /* primary SBus TIMEOUT */
+#define	SB_AFSR_P_BERR	0x2000000000000000ULL /* primary SBus ERR ack */
+#define	SB_AFSR_S_ERRS	0x1C00000000000000ULL /* secondary errors */
+#define	SB_AFSR_S_LE	0x1000000000000000ULL /* secondary LATE_ERR */
+#define	SB_AFSR_S_TO	0x0800000000000000ULL /* secondary SBus TIMEOUT */
+#define	SB_AFSR_S_BERR	0x0400000000000000ULL /* secondary SBus ERR ack */
+#define	SB_AFSR_RD	0x0000800000000000ULL /* primary error was READ op. */
+#define	SB_AFSR_SIZE	0x00001C0000000000ULL /* 2**size of failed transfer */
+#define	SB_AFSR_MID	0x000003E000000000ULL /* master ID for primary error */
+
+/*
+ * Shifts for Sun5 SBus Asynchronous Fault Status Register
+ */
+#define	SB_AFSR_SIZE_SHIFT	(42)
+#define	SB_AFSR_MID_SHIFT	(37)
+
+/*
+ * Bits of Fusion Desktop SBus Asynchronous Fault Address Register
+ */
+#define	SB_AFAR_PA	0x000001FFFFFFFFFFULL /* PA<40:0>: physical address */
+
+/*
+ * Function prototypes
+ */
+extern int
+sysio_err_init(struct sbus_soft_state *softsp, caddr_t address);
+extern int
+sysio_err_resume_init(struct sbus_soft_state *softsp);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_SYSIOERR_H */
diff --git a/usr/src/uts/sun4u/sys/sysiosbus.h b/usr/src/uts/sun4u/sys/sysiosbus.h
new file mode 100644
index 0000000000..d72c1c0aa3
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/sysiosbus.h
@@ -0,0 +1,421 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_SYSIOSBUS_H
+#define	_SYS_SYSIOSBUS_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifndef _ASM
+#include <sys/avintr.h>
+#include <sys/vmem.h>
+#include <sys/ontrap.h>
+#include <sys/machsystm.h>
+#endif
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* Things for debugging */
+#ifdef SYSIO_MEM_DEBUG
+#define	IO_MEMUSAGE
+#endif /* SYSIO_MEM_DEBUG */
+
+/*
+ * sysio sbus constant definitions.
+ */
+#define	NATURAL_REG_SIZE	0x8	/* 8 Bytes is Fusion reg size */
+#define	MIN_REG_SIZE		0x4	/* Smallest Fusion reg size */
+#define	OFF_SYSIO_CTRL_REG	0x10
+#define	SYSIO_CTRL_REG_SIZE	(NATURAL_REG_SIZE)
+#define	OFF_SBUS_CTRL_REG	0x2000
+#define	SBUS_CTRL_REG_SIZE	(NATURAL_REG_SIZE)
+#define	OFF_SBUS_SLOT_CONFIG	0x2020
+#define	SBUS_SLOT_CONFIG_SIZE	(NATURAL_REG_SIZE * 7)
+#define	OFF_INTR_MAPPING_REG	0x2c00
+/* #define	INTR_MAPPING_REG_SIZE	(NATURAL_REG_SIZE * 16 * 8)  */
+#define	INTR_MAPPING_REG_SIZE	0x490
+#define	OFF_CLR_INTR_REG	0x3408
+/* #define	CLR_INTR_REG_SIZE	(NATURAL_REG_SIZE * 16 * 8) */
+#define	CLR_INTR_REG_SIZE	0x488
+#define	OFF_INTR_RETRY_REG	0x2c20
+#define	INTR_RETRY_REG_SIZE	(MIN_REG_SIZE)
+#define	OFF_SBUS_INTR_STATE_REG	0x4800
+#define	SBUS_INTR_STATE_REG_SIZE (NATURAL_REG_SIZE * 2)
+#define	SYSIO_IGN		46
+#define	SBUS_ARBIT_ALL		0x3full
+#define	SYSIO_VER_SHIFT		56
+
+/* Error registers */
+#define	OFF_SYSIO_ECC_REGS	0x20
+#define	SYSIO_ECC_REGS_SIZE	NATURAL_REG_SIZE
+#define	OFF_SYSIO_UE_REGS	0x30
+#define	SYSIO_UE_REGS_SIZE	(NATURAL_REG_SIZE * 2)
+#define	OFF_SYSIO_CE_REGS	0x40
+#define	SYSIO_CE_REGS_SIZE	(NATURAL_REG_SIZE * 2)
+#define	OFF_SBUS_ERR_REGS	0x2010
+#define	SBUS_ERR_REGS_SIZE	(NATURAL_REG_SIZE * 2)
+
+/* Interrupts */
+#define	INTERRUPT_CPU_FIELD	26	/* Bit shift for mondo TID field */
+#define	INTERRUPT_GROUP_NUMBER	6	/* Bit shift for mondo IGN field */
+#define	INTERRUPT_VALID		0x80000000ull /* Mondo valid bit */
+#define	SBUS_INTR_IDLE		0ull
+#define	INT_PENDING 		3	/* state of the interrupt dispatch */
+/*
+ * Fix these (RAZ)
+ * Interrupt Mapping Register defines
+ */
+#define	IMR_VALID		0x80000000ull	/* Valid bit */
+#define	IMR_TID			0x7C000000ull	/* TID bits */
+#define	IMR_IGN			0x000007C0ull	/* IGN bits */
+#define	IMR_INO			0x0000003Full	/* INO bits */
+#define	IMR_TID_SHIFT		26		/* Bit shift for TID field */
+#define	IMR_IGN_SHIFT		6		/* Bit shift for IGN field */
+
+#define	MAX_SBUS		(30)
+#define	MAX_SBUS_LEVEL		(7)
+#define	MAX_SBUS_SLOTS	(7)		/* 4 external slots + 3 internal */
+#define	EXT_SBUS_SLOTS		4	/* Number of external sbus slots */
+#define	MAX_SBUS_SLOT_ADDR	0x10	/* Max slot address on SYSIO */
+#define	SYSIO_BURST_RANGE	(0x7f)	/* 32 bit: 64 Byte to 1 Byte burst */
+#define	SYSIO64_BURST_RANGE	(0x78)	/* 64 bit: 64 Byte to 8 Byte burst */
+#define	SYSIO_BURST_MASK	0xffff
+#define	SYSIO64_BURST_MASK	0xffff0000
+#define	SYSIO64_BURST_SHIFT	16
+#define	MAX_PIL			16
+
+/* Slot config register defines */
+#define	SBUS_ETM		0x4000ull
+#define	SYSIO_SLAVEBURST_MASK	0x1e	/* Mask for hardware register */
+#define	SYSIO_SLAVEBURST_RANGE	(0x78)	/* 32 bit: 64 Byte to 8 Byte burst */
+#define	SYSIO64_SLAVEBURST_RANGE (0x78)	/* 64 bit: 64 Byte to 8 Byte burst */
+#define	SYSIO_SLAVEBURST_REGSHIFT 2	/* Convert bit positions 2**8 to 2**1 */
+
+/*
+ * Offsets of sysio, sbus, registers
+ */
+/* Slot configuration register mapping offsets */
+#define	SBUS_SLOT0_CONFIG	0x0
+#define	SBUS_SLOT1_CONFIG	0x1
+#define	SBUS_SLOT2_CONFIG	0x2
+#define	SBUS_SLOT3_CONFIG	0x3
+#define	SBUS_SLOT4_CONFIG	0x4
+#define	SBUS_SLOT5_CONFIG	0x5
+#define	SBUS_SLOT6_CONFIG	0x6
+
+/* Interrupt mapping register mapping offsets */
+#define	SBUS_SLOT0_MAPREG	0x0
+#define	SBUS_SLOT1_MAPREG	0x1
+#define	SBUS_SLOT2_MAPREG	0x2
+#define	SBUS_SLOT3_MAPREG	0x3
+#define	ESP_MAPREG		0x80
+#define	ETHER_MAPREG		0x81
+#define	PP_MAPREG		0x82
+#define	AUDIO_MAPREG		0x83
+#define	KBDMOUSE_MAPREG		0x85
+#define	FLOPPY_MAPREG		0x86
+#define	THERMAL_MAPREG		0x87
+#define	TIMER0_MAPREG		0x8C
+#define	TIMER1_MAPREG		0x8D
+#define	UE_ECC_MAPREG		0x8E
+#define	CE_ECC_MAPREG		0x8F
+#define	SBUS_ERR_MAPREG		0x90
+#define	PM_WAKEUP_MAPREG	0x91
+#define	FFB_MAPPING_REG		0x92
+#define	EXP_MAPPING_REG		0x93
+
+/* Interrupt clear register mapping offsets */
+#define	SBUS_SLOT0_L1_CLEAR	0x0
+#define	SBUS_SLOT0_L2_CLEAR	0x1
+#define	SBUS_SLOT0_L3_CLEAR	0x2
+#define	SBUS_SLOT0_L4_CLEAR	0x3
+#define	SBUS_SLOT0_L5_CLEAR	0x4
+#define	SBUS_SLOT0_L6_CLEAR	0x5
+#define	SBUS_SLOT0_L7_CLEAR	0x6
+#define	SBUS_SLOT1_L1_CLEAR	0x8
+#define	SBUS_SLOT1_L2_CLEAR	0x9
+#define	SBUS_SLOT1_L3_CLEAR	0xa
+#define	SBUS_SLOT1_L4_CLEAR	0xb
+#define	SBUS_SLOT1_L5_CLEAR	0xc
+#define	SBUS_SLOT1_L6_CLEAR	0xd
+#define	SBUS_SLOT1_L7_CLEAR	0xe
+#define	SBUS_SLOT2_L1_CLEAR	0x10
+#define	SBUS_SLOT2_L2_CLEAR	0x11
+#define	SBUS_SLOT2_L3_CLEAR	0x12
+#define	SBUS_SLOT2_L4_CLEAR	0x13
+#define	SBUS_SLOT2_L5_CLEAR	0x14
+#define	SBUS_SLOT2_L6_CLEAR	0x15
+#define	SBUS_SLOT2_L7_CLEAR	0x16
+#define	SBUS_SLOT3_L1_CLEAR	0x18
+#define	SBUS_SLOT3_L2_CLEAR	0x19
+#define	SBUS_SLOT3_L3_CLEAR	0x1a
+#define	SBUS_SLOT3_L4_CLEAR	0x1b
+#define	SBUS_SLOT3_L5_CLEAR	0x1c
+#define	SBUS_SLOT3_L6_CLEAR	0x1d
+#define	SBUS_SLOT3_L7_CLEAR	0x1e
+#define	ESP_CLEAR		0x7f
+#define	ETHER_CLEAR		0x80
+#define	PP_CLEAR		0x81
+#define	AUDIO_CLEAR		0x82
+#define	KBDMOUSE_CLEAR		0x84
+#define	FLOPPY_CLEAR		0x85
+#define	THERMAL_CLEAR		0x86
+#define	TIMER0_CLEAR		0x8B
+#define	TIMER1_CLEAR		0x8C
+#define	UE_ECC_CLEAR		0x8D
+#define	CE_ECC_CLEAR		0x8E
+#define	SBUS_ERR_CLEAR		0x8F
+#define	PM_WAKEUP_CLEAR		0x90
+
+/*
+ * Bit shift for accessing the keyboard mouse interrupt state reg.
+ * note - The external devices are the only other devices where
+ * we need to check the interrupt state before adding or removing
+ * interrupts.  There is an algorithm to calculate their bit shift.
+ */
+#define	ESP_INTR_STATE_SHIFT		0
+#define	ETHER_INTR_STATE_SHIFT		2
+#define	PP_INTR_STATE_SHIFT		4
+#define	AUDIO_INTR_STATE_SHIFT		6
+#define	KBDMOUSE_INTR_STATE_SHIFT	10
+#define	FLOPPY_INTR_STATE_SHIFT		12
+#define	THERMAL_INTR_STATE_SHIFT	14
+#define	TIMER0_INTR_STATE_SHIFT		22
+#define	TIMER1_INTR_STATE_SHIFT		24
+#define	UE_INTR_STATE_SHIFT		26
+#define	CE_INTR_STATE_SHIFT		28
+#define	SERR_INTR_STATE_SHIFT		30
+#define	PM_INTR_STATE_SHIFT		32
+
+#define	MAX_INO_TABLE_SIZE	58	/* Max num of sbus devices on sysio */
+#define	MAX_MONDO_EXTERNAL	0x1f
+#define	SBUS_MAX_INO		0x3f
+#define	THERMAL_MONDO		0x2a
+#define	UE_ECC_MONDO		0x34
+#define	CE_ECC_MONDO		0x35
+#define	SBUS_ERR_MONDO		0x36
+
+/* used for the picN kstats */
+#define	SBUS_NUM_PICS	2
+#define	SBUS_NUM_EVENTS	14
+#define	SBUS_PIC0_MASK	0x00000000FFFFFFFFULL	/* pic0 bits of %pic */
+
+/* Offsets for Performance registers */
+#define	OFF_SBUS_PCR	0x100
+#define	OFF_SBUS_PIC	0x108
+
+/*
+ * used to build array of event-names and pcr-mask values
+ */
+typedef	struct	sbus_event_mask {
+	char	*event_name;
+	uint64_t pcr_mask;
+} sbus_event_mask_t;
+
+/*
+ * This type is used to describe addresses that we expect a device
+ * to place on a bus i.e. addresses from the iommu address space.
+ */
+typedef	uint32_t	ioaddr_t;
+
+
+/*
+ * sysio sbus soft state data structure.
+ * We use the sbus_ctrl_reg to flush hardware store buffers because
+ * there is very little hardware contention on this register.
+ */
+struct sbus_soft_state {
+	dev_info_t *dip;		/* dev info of myself */
+	int upa_id;			/* UPA ID of this SYSIO */
+
+	/*
+	 * device node address property:
+	 */
+	caddr_t address;
+
+	/*
+	 * access handles in case we need to map the registers ourself:
+	 */
+	ddi_acc_handle_t ac;
+
+	volatile uint64_t *iommu_flush_reg; /* IOMMU regs */
+	volatile uint64_t *iommu_ctrl_reg;
+	volatile uint64_t *tsb_base_addr;  /* Hardware reg for phys TSB base */
+	volatile uint64_t *soft_tsb_base_addr; /* virtual address of TSB base */
+	volatile uint64_t *iommu_tlb_tag;
+	volatile uint64_t *iommu_tlb_data;
+
+	size_t iommu_dvma_size;
+	ioaddr_t iommu_dvma_base;
+	uint16_t iommu_tsb_cookie;
+
+
+	volatile uint64_t *sysio_ctrl_reg;	/* sysio regs */
+	volatile uint64_t *sbus_ctrl_reg;   /* also used to flush store bufs */
+	volatile uint64_t *sbus_slot_config_reg;
+	uint_t sbus_slave_burstsizes[MAX_SBUS_SLOTS];
+
+	volatile uint64_t *intr_mapping_reg;	/* Interrupt regs */
+	volatile uint64_t *clr_intr_reg;
+	volatile uint64_t *intr_retry_reg;
+	volatile uint64_t *sbus_intr_state;
+	volatile uint64_t *obio_intr_state;
+	int8_t intr_hndlr_cnt[MAX_SBUS_SLOT_ADDR]; /* intmapreg cntr by slot */
+	uchar_t spurious_cntrs[MAX_PIL + 1];	/* Spurious intr counter */
+
+	volatile uint64_t *sysio_ecc_reg;	/* sysio ecc control reg */
+	volatile uint64_t *sysio_ue_reg;	/* sysio ue ecc error regs */
+	volatile uint64_t *sysio_ce_reg;	/* sysio ce ecc error regs */
+	volatile uint64_t *sbus_err_reg;	/* sbus async error regs */
+
+	volatile uint64_t *str_buf_ctrl_reg;	/* streaming buffer regs */
+	volatile uint64_t *str_buf_flush_reg;
+	volatile uint64_t *str_buf_sync_reg;
+	volatile uint64_t *str_buf_pg_tag_diag;
+	kmutex_t sync_reg_lock;			/* lock around sync flush reg */
+	int stream_buf_off;
+
+	uint_t sbus_burst_sizes;
+	uint_t sbus64_burst_sizes;
+
+	vmem_t *dvma_arena;		/* DVMA arena for this IOMMU */
+	uintptr_t dvma_call_list_id;	/* DVMA callback list */
+	kmutex_t dma_pool_lock;
+	caddr_t dmaimplbase;		/* dma_pool_lock protects this */
+	int	dma_reserve;		/* Size reserved for fast DVMA */
+
+	struct sbus_wrapper_arg *intr_list[MAX_INO_TABLE_SIZE];
+	kmutex_t intr_poll_list_lock;	/* to add/rem to intr poll list */
+	kmutex_t pokefault_mutex;	/* mutex for pokefaults */
+	on_trap_data_t *ontrap_data;	/* Data used to handle poke faults */
+	hrtime_t bto_timestamp;		/* time of first timeout */
+	int bto_ctr;			/* counter for timeouts thereafter */
+	pfn_t sbus_io_lo_pfn;
+	pfn_t sbus_io_hi_pfn;
+	struct iophyslist *sbus_io_ranges;
+	int intr_mapping_ign;		/* placeholder for the IGN */
+#ifdef	_STARFIRE
+	caddr_t ittrans_cookie;		/* starfire intr target translation */
+#endif	/* _STARFIRE */
+#ifdef	DEBUG
+	kmutex_t iomemlock;		/* Memory usage lock (debug only) */
+	struct io_mem_list *iomem;	/* Memory usage list (debug only) */
+#endif /* DEBUG */
+	/*
+	 * Performance registers and kstat.
+	 */
+	volatile uint64_t *sbus_pcr;	/* perf counter control */
+	volatile uint64_t *sbus_pic; 	/* perf counter register */
+	kstat_t	*sbus_counters_ksp;	/* perf counter kstat */
+};
+
+
+/*
+ * Ugly interrupt cruft due to sysio inconsistencies.
+ */
+struct sbus_slot_entry {
+	uint64_t slot_config;
+	uint64_t mapping_reg;
+	uint64_t clear_reg;
+	int diagreg_shift;
+};
+
+struct sbus_intr_handler {
+	dev_info_t *dip;
+	uint32_t inum;
+	uint_t (*funcp)();
+	caddr_t arg1;
+	caddr_t arg2;
+	uint_t	intr_state;
+	struct sbus_intr_handler *next;
+};
+
+/* sbus Interrupt routine wrapper structure */
+struct sbus_wrapper_arg {
+	struct sbus_soft_state *softsp;
+	volatile uint64_t *clear_reg;
+	uint32_t pil;
+	struct sbus_intr_handler *handler_list;
+};
+
+
+/*
+ * SYSIO parent private data structure contains register, interrupt, property
+ * and range information.
+ * Note: the only thing different from the "generic" sbus parent private
+ * data is the interrupt specification.
+ */
+struct sysio_parent_private_data {
+	int par_nreg;			/* number of regs */
+	struct regspec *par_reg;	/* array of regs */
+	int par_nintr;			/* number of interrupts */
+	struct sysiointrspec *par_intr;	/* array of possible interrupts */
+	int par_nrng;			/* number of ranges */
+	struct rangespec *par_rng;	/* array of ranges */
+	uint_t slot;			/* Slot number, on this sbus */
+	uint_t offset;			/* Offset of first real "reg" */
+};
+#define	SYSIO_PD(d)	\
+	((struct sysio_parent_private_data *)DEVI((d))->devi_parent_data)
+
+#define	sysio_pd_getnreg(dev)		(SYSIO_PD(dev)->par_nreg)
+#define	sysio_pd_getnintr(dev)		(SYSIO_PD(dev)->par_nintr)
+#define	sysio_pd_getnrng(dev)		(SYSIO_PD(dev)->par_nrng)
+#define	sysio_pd_getslot(dev)		(SYSIO_PD(dev)->slot)
+#define	sysio_pd_getoffset(dev)		(SYSIO_PD(dev)->offset)
+
+#define	sysio_pd_getreg(dev, n)		(&SYSIO_PD(dev)->par_reg[(n)])
+#define	sysio_pd_getintr(dev, n)	(&SYSIO_PD(dev)->par_intr[(n)])
+#define	sysio_pd_getrng(dev, n)		(&SYSIO_PD(dev)->par_rng[(n)])
+
+#define	IS_INTRA_SBUS(softsp, pfn)	(pfn >= softsp->sbus_io_lo_pfn && \
+					    pfn <= softsp->sbus_io_hi_pfn)
+
+/* Used for legacy interrupts */
+#define	SBUS_INTR_STATE_DISABLE		0	/* disabled */
+#define	SBUS_INTR_STATE_ENABLE		1	/* enabled */
+
+struct io_mem_list {
+	dev_info_t *rdip;
+	ulong_t	ioaddr;
+	ulong_t	addr;
+	pgcnt_t npages;
+	pfn_t *pfn;
+	struct io_mem_list *next;
+};
+
+/*
+ * Function prototypes.
+ */
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_SYSIOSBUS_H */
diff --git a/usr/src/uts/sun4u/sys/todds1287.h b/usr/src/uts/sun4u/sys/todds1287.h
new file mode 100644
index 0000000000..e4e1c01396
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/todds1287.h
@@ -0,0 +1,190 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 1999-2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_TODDS1287_H
+#define	_TODDS1287_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+extern  char    *v_rtc_addr_reg;
+extern  volatile uint8_t *v_rtc_data_reg;
+
+#ifdef	DEBUG
+#include <sys/promif.h>
+#define	DPRINTF if (ds1287_debug_flags) prom_printf
+#else
+#define	DPRINTF
+#endif	/* DEBUG */
+
+#define	DS1287_ADDR_REG		*(volatile uint8_t *)v_rtc_addr_reg
+#define	DS1287_DATA_REG		*(volatile uint8_t *)v_rtc_data_reg
+
+/*
+ * Maximum number of clones
+ */
+#define	DS1287_MAX_CLONE	256
+
+/*
+ * Minor number is instance << 8 + clone minor from range 1-255; clone 0 is
+ * reserved for the "original".
+ */
+#define	DS1287_MINOR_TO_CLONE(minor) ((minor) & (DS1287_MAX_CLONE - 1))
+
+struct ds1287 {
+	dev_info_t	*dip;		/* device info pointer */
+	kmutex_t	ds1287_mutex;	/* mutex lock */
+	uchar_t		clones[DS1287_MAX_CLONE]; /* array of clones */
+	int		monitor_on;	/* clone monitoring the button event */
+					/* clone 0 is used to indicate no one */
+					/* is monitoring the button event */
+	pollhead_t	pollhd;		/* poll head struct */
+	int		events;		/* bit map of occured events */
+	int		shutdown_pending; /* system shutdown in progress */
+};
+
+
+/*
+ * Definitions for Real Time Clock driver (Dallas DS1287 chip).
+ */
+
+/*
+ * Common registers between Banks 0, 1, and 2.
+ */
+#define	RTC_SEC		0x0	/* Seconds */
+#define	RTC_ASEC	0x1	/* Seconds Alarm */
+#define	RTC_MIN		0x2	/* Minutes */
+#define	RTC_AMIN	0x3	/* Minutes Alarm */
+#define	RTC_HRS		0x4	/* Hours */
+#define	RTC_AHRS	0x5	/* Hours Alarm */
+#define	RTC_DOW		0x6	/* Day-of-Week */
+#define	RTC_DOM		0x7	/* Day-of-Month */
+#define	RTC_MON		0x8	/* Month */
+#define	RTC_YEAR	0x9	/* Year */
+#define	RTC_A		0xa	/* Control Register A */
+#define	RTC_B		0xb	/* Control Register B */
+#define	RTC_C		0xc	/* Control Register C */
+#define	RTC_D		0xd	/* Control Register D */
+
+/*
+ * Control register A definitions
+ */
+#define	RTC_DIV0	0x10	/* Bank Select */
+#define	RTC_DIV1	0x20	/* Oscillator enable */
+#define	RTC_DIV2	0x40	/* Countdown chain */
+#define	RTC_UIP		0x80	/* Update in progress bit */
+
+/*
+ * Control register B definitions
+ */
+#define	RTC_DSE		0x01	/* Daylight Savings Enable */
+#define	RTC_HM		0x02	/* Hour mode, 1 = 24 hour, 0 = 12 hour */
+#define	RTC_DM		0x04	/* Date mode, 1 = binary, 0 = BCD */
+#define	RTC_UIE		0x10	/* Update-ended Interrupt Enable */
+#define	RTC_AIE		0x20	/* Alarm Interrupt Enable */
+#define	RTC_PIE		0x40	/* Periodic Interrupt Enable */
+#define	RTC_SET		0x80	/* Stop updates for time set */
+
+/*
+ * Control Register C definitions
+ */
+#define	RTC_UF		0x10	/* UF flag bit */
+#define	RTC_AF		0x20	/* AF flag bit */
+#define	RTC_PF		0x40	/* PF flag bit */
+#define	RTC_IRQF	0x80	/* IRQ flag */
+
+/*
+ * Control Register D definitions
+ */
+#define	RTC_VRT		0x80	/* Valid RAM and time bit */
+
+/*
+ * Bank 1 Registers
+ */
+#define	RTC_CENTURY	0x48	/* Century */
+#define	RTC_ADOM	0x49	/* Date of Month Alarm */
+#define	RTC_AMON	0x4a	/* Month Alarm */
+
+/*
+ * Bank 2 Registers
+ */
+#define	APC_APCR1	0x40	/* APC Control Register 1 */
+#define	APC_APCR2	0x41	/* APC Control Register 2 */
+#define	APC_APSR	0x42	/* APC Status Register */
+#define	APC_WDWR	0x43	/* Wake up Day of Week */
+#define	APC_WDMR	0x44	/* Wake up Date of Month */
+#define	APC_WMR		0x45	/* Wake up Month */
+#define	APC_WYR		0x46	/* Wake up Year */
+#define	APC_WCR		0x48	/* Wake up Century */
+
+#define	RTC_CADDR	0x51	/* Century address register */
+
+/*
+ * APC Control Register 1 (APCR1) definitions
+ */
+#define	APC_FSTRC	0x40	/* Fail-safe Timer Reset Command */
+
+/*
+ * APC Control Register 2 (APCR2) definitions
+ */
+#define	APC_TME		0x01	/* Timer Match Enable */
+
+struct	rtc_t {
+	uint8_t	rtc_sec;	/* seconds */
+	uint8_t	rtc_asec;	/* alarm seconds */
+	uint8_t	rtc_min;	/* mins */
+	uint8_t	rtc_amin;	/* alarm mins */
+	uint8_t	rtc_hrs;	/* hours */
+	uint8_t	rtc_ahrs;	/* alarm hours */
+	uint8_t	rtc_dow;	/* day of the week */
+	uint8_t	rtc_dom;	/* day of the month */
+	uint8_t	rtc_mon;	/* month */
+	uint8_t	rtc_year;	/* year */
+	uint8_t	rtc_rega;	/* REG A */
+	uint8_t	rtc_regb;	/* REG B */
+	uint8_t	rtc_regc;	/* REG C */
+	uint8_t	rtc_regd;	/* REG D */
+	uint8_t	rtc_century;	/* century */
+	uint8_t	rtc_adom;	/* alarm  day */
+	uint8_t	rtc_amon;	/* alarm  mon */
+	uint8_t	apc_apcr1;	/* APC Control register 1 */
+	uint8_t	apc_apcr2;	/* APC Control register 2 */
+	uint8_t	apc_apsr;	/* APC Status register */
+	uint8_t	apc_wdwr;	/* Wakeup date of the month */
+	uint8_t	apc_wdmr;	/* Wakeup day of month */
+	uint8_t	apc_wmr;	/* Wakeup month register */
+	uint8_t	apc_wyr;	/* Wakeup year register */
+	uint8_t	apc_wcr;	/* Wakeup Century reg. */
+};
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _TODDS1287_H */
diff --git a/usr/src/uts/sun4u/sys/todds1337.h b/usr/src/uts/sun4u/sys/todds1337.h
new file mode 100644
index 0000000000..2fa0101708
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/todds1337.h
@@ -0,0 +1,129 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_TODDS1337_H
+#define	_TODDS1337_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/cyclic.h>
+#include <sys/i2c/clients/i2c_client.h>
+
+extern char	*v_rtc_addr_reg;
+extern volatile uint8_t	*v_rtc_data_reg;
+
+#define	DS1337_ADDR_REG		*(volatile uint8_t *)v_rtc_addr_reg
+#define	DS1337_DATA_REG		*(volatile uint8_t *)v_rtc_data_reg
+#define	DS1337_NODE_TYPE	"ddi_i2c:tod"
+
+struct rtc_t {
+	uint8_t		rtc_sec;	/* Seconds[0-60] */
+	uint8_t		rtc_min;	/* Minutes[0-60] */
+	uint8_t		rtc_hrs;	/* Hours[(1-12)/(0-23)] */
+	uint8_t		rtc_dow;	/* Day of week[1-7] */
+	uint8_t		rtc_dom;	/* Day of month[(1-28/29/30/31)] */
+	uint8_t		rtc_mon;	/* Month[1-12] */
+	uint8_t		rtc_year;	/* Year[00-99] */
+	uint8_t		rtc_asec;	/* Alarm #1 seconds */
+	uint8_t		rtc_amin;	/* Alarm #1 minutes */
+	uint8_t		rtc_ahrs;	/* Alarm #1 hours   */
+	uint8_t		rtc_aday;	/* Alarm #1 day [month/week] */
+	uint8_t		rtc_a2min;	/* Alarm #2 minutes */
+	uint8_t		rtc_a2hrs;	/* Alarm #2 hours   */
+	uint8_t		rtc_a2day;	/* Alarm #2 day [month/week] */
+	uint8_t		rtc_ctl;	/* DS1337 Control register */
+	uint8_t		rtc_status;	/* DS1337 Status register  */
+};
+
+
+/*
+ * Register definitions for RTC driver (DS1337 chip)
+ */
+
+#define	RTC_SEC		0x00	/* 00h Second */
+#define	RTC_MIN		0x01	/* 01h Minutes */
+#define	RTC_HRS		0x02	/* 02h Hours */
+#define	RTC_DOW		0x03	/* 03h Day-of-week */
+#define	RTC_DOM		0x04	/* 04h Day-of-month */
+#define	RTC_MON		0x05	/* 05h Month */
+#define	RTC_YEAR	0x06	/* 06h Year */
+#define	RTC_ALARM_SEC	0x07	/* 07h Alarm #1 Second  */
+#define	RTC_ALARM_MIN	0x08	/* 08h Alarm #1 Minutes */
+#define	RTC_ALARM_HRS	0x09	/* 09h Alarm #1 Hours   */
+#define	RTC_ALARM_DAY	0x0a	/* 0Ah Alarm #1 Day [month/week] */
+#define	RTC_CTL		0x0e	/* 0Eh Control register */
+#define	RTC_STATUS	0x0f	/* 0Fh Status register  */
+
+#define	RTC_DYDT_MASK	0x40
+
+/*
+ * Control register definitions
+ */
+
+#define	RTC_CTL_EOSC	0x80	/* Active low */
+#define	RTC_CTL_RS2	0x10
+#define	RTC_CTL_RS1	0x08
+#define	RTC_CTL_INTCN	0x04
+#define	RTC_CTL_A2IE	0x02
+#define	RTC_CTL_A1IE	0x01
+
+
+/*
+ * Status register definitions
+ */
+
+#define	RTC_STATUS_OSF	0x80
+#define	RTC_STATUS_A2F	0x02
+#define	RTC_STATUS_A1F	0x01
+
+/* per instance based */
+
+#define	TOD_DETACHED		0x00	/* TOD detached */
+#define	TOD_ATTACHED		0x01	/* TOD attached */
+
+typedef struct ds1337_state {
+	i2c_client_hdl_t	ds1337_i2c_hdl;
+	char			i2ctod_name[MAXNAMELEN];  /* node name */
+	kmutex_t		i2ctod_mutex;   /* protects soft state */
+	int			instance;
+	dev_info_t		*dip;
+	uint32_t		state;
+	cyclic_id_t		cycid;
+	struct rtc_t		rtc;
+	i2c_transfer_t		*i2c_tp;
+	ddi_softintr_t   	soft_intr_id;
+	uint32_t		progress;
+}ds1337_state_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _TODDS1337_H */
diff --git a/usr/src/uts/sun4u/sys/todm5819.h b/usr/src/uts/sun4u/sys/todm5819.h
new file mode 100644
index 0000000000..1e964e034e
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/todm5819.h
@@ -0,0 +1,176 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2001-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_TODM5819_H
+#define	_TODM5819_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+extern  char    *v_rtc_addr_reg;
+extern  volatile uint8_t *v_rtc_data_reg;
+
+#ifdef	DEBUG
+#include <sys/promif.h>
+#define	DPRINTF if (m5819_debug_flags) prom_printf
+#else
+#define	DPRINTF
+#endif	/* DEBUG */
+
+#define	M5819_ADDR_REG		*(volatile uint8_t *)v_rtc_addr_reg
+#define	M5819_DATA_REG		*(volatile uint8_t *)v_rtc_data_reg
+
+
+/*
+ * Definitions for Real Time Clock driver (m5819 chip).
+ */
+
+/*
+ * Common registers between Banks 0, 1, and 2.
+ */
+#define	RTC_SEC		0x0	/* Seconds */
+#define	RTC_ASEC	0x1	/* Seconds Alarm */
+#define	RTC_MIN		0x2	/* Minutes */
+#define	RTC_AMIN	0x3	/* Minutes Alarm */
+#define	RTC_HRS		0x4	/* Hours */
+#define	RTC_AHRS	0x5	/* Hours Alarm */
+#define	RTC_DOW		0x6	/* Day-of-Week */
+#define	RTC_DOM		0x7	/* Day-of-Month */
+#define	RTC_MON		0x8	/* Month */
+#define	RTC_YEAR	0x9	/* Year */
+#define	RTC_A		0xa	/* Control Register A */
+#define	RTC_B		0xb	/* Control Register B */
+#define	RTC_C		0xc	/* Control Register C */
+#define	RTC_D		0xd	/* Control Register D */
+#define	RTC_CENTURY	0x32	/* Century */
+
+/*
+ * Control register A definitions
+ */
+#define	RTC_DIV0	0x10	/* Bank Select */
+#define	RTC_DIV1	0x20	/* Oscillator enable */
+#define	RTC_DIV2	0x40	/* Countdown chain */
+#define	RTC_UIP		0x80	/* Update in progress bit */
+
+/*
+ * Control register B definitions
+ */
+#define	RTC_DSE		0x01	/* Daylight Savings Enable */
+#define	RTC_HM		0x02	/* Hour mode, 1 = 24 hour, 0 = 12 hour */
+#define	RTC_DM		0x04	/* Date mode, 1 = binary, 0 = BCD */
+#define	RTC_UIE		0x10	/* Update-ended Interrupt Enable */
+#define	RTC_AIE		0x20	/* Alarm Interrupt Enable */
+#define	RTC_PIE		0x40	/* Periodic Interrupt Enable */
+#define	RTC_SET		0x80	/* Stop updates for time set */
+
+/*
+ * Control Register C definitions
+ */
+#define	RTC_UF		0x10	/* UF flag bit */
+#define	RTC_AF		0x20	/* AF flag bit */
+#define	RTC_PF		0x40	/* PF flag bit */
+#define	RTC_IRQF	0x80	/* IRQ flag */
+
+/*
+ * Control Register D definitions
+ */
+#define	RTC_VRT		0x80	/* Valid RAM and time bit */
+
+
+/*
+ * Bank 2 Registers
+ */
+#define	APC_APCR1	0x40	/* APC Control Register 1 */
+#define	APC_APCR2	0x41	/* APC Control Register 2 */
+#define	APC_APSR	0x42	/* APC Status Register */
+#define	APC_WDWR	0x43	/* Wake up Day of Week */
+#define	APC_WDMR	0x44	/* Wake up Date of Month */
+#define	APC_WMR		0x45	/* Wake up Month */
+#define	APC_WYR		0x46	/* Wake up Year */
+#define	APC_WCR		0x48	/* Wake up Century */
+
+#define	RTC_CADDR	0x51	/* Century address register */
+
+/*
+ * APC Control Register 1 (APCR1) definitions
+ */
+#define	APC_FSTRC	0x40	/* Fail-safe Timer Reset Command */
+
+/*
+ * APC Control Register 2 (APCR2) definitions
+ */
+#define	APC_TME		0x01	/* Timer Match Enable */
+
+/*
+ * The following two defintions are used in conjuction to wait
+ * for the UIP bit to clear.
+ */
+#define	TODM5819_UIP_RETRY_THRESH 6
+#define	TODM5819_UIP_WAIT_USEC 56
+
+
+struct	rtc_t {
+	uint8_t	rtc_sec;	/* seconds */
+	uint8_t	rtc_asec;	/* alarm seconds */
+	uint8_t	rtc_min;	/* mins */
+	uint8_t	rtc_amin;	/* alarm mins */
+	uint8_t	rtc_hrs;	/* hours */
+	uint8_t	rtc_ahrs;	/* alarm hours */
+	uint8_t	rtc_dow;	/* day of the week */
+	uint8_t	rtc_dom;	/* day of the month */
+	uint8_t	rtc_mon;	/* month */
+	uint8_t	rtc_year;	/* year */
+	uint8_t	rtc_rega;	/* REG A */
+	uint8_t	rtc_regb;	/* REG B */
+	uint8_t	rtc_regc;	/* REG C */
+	uint8_t	rtc_regd;	/* REG D */
+	uint8_t	rtc_century;	/* century */
+	uint8_t	rtc_adom;	/* alarm  day */
+	uint8_t	rtc_amon;	/* alarm  mon */
+	uint8_t	apc_apcr1;	/* APC Control register 1 */
+	uint8_t	apc_apcr2;	/* APC Control register 2 */
+	uint8_t	apc_apsr;	/* APC Status register */
+	uint8_t	apc_wdwr;	/* Wakeup date of the month */
+	uint8_t	apc_wdmr;	/* Wakeup day of month */
+	uint8_t	apc_wmr;	/* Wakeup month register */
+	uint8_t	apc_wyr;	/* Wakeup year register */
+	uint8_t	apc_wcr;	/* Wakeup Century reg. */
+};
+
+
+#define	RTC_GET8(offset) (M5819_ADDR_REG = (offset), M5819_DATA_REG)
+#define	RTC_PUT8(offset, value) (	\
+	M5819_ADDR_REG = (offset),	\
+	M5819_DATA_REG = (value))
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _TODM5819_H */
diff --git a/usr/src/uts/sun4u/sys/todm5819p.h b/usr/src/uts/sun4u/sys/todm5819p.h
new file mode 100644
index 0000000000..51733e087f
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/todm5819p.h
@@ -0,0 +1,136 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2002-2003 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_TODM5819P_H
+#define	_TODM5819P_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+extern  char    *v_rtc_addr_reg;
+extern  volatile uint8_t *v_rtc_data_reg;
+
+#ifdef	DEBUG
+#include <sys/promif.h>
+#define	DPRINTF if (m5819p_debug_flags) prom_printf
+#else
+#define	DPRINTF
+#endif /* DEBUG */
+
+#define	M5819P_ADDR_REG		*(volatile uint8_t *)v_rtc_addr_reg
+#define	M5819P_DATA_REG		*(volatile uint8_t *)v_rtc_data_reg
+
+/*
+ * Definitions for Real Time Clock driver (ALI M5819P chip).
+ */
+#define	RTC_SEC		0x0	/* Seconds */
+#define	RTC_ASEC	0x1	/* Seconds Alarm */
+#define	RTC_MIN		0x2	/* Minutes */
+#define	RTC_AMIN	0x3	/* Minutes Alarm */
+#define	RTC_HRS		0x4	/* Hours */
+#define	RTC_AHRS	0x5	/* Hours Alarm */
+#define	RTC_DOW		0x6	/* Day-of-Week */
+#define	RTC_DOM		0x7	/* Day-of-Month */
+#define	RTC_MON		0x8	/* Month */
+#define	RTC_YEAR	0x9	/* Year */
+#define	RTC_CENTURY	0x32	/* Century */
+
+
+#define	RTC_A		0xa	/* Control Register A */
+#define	RTC_B		0xb	/* Control Register B */
+#define	RTC_C		0xc	/* Control Register C */
+#define	RTC_D		0xd	/* Control Register D */
+
+/*
+ * Control register A definitions
+ */
+#define	RTC_RS		0x0f	/* Rate select for periodic interrupt */
+#define	RTC_DIV		0x70	/* Divider control */
+#define	RTC_UIP		0x80	/* Update in progress bit */
+
+#define	RTC_DIV_OPERATE	0x50	/* dividor value for operate mode */
+
+/*
+ * Control register B definitions
+ */
+#define	RTC_DSE		0x01	/* Daylight Savings Enable */
+#define	RTC_HM		0x02	/* Hour mode, 1 = 24 hour, 0 = 12 hour */
+#define	RTC_DM		0x04	/* Date mode, 1 = binary, 0 = BCD */
+#define	RTC_UIE		0x10	/* Update-ended Interrupt Enable */
+#define	RTC_AIE		0x20	/* Alarm Interrupt Enable */
+#define	RTC_PIE		0x40	/* Periodic Interrupt Enable */
+#define	RTC_SET		0x80	/* Stop updates for time set */
+
+/*
+ * Control Register C definitions
+ */
+#define	RTC_UF		0x10	/* UF flag bit */
+#define	RTC_AF		0x20	/* AF flag bit */
+#define	RTC_PF		0x40	/* PF flag bit */
+#define	RTC_IRQF	0x80	/* IRQ flag */
+
+/*
+ * Control Register D definitions
+ */
+#define	RTC_ADOM_REG	RTC_D
+#define	RTC_ADOM	0x3f	/*  Day-of-Month Alarm */
+
+
+/*
+ * The following two definitions are used in conjunction to wait
+ * for the UIP bit to clear.
+ */
+#define	TODM5819_UIP_RETRY_THRESH	6
+#define	TODM5819_UIP_WAIT_USEC		56
+
+
+struct	rtc_t {
+	uint8_t	rtc_sec;	/* seconds */
+	uint8_t	rtc_asec;	/* alarm seconds */
+	uint8_t	rtc_min;	/* mins */
+	uint8_t	rtc_amin;	/* alarm mins */
+	uint8_t	rtc_hrs;	/* hours */
+	uint8_t	rtc_ahrs;	/* alarm hours */
+	uint8_t	rtc_dow;	/* day of the week */
+	uint8_t	rtc_dom;	/* day of the month */
+	uint8_t	rtc_mon;	/* month */
+	uint8_t	rtc_year;	/* year */
+	uint8_t	rtc_rega;	/* REG A */
+	uint8_t	rtc_regb;	/* REG B */
+	uint8_t	rtc_regc;	/* REG C */
+	uint8_t	rtc_regd;	/* REG D */
+	uint8_t	rtc_century;	/* century */
+	uint8_t	rtc_adom;	/* alarm  day */
+};
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _TODM5819P_H */
diff --git a/usr/src/uts/sun4u/sys/todm5823.h b/usr/src/uts/sun4u/sys/todm5823.h
new file mode 100644
index 0000000000..e7c5974978
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/todm5823.h
@@ -0,0 +1,141 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_TODM5823_H
+#define	_TODM5823_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+extern  char	*v_rtc_addr_reg;
+extern  volatile uint8_t	*v_rtc_data_reg;
+
+#ifdef	DEBUG
+#include <sys/promif.h>
+#define	DPRINTF if (m5823_debug_flags) prom_printf
+#else
+#define	DPRINTF
+#endif	/* DEBUG */
+
+#define	M5823_ADDR_BANK0_REG	*(volatile uint8_t *)v_rtc_addr_reg
+#define	M5823_DATA_BANK0_REG	*v_rtc_data_reg
+#define	M5823_ADDR_BANK1_REG	*((volatile uint8_t *)v_rtc_addr_reg + 2)
+#define	M5823_DATA_BANK1_REG	*(v_rtc_data_reg + 2)
+
+/*
+ * Definitions for Real Time Clock driver (ALI M5823 chip).
+ */
+#define	RTC_SEC		0x0	/* Seconds */
+#define	RTC_ASEC	0x1	/* Seconds Alarm */
+#define	RTC_MIN		0x2	/* Minutes */
+#define	RTC_AMIN	0x3	/* Minutes Alarm */
+#define	RTC_HRS		0x4	/* Hours */
+#define	RTC_AHRS	0x5	/* Hours Alarm */
+#define	RTC_DOW		0x6	/* Day-of-Week */
+#define	RTC_DOM		0x7	/* Day-of-Month */
+#define	RTC_MON		0x8	/* Month */
+#define	RTC_YEAR	0x9	/* Year */
+#define	RTC_CENTURY	0x32	/* Century */
+
+#define	RTC_AMON	0x7c	/* Month Alarm Bank 1 */
+#define	RTC_AWEK	0x7d	/* Week Alarm Bank 1 */
+
+#define	RTC_A		0xa	/* Control Register A */
+#define	RTC_B		0xb	/* Control Register B */
+#define	RTC_C		0xc	/* Control Register C */
+#define	RTC_D		0xd	/* Control Register D */
+
+/*
+ * Control register A definitions
+ */
+#define	RTC_RS		0x0f	/* Rate select for periodic interrupt */
+#define	RTC_DIV		0x70	/* Divider control */
+#define	RTC_UIP		0x80	/* Update in progress bit */
+
+#define	RTC_DIV_OPERATE	0x50	/* dividor value for operate mode */
+
+/*
+ * Control register B definitions
+ */
+#define	RTC_DSE		0x01	/* Daylight Savings Enable */
+#define	RTC_HM		0x02	/* Hour mode, 1 = 24 hour, 0 = 12 hour */
+#define	RTC_DM		0x04	/* Date mode, 1 = binary, 0 = BCD */
+#define	RTC_UIE		0x10	/* Update-ended Interrupt Enable */
+#define	RTC_AIE		0x20	/* Alarm Interrupt Enable */
+#define	RTC_PIE		0x40	/* Periodic Interrupt Enable */
+#define	RTC_SET		0x80	/* Stop updates for time set */
+
+/*
+ * Control Register C definitions
+ */
+#define	RTC_UF		0x10	/* UF flag bit */
+#define	RTC_AF		0x20	/* AF flag bit */
+#define	RTC_PF		0x40	/* PF flag bit */
+#define	RTC_IRQF	0x80	/* IRQ flag */
+
+/*
+ * Control Register D definitions
+ */
+#define	RTC_ADOM_REG	RTC_D
+#define	RTC_ADOM	0x3f	/*  Day-of-Month Alarm */
+
+/*
+ * The following two defintions are used in conjuction to wait
+ * for the UIP bit to clear. UIP  bit is set 274 usec before the
+ * update and remains set for 336 usec.
+ */
+#define	TODM5823_UIP_RETRY_THRESH 134
+#define	TODM5823_UIP_WAIT_USEC 5
+
+struct	rtc_t {
+	uint8_t	rtc_sec;	/* seconds */
+	uint8_t	rtc_asec;	/* alarm seconds */
+	uint8_t	rtc_min;	/* mins */
+	uint8_t	rtc_amin;	/* alarm mins */
+	uint8_t	rtc_hrs;	/* hours */
+	uint8_t	rtc_ahrs;	/* alarm hours */
+	uint8_t	rtc_dow;	/* day of the week */
+	uint8_t	rtc_dom;	/* day of the month */
+	uint8_t	rtc_mon;	/* month */
+	uint8_t	rtc_year;	/* year */
+	uint8_t	rtc_rega;	/* REG A */
+	uint8_t	rtc_regb;	/* REG B */
+	uint8_t	rtc_regc;	/* REG C */
+	uint8_t	rtc_regd;	/* REG D */
+	uint8_t	rtc_century;	/* century */
+	uint8_t	rtc_adom;	/* alarm  day */
+	uint8_t rtc_amon;	/* alarm month */
+	uint8_t rtc_awek;	/* alarm week */
+};
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _TODM5823_H */
diff --git a/usr/src/uts/sun4u/sys/todmostek.h b/usr/src/uts/sun4u/sys/todmostek.h
new file mode 100644
index 0000000000..2a70d393a6
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/todmostek.h
@@ -0,0 +1,111 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 1997-1998 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _TODMOSTEK_H
+#define	_TODMOSTEK_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+extern caddr_t v_eeprom_addr;
+extern caddr_t v_timecheck_addr;
+
+#define	V_TOD_OFFSET		0x1FF0
+#define	V_TODCLKADDR		(v_eeprom_addr+V_TOD_OFFSET)
+#define	V_TIMECHECKADDR		(v_timecheck_addr+V_TOD_OFFSET)
+
+/*
+ * Definitions for the Mostek 48T59 clock chip. We use this chip as
+ * our TOD clock. Clock interrupts are generated by a separate timer
+ * circuit.
+ */
+
+#define	YRBASE		68	/* 1968 - what year 0 in chip represents */
+
+#ifndef _ASM
+struct mostek48T59 {
+	volatile uchar_t clk_flags;	/* flags register */
+	volatile uchar_t clk_unused;	/* unused */
+	volatile uchar_t clk_alm_secs;	/* alarm - seconds 0-59 */
+	volatile uchar_t clk_alm_mins;	/* alarm - minutes 0-59 */
+	volatile uchar_t clk_alm_hours;	/* alarm - hours 0-23 */
+	volatile uchar_t clk_alm_day;	/* alarm - day 1-31 */
+	volatile uchar_t clk_interrupts; /* interrupts register */
+	volatile uchar_t clk_watchdog;	/* watchdog register */
+	volatile uchar_t clk_ctrl;	/* ctrl register */
+	volatile uchar_t clk_sec;	/* counter - seconds 0-59 */
+	volatile uchar_t clk_min;	/* counter - minutes 0-59 */
+	volatile uchar_t clk_hour;	/* counter - hours 0-23 */
+	volatile uchar_t clk_weekday;	/* counter - weekday 1-7 */
+	volatile uchar_t clk_day;	/* counter - day 1-31 */
+	volatile uchar_t clk_month;	/* counter - month 1-12 */
+	volatile uchar_t clk_year;	/* counter - year 0-99 */
+};
+
+#define	CLOCK ((struct mostek48T59 *)(V_TODCLKADDR))
+#define	TIMECHECK_CLOCK ((struct mostek48T59 *)(V_TIMECHECKADDR))
+
+#endif	/* _ASM */
+
+/*
+ * Bit masks for various operations and register limits.
+ */
+#define	CLK_CTRL_WRITE		0x80
+#define	CLK_CTRL_READ		0x40
+#define	CLK_CTRL_SIGN		0x20
+
+#define	CLK_STOP		0x80
+#define	CLK_KICK		0x80
+#define	CLK_FREQT		0x40
+
+#define	CLK_MONTH_MASK		0x1f
+#define	CLK_DAY_MASK		0x3f
+#define	CLK_WEEKDAY_MASK	0x07
+#define	CLK_HOUR_MASK		0x3f
+#define	CLK_MIN_MASK		0x7f
+#define	CLK_SEC_MASK		0x7f
+
+#define	CLK_ALARM_ENABLE	0xa0
+
+/*
+ * If the passed in time is non-zero, enable the watchdog and set the scale
+ * to seconds
+ */
+#define	CLK_WATCHDOG_ENABLE	0x80
+#define	CLK_WATCHDOG_1SEC	0x02
+#define	CLK_WATCHDOG_TMASK	0x1f
+#define	CLK_WATCHDOG_BITS(n)	(((n) & CLK_WATCHDOG_TMASK) ? \
+				((((n) & CLK_WATCHDOG_TMASK) << 2) | \
+				CLK_WATCHDOG_ENABLE | CLK_WATCHDOG_1SEC) : 0)
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* !_TODMOSTEK_H */
diff --git a/usr/src/uts/sun4u/sys/traptrace.h b/usr/src/uts/sun4u/sys/traptrace.h
new file mode 100644
index 0000000000..9bf2076229
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/traptrace.h
@@ -0,0 +1,435 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_TRAPTRACE_H
+#define	_SYS_TRAPTRACE_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Trap tracing. If TRAPTRACE is defined, every trap records info
+ * in a circular buffer.  Define TRAPTRACE in Makefile.$ARCH.
+ *
+ * Trap trace records are TRAP_ENT_SIZE bytes, consisting of the
+ * %tick, %tl, %tt, %tpc, %tstate, %sp, and a few other words:
+ *
+ * struct trap_trace_record {
+ *	ushort_t tl, tt;
+ *	long	pc;
+ *	int64_t	tstate, tick;
+ *	long	sp, tr, f1, f2, f3, f4;
+ * };
+ *
+ * Note that for UltraSparc III and beyond %stick is used in place of %tick
+ * unless compiled with TRAPTRACE_FORCE_TICK.
+ *
+ * Auxilliary entries (not of just a trap), have obvious non-%tt values in
+ * the TRAP_ENT_TT field
+ */
+
+#define	TRAP_TPGS	(2 * PAGESIZE)	/* default size is two pages */
+
+#ifndef	_ASM
+
+struct trap_trace_record {
+	uint16_t	tt_tl;
+	uint16_t	tt_tt;
+	uintptr_t	tt_tpc;
+	uint64_t	tt_tstate;
+	uint64_t	tt_tick;
+	uintptr_t	tt_sp;
+	uintptr_t	tt_tr;
+	uintptr_t	tt_f1;
+	uintptr_t	tt_f2;
+	uintptr_t	tt_f3;
+	uintptr_t	tt_f4;
+};
+
+#define	TRAP_TSIZE	((TRAP_TPGS / sizeof (struct trap_trace_record)) * \
+			sizeof (struct trap_trace_record))
+
+#else
+
+#define	TRAP_TSIZE	((TRAP_TPGS / TRAP_ENT_SIZE) * TRAP_ENT_SIZE)
+
+#endif
+
+#define	TRAP_TBUF_SIZE	TRAP_TSIZE
+
+/*
+ * Trap tracing buffer header.
+ */
+
+#ifndef	_ASM
+
+/*
+ * Example buffer header stored in locore.s:
+ *
+ * (the actual implementation could be .skip TRAPTR_SIZE*NCPU)
+ */
+typedef union {
+    struct {
+	caddr_t		vaddr_base;	/* virtual address of top of buffer */
+	uint64_t	paddr_base;	/* physical address of buffer */
+	uint_t		last_offset;	/* to "know" what trace completed */
+	uint_t		offset;		/* current index into buffer (bytes) */
+	uint_t		limit;		/* upper limit on index */
+	uchar_t		asi;		/* cache for real asi */
+	} d;
+    char		cache_linesize[64];
+} TRAP_TRACE_CTL;
+
+#ifdef _KERNEL
+
+extern TRAP_TRACE_CTL	trap_trace_ctl[];	/* allocated in locore.s */
+extern int		trap_trace_bufsize;	/* default buffer size */
+extern char		trap_tr0[];		/* prealloc buf for boot cpu */
+extern int		trap_freeze;		/* freeze the trap trace */
+extern caddr_t		ttrace_buf;		/* buffer bop alloced */
+extern int		ttrace_index;		/* index used */
+extern caddr_t		trap_trace_alloc(caddr_t);
+extern void htrap_trace_setup(caddr_t, int);
+extern void htrap_trace_register(int);
+
+#endif
+
+/*
+ * freeze the trap trace
+ */
+#define	TRAPTRACE_FREEZE	trap_freeze = 1;
+#define	TRAPTRACE_UNFREEZE	trap_freeze = 0;
+
+#else /* _ASM */
+
+#include <sys/machthread.h>
+
+/*
+ * Offsets of words in trap_trace_ctl:
+ */
+/*
+ * XXX This should be done with genassym
+ */
+#define	TRAPTR_VBASE	0		/* virtual address of buffer */
+#define	TRAPTR_LAST_OFFSET 16		/* last completed trace entry */
+#define	TRAPTR_OFFSET	20		/* next trace entry pointer */
+#define	TRAPTR_LIMIT	24		/* pointer past end of buffer */
+#define	TRAPTR_PBASE	8		/* start of buffer */
+#define	TRAPTR_ASIBUF	28		/* cache of current asi */
+#define	TRAPTR_SIZE_SHIFT	6	/* shift count -- per CPU indexing */
+#define	TRAPTR_SIZE		(1<<TRAPTR_SIZE_SHIFT)
+
+#define	TRAPTR_ASI	ASI_MEM		/* ASI to use for TRAPTR access */
+
+/*
+ * Use new %stick register for UltraSparc III and beyond for
+ * sane debugging of mixed speed CPU systems. Use TRAPTRACE_FORCE_TICK
+ * for finer granularity on same speed systems.
+ *
+ * Note the label-less branches used due to contraints of where
+ * and when trap trace macros are used.
+ */
+#ifdef	TRAPTRACE_FORCE_TICK
+#define	GET_TRACE_TICK(reg)				\
+	rdpr	%tick, reg;
+#else
+#define	GET_TRACE_TICK(reg)				\
+	sethi	%hi(traptrace_use_stick), reg;		\
+	lduw	[reg + %lo(traptrace_use_stick)], reg;	\
+	/* CSTYLED */					\
+        brz,a	reg, .+12;				\
+	rdpr	%tick, reg;				\
+	rd	%asr24, reg;
+#endif
+
+/*
+ * TRACE_PTR(ptr, scr1) - get trap trace entry physical pointer.
+ *	ptr is the register to receive the trace pointer.
+ *	scr1 is a different register to be used as scratch.
+ * TRACING now needs a known processor state.  Hence the assertion.
+ *	NOTE: this caches and resets %asi
+ */
+#define	TRACE_PTR(ptr, scr1)				\
+	sethi	%hi(trap_freeze), ptr;			\
+	ld	[ptr + %lo(trap_freeze)], ptr;		\
+	/* CSTYLED */					\
+	brnz,pn	ptr, .+20; /* skip assertion */		\
+	rdpr	%pstate, scr1;				\
+	andcc	scr1, PSTATE_IE | PSTATE_AM, scr1;	\
+	/* CSTYLED */					\
+	bne,a,pn %icc, trace_ptr_panic;			\
+	rd	%pc, %g1;				\
+	CPU_INDEX(scr1, ptr);				\
+	sll	scr1, TRAPTR_SIZE_SHIFT, scr1;		\
+	set	trap_trace_ctl, ptr; 			\
+	add	ptr, scr1, scr1;			\
+	rd	%asi, ptr;				\
+	stb	ptr, [scr1 + TRAPTR_ASIBUF];		\
+	sethi	%hi(trap_freeze), ptr;			\
+	ld	[ptr + %lo(trap_freeze)], ptr;		\
+	/* CSTYLED */					\
+	brnz,pn	ptr, .+20; /* skip assertion */		\
+	ld	[scr1 + TRAPTR_LIMIT], ptr;		\
+	tst	ptr;					\
+	/* CSTYLED */					\
+	be,a,pn	%icc, trace_ptr_panic;			\
+	rd	%pc, %g1;				\
+	ldx	[scr1 + TRAPTR_PBASE], ptr;		\
+	ld	[scr1 + TRAPTR_OFFSET], scr1;		\
+	wr	%g0, TRAPTR_ASI, %asi;			\
+	add	ptr, scr1, ptr;
+
+/*
+ * TRACE_NEXT(scr1, scr2, scr3) - advance the trap trace pointer.
+ *	scr1, scr2, scr3 are scratch registers.
+ *	This routine will skip updating the trap pointers if the
+ *	global freeze register is set (e.g. in panic).
+ *	(we also restore the asi register)
+ */
+#define	TRACE_NEXT(scr1, scr2, scr3)			\
+	CPU_INDEX(scr2, scr1);				\
+	sll	scr2, TRAPTR_SIZE_SHIFT, scr2;		\
+	set	trap_trace_ctl, scr1; 			\
+	add	scr1, scr2, scr2;			\
+	ldub	[scr2 + TRAPTR_ASIBUF], scr1;		\
+	wr	%g0, scr1, %asi;			\
+	sethi	%hi(trap_freeze), scr1;			\
+	ld	[scr1 + %lo(trap_freeze)], scr1;	\
+	/* CSTYLED */					\
+	brnz	scr1, .+36; /* skip update on freeze */	\
+	ld	[scr2 + TRAPTR_OFFSET], scr1;		\
+	ld	[scr2 + TRAPTR_LIMIT], scr3;		\
+	st	scr1, [scr2 + TRAPTR_LAST_OFFSET];	\
+	add	scr1, TRAP_ENT_SIZE, scr1;		\
+	sub	scr3, TRAP_ENT_SIZE, scr3;		\
+	cmp	scr1, scr3;				\
+	movge	%icc, 0, scr1;				\
+	st	scr1, [scr2 + TRAPTR_OFFSET];
+
+/*
+ * macro to save %tl to trap trace record at addr
+ */
+#define	TRACE_SAVE_TL_GL_REGS(addr, scr1)		\
+	rdpr	%tl, scr1;				\
+	stha	scr1, [addr + TRAP_ENT_TL]%asi
+
+/*
+ * macro to save tl to trap trace record at addr
+ */
+#define	TRACE_SAVE_TL_VAL(addr, tl)			\
+	stha	tl, [addr + TRAP_ENT_TL]%asi
+
+/*
+ * dummy macro
+ */
+#define	TRACE_SAVE_GL_VAL(addr, gl)
+
+
+/*
+ * Trace macro for sys_trap return entries:
+ *	prom_rtt, priv_rtt, and user_rtt
+ *	%l7 - regs
+ *	%l6 - trap %pil for prom_rtt and priv_rtt; THREAD_REG for user_rtt
+ */
+#define	TRACE_RTT(code, scr1, scr2, scr3, scr4)		\
+	rdpr	%pstate, scr4;				\
+	andn	scr4, PSTATE_IE | PSTATE_AM, scr3;	\
+	wrpr	%g0, scr3, %pstate;			\
+	TRACE_PTR(scr1, scr2);				\
+	GET_TRACE_TICK(scr2);				\
+	stxa	scr2, [scr1 + TRAP_ENT_TICK]%asi;	\
+	rdpr	%tl, scr2;				\
+	stha	scr2, [scr1 + TRAP_ENT_TL]%asi;		\
+	set	code, scr2;				\
+	stha	scr2, [scr1 + TRAP_ENT_TT]%asi;		\
+	ldn	[%l7 + PC_OFF], scr2;			\
+	stna	scr2, [scr1 + TRAP_ENT_TPC]%asi;	\
+	ldx	[%l7 + TSTATE_OFF], scr2;		\
+	stxa	scr2, [scr1 + TRAP_ENT_TSTATE]%asi;	\
+	stna	%sp, [scr1 + TRAP_ENT_SP]%asi;		\
+	stna	%l6, [scr1 + TRAP_ENT_TR]%asi;		\
+	stna	%l7, [scr1 + TRAP_ENT_F1]%asi;		\
+	ldn	[THREAD_REG + T_CPU], scr2;		\
+	ld	[scr2 + CPU_BASE_SPL], scr2;		\
+	stna	scr2, [scr1 + TRAP_ENT_F2]%asi;		\
+	mov	MMU_SCONTEXT, scr2;			\
+	ldxa	[scr2]ASI_DMMU, scr2;			\
+	stna	scr2, [scr1 + TRAP_ENT_F3]%asi;		\
+	rdpr	%cwp, scr2;				\
+	stna	scr2, [scr1 + TRAP_ENT_F4]%asi;		\
+	TRACE_NEXT(scr1, scr2, scr3);			\
+	wrpr	%g0, scr4, %pstate
+
+/*
+ * Trace macro for spill and fill trap handlers
+ *	tl and tt fields indicate which spill handler is entered
+ */
+#define	TRACE_WIN_INFO(code, scr1, scr2, scr3)		\
+	TRACE_PTR(scr1, scr2);				\
+	GET_TRACE_TICK(scr2);				\
+	stxa	scr2, [scr1 + TRAP_ENT_TICK]%asi;	\
+	rdpr	%tl, scr2;				\
+	stha	scr2, [scr1 + TRAP_ENT_TL]%asi;		\
+	rdpr	%tt, scr2;				\
+	set	code, scr3;				\
+	or	scr2, scr3, scr2;			\
+	stha	scr2, [scr1 + TRAP_ENT_TT]%asi;		\
+	rdpr	%tstate, scr2;				\
+	stxa	scr2, [scr1 + TRAP_ENT_TSTATE]%asi;	\
+	stna	%sp, [scr1 + TRAP_ENT_SP]%asi;		\
+	rdpr	%tpc, scr2;				\
+	stna	scr2, [scr1 + TRAP_ENT_TPC]%asi;	\
+	set	TT_FSPILL_DEBUG, scr2;			\
+	stna	scr2, [scr1 + TRAP_ENT_TR]%asi;		\
+	rdpr	%pstate, scr2;				\
+	stna	scr2, [scr1 + TRAP_ENT_F1]%asi;		\
+	rdpr	%cwp, scr2;				\
+	sll	scr2, 24, scr2;				\
+	rdpr	%cansave, scr3;				\
+	sll	scr3, 16, scr3;				\
+	or	scr2, scr3, scr2;			\
+	rdpr	%canrestore, scr3;			\
+	or	scr2, scr3, scr2;			\
+	stna	scr2, [scr1 + TRAP_ENT_F2]%asi;		\
+	rdpr	%otherwin, scr2;			\
+	sll	scr2, 24, scr2;				\
+	rdpr	%cleanwin, scr3;			\
+	sll	scr3, 16, scr3;				\
+	or	scr2, scr3, scr2;			\
+	rdpr	%wstate, scr3;				\
+	or	scr2, scr3, scr2;			\
+	stna	scr2, [scr1 + TRAP_ENT_F3]%asi;		\
+	stna	%o7, [scr1 + TRAP_ENT_F4]%asi;		\
+	TRACE_NEXT(scr1, scr2, scr3)
+
+#ifdef TRAPTRACE
+
+#define	FAULT_WINTRACE(scr1, scr2, scr3, type)		\
+	TRACE_PTR(scr1, scr2);				\
+	GET_TRACE_TICK(scr2);				\
+	stxa	scr2, [scr1 + TRAP_ENT_TICK]%asi;	\
+	rdpr	%tl, scr2;				\
+	stha	scr2, [scr1 + TRAP_ENT_TL]%asi;		\
+	set	type, scr2;				\
+	stha	scr2, [scr1 + TRAP_ENT_TT]%asi;		\
+	rdpr	%tpc, scr2;				\
+	stna	scr2, [scr1 + TRAP_ENT_TPC]%asi;	\
+	rdpr	%tstate, scr2;				\
+	stxa	scr2, [scr1 + TRAP_ENT_TSTATE]%asi;	\
+	stna	%sp, [scr1 + TRAP_ENT_SP]%asi;		\
+	stna	%g0, [scr1 + TRAP_ENT_TR]%asi;		\
+	stna	%g0, [scr1 + TRAP_ENT_F1]%asi;		\
+	stna	%g4, [scr1 + TRAP_ENT_F2]%asi;		\
+	rdpr	%pil, scr2;				\
+	stna	scr2, [scr1 + TRAP_ENT_F3]%asi;		\
+	stna	%g0, [scr1 + TRAP_ENT_F4]%asi;		\
+	TRACE_NEXT(scr1, scr2, scr3)
+
+#define	SYSTRAP_TT	0x1300
+
+#define	SYSTRAP_TRACE(scr1, scr2, scr3)			\
+	TRACE_PTR(scr1, scr2);				\
+	GET_TRACE_TICK(scr2);				\
+	stxa	scr2, [scr1 + TRAP_ENT_TICK]%asi;	\
+	rdpr	%tl, scr2;				\
+	stha	scr2, [scr1 + TRAP_ENT_TL]%asi;		\
+	set	SYSTRAP_TT, scr3;			\
+	rdpr	%tt, scr2;				\
+	or	scr3, scr2, scr2;			\
+	stha	scr2, [scr1 + TRAP_ENT_TT]%asi;		\
+	rdpr	%tpc, scr2;				\
+	stna	scr2, [scr1 + TRAP_ENT_TPC]%asi;	\
+	rdpr	%tstate, scr2;				\
+	stxa	scr2, [scr1 + TRAP_ENT_TSTATE]%asi;	\
+	stna	%g1, [scr1 + TRAP_ENT_SP]%asi;		\
+	stna	%g2, [scr1 + TRAP_ENT_TR]%asi;		\
+	stna	%g3, [scr1 + TRAP_ENT_F1]%asi;		\
+	stna	%g4, [scr1 + TRAP_ENT_F2]%asi;		\
+	rdpr	%pil, scr2;				\
+	stna	scr2, [scr1 + TRAP_ENT_F3]%asi;		\
+	rdpr	%cwp, scr2;				\
+	stna	scr2, [scr1 + TRAP_ENT_F4]%asi;		\
+	TRACE_NEXT(scr1, scr2, scr3)
+
+#else /* TRAPTRACE */
+
+#define	FAULT_WINTRACE(scr1, scr2, scr3, type)
+#define	SYSTRAP_TRACE(scr1, scr2, scr3)
+
+#endif /* TRAPTRACE */
+
+#endif	/* _ASM */
+
+/*
+ * Trap trace codes used in place of a %tbr value when more than one
+ * entry is made by a trap.  The general scheme is that the trap-type is
+ * in the same position as in the TT, and the low-order bits indicate
+ * which precise entry is being made.
+ */
+
+#define	TT_F32_SN0	0x1084
+#define	TT_F64_SN0	0x1088
+#define	TT_F32_NT0	0x1094
+#define	TT_F64_NT0	0x1098
+#define	TT_F32_SO0	0x10A4
+#define	TT_F64_SO0	0x10A8
+#define	TT_F32_FN0	0x10C4
+#define	TT_F64_FN0	0x10C8
+#define	TT_F32_SN1	0x1284
+#define	TT_F64_SN1	0x1288
+#define	TT_F32_NT1	0x1294
+#define	TT_F64_NT1	0x1298
+#define	TT_F32_SO1	0x12A4
+#define	TT_F64_SO1	0x12A8
+#define	TT_F32_FN1	0x12C4
+#define	TT_F64_FN1	0x12C8
+
+#define	TT_SC_ENTR	0x880	/* enter system call */
+#define	TT_SC_RET	0x881	/* system call normal return */
+
+#define	TT_SYS_RTT_PROM	0x5555	/* return from trap to prom */
+#define	TT_SYS_RTT_PRIV	0x6666	/* return from trap to privilege */
+#define	TT_SYS_RTT_USER	0x7777	/* return from trap to user */
+
+#define	TT_INTR_EXIT	0x8888	/* interrupt thread exit (no pinned thread) */
+#define	TT_FSPILL_DEBUG	0x9999	/* fill/spill debugging */
+
+#define	TT_SERVE_INTR	0x6000	/* SERVE_INTR */
+#define	TT_XCALL	0xd000	/* xcall/xtrap */
+#define	TT_XCALL_CONT	0xdc00	/* continuation of an xcall/xtrap record */
+
+#define	TT_MMU_MISS	0x200	/* or'd into %tt to indicate a miss */
+#define	TT_SPURIOUS_INT	0x400	/* or'd into %tt for spurious intr. */
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_TRAPTRACE_H */
diff --git a/usr/src/uts/sun4u/sys/upa64s.h b/usr/src/uts/sun4u/sys/upa64s.h
new file mode 100644
index 0000000000..e8271995e3
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/upa64s.h
@@ -0,0 +1,199 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 1999-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_UPA64S_VAR_H
+#define	_SYS_UPA64S_VAR_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	HI32(x) ((uint32_t)(((uint64_t)(x)) >> 32))
+#define	LO32(x) ((uint32_t)(x))
+#define	UPA64S_PORTS	2	/* number of UPA ports per device */
+
+/*
+ * the following typedef is used to describe the state
+ * of a UPA port interrupt.
+ */
+typedef enum { INO_FREE = 0, INO_INUSE } ino_state_t;
+
+/*
+ * INO related macros:
+ */
+#define	UPA64S_MAKE_MONDO(id, ino)	((id) << 6 | (ino))
+#define	UPA64S_MONDO_TO_INO(mondo) 	((mondo) & 0x3f)
+
+/*
+ * Interrupt Mapping Registers
+ */
+#define	IMR_MONDO			0x7ff
+#define	IMR_TID_BIT			26
+#define	IMR_TID				(0x1f << IMR_TID_BIT)
+#define	IMR_VALID			(1u << 31)
+#define	UPA64S_IMR_TO_CPUID(imr)	(((imr) & IMR_TID) >> IMR_TID_BIT)
+#define	UPA64S_IMR_TO_MONDO(imr)	((imr) & IMR_MONDO)
+#define	UPA64S_CPUID_TO_IMR(cpuid)	((cpuid) << IMR_TID_BIT)
+#define	UPA64S_GET_MAP_REG(mondo, imr)	((mondo) | (imr) | IMR_VALID)
+
+/*
+ * The following structure defines the format of UPA64S addresses.
+ * This structure is used to hold UPA64S "reg" property entries.
+ */
+typedef struct upa64s_regspec {
+	uint64_t upa64s_phys;
+	uint64_t upa64s_size;
+} upa64s_regspec_t;
+
+/*
+ * The following structure defines the format of a "ranges"
+ * property entry for UPA64S bus node.
+ */
+typedef struct upa64s_ranges {
+	uint64_t upa64s_child;
+	uint64_t upa64s_parent;
+	uint64_t upa64s_size;
+} upa64s_ranges_t;
+
+/*
+ * per-upa64s soft state structure:
+ */
+typedef struct upa64s_devstate {
+	dev_info_t *dip;			/* devinfo structure */
+	uint_t safari_id;			/* safari device id */
+
+	ino_state_t ino_state[UPA64S_PORTS];	/* INO state */
+	uint64_t *imr[UPA64S_PORTS];		/* Intr mapping reg; treat */
+						/* as two element array */
+	ddi_acc_handle_t imr_ah[UPA64S_PORTS];	/* Mapping handle */
+	uint64_t imr_data[UPA64S_PORTS];	/* imr save/restore area */
+
+	caddr_t config_base;			/* conf base address */
+	uint64_t *upa0_config;			/* UPA 0 config */
+	uint64_t *upa1_config;			/* UPA 1 config */
+	uint64_t *if_config;			/* UPA inteface config */
+	uint64_t *estar;			/* UPA estar control */
+	ddi_acc_handle_t config_base_ah;	/* config acc handle */
+
+	int power_level;			/* upa64s' power level */
+	int saved_power_level;			/* power level during suspend */
+} upa64s_devstate_t;
+
+/*
+ * UPA64S Register Offsets
+ */
+#define	UPA64S_UPA0_CONFIG_OFFSET	0x00
+#define	UPA64S_UPA1_CONFIG_OFFSET	0x08
+#define	UPA64S_IF_CONFIG_OFFSET		0x10
+#define	UPA64S_ESTAR_OFFSET		0x18
+
+/*
+ * UPA64S Interface Configurations
+ */
+#define	UPA64S_NOT_POK_RST_L	0x0
+#define	UPA64S_POK_RST_L	0x2
+#define	UPA64S_POK_NOT_RST_L	0x3
+
+/*
+ * UPA64S Energy Star Control Register
+ */
+#define	UPA64S_FULL_SPEED	0x01
+#define	UPA64S_1_2_SPEED	0x02
+#define	UPA64S_1_64_SPEED	0x40
+
+/*
+ * Power Management definitions
+ */
+#define	UPA64S_PM_COMP		0		/* power management component */
+#define	UPA64S_PM_UNKNOWN	-1		/* power unknown */
+#define	UPA64S_PM_RESET		0		/* power off */
+#define	UPA64S_PM_NORMOP	1		/* power on */
+
+/*
+ * upa64s soft state macros:
+ */
+#define	get_upa64s_soft_state(i)	\
+	((upa64s_devstate_t *)ddi_get_soft_state(per_upa64s_state, (i)))
+#define	alloc_upa64s_soft_state(i)	\
+	ddi_soft_state_zalloc(per_upa64s_state, (i))
+#define	free_upa64s_soft_state(i)	\
+	ddi_soft_state_free(per_upa64s_state, (i))
+
+/*
+ * debugging definitions:
+ */
+#if defined(DEBUG)
+#define	D_ATTACH	0x00000001
+#define	D_DETACH	0x00000002
+#define	D_POWER		0x00000004
+#define	D_MAP		0x00000008
+#define	D_CTLOPS	0x00000010
+#define	D_G_ISPEC	0x00000020
+#define	D_A_ISPEC	0x00000040
+#define	D_R_ISPEC	0x00000080
+#define	D_INIT_CLD	0x00400000
+#define	D_RM_CLD	0x00800000
+#define	D_GET_REG	0x01000000
+#define	D_XLATE_REG	0x02000000
+#define	D_INTRDIST	0x04000000
+
+#define	D_CONT		0x80000000
+
+#define	DBG(flag, psp, fmt) \
+	upa64s_debug(flag, psp, fmt, 0, 0, 0, 0, 0);
+#define	DBG1(flag, psp, fmt, a1) \
+	upa64s_debug(flag, psp, fmt, (uintptr_t)(a1), 0, 0, 0, 0);
+#define	DBG2(flag, psp, fmt, a1, a2) \
+	upa64s_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), 0, 0, 0);
+#define	DBG3(flag, psp, fmt, a1, a2, a3) \
+	upa64s_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \
+		(uintptr_t)(a3), 0, 0);
+#define	DBG4(flag, psp, fmt, a1, a2, a3, a4) \
+	upa64s_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \
+		(uintptr_t)(a3), (uintptr_t)(a4), 0);
+#define	DBG5(flag, psp, fmt, a1, a2, a3, a4, a5) \
+	upa64s_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \
+		(uintptr_t)(a3), (uintptr_t)(a4), (uintptr_t)(a5));
+
+static void upa64s_debug(uint_t, dev_info_t *, char *, uintptr_t, uintptr_t, \
+	uintptr_t, uintptr_t, uintptr_t);
+#else
+#define	DBG(flag, psp, fmt)
+#define	DBG1(flag, psp, fmt, a1)
+#define	DBG2(flag, psp, fmt, a1, a2)
+#define	DBG3(flag, psp, fmt, a1, a2, a3)
+#define	DBG4(flag, psp, fmt, a1, a2, a3, a4)
+#define	DBG5(flag, psp, fmt, a1, a2, a3, a4, a5)
+#define	dump_dma_handle(flag, psp, h)
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_UPA64S_VAR_H */
diff --git a/usr/src/uts/sun4u/sys/us3_module.h b/usr/src/uts/sun4u/sys/us3_module.h
new file mode 100644
index 0000000000..836862a095
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/us3_module.h
@@ -0,0 +1,699 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_US3_MODULE_H
+#define	_SYS_US3_MODULE_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/async.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifdef _KERNEL
+
+/*
+ * Macros to access the "cheetah cpu private" data structure.
+ */
+#define	CPU_PRIVATE_PTR(cp, x)	(&(((cheetah_private_t *)CPU_PRIVATE(cp))->x))
+#define	CPU_PRIVATE_VAL(cp, x)	(((cheetah_private_t *)CPU_PRIVATE(cp))->x)
+
+#define	CHP_WORD_TO_OFF(word, off)	(((word) * 8) == off)
+
+#if defined(JALAPENO) || defined(SERRANO)
+/* JP J_REQ errors */
+#define	C_AFSR_JREQ_ERRS	(C_AFSR_RUE | C_AFSR_BP | C_AFSR_WBP | \
+			C_AFSR_RCE | C_AFSR_TO | C_AFSR_BERR | C_AFSR_UMS)
+/* JP AID errors */
+#define	C_AFSR_AID_ERRS		(C_AFSR_CPU | C_AFSR_FRU | C_AFSR_CPC | \
+			C_AFSR_FRC)
+
+#if defined(SERRANO)
+/* SERRANO AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */
+#define	C_AFSR_CECC_ERRS	(C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_CPC | \
+			C_AFSR_CPU | C_AFSR_WDC | C_AFSR_WDU | C_AFSR_EDC | \
+			C_AFSR_CE | C_AFSR_RCE | C_AFSR_WBP | C_AFSR_FRC | \
+			C_AFSR_FRU | C_AFSR_EDU | C_AFSR_ETI | C_AFSR_ETC)
+
+#else /* SERRANO */
+/* JP AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */
+#define	C_AFSR_CECC_ERRS	(C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_CPC | \
+			C_AFSR_CPU | C_AFSR_WDC | C_AFSR_WDU | C_AFSR_EDC | \
+			C_AFSR_CE | C_AFSR_RCE | C_AFSR_WBP | C_AFSR_FRC | \
+			C_AFSR_FRU | C_AFSR_EDU)
+#endif /* SERRANO */
+
+#if defined(SERRANO)
+/*
+ * SERRANO AFSR bits from {Instruction,Data}_access_error traps
+ * (Traps 0xa, 0x32)
+ */
+#define	C_AFSR_ASYNC_ERRS	(C_AFSR_OM | C_AFSR_TO | C_AFSR_BERR | \
+			C_AFSR_UE | C_AFSR_RUE | C_AFSR_EDU | C_AFSR_BP | \
+			C_AFSR_ETU | C_AFSR_ETS)
+#else /* SERRANO */
+/* JP AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */
+#define	C_AFSR_ASYNC_ERRS	(C_AFSR_OM | C_AFSR_TO | C_AFSR_BERR | \
+			C_AFSR_UE | C_AFSR_RUE | C_AFSR_EDU | C_AFSR_BP)
+#endif /* SERRANO */
+
+#if defined(SERRANO)
+/* SERRANO AFSR bits from Fast_ECC_error trap (Trap 0x70) */
+#define	C_AFSR_FECC_ERRS	(C_AFSR_UCU | C_AFSR_UCC | C_AFSR_ETI | \
+				C_AFSR_ETC)
+
+#else /* SERRANO */
+/* JP AFSR bits from Fast_ECC_error trap (Trap 0x70) */
+#define	C_AFSR_FECC_ERRS	(C_AFSR_UCU | C_AFSR_UCC)
+#endif /* SERRANO */
+
+#if defined(SERRANO)
+/* SERRANO AFSR bits from Fatal errors (processor asserts ERROR pin) */
+#define	C_AFSR_FATAL_ERRS	(C_AFSR_JETO | C_AFSR_SCE | C_AFSR_JEIC | \
+			C_AFSR_JEIT | C_AFSR_JEIS | C_AFSR_IERR | \
+			C_AFSR_ISAP | C_AFSR_EFES | C_AFSR_ETS | C_AFSR_ETU)
+
+#else /* SERRANO */
+/* JP AFSR bits from Fatal errors (processor asserts ERROR pin) */
+#define	C_AFSR_FATAL_ERRS	(C_AFSR_JETO | C_AFSR_SCE | C_AFSR_JEIC | \
+			C_AFSR_JEIT | C_AFSR_JEIS | C_AFSR_IERR | \
+			C_AFSR_ISAP | C_AFSR_ETP)
+#endif /* SERRANO */
+
+/* JP AFSR all valid error status bits */
+#define	C_AFSR_ALL_ERRS	(C_AFSR_FATAL_ERRS | C_AFSR_FECC_ERRS | \
+			C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME)
+
+#if defined(SERRANO)
+/* SERRANO AFSR all ME status bits */
+#define	C_AFSR_ALL_ME_ERRS	(C_AFSR_ISAP | C_AFSR_UE | C_AFSR_UCU | \
+			C_AFSR_EDU | C_AFSR_WDU | C_AFSR_CPU | C_AFSR_UCC | \
+			C_AFSR_BERR | C_AFSR_TO | C_AFSR_ETU | C_AFSR_OM | \
+			C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_RUE | C_AFSR_BP | \
+			C_AFSR_WBP | C_AFSR_FRU | C_AFSR_JETO | C_AFSR_SCE | \
+			C_AFSR_JEIC | C_AFSR_JEIT | C_AFSR_JEIS | \
+			C_AFSR_ETC | C_AFSR_ETI)
+
+#else /* SERRANO */
+/* JP AFSR all ME status bits */
+#define	C_AFSR_ALL_ME_ERRS	(C_AFSR_ISAP | C_AFSR_UE | C_AFSR_UCU | \
+			C_AFSR_EDU | C_AFSR_WDU | C_AFSR_CPU | C_AFSR_UCC | \
+			C_AFSR_BERR | C_AFSR_TO | C_AFSR_ETP | C_AFSR_OM | \
+			C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_RUE | C_AFSR_BP | \
+			C_AFSR_WBP | C_AFSR_FRU | C_AFSR_JETO | C_AFSR_SCE | \
+			C_AFSR_JEIC | C_AFSR_JEIT | C_AFSR_JEIS)
+#endif /* SERRANO */
+
+#if defined(SERRANO)
+/* SERRANO AFSR bits due to an Ecache error */
+#define	C_AFSR_ECACHE	(C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \
+			C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \
+			C_AFSR_ETU  | C_AFSR_ETS | C_AFSR_ETI | C_AFSR_ETC)
+
+#else /* SERRANO */
+/* JP AFSR bits due to an Ecache error */
+#define	C_AFSR_ECACHE	(C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \
+			C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \
+			C_AFSR_ETP)
+#endif /* SERRANO */
+
+/* JP AFSR bits due to a Memory error */
+#define	C_AFSR_MEMORY	(C_AFSR_UE | C_AFSR_CE | C_AFSR_FRC | C_AFSR_FRU |\
+			C_AFSR_RCE | C_AFSR_RUE)
+
+/* JP AFSR bits due to parity errors and have a valid BSYND */
+#define	C_AFSR_MSYND_ERRS	(C_AFSR_IVPE | C_AFSR_BP | C_AFSR_WBP)
+
+/* JP AFSR bits with a valid ESYND field */
+#define	C_AFSR_ESYND_ERRS	(C_AFSR_UE | C_AFSR_CE | \
+			C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \
+			C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \
+			C_AFSR_FRC | C_AFSR_FRU)
+
+/* JP AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */
+#define	C_AFSR_LEVEL1	(C_AFSR_UE | C_AFSR_RUE | C_AFSR_UCU | C_AFSR_EDU | \
+			C_AFSR_WDU | C_AFSR_CPU | C_AFSR_IVPE | C_AFSR_TO | \
+			C_AFSR_BERR | C_AFSR_UMS | C_AFSR_OM | C_AFSR_WBP | \
+			C_AFSR_FRU | C_AFSR_BP)
+
+#elif defined(CHEETAH_PLUS)
+
+/* Ch+ AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */
+#define	C_AFSR_CECC_ERRS	(C_AFSR_CE | C_AFSR_EMC | C_AFSR_EDU | \
+			C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \
+			C_AFSR_CPC | C_AFSR_IVU | C_AFSR_IVC | C_AFSR_DUE | \
+			C_AFSR_THCE | C_AFSR_DBERR | C_AFSR_DTO | C_AFSR_IMU | \
+			C_AFSR_IMC)
+
+/* Ch+ AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */
+#define	C_AFSR_ASYNC_ERRS	(C_AFSR_UE | C_AFSR_EMU | C_AFSR_EDU | \
+			C_AFSR_TO | C_AFSR_BERR)
+
+/* Ch+ AFSR bits from Fast_ECC_error trap (Trap 0x70) */
+#define	C_AFSR_FECC_ERRS	(C_AFSR_UCU | C_AFSR_UCC | C_AFSR_TSCE)
+
+/* Ch+ AFSR bits from Fatal errors (processor asserts ERROR pin) */
+#define	C_AFSR_FATAL_ERRS	(C_AFSR_PERR | C_AFSR_IERR | C_AFSR_ISAP | \
+			C_AFSR_TUE | C_AFSR_TUE_SH | C_AFSR_IMU | C_AFSR_EMU)
+
+/* Ch+ AFSR all valid error status bits */
+#define	C_AFSR_ALL_ERRS	(C_AFSR_FATAL_ERRS | C_AFSR_FECC_ERRS | \
+			C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME)
+
+/* Ch+ AFSR all errors that set ME bit, in both AFSR and AFSR_EXT */
+#define	C_AFSR_ALL_ME_ERRS	(C_AFSR_TUE_SH | C_AFSR_IMU | C_AFSR_DTO | \
+			C_AFSR_DBERR | C_AFSR_TSCE | C_AFSR_TUE | C_AFSR_DUE | \
+			C_AFSR_ISAP | C_AFSR_EMU | C_AFSR_IVU | C_AFSR_TO | \
+			C_AFSR_BERR | C_AFSR_UCC | C_AFSR_UCU | C_AFSR_CPU | \
+			C_AFSR_WDU | C_AFSR_EDU | C_AFSR_UE | \
+			C_AFSR_L3_TUE_SH | C_AFSR_L3_TUE | C_AFSR_L3_EDU | \
+			C_AFSR_L3_UCC | C_AFSR_L3_UCU | C_AFSR_L3_CPU | \
+			C_AFSR_L3_WDU)
+
+/* Ch+ AFSR bits due to an Ecache error */
+#define	C_AFSR_ECACHE	(C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \
+			C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \
+			C_AFSR_TUE | C_AFSR_TSCE | C_AFSR_THCE | C_AFSR_TUE_SH)
+
+/* Ch+ AFSR bits due to a Memory error */
+#define	C_AFSR_MEMORY	(C_AFSR_UE | C_AFSR_CE | C_AFSR_EMU | C_AFSR_EMC | \
+			C_AFSR_DUE)
+
+/* Ch+ AFSR bits due to an Mtag error and have a valid MSYND */
+#define	C_AFSR_MSYND_ERRS	(C_AFSR_EMU | C_AFSR_EMC | C_AFSR_IMU | \
+			C_AFSR_IMC)
+
+/* Ch+ AFSR bits with a valid ESYND field */
+#define	C_AFSR_ESYND_ERRS	(C_AFSR_UE | C_AFSR_CE | \
+			C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \
+			C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \
+			C_AFSR_IVU | C_AFSR_IVC | C_AFSR_DUE)
+
+/* Ch+ AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */
+#define	C_AFSR_LEVEL1	(C_AFSR_UE | C_AFSR_UCU | C_AFSR_EMU | C_AFSR_EDU | \
+			C_AFSR_WDU | C_AFSR_CPU | C_AFSR_IVU | C_AFSR_TO | \
+			C_AFSR_BERR | C_AFSR_DUE | C_AFSR_TUE | C_AFSR_DTO | \
+			C_AFSR_DBERR | C_AFSR_TUE_SH | C_AFSR_IMU)
+
+#else	/* CHEETAH_PLUS */
+
+/* AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */
+#define	C_AFSR_CECC_ERRS	(C_AFSR_CE | C_AFSR_EMC | C_AFSR_EDU | \
+			C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \
+			C_AFSR_CPC | C_AFSR_IVU | C_AFSR_IVC)
+
+/* AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */
+#define	C_AFSR_ASYNC_ERRS	(C_AFSR_UE | C_AFSR_EMU | C_AFSR_EDU | \
+			C_AFSR_TO | C_AFSR_BERR)
+
+/* AFSR bits from Fast_ECC_error trap (Trap 0x70) */
+#define	C_AFSR_FECC_ERRS	(C_AFSR_UCU | C_AFSR_UCC)
+
+/* AFSR bits from Fatal errors (processor asserts ERROR pin) */
+#define	C_AFSR_FATAL_ERRS	(C_AFSR_PERR | C_AFSR_IERR | C_AFSR_ISAP | \
+			C_AFSR_EMU)
+
+/* AFSR all valid error status bits */
+#define	C_AFSR_ALL_ERRS	(C_AFSR_FATAL_ERRS | C_AFSR_FECC_ERRS | \
+			C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME)
+
+/* AFSR all ME status bits */
+#define	C_AFSR_ALL_ME_ERRS	(C_AFSR_ISAP | C_AFSR_UE | C_AFSR_IVU | \
+			C_AFSR_EMU | C_AFSR_UCU | C_AFSR_EDU | C_AFSR_WDU | \
+			C_AFSR_CPU | C_AFSR_UCC | C_AFSR_BERR | C_AFSR_TO)
+
+/* AFSR bits due to an Ecache error */
+#define	C_AFSR_ECACHE	(C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \
+			C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC)
+
+/* AFSR bits due to a Memory error */
+#define	C_AFSR_MEMORY	(C_AFSR_UE | C_AFSR_CE | C_AFSR_EMU | C_AFSR_EMC)
+
+/* AFSR bits due to an Mtag error and have a valid MSYND */
+#define	C_AFSR_MSYND_ERRS	(C_AFSR_EMU | C_AFSR_EMC)
+
+/* AFSR bits with a valid ESYND field */
+#define	C_AFSR_ESYND_ERRS	(C_AFSR_UE | C_AFSR_CE | \
+			C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \
+			C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \
+			C_AFSR_IVU | C_AFSR_IVC)
+
+/* AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */
+#define	C_AFSR_LEVEL1	(C_AFSR_UE | C_AFSR_UCU | C_AFSR_EMU | C_AFSR_EDU | \
+			C_AFSR_WDU | C_AFSR_CPU | C_AFSR_IVU | C_AFSR_TO | \
+			C_AFSR_BERR)
+
+#endif	/* CHEETAH_PLUS */
+
+#if defined(JALAPENO) || defined(SERRANO)
+/* AFSR all valid bits (except for ETW) */
+#define	C_AFSR_MASK	(C_AFSR_ALL_ERRS | C_AFSR_PRIV | C_AFSR_B_SYND | \
+			C_AFSR_E_SYND | C_AFSR_AID | C_AFSR_JREQ)
+#else /* JALAPENO || SERRANO */
+/* AFSR all valid bits */
+#define	C_AFSR_MASK	(C_AFSR_ALL_ERRS | C_AFSR_PRIV | C_AFSR_M_SYND | \
+			C_AFSR_E_SYND)
+#endif /* JALAPENO || SERRANO */
+
+/*
+ * Panther AFSR_EXT bits from Disrupting (Corrected) ECC error Trap
+ * (Trap 0x63)
+ */
+#define	C_AFSR_EXT_CECC_ERRS	(C_AFSR_L3_EDU | C_AFSR_L3_EDC | \
+			C_AFSR_L3_WDU | C_AFSR_L3_WDC | C_AFSR_L3_CPU | \
+			C_AFSR_L3_CPC | C_AFSR_L3_THCE)
+
+/*
+ * Panther AFSR_EXT bits from {Instruction,Data}_access_error traps
+ * (Traps 0xa, 0x32)
+ */
+#define	C_AFSR_EXT_ASYNC_ERRS	(C_AFSR_L3_EDU)
+
+/* Panther AFSR_EXT bits from Fast_ECC_error trap (Trap 0x70) */
+#define	C_AFSR_EXT_FECC_ERRS	(C_AFSR_L3_UCU | C_AFSR_L3_UCC)
+
+/* Panther AFSR_EXT bits from Fatal errors (processor asserts ERROR pin) */
+#define	C_AFSR_EXT_FATAL_ERRS	(C_AFSR_L3_TUE | C_AFSR_L3_TUE_SH | \
+			C_AFSR_RED_ERR | C_AFSR_EFA_PAR_ERR)
+
+/* Panther AFSR_EXT all valid error status bits */
+#define	C_AFSR_EXT_ALL_ERRS	(C_AFSR_EXT_FATAL_ERRS | \
+			C_AFSR_EXT_FECC_ERRS | C_AFSR_EXT_CECC_ERRS | \
+			C_AFSR_EXT_ASYNC_ERRS | C_AFSR_L3_MECC)
+
+/* Panther AFSR_EXT bits due to L3 cache errors */
+#define	C_AFSR_EXT_L3_ERRS	(C_AFSR_L3_WDU | C_AFSR_L3_WDC | \
+			C_AFSR_L3_CPU | C_AFSR_L3_CPC | C_AFSR_L3_UCU | \
+			C_AFSR_L3_UCC | C_AFSR_L3_EDU | C_AFSR_L3_EDC | \
+			C_AFSR_L3_TUE | C_AFSR_L3_TUE_SH | C_AFSR_L3_THCE)
+
+/* Panther AFSR_EXT bits with a valid ESYND field */
+#define	C_AFSR_EXT_ESYND_ERRS	(C_AFSR_L3_UCU | C_AFSR_L3_UCC | \
+			C_AFSR_L3_EDU | C_AFSR_L3_EDC | C_AFSR_L3_WDU | \
+			C_AFSR_L3_WDC | C_AFSR_L3_CPU | C_AFSR_L3_CPC)
+
+/* PANTHER AFSR_EXT error bits for AFT Level 1 messages (uncorrected) */
+#define	C_AFSR_EXT_LEVEL1	(C_AFSR_L3_UCU | C_AFSR_L3_EDU | \
+			C_AFSR_L3_WDU | C_AFSR_L3_CPU | C_AFSR_L3_TUE | \
+			C_AFSR_L3_TUE_SH)
+
+/*
+ * AFSR / AFSR_EXT bits for which we need to panic the system.
+ */
+#define	C_AFSR_PANIC(errs)	(((errs) & (C_AFSR_FATAL_ERRS | \
+			C_AFSR_EXT_FATAL_ERRS)) != 0)
+
+/*
+ * For the Fast ECC TL1 handler, we are limited in how many registers
+ * we can use, so we need to store the AFSR_EXT bits within the AFSR
+ * register using some of the AFSR reserved bits.
+ */
+#define	AFSR_EXT_IN_AFSR_MASK	C_AFSR_EXT_ALL_ERRS
+#define	AFSR_EXT_IN_AFSR_SHIFT	20
+
+/*
+ * Defines for the flag field in the CPU logout structure.  See the
+ * definition of ch_cpu_logout_t for further description.
+ */
+#define	CLO_FLAGS_TT_MASK	0xff000
+#define	CLO_FLAGS_TT_SHIFT	12
+#define	CLO_FLAGS_TL_MASK	0xf00
+#define	CLO_FLAGS_TL_SHIFT	8
+#define	CLO_NESTING_MAX		20	/* Arbitrary maximum value */
+
+#define	C_M_SYND_SHIFT	16
+#define	GET_M_SYND(afsr)	(((afsr) & C_AFSR_M_SYND) >> C_M_SYND_SHIFT)
+#define	GET_E_SYND(afsr)	((afsr) & C_AFSR_E_SYND)
+
+/*
+ * Bits of Cheetah Asynchronous Fault Address Register
+ */
+#define	C_AFAR_PA INT64_C(0x000007fffffffff0) /* PA<42:4> physical address */
+
+/*
+ * Defines for the different types of dcache_flush
+ * it is stored in dflush_type
+ */
+#define	FLUSHALL_TYPE	0x0		/* blasts all cache lines */
+#define	FLUSHMATCH_TYPE	0x1		/* flush entire cache but check each */
+					/* each line for a match */
+#define	FLUSHPAGE_TYPE	0x2		/* flush only one page and check */
+					/* each line for a match */
+
+/*
+ * D-Cache Tag Data Register
+ *
+ * +----------+--------+----------+
+ * | Reserved | DC_Tag | DC_Valid |
+ * +----------+--------+----------+
+ *  63	    31 30     1		 0
+ *
+ */
+#define	ICACHE_FLUSHSZ	0x20	/* one line in i$ */
+#define	CHEETAH_DC_VBIT_SHIFT	1
+#define	CHEETAH_DC_VBIT_MASK	0x1
+
+/*
+ * Define for max size of "reason" string in panic flows.  Since this is on
+ * the stack, we want to keep it as small as is reasonable.
+ */
+#define	MAX_REASON_STRING	40
+
+/*
+ * These error types are specific to Cheetah and are used internally for the
+ * Cheetah fault structure flt_type field.
+ */
+#define	CPU_TO			1	/* Timeout */
+#define	CPU_BERR		2	/* Bus Error */
+#define	CPU_CE			3	/* Correctable Memory Error */
+#define	CPU_UE			4	/* Uncorrectable Memory Error */
+#define	CPU_CE_ECACHE		5	/* Correctable Ecache Error */
+#define	CPU_UE_ECACHE		6	/* Uncorrectable Ecache Error */
+#define	CPU_EMC			7	/* Correctable Mtag Error */
+#define	CPU_FATAL		8	/* Fatal Error */
+#define	CPU_ORPH		9	/* Orphaned UCC/UCU error */
+#define	CPU_IV			10	/* IVU or IVC */
+#define	CPU_INV_AFSR		11	/* Invalid AFSR */
+#define	CPU_UE_ECACHE_RETIRE	12	/* Uncorrectable Ecache, retire page */
+#define	CPU_IC_PARITY		13	/* Icache parity error trap */
+#define	CPU_DC_PARITY		14	/* Dcache parity error trap */
+#define	CPU_DUE			15	/* Disrupting UE */
+#define	CPU_FPUERR		16	/* FPU Error */
+/*
+ * These next six error types (17-22) are only used in Jalapeno code
+ */
+#define	CPU_RCE			17	/* Correctable remote memory error */
+#define	CPU_RUE			18	/* Uncorrectable remote memory error */
+#define	CPU_FRC			19	/* Correctable foreign memory error */
+#define	CPU_FRU			20	/* Uncorrectable foreign memory error */
+#define	CPU_BPAR		21	/* Bus parity (BP or WBP) errorrs */
+#define	CPU_UMS			22	/* Unsupported memory store */
+/*
+ * These next four error types (23-26) are only used in Panther code
+ */
+#define	CPU_PC_PARITY		23	/* Pcache parity error */
+#define	CPU_ITLB_PARITY		24	/* Panther ITLB parity error */
+#define	CPU_DTLB_PARITY		25	/* Panther DTLB parity error */
+#define	CPU_L3_ADDR_PE		26	/* Panther L3$ address parity error */
+
+/*
+ * Sets trap table entry ttentry by overwriting eight instructions from ttlabel
+ */
+#define	CH_SET_TRAP(ttentry, ttlabel)			\
+		bcopy((const void *)&ttlabel, &ttentry, 32);		\
+		flush_instr_mem((caddr_t)&ttentry, 32);
+
+/*
+ * Return values for implementation specific error logging in the routine
+ * cpu_impl_async_log_err()
+ */
+#define	CH_ASYNC_LOG_DONE	0	/* finished logging the error */
+#define	CH_ASYNC_LOG_CONTINUE	1	/* continue onto handle panicker */
+#define	CH_ASYNC_LOG_UNKNOWN	2	/* unknown error type */
+#define	CH_ASYNC_LOG_RECIRC	3	/* suppress logging of error */
+
+#ifndef	_ASM
+
+/*
+ * Define Cheetah family (UltraSPARC-III) specific asynchronous error structure
+ */
+typedef struct cheetah_async_flt {
+	struct async_flt cmn_asyncflt;	/* common - see sun4u/sys/async.h */
+	ushort_t flt_type;		/* types of faults - cpu specific */
+	uint64_t flt_bit;		/* fault bit for this log msg */
+	uint64_t afsr_ext;		/* Panther has an AFSR_EXT register */
+	uint64_t afsr_errs;		/* Store all AFSR error bits together */
+	uint64_t afar2;			/* Serrano has an AFAR2 for FRC/FRU */
+	ch_diag_data_t flt_diag_data;	/* Diagnostic data */
+	int flt_data_incomplete;	/* Diagnostic data is incomplete */
+	int flt_trapped_ce;		/* CEEN fault caught by trap handler */
+#if defined(CPU_IMP_L1_CACHE_PARITY)
+	ch_l1_parity_log_t parity_data;	/* L1$ Parity error logging info */
+#endif	/* CPU_IMP_L1_CACHE_PARITY */
+	pn_tlb_logout_t tlb_diag_data;	/* TLB parity error Diagnostic data */
+	uint32_t flt_fpdata[16];	/* Data from fpras failure */
+	uint64_t flt_sdw_afar;		/* Shadow AFAR */
+	uint64_t flt_sdw_afsr;		/* Shadow AFSR */
+	uint64_t flt_sdw_afsr_ext;	/* Shadow Extended AFSR */
+} ch_async_flt_t;
+
+#define	ECC_ALL_TRAPS	(ECC_D_TRAP | ECC_I_TRAP | ECC_C_TRAP | ECC_F_TRAP)
+#define	ECC_ORPH_TRAPS	(ECC_D_TRAP | ECC_I_TRAP | ECC_C_TRAP)
+#define	ECC_ASYNC_TRAPS	(ECC_D_TRAP | ECC_I_TRAP)
+#define	ECC_MECC_TRAPS	(ECC_D_TRAP | ECC_C_TRAP | ECC_F_TRAP)
+
+/*
+ * Error type table struct.
+ */
+typedef struct ecc_type_to_info {
+	uint64_t	ec_afsr_bit;	/* AFSR bit of error */
+	char		*ec_reason;	/* Short error description */
+	uint_t		ec_flags;	/* Trap type error should be seen at */
+	int		ec_flt_type;	/* Used by cpu_async_log_err */
+	char		*ec_desc;	/* Long error description */
+	uint64_t	ec_err_payload;	/* FM ereport payload information */
+	char		*ec_err_class;	/* FM ereport class */
+} ecc_type_to_info_t;
+
+typedef struct bus_config_eclk {
+	uint_t		divisor;
+	uint64_t	mask;
+} bus_config_eclk_t;
+
+#endif /* _ASM */
+
+#endif /* _KERNEL */
+
+#ifndef _ASM
+
+#include <sys/cpuvar.h>
+
+/*
+ * Since all the US3_* files share a bunch of routines between each other
+ * we will put all the "extern" definitions in this header file so that we
+ * don't have to repeat it all in every file.
+ */
+
+/*
+ * functions that are defined in the US3 cpu module:
+ * -------------------------------------------------
+ */
+extern uint64_t get_safari_config(void);
+extern void set_safari_config(uint64_t safari_config);
+extern void shipit(int, int);
+extern void cpu_aflt_log(int ce_code, int tagnum, ch_async_flt_t *aflt,
+    uint_t logflags, const char *endstr, const char *fmt, ...);
+extern uint8_t flt_to_trap_type(struct async_flt *aflt);
+extern char *tag_state_to_desc(uint64_t tagstate);
+extern void cpu_log_err(struct async_flt *aflt);
+extern void cpu_page_retire(ch_async_flt_t *ch_flt);
+extern int clear_errors(ch_async_flt_t *ch_flt);
+extern void cpu_init_ecache_scrub_dr(struct cpu *cp);
+extern void get_cpu_error_state(ch_cpu_errors_t *);
+extern void set_cpu_error_state(ch_cpu_errors_t *);
+extern int cpu_flt_in_memory(ch_async_flt_t *ch_flt, uint64_t t_afsr_bit);
+extern int cpu_queue_events(ch_async_flt_t *ch_flt, char *reason,
+    uint64_t t_afsr, ch_cpu_logout_t *clop);
+extern void cpu_error_ecache_flush(ch_async_flt_t *);
+extern void cpu_clearphys(struct async_flt *aflt);
+extern void cpu_async_log_ic_parity_err(ch_async_flt_t *);
+extern void cpu_async_log_dc_parity_err(ch_async_flt_t *);
+extern uint64_t get_ecache_ctrl(void);
+extern uint64_t get_jbus_config(void);
+extern void set_jbus_config(uint64_t jbus_config);
+extern uint64_t get_mcu_ctl_reg1(void);
+extern void set_mcu_ctl_reg1(uint64_t mcu_ctl);
+extern void cpu_init_trap(void);
+extern int cpu_ecache_nway(void);
+extern void cpu_delayed_logout(size_t, ch_cpu_logout_t *);
+extern void cpu_payload_add_pcache(struct async_flt *, nvlist_t *);
+extern void cpu_payload_add_tlb(struct async_flt *, nvlist_t *);
+extern int cpu_scrub_cpu_setup(cpu_setup_t, int, void *);
+#if defined(JALAPENO) || defined(SERRANO)
+extern int afsr_to_jaid_status(uint64_t afsr, uint64_t afsr_bit);
+#endif	/* JALAPENO || SERRANO */
+/*
+ * Address of the level 15 interrupt handler preamble, used to log Fast ECC
+ * at TL>0 errors, which will be moved to the trap table address above.
+ */
+extern void ch_pil15_interrupt_instr();
+#ifdef CHEETAHPLUS_ERRATUM_25
+extern int mondo_recover(uint16_t, int);
+#endif	/* CHEETAHPLUS_ERRATUM_25 */
+/*
+ * Adddresses of the Fast ECC Error trap handler preambles which will be
+ * moved to the appropriate trap table addresses.
+ */
+extern void fecc_err_instr(void);
+extern void fecc_err_tl1_instr(void);
+extern void fecc_err_tl1_cont_instr(void);
+
+extern int afsr_to_overw_status(uint64_t afsr, uint64_t afsr_bit,
+    uint64_t *ow_bits);
+#if defined(CHEETAH_PLUS)
+extern int afsr_to_pn_esynd_status(uint64_t afsr, uint64_t afsr_bit);
+#endif	/* CHEETAH_PLUS */
+extern void flush_ecache(uint64_t physaddr, size_t ecachesize, size_t linesize);
+extern void flush_dcache(void);
+extern void flush_icache(void);
+extern void flush_pcache(void);
+extern void flush_ipb(void);
+extern uint64_t get_dcu(void);
+extern void set_dcu(uint64_t ncc);
+extern void scrubphys(uint64_t paddr, int ecache_set_size);
+extern void clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize);
+extern void stick_adj(int64_t skew);
+extern void stick_timestamp(int64_t *ts);
+extern void icache_inval_all(void);
+extern void dcache_inval_line(int index);
+extern void ecache_flush_line(uint64_t flushaddr, int ec_size);
+extern int ecache_get_lineinfo(uint32_t ecache_index, uint64_t *tag,
+		uint64_t *data);
+#if defined(CPU_IMP_L1_CACHE_PARITY)
+extern void get_dcache_dtag(uint32_t dcache_idx, uint64_t *data);
+extern void get_icache_dtag(uint32_t icache_idx, uint64_t *data);
+extern void get_pcache_dtag(uint32_t pcache_idx, uint64_t *data);
+extern void correct_dcache_parity(size_t dcache_size, size_t dcache_linesize);
+#endif	/* CPU_IMP_L1_CACHE_PARITY */
+extern void cpu_check_block(caddr_t, uint_t);
+extern uint32_t us3_gen_ecc(uint64_t data_low, uint64_t data_high);
+extern int cpu_impl_async_log_err(void *, errorq_elem_t *);
+extern void cpu_fast_ecc_error(struct regs *rp, ulong_t p_clo_flags);
+extern void cpu_tl1_error(struct regs *rp, int panic);
+extern void cpu_tl1_err_panic(struct regs *rp, ulong_t flags);
+extern void cpu_disrupting_error(struct regs *rp, ulong_t p_clo_flags);
+extern void cpu_deferred_error(struct regs *rp, ulong_t p_clo_flags);
+#if defined(CPU_IMP_L1_CACHE_PARITY)
+extern void cpu_parity_error(struct regs *rp, uint_t flags, caddr_t tpc);
+#endif	/* CPU_IMP_L1_CACHE_PARITY */
+extern void claimlines(uint64_t startpa, size_t len, int stride);
+extern void copy_tsb_entry(uintptr_t src, uintptr_t dest);
+extern void hwblkpagecopy(const void *src, void *dst);
+#if defined(CHEETAH_PLUS)
+extern void pn_cpu_log_diag_l2_info(ch_async_flt_t *ch_flt);
+extern void set_afsr_ext(uint64_t afsr_ext);
+#endif
+extern void cpu_tlb_parity_error(struct regs *rp, ulong_t trap_va,
+    ulong_t tlb_info);
+extern void log_flt_func(struct async_flt *aflt, char *unum);
+extern uint64_t pn_get_tlb_index(uint64_t va, uint64_t pg_sz);
+extern int popc64(uint64_t val);
+
+/*
+ * variables and structures that are defined in the US3 cpu module:
+ * ----------------------------------------------------------------
+ */
+extern bus_config_eclk_t bus_config_eclk[];
+extern ecc_type_to_info_t ecc_type_to_info[];
+extern uint64_t ch_err_tl1_paddrs[];
+extern uchar_t ch_err_tl1_pending[];
+#ifdef CHEETAHPLUS_ERRATUM_25
+/*
+ * Tunable defined in us3_common.c
+ */
+extern int cheetah_sendmondo_recover;
+#endif	/* CHEETAHPLUS_ERRATUM_25 */
+/*
+ * The following allows for a one time calculation of the number of dcache
+ * lines vs. calculating the number every time through the scrub routine.
+ */
+int dcache_nlines;			/* max number of D$ lines */
+
+extern uint64_t afar_overwrite[];
+extern uint64_t esynd_overwrite[];
+extern uint64_t msynd_overwrite[];
+
+#if defined(JALAPENO) || defined(SERRANO)
+extern uint64_t jreq_overwrite[];
+#if defined(SERRANO)
+extern uint64_t	afar2_overwrite[];
+#endif	/* SERRANO */
+#endif	/* JALAPENO || SERRANO */
+
+/*
+ * variables and structures that are defined outside the US3 cpu module:
+ * ---------------------------------------------------------------------
+ */
+extern uint64_t xc_tick_limit;
+extern uint64_t xc_tick_jump_limit;
+extern struct kmem_cache *ch_private_cache;
+
+#if defined(CPU_IMP_L1_CACHE_PARITY)
+/*
+ * Addresses of the Dcache and Icache parity error trap table entries.
+ * If L1 cache parity protection is implemented, need to replace Dcache and
+ * Icache parity error handlers.
+ */
+extern void *tt0_dperr;
+extern void *tt1_dperr;
+extern void *tt1_swtrap1;
+extern void *tt0_iperr;
+extern void *tt1_iperr;
+extern void *tt1_swtrap2;
+/*
+ * Addresses of the Dcache and Icache parity error trap preambles, which will
+ * be moved to the appropriate trap table addresses.
+ */
+extern void dcache_parity_instr();
+extern void dcache_parity_tl1_instr();
+extern void dcache_parity_tl1_cont_instr();
+extern void icache_parity_instr();
+extern void icache_parity_tl1_instr();
+extern void icache_parity_tl1_cont_instr();
+#endif	/* CPU_IMP_L1_CACHE_PARITY */
+
+/*
+ * Addresses of the Fast ECC error trap table entries.
+ */
+extern void *tt0_fecc;
+extern void *tt1_fecc;
+extern void *tt1_swtrap0;
+/*
+ * Address of trap table level 15 interrupt handler in the trap table.
+ */
+extern void *tt_pil15;
+/*
+ * D$ and I$ global parameters.
+ */
+extern int dcache_size;
+extern int dcache_linesize;
+extern int icache_size;
+extern int icache_linesize;
+
+/*
+ * Set of all offline cpus
+ */
+extern cpuset_t cpu_offline_set;
+
+#endif /* _ASM */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* _SYS_US3_MODULE_H */
diff --git a/usr/src/uts/sun4u/sys/us_drv.h b/usr/src/uts/sun4u/sys/us_drv.h
new file mode 100644
index 0000000000..276a29cc00
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/us_drv.h
@@ -0,0 +1,184 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 1999-2003 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_US_DRV_H
+#define	_SYS_US_DRV_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/promif.h>
+#include <sys/cpuvar.h>
+#include <sys/taskq.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifdef _KERNEL
+
+/*
+ * UltraSPARC CPU power management data
+ */
+/*
+ * Data related to a particular speed.
+ *
+ * All per speed data nodes for a CPU are linked together using down_spd.
+ * The link list is ordered with first node containing data for
+ * normal (maximum) speed. up_spd points to the next speed up. Currently
+ * all up_spd's point to the normal speed but this can be changed in future.
+ * quant_cnt is the number of ticks when monitoring system will be called
+ * next. There are different quant_cnt for different speeds.
+ */
+typedef struct us_pm_spd {
+	uint_t			divisor;	/* speed divisor */
+	uint_t			quant_cnt;	/* quantum count in ticks */
+	struct us_pm_spd	*down_spd;	/* ptr to next speed down */
+	struct us_pm_spd	*up_spd;	/* ptr to next speed up */
+	uint_t			idle_hwm;	/* down if idle thread >= hwm */
+	uint_t			idle_lwm;	/* up if idle thread < lwm */
+	uint_t			idle_bhwm_cnt;	/* # of iters idle is < hwm */
+	uint_t			idle_blwm_cnt;	/* # of iters idle is < lwm */
+	uint_t			user_hwm;	/* up if user thread > hwm */
+	int			user_lwm;	/* down if user thread <= lwm */
+	int			pm_level;	/* power level for framework */
+} us_pm_spd_t;
+
+/*
+ * Power management data
+ */
+typedef struct us_pm {
+	us_pm_spd_t	*head_spd;	/* ptr to head of speed */
+	us_pm_spd_t	*cur_spd;	/* ptr to current speed */
+	us_pm_spd_t	*targ_spd;	/* target speed when cur_spd */
+					/* is unknown (i.e. NULL) */
+	uint_t		num_spd;	/* number of speeds */
+	uint_t		lastquan_idle;	/* last quantum's CPU_IDLE timestamp */
+	uint_t		lastquan_user;	/* last quantum's CPU_USER timestamp */
+	clock_t		lastquan_lbolt;	/* last quantum's lbolt */
+	int		pm_busycnt;	/* pm_busy_component() count  */
+	taskq_t		*tq;		/* taskq handler for CPU monitor */
+	timeout_id_t	timeout_id;	/* us_pm_monitor()'s timeout_id */
+	int		timeout_count;	/* count dispatched timeouts */
+	kmutex_t	timeout_lock;	/* protect timeout_count */
+	kcondvar_t	timeout_cv;	/* wait on timeout_count change */
+} us_pm_t;
+
+/*
+ * Idle & user threads water marks in percentage
+ */
+#define	US_PM_IDLE_LWM		8	/* idle low water mark */
+#define	US_PM_IDLE_HWM		98	/* idle high water mark */
+#define	US_PM_USER_HWM		20	/* user high water mark */
+#define	US_PM_IDLE_BUF_ZONE	4	/* buffer zone when going down */
+
+#define	US_PM_IDLE_BLWM_CNT_MAX	2	/* # of iters idle can be < lwm */
+#define	US_PM_IDLE_BHWM_CNT_MAX	2	/* # of iters idle can be < hwm */
+
+/*
+ * Maximums for creating 'pm-components' property
+ */
+#define	US_PM_COMP_MAX_DIG	4	/* max digits in power level */
+					/* or divisor */
+#define	US_PM_COMP_MAX_VAL	9999	/* max value in above digits */
+
+/*
+ * Component number for calls to PM framework
+ */
+#define	US_PM_COMP_NUM		0	/* first component is 0 */
+
+/*
+ * Quantum counts for normal and other clock speeds in terms of ticks.
+ *
+ * In determining the quantum count, we need to balance two opposing factors:
+ *
+ *	1) Minimal delay when user start using the CPU that is in low
+ *	power mode -- requires that we monitor more frequently,
+ *
+ *	2) Extra code executed because of frequent monitoring -- requires
+ *	that we monitor less frequently.
+ *
+ * We reach a tradeoff between these two requirements by monitoring
+ * more frequently when we are in low speed mode (US_PM_QUANT_CNT_OTHR)
+ * so we can bring the CPU up without user noticing it. Moreover, at low
+ * speed we are not using CPU much so extra code execution should be fine.
+ * Since we are in no hurry to bring CPU down and at normal speed and we
+ * might really be using the CPU fully, we monitor less frequently
+ * (US_PM_QUANT_CNT_NORMAL).
+ */
+#define	US_PM_QUANT_CNT_NORMAL	(hz * 5)		/* 5 sec */
+#define	US_PM_QUANT_CNT_OTHR	(hz * 1)		/* 1 sec */
+
+/*
+ * Taskq parameters
+ */
+#define	US_PM_TASKQ_THREADS	1	/* # threads to run CPU monitor */
+#define	US_PM_TASKQ_MIN		2	/* min # of taskq entries */
+#define	US_PM_TASKQ_MAX		2	/* max # of taskq entries */
+
+
+/*
+ * Device driver state structure
+ */
+typedef struct us_devstate {
+	dev_info_t	*dip;		/* devinfo handle */
+	processorid_t	cpu_id;		/* CPU number for this node */
+	us_pm_t		us_pm;		/* power management data */
+	kmutex_t	lock;		/* protects state struct */
+} us_devstate_t;
+
+
+
+/*
+ * Debugging definitions
+ */
+#ifdef	DEBUG
+#define	D_INIT			0x00000001
+#define	D_FINI			0x00000002
+#define	D_ATTACH		0x00000004
+#define	D_DETACH		0x00000008
+#define	D_POWER			0x00000010
+#define	D_PM_INIT		0x00000020
+#define	D_PM_FREE		0x00000040
+#define	D_PM_COMP_CREATE	0x00000080
+#define	D_PM_MONITOR		0x00000100
+#define	D_PM_MONITOR_VERBOSE	0x00000200
+#define	D_PM_MONITOR_DELAY	0x00000400
+
+extern uint_t	us_drv_debug;
+
+#define	_PRINTF prom_printf
+#define	DPRINTF(flag, args)	if (us_drv_debug & flag) _PRINTF args;
+#else
+#define	DPRINTF(flag, args)
+#endif /* DEBUG */
+
+#endif /* _KERNEL */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _SYS_US_DRV_H */
diff --git a/usr/src/uts/sun4u/sys/wci_cmmu.h b/usr/src/uts/sun4u/sys/wci_cmmu.h
new file mode 100644
index 0000000000..d43d07dd3c
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wci_cmmu.h
@@ -0,0 +1,181 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ * Automatically Generated file based on CSR definitions
+ *
+ */
+
+/*
+ * This file automatically generated from
+ *    wci_sram.csr
+ *    03/27/2000 13:46:00
+ *    Using  ./csr_filter.pl by pcw
+ */
+
+/* **DO NOT EDIT THIS FILE**  */
+/*
+ * File ../../../design/wci/include/cmmu.h *
+ */
+
+#ifndef _SYS_WCI_CMMU_H
+#define	_SYS_WCI_CMMU_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Include any headers you depend on.
+ */
+
+
+
+/*
+ * wci_sram_array_as_cmmu_1_addr
+ */
+typedef union {
+	struct wci_sram_array_as_cmmu_1_addr {
+		uint32_t error				: 1;	/* 63 */
+		uint32_t filler				: 15;	/* 62:48 */
+		uint32_t ecc_syndrome			: 7;	/* 47:41 */
+		uint32_t ecc_check			: 7;	/* 40:34 */
+		uint32_t reserved1			: 2;	/* 33:32 */
+		uint32_t reserved2			: 3;	/* 31:29 */
+		uint32_t lpa_page			: 29;	/* 28:0 */
+	} bit;
+	uint64_t val;
+} wci_sram_array_as_cmmu_1_addr_u;
+
+#define	wci_sram_array_as_cmmu_1_addr_error	\
+	bit.error
+#define	wci_sram_array_as_cmmu_1_addr_ecc_syndrome	\
+	bit.ecc_syndrome
+#define	wci_sram_array_as_cmmu_1_addr_ecc_check	\
+	bit.ecc_check
+#define	wci_sram_array_as_cmmu_1_addr_reserved	\
+	bit.reserved
+#define	wci_sram_array_as_cmmu_1_addr_lpa_page	\
+	bit.lpa_page
+
+
+/*
+ * wci_sram_array_as_cmmu_1_int
+ */
+typedef union {
+	struct wci_sram_array_as_cmmu_1_int {
+		uint32_t error				: 1;	/* 63 */
+		uint32_t filler				: 15;	/* 62:48 */
+		uint32_t ecc_syndrome			: 7;	/* 47:41 */
+		uint32_t ecc_check			: 7;	/* 40:34 */
+		uint32_t reserved1			: 2;	/* 33:32 */
+		uint32_t reserved2			: 3;	/* 31:29 */
+		uint32_t lpa_page_1			: 2;	/* 28:27 */
+		uint32_t mondo				: 16;	/* 26:11 */
+		uint32_t lpa_page_2			: 11;	/* 10:0 */
+	} bit;
+	uint64_t val;
+} wci_sram_array_as_cmmu_1_int_u;
+
+#define	wci_sram_array_as_cmmu_1_int_error	\
+	bit.error
+#define	wci_sram_array_as_cmmu_1_int_ecc_syndrome	\
+	bit.ecc_syndrome
+#define	wci_sram_array_as_cmmu_1_int_ecc_check	\
+	bit.ecc_check
+#define	wci_sram_array_as_cmmu_1_int_reserved	\
+	bit.reserved
+#define	wci_sram_array_as_cmmu_1_int_lpa_page_1	\
+	bit.lpa_page_1
+#define	wci_sram_array_as_cmmu_1_int_mondo	\
+	bit.mondo
+#define	wci_sram_array_as_cmmu_1_int_lpa_page_2	\
+	bit.lpa_page_2
+
+
+/*
+ * wci_sram_array_as_cmmu_0
+ */
+typedef union {
+	struct wci_sram_array_as_cmmu_0 {
+		uint32_t error				: 1;	/* 63 */
+		uint32_t filler				: 15;	/* 62:48 */
+		uint32_t ecc_syndrome			: 7;	/* 47:41 */
+		uint32_t ecc_check			: 7;	/* 40:34 */
+		uint32_t reserved1			: 2;	/* 33:31 */
+		uint32_t reserved2			: 3;	/* 31:29 */
+		uint32_t writable			: 1;	/* 28 */
+		uint32_t from_all			: 1;	/* 27 */
+		uint32_t valid				: 1;	/* 26 */
+		uint32_t type				: 2;	/* 25:24 */
+		uint32_t from_node			: 8;	/* 23:16 */
+		uint32_t atomic_orig_id			: 12;	/* 15:4 */
+		uint32_t count_enable			: 1;	/* 3 */
+		uint32_t large_page			: 1;	/* 2 */
+		uint32_t user_err			: 1;	/* 1 */
+		uint32_t lpa_page			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sram_array_as_cmmu_0_u;
+
+#define	wci_sram_array_as_cmmu_0_error	\
+	bit.error
+#define	wci_sram_array_as_cmmu_0_ecc_syndrome	\
+	bit.ecc_syndrome
+#define	wci_sram_array_as_cmmu_0_ecc_check	\
+	bit.ecc_check
+#define	wci_sram_array_as_cmmu_0_reserved	\
+	bit.reserved
+#define	wci_sram_array_as_cmmu_0_writable	\
+	bit.writable
+#define	wci_sram_array_as_cmmu_0_from_all	\
+	bit.from_all
+#define	wci_sram_array_as_cmmu_0_valid	\
+	bit.valid
+#define	wci_sram_array_as_cmmu_0_type	\
+	bit.type
+#define	wci_sram_array_as_cmmu_0_from_node	\
+	bit.from_node
+#define	wci_sram_array_as_cmmu_0_atomic_orig_id	\
+	bit.atomic_orig_id
+#define	wci_sram_array_as_cmmu_0_count_enable	\
+	bit.count_enable
+#define	wci_sram_array_as_cmmu_0_large_page	\
+	bit.large_page
+#define	wci_sram_array_as_cmmu_0_user_err	\
+	bit.user_err
+#define	wci_sram_array_as_cmmu_0_lpa_page	\
+	bit.lpa_page
+
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_WCI_CMMU_H */
diff --git a/usr/src/uts/sun4u/sys/wci_common.h b/usr/src/uts/sun4u/sys/wci_common.h
new file mode 100644
index 0000000000..5b0cfaf5c4
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wci_common.h
@@ -0,0 +1,840 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _WCI_COMMON_H
+#define	_WCI_COMMON_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/kstat.h>
+#include <sys/wci_offsets.h>
+
+/*
+ * From PRM, 0 indicates a paroli that is present. This is set in
+ * Wci register:  wci_sw_link_status, field: paroli_present
+ * such that, when paroli_present == 0 the paroli IS present.
+ */
+#define	WCI_PAROLI_PRESENT	0
+
+#define	WCI_ID_WCI1		0x14776049
+#define	WCI_ID_WCI2		0x14147049
+#define	WCI_ID_WCI3		0x14063049
+#define	WCI_ID_WCI31		0x24063049
+#define	WCI_ID_WCI4		0x14478049
+#define	WCI_ID_WCI41		0x24478049
+
+/* stripe bits */
+#define	WCI_OFF			0x0
+#define	WCI_STRIPE_NONE		0xf
+#define	WCI_STRIPE_2WAY_EVEN	0x3
+#define	WCI_STRIPE_2WAY_ODD	0xc
+#define	WCI_STRIPE_4WAY_0	0x1
+#define	WCI_STRIPE_4WAY_1	0x2
+#define	WCI_STRIPE_4WAY_2	0x4
+#define	WCI_STRIPE_4WAY_3	0x8
+
+/* For cluster mode striping, WCI uses addr bits 7 and 8, link uses 9 and 10 */
+#define	WCI_CLUSTER_STRIPE_STRIDE	(1 << 7)
+#define	WCI_CLUSTER_STRIPE_MASK		0x0780 /* Bits 7-10 set */
+
+#define	WCI_ERRPAGE_CESR_OFFSET		0
+#define	WCI_ERRPAGE_CLUSTER_ERROR_OFFSET 64	/* byte offset into CESR page */
+
+/* CESR values */
+#define	WCI_CESR_NO_ERRORS		0x0
+#define	WCI_CESR_PASSTHRU_CAG_ERROR	0x1
+#define	WCI_CESR_CMMU_ACCESS_VIOLATION	0x2
+#define	WCI_CESR_DEST_CAG_BUSY		0x3
+#define	WCI_CESR_USER_ERROR_BIT_SET	0x4
+#define	WCI_CESR_PAUSE_REPLY		0x5
+#define	WCI_CESR_PASSTHRU_RAG_ERROR	0x6
+#define	WCI_CESR_TOO_MANY_PASSTHRU_HOPS	0x7
+#define	WCI_CESR_INTR_DEST_BUSY		0x8
+#define	WCI_CESR_INVALID_TRANSACTION	0x9
+#define	WCI_CESR_RAG_READ_TIMEOUT	0xA
+#define	WCI_CESR_RAG_DATA_ERROR		0xB
+#define	WCI_CESR_RAG_WRITE_TIMEOUT	0xC
+#define	WCI_CESR_RESERVED_13		0xD
+#define	WCI_CESR_RESERVED_14		0xE
+#define	WCI_CESR_RESERVED_15		0xF
+#define	WCI_CESR_BUSY_TOO_LONG		(-1) /* Software can't read CESR */
+
+#define	WCI_NUM_LINKS	ENTRIES_WCI_SW_LINK_ERROR_COUNT
+
+/* WCI ECC error handling support */
+
+/* this is needed for number of errors */
+#define	ECC_MAX_CNT		0xff /* maximum ecc count */
+/*
+ * PA[42:4] represent the address fields defined in Safari interface.
+ * In cacheable address space or flush address space, PA[41:38] represents
+ * the SSM node id
+ */
+#define	SAFARI_ADDR_FIELDS_MASK	0x000007FFFFFFFFF0ULL
+#define	WCI_ECC_NODE_ID_MASK	0x000003C000000000ULL
+
+/*
+ * In wci_dco_state, the following bit fields indentify Agent ID.
+ *
+ * mtag_ecc_error_aid  <41:35>
+ * data_ecc_error_aid  <34:28>
+ *
+ * Agent ID for Mtag/data ecc error encoding is in
+ * binary, where "nnn" denote instance id used by the agent :
+ *
+ * 0000000 = rsrvd
+ * 0000001 = Csr_Agent
+ * 0000010 = Modifier_Logic
+ * 0000011-0010111 = rsrvd
+ * 0011nnn = Slave_Agent
+ * 01nnnnn = Request_Agent
+ * 10nnnnn = Cluster_Agent
+ * 11nnnnn = Home_Agent
+ *
+ */
+#define	CSR_AGENT_MASK	0x01
+#define	SLAVE_AGENT_MASK	0x18
+#define	REQUEST_AGENT_MASK	0x20
+#define	CLUSTER_AGENT_MASK	0x40
+#define	HOME_AGENT_MASK		0x60
+#define	REQ_CLUSTER_MASK	0x60
+
+#define	CSR_AGENT	1
+#define	SLAVE_AGENT	2
+#define	REQUEST_AGENT	3
+#define	CLUSTER_AGENT	4
+#define	HOME_AGENT	5
+
+#define	ECC_MTAG_UE	1
+#define	ECC_MTAG_CE	2
+#define	ECC_DATA_UE	3
+#define	ECC_DATA_CE	4
+
+
+/*
+ * define which agent has what type of ECC error so that
+ * we can log them explicitely in wci_log_ce_error().
+ *
+ * when calling ce_error(), cheetah has to make a distinction when decoding
+ * the syndrome of the error: data or mtag. in order to comply with cheetah
+ * semantics, we set the high bits of the flt_stat field similar to afsr reg:
+ */
+
+#define	RA_ECC_MTAG_UE	(0x1 | C_AFSR_EMU)
+#define	RA_ECC_MTAG_CE	(0x2 | C_AFSR_EMC)
+#define	RA_ECC_DATA_UE	(0x4 | C_AFSR_UE)
+#define	RA_ECC_DATA_CE	(0x8 | C_AFSR_CE)
+
+#define	HA_ECC_MTAG_UE	(0x10 | C_AFSR_EMU)
+#define	HA_ECC_MTAG_CE	(0x20 | C_AFSR_EMC)
+#define	HA_ECC_DATA_UE	(0x40 | C_AFSR_UE)
+#define	HA_ECC_DATA_CE	(0x80 | C_AFSR_CE)
+
+#define	SA_ECC_MTAG_UE	(0x100 | C_AFSR_EMU)
+#define	SA_ECC_MTAG_CE	(0x200 | C_AFSR_EMC)
+#define	SA_ECC_DATA_UE	(0x400 | C_AFSR_UE)
+#define	SA_ECC_DATA_CE	(0x800 | C_AFSR_CE)
+
+#define	CA_ECC_MTAG_UE	(0x1000 | C_AFSR_EMU)
+#define	CA_ECC_MTAG_CE	(0x2000 | C_AFSR_EMC)
+#define	CA_ECC_DATA_UE	(0x4000 | C_AFSR_UE)
+#define	CA_ECC_DATA_CE	(0x8000 | C_AFSR_CE)
+
+#define	CA_ECC_NOTPASS	0x10000
+
+/*
+ * define which type of SRAM error occured
+ */
+#define	SRAM_ECC_CE_DATA	0x20000
+#define	SRAM_ECC_UE_ADDR	0x40000
+#define	SRAM_ECC_UE_CAG		0x80000
+#define	SRAM_ECC_UE_CSRA	0x100000
+#define	SRAM_ECC_UE_RAG		0x200000
+#define	SRAM_ECC_UE_SAG		0x400000
+#define	SRAM_PARITY_HAG		0x800000
+
+/*
+ * need ECC error status - ecc.status for wci, plan to add in async.h,
+ * for now, we just add here
+ */
+#define	ECC_WCI		0x80
+#define	ECC_WCI_SRAM	0x200
+/*
+ * register wci_dco_state logs only mtag/data first CE (UE overwrites CE)
+ * syndrome for all agent types. Thus, except 1st error, all other ECC
+ * errors don't have a syndrome corresponding with them, thus NO_SYNDROME
+ * for these NO_SYNDROME ECC errors, even we schedule scrubbing, they can't
+ * be scrubbed i.e, corrected, because of no syndrome
+ *
+ */
+#define	NO_SYNDROME	-1
+
+/*
+ * syndrome can be logged in either part of the wci_dco_state register
+ * depending on which cacheline it came from
+ */
+#define	WCI_MTAG_SYNDROME(r) \
+	(r.bit.mtag_syndrome_0 ? r.bit.mtag_syndrome_0 : r.bit.mtag_syndrome_1)
+#define	WCI_DATA_SYNDROME(r) \
+	(r.bit.data_syndrome_0 ? r.bit.data_syndrome_0 : r.bit.data_syndrome_1)
+
+#define	WCI_CTRCTL_KSTAT_NAMED  "pcr"           /* "wci_ctr_ctl" */
+#define	WCI_CTR0_KSTAT_NAMED    "pic0"          /* "wci_ctr0" */
+#define	WCI_CTR1_KSTAT_NAMED    "pic1"          /* "wci_ctr1" */
+
+#define	WCI_NUM_PICS    2
+#define	WCI_MISC_NUM_EVENTS  350  /* Max number of events in Misc Counter */
+#define	WCI_LINK_NUM_EVENTS  0x13 /* Max number of events in Link Counter */
+#define	WCI_LPBK_NUM_EVENTS  0x17 /* Max number of events in Lpbk Counter */
+
+#define	WCI_SFI_NUM_EVENTS   0xb /* Max # of evts in safari histogram counter */
+
+
+#define	WCI_DURATION_BIT	0x100000
+
+#define	WCI_PIC0_MASK	0x00000000FFFFFFFFULL  /* pic0 bits of %pic */
+#define	WCI_PIC0_CTR_CTL_MASK	0x000000000000FFFFULL
+#define	WCI_PIC1_CTR_CTL_MASK	0x00000000FFFF0000ULL
+#define	WCI_CLUSTER_MASK	0x00000000000000FFULL
+
+/*
+ * used to build array of event-names and pcr-mask values
+ */
+typedef struct wci_event_mask {
+	char *event_name;
+	uint64_t pcr_mask;
+} wci_event_mask_t;
+
+
+/* common soft state hook for either wrsm or wssm */
+struct wci_common_soft_state {
+	int instance;  /* device instance */
+	int node_id;    /* ssm node id */
+	uint32_t local_aid;  /* safari local agent id */
+	volatile unsigned char *wci_regs;  /* vaddr of wrsm/wssm base regs */
+	/* Mapped addresses of registers */
+	volatile uint64_t *wci_misc_ctr_vaddr;
+	volatile uint64_t *wci_misc_ctr_ctl_vaddr;
+	volatile uint64_t *wci_cluster_ctr_ctl_vaddr;
+	volatile uint64_t *wci_link_ctr_vaddr[WCI_NUM_LINKS];
+	volatile uint64_t *wci_link_ctr_ctl_vaddr[WCI_NUM_LINKS];
+	volatile uint64_t *wci_lpbk_ctr_vaddr;
+	volatile uint64_t *wci_lpbk_ctr_ctl_vaddr;
+	volatile uint64_t *wci_sfi_ctr0_mask_vaddr;
+	volatile uint64_t *wci_sfi_ctr0_match_vaddr;
+	volatile uint64_t *wci_sfi_ctr0_match_transaction_vaddr;
+	volatile uint64_t *wci_sfi_ctr1_mask_vaddr;
+	volatile uint64_t *wci_sfi_ctr1_match_vaddr;
+	volatile uint64_t *wci_sfi_ctr1_match_transaction_vaddr;
+	/* performace counters kstat */
+	kstat_t *wci_misc_counters_ksp;
+	kstat_t *wci_lpbk_counters_ksp;
+	kstat_t *wci_link_counters_ksp[WCI_NUM_LINKS];
+	/* wci safari histogramming kstat */
+	kstat_t *wci_sfi_counters_ksp;
+	/*
+	 * wci safari histogramming counter control value.  It is a
+	 * software simulation of a hardware counter control register
+	 * to make busstat happy.
+	 */
+	uint64_t wci_sfi_sw_ctr_ctl;
+
+
+	/* A running SUM of the number of link errors since power-on */
+	uint64_t wci_sw_link_error_count_sum[WCI_NUM_LINKS];
+
+} wci_common_softstate_t;
+
+
+/*
+ * Global Function prototypes
+ */
+void wci_add_counters_kstats(struct wci_common_soft_state *, char *drvname);
+void wci_add_picN_kstats(char *drvname);
+void wci_del_counters_kstats(struct wci_common_soft_state *);
+void wci_del_picN_kstats();
+struct async_flt;
+void wci_log_ce_error(struct async_flt *ecc, char *unum);
+
+/*
+ * Misc Counter
+ * Agent Type -- 0: SFI, 1: Cluster Agent, 2: DC, 3: Request Agent,
+ *               4: Home Agent, 5: Slave Agent, 6: Cache Controller,
+ *               7: SFQ, 8: HLI, 9: LC
+ */
+/* SFI Event Control --- agent = 0 */
+/* Safari Event Encoding */
+#define	SFI_SFI_HISTOGRAM0	0x000
+#define	SFI_SFI_HISTOGRAM1	0x001
+#define	SFI_ATRANSID_ALLOC_1	0x002
+#define	SFI_ATRANSID_ALLOC_4	0x003
+#define	SFI_ATRANSID_ALLOC_8	0x004
+#define	SFI_ATRANSID_ALLOC_10	0x005
+#define	SFI_ATRANSID_ALLOC_12	0x006
+#define	SFI_ATRANSID_DEALLOC	0x007
+#define	SFI_TARGID_ALLOC_0	0x008
+#define	SFI_TARGID_ALLOC_2	0x009
+#define	SFI_TARGID_ALLOC_8	0x00a
+#define	SFI_TARGID_DEALLOC	0x00b
+#define	SFI_P0_REQ_VALID	0x00c
+#define	SFI_P1_REQ_VALID	0x00d
+#define	SFI_P2_REQ_VALID	0x00e
+#define	SFI_P3_REQ_VALID	0x00f
+#define	SFI_P4_REQ_VALID	0x010
+#define	SFI_P5_REQ_VALID	0x011
+#define	SFI_P6_REQ_VALID	0x012
+#define	SFI_P7_REQ_VALID	0x013
+#define	SFI_P8_REQ_VALID	0x014
+#define	SFI_P9_REQ_VALID	0x015
+#define	SFI_P10_REQ_VALID	0x016
+#define	SFI_P11_REQ_VALID	0x017
+#define	SFI_P12_REQ_VALID	0x018
+#define	SFI_P0_GRANT	0x019
+#define	SFI_P1_GRANT	0x01a
+#define	SFI_P2_GRANT	0x01b
+#define	SFI_P3_GRANT	0x01c
+#define	SFI_P4_GRANT	0x01d
+#define	SFI_P5_GRANT	0x01e
+#define	SFI_P6_GRANT	0x01f
+#define	SFI_P7_GRANT	0x020
+#define	SFI_P8_GRANT	0x021
+#define	SFI_P9_GRANT	0x022
+#define	SFI_P10_GRANT	0x023
+#define	SFI_P11_GRANT	0x024
+#define	SFI_P12_GRANT	0x025
+#define	SFI_SFI_PULL_REQ	0x026
+#define	SFI_SFI_PULL_GRANT	0x027
+/* Safari Durations */
+/* cnt1 */
+#define	SFI_ATRANSID_ALLOC_1_DURATION	0x00100800
+#define	SFI_ATRANSID_ALLOC_4_DURATION	0x00100c00
+#define	SFI_ATRANSID_ALLOC_8_DURATION	0x00101000
+#define	SFI_ATRANSID_ALLOC_10_DURATION	0x00101400
+#define	SFI_ATRANSID_ALLOC_12_DURATION	0x00101800
+#define	SFI_TARGID_ALLOC_0_DURATION	0x00102000
+#define	SFI_TARGID_ALLOC_2_DURATION	0x00102400
+#define	SFI_TARGID_ALLOC_8_DURATION	0x00102800
+/* cnt 0 */
+#define	SFI_ATRANSID_DEALLOC_DURATION	0x00100007
+#define	SFI_TARGID_DEALLOC_DURATION	0x0010000b
+
+/* DC Event Control ---  agent = 2 */
+/* DC Event Encoding */
+#define	DC_DIF_OUTPUT_VALID	0x080
+#define	DC_SFI_DATA_GRANT	0x081
+
+/* LC Event Count --- agent = 9 */
+/* LC Event Encoding */
+#define	LC_DIF_PUSH	0x240
+#define	LC_COM_VALID_LINKS_DIF_FULL	0x241
+#define	LC_DATA_PKT_FR_NODE	0x242
+#define	LC_SFI_DATA_CANCEL	0x243
+
+/* SFQ Event Control --- agent = 7 */
+/* SFQ Event Encoding */
+#define	SFQ_PIQ_PUSH	0x1c0
+#define	SFQ_PIQ_POP	0x1c1
+#define	SFQ_NIQ_PUSH	0x1c2
+#define	SFQ_NIQ_POP	0x1c3
+#define	SFQ_SIQ_PUSH	0x1c4
+#define	SFQ_SIQ_POP	0x1c5
+
+/* HLI Event Control --- agent = 8 */
+/* HLI Event Encoding */
+#define	HLI_SLQ_PUSH	0x200
+#define	HLI_SLQ_POP	0x201
+#define	HLI_CHQ_PUSH	0x202
+#define	HLI_CHQ_POP	0x203
+#define	HLI_PHQ_PUSH	0x204
+#define	HLI_PHQ_POP	0x205
+
+/* Cacahe Controller Event Control --- agent = 6 */
+/* Cache Control Event Encoding */
+#define	CACHECTL_CLUST0	0x180
+#define	CACHECTL_CLUST1	0x181
+#define	CACHECTL_CLUST_CWR	0x01000000ULL
+#define	CACHECTL_CLUST_CRD	0x02000000ULL
+#define	CACHECTL_CLUST_CRD_CWR	0x03000000ULL
+#define	CACHECTL_CLUST_AT	0x04000000
+#define	CACHECTL_CLUST_AT_CWR	0x05000000ULL
+#define	CACHECTL_CLUST_AT_CRD	0x06000000ULL
+#define	CACHECTL_CLUST_AT_CRD_CWR	0x07000000ULL
+#define	CACHECTL_CLUST_INT	0x08000000ULL
+#define	CACHECTL_CLUST_INT_CWR	0x09000000ULL
+#define	CACHECTL_CLUST_INT_CRD	0x0a000000ULL
+#define	CACHECTL_CLUST_INT_CRD_CWR	0x0b000000ULL
+#define	CACHECTL_CLUST_INT_AT	0x0c000000ULL
+#define	CACHECTL_CLUST_INT_AT_CWR	0x0d000000ULL
+#define	CACHECTL_CLUST_INT_AT_CRD	0x0e000000ULL
+#define	CACHECTL_CLUST_INT_AT_CRD_CWR	0x0f000000ULL
+#define	CACHECTL_CACHE_CYL_USED	0x182
+#define	CACHECTL_LPA2GA_LOOKUP	0x183
+#define	CACHECTL_GA2LPA_ACCESS	0x184
+#define	CACHECTL_GA2LPA_LOOKUP	0x185
+#define	CACHECTL_GA2LPA_MISS	0x186
+#define	CACHECTL_DIR_LOOKUP	0x187
+#define	CACHECTL_DIR_MISS	0x188
+#define	CACHECTL_DIR_WRTBK	0x189
+#define	CACHECTL_CMMU_ACCESS	0x18a
+#define	CACHECTL_CMMU_LOOKUP	0x18b
+#define	CACHECTL_CSR_LOOKUP	0x18c
+#define	CACHECTL_CNT_ALWYS	0x18d
+#define	CACHECTL_HAG_REQ_VALID	0x18e
+#define	CACHECTL_CIQ_REQ_VALID	0x18f
+#define	CACHECTL_SLQ_REQ_VALID	0x190
+
+/* Cluster Agent Event Control --- agent = 1 */
+/* Cluster Agent Event Encoding */
+#define	CLUSTER_AGENT_ALLOC	0x040
+#define	CLUSTER_AGENT_RETIRED	0x041
+#define	CLUSTER_SFI_GRANT_RD	0x042
+#define	CLUSTER_SFI_GRANT_WR	0x043
+#define	CLUSTER_PULL_SEEN	0x044
+#define	CLUSTER_1DC_RCV_ACK	0x045
+#define	CLUSTER_2DC_SND_ACK	0x046
+#define	CLUSTER_1_CPI_RCV_ACK	0x047
+#define	CLUSTER_2_CPI_RCV_ACK	0x048
+#define	CLUSTER_PKT_QUE_ODD	0x049
+#define	CLUSTER_PKT_QUE_EVEN	0x04a
+#define	CLUSTER_PKT_SENT_ODD	0x04b
+#define	CLUSTER_PKT_SENT_EVEN	0x04c
+#define	CLUSTER_HLI_REQ_0	0x04d
+#define	CLUSTER_HLI_REQ_1	0x04e
+#define	CLUSTER_HLI_REQ_2	0x04f
+#define	CLUSTER_HLI_REQ_3	0x050
+#define	CLUSTER_HLI_REQ_4	0x051
+#define	CLUSTER_HLI_REQ_5	0x052
+#define	CLUSTER_HLI_GRANT_0	0x053
+#define	CLUSTER_HLI_GRANT_1	0x054
+#define	CLUSTER_HLI_GRANT_2	0x055
+#define	CLUSTER_HLI_GRANT_3	0x056
+#define	CLUSTER_HLI_GRANT_4	0x057
+#define	CLUSTER_HLI_GRANT_5	0x058
+/* Cluster Agent Durations */
+/* cnt1 */
+#define	CLUSTER_AGENT_ALLOC_DURATION	0x00110000
+#define	CLUSTER_SFI_GRANT_RD_DURATION	0x00110800
+#define	CLUSTER_SFI_GRANT_WR_DURATION	0x00110c00
+#define	CLUSTER_1DC_RCV_ACK_CNT1_DURATION	0x00111400
+#define	CLUSTER_PKT_QUE_ODD_DURATION	0x00112400
+#define	CLUSTER_PKT_QUE_EVEN_DURATION	0x00112800
+#define	CLUSTER_HLI_GRANT_0_DURATION	0x00114c00
+#define	CLUSTER_HLI_GRANT_1_DURATION	0x00115000
+#define	CLUSTER_HLI_GRANT_2_DURATION	0x00115400
+#define	CLUSTER_HLI_GRANT_3_DURATION	0x00115800
+#define	CLUSTER_HLI_GRANT_4_DURATION	0x00115c00
+#define	CLUSTER_HLI_GRANT_5_DURATION	0x00116000
+#define	CLUSTER_1_CPI_RCV_ACK_CNT1_DURATION	0x00111c00
+/* cnt0 */
+#define	CLUSTER_AGENT_RETIRED_DURATION	0x00100041
+#define	CLUSTER_PULL_SEEN_DURATION	0x00100044
+#define	CLUSTER_1DC_RCV_ACK_CNT0_DURATION	0x00100045
+#define	CLUSTER_2DC_SND_ACK_DURATION	0x00100046
+#define	CLUSTER_PKT_SENT_ODD_DURATION	0x0010004b
+#define	CLUSTER_PKT_SENT_EVEN_DURATION	0x0010004c
+#define	CLUSTER_1_CPI_RCV_ACK_CNT0_DURATION	0x00100047
+#define	CLUSTER_2_CPI_RCV_ACK_DURATION	0x00100048
+
+
+/* Request Agent Event Control --- agent = 3 */
+/* Request Agent Event Encoding */
+#define	REQ_AGENT_ALLOC	0x0c0
+#define	REQ_AGENT_RETIRED	0x0c1
+#define	REQ_SFI_GRANT_P2	0x0c2
+#define	REQ_1DC_RCV_ACK	0x0c3
+#define	REQ_2DC_SND_ACK	0x0c4
+#define	REQ_1_CPI_RCV_ACK	0x0c5
+#define	REQ_2_CPI_RCV_ACK	0x0c6
+#define	REQ_PKT_QUE	0x0c7
+#define	REQ_PKT_SENT	0x0c8
+#define	REQ_PKT_SENT_CLUST_RD	0x0c9
+#define	REQ_PKT_SENT_CLUST_WR	0x0ca
+#define	REQ_HLI_REQ_0	0x0cb
+#define	REQ_HLI_REQ_1	0x0cc
+#define	REQ_HLI_REQ_2	0x0cd
+#define	REQ_HLI_REQ_3	0x0ce
+#define	REQ_HLI_REQ_4	0x0cf
+#define	REQ_HLI_REQ_5	0x0d0
+#define	REQ_HLI_GRANT_0	0x0d1
+#define	REQ_HLI_GRANT_1	0x0d2
+#define	REQ_HLI_GRANT_2	0x0d3
+#define	REQ_HLI_GRANT_3	0x0d4
+#define	REQ_HLI_GRANT_4	0x0d5
+#define	REQ_HLI_GRANT_5	0x0d6
+#define	REQ_LAST_REPLY_RCVD	0x0d7
+#define	REQ_SENT_CLUST_RD	0x0d8
+#define	REQ_SENT_CLUST_WR	0x0d9
+#define	REQ_PIQ_VALID	0x0da
+#define	REQ_PIQ_DISPATCH	0x0db
+#define	REQ_CIQ_VALID	0x0dc
+#define	REQ_CIQ_DISPATCH	0x0dd
+#define	REQ_NIQ_VALID	0x0de
+#define	REQ_NIQ_DISPATCH	0x0df
+#define	REQ_NUMA_BYPASS_DISPATCH	0x0e0
+/* Request Agent Durations */
+/* cnt 1 */
+#define	REQ_AGNT_ALLOC_DURATION	0x00130000
+#define	REQ_SFI_GRANT_P2_DURATION	0x00130800
+#define	REQ_1DC_RCV_ACK_CNT1_DURATION	0x00130c00
+#define	REQ_PKT_SENT_CLUST_RD_DURATION  0x00132400
+#define	REQ_1_CPI_RCV_ACK_CNT1_DURATION	0x00131400
+#define	REQ_PKT_QUE_DURATION	0x00131c00
+#define	REQ_PKT_SENT_CNT1_DURATION	0x00132000
+/* cnt 0 */
+#define	REQ_AGNT_RETIRED_DURATION	0x001000c1
+#define	REQ_1DC_RCV_ACK_CNT0_DURATION	0x001000c3
+#define	REQ_2DC_SND_ACK_DURATION	0x001000c4
+#define	REQ_1_CPI_RCV_ACK_CNT0_DURATION	0x001000c5
+#define	REQ_2_CPI_RCV_ACK_DURATION	0x001000c6
+#define	REQ_PKT_SENT_CNT0_DURATION	0x001000c8
+#define	REQ_LAST_REPLY_RCVD_DURATION	0x001000d7
+
+
+/* Home Agent Event Control --- agent = 4 */
+/* Home Agent Event Encoding */
+#define	HOME_AGENT_ALLOC	0x100
+#define	HOME_AGENT_RETIRED	0x101
+#define	HOME_SFI_P8_RD_AUX	0x102
+#define	HOME_SFI_P8_RD_MAIN	0x103
+#define	HOME_SFI_P8_WR	0x104
+#define	HOME_SFI_P9_WR	0x105
+#define	HOME_SFI_P10_WR	0x106
+#define	HOME_1DC_RCV_ACK_AUX	0x107
+#define	HOME_1DC_RCV_ACK_MAIN	0x108
+#define	HOME_2DC_SND_ACK	0x109
+#define	HOME_SFI_PULL_SEEN	0x10a
+#define	HOME_LAST_DEMREP_SENT	0x10b
+#define	HOME_COMP_PKT_SEEN	0x10c
+#define	HOME_HLI_REQ_LINK_0_A	0x10d
+#define	HOME_HLI_REQ_LINK_0_B	0x10e
+#define	HOME_HLI_REQ_LINK_1_A	0x10f
+#define	HOME_HLI_REQ_LINK_1_B	0x110
+#define	HOME_HLI_REQ_LINK_2_A	0x111
+#define	HOME_HLI_REQ_LINK_2_B	0x112
+#define	HOME_HLI_REQ_LINK_3_A	0x113
+#define	HOME_HLI_REQ_LINK_3_B	0x114
+#define	HOME_HLI_REQ_LINK_4_A	0x115
+#define	HOME_HLI_REQ_LINK_4_B	0x116
+#define	HOME_HLI_REQ_LINK_5_A	0x117
+#define	HOME_HLI_REQ_LINK_5_B	0x118
+#define	HOME_HLI_GRANT_LINK_0_A	0x119
+#define	HOME_HLI_GRANT_LINK_0_B	0x11a
+#define	HOME_HLI_GRANT_LINK_1_A	0x11b
+#define	HOME_HLI_GRANT_LINK_1_B	0x11c
+#define	HOME_HLI_GRANT_LINK_2_A	0x11d
+#define	HOME_HLI_GRANT_LINK_2_B	0x11e
+#define	HOME_HLI_GRANT_LINK_3_A	0x11f
+#define	HOME_HLI_GRANT_LINK_3_B	0x120
+#define	HOME_HLI_GRANT_LINK_4_A	0x121
+#define	HOME_HLI_GRANT_LINK_4_B	0x122
+#define	HOME_HLI_GRANT_LINK_5_A	0x123
+#define	HOME_HLI_GRANT_LINK_5_B	0x124
+#define	HOME_BLK_CAM_HIT	0x125
+#define	HOME_DIR_RTNED_BEFORE_RD_GRANT	0x126
+#define	HOME_DIR_RTNED_BEFORE_RD_ORDER	0x127
+#define	HOME_DIR_RTNED_BEFORE_RD_DATA	0x128
+#define	HOME_DIR_RTNED_AFTER_RD_DATA	0x129
+#define	HOME_REQ_HOME	0x12a
+#define	HOME_REQ_SAME_BOX	0x12b
+#define	HOME_REF_DATA_BACK_HOME	0x12c
+#define	HOME_DIR_MISS_ALLOC	0x12d
+#define	HOME_DIR_HIT_GI	0x12e
+#define	HOME_DIR_HIT_GS	0x12f
+#define	HOME_DIR_HIT_GM	0x130
+#define	HOME_DIR_HIT_RTO_GM	0x131
+#define	HOME_DIR_HIT_RTS_GMS	0x132
+#define	HOME_DIR_MISS_RTS_GI	0x133
+#define	HOME_DIR_MISS_RTS	0x134
+#define	HOME_DIR_MISS_RTO_GS_GI	0x135
+#define	HOME_DIR_MISS_RTO	0x136
+/* Home Agent Metrics, Durations Mode */
+/* cnt 1 */
+#define	HOME_AGENT_ALLOC_DURATION	0x00140000
+#define	HOME_SFI_P8_RD_AUX_DURATION	0x00140800
+#define	HOME_SFI_P8_RD_MAIN_DURATION	0x00140c00
+#define	HOME_1DC_RCV_ACK_AUX_CNT1_DURATION	0x00141c00
+#define	HOME_1DC_RCV_ACK_MAIN_CNT1_DURATION	0x00142000
+#define	HOME_SFI_P8_WR_DURATION	0x00141000
+#define	HOME_SFI_P9_WR_DURATION	0x00141400
+#define	HOME_SFI_P10_WR_DURATION	0x00141800
+#define	HOME_LAST_DEMREP_SENT_DURATION	0x00142c00
+/* cnt 0 */
+#define	HOME_AGENT_RETIRED_DURATION	0x00100101
+#define	HOME_1DC_RCV_ACK_AUX_CNT0_DURATION	0x00100107
+#define	HOME_1DC_RCV_ACK_MAIN_CNT0_DURATION	0x00100108
+#define	HOME_2DC_SND_ACK_DURATION	0x00100109
+#define	HOME_SFI_PULL_SEEN_DURATION	0x0010010a
+#define	HOME_COMP_PKT_SEEN_DURATION	0x0010010c
+
+
+/* Slave Agent Event Control --- agent = 5 */
+#define	SLAVE_AGENT_ALLOC	0x140
+#define	SLAVE_AGENT_ALLOC_LPA	0x141
+#define	SLAVE_AGENT_ALLOC_GA	0x142
+#define	SLAVE_AGENT_ALLOC_H_LPA	0x143
+#define	SLAVE_AGENT_ALLOC_H_GA	0x144
+#define	SLAVE_AGENT_ALLOC_H_MLPA	0x145
+#define	SLAVE_AGENT_ALLOC_H_MGA	0x146
+#define	SLAVE_AGENT_ALLOC_H_M	0x147
+#define	SLAVE_AGENT_ALLOC_H_INV_LPA	0x148
+#define	SLAVE_AGENT_ALLOC_H_INV_GA	0x149
+#define	SLAVE_AGENT_RETIRED	0x14a
+#define	SLAVE_REPLY_SENT	0x14b
+#define	SLAVE_SFI_P6_GRANT_WR	0x14c
+#define	SLAVE_SFI_P12GT_RLPA	0x14d
+#define	SLAVE_SFI_P12GT_RGA	0x14e
+#define	SLAVE_SFI_P12GT_RHLPA	0x14f
+#define	SLAVE_SFI_P12GT_RHGA	0x150
+#define	SLAVE_SFI_P12GT_RHMLPA	0x151
+#define	SLAVE_SFI_P12GT_RHMGA	0x152
+#define	SLAVE_SFI_P12GT_WR	0x153
+#define	SLAVE_1DC_RCV_ACK	0x154
+#define	SLAVE_2DC_SND_ACK	0x155
+#define	SLAVE_2DC_SND_ACK_REFL	0x156
+#define	SLAVE_4DC_SND_ACK	0x157
+#define	SLAVE_PULL_SEEN	0x158
+#define	SLAVE_H_M_GA_NOT_OWND	0x159
+#define	SLAVE_H_M_NO_STATE_CHANGE	0x15a
+#define	SLAVE_HLI_REQ_0	0x15b
+#define	SLAVE_HLI_REQ_1	0x15c
+#define	SLAVE_HLI_REQ_2	0x15d
+#define	SLAVE_HLI_REQ_3	0x15e
+#define	SLAVE_HLI_REQ_4	0x15f
+#define	SLAVE_HLI_REQ_5	0x160
+#define	SLAVE_HLI_GRANT_0	0x161
+#define	SLAVE_HLI_GRANT_1	0x162
+#define	SLAVE_HLI_GRANT_2	0x163
+#define	SLAVE_HLI_GRANT_3	0x164
+#define	SLAVE_HLI_GRANT_4	0x165
+#define	SLAVE_HLI_GRANT_5	0x166
+/* Slave Agent Durations */
+/* cnt 1 (pic1) */
+#define	SLAVE_AGENT_ALLOC_DURATION	0x00150000
+#define	SLAVE_SFI_P12GT_RLPA_DURATION	0x00153400
+#define	SLAVE_SFI_P12GT_RGA_DURATION	0x00153800
+#define	SLAVE_SFI_P12GT_RHLPA_DURATION	0x00153c00
+#define	SLAVE_SFI_P12GT_RHGA_DURATION	0x00154000
+#define	SLAVE_SFI_P12GT_RHMLPA_DURATION	0x00154400
+#define	SLAVE_SFI_P12GT_RHMGA_DURATION	0x00154800
+#define	SLAVE_1DC_RCV_ACK_CNT1_DURATION	0x00155000
+#define	SLAVE_SFI_P6_GRANT_WR_DURATION	0x00153000
+#define	SLAVE_SFI_P12GT_WR_DURATION	0x00154c00
+#define	SLAVE_AGENT_ALLOC_LPA_DURATION	0x00150400
+#define	SLAVE_AGENT_ALLOC_GA_DURATION	0x00150800
+#define	SLAVE_AGENT_ALLOC_H_LPA_DURATION	0x00150c00
+#define	SLAVE_AGENT_ALLOC_H_GA_DURATION	0x00151000
+#define	SLAVE_AGENT_ALLOC_H_MLPA_DURATION	0x00151400
+#define	SLAVE_AGENT_ALLOC_H_MGA_DURATION	0x00151800
+#define	SLAVE_AGENT_ALLOC_H_M_DURATION	0x00151c00
+#define	SLAVE_AGENT_ALLOC_H_INV_LPA_DURATION	0x00152000
+#define	SLAVE_AGENT_ALLOC_H_INV_GA_DURATION	0x00152400
+#define	SLAVE_2DC_SND_ACK_REFL_DURATION	0x00155800
+/* cnt 0 (pic0) */
+#define	SLAVE_AGENT_RETIRED_DURATION	0x0010014a
+#define	SLAVE_1DC_RCV_ACK_CNT0_DURATION	0x00100154
+#define	SLAVE_2DC_SND_ACK_DURATION	0x00100155
+#define	SLAVE_PULL_SEEN_DURATION	0x00100158
+#define	SLAVE_REPLY_SENT_DURATION	0x0010014b
+#define	SLAVE_4DC_SND_ACK_DURATION	0x00100157
+
+/* Misc counter pic0 clear mask */
+#define	MISC_CLEAR_PIC0	~(0x0f1003ffULL)
+/* Misc counter pic1 clear mask */
+#define	MISC_CLEAR_PIC1	~(0xf01ffc00ULL)
+
+
+
+/* Link Counter */
+#define	LINK_SENDING_ADMIN_PKTS	0x01
+#define	LINK_RCVD_MH_DATA_PKT	0x02
+#define	LINK_RMHDP_SADM	0x03
+#define	LINK_RCVD_DATA_PKT	0x04
+#define	LINK_RDP_SADM	0x05
+#define	LINK_RDP_RMHDP	0x06
+#define	LINK_REJECTED_FLIT	0x08
+#define	LINK_REJFLIT_SADM	0x09
+#define	LINK_REJFLIT_RMHDP	0x0a
+#define	LINK_REJFLIT_RMHDP_SADM	0x0b
+#define	LINK_REJFLIT_RDP	0x0c
+#define	LINK_REJFLIT_RDP_SADM	0x0d
+#define	LINK_RCVD_ADMIN_PKT	0x10
+#define	LINK_RADMP_SADM	0x11
+#define	LINK_RADMP_RMHDP	0x12
+#define	LINK_RADMP_RMHDP_SADM	0x13
+#define	LINK_RADMP_RDP	0x14
+#define	LINK_RADMP_RDP_SADM	0x15
+#define	LINK_RADMP_REJFLIT	0x18
+#define	LINK_CLEAR_PIC0	~(0x7fffULL)
+#define	LINK_CLEAR_PIC1 ~(0x7fffULL << 16)
+
+/* Loopback Counter */
+#define	LPBK_RCVD_DATA_PKT	0x01
+#define	LPBK_RCVD_ADDR_2_PKT	0x02
+#define	LPBK_RADDR2_RDATA	0x03
+#define	LPBK_RCVD_ADDR_1_PKT	0x04
+#define	LPBK_RADDR1_RDATA	0x05
+#define	LPBK_DATA_LPBK_FULL	0x08
+#define	LPBK_DFULL_RDATA	0x09
+#define	LPBK_DFULL_RADDR2	0x0a
+#define	LPBK_DFULL_RADDR2_RDATA	0x0b
+#define	LPBK_DFULL_RADDR1	0x0c
+#define	LPBK_DFULL_RADDR1_RDATA	0x0d
+#define	LPBK_ADDR_LPBK_FULL	0x10
+#define	LPBK_AFULL_RDATA	0x11
+#define	LPBK_AFULL_RADDR2	0x12
+#define	LPBK_AFULL_RADDR2_RDATA	0x13
+#define	LPBK_AFULL_RADDR1	0x14
+#define	LPBK_AFULL_RADDR1_RDATA	0x15
+#define	LPBK_AFULL_DFULL	0x18
+#define	LPBK_AFULL_DFULL_RDATA	0x19
+#define	LPBK_AFULL_DFULL_RADDR2	0x1a
+#define	LPBK_AFULL_DFULL_RADDR2_RDATA	0x1b
+#define	LPBK_AFULL_DFULL_RADDR1	0x1c
+#define	LPBK_AFULL_DFULL_RADDR1_RDATA	0x1d
+#define	LPBK_CLEAR_PIC0	~(0x3ffULL)
+#define	LPBK_CLEAR_PIC1 ~(0x3ffULL << 16)
+
+
+/*
+ * WCI Safari Histogramming Counter
+ *
+ * NOTE : wci_sfi_sw_ctr_ctl is not a real WCI HW register. It is created
+ * and manipulated by kernel software  to facilitate busstat requiremnets.
+ * Unlike wci_misc, wci_link & wci_lpbk performance counters, wci_sfi
+ * histogramming Counter is not a real busstat-style performance counter.
+ * What we do here is a SW hack to add wci_sfi histogramming Counter support
+ * into busstat, as requested by Wildcat perfomance group people.
+ *
+ * Bits of wci_sfi_sw_ctr_ctl.
+ *
+ * +--------------+--------------+--------------------+--------------------+
+ * | sfi_hstgrm 1 | sfi_hstgrm 0 | misc_ctr_ctl cnt1  | misc_ctr_ctl cnt0  |
+ * +--------------+--------------+--------------------+--------------------+
+ * 27           24 23          20 19                10 9                   0
+ *
+ *
+ * When user select WCI Safari Histogramming Counter pic0 through busstat,
+ * the corresponding wci_misc_ctr_ctl <9:0> should be set to :
+ *	wci_misc_ctr_ctl.cnt0_agent_select = 0
+ *	wci_misc_ctr_ctl.cnt0_event_select = 0 (safari histogram 0)
+ * the counter value should be read out from wci_misc_ctr.count0.
+ *
+ * When user select WCI Safari Histogramming Counter pic1 through busstat,
+ * the corresponding wci_misc_ctr_ctl <19:10> should be set to :
+ *	wci_misc_ctr_ctl.cnt1_agent_select = 0
+ *	wci_misc_ctr_ctl.cnt1_event_select = 1 (safari histogram 1)
+ * the counter value should be read out from wci_misc_ctr.count1.
+ *
+ * Note: The event encoding values of Bit <23:20> of wci_sfi_sw_str_ctl
+ * should start from 1 instead of 0 to avoid the confusion.  When user
+ * selects Safari Histogram Counter pic0, the corresponding misc_ctr_ctl
+ * register bits <9:0>is 0, as it represents agent 0, event 0. If
+ * wci_sfi_sw_ctr_ctl bit<23:20> encoding starts from 0, then both
+ * wci_sfi_sw_ctr_ctl bits <23:20> & <9:0> are all set to 0.  This could
+ * be mis-understood as NO Event Selected. It is also inconvenient for us to
+ * determine whether a pic counter is selected or not.
+ *
+ * WCI Safari Histogramming Counter Event Mask Encoding :
+ *
+ */
+#define	SFI_HSTGRM_ALL_TRANS	0x00100000ULL
+#define	SFI_HSTGRM_INT	0x00200000ULL
+#define	SFI_HSTGRM_LOCAL_INT	0x00300000ULL
+#define	SFI_HSTGRM_RMT_CLU_INCM_INT	0x00400000ULL
+#define	SFI_HSTGRM_RMT_SSM_INCM_INT	0x00500000ULL
+#define	SFI_HSTGRM_IO	0x00600000ULL
+#define	SFI_HSTGRM_RMT_SSM_INCM_IO	0x00700000ULL
+#define	SFI_HSTGRM_COHRNT	0x00800000ULL
+#define	SFI_HSTGRM_RMT_CLU_INCM_COHRNT	0x00900000ULL
+#define	SFI_HSTGRM_RMT_SSM_OTG_COHRNT	0x00a00000ULL
+#define	SFI_HSTGRM_RMT_SSM_INCM_COHRNT	0x00b00000ULL
+/* WCI Safari Histogramming Counter pic0 clear mask */
+#define	WCI_SFI_CLEAR_PIC0 ~(0x00f003ffULL)
+/* WCI Safari Histogramming Counter pic1 clear mask */
+#define	WCI_SFI_CLEAR_PIC1 ~(0x0f0ffc00ULL)
+
+/*
+ * The following mask is used to obtain wci_misc_ctr_ctl bits <19:0>
+ * and is also used to mask the wci_sfi_sw_ctr_ctl bits <19:0> by
+ * complementing the same mask.
+ */
+#define	WCI_SFI_SW_CTR_CTL_MASK	0x000FFFFFULL
+#define	WCI_SFI_CTR0_EVENT_SHIFT	20
+#define	WCI_SFI_CTR1_EVENT_SHIFT	24
+#define	WCI_SFI_CTR0_EVENT_MASK	0x00F00000ULL
+#define	WCI_SFI_CTR1_EVENT_MASK	0x0F000000ULL
+/*
+ * wci_sfi_ctr0/1_mask, wci_sfi_ctr0/1_match bits
+ *
+ * E.g., For interrupt transaction type,
+ *
+ * Address Field <42:4> definition  <---->  Address Field <38:0> definition
+ * INT :    <38:29> sender                     <34:25> sender
+ *          <23:14> target                     <19:10> target
+ *
+ * 57   48 47 atransid   39 38             address                            0
+ * +------+-------+--------+------+------+------+------+------+------+--------+
+ * | mask | devID | Seq.ID |      | SNID | SAID |      | TNID | TAID |        |
+ * +------+-------+--------+------+------+------+------+------+------+--------+
+ * 57   48 47   43 42    39 38  35 34  30 29  25 24  20 19  15 14  10 9       0
+ *
+ */
+#define	WCI_SFI_ADDR_TNID_SHIFT	15
+#define	WCI_SFI_ATRANS_DEVID_SHIFT	43
+
+/*
+ * The following structure is used to define register wci_sfi_ctr#_mask,
+ * wci_sfi_ctr#_match and wci_sfi_ctr#_match_transaction settings
+ * for wci safari histogramming counters.
+ */
+	typedef struct wci_sfi_regs_value {
+		uint64_t wci_sfi_ctr_mask_val;
+		uint64_t wci_sfi_ctr_match_val;
+		uint64_t wci_sfi_ctr_match_trans_val;
+	} wci_sfi_regs_value_t;
+
+/*
+ * kstat structures used by wci to pass data to user programs.
+ * wci_misc_counters_kstat - Misc counters (busstat support)
+ *
+ */
+
+	struct wci_counters_kstat {
+		kstat_named_t	wci_ctr_ctl;	/* ctr ctl reg */
+		kstat_named_t	wci_ctr0;	/* ctr0 reg    */
+		kstat_named_t	wci_ctr1;	/* ctr1 reg    */
+	};
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _WCI_COMMON_H */
diff --git a/usr/src/uts/sun4u/sys/wci_masks.h b/usr/src/uts/sun4u/sys/wci_masks.h
new file mode 100644
index 0000000000..e78c059ecc
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wci_masks.h
@@ -0,0 +1,1988 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _SYS_WCI_MASKS_H
+#define	_SYS_WCI_MASKS_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * This file was automatically generated from wci_regs.h
+ * Each macro is of the form MASK_<register name>_<field name>.
+ * The definitions are mask-high-word, mask-low-word, shift.
+ */
+
+#define	MASK_WCI_BOARD2CNID_ARRAY_RSVD_Z 0xffffffff, 0xffffff00, 8
+#define	MASK_WCI_BOARD2CNID_ARRAY_DATA 0x0, 0xff, 0
+#define	MASK_WCI_BOARD2CNID_CONTROL_RSVD_Z 0xffffffff, 0xfffffffe, 1
+#define	MASK_WCI_BOARD2CNID_CONTROL_BOARD2CNID_ENABLE 0x0, 0x1, 0
+#define	MASK_WCI_CA_BUSY_RSVD_Z 0xffffffff, 0x0, 32
+#define	MASK_WCI_CA_BUSY_VECTOR 0x0, 0xffffffff, 0
+#define	MASK_WCI_CA_CONFIG_RSVD_Z 0xffffffff, 0xffffffc0, 6
+#define	MASK_WCI_CA_CONFIG_CLUSTER_DISABLE 0x0, 0x20, 5
+#define	MASK_WCI_CA_CONFIG_REUSE_TIMEOUT_LIMIT 0x0, 0x1f, 0
+#define	MASK_WCI_CA_ECC_ADDRESS_DATA 0x80000000, 0x0, 63
+#define	MASK_WCI_CA_ECC_ADDRESS_UE 0x40000000, 0x0, 62
+#define	MASK_WCI_CA_ECC_ADDRESS_PASSTHRU 0x20000000, 0x0, 61
+#define	MASK_WCI_CA_ECC_ADDRESS_RSVD_Z 0x1fffffe0, 0x0, 37
+#define	MASK_WCI_CA_ECC_ADDRESS_ADDR 0x1f, 0xffffffff, 0
+#define	MASK_WCI_CA_ERROR_TRANSACTION_STATUS 0xf0000000, 0x0, 60
+#define	MASK_WCI_CA_ERROR_TRANSACTION_ESR_REG 0x8000000, 0x0, 59
+#define	MASK_WCI_CA_ERROR_TRANSACTION_ESR_INDEX 0x7800000, 0x0, 55
+#define	MASK_WCI_CA_ERROR_TRANSACTION_CTID 0x7c0000, 0x0, 50
+#define	MASK_WCI_CA_ERROR_TRANSACTION_TARGID 0x3fe00, 0x0, 41
+#define	MASK_WCI_CA_ERROR_TRANSACTION_SECOND_ATRANSID 0x1e0, 0x0, 37
+#define	MASK_WCI_CA_ERROR_TRANSACTION_FIRST_ATRANSID 0x1e, 0x0, 33
+#define	MASK_WCI_CA_ERROR_TRANSACTION_CMD_GRANT_1 0x1, 0x0, 32
+#define	MASK_WCI_CA_ERROR_TRANSACTION_CMD_GRANT_2 0x0, 0x80000000, 31
+#define	MASK_WCI_CA_ERROR_TRANSACTION_REISSUE_PENDING_1 0x0, 0x40000000, 30
+#define	MASK_WCI_CA_ERROR_TRANSACTION_REISSUE_PENDING_2 0x0, 0x20000000, 29
+#define	MASK_WCI_CA_ERROR_TRANSACTION_TRANSID_RELEASED 0x0, 0x10000000, 28
+#define	MASK_WCI_CA_ERROR_TRANSACTION_CONST_GRANT 0x0, 0x8000000, 27
+#define	MASK_WCI_CA_ERROR_TRANSACTION_MAP_GRANT 0x0, 0x4000000, 26
+#define	MASK_WCI_CA_ERROR_TRANSACTION_MAP_QUEUED 0x0, 0x2000000, 25
+#define	MASK_WCI_CA_ERROR_TRANSACTION_REUSE_TIMEOUT 0x0, 0x1000000, 24
+#define	MASK_WCI_CA_ERROR_TRANSACTION_DATA_TIMEOUT 0x0, 0x800000, 23
+#define	MASK_WCI_CA_ERROR_TRANSACTION_APHASE_TIMEOUT 0x0, 0x400000, 22
+#define	MASK_WCI_CA_ERROR_TRANSACTION_PKT_SENT 0x0, 0x200000, 21
+#define	MASK_WCI_CA_ERROR_TRANSACTION_PKT_QUEUED 0x0, 0x100000, 20
+#define	MASK_WCI_CA_ERROR_TRANSACTION_CPI_INVAL 0x0, 0x80000, 19
+#define	MASK_WCI_CA_ERROR_TRANSACTION_CPI_QUEUED 0x0, 0x40000, 18
+#define	MASK_WCI_CA_ERROR_TRANSACTION_CPI_ERR 0x0, 0x20000, 17
+#define	MASK_WCI_CA_ERROR_TRANSACTION_CPI_RCV2 0x0, 0x10000, 16
+#define	MASK_WCI_CA_ERROR_TRANSACTION_CPI_RCV1 0x0, 0x8000, 15
+#define	MASK_WCI_CA_ERROR_TRANSACTION_DC_ATOM_ERR 0x0, 0x4000, 14
+#define	MASK_WCI_CA_ERROR_TRANSACTION_DC_SND2 0x0, 0x2000, 13
+#define	MASK_WCI_CA_ERROR_TRANSACTION_DC_RCV2 0x0, 0x1000, 12
+#define	MASK_WCI_CA_ERROR_TRANSACTION_DC_ERR1 0x0, 0x800, 11
+#define	MASK_WCI_CA_ERROR_TRANSACTION_PULL_LATE 0x0, 0x400, 10
+#define	MASK_WCI_CA_ERROR_TRANSACTION_PULL_TIMEOUT 0x0, 0x200, 9
+#define	MASK_WCI_CA_ERROR_TRANSACTION_PULL_CLEARED 0x0, 0x100, 8
+#define	MASK_WCI_CA_ERROR_TRANSACTION_PULL_ERR 0x0, 0x80, 7
+#define	MASK_WCI_CA_ERROR_TRANSACTION_PULL_OK 0x0, 0x40, 6
+#define	MASK_WCI_CA_ERROR_TRANSACTION_SNOOP_LATE 0x0, 0x20, 5
+#define	MASK_WCI_CA_ERROR_TRANSACTION_SNOOP2 0x0, 0x18, 3
+#define	MASK_WCI_CA_ERROR_TRANSACTION_SNOOP1 0x0, 0x7, 0
+#define	MASK_WCI_CA_ERROR_TRANSACTION_2_RSVD_Z 0xffffffff, 0xfffffff0, 4
+#define	MASK_WCI_CA_ERROR_TRANSACTION_2_SNOOP2_LATE_REISSUE 0x0, 0x8, 3
+#define	MASK_WCI_CA_ERROR_TRANSACTION_2_DC_RCV2_BARRIER 0x0, 0x4, 2
+#define	MASK_WCI_CA_ERROR_TRANSACTION_2_CPI_BARRIER 0x0, 0x2, 1
+#define	MASK_WCI_CA_ERROR_TRANSACTION_2_CPI_RCV2_BARRIER 0x0, 0x1, 0
+#define	MASK_WCI_CA_ESR_0_RSVD_Z 0xffffffff, 0x80000000, 31
+#define	MASK_WCI_CA_ESR_0_ACC_UNEXPECT_CPI_ACK 0x0, 0x40000000, 30
+#define	MASK_WCI_CA_ESR_0_ACC_UNEXPECT_DC_ACK 0x0, 0x20000000, 29
+#define	MASK_WCI_CA_ESR_0_ACC_UNEXPECT_PULL 0x0, 0x10000000, 28
+#define	MASK_WCI_CA_ESR_0_ACC_UNEXPECT_REISSUE 0x0, 0x8000000, 27
+#define	MASK_WCI_CA_ESR_0_ACC_ATOMIC_MAP_MISMATCH 0x0, 0x4000000, 26
+#define	MASK_WCI_CA_ESR_0_ACC_UNMAPPED 0x0, 0x2000000, 25
+#define	MASK_WCI_CA_ESR_0_ACC_UNCORRECTABLE_MTAG_ERROR 0x0, 0x1000000, 24
+#define	MASK_WCI_CA_ESR_0_ACC_UNCORRECTABLE_DATA_ERROR 0x0, 0x800000, 23
+#define	MASK_WCI_CA_ESR_0_ACC_CORRECTABLE_MTAG_ERROR 0x0, 0x400000, 22
+#define	MASK_WCI_CA_ESR_0_ACC_CORRECTABLE_DATA_ERROR 0x0, 0x200000, 21
+#define	MASK_WCI_CA_ESR_0_ACC_DSTAT_INCONSISTENT 0x0, 0x100000, 20
+#define	MASK_WCI_CA_ESR_0_ACC_MTAG_MISMATCH_WITHIN_HCL 0x0, 0x80000, 19
+#define	MASK_WCI_CA_ESR_0_ACC_MTAG_MISMATCH_BETWEEN_HCLS 0x0, 0x40000, 18
+#define	MASK_WCI_CA_ESR_0_ACC_REMOTE_TIMEOUT 0x0, 0x20000, 17
+#define	MASK_WCI_CA_ESR_0_ACC_LOCAL_TIMEOUT 0x0, 0x10000, 16
+#define	MASK_WCI_CA_ESR_0_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_CA_ESR_0_UNEXPECT_CPI_ACK 0x0, 0x4000, 14
+#define	MASK_WCI_CA_ESR_0_UNEXPECT_DC_ACK 0x0, 0x2000, 13
+#define	MASK_WCI_CA_ESR_0_UNEXPECT_PULL 0x0, 0x1000, 12
+#define	MASK_WCI_CA_ESR_0_UNEXPECT_REISSUE 0x0, 0x800, 11
+#define	MASK_WCI_CA_ESR_0_ATOMIC_MAP_MISMATCH 0x0, 0x400, 10
+#define	MASK_WCI_CA_ESR_0_UNMAPPED 0x0, 0x200, 9
+#define	MASK_WCI_CA_ESR_0_UNCORRECTABLE_MTAG_ERROR 0x0, 0x100, 8
+#define	MASK_WCI_CA_ESR_0_UNCORRECTABLE_DATA_ERROR 0x0, 0x80, 7
+#define	MASK_WCI_CA_ESR_0_CORRECTABLE_MTAG_ERROR 0x0, 0x40, 6
+#define	MASK_WCI_CA_ESR_0_CORRECTABLE_DATA_ERROR 0x0, 0x20, 5
+#define	MASK_WCI_CA_ESR_0_DSTAT_INCONSISTENT 0x0, 0x10, 4
+#define	MASK_WCI_CA_ESR_0_MTAG_MISMATCH_WITHIN_HCL 0x0, 0x8, 3
+#define	MASK_WCI_CA_ESR_0_MTAG_MISMATCH_BETWEEN_HCLS 0x0, 0x4, 2
+#define	MASK_WCI_CA_ESR_0_REMOTE_TIMEOUT 0x0, 0x2, 1
+#define	MASK_WCI_CA_ESR_0_LOCAL_TIMEOUT 0x0, 0x1, 0
+#define	MASK_WCI_CA_ESR_1_RSVD_Z 0xffffffff, 0xffe00000, 21
+#define	MASK_WCI_CA_ESR_1_ACC_QLIMIT_TIMEOUT 0x0, 0x100000, 20
+#define	MASK_WCI_CA_ESR_1_ACC_INTERNAL_ERROR 0x0, 0x80000, 19
+#define	MASK_WCI_CA_ESR_1_ACC_CMMU_ECC_ERROR 0x0, 0x40000, 18
+#define	MASK_WCI_CA_ESR_1_ACC_WRONG_CMD 0x0, 0x20000, 17
+#define	MASK_WCI_CA_ESR_1_ACC_DATA_PHASE_TIMEOUT 0x0, 0x10000, 16
+#define	MASK_WCI_CA_ESR_1_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_CA_ESR_1_RSVD_Y 0x0, 0x7fe0, 5
+#define	MASK_WCI_CA_ESR_1_QLIMIT_TIMEOUT 0x0, 0x10, 4
+#define	MASK_WCI_CA_ESR_1_INTERNAL_ERROR 0x0, 0x8, 3
+#define	MASK_WCI_CA_ESR_1_CMMU_ECC_ERROR 0x0, 0x4, 2
+#define	MASK_WCI_CA_ESR_1_WRONG_CMD 0x0, 0x2, 1
+#define	MASK_WCI_CA_ESR_1_DATA_PHASE_TIMEOUT 0x0, 0x1, 0
+#define	MASK_WCI_CA_ESR_MASK_RSVD_Z 0xffffffff, 0xffe00000, 21
+#define	MASK_WCI_CA_ESR_MASK_QLIMIT_TIMEOUT 0x0, 0x100000, 20
+#define	MASK_WCI_CA_ESR_MASK_INTERNAL_ERROR 0x0, 0x80000, 19
+#define	MASK_WCI_CA_ESR_MASK_CMMU_ECC_ERROR 0x0, 0x40000, 18
+#define	MASK_WCI_CA_ESR_MASK_WRONG_CMD 0x0, 0x20000, 17
+#define	MASK_WCI_CA_ESR_MASK_DATA_PHASE_TIMEOUT 0x0, 0x10000, 16
+#define	MASK_WCI_CA_ESR_MASK_RSVD_Y 0x0, 0x8000, 15
+#define	MASK_WCI_CA_ESR_MASK_UNEXPECT_CPI_ACK 0x0, 0x4000, 14
+#define	MASK_WCI_CA_ESR_MASK_UNEXPECT_DC_ACK 0x0, 0x2000, 13
+#define	MASK_WCI_CA_ESR_MASK_UNEXPECT_PULL 0x0, 0x1000, 12
+#define	MASK_WCI_CA_ESR_MASK_UNEXPECT_REISSUE 0x0, 0x800, 11
+#define	MASK_WCI_CA_ESR_MASK_ATOMIC_MAP_MISMATCH 0x0, 0x400, 10
+#define	MASK_WCI_CA_ESR_MASK_UNMAPPED 0x0, 0x200, 9
+#define	MASK_WCI_CA_ESR_MASK_UNCORRECTABLE_MTAG_ERROR 0x0, 0x100, 8
+#define	MASK_WCI_CA_ESR_MASK_UNCORRECTABLE_DATA_ERROR 0x0, 0x80, 7
+#define	MASK_WCI_CA_ESR_MASK_CORRECTABLE_MTAG_ERROR 0x0, 0x40, 6
+#define	MASK_WCI_CA_ESR_MASK_CORRECTABLE_DATA_ERROR 0x0, 0x20, 5
+#define	MASK_WCI_CA_ESR_MASK_DSTAT_INCONSISTENT 0x0, 0x10, 4
+#define	MASK_WCI_CA_ESR_MASK_MTAG_MISMATCH_WITHIN_HCL 0x0, 0x8, 3
+#define	MASK_WCI_CA_ESR_MASK_MTAG_MISMATCH_BETWEEN_HCLS 0x0, 0x4, 2
+#define	MASK_WCI_CA_ESR_MASK_REMOTE_TIMEOUT 0x0, 0x2, 1
+#define	MASK_WCI_CA_ESR_MASK_LOCAL_TIMEOUT 0x0, 0x1, 0
+#define	MASK_WCI_CA_FIRST_PACKET_0_ADDR 0xfc000000, 0x0, 58
+#define	MASK_WCI_CA_FIRST_PACKET_0_RSVD_Z 0x3ffe000, 0x0, 45
+#define	MASK_WCI_CA_FIRST_PACKET_0_RTRANSID 0x1ff0, 0x0, 36
+#define	MASK_WCI_CA_FIRST_PACKET_0_SCNID 0xf, 0xf0000000, 28
+#define	MASK_WCI_CA_FIRST_PACKET_0_RSVD_Y 0x0, 0xff00000, 20
+#define	MASK_WCI_CA_FIRST_PACKET_0_RTID 0x0, 0xf8000, 15
+#define	MASK_WCI_CA_FIRST_PACKET_0_SNID 0x0, 0x7800, 11
+#define	MASK_WCI_CA_FIRST_PACKET_0_OPCODE 0x0, 0x7e0, 5
+#define	MASK_WCI_CA_FIRST_PACKET_0_STRIPE 0x0, 0x10, 4
+#define	MASK_WCI_CA_FIRST_PACKET_0_DNID 0x0, 0xf, 0
+#define	MASK_WCI_CA_FIRST_PACKET_1_RSVD_Z 0xffffffff, 0x80000000, 31
+#define	MASK_WCI_CA_FIRST_PACKET_1_ADDR 0x0, 0x7fffffff, 0
+#define	MASK_WCI_CA_FREEZE_RSVD_Z 0xffffffff, 0x0, 32
+#define	MASK_WCI_CA_FREEZE_VECTOR 0x0, 0xffffffff, 0
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_RSVD_Z 0xfc000000, 0x0, 58
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_DPHASE_DISABLE 0x2000000, 0x0, 57
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_DPHASE_FREEZE 0x1000000, 0x0, 56
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_RSVD_Y 0xc00000, 0x0, 54
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_DPHASE_DEST_MAG 0x300000, 0x0, 52
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_DPHASE_DEST_VAL 0xff000, 0x0, 44
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_RSVD_X 0xc00, 0x0, 42
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_DPHASE_PASS_MAG 0x300, 0x0, 40
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_DPHASE_PASS_VAL 0xff, 0x0, 32
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_RSVD_W 0x0, 0xc0000000, 30
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_APHASE_DISABLE 0x0, 0x20000000, 29
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_APHASE_FREEZE 0x0, 0x10000000, 28
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_RSVD_V 0x0, 0xc000000, 26
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_APHASE_MAG 0x0, 0x3000000, 24
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_APHASE_VAL 0x0, 0xff0000, 16
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_RSVD_U 0x0, 0x8000, 15
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_REUSE_DISABLE 0x0, 0x4000, 14
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_REUSE_FREEZE 0x0, 0x2000, 13
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_REUSE_MAG 0x0, 0x1800, 11
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_REUSE_VAL 0x0, 0x7ff, 0
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_2_RSVD_Z 0xffffffff, 0xfe000000, 25
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_2_SFI_TARGID_TIMEOUT_DISABLE 0x0, \
+0x1000000, 24
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_2_RSVD_Y 0x0, 0x800000, 23
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_2_SFI_TARGID_TIMEOUT_SEL 0x0, 0x700000, 20
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_2_RSVD_X 0x0, 0xfc000, 14
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_2_LOC_REUSE_MAG 0x0, 0x3000, 12
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_2_RSVD_W 0x0, 0x800, 11
+#define	MASK_WCI_CA_TIMEOUT_CONFIG_2_LOC_REUSE_VAL 0x0, 0x7ff, 0
+#define	MASK_WCI_CCI_ESR_RSVD_Z 0xffffffff, 0xffc00000, 22
+#define	MASK_WCI_CCI_ESR_ACC_PARITY 0x0, 0x200000, 21
+#define	MASK_WCI_CCI_ESR_ACC_THRESHOLD 0x0, 0x100000, 20
+#define	MASK_WCI_CCI_ESR_ACC_SRAM_AE 0x0, 0x80000, 19
+#define	MASK_WCI_CCI_ESR_ACC_SRAM_UE 0x0, 0x40000, 18
+#define	MASK_WCI_CCI_ESR_ACC_SRAM_CE 0x0, 0x20000, 17
+#define	MASK_WCI_CCI_ESR_ACC_CE_COUNT_ZERO 0x0, 0x10000, 16
+#define	MASK_WCI_CCI_ESR_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_CCI_ESR_RSVD_Y 0x0, 0x7fc0, 6
+#define	MASK_WCI_CCI_ESR_PARITY 0x0, 0x20, 5
+#define	MASK_WCI_CCI_ESR_THRESHOLD 0x0, 0x10, 4
+#define	MASK_WCI_CCI_ESR_SRAM_AE 0x0, 0x8, 3
+#define	MASK_WCI_CCI_ESR_SRAM_UE 0x0, 0x4, 2
+#define	MASK_WCI_CCI_ESR_SRAM_CE 0x0, 0x2, 1
+#define	MASK_WCI_CCI_ESR_CE_COUNT_ZERO 0x0, 0x1, 0
+#define	MASK_WCI_CCI_ESR_MASK_RSVD_Z 0xffffffff, 0xffffffc0, 6
+#define	MASK_WCI_CCI_ESR_MASK_PARITY 0x0, 0x20, 5
+#define	MASK_WCI_CCI_ESR_MASK_THRESHOLD 0x0, 0x10, 4
+#define	MASK_WCI_CCI_ESR_MASK_SRAM_AE 0x0, 0x8, 3
+#define	MASK_WCI_CCI_ESR_MASK_SRAM_UE 0x0, 0x4, 2
+#define	MASK_WCI_CCI_ESR_MASK_SRAM_CE 0x0, 0x2, 1
+#define	MASK_WCI_CCI_ESR_MASK_CE_COUNT_ZERO 0x0, 0x1, 0
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_CCI_ROUTE_MAP0_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_CCI_ROUTE_MAP0_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_CCI_ROUTE_MAP1_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_CCI_ROUTE_MAP1_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_CLUSTER_CONFIG_RSVD_Z 0xffffffff, 0xfffffff8, 3
+#define	MASK_WCI_CLUSTER_CONFIG_IN_AN_SSM 0x0, 0x4, 2
+#define	MASK_WCI_CLUSTER_CONFIG_BAD_ECC_ON_WRITE_ERROR 0x0, 0x2, 1
+#define	MASK_WCI_CLUSTER_CONFIG_ALLOW_MULTIPLE_HOPS 0x0, 0x1, 0
+#define	MASK_WCI_CLUSTER_CTR_CTL_RSVD_Z 0xffffffff, 0xfffffe00, 9
+#define	MASK_WCI_CLUSTER_CTR_CTL_ENABLE_ALL 0x0, 0x100, 8
+#define	MASK_WCI_CLUSTER_CTR_CTL_CNT1_RECEIVED_INTERRUPT 0x0, 0x80, 7
+#define	MASK_WCI_CLUSTER_CTR_CTL_CNT1_RECEIVED_ATOMIC 0x0, 0x40, 6
+#define	MASK_WCI_CLUSTER_CTR_CTL_CNT1_RECEIVED_CACHEABLE_READ 0x0, 0x20, 5
+#define	MASK_WCI_CLUSTER_CTR_CTL_CNT1_RECEIVED_CACHEABLE_WRITE 0x0, 0x10, 4
+#define	MASK_WCI_CLUSTER_CTR_CTL_CNT0_RECEIVED_INTERRUPT 0x0, 0x8, 3
+#define	MASK_WCI_CLUSTER_CTR_CTL_CNT0_RECEIVED_ATOMIC 0x0, 0x4, 2
+#define	MASK_WCI_CLUSTER_CTR_CTL_CNT0_RECEIVED_CACHEABLE_READ 0x0, 0x2, 1
+#define	MASK_WCI_CLUSTER_CTR_CTL_CNT0_RECEIVED_CACHEABLE_WRITE 0x0, 0x1, 0
+#define	MASK_WCI_CLUSTER_ERROR_COUNT_VALUE 0xffffffff, 0xffffffff, 0
+#define	MASK_WCI_CLUSTER_ERROR_STATUS_ARRAY_RSVD_Z 0xffffffff, 0xffffffc0, 6
+#define	MASK_WCI_CLUSTER_ERROR_STATUS_ARRAY_DISABLE_FAIL_FAST 0x0, 0x20, 5
+#define	MASK_WCI_CLUSTER_ERROR_STATUS_ARRAY_NOT_VALID 0x0, 0x10, 4
+#define	MASK_WCI_CLUSTER_ERROR_STATUS_ARRAY_VALUE 0x0, 0xf, 0
+#define	MASK_WCI_CLUSTER_MEMBERS_BITS_MASK 0xffffffff, 0xffffffff, 0
+#define	MASK_WCI_CLUSTER_SYNC_SYNC_IN_PROGRESS 0x80000000, 0x0, 63
+#define	MASK_WCI_CLUSTER_SYNC_RSVD_Z 0x7fffffff, 0x0, 32
+#define	MASK_WCI_CLUSTER_SYNC_CAG_BUSY 0x0, 0xffffffff, 0
+#define	MASK_WCI_CLUSTER_WRITE_LOCKOUT_MASK 0xffffffff, 0xffffffff, 0
+#define	MASK_WCI_CONFIG_RSVD_Z 0xffffe000, 0x0, 45
+#define	MASK_WCI_CONFIG_WR_DIR_ON_RINV_MISS 0x1000, 0x0, 44
+#define	MASK_WCI_CONFIG_WR_DIR_ON_RWS_MISS 0x800, 0x0, 43
+#define	MASK_WCI_CONFIG_SAFARI_COMPLIANT_TARGID 0x400, 0x0, 42
+#define	MASK_WCI_CONFIG_RSVD_Y 0x380, 0x0, 39
+#define	MASK_WCI_CONFIG_CLUSTER_EARLY_REUSE_EN 0x40, 0x0, 38
+#define	MASK_WCI_CONFIG_RESERVED_DEFAULT_0 0x20, 0x0, 37
+#define	MASK_WCI_CONFIG_RA_NUMA_BYPASS_EN 0x10, 0x0, 36
+#define	MASK_WCI_CONFIG_HA_DISABLE_UNEXP_SNID 0x8, 0x0, 35
+#define	MASK_WCI_CONFIG_RA_DISABLE_UNEXP_SNID 0x4, 0x0, 34
+#define	MASK_WCI_CONFIG_DC_CPI_SNID_DISABLE 0x2, 0x0, 33
+#define	MASK_WCI_CONFIG_DBG_BYTEMASK_EN 0x1, 0x0, 32
+#define	MASK_WCI_CONFIG_PARTNER_NODE_ID 0x0, 0xf0000000, 28
+#define	MASK_WCI_CONFIG_CLUSTER_MODE 0x0, 0x8000000, 27
+#define	MASK_WCI_CONFIG_RSVD_X 0x0, 0x4000000, 26
+#define	MASK_WCI_CONFIG_NC_STRIPE_BY_ADDR 0x0, 0x2000000, 25
+#define	MASK_WCI_CONFIG_ENABLE_INID 0x0, 0x1000000, 24
+#define	MASK_WCI_CONFIG_STRIPE_BITS 0x0, 0xf00000, 20
+#define	MASK_WCI_CONFIG_DEV_CONFIG_NODE_ID 0x0, 0xf8000, 15
+#define	MASK_WCI_CONFIG_BOX_ID 0x0, 0x7e00, 9
+#define	MASK_WCI_CONFIG_DEVICE_ID 0x0, 0x1f0, 4
+#define	MASK_WCI_CONFIG_NODE_ID 0x0, 0xf, 0
+#define	MASK_WCI_CSR_CONTROL_RSVD_Z 0xffffffff, 0xfffffffe, 1
+#define	MASK_WCI_CSR_CONTROL_JTAG_WR_ONLY 0x0, 0x1, 0
+#define	MASK_WCI_CSRA_ESR_RSVD_Z 0xffffffff, 0xf8000000, 27
+#define	MASK_WCI_CSRA_ESR_ACC_TIMEOUT 0x0, 0x4000000, 26
+#define	MASK_WCI_CSRA_ESR_ACC_PULL_TARGID_TIMEOUT 0x0, 0x2000000, 25
+#define	MASK_WCI_CSRA_ESR_ACC_PULL_TIMEOUT 0x0, 0x1000000, 24
+#define	MASK_WCI_CSRA_ESR_ACC_SRAM_ERROR 0x0, 0x800000, 23
+#define	MASK_WCI_CSRA_ESR_ACC_PROTECTION_ERROR 0x0, 0x400000, 22
+#define	MASK_WCI_CSRA_ESR_ACC_UNCORRECTABLE_MTAG_ERROR 0x0, 0x200000, 21
+#define	MASK_WCI_CSRA_ESR_ACC_UNCORRECTABLE_DATA_ERROR 0x0, 0x100000, 20
+#define	MASK_WCI_CSRA_ESR_ACC_CORRECTABLE_MTAG_ERROR 0x0, 0x80000, 19
+#define	MASK_WCI_CSRA_ESR_ACC_CORRECTABLE_DATA_ERROR 0x0, 0x40000, 18
+#define	MASK_WCI_CSRA_ESR_ACC_MTAG_NOT_GM 0x0, 0x20000, 17
+#define	MASK_WCI_CSRA_ESR_ACC_MTAG_MISMATCH 0x0, 0x10000, 16
+#define	MASK_WCI_CSRA_ESR_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_CSRA_ESR_RSVD_Y 0x0, 0x7800, 11
+#define	MASK_WCI_CSRA_ESR_TIMEOUT 0x0, 0x400, 10
+#define	MASK_WCI_CSRA_ESR_PULL_TARGID_TIMEOUT 0x0, 0x200, 9
+#define	MASK_WCI_CSRA_ESR_PULL_TIMEOUT 0x0, 0x100, 8
+#define	MASK_WCI_CSRA_ESR_SRAM_ERROR 0x0, 0x80, 7
+#define	MASK_WCI_CSRA_ESR_PROTECTION_ERROR 0x0, 0x40, 6
+#define	MASK_WCI_CSRA_ESR_UNCORRECTABLE_MTAG_ERROR 0x0, 0x20, 5
+#define	MASK_WCI_CSRA_ESR_UNCORRECTABLE_DATA_ERROR 0x0, 0x10, 4
+#define	MASK_WCI_CSRA_ESR_CORRECTABLE_MTAG_ERROR 0x0, 0x8, 3
+#define	MASK_WCI_CSRA_ESR_CORRECTABLE_DATA_ERROR 0x0, 0x4, 2
+#define	MASK_WCI_CSRA_ESR_MTAG_NOT_GM 0x0, 0x2, 1
+#define	MASK_WCI_CSRA_ESR_MTAG_MISMATCH 0x0, 0x1, 0
+#define	MASK_WCI_CSRA_ESR_MASK_RSVD_Z 0xffffffff, 0xfffff800, 11
+#define	MASK_WCI_CSRA_ESR_MASK_TIMEOUT 0x0, 0x400, 10
+#define	MASK_WCI_CSRA_ESR_MASK_PULL_TARGID_TIMEOUT 0x0, 0x200, 9
+#define	MASK_WCI_CSRA_ESR_MASK_PULL_TIMEOUT 0x0, 0x100, 8
+#define	MASK_WCI_CSRA_ESR_MASK_SRAM_ERROR 0x0, 0x80, 7
+#define	MASK_WCI_CSRA_ESR_MASK_PROTECTION_ERROR 0x0, 0x40, 6
+#define	MASK_WCI_CSRA_ESR_MASK_UNCORRECTABLE_MTAG_ERROR 0x0, 0x20, 5
+#define	MASK_WCI_CSRA_ESR_MASK_UNCORRECTABLE_DATA_ERROR 0x0, 0x10, 4
+#define	MASK_WCI_CSRA_ESR_MASK_CORRECTABLE_MTAG_ERROR 0x0, 0x8, 3
+#define	MASK_WCI_CSRA_ESR_MASK_CORRECTABLE_DATA_ERROR 0x0, 0x4, 2
+#define	MASK_WCI_CSRA_ESR_MASK_MTAG_NOT_GM 0x0, 0x2, 1
+#define	MASK_WCI_CSRA_ESR_MASK_MTAG_MISMATCH 0x0, 0x1, 0
+#define	MASK_WCI_CSRA_STATUS_RSVD_Z 0x80000000, 0x0, 63
+#define	MASK_WCI_CSRA_STATUS_ESR_INDEX 0x78000000, 0x0, 59
+#define	MASK_WCI_CSRA_STATUS_SCAR 0x4000000, 0x0, 58
+#define	MASK_WCI_CSRA_STATUS_ATRANSID 0x3fe0000, 0x0, 49
+#define	MASK_WCI_CSRA_STATUS_TARGID_3_TO_0 0x1c000, 0x0, 46
+#define	MASK_WCI_CSRA_STATUS_CESR_NUMBER 0x3fc0, 0x0, 38
+#define	MASK_WCI_CSRA_STATUS_RW 0x20, 0x0, 37
+#define	MASK_WCI_CSRA_STATUS_NC_SLICE 0x1f, 0xe0000000, 29
+#define	MASK_WCI_CSRA_STATUS_SF_ADDR_28_TO_5 0x0, 0x1fffffe0, 5
+#define	MASK_WCI_CSRA_STATUS_FSM_STATE 0x0, 0x1c, 2
+#define	MASK_WCI_CSRA_STATUS_TYPE 0x0, 0x3, 0
+#define	MASK_WCI_CSRA_TIMEOUT_CONFIG_RSVD_Z 0xffffffff, 0xffe00000, 21
+#define	MASK_WCI_CSRA_TIMEOUT_CONFIG_PULL_TARGID_FAIL_FAST_ENABLE 0x0, \
+0x100000, 20
+#define	MASK_WCI_CSRA_TIMEOUT_CONFIG_PULL_FAIL_FAST_ENABLE 0x0, 0x80000, 19
+#define	MASK_WCI_CSRA_TIMEOUT_CONFIG_DISABLE 0x0, 0x40000, 18
+#define	MASK_WCI_CSRA_TIMEOUT_CONFIG_FREEZE 0x0, 0x20000, 17
+#define	MASK_WCI_CSRA_TIMEOUT_CONFIG_MAGNITUDE 0x0, 0x10000, 16
+#define	MASK_WCI_CSRA_TIMEOUT_CONFIG_RD_TIMEOUT 0x0, 0xff00, 8
+#define	MASK_WCI_CSRA_TIMEOUT_CONFIG_WR_TIMEOUT 0x0, 0xff, 0
+#define	MASK_WCI_DC_ESR_RSVD_Z 0xffffffff, 0xfc000000, 26
+#define	MASK_WCI_DC_ESR_ACC_DIF_TIMEOUT 0x0, 0x2000000, 25
+#define	MASK_WCI_DC_ESR_ACC_DCI_D_ERR_DSTAT 0x0, 0x1000000, 24
+#define	MASK_WCI_DC_ESR_ACC_DCO_CE 0x0, 0x800000, 23
+#define	MASK_WCI_DC_ESR_ACC_DC_DIF_OVERFLOW 0x0, 0x400000, 22
+#define	MASK_WCI_DC_ESR_ACC_DC_LAUNCH_QUEUE_OVERFLOW 0x0, 0x200000, 21
+#define	MASK_WCI_DC_ESR_ACC_DCO_MAP_ERROR 0x0, 0x100000, 20
+#define	MASK_WCI_DC_ESR_ACC_DCO_DATA_PARITY_ERROR 0x0, 0x80000, 19
+#define	MASK_WCI_DC_ESR_ACC_DCI_D_ERR 0x0, 0x40000, 18
+#define	MASK_WCI_DC_ESR_ACC_DCI_CPI_INVALID 0x0, 0x20000, 17
+#define	MASK_WCI_DC_ESR_ACC_DCI_CPI_SNID_MISMATCH 0x0, 0x10000, 16
+#define	MASK_WCI_DC_ESR_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_DC_ESR_RSVD_Y 0x0, 0x7c00, 10
+#define	MASK_WCI_DC_ESR_DIF_TIMEOUT 0x0, 0x200, 9
+#define	MASK_WCI_DC_ESR_DCI_D_ERR_DSTAT 0x0, 0x100, 8
+#define	MASK_WCI_DC_ESR_DCO_CE 0x0, 0x80, 7
+#define	MASK_WCI_DC_ESR_DC_DIF_OVERFLOW 0x0, 0x40, 6
+#define	MASK_WCI_DC_ESR_DC_LAUNCH_QUEUE_OVERFLOW 0x0, 0x20, 5
+#define	MASK_WCI_DC_ESR_DCO_MAP_ERROR 0x0, 0x10, 4
+#define	MASK_WCI_DC_ESR_DCO_DATA_PARITY_ERROR 0x0, 0x8, 3
+#define	MASK_WCI_DC_ESR_DCI_D_ERR 0x0, 0x4, 2
+#define	MASK_WCI_DC_ESR_DCI_CPI_INVALID 0x0, 0x2, 1
+#define	MASK_WCI_DC_ESR_DCI_CPI_SNID_MISMATCH 0x0, 0x1, 0
+#define	MASK_WCI_DC_ESR_MASK_RSVD_Z 0xffffffff, 0xfffffc00, 10
+#define	MASK_WCI_DC_ESR_MASK_DIF_TIMEOUT 0x0, 0x200, 9
+#define	MASK_WCI_DC_ESR_MASK_DCI_D_ERR_DSTAT 0x0, 0x100, 8
+#define	MASK_WCI_DC_ESR_MASK_DCO_CE 0x0, 0x80, 7
+#define	MASK_WCI_DC_ESR_MASK_DC_DIF_OVERFLOW 0x0, 0x40, 6
+#define	MASK_WCI_DC_ESR_MASK_DC_LAUNCH_QUEUE_OVERFLOW 0x0, 0x20, 5
+#define	MASK_WCI_DC_ESR_MASK_DCO_MAP_ERROR 0x0, 0x10, 4
+#define	MASK_WCI_DC_ESR_MASK_DCO_DATA_PARITY_ERROR 0x0, 0x8, 3
+#define	MASK_WCI_DC_ESR_MASK_DCI_D_ERR 0x0, 0x4, 2
+#define	MASK_WCI_DC_ESR_MASK_DCI_CPI_INVALID 0x0, 0x2, 1
+#define	MASK_WCI_DC_ESR_MASK_DCI_CPI_SNID_MISMATCH 0x0, 0x1, 0
+#define	MASK_WCI_DCI_STATE_RSVD_Z 0xffffffff, 0xff000000, 24
+#define	MASK_WCI_DCI_STATE_DCI_D_ERR_DTARG 0x0, 0x800000, 23
+#define	MASK_WCI_DCI_STATE_DCI_D_ERR_DTRANSID 0x0, 0x7fc000, 14
+#define	MASK_WCI_DCI_STATE_DCI_CPI_ERR_DTARG 0x0, 0x2000, 13
+#define	MASK_WCI_DCI_STATE_DCI_CPI_ERR_DTRANSID 0x0, 0x1ff0, 4
+#define	MASK_WCI_DCI_STATE_DCI_CPI_ERR_SOURCE_NID 0x0, 0xf, 0
+#define	MASK_WCI_DCO_CE_COUNT_RSVD_Z 0xffffffff, 0xffffff00, 8
+#define	MASK_WCI_DCO_CE_COUNT_CE_COUNT 0x0, 0xff, 0
+#define	MASK_WCI_DCO_STATE_LINK_0_LQ_OVERFLOW 0x80000000, 0x0, 63
+#define	MASK_WCI_DCO_STATE_LINK_1_LQ_OVERFLOW 0x40000000, 0x0, 62
+#define	MASK_WCI_DCO_STATE_LINK_2_LQ_OVERFLOW 0x20000000, 0x0, 61
+#define	MASK_WCI_DCO_STATE_RSVD_Z 0x18000000, 0x0, 59
+#define	MASK_WCI_DCO_STATE_LPBK_LQ_OVERFLOW 0x4000000, 0x0, 58
+#define	MASK_WCI_DCO_STATE_CSR_LQ_OVERFLOW 0x2000000, 0x0, 57
+#define	MASK_WCI_DCO_STATE_RSVD_Y 0x1f00000, 0x0, 52
+#define	MASK_WCI_DCO_STATE_DCO_MAP_ERROR_DTARG 0x80000, 0x0, 51
+#define	MASK_WCI_DCO_STATE_DCO_MAP_ERROR_DTRANSID 0x7fc00, 0x0, 42
+#define	MASK_WCI_DCO_STATE_MTAG_ECC_ERROR_AID 0x3f8, 0x0, 35
+#define	MASK_WCI_DCO_STATE_DATA_ECC_ERROR_AID 0x7, 0xf0000000, 28
+#define	MASK_WCI_DCO_STATE_DATA_ECC_UE 0x0, 0x8000000, 27
+#define	MASK_WCI_DCO_STATE_MTAG_ECC_UE 0x0, 0x4000000, 26
+#define	MASK_WCI_DCO_STATE_MTAG_SYNDROME_0 0x0, 0x3c00000, 22
+#define	MASK_WCI_DCO_STATE_MTAG_SYNDROME_1 0x0, 0x3c0000, 18
+#define	MASK_WCI_DCO_STATE_DATA_SYNDROME_0 0x0, 0x3fe00, 9
+#define	MASK_WCI_DCO_STATE_DATA_SYNDROME_1 0x0, 0x1ff, 0
+#define	MASK_WCI_DIF_TIMEOUT_CNTL_RSVD_Z 0xffffffff, 0xfffff000, 12
+#define	MASK_WCI_DIF_TIMEOUT_CNTL_TIMEOUT_DISABLE 0x0, 0x800, 11
+#define	MASK_WCI_DIF_TIMEOUT_CNTL_TIMEOUT_FREEZE 0x0, 0x400, 10
+#define	MASK_WCI_DIF_TIMEOUT_CNTL_TIMEOUT_MAG 0x0, 0x300, 8
+#define	MASK_WCI_DIF_TIMEOUT_CNTL_TIMEOUT_VAL 0x0, 0xff, 0
+#define	MASK_WCI_DIF_TIMEOUT_COUNT_RSVD_Z 0xffffffff, 0x0, 32
+#define	MASK_WCI_DIF_TIMEOUT_COUNT_COUNT 0x0, 0xffffffff, 0
+#define	MASK_WCI_DOMAIN_CONFIG_RSVD_Z 0xffffffff, 0xffff0000, 16
+#define	MASK_WCI_DOMAIN_CONFIG_DOMAIN_MASK 0x0, 0xffff, 0
+#define	MASK_WCI_EMISS_CNTL_ARRAY_RSVD_Z 0xfff80000, 0x0, 51
+#define	MASK_WCI_EMISS_CNTL_ARRAY_AUTO_RESET_ACTIVE 0x40000, 0x0, 50
+#define	MASK_WCI_EMISS_CNTL_ARRAY_ENABLED 0x20000, 0x0, 49
+#define	MASK_WCI_EMISS_CNTL_ARRAY_ADDRESS 0x1ffff, 0xfffff000, 12
+#define	MASK_WCI_EMISS_CNTL_ARRAY_NID 0x0, 0xf00, 8
+#define	MASK_WCI_EMISS_CNTL_ARRAY_LENGTH 0x0, 0xc0, 6
+#define	MASK_WCI_EMISS_CNTL_ARRAY_EVENT0 0x0, 0x38, 3
+#define	MASK_WCI_EMISS_CNTL_ARRAY_EVENT1 0x0, 0x7, 0
+#define	MASK_WCI_EMISS_DATA_ARRAY_RSVD_Z 0xfffff000, 0x0, 44
+#define	MASK_WCI_EMISS_DATA_ARRAY_EVENT0_COUNT 0xffc, 0x0, 34
+#define	MASK_WCI_EMISS_DATA_ARRAY_EVENT1_COUNT 0x3, 0xff000000, 24
+#define	MASK_WCI_EMISS_DATA_ARRAY_EVENT0_COUNT_ALL 0x0, 0xfff000, 12
+#define	MASK_WCI_EMISS_DATA_ARRAY_EVENT1_COUNT_ALL 0x0, 0xfff, 0
+#define	MASK_WCI_EMISS_RESET_CTL_RSVD_Z 0xffffffff, 0xffc00000, 22
+#define	MASK_WCI_EMISS_RESET_CTL_AUTO_RESET_MASK 0x0, 0x3ff000, 12
+#define	MASK_WCI_EMISS_RESET_CTL_COUNT 0x0, 0xfff, 0
+#define	MASK_WCI_ERROR_INDUCEMENT_RSVD_Z 0xff000000, 0x0, 56
+#define	MASK_WCI_ERROR_INDUCEMENT_INTERNAL_SRAM_VECTOR 0xfe0000, 0x0, 49
+#define	MASK_WCI_ERROR_INDUCEMENT_HMQ_P 0x10000, 0x0, 48
+#define	MASK_WCI_ERROR_INDUCEMENT_SLQ_P 0x8000, 0x0, 47
+#define	MASK_WCI_ERROR_INDUCEMENT_SFQ_P 0x4000, 0x0, 46
+#define	MASK_WCI_ERROR_INDUCEMENT_SRAM_ECC_XOR_2_SELECT 0x3f00, 0x0, 40
+#define	MASK_WCI_ERROR_INDUCEMENT_SRAM_ECC_XOR_1_SELECT 0xfc, 0x0, 34
+#define	MASK_WCI_ERROR_INDUCEMENT_SRAM_P 0x3, 0x0, 32
+#define	MASK_WCI_ERROR_INDUCEMENT_MTAG_ECC0_XOR 0x0, 0xf0000000, 28
+#define	MASK_WCI_ERROR_INDUCEMENT_MTAG_ECC1_XOR 0x0, 0xf000000, 24
+#define	MASK_WCI_ERROR_INDUCEMENT_MTAG0_XOR 0x0, 0xe00000, 21
+#define	MASK_WCI_ERROR_INDUCEMENT_MTAG1_XOR 0x0, 0x1c0000, 18
+#define	MASK_WCI_ERROR_INDUCEMENT_ECC0_XOR 0x0, 0x3fe00, 9
+#define	MASK_WCI_ERROR_INDUCEMENT_ECC1_XOR 0x0, 0x1ff, 0
+#define	MASK_WCI_ERROR_PAUSE_TIMER_HOLD_RSVD_Z 0xffffffff, 0xffffff00, 8
+#define	MASK_WCI_ERROR_PAUSE_TIMER_HOLD_CA_APHASE 0x0, 0x80, 7
+#define	MASK_WCI_ERROR_PAUSE_TIMER_HOLD_CA_DPHASE 0x0, 0x40, 6
+#define	MASK_WCI_ERROR_PAUSE_TIMER_HOLD_CA_REUSE 0x0, 0x20, 5
+#define	MASK_WCI_ERROR_PAUSE_TIMER_HOLD_RESERVED 0x0, 0x10, 4
+#define	MASK_WCI_ERROR_PAUSE_TIMER_HOLD_RA_CLUSTER_PRIMARY 0x0, 0x8, 3
+#define	MASK_WCI_ERROR_PAUSE_TIMER_HOLD_RA_SSM_PRIMARY 0x0, 0x4, 2
+#define	MASK_WCI_ERROR_PAUSE_TIMER_HOLD_HA_PRIMARY 0x0, 0x2, 1
+#define	MASK_WCI_ERROR_PAUSE_TIMER_HOLD_SA_PRIMARY 0x0, 0x1, 0
+#define	MASK_WCI_ERROR_SUMMARY_RSVD_Z 0xffffffff, 0xfffff800, 11
+#define	MASK_WCI_ERROR_SUMMARY_CCI_ERROR 0x0, 0x400, 10
+#define	MASK_WCI_ERROR_SUMMARY_REQUEST_AGENT_ERROR 0x0, 0x200, 9
+#define	MASK_WCI_ERROR_SUMMARY_HOME_AGENT_ERROR 0x0, 0x100, 8
+#define	MASK_WCI_ERROR_SUMMARY_SLAVE_AGENT_ERROR 0x0, 0x80, 7
+#define	MASK_WCI_ERROR_SUMMARY_CLUSTER_AGENT_ERROR 0x0, 0x40, 6
+#define	MASK_WCI_ERROR_SUMMARY_CSR_AGENT_ERROR 0x0, 0x20, 5
+#define	MASK_WCI_ERROR_SUMMARY_LC_ERROR 0x0, 0x10, 4
+#define	MASK_WCI_ERROR_SUMMARY_SFI_ERROR 0x0, 0x8, 3
+#define	MASK_WCI_ERROR_SUMMARY_SFQ_ERROR 0x0, 0x4, 2
+#define	MASK_WCI_ERROR_SUMMARY_DC_ERROR 0x0, 0x2, 1
+#define	MASK_WCI_ERROR_SUMMARY_HLI_ERROR 0x0, 0x1, 0
+#define	MASK_WCI_FIRST_ERROR_TIME_STICK_TIME 0xffffffff, 0xffffffff, 0
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_FO_ROUTE_MAP_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_FO_ROUTE_MAP_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_FO_ROUTE_MAP_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_FO_ROUTE_MAP_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_FO_ROUTE_MAP_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_FO_ROUTE_MAP_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_FO_ROUTE_MAP_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_FO_ROUTE_MAP_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_FO_ROUTE_MAP_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_FO_ROUTE_MAP_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_FO_ROUTE_MAP_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_FO_ROUTE_MAP_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_FO_ROUTE_MAP_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_FO_ROUTE_MAP_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_FO_ROUTE_MAP_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_FO_ROUTE_MAP_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_FO_ROUTE_MAP_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_FO_TNID_MAP_RSVD_Z 0xffffffff, 0xfffff000, 12
+#define	MASK_WCI_FO_TNID_MAP_LINK2_TNID 0x0, 0xf00, 8
+#define	MASK_WCI_FO_TNID_MAP_LINK1_TNID 0x0, 0xf0, 4
+#define	MASK_WCI_FO_TNID_MAP_LINK0_TNID 0x0, 0xf, 0
+#define	MASK_WCI_GENERATES_CESR_NUMBER_RSVD_Z 0xfffffffe, 0x0, 33
+#define	MASK_WCI_GENERATES_CESR_NUMBER_ENABLE 0x1, 0x0, 32
+#define	MASK_WCI_GENERATES_CESR_NUMBER_DEVICE_VECTOR 0x0, 0xffffffff, 0
+#define	MASK_WCI_GLOBAL_EMISS_COUNTER_RSVD_Z 0xffffffff, 0xff000000, 24
+#define	MASK_WCI_GLOBAL_EMISS_COUNTER_COUNT 0x0, 0xffffff, 0
+#define	MASK_WCI_GNID_MAP0_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_GNID_MAP0_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_GNID_MAP0_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_GNID_MAP0_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_GNID_MAP0_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_GNID_MAP0_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_GNID_MAP0_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_GNID_MAP0_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_GNID_MAP0_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_GNID_MAP0_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_GNID_MAP0_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_GNID_MAP0_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_GNID_MAP0_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_GNID_MAP0_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_GNID_MAP0_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_GNID_MAP0_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_GNID_MAP0_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_GNID_MAP0_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_GNID_MAP0_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_GNID_MAP0_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_GNID_MAP0_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_GNID_MAP0_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_GNID_MAP0_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_GNID_MAP0_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_GNID_MAP0_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_GNID_MAP0_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_GNID_MAP0_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_GNID_MAP0_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_GNID_MAP0_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_GNID_MAP0_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_GNID_MAP0_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_GNID_MAP0_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_GNID_MAP1_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_GNID_MAP1_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_GNID_MAP1_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_GNID_MAP1_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_GNID_MAP1_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_GNID_MAP1_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_GNID_MAP1_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_GNID_MAP1_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_GNID_MAP1_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_GNID_MAP1_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_GNID_MAP1_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_GNID_MAP1_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_GNID_MAP1_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_GNID_MAP1_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_GNID_MAP1_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_GNID_MAP1_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_GNID_MAP1_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_GNID_MAP1_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_GNID_MAP1_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_GNID_MAP1_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_GNID_MAP1_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_GNID_MAP1_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_GNID_MAP1_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_GNID_MAP1_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_GNID_MAP1_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_GNID_MAP1_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_GNID_MAP1_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_GNID_MAP1_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_GNID_MAP1_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_GNID_MAP1_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_GNID_MAP1_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_GNID_MAP1_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_HA_BUSY_RSVD_Z 0xffffffff, 0xffff0000, 16
+#define	MASK_WCI_HA_BUSY_VECTOR 0x0, 0xffff, 0
+#define	MASK_WCI_HA_CONFIG_RSVD_Z 0xffffffff, 0xfffffe00, 9
+#define	MASK_WCI_HA_CONFIG_SNID_IN_MASK 0x0, 0x100, 8
+#define	MASK_WCI_HA_CONFIG_DISABLE_SAME_BOX_OPT 0x0, 0x80, 7
+#define	MASK_WCI_HA_CONFIG_MIGRATORY_SHARING_CTRL 0x0, 0x7f, 0
+#define	MASK_WCI_HA_ECC_ADDRESS_DATA 0x80000000, 0x0, 63
+#define	MASK_WCI_HA_ECC_ADDRESS_UE 0x40000000, 0x0, 62
+#define	MASK_WCI_HA_ECC_ADDRESS_RSVD_Z 0x3ffff800, 0x0, 43
+#define	MASK_WCI_HA_ECC_ADDRESS_ADDR 0x7ff, 0xfffffff0, 4
+#define	MASK_WCI_HA_ECC_ADDRESS_RSVD_Y 0x0, 0xf, 0
+#define	MASK_WCI_HA_ERROR_ADDRESS_ESR_REG 0x80000000, 0x0, 63
+#define	MASK_WCI_HA_ERROR_ADDRESS_ESR_INDEX 0x78000000, 0x0, 59
+#define	MASK_WCI_HA_ERROR_ADDRESS_RSVD_Z 0x7fff800, 0x0, 43
+#define	MASK_WCI_HA_ERROR_ADDRESS_ADDR 0x7ff, 0xfffffff0, 4
+#define	MASK_WCI_HA_ERROR_ADDRESS_RSVD_Y 0x0, 0xf, 0
+#define	MASK_WCI_HA_ESR_0_RSVD_Z 0xffffffff, 0xe0000000, 29
+#define	MASK_WCI_HA_ESR_0_ACC_UNEXPECTED_SNID 0x0, 0x10000000, 28
+#define	MASK_WCI_HA_ESR_0_ACC_ADDRESS_NOT_MAPPED_IO 0x0, 0x8000000, 27
+#define	MASK_WCI_HA_ESR_0_ACC_DIR_PARITY_ERROR 0x0, 0x4000000, 26
+#define	MASK_WCI_HA_ESR_0_ACC_NOT_EXPECTED_COMPL 0x0, 0x2000000, 25
+#define	MASK_WCI_HA_ESR_0_ACC_ILLEGAL_SENDER 0x0, 0x1000000, 24
+#define	MASK_WCI_HA_ESR_0_ACC_WRONG_CMD 0x0, 0x800000, 23
+#define	MASK_WCI_HA_ESR_0_ACC_UNCORRECTABLE_MTAG_ERROR 0x0, 0x400000, 22
+#define	MASK_WCI_HA_ESR_0_ACC_UNCORRECTABLE_DATA_ERROR 0x0, 0x200000, 21
+#define	MASK_WCI_HA_ESR_0_ACC_CORRECTABLE_MTAG_ERROR 0x0, 0x100000, 20
+#define	MASK_WCI_HA_ESR_0_ACC_CORRECTABLE_DATA_ERROR 0x0, 0x80000, 19
+#define	MASK_WCI_HA_ESR_0_ACC_MTAG_MISMATCH_WITHIN_HCL 0x0, 0x40000, 18
+#define	MASK_WCI_HA_ESR_0_ACC_MTAG_MISMATCH_BETWEEN_HCLS 0x0, 0x20000, 17
+#define	MASK_WCI_HA_ESR_0_ACC_TIMEOUT 0x0, 0x10000, 16
+#define	MASK_WCI_HA_ESR_0_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_HA_ESR_0_RSVD_Y 0x0, 0x6000, 13
+#define	MASK_WCI_HA_ESR_0_UNEXPECTED_SNID 0x0, 0x1000, 12
+#define	MASK_WCI_HA_ESR_0_ADDRESS_NOT_MAPPED_IO 0x0, 0x800, 11
+#define	MASK_WCI_HA_ESR_0_DIR_PARITY_ERROR 0x0, 0x400, 10
+#define	MASK_WCI_HA_ESR_0_NOT_EXPECTED_COMPL 0x0, 0x200, 9
+#define	MASK_WCI_HA_ESR_0_ILLEGAL_SENDER 0x0, 0x100, 8
+#define	MASK_WCI_HA_ESR_0_WRONG_CMD 0x0, 0x80, 7
+#define	MASK_WCI_HA_ESR_0_UNCORRECTABLE_MTAG_ERROR 0x0, 0x40, 6
+#define	MASK_WCI_HA_ESR_0_UNCORRECTABLE_DATA_ERROR 0x0, 0x20, 5
+#define	MASK_WCI_HA_ESR_0_CORRECTABLE_MTAG_ERROR 0x0, 0x10, 4
+#define	MASK_WCI_HA_ESR_0_CORRECTABLE_DATA_ERROR 0x0, 0x8, 3
+#define	MASK_WCI_HA_ESR_0_MTAG_MISMATCH_WITHIN_HCL 0x0, 0x4, 2
+#define	MASK_WCI_HA_ESR_0_MTAG_MISMATCH_BETWEEN_HCLS 0x0, 0x2, 1
+#define	MASK_WCI_HA_ESR_0_TIMEOUT 0x0, 0x1, 0
+#define	MASK_WCI_HA_ESR_1_RSVD_Z 0xffffffff, 0xffc00000, 22
+#define	MASK_WCI_HA_ESR_1_ACC_GNR_ERR 0x0, 0x200000, 21
+#define	MASK_WCI_HA_ESR_1_ACC_HW_ERR 0x0, 0x100000, 20
+#define	MASK_WCI_HA_ESR_1_ACC_ADDRESS_NOT_MAPPED 0x0, 0x80000, 19
+#define	MASK_WCI_HA_ESR_1_ACC_DSTAT_INCONSISTENT 0x0, 0x40000, 18
+#define	MASK_WCI_HA_ESR_1_ACC_MTAG_NOT_GM 0x0, 0x20000, 17
+#define	MASK_WCI_HA_ESR_1_ACC_UNEXPECTED_MTAG 0x0, 0x10000, 16
+#define	MASK_WCI_HA_ESR_1_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_HA_ESR_1_RSVD_Y 0x0, 0x7fc0, 6
+#define	MASK_WCI_HA_ESR_1_GNR_ERR 0x0, 0x20, 5
+#define	MASK_WCI_HA_ESR_1_HW_ERR 0x0, 0x10, 4
+#define	MASK_WCI_HA_ESR_1_ADDRESS_NOT_MAPPED 0x0, 0x8, 3
+#define	MASK_WCI_HA_ESR_1_DSTAT_INCONSISTENT 0x0, 0x4, 2
+#define	MASK_WCI_HA_ESR_1_MTAG_NOT_GM 0x0, 0x2, 1
+#define	MASK_WCI_HA_ESR_1_UNEXPECTED_MTAG 0x0, 0x1, 0
+#define	MASK_WCI_HA_ESR_MASK_RSVD_Z 0xffffffff, 0xffc00000, 22
+#define	MASK_WCI_HA_ESR_MASK_GNR_ERR 0x0, 0x200000, 21
+#define	MASK_WCI_HA_ESR_MASK_HW_ERR 0x0, 0x100000, 20
+#define	MASK_WCI_HA_ESR_MASK_ADDRESS_NOT_MAPPED 0x0, 0x80000, 19
+#define	MASK_WCI_HA_ESR_MASK_DSTAT_INCONSISTENT 0x0, 0x40000, 18
+#define	MASK_WCI_HA_ESR_MASK_MTAG_NOT_GM 0x0, 0x20000, 17
+#define	MASK_WCI_HA_ESR_MASK_UNEXPECTED_MTAG 0x0, 0x10000, 16
+#define	MASK_WCI_HA_ESR_MASK_RSVD_Y 0x0, 0xe000, 13
+#define	MASK_WCI_HA_ESR_MASK_UNEXPECTED_SNID 0x0, 0x1000, 12
+#define	MASK_WCI_HA_ESR_MASK_ADDRESS_NOT_MAPPED_IO 0x0, 0x800, 11
+#define	MASK_WCI_HA_ESR_MASK_DIR_PARITY_ERROR 0x0, 0x400, 10
+#define	MASK_WCI_HA_ESR_MASK_NOT_EXPECTED_COMPL 0x0, 0x200, 9
+#define	MASK_WCI_HA_ESR_MASK_ILLEGAL_SENDER 0x0, 0x100, 8
+#define	MASK_WCI_HA_ESR_MASK_WRONG_CMD 0x0, 0x80, 7
+#define	MASK_WCI_HA_ESR_MASK_UNCORRECTABLE_MTAG_ERROR 0x0, 0x40, 6
+#define	MASK_WCI_HA_ESR_MASK_UNCORRECTABLE_DATA_ERROR 0x0, 0x20, 5
+#define	MASK_WCI_HA_ESR_MASK_CORRECTABLE_MTAG_ERROR 0x0, 0x10, 4
+#define	MASK_WCI_HA_ESR_MASK_CORRECTABLE_DATA_ERROR 0x0, 0x8, 3
+#define	MASK_WCI_HA_ESR_MASK_MTAG_MISMATCH_WITHIN_HCL 0x0, 0x4, 2
+#define	MASK_WCI_HA_ESR_MASK_MTAG_MISMATCH_BETWEEN_HCLS 0x0, 0x2, 1
+#define	MASK_WCI_HA_ESR_MASK_TIMEOUT 0x0, 0x1, 0
+#define	MASK_WCI_HA_FIRST_ERROR_AGENT_ESR_REG 0x80000000, 0x0, 63
+#define	MASK_WCI_HA_FIRST_ERROR_AGENT_ESR_INDEX 0x78000000, 0x0, 59
+#define	MASK_WCI_HA_FIRST_ERROR_AGENT_RSVD_Z 0x7ffffff, 0xffffffe0, 5
+#define	MASK_WCI_HA_FIRST_ERROR_AGENT_INSTANCE 0x0, 0x1f, 0
+#define	MASK_WCI_HA_FIRST_PACKET_0_LO_A 0xfffffff0, 0x0, 36
+#define	MASK_WCI_HA_FIRST_PACKET_0_RSVD_Z 0xf, 0xf0000000, 28
+#define	MASK_WCI_HA_FIRST_PACKET_0_LO_B 0x0, 0xfffffff, 0
+#define	MASK_WCI_HA_FIRST_PACKET_1_ESR_REG 0x80000000, 0x0, 63
+#define	MASK_WCI_HA_FIRST_PACKET_1_ESR_INDEX 0x78000000, 0x0, 59
+#define	MASK_WCI_HA_FIRST_PACKET_1_RSVD_Z 0x7ffffff, 0x80000000, 31
+#define	MASK_WCI_HA_FIRST_PACKET_1_HI 0x0, 0x7fffffff, 0
+#define	MASK_WCI_HA_FREEZE_RSVD_Z 0xffffffff, 0xffff0000, 16
+#define	MASK_WCI_HA_FREEZE_VECTOR 0x0, 0xffff, 0
+#define	MASK_WCI_HA_HW_ERR_STATUS_RSVD_Z 0xffffffff, 0xfff80000, 19
+#define	MASK_WCI_HA_HW_ERR_STATUS_OH_ERROR_CASE_FALL_THROUGH 0x0, 0x40000, 18
+#define	MASK_WCI_HA_HW_ERR_STATUS_DIR_FETCHQ_OVFL 0x0, 0x20000, 17
+#define	MASK_WCI_HA_HW_ERR_STATUS_DIR_FETCHQ_UNFL 0x0, 0x10000, 16
+#define	MASK_WCI_HA_HW_ERR_STATUS_SRQ4_ERRORS_OVFL 0x0, 0x8000, 15
+#define	MASK_WCI_HA_HW_ERR_STATUS_SRQ4_ERRORS_UNFL 0x0, 0x4000, 14
+#define	MASK_WCI_HA_HW_ERR_STATUS_SRQ3_ERRORS_OVFL 0x0, 0x2000, 13
+#define	MASK_WCI_HA_HW_ERR_STATUS_SRQ3_ERRORS_UNFL 0x0, 0x1000, 12
+#define	MASK_WCI_HA_HW_ERR_STATUS_SRQ2_ERRORS_OVFL 0x0, 0x800, 11
+#define	MASK_WCI_HA_HW_ERR_STATUS_SRQ2_ERRORS_UNFL 0x0, 0x400, 10
+#define	MASK_WCI_HA_HW_ERR_STATUS_SRQ1_ERRORS_OVFL 0x0, 0x200, 9
+#define	MASK_WCI_HA_HW_ERR_STATUS_SRQ1_ERRORS_UNFL 0x0, 0x100, 8
+#define	MASK_WCI_HA_HW_ERR_STATUS_KMAPQ_ERRORS_OVFL 0x0, 0x80, 7
+#define	MASK_WCI_HA_HW_ERR_STATUS_KMAPQ_ERRORS_UNFL 0x0, 0x40, 6
+#define	MASK_WCI_HA_HW_ERR_STATUS_OHQ_ERRORS_OVFL 0x0, 0x20, 5
+#define	MASK_WCI_HA_HW_ERR_STATUS_OHQ_ERRORS_UNFL 0x0, 0x10, 4
+#define	MASK_WCI_HA_HW_ERR_STATUS_SHQ_ERRORS_OVFL 0x0, 0x8, 3
+#define	MASK_WCI_HA_HW_ERR_STATUS_SHQ_ERRORS_UNFL 0x0, 0x4, 2
+#define	MASK_WCI_HA_HW_ERR_STATUS_DHC_ALL_UEXP_RCV_ERROR 0x0, 0x2, 1
+#define	MASK_WCI_HA_HW_ERR_STATUS_DHC_ALL_UEXP_SND_ERROR 0x0, 0x1, 0
+#define	MASK_WCI_HA_STATUS_2_ARRAY_RSVD_Z 0xfffffffc, 0x0, 34
+#define	MASK_WCI_HA_STATUS_2_ARRAY_DIR_VLD 0x2, 0x0, 33
+#define	MASK_WCI_HA_STATUS_2_ARRAY_DIR_HIT 0x1, 0x0, 32
+#define	MASK_WCI_HA_STATUS_2_ARRAY_OLD_DIR_ENTRY 0x0, 0xfff00000, 20
+#define	MASK_WCI_HA_STATUS_2_ARRAY_RSVD_Y 0x0, 0x80000, 19
+#define	MASK_WCI_HA_STATUS_2_ARRAY_OLD_MTAG 0x0, 0x70000, 16
+#define	MASK_WCI_HA_STATUS_2_ARRAY_DIR_COPT 0x0, 0xc000, 14
+#define	MASK_WCI_HA_STATUS_2_ARRAY_DATA_COPT 0x0, 0x3000, 12
+#define	MASK_WCI_HA_STATUS_2_ARRAY_RSVD_X 0x0, 0xe00, 9
+#define	MASK_WCI_HA_STATUS_2_ARRAY_SAFARI_THREAD 0x0, 0x100, 8
+#define	MASK_WCI_HA_STATUS_2_ARRAY_AUXID_THREAD 0x0, 0x80, 7
+#define	MASK_WCI_HA_STATUS_2_ARRAY_CMPL_THREAD 0x0, 0x40, 6
+#define	MASK_WCI_HA_STATUS_2_ARRAY_DATA_SENT_THREAD 0x0, 0x20, 5
+#define	MASK_WCI_HA_STATUS_2_ARRAY_DATA_RCVD_THREAD 0x0, 0x10, 4
+#define	MASK_WCI_HA_STATUS_2_ARRAY_DOB_CLRD_THREAD 0x0, 0x8, 3
+#define	MASK_WCI_HA_STATUS_2_ARRAY_HDR_SENT_THREAD 0x0, 0x4, 2
+#define	MASK_WCI_HA_STATUS_2_ARRAY_CONSTMAP_THREAD 0x0, 0x2, 1
+#define	MASK_WCI_HA_STATUS_2_ARRAY_PULL_SEEN_THREAD 0x0, 0x1, 0
+#define	MASK_WCI_HA_STATUS_ARRAY_ORIG_ATRANSID 0xff800000, 0x0, 55
+#define	MASK_WCI_HA_STATUS_ARRAY_ORIG_RTID 0x7c0000, 0x0, 50
+#define	MASK_WCI_HA_STATUS_ARRAY_DISPATCHED_OP 0x3f000, 0x0, 44
+#define	MASK_WCI_HA_STATUS_ARRAY_RSVD_Z 0x800, 0x0, 43
+#define	MASK_WCI_HA_STATUS_ARRAY_ORIG_ADDR 0x7ff, 0xfffffff0, 4
+#define	MASK_WCI_HA_STATUS_ARRAY_ORIG_SNID 0x0, 0xf, 0
+#define	MASK_WCI_HA_TIMEOUT_CONFIG_RSVD_Z 0xffffffff, 0xffffc000, 14
+#define	MASK_WCI_HA_TIMEOUT_CONFIG_SSM_DISABLE 0x0, 0x2000, 13
+#define	MASK_WCI_HA_TIMEOUT_CONFIG_SSM_FREEZE 0x0, 0x1000, 12
+#define	MASK_WCI_HA_TIMEOUT_CONFIG_RSVD_Y 0x0, 0xc00, 10
+#define	MASK_WCI_HA_TIMEOUT_CONFIG_SSM_MAG 0x0, 0x300, 8
+#define	MASK_WCI_HA_TIMEOUT_CONFIG_SSM_VAL 0x0, 0xff, 0
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_HAG_ROUTE_MAP0_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_HAG_ROUTE_MAP0_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_HAG_ROUTE_MAP1_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_HAG_ROUTE_MAP1_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_HLI_ESR_RSVD_Z 0xffffffff, 0xff800000, 23
+#define	MASK_WCI_HLI_ESR_ACC_SLQ_PERR 0x0, 0x400000, 22
+#define	MASK_WCI_HLI_ESR_ACC_HMQ_PERR 0x0, 0x200000, 21
+#define	MASK_WCI_HLI_ESR_ACC_STRANGE_PKT 0x0, 0x100000, 20
+#define	MASK_WCI_HLI_ESR_ACC_BQ_UNFL 0x0, 0x80000, 19
+#define	MASK_WCI_HLI_ESR_ACC_HMQ_UNFL 0x0, 0x40000, 18
+#define	MASK_WCI_HLI_ESR_ACC_HMQ_OVFL 0x0, 0x20000, 17
+#define	MASK_WCI_HLI_ESR_ACC_SLQ_OVFL 0x0, 0x10000, 16
+#define	MASK_WCI_HLI_ESR_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_HLI_ESR_RSVD_Y 0x0, 0x7f80, 7
+#define	MASK_WCI_HLI_ESR_SLQ_PERR 0x0, 0x40, 6
+#define	MASK_WCI_HLI_ESR_HMQ_PERR 0x0, 0x20, 5
+#define	MASK_WCI_HLI_ESR_STRANGE_PKT 0x0, 0x10, 4
+#define	MASK_WCI_HLI_ESR_BQ_UNFL 0x0, 0x8, 3
+#define	MASK_WCI_HLI_ESR_HMQ_UNFL 0x0, 0x4, 2
+#define	MASK_WCI_HLI_ESR_HMQ_OVFL 0x0, 0x2, 1
+#define	MASK_WCI_HLI_ESR_SLQ_OVFL 0x0, 0x1, 0
+#define	MASK_WCI_HLI_ESR_MASK_RSVD_Z 0xffffffff, 0xffffff80, 7
+#define	MASK_WCI_HLI_ESR_MASK_SLQ_PERR 0x0, 0x40, 6
+#define	MASK_WCI_HLI_ESR_MASK_HMQ_PERR 0x0, 0x20, 5
+#define	MASK_WCI_HLI_ESR_MASK_STRANGE_PKT 0x0, 0x10, 4
+#define	MASK_WCI_HLI_ESR_MASK_BQ_UNFL 0x0, 0x8, 3
+#define	MASK_WCI_HLI_ESR_MASK_HMQ_UNFL 0x0, 0x4, 2
+#define	MASK_WCI_HLI_ESR_MASK_HMQ_OVFL 0x0, 0x2, 1
+#define	MASK_WCI_HLI_ESR_MASK_SLQ_OVFL 0x0, 0x1, 0
+#define	MASK_WCI_HLI_STATE_RSVD_Z 0x80000000, 0x0, 63
+#define	MASK_WCI_HLI_STATE_ESR_INDEX 0x78000000, 0x0, 59
+#define	MASK_WCI_HLI_STATE_RSVD_Y 0x7ffffff, 0xfe000000, 25
+#define	MASK_WCI_HLI_STATE_QUEUE 0x0, 0x1ffff00, 8
+#define	MASK_WCI_HLI_STATE_INDEX 0x0, 0xff, 0
+#define	MASK_WCI_HLI_STRANGE_PKT_0_LO 0xffffffff, 0xffffffff, 0
+#define	MASK_WCI_HLI_STRANGE_PKT_1_RSVD_Z 0xffffffff, 0x80000000, 31
+#define	MASK_WCI_HLI_STRANGE_PKT_1_HI 0x0, 0x7fffffff, 0
+#define	MASK_WCI_ID_RSVD_Z 0xffffffff, 0x0, 32
+#define	MASK_WCI_ID_VERSION 0x0, 0xf0000000, 28
+#define	MASK_WCI_ID_PARID 0x0, 0xffff000, 12
+#define	MASK_WCI_ID_MANFID 0x0, 0xffe, 1
+#define	MASK_WCI_ID_ONE 0x0, 0x1, 0
+#define	MASK_WCI_INID2DNID_ARRAY_RSVD_Z 0xffffffff, 0xfffffff0, 4
+#define	MASK_WCI_INID2DNID_ARRAY_DNID 0x0, 0xf, 0
+#define	MASK_WCI_INT_DEST_BUSY_COUNT_VALUE 0xffffffff, 0xffffffff, 0
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_JNK_ROUTE_MAP0_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_JNK_ROUTE_MAP0_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_JNK_ROUTE_MAP1_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_JNK_ROUTE_MAP1_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_LINK_CTR_CNT1 0xffffffff, 0x0, 32
+#define	MASK_WCI_LINK_CTR_CNT0 0x0, 0xffffffff, 0
+#define	MASK_WCI_LINK_CTR_CTL_RSVD_Z 0xffffffff, 0x80000000, 31
+#define	MASK_WCI_LINK_CTR_CTL_CNT1_SOURCE_SELECT 0x0, 0x60000000, 29
+#define	MASK_WCI_LINK_CTR_CTL_CNT1_GNID_TARGET 0x0, 0x1e000000, 25
+#define	MASK_WCI_LINK_CTR_CTL_CNT1_SNID_TARGET 0x0, 0x1e00000, 21
+#define	MASK_WCI_LINK_CTR_CTL_CNT1_RCVD_ADMIN_PACKET 0x0, 0x100000, 20
+#define	MASK_WCI_LINK_CTR_CTL_CNT1_REJECTED_NORMAL_FLIT 0x0, 0x80000, 19
+#define	MASK_WCI_LINK_CTR_CTL_CNT1_DATA_RCVD_DATA_PACKET 0x0, 0x40000, 18
+#define	MASK_WCI_LINK_CTR_CTL_CNT1_MHOP_RCVD_DATA_PACKET 0x0, 0x20000, 17
+#define	MASK_WCI_LINK_CTR_CTL_CNT1_XMITTING_ADMIN_PACKET 0x0, 0x10000, 16
+#define	MASK_WCI_LINK_CTR_CTL_RSVD_Y 0x0, 0x8000, 15
+#define	MASK_WCI_LINK_CTR_CTL_CNT0_SOURCE_SELECT 0x0, 0x6000, 13
+#define	MASK_WCI_LINK_CTR_CTL_CNT0_GNID_TARGET 0x0, 0x1e00, 9
+#define	MASK_WCI_LINK_CTR_CTL_CNT0_SNID_TARGET 0x0, 0x1e0, 5
+#define	MASK_WCI_LINK_CTR_CTL_CNT0_RCVD_ADMIN_PACKET 0x0, 0x10, 4
+#define	MASK_WCI_LINK_CTR_CTL_CNT0_REJECTED_NORMAL_FLIT 0x0, 0x8, 3
+#define	MASK_WCI_LINK_CTR_CTL_CNT0_DATA_RCVD_DATA_PACKET 0x0, 0x4, 2
+#define	MASK_WCI_LINK_CTR_CTL_CNT0_MHOP_RCVD_DATA_PACKET 0x0, 0x2, 1
+#define	MASK_WCI_LINK_CTR_CTL_CNT0_XMITTING_ADMIN_PACKET 0x0, 0x1, 0
+#define	MASK_WCI_LINK_ESR_RSVD_Z 0xffffffff, 0xff000000, 24
+#define	MASK_WCI_LINK_ESR_ACC_LINK_2_ILLEGAL_GNID 0x0, 0x800000, 23
+#define	MASK_WCI_LINK_ESR_ACC_LINK_2_ILLEGAL_LINK 0x0, 0x400000, 22
+#define	MASK_WCI_LINK_ESR_RSVD_Y 0x0, 0x200000, 21
+#define	MASK_WCI_LINK_ESR_ACC_LINK_1_ILLEGAL_GNID 0x0, 0x100000, 20
+#define	MASK_WCI_LINK_ESR_ACC_LINK_1_ILLEGAL_LINK 0x0, 0x80000, 19
+#define	MASK_WCI_LINK_ESR_RSVD_X 0x0, 0x40000, 18
+#define	MASK_WCI_LINK_ESR_ACC_LINK_0_ILLEGAL_GNID 0x0, 0x20000, 17
+#define	MASK_WCI_LINK_ESR_ACC_LINK_0_ILLEGAL_LINK 0x0, 0x10000, 16
+#define	MASK_WCI_LINK_ESR_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_LINK_ESR_RSVD_W 0x0, 0x7f00, 8
+#define	MASK_WCI_LINK_ESR_LINK_2_ILLEGAL_GNID 0x0, 0x80, 7
+#define	MASK_WCI_LINK_ESR_LINK_2_ILLEGAL_LINK 0x0, 0x40, 6
+#define	MASK_WCI_LINK_ESR_RSVD_V 0x0, 0x20, 5
+#define	MASK_WCI_LINK_ESR_LINK_1_ILLEGAL_GNID 0x0, 0x10, 4
+#define	MASK_WCI_LINK_ESR_LINK_1_ILLEGAL_LINK 0x0, 0x8, 3
+#define	MASK_WCI_LINK_ESR_RSVD_U 0x0, 0x4, 2
+#define	MASK_WCI_LINK_ESR_LINK_0_ILLEGAL_GNID 0x0, 0x2, 1
+#define	MASK_WCI_LINK_ESR_LINK_0_ILLEGAL_LINK 0x0, 0x1, 0
+#define	MASK_WCI_LINK_ESR_MASK_RSVD_Z 0xffffffff, 0xffffff00, 8
+#define	MASK_WCI_LINK_ESR_MASK_LINK_2_ILLEGAL_GNID 0x0, 0x80, 7
+#define	MASK_WCI_LINK_ESR_MASK_LINK_2_ILLEGAL_LINK 0x0, 0x40, 6
+#define	MASK_WCI_LINK_ESR_MASK_RSVD_Y 0x0, 0x20, 5
+#define	MASK_WCI_LINK_ESR_MASK_LINK_1_ILLEGAL_GNID 0x0, 0x10, 4
+#define	MASK_WCI_LINK_ESR_MASK_LINK_1_ILLEGAL_LINK 0x0, 0x8, 3
+#define	MASK_WCI_LINK_ESR_MASK_RSVD_X 0x0, 0x4, 2
+#define	MASK_WCI_LINK_ESR_MASK_LINK_0_ILLEGAL_GNID 0x0, 0x2, 1
+#define	MASK_WCI_LINK_ESR_MASK_LINK_0_ILLEGAL_LINK 0x0, 0x1, 0
+#define	MASK_WCI_LOCAL_DEVICE_ID_SKIP_RS_VEC 0xffffffff, 0x0, 32
+#define	MASK_WCI_LOCAL_DEVICE_ID_SSM_MASK 0x0, 0xffffffff, 0
+#define	MASK_WCI_LPBK_CTR_CNT1 0xffffffff, 0x0, 32
+#define	MASK_WCI_LPBK_CTR_CNT0 0x0, 0xffffffff, 0
+#define	MASK_WCI_LPBK_CTR_CTL_RSVD_Z 0xffffffff, 0xfc000000, 26
+#define	MASK_WCI_LPBK_CTR_CTL_CNT1_DATA_GNID_SOURCE_SELECT 0x0, 0x2000000, 25
+#define	MASK_WCI_LPBK_CTR_CTL_CNT1_DATA_GNID_TARGET 0x0, 0x1e00000, 21
+#define	MASK_WCI_LPBK_CTR_CTL_CNT1_ADDR_LPBK_FULL 0x0, 0x100000, 20
+#define	MASK_WCI_LPBK_CTR_CTL_CNT1_DATA_LPBK_FULL 0x0, 0x80000, 19
+#define	MASK_WCI_LPBK_CTR_CTL_CNT1_ADDR_LPBK_RCVD_ADDR_1_PACKET 0x0, 0x40000, 18
+#define	MASK_WCI_LPBK_CTR_CTL_CNT1_ADDR_LPBK_RCVD_ADDR_2_PACKET 0x0, 0x20000, 17
+#define	MASK_WCI_LPBK_CTR_CTL_CNT1_DATA_LPBK_RCVD_DATA_PACKET 0x0, 0x10000, 16
+#define	MASK_WCI_LPBK_CTR_CTL_RSVD_Y 0x0, 0xfc00, 10
+#define	MASK_WCI_LPBK_CTR_CTL_CNT0_DATA_GNID_SOURCE_SELECT 0x0, 0x200, 9
+#define	MASK_WCI_LPBK_CTR_CTL_CNT0_DATA_GNID_TARGET 0x0, 0x1e0, 5
+#define	MASK_WCI_LPBK_CTR_CTL_CNT0_ADDR_LPBK_FULL 0x0, 0x10, 4
+#define	MASK_WCI_LPBK_CTR_CTL_CNT0_DATA_LPBK_FULL 0x0, 0x8, 3
+#define	MASK_WCI_LPBK_CTR_CTL_CNT0_ADDR_LPBK_RCVD_ADDR_1_PACKET 0x0, 0x4, 2
+#define	MASK_WCI_LPBK_CTR_CTL_CNT0_ADDR_LPBK_RCVD_ADDR_2_PACKET 0x0, 0x2, 1
+#define	MASK_WCI_LPBK_CTR_CTL_CNT0_DATA_LPBK_RCVD_DATA_PACKET 0x0, 0x1, 0
+#define	MASK_WCI_MAX_RSVD_Z 0xfffffff8, 0x0, 35
+#define	MASK_WCI_MAX_SEL 0x7, 0x0, 32
+#define	MASK_WCI_MAX_VALUE 0x0, 0xffffffff, 0
+#define	MASK_WCI_MISC_CTR_COUNT1 0xffffffff, 0x0, 32
+#define	MASK_WCI_MISC_CTR_COUNT0 0x0, 0xffffffff, 0
+#define	MASK_WCI_MISC_CTR_CTL_RSVD_Z 0xffffffff, 0xffe00000, 21
+#define	MASK_WCI_MISC_CTR_CTL_DURATION_MODE 0x0, 0x100000, 20
+#define	MASK_WCI_MISC_CTR_CTL_CNT1_AGENT_SELECT 0x0, 0xf0000, 16
+#define	MASK_WCI_MISC_CTR_CTL_CNT1_EVENT_SELECT 0x0, 0xfc00, 10
+#define	MASK_WCI_MISC_CTR_CTL_CNT0_AGENT_SELECT 0x0, 0x3c0, 6
+#define	MASK_WCI_MISC_CTR_CTL_CNT0_EVENT_SELECT 0x0, 0x3f, 0
+#define	MASK_WCI_MONITOR_PINS_RSVD_Z 0xffff0000, 0x0, 48
+#define	MASK_WCI_MONITOR_PINS_MONITOR_PINS 0xffff, 0x0, 32
+#define	MASK_WCI_MONITOR_PINS_RSVD_Y 0x0, 0xfffffe00, 9
+#define	MASK_WCI_MONITOR_PINS_SIGNAL_SEL 0x0, 0x1f0, 4
+#define	MASK_WCI_MONITOR_PINS_MODULE_SEL 0x0, 0xf, 0
+#define	MASK_WCI_NC2NID_ARRAY_RSVD_Z 0xffffffff, 0xffffff00, 8
+#define	MASK_WCI_NC2NID_ARRAY_NO_STRIPE 0x0, 0x80, 7
+#define	MASK_WCI_NC2NID_ARRAY_ENCODE_CLUSTER_ORIGIN_TAG 0x0, 0x40, 6
+#define	MASK_WCI_NC2NID_ARRAY_LAUNCH_REMOTE 0x0, 0x20, 5
+#define	MASK_WCI_NC2NID_ARRAY_LAUNCH_LOCAL_SRAM 0x0, 0x10, 4
+#define	MASK_WCI_NC2NID_ARRAY_DEST_NODE_ID 0x0, 0xf, 0
+#define	MASK_WCI_NC_SLICE_CONFIG_ARRAY_CONFIG 0xffffffff, 0xffffffff, 0
+#define	MASK_WCI_OS_CLUSTER_DISABLE_RSVD_Z 0xffffffff, 0xfffffff0, 4
+#define	MASK_WCI_OS_CLUSTER_DISABLE_CA_CLUSTER_DISABLE 0x0, 0x8, 3
+#define	MASK_WCI_OS_CLUSTER_DISABLE_RA_PIQ_DISABLE 0x0, 0x4, 2
+#define	MASK_WCI_OS_CLUSTER_DISABLE_RA_NIQ_DISABLE 0x0, 0x2, 1
+#define	MASK_WCI_OS_CLUSTER_DISABLE_RA_CIQ_DISABLE 0x0, 0x1, 0
+#define	MASK_WCI_PROBE_MEMORY_DONE 0x80000000, 0x0, 63
+#define	MASK_WCI_PROBE_MEMORY_IN_PROGRESS 0x40000000, 0x0, 62
+#define	MASK_WCI_PROBE_MEMORY_RSVD_Z 0x3fff8000, 0x0, 47
+#define	MASK_WCI_PROBE_MEMORY_MTAG 0x7000, 0x0, 44
+#define	MASK_WCI_PROBE_MEMORY_RSVD_Y 0x800, 0x0, 43
+#define	MASK_WCI_PROBE_MEMORY_ADDRESS 0x7ff, 0xfffffff0, 4
+#define	MASK_WCI_PROBE_MEMORY_RSVD_X 0x0, 0xf, 0
+#define	MASK_WCI_QLIM_2REQ_PRIORITY_RSVD_Z 0xf0000000, 0x0, 60
+#define	MASK_WCI_QLIM_2REQ_PRIORITY_CIQ_NIQ_NUM_SLOTS 0xf000000, 0x0, 56
+#define	MASK_WCI_QLIM_2REQ_PRIORITY_PIQ_CIQ_NUM_SLOTS 0xf00000, 0x0, 52
+#define	MASK_WCI_QLIM_2REQ_PRIORITY_NIQ_PIQ_NUM_SLOTS 0xf0000, 0x0, 48
+#define	MASK_WCI_QLIM_2REQ_PRIORITY_CIQ_NIQ_ARB_SLOTS 0xffff, 0x0, 32
+#define	MASK_WCI_QLIM_2REQ_PRIORITY_PIQ_CIQ_ARB_SLOTS 0x0, 0xffff0000, 16
+#define	MASK_WCI_QLIM_2REQ_PRIORITY_NIQ_PIQ_ARB_SLOTS 0x0, 0xffff, 0
+#define	MASK_WCI_QLIM_3REQ_PRIORITY_RSVD_Z 0xfffffff0, 0x0, 36
+#define	MASK_WCI_QLIM_3REQ_PRIORITY_NUM_SLOTS 0xf, 0x0, 32
+#define	MASK_WCI_QLIM_3REQ_PRIORITY_ARB_SLOTS 0x0, 0xffffffff, 0
+#define	MASK_WCI_QLIM_CAG_TIMER_RSVD_Z 0xffffffff, 0xe0000000, 29
+#define	MASK_WCI_QLIM_CAG_TIMER_VALUE 0x0, 0x1fffffff, 0
+#define	MASK_WCI_QLIM_CIQ_TIMER_RSVD_Z 0xffffffff, 0xe0000000, 29
+#define	MASK_WCI_QLIM_CIQ_TIMER_VALUE 0x0, 0x1fffffff, 0
+#define	MASK_WCI_QLIM_CONFIG_CAG_FREEZE 0x80000000, 0x0, 63
+#define	MASK_WCI_QLIM_CONFIG_CAG_DISABLE 0x40000000, 0x0, 62
+#define	MASK_WCI_QLIM_CONFIG_CAG_RSVD_Z 0x3fe00000, 0x0, 53
+#define	MASK_WCI_QLIM_CONFIG_CAG_MAX_DISCARD 0x1fff00, 0x0, 40
+#define	MASK_WCI_QLIM_CONFIG_CAG_RSVD_Y 0xc0, 0x0, 38
+#define	MASK_WCI_QLIM_CONFIG_CAG_NUM2DISCARD 0x3f, 0xf0000000, 28
+#define	MASK_WCI_QLIM_CONFIG_CAG_RSVD_X 0x0, 0xffe0000, 17
+#define	MASK_WCI_QLIM_CONFIG_CAG_TMIN_MAG 0x0, 0x1fff0, 4
+#define	MASK_WCI_QLIM_CONFIG_CAG_RSVD_W 0x0, 0x8, 3
+#define	MASK_WCI_QLIM_CONFIG_CAG_HWMARK_EXP 0x0, 0x7, 0
+#define	MASK_WCI_QLIM_CONFIG_CIQ_FREEZE 0x80000000, 0x0, 63
+#define	MASK_WCI_QLIM_CONFIG_CIQ_DISABLE 0x40000000, 0x0, 62
+#define	MASK_WCI_QLIM_CONFIG_CIQ_RSVD_Z 0x30000000, 0x0, 60
+#define	MASK_WCI_QLIM_CONFIG_CIQ_DISCARD_CNT_TIMER_EN 0x8000000, 0x0, 59
+#define	MASK_WCI_QLIM_CONFIG_CIQ_DISCARD_CNT_TIMER_MAG 0x7000000, 0x0, 56
+#define	MASK_WCI_QLIM_CONFIG_CIQ_DISCARD_CNT_TIMER_VAL 0xe00000, 0x0, 53
+#define	MASK_WCI_QLIM_CONFIG_CIQ_MAX_DISCARD 0x1fff00, 0x0, 40
+#define	MASK_WCI_QLIM_CONFIG_CIQ_RSVD_Y 0xc0, 0x0, 38
+#define	MASK_WCI_QLIM_CONFIG_CIQ_NUM2DISCARD 0x3f, 0xf0000000, 28
+#define	MASK_WCI_QLIM_CONFIG_CIQ_RSVD_X 0x0, 0xf000000, 24
+#define	MASK_WCI_QLIM_CONFIG_CIQ_DECAY 0x0, 0xf00000, 20
+#define	MASK_WCI_QLIM_CONFIG_CIQ_RSVD_W 0x0, 0xe0000, 17
+#define	MASK_WCI_QLIM_CONFIG_CIQ_TMIN_MAG 0x0, 0x1fff0, 4
+#define	MASK_WCI_QLIM_CONFIG_CIQ_RSVD_V 0x0, 0x8, 3
+#define	MASK_WCI_QLIM_CONFIG_CIQ_HWMARK_EXP 0x0, 0x7, 0
+#define	MASK_WCI_QLIM_CONFIG_NIQ_FREEZE 0x80000000, 0x0, 63
+#define	MASK_WCI_QLIM_CONFIG_NIQ_DISABLE 0x40000000, 0x0, 62
+#define	MASK_WCI_QLIM_CONFIG_NIQ_RSVD_Z 0x30000000, 0x0, 60
+#define	MASK_WCI_QLIM_CONFIG_NIQ_DISCARD_CNT_TIMER_EN 0x8000000, 0x0, 59
+#define	MASK_WCI_QLIM_CONFIG_NIQ_DISCARD_CNT_TIMER_MAG 0x7000000, 0x0, 56
+#define	MASK_WCI_QLIM_CONFIG_NIQ_DISCARD_CNT_TIMER_VAL 0xe00000, 0x0, 53
+#define	MASK_WCI_QLIM_CONFIG_NIQ_MAX_DISCARD 0x1fff00, 0x0, 40
+#define	MASK_WCI_QLIM_CONFIG_NIQ_RSVD_Y 0xc0, 0x0, 38
+#define	MASK_WCI_QLIM_CONFIG_NIQ_NUM2DISCARD 0x3f, 0xf0000000, 28
+#define	MASK_WCI_QLIM_CONFIG_NIQ_RSVD_X 0x0, 0xf000000, 24
+#define	MASK_WCI_QLIM_CONFIG_NIQ_DECAY 0x0, 0xf00000, 20
+#define	MASK_WCI_QLIM_CONFIG_NIQ_RSVD_W 0x0, 0xe0000, 17
+#define	MASK_WCI_QLIM_CONFIG_NIQ_TMIN_MAG 0x0, 0x1fff0, 4
+#define	MASK_WCI_QLIM_CONFIG_NIQ_RSVD_V 0x0, 0x8, 3
+#define	MASK_WCI_QLIM_CONFIG_NIQ_HWMARK_EXP 0x0, 0x7, 0
+#define	MASK_WCI_QLIM_CONFIG_PIQ_FREEZE 0x80000000, 0x0, 63
+#define	MASK_WCI_QLIM_CONFIG_PIQ_DISABLE 0x40000000, 0x0, 62
+#define	MASK_WCI_QLIM_CONFIG_PIQ_RSVD_Z 0x30000000, 0x0, 60
+#define	MASK_WCI_QLIM_CONFIG_PIQ_DISCARD_CNT_TIMER_EN 0x8000000, 0x0, 59
+#define	MASK_WCI_QLIM_CONFIG_PIQ_DISCARD_CNT_TIMER_MAG 0x7000000, 0x0, 56
+#define	MASK_WCI_QLIM_CONFIG_PIQ_DISCARD_CNT_TIMER_VAL 0xe00000, 0x0, 53
+#define	MASK_WCI_QLIM_CONFIG_PIQ_MAX_DISCARD 0x1fff00, 0x0, 40
+#define	MASK_WCI_QLIM_CONFIG_PIQ_RSVD_Y 0xc0, 0x0, 38
+#define	MASK_WCI_QLIM_CONFIG_PIQ_NUM2DISCARD 0x3f, 0xf0000000, 28
+#define	MASK_WCI_QLIM_CONFIG_PIQ_RSVD_X 0x0, 0xf000000, 24
+#define	MASK_WCI_QLIM_CONFIG_PIQ_DECAY 0x0, 0xf00000, 20
+#define	MASK_WCI_QLIM_CONFIG_PIQ_RSVD_W 0x0, 0xe0000, 17
+#define	MASK_WCI_QLIM_CONFIG_PIQ_TMIN_MAG 0x0, 0x1fff0, 4
+#define	MASK_WCI_QLIM_CONFIG_PIQ_RSVD_V 0x0, 0x8, 3
+#define	MASK_WCI_QLIM_CONFIG_PIQ_HWMARK_EXP 0x0, 0x7, 0
+#define	MASK_WCI_QLIM_NIQ_TIMER_RSVD_Z 0xffffffff, 0xe0000000, 29
+#define	MASK_WCI_QLIM_NIQ_TIMER_VALUE 0x0, 0x1fffffff, 0
+#define	MASK_WCI_QLIM_PIQ_TIMER_RSVD_Z 0xffffffff, 0xe0000000, 29
+#define	MASK_WCI_QLIM_PIQ_TIMER_VALUE 0x0, 0x1fffffff, 0
+#define	MASK_WCI_QLIM_SORT_CIQ_RSVD_Z 0xffffffff, 0x0, 32
+#define	MASK_WCI_QLIM_SORT_CIQ_DEV_ID_VEC 0x0, 0xffffffff, 0
+#define	MASK_WCI_QLIM_SORT_NIQ_RSVD_Z 0xffffffff, 0x0, 32
+#define	MASK_WCI_QLIM_SORT_NIQ_DEV_ID_VEC 0x0, 0xffffffff, 0
+#define	MASK_WCI_QLIM_SORT_PIQ_RSVD_Z 0xffffffff, 0x0, 32
+#define	MASK_WCI_QLIM_SORT_PIQ_DEV_ID_VEC 0x0, 0xffffffff, 0
+#define	MASK_WCI_RA_BUSY_REQUEST_SYNCH 0xffffffff, 0x0, 32
+#define	MASK_WCI_RA_BUSY_VECTOR 0x0, 0xffffffff, 0
+#define	MASK_WCI_RA_ECC_ADDRESS_DATA 0x80000000, 0x0, 63
+#define	MASK_WCI_RA_ECC_ADDRESS_UE 0x40000000, 0x0, 62
+#define	MASK_WCI_RA_ECC_ADDRESS_ATRANSID 0x3fe00000, 0x0, 53
+#define	MASK_WCI_RA_ECC_ADDRESS_TRANSACTION_TYPE 0x1f8000, 0x0, 47
+#define	MASK_WCI_RA_ECC_ADDRESS_RSVD_Z 0x7800, 0x0, 43
+#define	MASK_WCI_RA_ECC_ADDRESS_ADDR 0x7ff, 0xfffffff0, 4
+#define	MASK_WCI_RA_ECC_ADDRESS_RSVD_Y 0x0, 0xf, 0
+#define	MASK_WCI_RA_ERROR_TRANSACTION_0_ESR_REG 0x80000000, 0x0, 63
+#define	MASK_WCI_RA_ERROR_TRANSACTION_0_ESR_INDEX 0x78000000, 0x0, 59
+#define	MASK_WCI_RA_ERROR_TRANSACTION_0_RSVD_Z 0x7000000, 0x0, 56
+#define	MASK_WCI_RA_ERROR_TRANSACTION_0_CESR_INDEX 0xff0000, 0x0, 48
+#define	MASK_WCI_RA_ERROR_TRANSACTION_0_ATRANSID 0xff80, 0x0, 39
+#define	MASK_WCI_RA_ERROR_TRANSACTION_0_ADDR 0x7f, 0xffffffff, 0
+#define	MASK_WCI_RA_ERROR_TRANSACTION_1_FSM_STATE 0xfe000000, 0x0, 57
+#define	MASK_WCI_RA_ERROR_TRANSACTION_1_RSVD_Z 0x1ffffff, 0x0, 32
+#define	MASK_WCI_RA_ERROR_TRANSACTION_1_RTID 0x0, 0xf0000000, 28
+#define	MASK_WCI_RA_ERROR_TRANSACTION_1_RSVD_Y 0x0, 0x8000000, 27
+#define	MASK_WCI_RA_ERROR_TRANSACTION_1_DH_ERRORS 0x0, 0x7f00000, 20
+#define	MASK_WCI_RA_ERROR_TRANSACTION_1_ERROR_CODE 0x0, 0xf0000, 16
+#define	MASK_WCI_RA_ERROR_TRANSACTION_1_RCV_CNTR 0x0, 0xc000, 14
+#define	MASK_WCI_RA_ERROR_TRANSACTION_1_SND_CNTR 0x0, 0x3000, 12
+#define	MASK_WCI_RA_ERROR_TRANSACTION_1_TMOT_ERR 0x0, 0x800, 11
+#define	MASK_WCI_RA_ERROR_TRANSACTION_1_RH_ERR 0x0, 0x400, 10
+#define	MASK_WCI_RA_ERROR_TRANSACTION_1_TRANSACTION_TYPE 0x0, 0x3f0, 4
+#define	MASK_WCI_RA_ERROR_TRANSACTION_1_RSVD_X 0x0, 0xf, 0
+#define	MASK_WCI_RA_ESR_0_RSVD_Z 0xffffffff, 0x80000000, 31
+#define	MASK_WCI_RA_ESR_0_ACC_SSM_TIMEOUT 0x0, 0x40000000, 30
+#define	MASK_WCI_RA_ESR_0_ACC_WRONG_REPLY 0x0, 0x20000000, 29
+#define	MASK_WCI_RA_ESR_0_ACC_ILLEGAL_SENDER 0x0, 0x10000000, 28
+#define	MASK_WCI_RA_ESR_0_ACC_NOT_EXPECTED_REPLY 0x0, 0x8000000, 27
+#define	MASK_WCI_RA_ESR_0_ACC_QLIMIT_TIMEOUT 0x0, 0x4000000, 26
+#define	MASK_WCI_RA_ESR_0_ACC_UNEXPECTED_SNID 0x0, 0x2000000, 25
+#define	MASK_WCI_RA_ESR_0_ACC_WRONG_SAFARI_COMMAND 0x0, 0x1000000, 24
+#define	MASK_WCI_RA_ESR_0_ACC_NON_BLOCK_TRANS 0x0, 0x800000, 23
+#define	MASK_WCI_RA_ESR_0_ACC_CESR_ERROR_WRONG 0x0, 0x400000, 22
+#define	MASK_WCI_RA_ESR_0_ACC_CLUSTER_LOCAL_TIMEOUT 0x0, 0x200000, 21
+#define	MASK_WCI_RA_ESR_0_ACC_CLUSTER_REMOTE_TIMEOUT 0x0, 0x100000, 20
+#define	MASK_WCI_RA_ESR_0_ACC_MTAG_MISMATCH_BETWEEN_HCLS 0x0, 0x80000, 19
+#define	MASK_WCI_RA_ESR_0_ACC_MTAG_MISMATCH_WITHIN_HCL 0x0, 0x40000, 18
+#define	MASK_WCI_RA_ESR_0_ACC_DSTAT_INCONSISTENT 0x0, 0x20000, 17
+#define	MASK_WCI_RA_ESR_0_ACC_MTAG_NOT_GM 0x0, 0x10000, 16
+#define	MASK_WCI_RA_ESR_0_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_RA_ESR_0_SSM_TIMEOUT 0x0, 0x4000, 14
+#define	MASK_WCI_RA_ESR_0_WRONG_REPLY 0x0, 0x2000, 13
+#define	MASK_WCI_RA_ESR_0_ILLEGAL_SENDER 0x0, 0x1000, 12
+#define	MASK_WCI_RA_ESR_0_NOT_EXPECTED_REPLY 0x0, 0x800, 11
+#define	MASK_WCI_RA_ESR_0_QLIMIT_TIMEOUT 0x0, 0x400, 10
+#define	MASK_WCI_RA_ESR_0_UNEXPECTED_SNID 0x0, 0x200, 9
+#define	MASK_WCI_RA_ESR_0_WRONG_SAFARI_COMMAND 0x0, 0x100, 8
+#define	MASK_WCI_RA_ESR_0_NON_BLOCK_TRANS 0x0, 0x80, 7
+#define	MASK_WCI_RA_ESR_0_CESR_ERROR_WRONG 0x0, 0x40, 6
+#define	MASK_WCI_RA_ESR_0_CLUSTER_LOCAL_TIMEOUT 0x0, 0x20, 5
+#define	MASK_WCI_RA_ESR_0_CLUSTER_REMOTE_TIMEOUT 0x0, 0x10, 4
+#define	MASK_WCI_RA_ESR_0_MTAG_MISMATCH_BETWEEN_HCLS 0x0, 0x8, 3
+#define	MASK_WCI_RA_ESR_0_MTAG_MISMATCH_WITHIN_HCL 0x0, 0x4, 2
+#define	MASK_WCI_RA_ESR_0_DSTAT_INCONSISTENT 0x0, 0x2, 1
+#define	MASK_WCI_RA_ESR_0_MTAG_NOT_GM 0x0, 0x1, 0
+#define	MASK_WCI_RA_ESR_1_RSVD_Z 0xffffffff, 0x80000000, 31
+#define	MASK_WCI_RA_ESR_1_ACC_WRITE_LOCKOUT 0x0, 0x40000000, 30
+#define	MASK_WCI_RA_ESR_1_ACC_UNEXPECTED_MTAG 0x0, 0x20000000, 29
+#define	MASK_WCI_RA_ESR_1_ACC_ADDRESS_NOT_MAPPED 0x0, 0x10000000, 28
+#define	MASK_WCI_RA_ESR_1_ACC_ILLEGAL_HOME_NODE 0x0, 0x8000000, 27
+#define	MASK_WCI_RA_ESR_1_ACC_LPA2GA_ECC_ERROR 0x0, 0x4000000, 26
+#define	MASK_WCI_RA_ESR_1_ACC_LPA2GA_VIOLATION 0x0, 0x2000000, 25
+#define	MASK_WCI_RA_ESR_1_ACC_UNEXPECTED_SEND_ACK 0x0, 0x1000000, 24
+#define	MASK_WCI_RA_ESR_1_ACC_UNEXPECTED_RECEIVE_ACK 0x0, 0x800000, 23
+#define	MASK_WCI_RA_ESR_1_ACC_INVALID_REPLY_PATTERN 0x0, 0x400000, 22
+#define	MASK_WCI_RA_ESR_1_ACC_HW_PROTOCOL_ERROR 0x0, 0x200000, 21
+#define	MASK_WCI_RA_ESR_1_ACC_HW_FIFO_OVFL_UNFL 0x0, 0x100000, 20
+#define	MASK_WCI_RA_ESR_1_ACC_CORRECTABLE_MTAG_ERROR 0x0, 0x80000, 19
+#define	MASK_WCI_RA_ESR_1_ACC_CORRECTABLE_DATA_ERROR 0x0, 0x40000, 18
+#define	MASK_WCI_RA_ESR_1_ACC_UNCORRECTABLE_MTAG_ERROR 0x0, 0x20000, 17
+#define	MASK_WCI_RA_ESR_1_ACC_UNCORRECTABLE_DATA_ERROR 0x0, 0x10000, 16
+#define	MASK_WCI_RA_ESR_1_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_RA_ESR_1_WRITE_LOCKOUT 0x0, 0x4000, 14
+#define	MASK_WCI_RA_ESR_1_UNEXPECTED_MTAG 0x0, 0x2000, 13
+#define	MASK_WCI_RA_ESR_1_ADDRESS_NOT_MAPPED 0x0, 0x1000, 12
+#define	MASK_WCI_RA_ESR_1_ILLEGAL_HOME_NODE 0x0, 0x800, 11
+#define	MASK_WCI_RA_ESR_1_LPA2GA_ECC_ERROR 0x0, 0x400, 10
+#define	MASK_WCI_RA_ESR_1_LPA2GA_VIOLATION 0x0, 0x200, 9
+#define	MASK_WCI_RA_ESR_1_UNEXPECTED_SEND_ACK 0x0, 0x100, 8
+#define	MASK_WCI_RA_ESR_1_UNEXPECTED_RECEIVE_ACK 0x0, 0x80, 7
+#define	MASK_WCI_RA_ESR_1_INVALID_REPLY_PATTERN 0x0, 0x40, 6
+#define	MASK_WCI_RA_ESR_1_HW_PROTOCOL_ERROR 0x0, 0x20, 5
+#define	MASK_WCI_RA_ESR_1_HW_FIFO_OVFL_UNFL 0x0, 0x10, 4
+#define	MASK_WCI_RA_ESR_1_CORRECTABLE_MTAG_ERROR 0x0, 0x8, 3
+#define	MASK_WCI_RA_ESR_1_CORRECTABLE_DATA_ERROR 0x0, 0x4, 2
+#define	MASK_WCI_RA_ESR_1_UNCORRECTABLE_MTAG_ERROR 0x0, 0x2, 1
+#define	MASK_WCI_RA_ESR_1_UNCORRECTABLE_DATA_ERROR 0x0, 0x1, 0
+#define	MASK_WCI_RA_ESR_MASK_RSVD_Z 0xffffffff, 0x80000000, 31
+#define	MASK_WCI_RA_ESR_MASK_WRITE_LOCKOUT 0x0, 0x40000000, 30
+#define	MASK_WCI_RA_ESR_MASK_UNEXPECTED_MTAG 0x0, 0x20000000, 29
+#define	MASK_WCI_RA_ESR_MASK_ADDRESS_NOT_MAPPED 0x0, 0x10000000, 28
+#define	MASK_WCI_RA_ESR_MASK_ILLEGAL_HOME_NODE 0x0, 0x8000000, 27
+#define	MASK_WCI_RA_ESR_MASK_LPA2GA_ECC_ERROR 0x0, 0x4000000, 26
+#define	MASK_WCI_RA_ESR_MASK_LPA2GA_VIOLATION 0x0, 0x2000000, 25
+#define	MASK_WCI_RA_ESR_MASK_UNEXPECTED_SEND_ACK 0x0, 0x1000000, 24
+#define	MASK_WCI_RA_ESR_MASK_UNEXPECTED_RECEIVE_ACK 0x0, 0x800000, 23
+#define	MASK_WCI_RA_ESR_MASK_INVALID_REPLY_PATTERN 0x0, 0x400000, 22
+#define	MASK_WCI_RA_ESR_MASK_HW_PROTOCOL_ERROR 0x0, 0x200000, 21
+#define	MASK_WCI_RA_ESR_MASK_HW_FIFO_OVFL_UNFL 0x0, 0x100000, 20
+#define	MASK_WCI_RA_ESR_MASK_CORRECTABLE_MTAG_ERROR 0x0, 0x80000, 19
+#define	MASK_WCI_RA_ESR_MASK_CORRECTABLE_DATA_ERROR 0x0, 0x40000, 18
+#define	MASK_WCI_RA_ESR_MASK_UNCORRECTABLE_MTAG_ERROR 0x0, 0x20000, 17
+#define	MASK_WCI_RA_ESR_MASK_UNCORRECTABLE_DATA_ERROR 0x0, 0x10000, 16
+#define	MASK_WCI_RA_ESR_MASK_RSVD_Y 0x0, 0x8000, 15
+#define	MASK_WCI_RA_ESR_MASK_SSM_TIMEOUT 0x0, 0x4000, 14
+#define	MASK_WCI_RA_ESR_MASK_WRONG_REPLY 0x0, 0x2000, 13
+#define	MASK_WCI_RA_ESR_MASK_ILLEGAL_SENDER 0x0, 0x1000, 12
+#define	MASK_WCI_RA_ESR_MASK_NOT_EXPECTED_REPLY 0x0, 0x800, 11
+#define	MASK_WCI_RA_ESR_MASK_QLIMIT_TIMEOUT 0x0, 0x400, 10
+#define	MASK_WCI_RA_ESR_MASK_UNEXPECTED_SNID 0x0, 0x200, 9
+#define	MASK_WCI_RA_ESR_MASK_WRONG_SAFARI_COMMAND 0x0, 0x100, 8
+#define	MASK_WCI_RA_ESR_MASK_NON_BLOCK_TRANS 0x0, 0x80, 7
+#define	MASK_WCI_RA_ESR_MASK_CESR_ERROR_WRONG 0x0, 0x40, 6
+#define	MASK_WCI_RA_ESR_MASK_CLUSTER_LOCAL_TIMEOUT 0x0, 0x20, 5
+#define	MASK_WCI_RA_ESR_MASK_CLUSTER_REMOTE_TIMEOUT 0x0, 0x10, 4
+#define	MASK_WCI_RA_ESR_MASK_MTAG_MISMATCH_BETWEEN_HCLS 0x0, 0x8, 3
+#define	MASK_WCI_RA_ESR_MASK_MTAG_MISMATCH_WITHIN_HCL 0x0, 0x4, 2
+#define	MASK_WCI_RA_ESR_MASK_DSTAT_INCONSISTENT 0x0, 0x2, 1
+#define	MASK_WCI_RA_ESR_MASK_MTAG_NOT_GM 0x0, 0x1, 0
+#define	MASK_WCI_RA_FIRST_ERROR_AGENT_ESR_REG 0x80000000, 0x0, 63
+#define	MASK_WCI_RA_FIRST_ERROR_AGENT_ESR_INDEX 0x78000000, 0x0, 59
+#define	MASK_WCI_RA_FIRST_ERROR_AGENT_RSVD_Z 0x7ffffff, 0xffffffe0, 5
+#define	MASK_WCI_RA_FIRST_ERROR_AGENT_INSTANCE 0x0, 0x1f, 0
+#define	MASK_WCI_RA_FIRST_PACKET_0_LO 0xffffffff, 0xffffffff, 0
+#define	MASK_WCI_RA_FIRST_PACKET_1_ESR_REG 0x80000000, 0x0, 63
+#define	MASK_WCI_RA_FIRST_PACKET_1_ESR_INDEX 0x78000000, 0x0, 59
+#define	MASK_WCI_RA_FIRST_PACKET_1_SFQ_INPUT 0x6000000, 0x0, 57
+#define	MASK_WCI_RA_FIRST_PACKET_1_TRANSACTION_TYPE 0x1f80000, 0x0, 51
+#define	MASK_WCI_RA_FIRST_PACKET_1_RSVD_Z 0x7ffff, 0x80000000, 31
+#define	MASK_WCI_RA_FIRST_PACKET_1_HI 0x0, 0x7fffffff, 0
+#define	MASK_WCI_RA_FREEZE_RSVD_Z 0xffffffff, 0x0, 32
+#define	MASK_WCI_RA_FREEZE_VECTOR 0x0, 0xffffffff, 0
+#define	MASK_WCI_RA_STATUS_2_ARRAY_TFLG_ECC 0x80000000, 0x0, 63
+#define	MASK_WCI_RA_STATUS_2_ARRAY_REPLIES_RCVD_VLD 0x40000000, 0x0, 62
+#define	MASK_WCI_RA_STATUS_2_ARRAY_STRIPE 0x20000000, 0x0, 61
+#define	MASK_WCI_RA_STATUS_2_ARRAY_RH_SM 0x18000000, 0x0, 59
+#define	MASK_WCI_RA_STATUS_2_ARRAY_RCVD_MTAG 0x7000000, 0x0, 56
+#define	MASK_WCI_RA_STATUS_2_ARRAY_CESR_INDEX 0xff0000, 0x0, 48
+#define	MASK_WCI_RA_STATUS_2_ARRAY_NTRANSID 0xff80, 0x0, 39
+#define	MASK_WCI_RA_STATUS_2_ARRAY_DTARG 0x40, 0x0, 38
+#define	MASK_WCI_RA_STATUS_2_ARRAY_SAW_S_ACK 0x20, 0x0, 37
+#define	MASK_WCI_RA_STATUS_2_ARRAY_SAW_H_D 0x10, 0x0, 36
+#define	MASK_WCI_RA_STATUS_2_ARRAY_SAW_S_D 0x8, 0x0, 35
+#define	MASK_WCI_RA_STATUS_2_ARRAY_SAW_H_PULL 0x4, 0x0, 34
+#define	MASK_WCI_RA_STATUS_2_ARRAY_SAW_H_PULL_M 0x2, 0x0, 33
+#define	MASK_WCI_RA_STATUS_2_ARRAY_SAW_H_PULL_I 0x1, 0x0, 32
+#define	MASK_WCI_RA_STATUS_2_ARRAY_REPLIES_RCVD 0x0, 0xffff0000, 16
+#define	MASK_WCI_RA_STATUS_2_ARRAY_RCV_CNTR 0x0, 0xc000, 14
+#define	MASK_WCI_RA_STATUS_2_ARRAY_SND_CNTR 0x0, 0x3000, 12
+#define	MASK_WCI_RA_STATUS_2_ARRAY_SAW_H_NACK 0x0, 0x800, 11
+#define	MASK_WCI_RA_STATUS_2_ARRAY_SAW_H_ERR 0x0, 0x400, 10
+#define	MASK_WCI_RA_STATUS_2_ARRAY_TRANSACTION_TYPE 0x0, 0x3f0, 4
+#define	MASK_WCI_RA_STATUS_2_ARRAY_HNID 0x0, 0xf, 0
+#define	MASK_WCI_RA_STATUS_ARRAY_FSM_STATE 0xfe000000, 0x0, 57
+#define	MASK_WCI_RA_STATUS_ARRAY_DTARGID 0x1ff0000, 0x0, 48
+#define	MASK_WCI_RA_STATUS_ARRAY_ATRANSID 0xff80, 0x0, 39
+#define	MASK_WCI_RA_STATUS_ARRAY_ADDR 0x7f, 0xffffffff, 0
+#define	MASK_WCI_RA_TIMEOUT_CONFIG_RSVD_Z 0xfffffc00, 0x0, 42
+#define	MASK_WCI_RA_TIMEOUT_CONFIG_CLUS_DISABLE 0x200, 0x0, 41
+#define	MASK_WCI_RA_TIMEOUT_CONFIG_CLUS_FREEZE 0x100, 0x0, 40
+#define	MASK_WCI_RA_TIMEOUT_CONFIG_RSVD_Y 0xc0, 0x0, 38
+#define	MASK_WCI_RA_TIMEOUT_CONFIG_CLUS_APHASE_MAG 0x30, 0x0, 36
+#define	MASK_WCI_RA_TIMEOUT_CONFIG_RSVD_X 0xc, 0x0, 34
+#define	MASK_WCI_RA_TIMEOUT_CONFIG_CLUS_APHASE_VAL 0x3, 0xfc000000, 26
+#define	MASK_WCI_RA_TIMEOUT_CONFIG_CLUS_DPHASE_MAG 0x0, 0x3000000, 24
+#define	MASK_WCI_RA_TIMEOUT_CONFIG_CLUS_DPHASE_VAL 0x0, 0xff0000, 16
+#define	MASK_WCI_RA_TIMEOUT_CONFIG_RSVD_W 0x0, 0xc000, 14
+#define	MASK_WCI_RA_TIMEOUT_CONFIG_SSM_DISABLE 0x0, 0x2000, 13
+#define	MASK_WCI_RA_TIMEOUT_CONFIG_SSM_FREEZE 0x0, 0x1000, 12
+#define	MASK_WCI_RA_TIMEOUT_CONFIG_RSVD_V 0x0, 0xc00, 10
+#define	MASK_WCI_RA_TIMEOUT_CONFIG_SSM_MAG 0x0, 0x300, 8
+#define	MASK_WCI_RA_TIMEOUT_CONFIG_SSM_VAL 0x0, 0xff, 0
+#define	MASK_WCI_RA_WRITE_LOCKOUT_STATUS_RSVD_Z 0xffffffff, 0xfffffc00, 10
+#define	MASK_WCI_RA_WRITE_LOCKOUT_STATUS_LINK_STRIPE 0x0, 0x300, 8
+#define	MASK_WCI_RA_WRITE_LOCKOUT_STATUS_NC_SLICE 0x0, 0xff, 0
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_RAG_ROUTE_MAP0_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_RAG_ROUTE_MAP0_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_RAG_ROUTE_MAP1_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_RAG_ROUTE_MAP1_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_RESET_CONFIG_RSVD_Z 0xffffffff, 0xfffffffe, 1
+#define	MASK_WCI_RESET_CONFIG_AGENT_RESET_E 0x0, 0x1, 0
+#define	MASK_WCI_RESET_STATUS_RSVD_Z 0xffffffff, 0xfffffff8, 3
+#define	MASK_WCI_RESET_STATUS_POR 0x0, 0x4, 2
+#define	MASK_WCI_RESET_STATUS_NODE_RESET 0x0, 0x2, 1
+#define	MASK_WCI_RESET_STATUS_AGENT_RESET 0x0, 0x1, 0
+#define	MASK_WCI_SA_BUSY_RSVD_Z 0xffffffff, 0xffffff00, 8
+#define	MASK_WCI_SA_BUSY_VECTOR 0x0, 0xff, 0
+#define	MASK_WCI_SA_ECC_ADDRESS_DATA 0x80000000, 0x0, 63
+#define	MASK_WCI_SA_ECC_ADDRESS_UE 0x40000000, 0x0, 62
+#define	MASK_WCI_SA_ECC_ADDRESS_RSVD_Z 0x3ffff800, 0x0, 43
+#define	MASK_WCI_SA_ECC_ADDRESS_ADDR 0x7ff, 0xffffffe0, 5
+#define	MASK_WCI_SA_ECC_ADDRESS_RSVD_Y 0x0, 0x1f, 0
+#define	MASK_WCI_SA_ESR_0_RSVD_Z 0xffffffff, 0x80000000, 31
+#define	MASK_WCI_SA_ESR_0_ACC_HW_ERR 0x0, 0x40000000, 30
+#define	MASK_WCI_SA_ESR_0_ACC_ADDRESS_NOT_OWNED 0x0, 0x20000000, 29
+#define	MASK_WCI_SA_ESR_0_ACC_ADDRESS_NOT_MAPPED 0x0, 0x10000000, 28
+#define	MASK_WCI_SA_ESR_0_ACC_GA2LPA_ECC_ERROR 0x0, 0x8000000, 27
+#define	MASK_WCI_SA_ESR_0_ACC_RIP_MULTI_HIT 0x0, 0x4000000, 26
+#define	MASK_WCI_SA_ESR_0_ACC_ILLEGAL_SENDER 0x0, 0x2000000, 25
+#define	MASK_WCI_SA_ESR_0_ACC_WRONG_DEMAND 0x0, 0x1000000, 24
+#define	MASK_WCI_SA_ESR_0_ACC_UNCORRECTABLE_MTAG_ERROR 0x0, 0x800000, 23
+#define	MASK_WCI_SA_ESR_0_ACC_UNCORRECTABLE_DATA_ERROR 0x0, 0x400000, 22
+#define	MASK_WCI_SA_ESR_0_ACC_CORRECTABLE_MTAG_ERROR 0x0, 0x200000, 21
+#define	MASK_WCI_SA_ESR_0_ACC_CORRECTABLE_DATA_ERROR 0x0, 0x100000, 20
+#define	MASK_WCI_SA_ESR_0_ACC_MTAG_MISMATCH_WITHIN_HCL 0x0, 0x80000, 19
+#define	MASK_WCI_SA_ESR_0_ACC_MTAG_MISMATCH_BETWEEN_HCLS 0x0, 0x40000, 18
+#define	MASK_WCI_SA_ESR_0_ACC_UNEXPECTED_MTAG 0x0, 0x20000, 17
+#define	MASK_WCI_SA_ESR_0_ACC_TIMEOUT 0x0, 0x10000, 16
+#define	MASK_WCI_SA_ESR_0_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_SA_ESR_0_HW_ERR 0x0, 0x4000, 14
+#define	MASK_WCI_SA_ESR_0_ADDRESS_NOT_OWNED 0x0, 0x2000, 13
+#define	MASK_WCI_SA_ESR_0_ADDRESS_NOT_MAPPED 0x0, 0x1000, 12
+#define	MASK_WCI_SA_ESR_0_GA2LPA_ECC_ERROR 0x0, 0x800, 11
+#define	MASK_WCI_SA_ESR_0_RIP_MULTI_HIT 0x0, 0x400, 10
+#define	MASK_WCI_SA_ESR_0_ILLEGAL_SENDER 0x0, 0x200, 9
+#define	MASK_WCI_SA_ESR_0_WRONG_DEMAND 0x0, 0x100, 8
+#define	MASK_WCI_SA_ESR_0_UNCORRECTABLE_MTAG_ERROR 0x0, 0x80, 7
+#define	MASK_WCI_SA_ESR_0_UNCORRECTABLE_DATA_ERROR 0x0, 0x40, 6
+#define	MASK_WCI_SA_ESR_0_CORRECTABLE_MTAG_ERROR 0x0, 0x20, 5
+#define	MASK_WCI_SA_ESR_0_CORRECTABLE_DATA_ERROR 0x0, 0x10, 4
+#define	MASK_WCI_SA_ESR_0_MTAG_MISMATCH_WITHIN_HCL 0x0, 0x8, 3
+#define	MASK_WCI_SA_ESR_0_MTAG_MISMATCH_BETWEEN_HCLS 0x0, 0x4, 2
+#define	MASK_WCI_SA_ESR_0_UNEXPECTED_MTAG 0x0, 0x2, 1
+#define	MASK_WCI_SA_ESR_0_TIMEOUT 0x0, 0x1, 0
+#define	MASK_WCI_SA_ESR_MASK_RSVD_Z 0xffffffff, 0xffff8000, 15
+#define	MASK_WCI_SA_ESR_MASK_HW_ERR 0x0, 0x4000, 14
+#define	MASK_WCI_SA_ESR_MASK_ADDRESS_NOT_OWNED 0x0, 0x2000, 13
+#define	MASK_WCI_SA_ESR_MASK_ADDRESS_NOT_MAPPED 0x0, 0x1000, 12
+#define	MASK_WCI_SA_ESR_MASK_GA2LPA_ECC_ERROR 0x0, 0x800, 11
+#define	MASK_WCI_SA_ESR_MASK_RIP_MULTI_HIT 0x0, 0x400, 10
+#define	MASK_WCI_SA_ESR_MASK_ILLEGAL_SENDER 0x0, 0x200, 9
+#define	MASK_WCI_SA_ESR_MASK_WRONG_DEMAND 0x0, 0x100, 8
+#define	MASK_WCI_SA_ESR_MASK_UNCORRECTABLE_MTAG_ERROR 0x0, 0x80, 7
+#define	MASK_WCI_SA_ESR_MASK_UNCORRECTABLE_DATA_ERROR 0x0, 0x40, 6
+#define	MASK_WCI_SA_ESR_MASK_CORRECTABLE_MTAG_ERROR 0x0, 0x20, 5
+#define	MASK_WCI_SA_ESR_MASK_CORRECTABLE_DATA_ERROR 0x0, 0x10, 4
+#define	MASK_WCI_SA_ESR_MASK_MTAG_MISMATCH_WITHIN_HCL 0x0, 0x8, 3
+#define	MASK_WCI_SA_ESR_MASK_MTAG_MISMATCH_BETWEEN_HCLS 0x0, 0x4, 2
+#define	MASK_WCI_SA_ESR_MASK_UNEXPECTED_MTAG 0x0, 0x2, 1
+#define	MASK_WCI_SA_ESR_MASK_TIMEOUT 0x0, 0x1, 0
+#define	MASK_WCI_SA_FIRST_ERROR_AGENT_ESR_REG 0x80000000, 0x0, 63
+#define	MASK_WCI_SA_FIRST_ERROR_AGENT_ESR_INDEX 0x78000000, 0x0, 59
+#define	MASK_WCI_SA_FIRST_ERROR_AGENT_RSVD_Z 0x7ffffff, 0xfffffff8, 3
+#define	MASK_WCI_SA_FIRST_ERROR_AGENT_INSTANCE 0x0, 0x7, 0
+#define	MASK_WCI_SA_FIRST_PACKET_0_RSVD_Z 0xfe000000, 0x0, 57
+#define	MASK_WCI_SA_FIRST_PACKET_0_NTRANSID 0x1ff0000, 0x0, 48
+#define	MASK_WCI_SA_FIRST_PACKET_0_RSVD_Y 0xc000, 0x0, 46
+#define	MASK_WCI_SA_FIRST_PACKET_0_CMR 0x2000, 0x0, 45
+#define	MASK_WCI_SA_FIRST_PACKET_0_OTRANSID 0x1ff0, 0x0, 36
+#define	MASK_WCI_SA_FIRST_PACKET_0_RSVD_X 0xc, 0x0, 34
+#define	MASK_WCI_SA_FIRST_PACKET_0_RNID 0x3, 0xc0000000, 30
+#define	MASK_WCI_SA_FIRST_PACKET_0_R2E 0x0, 0x3c000000, 26
+#define	MASK_WCI_SA_FIRST_PACKET_0_EMISS 0x0, 0x2000000, 25
+#define	MASK_WCI_SA_FIRST_PACKET_0_RSVD_W 0x0, 0x1000000, 24
+#define	MASK_WCI_SA_FIRST_PACKET_0_HTID 0x0, 0xf00000, 20
+#define	MASK_WCI_SA_FIRST_PACKET_0_RTID 0x0, 0xf8000, 15
+#define	MASK_WCI_SA_FIRST_PACKET_0_SNID 0x0, 0x7800, 11
+#define	MASK_WCI_SA_FIRST_PACKET_0_MSGOP 0x0, 0x780, 7
+#define	MASK_WCI_SA_FIRST_PACKET_0_HTYP 0x0, 0x60, 5
+#define	MASK_WCI_SA_FIRST_PACKET_0_STRIPE 0x0, 0x10, 4
+#define	MASK_WCI_SA_FIRST_PACKET_0_DNID 0x0, 0xf, 0
+#define	MASK_WCI_SA_FIRST_PACKET_1_ESR_REG 0x80000000, 0x0, 63
+#define	MASK_WCI_SA_FIRST_PACKET_1_ESR_INDEX 0x78000000, 0x0, 59
+#define	MASK_WCI_SA_FIRST_PACKET_1_A_ENTRY 0x4000000, 0x0, 58
+#define	MASK_WCI_SA_FIRST_PACKET_1_S_ENTRY 0x2000000, 0x0, 57
+#define	MASK_WCI_SA_FIRST_PACKET_1_RSVD_Z 0x1fff800, 0x0, 43
+#define	MASK_WCI_SA_FIRST_PACKET_1_GA 0x7ff, 0xffffffe0, 5
+#define	MASK_WCI_SA_FIRST_PACKET_1_RSVD_Y 0x0, 0x1f, 0
+#define	MASK_WCI_SA_FREEZE_RSVD_Z 0xffffffff, 0xffffff00, 8
+#define	MASK_WCI_SA_FREEZE_VECTOR 0x0, 0xff, 0
+#define	MASK_WCI_SA_HW_ERR_STATE_RSVD_Z 0xffffffff, 0xffffff00, 8
+#define	MASK_WCI_SA_HW_ERR_STATE_SH_QUEUE_OVERFLOW 0x0, 0x80, 7
+#define	MASK_WCI_SA_HW_ERR_STATE_SH_WRONG_STID 0x0, 0x40, 6
+#define	MASK_WCI_SA_HW_ERR_STATE_SH_UNEXPECTED_SNOOP 0x0, 0x20, 5
+#define	MASK_WCI_SA_HW_ERR_STATE_OH_QUEUE_OVERFLOW 0x0, 0x10, 4
+#define	MASK_WCI_SA_HW_ERR_STATE_OH_WRONG_STID 0x0, 0x8, 3
+#define	MASK_WCI_SA_HW_ERR_STATE_OH_UNEXPECTED_ORDERED 0x0, 0x4, 2
+#define	MASK_WCI_SA_HW_ERR_STATE_UNEXPECTED_SEND_ACK 0x0, 0x2, 1
+#define	MASK_WCI_SA_HW_ERR_STATE_UNEXPECTED_RECEIVE_ACK 0x0, 0x1, 0
+#define	MASK_WCI_SA_STATUS_2_ARRAY_RSVD_Z 0xffffffff, 0xfffff800, 11
+#define	MASK_WCI_SA_STATUS_2_ARRAY_SEND_DONE 0x0, 0x400, 10
+#define	MASK_WCI_SA_STATUS_2_ARRAY_PH_DONE 0x0, 0x200, 9
+#define	MASK_WCI_SA_STATUS_2_ARRAY_GOT_2ND_SNOOP 0x0, 0x100, 8
+#define	MASK_WCI_SA_STATUS_2_ARRAY_GOT_1ST_SNOOP 0x0, 0x80, 7
+#define	MASK_WCI_SA_STATUS_2_ARRAY_GOT_2ND_ORD 0x0, 0x40, 6
+#define	MASK_WCI_SA_STATUS_2_ARRAY_GOT_1ST_ORD 0x0, 0x20, 5
+#define	MASK_WCI_SA_STATUS_2_ARRAY_SF_3_DONE 0x0, 0x10, 4
+#define	MASK_WCI_SA_STATUS_2_ARRAY_SF_2_DONE 0x0, 0x8, 3
+#define	MASK_WCI_SA_STATUS_2_ARRAY_DSH_DONE 0x0, 0x4, 2
+#define	MASK_WCI_SA_STATUS_2_ARRAY_DRH_DONE 0x0, 0x2, 1
+#define	MASK_WCI_SA_STATUS_2_ARRAY_REQ_DONE 0x0, 0x1, 0
+#define	MASK_WCI_SA_STATUS_3_ARRAY_RSVD_Z 0xffffffff, 0xffffe000, 13
+#define	MASK_WCI_SA_STATUS_3_ARRAY_NTRANSID 0x0, 0x1ff0, 4
+#define	MASK_WCI_SA_STATUS_3_ARRAY_SNID 0x0, 0xf, 0
+#define	MASK_WCI_SA_STATUS_4_ARRAY_RSVD_Z 0xfffffffe, 0x0, 33
+#define	MASK_WCI_SA_STATUS_4_ARRAY_OTRANSID 0x1, 0xff000000, 24
+#define	MASK_WCI_SA_STATUS_4_ARRAY_RNID 0x0, 0xf00000, 20
+#define	MASK_WCI_SA_STATUS_4_ARRAY_REPLIES_2_EXP 0x0, 0xf0000, 16
+#define	MASK_WCI_SA_STATUS_4_ARRAY_HTID 0x0, 0xf000, 12
+#define	MASK_WCI_SA_STATUS_4_ARRAY_RSVD_Y 0x0, 0xe00, 9
+#define	MASK_WCI_SA_STATUS_4_ARRAY_RTID 0x0, 0x1f0, 4
+#define	MASK_WCI_SA_STATUS_4_ARRAY_RSVD_X 0x0, 0xc, 2
+#define	MASK_WCI_SA_STATUS_4_ARRAY_EMISS 0x0, 0x2, 1
+#define	MASK_WCI_SA_STATUS_4_ARRAY_STRIPE 0x0, 0x1, 0
+#define	MASK_WCI_SA_STATUS_5_ARRAY_RSVD_Z 0xfffff800, 0x0, 43
+#define	MASK_WCI_SA_STATUS_5_ARRAY_ORIGINAL_GA 0x7ff, 0xffffe000, 13
+#define	MASK_WCI_SA_STATUS_5_ARRAY_RSVD_Y 0x0, 0x1ffe, 1
+#define	MASK_WCI_SA_STATUS_5_ARRAY_CMR 0x0, 0x1, 0
+#define	MASK_WCI_SA_STATUS_6_ARRAY_RSVD_Z 0xfffff800, 0x0, 43
+#define	MASK_WCI_SA_STATUS_6_ARRAY_SAFARI_ADDR_42 0x400, 0x0, 42
+#define	MASK_WCI_SA_STATUS_6_ARRAY_SAFARI_ADDR_41_38 0x3c0, 0x0, 38
+#define	MASK_WCI_SA_STATUS_6_ARRAY_SAFARI_ADDR_37 0x20, 0x0, 37
+#define	MASK_WCI_SA_STATUS_6_ARRAY_SAFARI_ADDR_36_5 0x1f, 0xffffffe0, 5
+#define	MASK_WCI_SA_STATUS_6_ARRAY_RSVD_Y 0x0, 0x1f, 0
+#define	MASK_WCI_SA_STATUS_ARRAY_RSVD_Z 0xffffffff, 0xffe00000, 21
+#define	MASK_WCI_SA_STATUS_ARRAY_RECEIVE_COUNT 0x0, 0x180000, 19
+#define	MASK_WCI_SA_STATUS_ARRAY_SEND_COUNT 0x0, 0x70000, 16
+#define	MASK_WCI_SA_STATUS_ARRAY_OWNED 0x0, 0x8000, 15
+#define	MASK_WCI_SA_STATUS_ARRAY_FIRST_MTAG 0x0, 0x7000, 12
+#define	MASK_WCI_SA_STATUS_ARRAY_ATRANSID_3_0 0x0, 0xf00, 8
+#define	MASK_WCI_SA_STATUS_ARRAY_RSVD_Y 0x0, 0xc0, 6
+#define	MASK_WCI_SA_STATUS_ARRAY_GA2LPA_STATUS 0x0, 0x30, 4
+#define	MASK_WCI_SA_STATUS_ARRAY_MSGOP 0x0, 0xf, 0
+#define	MASK_WCI_SA_TIMEOUT_CONFIG_RSVD_Z 0xffffffff, 0xffffc000, 14
+#define	MASK_WCI_SA_TIMEOUT_CONFIG_SSM_DISABLE 0x0, 0x2000, 13
+#define	MASK_WCI_SA_TIMEOUT_CONFIG_SSM_FREEZE 0x0, 0x1000, 12
+#define	MASK_WCI_SA_TIMEOUT_CONFIG_RSVD_Y 0x0, 0xc00, 10
+#define	MASK_WCI_SA_TIMEOUT_CONFIG_SSM_MAG 0x0, 0x300, 8
+#define	MASK_WCI_SA_TIMEOUT_CONFIG_SSM_VAL 0x0, 0xff, 0
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_SAG_ROUTE_MAP0_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_SAG_ROUTE_MAP0_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_SAG_ROUTE_MAP1_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_SAG_ROUTE_MAP1_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_SC_CLUSTER_DISABLE_RSVD_Z 0xffffffff, 0xfffffff0, 4
+#define	MASK_WCI_SC_CLUSTER_DISABLE_CA_CLUSTER_DISABLE 0x0, 0x8, 3
+#define	MASK_WCI_SC_CLUSTER_DISABLE_RA_PIQ_DISABLE 0x0, 0x4, 2
+#define	MASK_WCI_SC_CLUSTER_DISABLE_RA_NIQ_DISABLE 0x0, 0x2, 1
+#define	MASK_WCI_SC_CLUSTER_DISABLE_RA_CIQ_DISABLE 0x0, 0x1, 0
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_SEC_FO_ROUTE_MAP_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_SFI_ANALYZER_VALID 0x80000000, 0x0, 63
+#define	MASK_WCI_SFI_ANALYZER_IN_USE 0x40000000, 0x0, 62
+#define	MASK_WCI_SFI_ANALYZER_SHARED 0x20000000, 0x0, 61
+#define	MASK_WCI_SFI_ANALYZER_OWNED 0x10000000, 0x0, 60
+#define	MASK_WCI_SFI_ANALYZER_MAPPED 0x8000000, 0x0, 59
+#define	MASK_WCI_SFI_ANALYZER_OVERFLOW 0x7e00000, 0x0, 53
+#define	MASK_WCI_SFI_ANALYZER_ADDRESS 0x1fffff, 0xffffc000, 14
+#define	MASK_WCI_SFI_ANALYZER_MASK 0x0, 0x3c00, 10
+#define	MASK_WCI_SFI_ANALYZER_COMMAND 0x0, 0x200, 9
+#define	MASK_WCI_SFI_ANALYZER_ATRANSID 0x0, 0x1ff, 0
+#define	MASK_WCI_SFI_CTR0_MASK_RSVD_Z 0xfc000000, 0x0, 58
+#define	MASK_WCI_SFI_CTR0_MASK_MASK 0x3ff0000, 0x0, 48
+#define	MASK_WCI_SFI_CTR0_MASK_ATRANSID 0xff80, 0x0, 39
+#define	MASK_WCI_SFI_CTR0_MASK_ADDRESS 0x7f, 0xffffffff, 0
+#define	MASK_WCI_SFI_CTR0_MATCH_RSVD_Z 0xfc000000, 0x0, 58
+#define	MASK_WCI_SFI_CTR0_MATCH_MASK 0x3ff0000, 0x0, 48
+#define	MASK_WCI_SFI_CTR0_MATCH_ATRANSID 0xff80, 0x0, 39
+#define	MASK_WCI_SFI_CTR0_MATCH_ADDRESS 0x7f, 0xffffffff, 0
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_RSVD_Z 0xffffffff, 0xfff80000, 19
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_RTS 0x0, 0x40000, 18
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_RTO 0x0, 0x20000, 17
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_RS 0x0, 0x10000, 16
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_WS 0x0, 0x8000, 15
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_RTSR 0x0, 0x4000, 14
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_RTOR 0x0, 0x2000, 13
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_RSR 0x0, 0x1000, 12
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_WB 0x0, 0x800, 11
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_RTSM 0x0, 0x400, 10
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_INTERRUPT 0x0, 0x200, 9
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_R_RTS 0x0, 0x100, 8
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_R_RTO 0x0, 0x80, 7
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_R_RS 0x0, 0x40, 6
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_R_WS 0x0, 0x20, 5
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_R_WB 0x0, 0x10, 4
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_RBIO 0x0, 0x8, 3
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_RIO 0x0, 0x4, 2
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_WBIO 0x0, 0x2, 1
+#define	MASK_WCI_SFI_CTR0_MATCH_TRANSACTION_WIO 0x0, 0x1, 0
+#define	MASK_WCI_SFI_CTR1_MASK_RSVD_Z 0xfc000000, 0x0, 58
+#define	MASK_WCI_SFI_CTR1_MASK_MASK 0x3ff0000, 0x0, 48
+#define	MASK_WCI_SFI_CTR1_MASK_ATRANSID 0xff80, 0x0, 39
+#define	MASK_WCI_SFI_CTR1_MASK_ADDRESS 0x7f, 0xffffffff, 0
+#define	MASK_WCI_SFI_CTR1_MATCH_RSVD_Z 0xfc000000, 0x0, 58
+#define	MASK_WCI_SFI_CTR1_MATCH_MASK 0x3ff0000, 0x0, 48
+#define	MASK_WCI_SFI_CTR1_MATCH_ATRANSID 0xff80, 0x0, 39
+#define	MASK_WCI_SFI_CTR1_MATCH_ADDRESS 0x7f, 0xffffffff, 0
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_RSVD_Z 0xffffffff, 0xfff80000, 19
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_RTS 0x0, 0x40000, 18
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_RTO 0x0, 0x20000, 17
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_RS 0x0, 0x10000, 16
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_WS 0x0, 0x8000, 15
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_RTSR 0x0, 0x4000, 14
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_RTOR 0x0, 0x2000, 13
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_RSR 0x0, 0x1000, 12
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_WB 0x0, 0x800, 11
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_RTSM 0x0, 0x400, 10
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_INTERRUPT 0x0, 0x200, 9
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_R_RTS 0x0, 0x100, 8
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_R_RTO 0x0, 0x80, 7
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_R_RS 0x0, 0x40, 6
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_R_WS 0x0, 0x20, 5
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_R_WB 0x0, 0x10, 4
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_RBIO 0x0, 0x8, 3
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_RIO 0x0, 0x4, 2
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_WBIO 0x0, 0x2, 1
+#define	MASK_WCI_SFI_CTR1_MATCH_TRANSACTION_WIO 0x0, 0x1, 0
+#define	MASK_WCI_SFI_ESR_RSVD_Z 0xffffffff, 0xfc000000, 26
+#define	MASK_WCI_SFI_ESR_ACC_TARGID_TIMEOUT 0x0, 0x2000000, 25
+#define	MASK_WCI_SFI_ESR_ACC_NC2NID_MISCONFIG 0x0, 0x1000000, 24
+#define	MASK_WCI_SFI_ESR_ACC_ADDR_PTY 0x0, 0x800000, 23
+#define	MASK_WCI_SFI_ESR_ACC_INCOMING_PREREQ_CONFLICT 0x0, 0x400000, 22
+#define	MASK_WCI_SFI_ESR_ACC_MODCAM_CLR_SET_CONFLICT 0x0, 0x200000, 21
+#define	MASK_WCI_SFI_ESR_ACC_MODCAM_MULTI_HIT 0x0, 0x100000, 20
+#define	MASK_WCI_SFI_ESR_ACC_MODCAM_SET_SET 0x0, 0x80000, 19
+#define	MASK_WCI_SFI_ESR_ACC_UNEXPECTED_INCOMING 0x0, 0x40000, 18
+#define	MASK_WCI_SFI_ESR_ACC_UNEXPECTED_TARGARBGNT 0x0, 0x20000, 17
+#define	MASK_WCI_SFI_ESR_ACC_TRANSID_UNALLOC_RELEASED 0x0, 0x10000, 16
+#define	MASK_WCI_SFI_ESR_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_SFI_ESR_RSVD_Y 0x0, 0x7c00, 10
+#define	MASK_WCI_SFI_ESR_TARGID_TIMEOUT 0x0, 0x200, 9
+#define	MASK_WCI_SFI_ESR_NC2NID_MISCONFIG 0x0, 0x100, 8
+#define	MASK_WCI_SFI_ESR_ADDR_PTY 0x0, 0x80, 7
+#define	MASK_WCI_SFI_ESR_INCOMING_PREREQ_CONFLICT 0x0, 0x40, 6
+#define	MASK_WCI_SFI_ESR_MODCAM_CLR_SET_CONFLICT 0x0, 0x20, 5
+#define	MASK_WCI_SFI_ESR_MODCAM_MULTI_HIT 0x0, 0x10, 4
+#define	MASK_WCI_SFI_ESR_MODCAM_SET_SET 0x0, 0x8, 3
+#define	MASK_WCI_SFI_ESR_UNEXPECTED_INCOMING 0x0, 0x4, 2
+#define	MASK_WCI_SFI_ESR_UNEXPECTED_TARGARBGNT 0x0, 0x2, 1
+#define	MASK_WCI_SFI_ESR_TRANSID_UNALLOC_RELEASED 0x0, 0x1, 0
+#define	MASK_WCI_SFI_ESR_MASK_RSVD_Z 0xffffffff, 0xfffffc00, 10
+#define	MASK_WCI_SFI_ESR_MASK_TARGID_TIMEOUT 0x0, 0x200, 9
+#define	MASK_WCI_SFI_ESR_MASK_NC2NID_MISCONFIG 0x0, 0x100, 8
+#define	MASK_WCI_SFI_ESR_MASK_ADDR_PTY 0x0, 0x80, 7
+#define	MASK_WCI_SFI_ESR_MASK_INCOMING_PREREQ_CONFLICT 0x0, 0x40, 6
+#define	MASK_WCI_SFI_ESR_MASK_MODCAM_CLR_SET_CONFLICT 0x0, 0x20, 5
+#define	MASK_WCI_SFI_ESR_MASK_MODCAM_MULTI_HIT 0x0, 0x10, 4
+#define	MASK_WCI_SFI_ESR_MASK_MODCAM_SET_SET 0x0, 0x8, 3
+#define	MASK_WCI_SFI_ESR_MASK_UNEXPECTED_INCOMING 0x0, 0x4, 2
+#define	MASK_WCI_SFI_ESR_MASK_UNEXPECTED_TARGARBGNT 0x0, 0x2, 1
+#define	MASK_WCI_SFI_ESR_MASK_TRANSID_UNALLOC_RELEASED 0x0, 0x1, 0
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_SFI_ROUTE_MAP0_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_SFI_ROUTE_MAP0_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_Z 0xffff8000, 0x0, 47
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE15_TLINK 0x6000, 0x0, 45
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_Y 0x1000, 0x0, 44
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE14_TLINK 0xc00, 0x0, 42
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_X 0x200, 0x0, 41
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE13_TLINK 0x180, 0x0, 39
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_W 0x40, 0x0, 38
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE12_TLINK 0x30, 0x0, 36
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_V 0x8, 0x0, 35
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE11_TLINK 0x6, 0x0, 33
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_U 0x1, 0x0, 32
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE10_TLINK 0x0, 0xc0000000, 30
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_T 0x0, 0x20000000, 29
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE9_TLINK 0x0, 0x18000000, 27
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_S 0x0, 0x4000000, 26
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE8_TLINK 0x0, 0x3000000, 24
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_R 0x0, 0x800000, 23
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE7_TLINK 0x0, 0x600000, 21
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_Q 0x0, 0x100000, 20
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE6_TLINK 0x0, 0xc0000, 18
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_P 0x0, 0x20000, 17
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE5_TLINK 0x0, 0x18000, 15
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_O 0x0, 0x4000, 14
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE4_TLINK 0x0, 0x3000, 12
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_N 0x0, 0x800, 11
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE3_TLINK 0x0, 0x600, 9
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_M 0x0, 0x100, 8
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE2_TLINK 0x0, 0xc0, 6
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_L 0x0, 0x20, 5
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE1_TLINK 0x0, 0x18, 3
+#define	MASK_WCI_SFI_ROUTE_MAP1_RSVD_K 0x0, 0x4, 2
+#define	MASK_WCI_SFI_ROUTE_MAP1_NODE0_TLINK 0x0, 0x3, 0
+#define	MASK_WCI_SFI_STATE_RSVD_Z 0x80000000, 0x0, 63
+#define	MASK_WCI_SFI_STATE_ESR_INDEX 0x78000000, 0x0, 59
+#define	MASK_WCI_SFI_STATE_RSVD_Y 0x7fe0000, 0x0, 49
+#define	MASK_WCI_SFI_STATE_WCI_ISSUED 0x10000, 0x0, 48
+#define	MASK_WCI_SFI_STATE_AGENT_ID 0xfe00, 0x0, 41
+#define	MASK_WCI_SFI_STATE_MODCAM_INDEX 0x1e0, 0x0, 37
+#define	MASK_WCI_SFI_STATE_MODCAM_ADDR 0x1f, 0xffffffc0, 6
+#define	MASK_WCI_SFI_STATE_SF_CMD 0x0, 0x30, 4
+#define	MASK_WCI_SFI_STATE_SF_MASK_3_TO_0 0x0, 0xf, 0
+#define	MASK_WCI_SFI_STATE1_RSVD_Z 0x80000000, 0x0, 63
+#define	MASK_WCI_SFI_STATE1_ESR_INDEX 0x78000000, 0x0, 59
+#define	MASK_WCI_SFI_STATE1_RSVD_Y 0x7f80000, 0x0, 51
+#define	MASK_WCI_SFI_STATE1_UNALLOC_RELEASE_AGENTS 0x7c000, 0x0, 46
+#define	MASK_WCI_SFI_STATE1_UNALLOC_TARGIDS_RELEASED 0x3fff, 0x80000000, 31
+#define	MASK_WCI_SFI_STATE1_UNALLOC_ATRANSIDS_RELEASED 0x0, 0x7fff0000, 16
+#define	MASK_WCI_SFI_STATE1_NC2NID_INDEX 0x0, 0xff00, 8
+#define	MASK_WCI_SFI_STATE1_NC2NID_DATA 0x0, 0xff, 0
+#define	MASK_WCI_SFI_TRANSID_ALLOC_RSVD_Z 0xffffffff, 0x80000000, 31
+#define	MASK_WCI_SFI_TRANSID_ALLOC_TARGID_AVAILABLE 0x0, 0x7fff0000, 16
+#define	MASK_WCI_SFI_TRANSID_ALLOC_ATRANSID_AVAILABLE 0x0, 0xfffe, 1
+#define	MASK_WCI_SFI_TRANSID_ALLOC_RSVD_Y 0x0, 0x1, 0
+#define	MASK_WCI_SFQ_ESR_RSVD_Z 0xffffffff, 0xfffc0000, 18
+#define	MASK_WCI_SFQ_ESR_ACC_SFQ_PERR 0x0, 0x20000, 17
+#define	MASK_WCI_SFQ_ESR_ACC_SFQ_OVFL 0x0, 0x10000, 16
+#define	MASK_WCI_SFQ_ESR_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_SFQ_ESR_RSVD_Y 0x0, 0x7ffc, 2
+#define	MASK_WCI_SFQ_ESR_SFQ_PERR 0x0, 0x2, 1
+#define	MASK_WCI_SFQ_ESR_SFQ_OVFL 0x0, 0x1, 0
+#define	MASK_WCI_SFQ_ESR_MASK_RSVD_Z 0xffffffff, 0xfffffffc, 2
+#define	MASK_WCI_SFQ_ESR_MASK_SFQ_PERR 0x0, 0x2, 1
+#define	MASK_WCI_SFQ_ESR_MASK_SFQ_OVFL 0x0, 0x1, 0
+#define	MASK_WCI_SFQ_STATE_RSVD_Z 0xffffffff, 0xfffffe00, 9
+#define	MASK_WCI_SFQ_STATE_INDEX 0x0, 0x1ff, 0
+#define	MASK_WCI_SHADOW_ADDR_SET_AGENT_RESET 0x80000000, 0x0, 63
+#define	MASK_WCI_SHADOW_ADDR_PULL_STOP 0x40000000, 0x0, 62
+#define	MASK_WCI_SHADOW_ADDR_DATA_STOP 0x20000000, 0x0, 61
+#define	MASK_WCI_SHADOW_ADDR_SHADOW_RSVD 0x10000000, 0x0, 60
+#define	MASK_WCI_SHADOW_ADDR_RSVD_Z 0xffc0000, 0x0, 50
+#define	MASK_WCI_SHADOW_ADDR_SHADOW_VALID 0x20000, 0x0, 49
+#define	MASK_WCI_SHADOW_ADDR_SHADOW_TIMEOUT 0x10000, 0x0, 48
+#define	MASK_WCI_SHADOW_ADDR_SHADOW_ADDR_NOT_VLD 0x8000, 0x0, 47
+#define	MASK_WCI_SHADOW_ADDR_SHADOW_SRAM_ERROR 0x4000, 0x0, 46
+#define	MASK_WCI_SHADOW_ADDR_SHADOW_SRAM 0x2000, 0x0, 45
+#define	MASK_WCI_SHADOW_ADDR_SHADOW_WRITE 0x1000, 0x0, 44
+#define	MASK_WCI_SHADOW_ADDR_RSVD_Y 0xfff, 0xe0000000, 29
+#define	MASK_WCI_SHADOW_ADDR_SHADOW_ADDR 0x0, 0x1fffffe0, 5
+#define	MASK_WCI_SHADOW_ADDR_RSVD_X 0x0, 0x1f, 0
+#define	MASK_WCI_SHADOW_DATA_SHADOW_DATA 0xffffffff, 0xffffffff, 0
+#define	MASK_WCI_SRAM_ARRAY_ERROR 0x80000000, 0x0, 63
+#define	MASK_WCI_SRAM_ARRAY_DATA 0x7fffffff, 0xffffffff, 0
+#define	MASK_WCI_SRAM_CE_COUNT_RSVD_Z 0xffffffff, 0xffffff00, 8
+#define	MASK_WCI_SRAM_CE_COUNT_CE_COUNT 0x0, 0xff, 0
+#define	MASK_WCI_SRAM_CONFIG_RSVD_Z 0xffffffff, 0xfff80000, 19
+#define	MASK_WCI_SRAM_CONFIG_ERROR_THRESHOLD 0x0, 0x7c000, 14
+#define	MASK_WCI_SRAM_CONFIG_ECC_WRITEBACK_DISABLE 0x0, 0x2000, 13
+#define	MASK_WCI_SRAM_CONFIG_ECC_DISABLE 0x0, 0x1000, 12
+#define	MASK_WCI_SRAM_CONFIG_PARITY_DISABLE 0x0, 0x800, 11
+#define	MASK_WCI_SRAM_CONFIG_USE_GA2LPA 0x0, 0x400, 10
+#define	MASK_WCI_SRAM_CONFIG_USE_DIRECTORY 0x0, 0x200, 9
+#define	MASK_WCI_SRAM_CONFIG_DIR_STRIPE 0x0, 0x180, 7
+#define	MASK_WCI_SRAM_CONFIG_RSVD_Y 0x0, 0x60, 5
+#define	MASK_WCI_SRAM_CONFIG_SRAM_SIZE 0x0, 0x1c, 2
+#define	MASK_WCI_SRAM_CONFIG_SRAM_SIZE_PINS 0x0, 0x3, 0
+#define	MASK_WCI_SRAM_ECC_ADDRESS_RSVD_Z 0xfffffffe, 0x0, 33
+#define	MASK_WCI_SRAM_ECC_ADDRESS_CE 0x1, 0x0, 32
+#define	MASK_WCI_SRAM_ECC_ADDRESS_ADDR_ERROR 0x0, 0x80000000, 31
+#define	MASK_WCI_SRAM_ECC_ADDRESS_SYNDROME 0x0, 0x7f000000, 24
+#define	MASK_WCI_SRAM_ECC_ADDRESS_ADDRESS 0x0, 0xffffff, 0
+#define	MASK_WCI_SRAM_STATUS_RSVD_Z 0xffffffff, 0xfff00000, 20
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_19 0x0, 0x80000, 19
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_18 0x0, 0x40000, 18
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_17 0x0, 0x20000, 17
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_16 0x0, 0x10000, 16
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_15 0x0, 0x8000, 15
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_14 0x0, 0x4000, 14
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_13 0x0, 0x2000, 13
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_12 0x0, 0x1000, 12
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_11 0x0, 0x800, 11
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_10 0x0, 0x400, 10
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_9 0x0, 0x200, 9
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_8 0x0, 0x100, 8
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_7 0x0, 0x80, 7
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_6 0x0, 0x40, 6
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_5 0x0, 0x20, 5
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_4 0x0, 0x10, 4
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_3 0x0, 0x8, 3
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_2 0x0, 0x4, 2
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_1 0x0, 0x2, 1
+#define	MASK_WCI_SRAM_STATUS_STICKY_ERROR_0 0x0, 0x1, 0
+#define	MASK_WCI_STICK_COUNT 0xffffffff, 0xffffffff, 0
+#define	MASK_WCI_STICK_RATE_RESET 0x80000000, 0x0, 63
+#define	MASK_WCI_STICK_RATE_CYCLE_LIMIT_INTEGER 0x7fff0000, 0x0, 48
+#define	MASK_WCI_STICK_RATE_CYCLE_LIMIT_FRACTION 0xffff, 0xffffffff, 0
+#define	MASK_WCI_SW_CONFIG_MAX_ERRORS 0xffffff00, 0x0, 40
+#define	MASK_WCI_SW_CONFIG_RSVD_Z 0xff, 0xfffe0000, 17
+#define	MASK_WCI_SW_CONFIG_ERROR_PAUSE_SHUTDOWN_EN 0x0, 0x10000, 16
+#define	MASK_WCI_SW_CONFIG_PARTNER_GNID 0x0, 0xf000, 12
+#define	MASK_WCI_SW_CONFIG_GNID 0x0, 0xf00, 8
+#define	MASK_WCI_SW_CONFIG_FAILOVER_EN 0x0, 0x80, 7
+#define	MASK_WCI_SW_CONFIG_DROP_ILLEGAL_GNID 0x0, 0x40, 6
+#define	MASK_WCI_SW_CONFIG_SYNC_BUFFER_SAFETY_LEVEL 0x0, 0x30, 4
+#define	MASK_WCI_SW_CONFIG_MASK_ORIGINATE_BROADCAST 0x0, 0x8, 3
+#define	MASK_WCI_SW_CONFIG_XMIT_ARB_POLICY 0x0, 0x6, 1
+#define	MASK_WCI_SW_CONFIG_ENABLE_DX_SHORTCUT 0x0, 0x1, 0
+#define	MASK_WCI_SW_ESR_RSVD_Z 0xffffffff, 0xf0000000, 28
+#define	MASK_WCI_SW_ESR_ACC_LINK_2_FAILOVER 0x0, 0x8000000, 27
+#define	MASK_WCI_SW_ESR_ACC_LINK_1_FAILOVER 0x0, 0x4000000, 26
+#define	MASK_WCI_SW_ESR_ACC_LINK_0_FAILOVER 0x0, 0x2000000, 25
+#define	MASK_WCI_SW_ESR_RSVD_Y 0x0, 0x1800000, 23
+#define	MASK_WCI_SW_ESR_ACC_LINK_2_AUTO_SHUT 0x0, 0x400000, 22
+#define	MASK_WCI_SW_ESR_ACC_LINK_1_AUTO_SHUT 0x0, 0x200000, 21
+#define	MASK_WCI_SW_ESR_ACC_LINK_0_AUTO_SHUT 0x0, 0x100000, 20
+#define	MASK_WCI_SW_ESR_ACC_ADDR_LPBK_ILLEGAL_GNID 0x0, 0x80000, 19
+#define	MASK_WCI_SW_ESR_ACC_ERROR_PAUSE_BROADCAST 0x0, 0x40000, 18
+#define	MASK_WCI_SW_ESR_ACC_ADDR_LPBK_FIFO_OVF 0x0, 0x20000, 17
+#define	MASK_WCI_SW_ESR_ACC_DATA_LPBK_FIFO_OVF 0x0, 0x10000, 16
+#define	MASK_WCI_SW_ESR_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_SW_ESR_RSVD_X 0x0, 0x7000, 12
+#define	MASK_WCI_SW_ESR_LINK_2_FAILOVER 0x0, 0x800, 11
+#define	MASK_WCI_SW_ESR_LINK_1_FAILOVER 0x0, 0x400, 10
+#define	MASK_WCI_SW_ESR_LINK_0_FAILOVER 0x0, 0x200, 9
+#define	MASK_WCI_SW_ESR_RSVD_W 0x0, 0x180, 7
+#define	MASK_WCI_SW_ESR_LINK_2_AUTO_SHUT 0x0, 0x40, 6
+#define	MASK_WCI_SW_ESR_LINK_1_AUTO_SHUT 0x0, 0x20, 5
+#define	MASK_WCI_SW_ESR_LINK_0_AUTO_SHUT 0x0, 0x10, 4
+#define	MASK_WCI_SW_ESR_ADDR_LPBK_ILLEGAL_GNID 0x0, 0x8, 3
+#define	MASK_WCI_SW_ESR_ERROR_PAUSE_BROADCAST 0x0, 0x4, 2
+#define	MASK_WCI_SW_ESR_ADDR_LPBK_FIFO_OVF 0x0, 0x2, 1
+#define	MASK_WCI_SW_ESR_DATA_LPBK_FIFO_OVF 0x0, 0x1, 0
+#define	MASK_WCI_SW_ESR_A_RSVD_Z 0xffffffff, 0xfffc0000, 18
+#define	MASK_WCI_SW_ESR_A_ACC_FO_B_FIFO_OVF 0x0, 0x20000, 17
+#define	MASK_WCI_SW_ESR_A_ACC_FO_A_FIFO_OVF 0x0, 0x10000, 16
+#define	MASK_WCI_SW_ESR_A_FIRST_ERROR 0x0, 0x8000, 15
+#define	MASK_WCI_SW_ESR_A_RSVD_Y 0x0, 0x7ffc, 2
+#define	MASK_WCI_SW_ESR_A_FO_B_FIFO_OVF 0x0, 0x2, 1
+#define	MASK_WCI_SW_ESR_A_FO_A_FIFO_OVF 0x0, 0x1, 0
+#define	MASK_WCI_SW_ESR_A_MASK_RSVD_Z 0xffffffff, 0xfffffffc, 2
+#define	MASK_WCI_SW_ESR_A_MASK_FO_B_FIFO_OVF 0x0, 0x2, 1
+#define	MASK_WCI_SW_ESR_A_MASK_FO_A_FIFO_OVF 0x0, 0x1, 0
+#define	MASK_WCI_SW_ESR_MASK_RSVD_Z 0xffffffff, 0xfffff000, 12
+#define	MASK_WCI_SW_ESR_MASK_LINK_2_FAILOVER 0x0, 0x800, 11
+#define	MASK_WCI_SW_ESR_MASK_LINK_1_FAILOVER 0x0, 0x400, 10
+#define	MASK_WCI_SW_ESR_MASK_LINK_0_FAILOVER 0x0, 0x200, 9
+#define	MASK_WCI_SW_ESR_MASK_RSVD_Y 0x0, 0x180, 7
+#define	MASK_WCI_SW_ESR_MASK_LINK_2_AUTO_SHUT 0x0, 0x40, 6
+#define	MASK_WCI_SW_ESR_MASK_LINK_1_AUTO_SHUT 0x0, 0x20, 5
+#define	MASK_WCI_SW_ESR_MASK_LINK_0_AUTO_SHUT 0x0, 0x10, 4
+#define	MASK_WCI_SW_ESR_MASK_ADDR_LPBK_ILLEGAL_GNID 0x0, 0x8, 3
+#define	MASK_WCI_SW_ESR_MASK_ERROR_PAUSE_BROADCAST 0x0, 0x4, 2
+#define	MASK_WCI_SW_ESR_MASK_ADDR_LPBK_FIFO_OVF 0x0, 0x2, 1
+#define	MASK_WCI_SW_ESR_MASK_DATA_LPBK_FIFO_OVF 0x0, 0x1, 0
+#define	MASK_WCI_SW_LINK_CONTROL_RSVD_Z 0xff800000, 0x0, 55
+#define	MASK_WCI_SW_LINK_CONTROL_REXMIT_FREEZE 0x400000, 0x0, 54
+#define	MASK_WCI_SW_LINK_CONTROL_REXMIT_MAG 0x300000, 0x0, 52
+#define	MASK_WCI_SW_LINK_CONTROL_REXMIT_VAL 0xff000, 0x0, 44
+#define	MASK_WCI_SW_LINK_CONTROL_ERROR_INDUCEMENT 0xc00, 0x0, 42
+#define	MASK_WCI_SW_LINK_CONTROL_XMIT_TIMEOUT 0x3fc, 0x0, 34
+#define	MASK_WCI_SW_LINK_CONTROL_USR_DATA_2 0x3, 0x0, 32
+#define	MASK_WCI_SW_LINK_CONTROL_USR_DATA_1 0x0, 0xffff0000, 16
+#define	MASK_WCI_SW_LINK_CONTROL_RSVD_Y 0x0, 0xe000, 13
+#define	MASK_WCI_SW_LINK_CONTROL_XMIT_ENABLE 0x0, 0x1000, 12
+#define	MASK_WCI_SW_LINK_CONTROL_USTAT_SRC 0x0, 0xc00, 10
+#define	MASK_WCI_SW_LINK_CONTROL_IN_DOMAIN 0x0, 0x200, 9
+#define	MASK_WCI_SW_LINK_CONTROL_PAROLI_TCK_ENABLE 0x0, 0x100, 8
+#define	MASK_WCI_SW_LINK_CONTROL_LASER_ENABLE 0x0, 0x80, 7
+#define	MASK_WCI_SW_LINK_CONTROL_RSVD_X 0x0, 0x40, 6
+#define	MASK_WCI_SW_LINK_CONTROL_REXMIT_SHUTDOWN_EN 0x0, 0x20, 5
+#define	MASK_WCI_SW_LINK_CONTROL_NEAR_END_SHUTDOWN_LOCK 0x0, 0x10, 4
+#define	MASK_WCI_SW_LINK_CONTROL_FAILOVER_EN 0x0, 0x8, 3
+#define	MASK_WCI_SW_LINK_CONTROL_AUTO_SHUT_EN 0x0, 0x4, 2
+#define	MASK_WCI_SW_LINK_CONTROL_LINK_STATE 0x0, 0x3, 0
+#define	MASK_WCI_SW_LINK_ERROR_COUNT_ERROR_COUNT 0xffffff00, 0x0, 40
+#define	MASK_WCI_SW_LINK_ERROR_COUNT_RSVD_Z 0xff, 0xffffffff, 0
+#define	MASK_WCI_SW_LINK_REXMIT_RSVD_Z 0xffffffff, 0x0, 32
+#define	MASK_WCI_SW_LINK_REXMIT_REXMIT_COUNT 0x0, 0xffffffff, 0
+#define	MASK_WCI_SW_LINK_STATUS_RSVD_Z 0xff800000, 0x0, 55
+#define	MASK_WCI_SW_LINK_STATUS_PAROLI_PRESENT 0x400000, 0x0, 54
+#define	MASK_WCI_SW_LINK_STATUS_BAD_GNID 0x3c0000, 0x0, 50
+#define	MASK_WCI_SW_LINK_STATUS_FAREND_USTAT_2 0x30000, 0x0, 48
+#define	MASK_WCI_SW_LINK_STATUS_FAREND_USTAT_1 0xffff, 0x0, 32
+#define	MASK_WCI_SW_LINK_STATUS_USTAT_1 0x0, 0xffff0000, 16
+#define	MASK_WCI_SW_LINK_STATUS_SHUTDOWN_CAUSE 0x0, 0xc000, 14
+#define	MASK_WCI_SW_LINK_STATUS_GOT_FO_PKT 0x0, 0x2000, 13
+#define	MASK_WCI_SW_LINK_STATUS_MULTIPLE_LINK_FAILOVER 0x0, 0x1000, 12
+#define	MASK_WCI_SW_LINK_STATUS_FAILOVER_CAUSE 0x0, 0x800, 11
+#define	MASK_WCI_SW_LINK_STATUS_LINK_IDLE 0x0, 0x400, 10
+#define	MASK_WCI_SW_LINK_STATUS_SYNC_LOCKED 0x0, 0x200, 9
+#define	MASK_WCI_SW_LINK_STATUS_OPTICAL_SIGNAL_DETECT 0x0, 0x100, 8
+#define	MASK_WCI_SW_LINK_STATUS_RESET_PENDING 0x0, 0x80, 7
+#define	MASK_WCI_SW_LINK_STATUS_FRAMING_ERROR 0x0, 0x40, 6
+#define	MASK_WCI_SW_LINK_STATUS_CLOCKING_ERROR 0x0, 0x20, 5
+#define	MASK_WCI_SW_LINK_STATUS_END_STATUS 0x0, 0x18, 3
+#define	MASK_WCI_SW_LINK_STATUS_CRC_ERROR 0x0, 0x4, 2
+#define	MASK_WCI_SW_LINK_STATUS_RSVD_Y 0x0, 0x2, 1
+#define	MASK_WCI_SW_LINK_STATUS_PACKETS_DISCARDED 0x0, 0x1, 0
+#define	MASK_WCI_SW_STATUS_RSVD_Z 0xffffffff, 0xfffffe00, 9
+#define	MASK_WCI_SW_STATUS_ADDR_LPBK_ILLEGAL_GNID 0x0, 0x1e0, 5
+#define	MASK_WCI_SW_STATUS_ERROR_PAUSE_BROADCAST_STATUS 0x0, 0x1c, 2
+#define	MASK_WCI_SW_STATUS_ORIGINATE 0x0, 0x2, 1
+#define	MASK_WCI_SW_STATUS_LOCAL_SOURCE 0x0, 0x1, 0
+#define	MASK_WCI_UE_DIRECTION_RSVD_Z 0xffffff80, 0x0, 39
+#define	MASK_WCI_UE_DIRECTION_OUTBOUND_ERROR_DETECTED 0x40, 0x0, 38
+#define	MASK_WCI_UE_DIRECTION_UE_INBOUND 0x20, 0x0, 37
+#define	MASK_WCI_UE_DIRECTION_UE_OUTBOUND 0x10, 0x0, 36
+#define	MASK_WCI_UE_DIRECTION_UE_AGENT 0xf, 0x0, 32
+#define	MASK_WCI_UE_DIRECTION_UE_STICK 0x0, 0xffffffff, 0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_WCI_MASKS_H */
diff --git a/usr/src/uts/sun4u/sys/wci_offsets.h b/usr/src/uts/sun4u/sys/wci_offsets.h
new file mode 100644
index 0000000000..f6bf2936c6
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wci_offsets.h
@@ -0,0 +1,299 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ * Automatically Generated file based on CSR definitions
+ *
+ */
+
+/*
+ * This file automatically generated from
+ *    wci_defs.csr
+ *    11/27/2000 17:21:38
+ *    Using  ./csr_filter.pl by pcw
+ */
+
+/* **DO NOT EDIT THIS FILE**  */
+/*
+ * File ../../../design/wci/include/wci_offsets.h *
+ */
+
+#ifndef _SYS_WCI_OFFSETS_H
+#define	_SYS_WCI_OFFSETS_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Include any headers you depend on.
+ */
+
+
+
+#define	ADDR_WCI_SRAM_ARRAY		0x00000000000
+#define	ENTRIES_WCI_SRAM_ARRAY		0x1000000
+#define	STRIDE_WCI_SRAM_ARRAY		0x20
+#define	ADDR_WCI_SHADOW_ADDR		0x00000000000
+#define	ADDR_WCI_SHADOW_DATA		0x00000000020
+#define	ADDR_WCI_CONFIG		0x00000000040
+#define	ADDR_WCI_DOMAIN_CONFIG		0x00000000060
+#define	ADDR_WCI_LOCAL_DEVICE_ID		0x00000000080
+#define	ADDR_WCI_RESET_CONFIG		0x000000000a0
+#define	ADDR_WCI_RESET_STATUS		0x000000000c0
+#define	ADDR_WCI_ID		0x000000000e0
+#define	ADDR_WCI_BOARD2CNID_CONTROL		0x00000000100
+#define	ADDR_WCI_CSR_CONTROL		0x00000000120
+#define	ADDR_WCI_ERROR_SUMMARY		0x00000000160
+#define	ADDR_WCI_ERROR_PAUSE_TIMER_HOLD		0x00000000180
+#define	ADDR_WCI_FIRST_ERROR_TIME		0x000000001a0
+#define	ADDR_WCI_CSRA_ESR		0x000000001c0
+#define	ADDR_WCI_CSRA_ESR_MASK		0x000000001e0
+#define	ADDR_WCI_CSRA_STATUS		0x00000000200
+#define	ADDR_WCI_CSRA_TIMEOUT_CONFIG		0x00000000220
+#define	ADDR_WCI_DC_ESR		0x00000000240
+#define	ADDR_WCI_DC_ESR_MASK		0x00000000260
+#define	ADDR_WCI_DCO_STATE		0x00000000280
+#define	ADDR_WCI_DCO_CE_COUNT		0x000000002a0
+#define	ADDR_WCI_DCI_STATE		0x000000002c0
+#define	ADDR_WCI_HLI_STRANGE_PKT_1		0x000000002e0
+#define	ADDR_WCI_HLI_STRANGE_PKT_0		0x00000000300
+#define	ADDR_WCI_HLI_ESR		0x00000000320
+#define	ADDR_WCI_HLI_ESR_MASK		0x00000000340
+#define	ADDR_WCI_HLI_STATE		0x00000000360
+#define	ADDR_WCI_SFQ_ESR		0x00000000380
+#define	ADDR_WCI_SFQ_ESR_MASK		0x000000003a0
+#define	ADDR_WCI_SFQ_STATE		0x000000003c0
+#define	ADDR_WCI_ERROR_INDUCEMENT		0x000000003e0
+#define	ADDR_WCI_UE_DIRECTION		0x00000000400
+#define	ADDR_WCI_GENERATES_CESR_NUMBER		0x00000000420
+#define	ADDR_WCI_DIF_TIMEOUT_CNTL		0x00000000440
+#define	ADDR_WCI_DIF_TIMEOUT_COUNT		0x00000000460
+#define	ADDR_WCI_MAX		0x00000000480
+#define	ADDR_WCI_JNK_ROUTE_MAP0		0x00000002000
+#define	ADDR_WCI_JNK_ROUTE_MAP1		0x00000002020
+#define	ADDR_WCI_STICK_RATE		0x00000004000
+#define	ADDR_WCI_STICK		0x00000004020
+#define	ADDR_WCI_MISC_CTR		0x00000006000
+#define	ADDR_WCI_MISC_CTR_CTL		0x00000006020
+#define	ADDR_WCI_MONITOR_PINS		0x00000006040
+#define	ADDR_WCI_SRAM_CONFIG		0x00000010000
+#define	ADDR_WCI_CLUSTER_MEMBERS_BITS		0x00000010080
+#define	ENTRIES_WCI_CLUSTER_MEMBERS_BITS		0x4
+#define	STRIDE_WCI_CLUSTER_MEMBERS_BITS		0x20
+#define	ADDR_WCI_NC_SLICE_CONFIG_ARRAY		0x00000010200
+#define	ENTRIES_WCI_NC_SLICE_CONFIG_ARRAY		0x8
+#define	STRIDE_WCI_NC_SLICE_CONFIG_ARRAY		0x20
+#define	ADDR_WCI_CLUSTER_CTR_CTL		0x00000010300
+#define	ADDR_WCI_SRAM_STATUS		0x00000010320
+#define	ADDR_WCI_SRAM_CE_COUNT		0x00000010340
+#define	ADDR_WCI_SRAM_ECC_ADDRESS		0x00000010360
+#define	ADDR_WCI_CCI_ESR		0x00000010380
+#define	ADDR_WCI_CCI_ESR_MASK		0x000000103a0
+#define	ADDR_WCI_CCI_ROUTE_MAP0		0x000000103c0
+#define	ADDR_WCI_CCI_ROUTE_MAP1		0x000000103e0
+#define	ADDR_WCI_CLUSTER_WRITE_LOCKOUT		0x00000010480
+#define	ENTRIES_WCI_CLUSTER_WRITE_LOCKOUT		0x4
+#define	STRIDE_WCI_CLUSTER_WRITE_LOCKOUT		0x20
+#define	ADDR_WCI_CLUSTER_CONFIG		0x00000020000
+#define	ADDR_WCI_CA_FREEZE		0x00000020020
+#define	ADDR_WCI_CA_BUSY		0x00000020040
+#define	ADDR_WCI_CA_FIRST_PACKET_0		0x00000020060
+#define	ADDR_WCI_CA_FIRST_PACKET_1		0x00000020080
+#define	ADDR_WCI_CA_ECC_ADDRESS		0x000000200a0
+#define	ADDR_WCI_CA_ERROR_TRANSACTION		0x000000200c0
+#define	ADDR_WCI_CA_TIMEOUT_CONFIG		0x000000200e0
+#define	ADDR_WCI_CA_CONFIG		0x00000020100
+#define	ADDR_WCI_CA_ESR_0		0x00000020120
+#define	ADDR_WCI_CA_ESR_1		0x00000020140
+#define	ADDR_WCI_CA_ESR_MASK		0x00000020160
+#define	ADDR_WCI_CLUSTER_SYNC		0x00000020180
+#define	ADDR_WCI_CA_TIMEOUT_CONFIG_2		0x000000201a0
+#define	ADDR_WCI_CA_ERROR_TRANSACTION_2		0x000000201c0
+#define	ADDR_WCI_QLIM_CONFIG_CAG		0x000000201e0
+#define	ADDR_WCI_QLIM_CAG_TIMER		0x00000020200
+#define	ADDR_WCI_BOARD2CNID_ARRAY		0x00000030000
+#define	ENTRIES_WCI_BOARD2CNID_ARRAY		0x38
+#define	STRIDE_WCI_BOARD2CNID_ARRAY		0x20
+#define	ADDR_WCI_INID2DNID_ARRAY		0x00000030800
+#define	ENTRIES_WCI_INID2DNID_ARRAY		0x40
+#define	STRIDE_WCI_INID2DNID_ARRAY		0x20
+#define	ADDR_WCI_RA_FREEZE		0x00000031000
+#define	ADDR_WCI_RA_BUSY		0x00000031020
+#define	ADDR_WCI_RA_FIRST_ERROR_AGENT		0x00000031040
+#define	ADDR_WCI_RA_FIRST_PACKET_0		0x00000031060
+#define	ADDR_WCI_RA_FIRST_PACKET_1		0x00000031080
+#define	ADDR_WCI_RA_ECC_ADDRESS		0x000000310a0
+#define	ADDR_WCI_RA_ERROR_TRANSACTION_0		0x000000310c0
+#define	ADDR_WCI_RA_ERROR_TRANSACTION_1		0x000000310e0
+#define	ADDR_WCI_RA_TIMEOUT_CONFIG		0x00000031100
+#define	ADDR_WCI_RA_ESR_0		0x00000031120
+#define	ADDR_WCI_RA_ESR_1		0x00000031140
+#define	ADDR_WCI_RA_ESR_MASK		0x00000031160
+#define	ADDR_WCI_RA_STATUS_ARRAY		0x00000031400
+#define	ENTRIES_WCI_RA_STATUS_ARRAY		0x20
+#define	STRIDE_WCI_RA_STATUS_ARRAY		0x20
+#define	ADDR_WCI_RA_STATUS_2_ARRAY		0x00000031800
+#define	ENTRIES_WCI_RA_STATUS_2_ARRAY		0x20
+#define	STRIDE_WCI_RA_STATUS_2_ARRAY		0x20
+#define	ADDR_WCI_RA_WRITE_LOCKOUT_STATUS		0x00000031c00
+#define	ADDR_WCI_RAG_ROUTE_MAP0		0x00000031c20
+#define	ADDR_WCI_RAG_ROUTE_MAP1		0x00000031c40
+#define	ADDR_WCI_CLUSTER_ERROR_STATUS_ARRAY		0x00000032000
+#define	ENTRIES_WCI_CLUSTER_ERROR_STATUS_ARRAY		0x100
+#define	STRIDE_WCI_CLUSTER_ERROR_STATUS_ARRAY		0x20
+#define	ADDR_WCI_CLUSTER_ERROR_COUNT		0x00000034000
+#define	ADDR_WCI_INT_DEST_BUSY_COUNT		0x00000034020
+#define	ADDR_WCI_QLIM_3REQ_PRIORITY		0x00000034040
+#define	ADDR_WCI_QLIM_2REQ_PRIORITY		0x00000034060
+#define	ADDR_WCI_QLIM_CONFIG_PIQ		0x00000034080
+#define	ADDR_WCI_QLIM_CONFIG_NIQ		0x000000340a0
+#define	ADDR_WCI_QLIM_CONFIG_CIQ		0x000000340c0
+#define	ADDR_WCI_QLIM_PIQ_TIMER		0x000000340e0
+#define	ADDR_WCI_QLIM_NIQ_TIMER		0x00000034100
+#define	ADDR_WCI_QLIM_CIQ_TIMER		0x00000034120
+#define	ADDR_WCI_OS_CLUSTER_DISABLE		0x00000034140
+#define	ADDR_WCI_SC_CLUSTER_DISABLE		0x00000034160
+#define	ADDR_WCI_HA_FREEZE		0x00000040000
+#define	ADDR_WCI_HA_BUSY		0x00000040020
+#define	ADDR_WCI_HA_FIRST_ERROR_AGENT		0x00000040040
+#define	ADDR_WCI_HA_FIRST_PACKET_0		0x00000040060
+#define	ADDR_WCI_HA_FIRST_PACKET_1		0x00000040080
+#define	ADDR_WCI_HA_ECC_ADDRESS		0x000000400a0
+#define	ADDR_WCI_HA_ERROR_ADDRESS		0x000000400c0
+#define	ADDR_WCI_HA_TIMEOUT_CONFIG		0x000000400e0
+#define	ADDR_WCI_HA_ESR_0		0x00000040100
+#define	ADDR_WCI_HA_ESR_1		0x00000040120
+#define	ADDR_WCI_HA_HW_ERR_STATUS		0x00000040140
+#define	ADDR_WCI_HA_ESR_MASK		0x00000040160
+#define	ADDR_WCI_PROBE_MEMORY		0x00000040180
+#define	ADDR_WCI_HA_STATUS_ARRAY		0x00000040200
+#define	ENTRIES_WCI_HA_STATUS_ARRAY		0x10
+#define	STRIDE_WCI_HA_STATUS_ARRAY		0x20
+#define	ADDR_WCI_HA_STATUS_2_ARRAY		0x00000040400
+#define	ENTRIES_WCI_HA_STATUS_2_ARRAY		0x10
+#define	STRIDE_WCI_HA_STATUS_2_ARRAY		0x20
+#define	ADDR_WCI_HA_CONFIG		0x00000040600
+#define	ADDR_WCI_HAG_ROUTE_MAP0		0x00000040620
+#define	ADDR_WCI_HAG_ROUTE_MAP1		0x00000040640
+#define	ADDR_WCI_EMISS_CNTL_ARRAY		0x00000042000
+#define	ENTRIES_WCI_EMISS_CNTL_ARRAY		0x10
+#define	STRIDE_WCI_EMISS_CNTL_ARRAY		0x20
+#define	ADDR_WCI_EMISS_DATA_ARRAY		0x00000042200
+#define	ENTRIES_WCI_EMISS_DATA_ARRAY		0x10
+#define	STRIDE_WCI_EMISS_DATA_ARRAY		0x20
+#define	ADDR_WCI_EMISS_RESET_CTL		0x00000042400
+#define	ADDR_WCI_GLOBAL_EMISS_COUNTER		0x00000042420
+#define	ADDR_WCI_SA_FREEZE		0x00000050000
+#define	ADDR_WCI_SA_BUSY		0x00000050020
+#define	ADDR_WCI_SA_FIRST_ERROR_AGENT		0x00000050040
+#define	ADDR_WCI_SA_FIRST_PACKET_0		0x00000050060
+#define	ADDR_WCI_SA_FIRST_PACKET_1		0x00000050080
+#define	ADDR_WCI_SA_ECC_ADDRESS		0x000000500a0
+#define	ADDR_WCI_SA_TIMEOUT_CONFIG		0x000000500c0
+#define	ADDR_WCI_SA_ESR_0		0x000000500e0
+#define	ADDR_WCI_SA_HW_ERR_STATE		0x00000050100
+#define	ADDR_WCI_SA_ESR_MASK		0x00000050120
+#define	ADDR_WCI_SA_STATUS_ARRAY		0x00000050200
+#define	ENTRIES_WCI_SA_STATUS_ARRAY		0x8
+#define	STRIDE_WCI_SA_STATUS_ARRAY		0x20
+#define	ADDR_WCI_SA_STATUS_2_ARRAY		0x00000050300
+#define	ENTRIES_WCI_SA_STATUS_2_ARRAY		0x8
+#define	STRIDE_WCI_SA_STATUS_2_ARRAY		0x20
+#define	ADDR_WCI_SA_STATUS_3_ARRAY		0x00000050400
+#define	ENTRIES_WCI_SA_STATUS_3_ARRAY		0x8
+#define	STRIDE_WCI_SA_STATUS_3_ARRAY		0x20
+#define	ADDR_WCI_SA_STATUS_4_ARRAY		0x00000050500
+#define	ENTRIES_WCI_SA_STATUS_4_ARRAY		0x8
+#define	STRIDE_WCI_SA_STATUS_4_ARRAY		0x20
+#define	ADDR_WCI_SA_STATUS_5_ARRAY		0x00000050600
+#define	ENTRIES_WCI_SA_STATUS_5_ARRAY		0x8
+#define	STRIDE_WCI_SA_STATUS_5_ARRAY		0x20
+#define	ADDR_WCI_SA_STATUS_6_ARRAY		0x00000050700
+#define	ENTRIES_WCI_SA_STATUS_6_ARRAY		0x8
+#define	STRIDE_WCI_SA_STATUS_6_ARRAY		0x20
+#define	ADDR_WCI_SAG_ROUTE_MAP0		0x00000050800
+#define	ADDR_WCI_SAG_ROUTE_MAP1		0x00000050820
+#define	ADDR_WCI_NC2NID_ARRAY		0x00000060000
+#define	ENTRIES_WCI_NC2NID_ARRAY		0x100
+#define	STRIDE_WCI_NC2NID_ARRAY		0x20
+#define	ADDR_WCI_SFI_TRANSID_ALLOC		0x00000062000
+#define	ADDR_WCI_SFI_ESR		0x00000062020
+#define	ADDR_WCI_SFI_ESR_MASK		0x00000062040
+#define	ADDR_WCI_SFI_STATE		0x00000062060
+#define	ADDR_WCI_SFI_STATE1		0x00000062080
+#define	ADDR_WCI_SFI_CTR1_MASK		0x00000064000
+#define	ADDR_WCI_SFI_CTR1_MATCH_TRANSACTION		0x00000064020
+#define	ADDR_WCI_SFI_CTR1_MATCH		0x00000064040
+#define	ADDR_WCI_SFI_CTR0_MASK		0x00000064060
+#define	ADDR_WCI_SFI_CTR0_MATCH_TRANSACTION		0x00000064080
+#define	ADDR_WCI_SFI_CTR0_MATCH		0x000000640a0
+#define	ADDR_WCI_SFI_ANALYZER		0x000000640c0
+#define	ADDR_WCI_SFI_ROUTE_MAP0		0x000000640e0
+#define	ADDR_WCI_SFI_ROUTE_MAP1		0x00000064100
+#define	ADDR_WCI_QLIM_SORT_PIQ		0x00000064120
+#define	ADDR_WCI_QLIM_SORT_NIQ		0x00000064140
+#define	ADDR_WCI_QLIM_SORT_CIQ		0x00000064160
+#define	ADDR_WCI_LINK_ESR		0x00000070000
+#define	ADDR_WCI_LINK_ESR_MASK		0x00000070100
+#define	ADDR_WCI_SW_ESR		0x00000070120
+#define	ADDR_WCI_SW_ESR_MASK		0x00000070140
+#define	ADDR_WCI_SW_LINK_CONTROL		0x00000070200
+#define	ENTRIES_WCI_SW_LINK_CONTROL		0x3
+#define	STRIDE_WCI_SW_LINK_CONTROL		0x20
+#define	ADDR_WCI_SW_LINK_ERROR_COUNT		0x00000070300
+#define	ENTRIES_WCI_SW_LINK_ERROR_COUNT		0x3
+#define	STRIDE_WCI_SW_LINK_ERROR_COUNT		0x20
+#define	ADDR_WCI_SW_LINK_STATUS		0x00000070400
+#define	ENTRIES_WCI_SW_LINK_STATUS		0x3
+#define	STRIDE_WCI_SW_LINK_STATUS		0x20
+#define	ADDR_WCI_SW_CONFIG		0x00000070500
+#define	ADDR_WCI_SW_STATUS		0x00000070520
+#define	ADDR_WCI_LINK_CTR_CTL		0x00000070600
+#define	ENTRIES_WCI_LINK_CTR_CTL		0x3
+#define	STRIDE_WCI_LINK_CTR_CTL		0x20
+#define	ADDR_WCI_LPBK_CTR_CTL		0x00000070700
+#define	ADDR_WCI_LINK_CTR		0x00000070800
+#define	ENTRIES_WCI_LINK_CTR		0x3
+#define	STRIDE_WCI_LINK_CTR		0x20
+#define	ADDR_WCI_LPBK_CTR		0x00000070900
+#define	ADDR_WCI_SW_ESR_A		0x00000070920
+#define	ADDR_WCI_SW_ESR_A_MASK		0x00000070940
+#define	ADDR_WCI_GNID_MAP0		0x00000070960
+#define	ADDR_WCI_GNID_MAP1		0x00000070980
+#define	ADDR_WCI_FO_ROUTE_MAP		0x000000709a0
+#define	ADDR_WCI_SEC_FO_ROUTE_MAP		0x000000709c0
+#define	ADDR_WCI_FO_TNID_MAP		0x000000709e0
+#define	ADDR_WCI_SW_LINK_REXMIT		0x00000070b00
+#define	ENTRIES_WCI_SW_LINK_REXMIT		0x3
+#define	STRIDE_WCI_SW_LINK_REXMIT		0x20
+#define	ADDR_WCI_DNID2GNID		0x00000070c00
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_WCI_OFFSETS_H */
diff --git a/usr/src/uts/sun4u/sys/wci_regs.h b/usr/src/uts/sun4u/sys/wci_regs.h
new file mode 100644
index 0000000000..e8ce40ae80
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wci_regs.h
@@ -0,0 +1,6920 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2001,2003 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_WCI_REGS_H
+#define	_SYS_WCI_REGS_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(_KERNEL) && !defined(_ASM)
+
+/*
+ * wci_sram_array
+ */
+typedef union {
+	struct wci_sram_array {
+		uint64_t error				: 1;	/* 63 */
+		uint64_t data				: 63;	/* 62:0 */
+	} bit;
+	uint64_t val;
+} wci_sram_array_u;
+
+#define	wci_sram_array_error	\
+	bit.error
+#define	wci_sram_array_data	\
+	bit.data
+
+
+/*
+ * wci_shadow_addr
+ */
+typedef union {
+	struct wci_shadow_addr {
+		uint64_t set_agent_reset		: 1;	/* 63 */
+		uint64_t pull_stop			: 1;	/* 62 */
+		uint64_t data_stop			: 1;	/* 61 */
+		uint64_t shadow_rsvd			: 1;	/* 60 */
+		uint64_t rsvd_z				: 10;	/* 59:50 */
+		uint64_t shadow_valid			: 1;	/* 49 */
+		uint64_t shadow_timeout			: 1;	/* 48 */
+		uint64_t shadow_addr_not_vld		: 1;	/* 47 */
+		uint64_t shadow_sram_error		: 1;	/* 46 */
+		uint64_t shadow_sram			: 1;	/* 45 */
+		uint64_t shadow_write			: 1;	/* 44 */
+		uint64_t rsvd_y				: 15;	/* 43:29 */
+		uint64_t shadow_addr			: 24;	/* 28:5 */
+		uint64_t rsvd_x				: 5;	/* 4:0 */
+	} bit;
+	uint64_t val;
+} wci_shadow_addr_u;
+
+#define	wci_shadow_addr_set_agent_reset	\
+	bit.set_agent_reset
+#define	wci_shadow_addr_pull_stop	\
+	bit.pull_stop
+#define	wci_shadow_addr_data_stop	\
+	bit.data_stop
+#define	wci_shadow_addr_shadow_rsvd	\
+	bit.shadow_rsvd
+#define	wci_shadow_addr_shadow_valid	\
+	bit.shadow_valid
+#define	wci_shadow_addr_shadow_timeout	\
+	bit.shadow_timeout
+#define	wci_shadow_addr_shadow_addr_not_vld	\
+	bit.shadow_addr_not_vld
+#define	wci_shadow_addr_shadow_sram_error	\
+	bit.shadow_sram_error
+#define	wci_shadow_addr_shadow_sram	\
+	bit.shadow_sram
+#define	wci_shadow_addr_shadow_write	\
+	bit.shadow_write
+#define	wci_shadow_addr_shadow_addr	\
+	bit.shadow_addr
+
+
+/*
+ * wci_shadow_data
+ */
+typedef union {
+	struct wci_shadow_data {
+		uint64_t shadow_data			: 64;	/* 63:0 */
+	} bit;
+	uint64_t val;
+} wci_shadow_data_u;
+
+#define	wci_shadow_data_shadow_data	\
+	bit.shadow_data
+
+
+/*
+ * wci_config
+ */
+typedef union {
+	struct wci_config {
+		uint64_t rsvd_z				: 19;	/* 63:45 */
+		uint64_t wr_dir_on_rinv_miss		: 1;	/* 44 */
+		uint64_t wr_dir_on_rws_miss		: 1;	/* 43 */
+		uint64_t safari_compliant_targid	: 1;	/* 42 */
+		uint64_t rsvd_y				: 3;	/* 41:39 */
+		uint64_t cluster_early_reuse_en		: 1;	/* 38 */
+		uint64_t reserved_default_0		: 1;	/* 37 */
+		uint64_t ra_numa_bypass_en		: 1;	/* 36 */
+		uint64_t ha_disable_unexp_snid		: 1;	/* 35 */
+		uint64_t ra_disable_unexp_snid		: 1;	/* 34 */
+		uint64_t dc_cpi_snid_disable		: 1;	/* 33 */
+		uint64_t dbg_bytemask_en		: 1;	/* 32 */
+		uint64_t partner_node_id		: 4;	/* 31:28 */
+		uint64_t cluster_mode			: 1;	/* 27 */
+		uint64_t rsvd_x				: 1;	/* 26 */
+		uint64_t nc_stripe_by_addr		: 1;	/* 25 */
+		uint64_t enable_inid			: 1;	/* 24 */
+		uint64_t stripe_bits			: 4;	/* 23:20 */
+		uint64_t dev_config_node_id		: 5;	/* 19:15 */
+		uint64_t box_id				: 6;	/* 14:9 */
+		uint64_t device_id			: 5;	/* 8:4 */
+		uint64_t node_id			: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_config_u;
+
+#define	wci_config_wr_dir_on_rinv_miss	\
+	bit.wr_dir_on_rinv_miss
+#define	wci_config_wr_dir_on_rws_miss	\
+	bit.wr_dir_on_rws_miss
+#define	wci_config_safari_compliant_targid	\
+	bit.safari_compliant_targid
+#define	wci_config_cluster_early_reuse_en	\
+	bit.cluster_early_reuse_en
+#define	wci_config_reserved_default_0	\
+	bit.reserved_default_0
+#define	wci_config_ra_numa_bypass_en	\
+	bit.ra_numa_bypass_en
+#define	wci_config_ha_disable_unexp_snid	\
+	bit.ha_disable_unexp_snid
+#define	wci_config_ra_disable_unexp_snid	\
+	bit.ra_disable_unexp_snid
+#define	wci_config_dc_cpi_snid_disable	\
+	bit.dc_cpi_snid_disable
+#define	wci_config_dbg_bytemask_en	\
+	bit.dbg_bytemask_en
+#define	wci_config_partner_node_id	\
+	bit.partner_node_id
+#define	wci_config_cluster_mode	\
+	bit.cluster_mode
+#define	wci_config_nc_stripe_by_addr	\
+	bit.nc_stripe_by_addr
+#define	wci_config_enable_inid	\
+	bit.enable_inid
+#define	wci_config_stripe_bits	\
+	bit.stripe_bits
+#define	wci_config_dev_config_node_id	\
+	bit.dev_config_node_id
+#define	wci_config_box_id	\
+	bit.box_id
+#define	wci_config_device_id	\
+	bit.device_id
+#define	wci_config_node_id	\
+	bit.node_id
+
+
+/*
+ * wci_domain_config
+ */
+typedef union {
+	struct wci_domain_config {
+		uint64_t rsvd_z				: 48;	/* 63:16 */
+		uint64_t domain_mask			: 16;	/* 15:0 */
+	} bit;
+	uint64_t val;
+} wci_domain_config_u;
+
+#define	wci_domain_config_domain_mask	\
+	bit.domain_mask
+
+
+/*
+ * wci_local_device_id
+ */
+typedef union {
+	struct wci_local_device_id {
+		uint64_t skip_rs_vec			: 32;	/* 63:32 */
+		uint64_t ssm_mask			: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_local_device_id_u;
+
+#define	wci_local_device_id_skip_rs_vec	\
+	bit.skip_rs_vec
+#define	wci_local_device_id_ssm_mask	\
+	bit.ssm_mask
+
+
+/*
+ * wci_reset_config
+ */
+typedef union {
+	struct wci_reset_config {
+		uint64_t rsvd_z				: 63;	/* 63:1 */
+		uint64_t agent_reset_e			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_reset_config_u;
+
+#define	wci_reset_config_agent_reset_e	\
+	bit.agent_reset_e
+
+
+/*
+ * wci_reset_status
+ */
+typedef union {
+	struct wci_reset_status {
+		uint64_t rsvd_z				: 61;	/* 63:3 */
+		uint64_t por				: 1;	/* 2 */
+		uint64_t node_reset			: 1;	/* 1 */
+		uint64_t agent_reset			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_reset_status_u;
+
+#define	wci_reset_status_por	\
+	bit.por
+#define	wci_reset_status_node_reset	\
+	bit.node_reset
+#define	wci_reset_status_agent_reset	\
+	bit.agent_reset
+
+
+/*
+ * wci_id
+ */
+typedef union {
+	struct wci_id {
+		uint64_t rsvd_z				: 32;	/* 63:32 */
+		uint64_t version			: 4;	/* 31:28 */
+		uint64_t parid				: 16;	/* 27:12 */
+		uint64_t manfid				: 11;	/* 11:1 */
+		uint64_t one				: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_id_u;
+
+#define	wci_id_version	\
+	bit.version
+#define	wci_id_parid	\
+	bit.parid
+#define	wci_id_manfid	\
+	bit.manfid
+#define	wci_id_one	\
+	bit.one
+
+
+/*
+ * wci_board2cnid_control
+ */
+typedef union {
+	struct wci_board2cnid_control {
+		uint64_t rsvd_z				: 63;	/* 63:1 */
+		uint64_t board2cnid_enable		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_board2cnid_control_u;
+
+#define	wci_board2cnid_control_board2cnid_enable	\
+	bit.board2cnid_enable
+
+
+/*
+ * wci_csr_control
+ */
+typedef union {
+	struct wci_csr_control {
+		uint64_t rsvd_z				: 63;	/* 63:1 */
+		uint64_t jtag_wr_only			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_csr_control_u;
+
+#define	wci_csr_control_jtag_wr_only	\
+	bit.jtag_wr_only
+
+
+/*
+ * wci_error_summary
+ */
+typedef union {
+	struct wci_error_summary {
+		uint64_t rsvd_z				: 53;	/* 63:11 */
+		uint64_t cci_error			: 1;	/* 10 */
+		uint64_t request_agent_error		: 1;	/* 9 */
+		uint64_t home_agent_error		: 1;	/* 8 */
+		uint64_t slave_agent_error		: 1;	/* 7 */
+		uint64_t cluster_agent_error		: 1;	/* 6 */
+		uint64_t csr_agent_error		: 1;	/* 5 */
+		uint64_t lc_error			: 1;	/* 4 */
+		uint64_t sfi_error			: 1;	/* 3 */
+		uint64_t sfq_error			: 1;	/* 2 */
+		uint64_t dc_error			: 1;	/* 1 */
+		uint64_t hli_error			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_error_summary_u;
+
+#define	wci_error_summary_cci_error	\
+	bit.cci_error
+#define	wci_error_summary_request_agent_error	\
+	bit.request_agent_error
+#define	wci_error_summary_home_agent_error	\
+	bit.home_agent_error
+#define	wci_error_summary_slave_agent_error	\
+	bit.slave_agent_error
+#define	wci_error_summary_cluster_agent_error	\
+	bit.cluster_agent_error
+#define	wci_error_summary_csr_agent_error	\
+	bit.csr_agent_error
+#define	wci_error_summary_lc_error	\
+	bit.lc_error
+#define	wci_error_summary_sfi_error	\
+	bit.sfi_error
+#define	wci_error_summary_sfq_error	\
+	bit.sfq_error
+#define	wci_error_summary_dc_error	\
+	bit.dc_error
+#define	wci_error_summary_hli_error	\
+	bit.hli_error
+
+
+/*
+ * wci_error_pause_timer_hold
+ */
+typedef union {
+	struct wci_error_pause_timer_hold {
+		uint64_t rsvd_z				: 56;	/* 63:8 */
+		uint64_t ca_aphase			: 1;	/* 7 */
+		uint64_t ca_dphase			: 1;	/* 6 */
+		uint64_t ca_reuse			: 1;	/* 5 */
+		uint64_t reserved			: 1;	/* 4 */
+		uint64_t ra_cluster_primary		: 1;	/* 3 */
+		uint64_t ra_ssm_primary			: 1;	/* 2 */
+		uint64_t ha_primary			: 1;	/* 1 */
+		uint64_t sa_primary			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_error_pause_timer_hold_u;
+
+#define	wci_error_pause_timer_hold_ca_aphase	\
+	bit.ca_aphase
+#define	wci_error_pause_timer_hold_ca_dphase	\
+	bit.ca_dphase
+#define	wci_error_pause_timer_hold_ca_reuse	\
+	bit.ca_reuse
+#define	wci_error_pause_timer_hold_reserved	\
+	bit.reserved
+#define	wci_error_pause_timer_hold_ra_cluster_primary	\
+	bit.ra_cluster_primary
+#define	wci_error_pause_timer_hold_ra_ssm_primary	\
+	bit.ra_ssm_primary
+#define	wci_error_pause_timer_hold_ha_primary	\
+	bit.ha_primary
+#define	wci_error_pause_timer_hold_sa_primary	\
+	bit.sa_primary
+
+
+/*
+ * wci_first_error_time
+ */
+typedef union {
+	struct wci_first_error_time {
+		uint64_t stick_time			: 64;	/* 63:0 */
+	} bit;
+	uint64_t val;
+} wci_first_error_time_u;
+
+#define	wci_first_error_time_stick_time	\
+	bit.stick_time
+
+
+/*
+ * wci_csra_esr
+ */
+typedef union {
+	struct wci_csra_esr {
+		uint64_t rsvd_z				: 37;	/* 63:27 */
+		uint64_t acc_timeout			: 1;	/* 26 */
+		uint64_t acc_pull_targid_timeout	: 1;	/* 25 */
+		uint64_t acc_pull_timeout		: 1;	/* 24 */
+		uint64_t acc_sram_error			: 1;	/* 23 */
+		uint64_t acc_protection_error		: 1;	/* 22 */
+		uint64_t acc_uncorrectable_mtag_error	: 1;	/* 21 */
+		uint64_t acc_uncorrectable_data_error	: 1;	/* 20 */
+		uint64_t acc_correctable_mtag_error	: 1;	/* 19 */
+		uint64_t acc_correctable_data_error	: 1;	/* 18 */
+		uint64_t acc_mtag_not_gm		: 1;	/* 17 */
+		uint64_t acc_mtag_mismatch		: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t rsvd_y				: 4;	/* 14:11 */
+		uint64_t timeout			: 1;	/* 10 */
+		uint64_t pull_targid_timeout		: 1;	/* 9 */
+		uint64_t pull_timeout			: 1;	/* 8 */
+		uint64_t sram_error			: 1;	/* 7 */
+		uint64_t protection_error		: 1;	/* 6 */
+		uint64_t uncorrectable_mtag_error	: 1;	/* 5 */
+		uint64_t uncorrectable_data_error	: 1;	/* 4 */
+		uint64_t correctable_mtag_error		: 1;	/* 3 */
+		uint64_t correctable_data_error		: 1;	/* 2 */
+		uint64_t mtag_not_gm			: 1;	/* 1 */
+		uint64_t mtag_mismatch			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_csra_esr_u;
+
+#define	wci_csra_esr_acc_timeout	\
+	bit.acc_timeout
+#define	wci_csra_esr_acc_pull_targid_timeout	\
+	bit.acc_pull_targid_timeout
+#define	wci_csra_esr_acc_pull_timeout	\
+	bit.acc_pull_timeout
+#define	wci_csra_esr_acc_sram_error	\
+	bit.acc_sram_error
+#define	wci_csra_esr_acc_protection_error	\
+	bit.acc_protection_error
+#define	wci_csra_esr_acc_uncorrectable_mtag_error	\
+	bit.acc_uncorrectable_mtag_error
+#define	wci_csra_esr_acc_uncorrectable_data_error	\
+	bit.acc_uncorrectable_data_error
+#define	wci_csra_esr_acc_correctable_mtag_error	\
+	bit.acc_correctable_mtag_error
+#define	wci_csra_esr_acc_correctable_data_error	\
+	bit.acc_correctable_data_error
+#define	wci_csra_esr_acc_mtag_not_gm	\
+	bit.acc_mtag_not_gm
+#define	wci_csra_esr_acc_mtag_mismatch	\
+	bit.acc_mtag_mismatch
+#define	wci_csra_esr_first_error	\
+	bit.first_error
+#define	wci_csra_esr_timeout	\
+	bit.timeout
+#define	wci_csra_esr_pull_targid_timeout	\
+	bit.pull_targid_timeout
+#define	wci_csra_esr_pull_timeout	\
+	bit.pull_timeout
+#define	wci_csra_esr_sram_error	\
+	bit.sram_error
+#define	wci_csra_esr_protection_error	\
+	bit.protection_error
+#define	wci_csra_esr_uncorrectable_mtag_error	\
+	bit.uncorrectable_mtag_error
+#define	wci_csra_esr_uncorrectable_data_error	\
+	bit.uncorrectable_data_error
+#define	wci_csra_esr_correctable_mtag_error	\
+	bit.correctable_mtag_error
+#define	wci_csra_esr_correctable_data_error	\
+	bit.correctable_data_error
+#define	wci_csra_esr_mtag_not_gm	\
+	bit.mtag_not_gm
+#define	wci_csra_esr_mtag_mismatch	\
+	bit.mtag_mismatch
+
+
+/*
+ * wci_csra_esr_mask
+ */
+typedef union {
+	struct wci_csra_esr_mask {
+		uint64_t rsvd_z				: 53;	/* 63:11 */
+		uint64_t timeout			: 1;	/* 10 */
+		uint64_t pull_targid_timeout		: 1;	/* 9 */
+		uint64_t pull_timeout			: 1;	/* 8 */
+		uint64_t sram_error			: 1;	/* 7 */
+		uint64_t protection_error		: 1;	/* 6 */
+		uint64_t uncorrectable_mtag_error	: 1;	/* 5 */
+		uint64_t uncorrectable_data_error	: 1;	/* 4 */
+		uint64_t correctable_mtag_error		: 1;	/* 3 */
+		uint64_t correctable_data_error		: 1;	/* 2 */
+		uint64_t mtag_not_gm			: 1;	/* 1 */
+		uint64_t mtag_mismatch			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_csra_esr_mask_u;
+
+#define	wci_csra_esr_mask_timeout	\
+	bit.timeout
+#define	wci_csra_esr_mask_pull_targid_timeout	\
+	bit.pull_targid_timeout
+#define	wci_csra_esr_mask_pull_timeout	\
+	bit.pull_timeout
+#define	wci_csra_esr_mask_sram_error	\
+	bit.sram_error
+#define	wci_csra_esr_mask_protection_error	\
+	bit.protection_error
+#define	wci_csra_esr_mask_uncorrectable_mtag_error	\
+	bit.uncorrectable_mtag_error
+#define	wci_csra_esr_mask_uncorrectable_data_error	\
+	bit.uncorrectable_data_error
+#define	wci_csra_esr_mask_correctable_mtag_error	\
+	bit.correctable_mtag_error
+#define	wci_csra_esr_mask_correctable_data_error	\
+	bit.correctable_data_error
+#define	wci_csra_esr_mask_mtag_not_gm	\
+	bit.mtag_not_gm
+#define	wci_csra_esr_mask_mtag_mismatch	\
+	bit.mtag_mismatch
+
+
+/*
+ * wci_csra_status
+ */
+typedef union {
+	struct wci_csra_status {
+		uint64_t rsvd_z				: 1;	/* 63 */
+		uint64_t esr_index			: 4;	/* 62:59 */
+		uint64_t scar				: 1;	/* 58 */
+		uint64_t atransid			: 9;	/* 57:49 */
+		uint64_t targid_3_to_0			: 3;	/* 48:46 */
+		uint64_t cesr_number			: 8;	/* 45:38 */
+		uint64_t rw				: 1;	/* 37 */
+		uint64_t nc_slice			: 8;	/* 36:29 */
+		uint64_t sf_addr_28_to_5		: 24;	/* 28:5 */
+		uint64_t fsm_state			: 3;	/* 4:2 */
+		uint64_t type				: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_csra_status_u;
+
+#define	wci_csra_status_esr_index	\
+	bit.esr_index
+#define	wci_csra_status_scar	\
+	bit.scar
+#define	wci_csra_status_atransid	\
+	bit.atransid
+#define	wci_csra_status_targid_3_to_0	\
+	bit.targid_3_to_0
+#define	wci_csra_status_cesr_number	\
+	bit.cesr_number
+#define	wci_csra_status_rw	\
+	bit.rw
+#define	wci_csra_status_nc_slice	\
+	bit.nc_slice
+#define	wci_csra_status_sf_addr_28_to_5	\
+	bit.sf_addr_28_to_5
+#define	wci_csra_status_fsm_state	\
+	bit.fsm_state
+#define	wci_csra_status_type	\
+	bit.type
+
+
+/*
+ * wci_csra_timeout_config
+ */
+typedef union {
+	struct wci_csra_timeout_config {
+		uint64_t rsvd_z				: 43;	/* 63:21 */
+		uint64_t pull_targid_fail_fast_enable	: 1;	/* 20 */
+		uint64_t pull_fail_fast_enable		: 1;	/* 19 */
+		uint64_t disable			: 1;	/* 18 */
+		uint64_t freeze				: 1;	/* 17 */
+		uint64_t magnitude			: 1;	/* 16 */
+		uint64_t rd_timeout			: 8;	/* 15:8 */
+		uint64_t wr_timeout			: 8;	/* 7:0 */
+	} bit;
+	uint64_t val;
+} wci_csra_timeout_config_u;
+
+#define	wci_csra_timeout_config_pull_targid_fail_fast_enable	\
+	bit.pull_targid_fail_fast_enable
+#define	wci_csra_timeout_config_pull_fail_fast_enable	\
+	bit.pull_fail_fast_enable
+#define	wci_csra_timeout_config_disable	\
+	bit.disable
+#define	wci_csra_timeout_config_freeze	\
+	bit.freeze
+#define	wci_csra_timeout_config_magnitude	\
+	bit.magnitude
+#define	wci_csra_timeout_config_rd_timeout	\
+	bit.rd_timeout
+#define	wci_csra_timeout_config_wr_timeout	\
+	bit.wr_timeout
+
+
+/*
+ * wci_dc_esr
+ */
+typedef union {
+	struct wci_dc_esr {
+		uint64_t rsvd_z				: 38;	/* 63:26 */
+		uint64_t acc_dif_timeout		: 1;	/* 25 */
+		uint64_t acc_dci_d_err_dstat		: 1;	/* 24 */
+		uint64_t acc_dco_ce			: 1;	/* 23 */
+		uint64_t acc_dc_dif_overflow		: 1;	/* 22 */
+		uint64_t acc_dc_launch_queue_overflow	: 1;	/* 21 */
+		uint64_t acc_dco_map_error		: 1;	/* 20 */
+		uint64_t acc_dco_data_parity_error	: 1;	/* 19 */
+		uint64_t acc_dci_d_err			: 1;	/* 18 */
+		uint64_t acc_dci_cpi_invalid		: 1;	/* 17 */
+		uint64_t acc_dci_cpi_snid_mismatch	: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t rsvd_y				: 5;	/* 14:10 */
+		uint64_t dif_timeout			: 1;	/* 9 */
+		uint64_t dci_d_err_dstat		: 1;	/* 8 */
+		uint64_t dco_ce				: 1;	/* 7 */
+		uint64_t dc_dif_overflow		: 1;	/* 6 */
+		uint64_t dc_launch_queue_overflow	: 1;	/* 5 */
+		uint64_t dco_map_error			: 1;	/* 4 */
+		uint64_t dco_data_parity_error		: 1;	/* 3 */
+		uint64_t dci_d_err			: 1;	/* 2 */
+		uint64_t dci_cpi_invalid		: 1;	/* 1 */
+		uint64_t dci_cpi_snid_mismatch		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_dc_esr_u;
+
+#define	wci_dc_esr_acc_dif_timeout	\
+	bit.acc_dif_timeout
+#define	wci_dc_esr_acc_dci_d_err_dstat	\
+	bit.acc_dci_d_err_dstat
+#define	wci_dc_esr_acc_dco_ce	\
+	bit.acc_dco_ce
+#define	wci_dc_esr_acc_dc_dif_overflow	\
+	bit.acc_dc_dif_overflow
+#define	wci_dc_esr_acc_dc_launch_queue_overflow	\
+	bit.acc_dc_launch_queue_overflow
+#define	wci_dc_esr_acc_dco_map_error	\
+	bit.acc_dco_map_error
+#define	wci_dc_esr_acc_dco_data_parity_error	\
+	bit.acc_dco_data_parity_error
+#define	wci_dc_esr_acc_dci_d_err	\
+	bit.acc_dci_d_err
+#define	wci_dc_esr_acc_dci_cpi_invalid	\
+	bit.acc_dci_cpi_invalid
+#define	wci_dc_esr_acc_dci_cpi_snid_mismatch	\
+	bit.acc_dci_cpi_snid_mismatch
+#define	wci_dc_esr_first_error	\
+	bit.first_error
+#define	wci_dc_esr_dif_timeout	\
+	bit.dif_timeout
+#define	wci_dc_esr_dci_d_err_dstat	\
+	bit.dci_d_err_dstat
+#define	wci_dc_esr_dco_ce	\
+	bit.dco_ce
+#define	wci_dc_esr_dc_dif_overflow	\
+	bit.dc_dif_overflow
+#define	wci_dc_esr_dc_launch_queue_overflow	\
+	bit.dc_launch_queue_overflow
+#define	wci_dc_esr_dco_map_error	\
+	bit.dco_map_error
+#define	wci_dc_esr_dco_data_parity_error	\
+	bit.dco_data_parity_error
+#define	wci_dc_esr_dci_d_err	\
+	bit.dci_d_err
+#define	wci_dc_esr_dci_cpi_invalid	\
+	bit.dci_cpi_invalid
+#define	wci_dc_esr_dci_cpi_snid_mismatch	\
+	bit.dci_cpi_snid_mismatch
+
+
+/*
+ * wci_dc_esr_mask
+ */
+typedef union {
+	struct wci_dc_esr_mask {
+		uint64_t rsvd_z				: 54;	/* 63:10 */
+		uint64_t dif_timeout			: 1;	/* 9 */
+		uint64_t dci_d_err_dstat		: 1;	/* 8 */
+		uint64_t dco_ce				: 1;	/* 7 */
+		uint64_t dc_dif_overflow		: 1;	/* 6 */
+		uint64_t dc_launch_queue_overflow	: 1;	/* 5 */
+		uint64_t dco_map_error			: 1;	/* 4 */
+		uint64_t dco_data_parity_error		: 1;	/* 3 */
+		uint64_t dci_d_err			: 1;	/* 2 */
+		uint64_t dci_cpi_invalid		: 1;	/* 1 */
+		uint64_t dci_cpi_snid_mismatch		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_dc_esr_mask_u;
+
+#define	wci_dc_esr_mask_dif_timeout	\
+	bit.dif_timeout
+#define	wci_dc_esr_mask_dci_d_err_dstat	\
+	bit.dci_d_err_dstat
+#define	wci_dc_esr_mask_dco_ce	\
+	bit.dco_ce
+#define	wci_dc_esr_mask_dc_dif_overflow	\
+	bit.dc_dif_overflow
+#define	wci_dc_esr_mask_dc_launch_queue_overflow	\
+	bit.dc_launch_queue_overflow
+#define	wci_dc_esr_mask_dco_map_error	\
+	bit.dco_map_error
+#define	wci_dc_esr_mask_dco_data_parity_error	\
+	bit.dco_data_parity_error
+#define	wci_dc_esr_mask_dci_d_err	\
+	bit.dci_d_err
+#define	wci_dc_esr_mask_dci_cpi_invalid	\
+	bit.dci_cpi_invalid
+#define	wci_dc_esr_mask_dci_cpi_snid_mismatch	\
+	bit.dci_cpi_snid_mismatch
+
+
+/*
+ * wci_dco_state
+ */
+typedef union {
+	struct wci_dco_state {
+		uint64_t link_0_lq_overflow		: 1;	/* 63 */
+		uint64_t link_1_lq_overflow		: 1;	/* 62 */
+		uint64_t link_2_lq_overflow		: 1;	/* 61 */
+		uint64_t rsvd_z				: 2;	/* 60:59 */
+		uint64_t lpbk_lq_overflow		: 1;	/* 58 */
+		uint64_t csr_lq_overflow		: 1;	/* 57 */
+		uint64_t rsvd_y				: 5;	/* 56:52 */
+		uint64_t dco_map_error_dtarg		: 1;	/* 51 */
+		uint64_t dco_map_error_dtransid		: 9;	/* 50:42 */
+		uint64_t mtag_ecc_error_aid		: 7;	/* 41:35 */
+		uint64_t data_ecc_error_aid		: 7;	/* 34:28 */
+		uint64_t data_ecc_ue			: 1;	/* 27 */
+		uint64_t mtag_ecc_ue			: 1;	/* 26 */
+		uint64_t mtag_syndrome_0		: 4;	/* 25:22 */
+		uint64_t mtag_syndrome_1		: 4;	/* 21:18 */
+		uint64_t data_syndrome_0		: 9;	/* 17:9 */
+		uint64_t data_syndrome_1		: 9;	/* 8:0 */
+	} bit;
+	uint64_t val;
+} wci_dco_state_u;
+
+#define	wci_dco_state_link_0_lq_overflow	\
+	bit.link_0_lq_overflow
+#define	wci_dco_state_link_1_lq_overflow	\
+	bit.link_1_lq_overflow
+#define	wci_dco_state_link_2_lq_overflow	\
+	bit.link_2_lq_overflow
+#define	wci_dco_state_lpbk_lq_overflow	\
+	bit.lpbk_lq_overflow
+#define	wci_dco_state_csr_lq_overflow	\
+	bit.csr_lq_overflow
+#define	wci_dco_state_dco_map_error_dtarg	\
+	bit.dco_map_error_dtarg
+#define	wci_dco_state_dco_map_error_dtransid	\
+	bit.dco_map_error_dtransid
+#define	wci_dco_state_mtag_ecc_error_aid	\
+	bit.mtag_ecc_error_aid
+#define	wci_dco_state_data_ecc_error_aid	\
+	bit.data_ecc_error_aid
+#define	wci_dco_state_data_ecc_ue	\
+	bit.data_ecc_ue
+#define	wci_dco_state_mtag_ecc_ue	\
+	bit.mtag_ecc_ue
+#define	wci_dco_state_mtag_syndrome_0	\
+	bit.mtag_syndrome_0
+#define	wci_dco_state_mtag_syndrome_1	\
+	bit.mtag_syndrome_1
+#define	wci_dco_state_data_syndrome_0	\
+	bit.data_syndrome_0
+#define	wci_dco_state_data_syndrome_1	\
+	bit.data_syndrome_1
+
+
+/*
+ * wci_dco_ce_count
+ */
+typedef union {
+	struct wci_dco_ce_count {
+		uint64_t rsvd_z				: 56;	/* 63:8 */
+		uint64_t ce_count			: 8;	/* 7:0 */
+	} bit;
+	uint64_t val;
+} wci_dco_ce_count_u;
+
+#define	wci_dco_ce_count_ce_count	\
+	bit.ce_count
+
+
+/*
+ * wci_dci_state
+ */
+typedef union {
+	struct wci_dci_state {
+		uint64_t rsvd_z				: 40;	/* 63:24 */
+		uint64_t dci_d_err_dtarg		: 1;	/* 23 */
+		uint64_t dci_d_err_dtransid		: 9;	/* 22:14 */
+		uint64_t dci_cpi_err_dtarg		: 1;	/* 13 */
+		uint64_t dci_cpi_err_dtransid		: 9;	/* 12:4 */
+		uint64_t dci_cpi_err_source_nid		: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_dci_state_u;
+
+#define	wci_dci_state_dci_d_err_dtarg	\
+	bit.dci_d_err_dtarg
+#define	wci_dci_state_dci_d_err_dtransid	\
+	bit.dci_d_err_dtransid
+#define	wci_dci_state_dci_cpi_err_dtarg	\
+	bit.dci_cpi_err_dtarg
+#define	wci_dci_state_dci_cpi_err_dtransid	\
+	bit.dci_cpi_err_dtransid
+#define	wci_dci_state_dci_cpi_err_source_nid	\
+	bit.dci_cpi_err_source_nid
+
+
+/*
+ * wci_hli_strange_pkt_1
+ */
+typedef union {
+	struct wci_hli_strange_pkt_1 {
+		uint64_t rsvd_z				: 33;	/* 63:31 */
+		uint64_t hi				: 31;	/* 30:0 */
+	} bit;
+	uint64_t val;
+} wci_hli_strange_pkt_1_u;
+
+#define	wci_hli_strange_pkt_1_hi	\
+	bit.hi
+
+
+/*
+ * wci_hli_strange_pkt_0
+ */
+typedef union {
+	struct wci_hli_strange_pkt_0 {
+		uint64_t lo				: 64;	/* 63:0 */
+	} bit;
+	uint64_t val;
+} wci_hli_strange_pkt_0_u;
+
+#define	wci_hli_strange_pkt_0_lo	\
+	bit.lo
+
+
+/*
+ * wci_hli_esr
+ */
+typedef union {
+	struct wci_hli_esr {
+		uint64_t rsvd_z				: 41;	/* 63:23 */
+		uint64_t acc_slq_perr			: 1;	/* 22 */
+		uint64_t acc_hmq_perr			: 1;	/* 21 */
+		uint64_t acc_strange_pkt		: 1;	/* 20 */
+		uint64_t acc_bq_unfl			: 1;	/* 19 */
+		uint64_t acc_hmq_unfl			: 1;	/* 18 */
+		uint64_t acc_hmq_ovfl			: 1;	/* 17 */
+		uint64_t acc_slq_ovfl			: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t rsvd_y				: 8;	/* 14:7 */
+		uint64_t slq_perr			: 1;	/* 6 */
+		uint64_t hmq_perr			: 1;	/* 5 */
+		uint64_t strange_pkt			: 1;	/* 4 */
+		uint64_t bq_unfl			: 1;	/* 3 */
+		uint64_t hmq_unfl			: 1;	/* 2 */
+		uint64_t hmq_ovfl			: 1;	/* 1 */
+		uint64_t slq_ovfl			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_hli_esr_u;
+
+#define	wci_hli_esr_acc_slq_perr	\
+	bit.acc_slq_perr
+#define	wci_hli_esr_acc_hmq_perr	\
+	bit.acc_hmq_perr
+#define	wci_hli_esr_acc_strange_pkt	\
+	bit.acc_strange_pkt
+#define	wci_hli_esr_acc_bq_unfl	\
+	bit.acc_bq_unfl
+#define	wci_hli_esr_acc_hmq_unfl	\
+	bit.acc_hmq_unfl
+#define	wci_hli_esr_acc_hmq_ovfl	\
+	bit.acc_hmq_ovfl
+#define	wci_hli_esr_acc_slq_ovfl	\
+	bit.acc_slq_ovfl
+#define	wci_hli_esr_first_error	\
+	bit.first_error
+#define	wci_hli_esr_slq_perr	\
+	bit.slq_perr
+#define	wci_hli_esr_hmq_perr	\
+	bit.hmq_perr
+#define	wci_hli_esr_strange_pkt	\
+	bit.strange_pkt
+#define	wci_hli_esr_bq_unfl	\
+	bit.bq_unfl
+#define	wci_hli_esr_hmq_unfl	\
+	bit.hmq_unfl
+#define	wci_hli_esr_hmq_ovfl	\
+	bit.hmq_ovfl
+#define	wci_hli_esr_slq_ovfl	\
+	bit.slq_ovfl
+
+
+/*
+ * wci_hli_esr_mask
+ */
+typedef union {
+	struct wci_hli_esr_mask {
+		uint64_t rsvd_z				: 57;	/* 63:7 */
+		uint64_t slq_perr			: 1;	/* 6 */
+		uint64_t hmq_perr			: 1;	/* 5 */
+		uint64_t strange_pkt			: 1;	/* 4 */
+		uint64_t bq_unfl			: 1;	/* 3 */
+		uint64_t hmq_unfl			: 1;	/* 2 */
+		uint64_t hmq_ovfl			: 1;	/* 1 */
+		uint64_t slq_ovfl			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_hli_esr_mask_u;
+
+#define	wci_hli_esr_mask_slq_perr	\
+	bit.slq_perr
+#define	wci_hli_esr_mask_hmq_perr	\
+	bit.hmq_perr
+#define	wci_hli_esr_mask_strange_pkt	\
+	bit.strange_pkt
+#define	wci_hli_esr_mask_bq_unfl	\
+	bit.bq_unfl
+#define	wci_hli_esr_mask_hmq_unfl	\
+	bit.hmq_unfl
+#define	wci_hli_esr_mask_hmq_ovfl	\
+	bit.hmq_ovfl
+#define	wci_hli_esr_mask_slq_ovfl	\
+	bit.slq_ovfl
+
+
+/*
+ * wci_hli_state
+ */
+typedef union {
+	struct wci_hli_state {
+		uint64_t rsvd_z				: 1;	/* 63 */
+		uint64_t esr_index			: 4;	/* 62:59 */
+		uint64_t rsvd_y				: 34;	/* 58:25 */
+		uint64_t queue				: 17;	/* 24:8 */
+		uint64_t index				: 8;	/* 7:0 */
+	} bit;
+	uint64_t val;
+} wci_hli_state_u;
+
+#define	wci_hli_state_esr_index	\
+	bit.esr_index
+#define	wci_hli_state_queue	\
+	bit.queue
+#define	wci_hli_state_index	\
+	bit.index
+
+
+/*
+ * wci_sfq_esr
+ */
+typedef union {
+	struct wci_sfq_esr {
+		uint64_t rsvd_z				: 46;	/* 63:18 */
+		uint64_t acc_sfq_perr			: 1;	/* 17 */
+		uint64_t acc_sfq_ovfl			: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t rsvd_y				: 13;	/* 14:2 */
+		uint64_t sfq_perr			: 1;	/* 1 */
+		uint64_t sfq_ovfl			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sfq_esr_u;
+
+#define	wci_sfq_esr_acc_sfq_perr	\
+	bit.acc_sfq_perr
+#define	wci_sfq_esr_acc_sfq_ovfl	\
+	bit.acc_sfq_ovfl
+#define	wci_sfq_esr_first_error	\
+	bit.first_error
+#define	wci_sfq_esr_sfq_perr	\
+	bit.sfq_perr
+#define	wci_sfq_esr_sfq_ovfl	\
+	bit.sfq_ovfl
+
+
+/*
+ * wci_sfq_esr_mask
+ */
+typedef union {
+	struct wci_sfq_esr_mask {
+		uint64_t rsvd_z				: 62;	/* 63:2 */
+		uint64_t sfq_perr			: 1;	/* 1 */
+		uint64_t sfq_ovfl			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sfq_esr_mask_u;
+
+#define	wci_sfq_esr_mask_sfq_perr	\
+	bit.sfq_perr
+#define	wci_sfq_esr_mask_sfq_ovfl	\
+	bit.sfq_ovfl
+
+
+/*
+ * wci_sfq_state
+ */
+typedef union {
+	struct wci_sfq_state {
+		uint64_t rsvd_z				: 55;	/* 63:9 */
+		uint64_t index				: 9;	/* 8:0 */
+	} bit;
+	uint64_t val;
+} wci_sfq_state_u;
+
+#define	wci_sfq_state_index	\
+	bit.index
+
+
+/*
+ * wci_error_inducement
+ */
+typedef union {
+	struct wci_error_inducement {
+		uint64_t rsvd_z				: 8;	/* 63:56 */
+		uint64_t internal_sram_vector		: 7;	/* 55:49 */
+		uint64_t hmq_p				: 1;	/* 48 */
+		uint64_t slq_p				: 1;	/* 47 */
+		uint64_t sfq_p				: 1;	/* 46 */
+		uint64_t sram_ecc_xor_2_select		: 6;	/* 45:40 */
+		uint64_t sram_ecc_xor_1_select		: 6;	/* 39:34 */
+		uint64_t sram_p				: 2;	/* 33:32 */
+		uint64_t mtag_ecc0_xor			: 4;	/* 31:28 */
+		uint64_t mtag_ecc1_xor			: 4;	/* 27:24 */
+		uint64_t mtag0_xor			: 3;	/* 23:21 */
+		uint64_t mtag1_xor			: 3;	/* 20:18 */
+		uint64_t ecc0_xor			: 9;	/* 17:9 */
+		uint64_t ecc1_xor			: 9;	/* 8:0 */
+	} bit;
+	uint64_t val;
+} wci_error_inducement_u;
+
+#define	wci_error_inducement_internal_sram_vector	\
+	bit.internal_sram_vector
+#define	wci_error_inducement_hmq_p	\
+	bit.hmq_p
+#define	wci_error_inducement_slq_p	\
+	bit.slq_p
+#define	wci_error_inducement_sfq_p	\
+	bit.sfq_p
+#define	wci_error_inducement_sram_ecc_xor_2_select	\
+	bit.sram_ecc_xor_2_select
+#define	wci_error_inducement_sram_ecc_xor_1_select	\
+	bit.sram_ecc_xor_1_select
+#define	wci_error_inducement_sram_p	\
+	bit.sram_p
+#define	wci_error_inducement_mtag_ecc0_xor	\
+	bit.mtag_ecc0_xor
+#define	wci_error_inducement_mtag_ecc1_xor	\
+	bit.mtag_ecc1_xor
+#define	wci_error_inducement_mtag0_xor	\
+	bit.mtag0_xor
+#define	wci_error_inducement_mtag1_xor	\
+	bit.mtag1_xor
+#define	wci_error_inducement_ecc0_xor	\
+	bit.ecc0_xor
+#define	wci_error_inducement_ecc1_xor	\
+	bit.ecc1_xor
+
+
+/*
+ * wci_ue_direction
+ */
+typedef union {
+	struct wci_ue_direction {
+		uint64_t rsvd_z				: 25;	/* 63:39 */
+		uint64_t outbound_error_detected	: 1;	/* 38 */
+		uint64_t ue_inbound			: 1;	/* 37 */
+		uint64_t ue_outbound			: 1;	/* 36 */
+		uint64_t ue_agent			: 4;	/* 35:32 */
+		uint64_t ue_stick			: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_ue_direction_u;
+
+#define	wci_ue_direction_outbound_error_detected	\
+	bit.outbound_error_detected
+#define	wci_ue_direction_ue_inbound	\
+	bit.ue_inbound
+#define	wci_ue_direction_ue_outbound	\
+	bit.ue_outbound
+#define	wci_ue_direction_ue_agent	\
+	bit.ue_agent
+#define	wci_ue_direction_ue_stick	\
+	bit.ue_stick
+
+
+/*
+ * wci_generates_cesr_number
+ */
+typedef union {
+	struct wci_generates_cesr_number {
+		uint64_t rsvd_z				: 31;	/* 63:33 */
+		uint64_t enable				: 1;	/* 32 */
+		uint64_t device_vector			: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_generates_cesr_number_u;
+
+#define	wci_generates_cesr_number_enable	\
+	bit.enable
+#define	wci_generates_cesr_number_device_vector	\
+	bit.device_vector
+
+
+/*
+ * wci_dif_timeout_cntl
+ */
+typedef union {
+	struct wci_dif_timeout_cntl {
+		uint64_t rsvd_z				: 52;	/* 63:12 */
+		uint64_t timeout_disable		: 1;	/* 11 */
+		uint64_t timeout_freeze			: 1;	/* 10 */
+		uint64_t timeout_mag			: 2;	/* 9:8 */
+		uint64_t timeout_val			: 8;	/* 7:0 */
+	} bit;
+	uint64_t val;
+} wci_dif_timeout_cntl_u;
+
+#define	wci_dif_timeout_cntl_timeout_disable	\
+	bit.timeout_disable
+#define	wci_dif_timeout_cntl_timeout_freeze	\
+	bit.timeout_freeze
+#define	wci_dif_timeout_cntl_timeout_mag	\
+	bit.timeout_mag
+#define	wci_dif_timeout_cntl_timeout_val	\
+	bit.timeout_val
+
+
+/*
+ * wci_dif_timeout_count
+ */
+typedef union {
+	struct wci_dif_timeout_count {
+		uint64_t rsvd_z				: 32;	/* 63:32 */
+		uint64_t count				: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_dif_timeout_count_u;
+
+#define	wci_dif_timeout_count_count	\
+	bit.count
+
+
+/*
+ * wci_max
+ */
+typedef union {
+	struct wci_max {
+		uint64_t rsvd_z				: 29;	/* 63:35 */
+		uint64_t sel				: 3;	/* 34:32 */
+		uint64_t value				: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_max_u;
+
+#define	wci_max_sel	\
+	bit.sel
+#define	wci_max_value	\
+	bit.value
+
+
+/*
+ * wci_jnk_route_map0
+ */
+typedef union {
+	struct wci_jnk_route_map0 {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_jnk_route_map0_u;
+
+#define	wci_jnk_route_map0_node15_tlink	\
+	bit.node15_tlink
+#define	wci_jnk_route_map0_node14_tlink	\
+	bit.node14_tlink
+#define	wci_jnk_route_map0_node13_tlink	\
+	bit.node13_tlink
+#define	wci_jnk_route_map0_node12_tlink	\
+	bit.node12_tlink
+#define	wci_jnk_route_map0_node11_tlink	\
+	bit.node11_tlink
+#define	wci_jnk_route_map0_node10_tlink	\
+	bit.node10_tlink
+#define	wci_jnk_route_map0_node9_tlink	\
+	bit.node9_tlink
+#define	wci_jnk_route_map0_node8_tlink	\
+	bit.node8_tlink
+#define	wci_jnk_route_map0_node7_tlink	\
+	bit.node7_tlink
+#define	wci_jnk_route_map0_node6_tlink	\
+	bit.node6_tlink
+#define	wci_jnk_route_map0_node5_tlink	\
+	bit.node5_tlink
+#define	wci_jnk_route_map0_node4_tlink	\
+	bit.node4_tlink
+#define	wci_jnk_route_map0_node3_tlink	\
+	bit.node3_tlink
+#define	wci_jnk_route_map0_node2_tlink	\
+	bit.node2_tlink
+#define	wci_jnk_route_map0_node1_tlink	\
+	bit.node1_tlink
+#define	wci_jnk_route_map0_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_jnk_route_map1
+ */
+typedef union {
+	struct wci_jnk_route_map1 {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_jnk_route_map1_u;
+
+#define	wci_jnk_route_map1_node15_tlink	\
+	bit.node15_tlink
+#define	wci_jnk_route_map1_node14_tlink	\
+	bit.node14_tlink
+#define	wci_jnk_route_map1_node13_tlink	\
+	bit.node13_tlink
+#define	wci_jnk_route_map1_node12_tlink	\
+	bit.node12_tlink
+#define	wci_jnk_route_map1_node11_tlink	\
+	bit.node11_tlink
+#define	wci_jnk_route_map1_node10_tlink	\
+	bit.node10_tlink
+#define	wci_jnk_route_map1_node9_tlink	\
+	bit.node9_tlink
+#define	wci_jnk_route_map1_node8_tlink	\
+	bit.node8_tlink
+#define	wci_jnk_route_map1_node7_tlink	\
+	bit.node7_tlink
+#define	wci_jnk_route_map1_node6_tlink	\
+	bit.node6_tlink
+#define	wci_jnk_route_map1_node5_tlink	\
+	bit.node5_tlink
+#define	wci_jnk_route_map1_node4_tlink	\
+	bit.node4_tlink
+#define	wci_jnk_route_map1_node3_tlink	\
+	bit.node3_tlink
+#define	wci_jnk_route_map1_node2_tlink	\
+	bit.node2_tlink
+#define	wci_jnk_route_map1_node1_tlink	\
+	bit.node1_tlink
+#define	wci_jnk_route_map1_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_stick_rate
+ */
+typedef union {
+	struct wci_stick_rate {
+		uint64_t reset				: 1;	/* 63 */
+		uint64_t cycle_limit_integer		: 15;	/* 62:48 */
+		uint64_t cycle_limit_fraction		: 48;	/* 47:0 */
+	} bit;
+	uint64_t val;
+} wci_stick_rate_u;
+
+#define	wci_stick_rate_reset	\
+	bit.reset
+#define	wci_stick_rate_cycle_limit_integer	\
+	bit.cycle_limit_integer
+#define	wci_stick_rate_cycle_limit_fraction	\
+	bit.cycle_limit_fraction
+
+
+/*
+ * wci_stick
+ */
+typedef union {
+	struct wci_stick {
+		uint64_t count				: 64;	/* 63:0 */
+	} bit;
+	uint64_t val;
+} wci_stick_u;
+
+#define	wci_stick_count	\
+	bit.count
+
+
+/*
+ * wci_misc_ctr
+ */
+typedef union {
+	struct wci_misc_ctr {
+		uint64_t count1				: 32;	/* 63:32 */
+		uint64_t count0				: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_misc_ctr_u;
+
+#define	wci_misc_ctr_count1	\
+	bit.count1
+#define	wci_misc_ctr_count0	\
+	bit.count0
+
+
+/*
+ * wci_misc_ctr_ctl
+ */
+typedef union {
+	struct wci_misc_ctr_ctl {
+		uint64_t rsvd_z				: 43;	/* 63:21 */
+		uint64_t duration_mode			: 1;	/* 20 */
+		uint64_t cnt1_agent_select		: 4;	/* 19:16 */
+		uint64_t cnt1_event_select		: 6;	/* 15:10 */
+		uint64_t cnt0_agent_select		: 4;	/* 9:6 */
+		uint64_t cnt0_event_select		: 6;	/* 5:0 */
+	} bit;
+	uint64_t val;
+} wci_misc_ctr_ctl_u;
+
+#define	wci_misc_ctr_ctl_duration_mode	\
+	bit.duration_mode
+#define	wci_misc_ctr_ctl_cnt1_agent_select	\
+	bit.cnt1_agent_select
+#define	wci_misc_ctr_ctl_cnt1_event_select	\
+	bit.cnt1_event_select
+#define	wci_misc_ctr_ctl_cnt0_agent_select	\
+	bit.cnt0_agent_select
+#define	wci_misc_ctr_ctl_cnt0_event_select	\
+	bit.cnt0_event_select
+
+
+/*
+ * wci_monitor_pins
+ */
+typedef union {
+	struct wci_monitor_pins {
+		uint64_t rsvd_z				: 16;	/* 63:48 */
+		uint64_t monitor_pins			: 16;	/* 47:32 */
+		uint64_t rsvd_y				: 23;	/* 31:9 */
+		uint64_t signal_sel			: 5;	/* 8:4 */
+		uint64_t module_sel			: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_monitor_pins_u;
+
+#define	wci_monitor_pins_monitor_pins	\
+	bit.monitor_pins
+#define	wci_monitor_pins_signal_sel	\
+	bit.signal_sel
+#define	wci_monitor_pins_module_sel	\
+	bit.module_sel
+
+
+/*
+ * wci_sram_config
+ */
+typedef union {
+	struct wci_sram_config {
+		uint64_t rsvd_z				: 45;	/* 63:19 */
+		uint64_t error_threshold		: 5;	/* 18:14 */
+		uint64_t ecc_writeback_disable		: 1;	/* 13 */
+		uint64_t ecc_disable			: 1;	/* 12 */
+		uint64_t parity_disable			: 1;	/* 11 */
+		uint64_t use_ga2lpa			: 1;	/* 10 */
+		uint64_t use_directory			: 1;	/* 9 */
+		uint64_t dir_stripe			: 2;	/* 8:7 */
+		uint64_t rsvd_y				: 2;	/* 6:5 */
+		uint64_t sram_size			: 3;	/* 4:2 */
+		uint64_t sram_size_pins			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_sram_config_u;
+
+#define	wci_sram_config_error_threshold	\
+	bit.error_threshold
+#define	wci_sram_config_ecc_writeback_disable	\
+	bit.ecc_writeback_disable
+#define	wci_sram_config_ecc_disable	\
+	bit.ecc_disable
+#define	wci_sram_config_parity_disable	\
+	bit.parity_disable
+#define	wci_sram_config_use_ga2lpa	\
+	bit.use_ga2lpa
+#define	wci_sram_config_use_directory	\
+	bit.use_directory
+#define	wci_sram_config_dir_stripe	\
+	bit.dir_stripe
+#define	wci_sram_config_sram_size	\
+	bit.sram_size
+#define	wci_sram_config_sram_size_pins	\
+	bit.sram_size_pins
+
+
+/*
+ * wci_cluster_members_bits
+ */
+typedef union {
+	struct wci_cluster_members_bits {
+		uint64_t mask				: 64;	/* 63:0 */
+	} bit;
+	uint64_t val;
+} wci_cluster_members_bits_u;
+
+#define	wci_cluster_members_bits_mask	\
+	bit.mask
+
+
+/*
+ * wci_nc_slice_config_array
+ */
+typedef union {
+	struct wci_nc_slice_config_array {
+		uint64_t config				: 64;	/* 63:0 */
+	} bit;
+	uint64_t val;
+} wci_nc_slice_config_array_u;
+
+#define	wci_nc_slice_config_array_config	\
+	bit.config
+
+
+/*
+ * wci_cluster_ctr_ctl
+ */
+typedef union {
+	struct wci_cluster_ctr_ctl {
+		uint64_t rsvd_z				: 55;	/* 63:9 */
+		uint64_t enable_all			: 1;	/* 8 */
+		uint64_t cnt1_received_interrupt	: 1;	/* 7 */
+		uint64_t cnt1_received_atomic		: 1;	/* 6 */
+		uint64_t cnt1_received_cacheable_read	: 1;	/* 5 */
+		uint64_t cnt1_received_cacheable_write	: 1;	/* 4 */
+		uint64_t cnt0_received_interrupt	: 1;	/* 3 */
+		uint64_t cnt0_received_atomic		: 1;	/* 2 */
+		uint64_t cnt0_received_cacheable_read	: 1;	/* 1 */
+		uint64_t cnt0_received_cacheable_write	: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_cluster_ctr_ctl_u;
+
+#define	wci_cluster_ctr_ctl_enable_all	\
+	bit.enable_all
+#define	wci_cluster_ctr_ctl_cnt1_received_interrupt	\
+	bit.cnt1_received_interrupt
+#define	wci_cluster_ctr_ctl_cnt1_received_atomic	\
+	bit.cnt1_received_atomic
+#define	wci_cluster_ctr_ctl_cnt1_received_cacheable_read	\
+	bit.cnt1_received_cacheable_read
+#define	wci_cluster_ctr_ctl_cnt1_received_cacheable_write	\
+	bit.cnt1_received_cacheable_write
+#define	wci_cluster_ctr_ctl_cnt0_received_interrupt	\
+	bit.cnt0_received_interrupt
+#define	wci_cluster_ctr_ctl_cnt0_received_atomic	\
+	bit.cnt0_received_atomic
+#define	wci_cluster_ctr_ctl_cnt0_received_cacheable_read	\
+	bit.cnt0_received_cacheable_read
+#define	wci_cluster_ctr_ctl_cnt0_received_cacheable_write	\
+	bit.cnt0_received_cacheable_write
+
+
+/*
+ * wci_sram_status
+ */
+typedef union {
+	struct wci_sram_status {
+		uint64_t rsvd_z				: 44;	/* 63:20 */
+		uint64_t sticky_error_19		: 1;	/* 19 */
+		uint64_t sticky_error_18		: 1;	/* 18 */
+		uint64_t sticky_error_17		: 1;	/* 17 */
+		uint64_t sticky_error_16		: 1;	/* 16 */
+		uint64_t sticky_error_15		: 1;	/* 15 */
+		uint64_t sticky_error_14		: 1;	/* 14 */
+		uint64_t sticky_error_13		: 1;	/* 13 */
+		uint64_t sticky_error_12		: 1;	/* 12 */
+		uint64_t sticky_error_11		: 1;	/* 11 */
+		uint64_t sticky_error_10		: 1;	/* 10 */
+		uint64_t sticky_error_9			: 1;	/* 9 */
+		uint64_t sticky_error_8			: 1;	/* 8 */
+		uint64_t sticky_error_7			: 1;	/* 7 */
+		uint64_t sticky_error_6			: 1;	/* 6 */
+		uint64_t sticky_error_5			: 1;	/* 5 */
+		uint64_t sticky_error_4			: 1;	/* 4 */
+		uint64_t sticky_error_3			: 1;	/* 3 */
+		uint64_t sticky_error_2			: 1;	/* 2 */
+		uint64_t sticky_error_1			: 1;	/* 1 */
+		uint64_t sticky_error_0			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sram_status_u;
+
+#define	wci_sram_status_sticky_error_19	\
+	bit.sticky_error_19
+#define	wci_sram_status_sticky_error_18	\
+	bit.sticky_error_18
+#define	wci_sram_status_sticky_error_17	\
+	bit.sticky_error_17
+#define	wci_sram_status_sticky_error_16	\
+	bit.sticky_error_16
+#define	wci_sram_status_sticky_error_15	\
+	bit.sticky_error_15
+#define	wci_sram_status_sticky_error_14	\
+	bit.sticky_error_14
+#define	wci_sram_status_sticky_error_13	\
+	bit.sticky_error_13
+#define	wci_sram_status_sticky_error_12	\
+	bit.sticky_error_12
+#define	wci_sram_status_sticky_error_11	\
+	bit.sticky_error_11
+#define	wci_sram_status_sticky_error_10	\
+	bit.sticky_error_10
+#define	wci_sram_status_sticky_error_9	\
+	bit.sticky_error_9
+#define	wci_sram_status_sticky_error_8	\
+	bit.sticky_error_8
+#define	wci_sram_status_sticky_error_7	\
+	bit.sticky_error_7
+#define	wci_sram_status_sticky_error_6	\
+	bit.sticky_error_6
+#define	wci_sram_status_sticky_error_5	\
+	bit.sticky_error_5
+#define	wci_sram_status_sticky_error_4	\
+	bit.sticky_error_4
+#define	wci_sram_status_sticky_error_3	\
+	bit.sticky_error_3
+#define	wci_sram_status_sticky_error_2	\
+	bit.sticky_error_2
+#define	wci_sram_status_sticky_error_1	\
+	bit.sticky_error_1
+#define	wci_sram_status_sticky_error_0	\
+	bit.sticky_error_0
+
+
+/*
+ * wci_sram_ce_count
+ */
+typedef union {
+	struct wci_sram_ce_count {
+		uint64_t rsvd_z				: 56;	/* 63:8 */
+		uint64_t ce_count			: 8;	/* 7:0 */
+	} bit;
+	uint64_t val;
+} wci_sram_ce_count_u;
+
+#define	wci_sram_ce_count_ce_count	\
+	bit.ce_count
+
+
+/*
+ * wci_sram_ecc_address
+ */
+typedef union {
+	struct wci_sram_ecc_address {
+		uint64_t rsvd_z				: 31;	/* 63:33 */
+		uint64_t ce				: 1;	/* 32 */
+		uint64_t addr_error			: 1;	/* 31 */
+		uint64_t syndrome			: 7;	/* 30:24 */
+		uint64_t address			: 24;	/* 23:0 */
+	} bit;
+	uint64_t val;
+} wci_sram_ecc_address_u;
+
+#define	wci_sram_ecc_address_ce	\
+	bit.ce
+#define	wci_sram_ecc_address_addr_error	\
+	bit.addr_error
+#define	wci_sram_ecc_address_syndrome	\
+	bit.syndrome
+#define	wci_sram_ecc_address_address	\
+	bit.address
+
+
+/*
+ * wci_cci_esr
+ */
+typedef union {
+	struct wci_cci_esr {
+		uint64_t rsvd_z				: 42;	/* 63:22 */
+		uint64_t acc_parity			: 1;	/* 21 */
+		uint64_t acc_threshold			: 1;	/* 20 */
+		uint64_t acc_sram_ae			: 1;	/* 19 */
+		uint64_t acc_sram_ue			: 1;	/* 18 */
+		uint64_t acc_sram_ce			: 1;	/* 17 */
+		uint64_t acc_ce_count_zero		: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t rsvd_y				: 9;	/* 14:6 */
+		uint64_t parity				: 1;	/* 5 */
+		uint64_t threshold			: 1;	/* 4 */
+		uint64_t sram_ae			: 1;	/* 3 */
+		uint64_t sram_ue			: 1;	/* 2 */
+		uint64_t sram_ce			: 1;	/* 1 */
+		uint64_t ce_count_zero			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_cci_esr_u;
+
+#define	wci_cci_esr_acc_parity	\
+	bit.acc_parity
+#define	wci_cci_esr_acc_threshold	\
+	bit.acc_threshold
+#define	wci_cci_esr_acc_sram_ae	\
+	bit.acc_sram_ae
+#define	wci_cci_esr_acc_sram_ue	\
+	bit.acc_sram_ue
+#define	wci_cci_esr_acc_sram_ce	\
+	bit.acc_sram_ce
+#define	wci_cci_esr_acc_ce_count_zero	\
+	bit.acc_ce_count_zero
+#define	wci_cci_esr_first_error	\
+	bit.first_error
+#define	wci_cci_esr_parity	\
+	bit.parity
+#define	wci_cci_esr_threshold	\
+	bit.threshold
+#define	wci_cci_esr_sram_ae	\
+	bit.sram_ae
+#define	wci_cci_esr_sram_ue	\
+	bit.sram_ue
+#define	wci_cci_esr_sram_ce	\
+	bit.sram_ce
+#define	wci_cci_esr_ce_count_zero	\
+	bit.ce_count_zero
+
+
+/*
+ * wci_cci_esr_mask
+ */
+typedef union {
+	struct wci_cci_esr_mask {
+		uint64_t rsvd_z				: 58;	/* 63:6 */
+		uint64_t parity				: 1;	/* 5 */
+		uint64_t threshold			: 1;	/* 4 */
+		uint64_t sram_ae			: 1;	/* 3 */
+		uint64_t sram_ue			: 1;	/* 2 */
+		uint64_t sram_ce			: 1;	/* 1 */
+		uint64_t ce_count_zero			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_cci_esr_mask_u;
+
+#define	wci_cci_esr_mask_parity	\
+	bit.parity
+#define	wci_cci_esr_mask_threshold	\
+	bit.threshold
+#define	wci_cci_esr_mask_sram_ae	\
+	bit.sram_ae
+#define	wci_cci_esr_mask_sram_ue	\
+	bit.sram_ue
+#define	wci_cci_esr_mask_sram_ce	\
+	bit.sram_ce
+#define	wci_cci_esr_mask_ce_count_zero	\
+	bit.ce_count_zero
+
+
+/*
+ * wci_cci_route_map0
+ */
+typedef union {
+	struct wci_cci_route_map0 {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_cci_route_map0_u;
+
+#define	wci_cci_route_map0_node15_tlink	\
+	bit.node15_tlink
+#define	wci_cci_route_map0_node14_tlink	\
+	bit.node14_tlink
+#define	wci_cci_route_map0_node13_tlink	\
+	bit.node13_tlink
+#define	wci_cci_route_map0_node12_tlink	\
+	bit.node12_tlink
+#define	wci_cci_route_map0_node11_tlink	\
+	bit.node11_tlink
+#define	wci_cci_route_map0_node10_tlink	\
+	bit.node10_tlink
+#define	wci_cci_route_map0_node9_tlink	\
+	bit.node9_tlink
+#define	wci_cci_route_map0_node8_tlink	\
+	bit.node8_tlink
+#define	wci_cci_route_map0_node7_tlink	\
+	bit.node7_tlink
+#define	wci_cci_route_map0_node6_tlink	\
+	bit.node6_tlink
+#define	wci_cci_route_map0_node5_tlink	\
+	bit.node5_tlink
+#define	wci_cci_route_map0_node4_tlink	\
+	bit.node4_tlink
+#define	wci_cci_route_map0_node3_tlink	\
+	bit.node3_tlink
+#define	wci_cci_route_map0_node2_tlink	\
+	bit.node2_tlink
+#define	wci_cci_route_map0_node1_tlink	\
+	bit.node1_tlink
+#define	wci_cci_route_map0_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_cci_route_map1
+ */
+typedef union {
+	struct wci_cci_route_map1 {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_cci_route_map1_u;
+
+#define	wci_cci_route_map1_node15_tlink	\
+	bit.node15_tlink
+#define	wci_cci_route_map1_node14_tlink	\
+	bit.node14_tlink
+#define	wci_cci_route_map1_node13_tlink	\
+	bit.node13_tlink
+#define	wci_cci_route_map1_node12_tlink	\
+	bit.node12_tlink
+#define	wci_cci_route_map1_node11_tlink	\
+	bit.node11_tlink
+#define	wci_cci_route_map1_node10_tlink	\
+	bit.node10_tlink
+#define	wci_cci_route_map1_node9_tlink	\
+	bit.node9_tlink
+#define	wci_cci_route_map1_node8_tlink	\
+	bit.node8_tlink
+#define	wci_cci_route_map1_node7_tlink	\
+	bit.node7_tlink
+#define	wci_cci_route_map1_node6_tlink	\
+	bit.node6_tlink
+#define	wci_cci_route_map1_node5_tlink	\
+	bit.node5_tlink
+#define	wci_cci_route_map1_node4_tlink	\
+	bit.node4_tlink
+#define	wci_cci_route_map1_node3_tlink	\
+	bit.node3_tlink
+#define	wci_cci_route_map1_node2_tlink	\
+	bit.node2_tlink
+#define	wci_cci_route_map1_node1_tlink	\
+	bit.node1_tlink
+#define	wci_cci_route_map1_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_cluster_write_lockout
+ */
+typedef union {
+	struct wci_cluster_write_lockout {
+		uint64_t mask				: 64;	/* 63:0 */
+	} bit;
+	uint64_t val;
+} wci_cluster_write_lockout_u;
+
+#define	wci_cluster_write_lockout_mask	\
+	bit.mask
+
+
+/*
+ * wci_cluster_config
+ */
+typedef union {
+	struct wci_cluster_config {
+		uint64_t rsvd_z				: 61;	/* 63:3 */
+		uint64_t in_an_ssm			: 1;	/* 2 */
+		uint64_t bad_ecc_on_write_error		: 1;	/* 1 */
+		uint64_t allow_multiple_hops		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_cluster_config_u;
+
+#define	wci_cluster_config_in_an_ssm	\
+	bit.in_an_ssm
+#define	wci_cluster_config_bad_ecc_on_write_error	\
+	bit.bad_ecc_on_write_error
+#define	wci_cluster_config_allow_multiple_hops	\
+	bit.allow_multiple_hops
+
+
+/*
+ * wci_ca_freeze
+ */
+typedef union {
+	struct wci_ca_freeze {
+		uint64_t rsvd_z				: 32;	/* 63:32 */
+		uint64_t vector				: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_ca_freeze_u;
+
+#define	wci_ca_freeze_vector	\
+	bit.vector
+
+
+/*
+ * wci_ca_busy
+ */
+typedef union {
+	struct wci_ca_busy {
+		uint64_t rsvd_z				: 32;	/* 63:32 */
+		uint64_t vector				: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_ca_busy_u;
+
+#define	wci_ca_busy_vector	\
+	bit.vector
+
+
+/*
+ * wci_ca_first_packet_0
+ */
+typedef union {
+	struct wci_ca_first_packet_0 {
+		uint64_t addr				: 6;	/* 63:58 */
+		uint64_t rsvd_z				: 13;	/* 57:45 */
+		uint64_t rtransid			: 9;	/* 44:36 */
+		uint64_t scnid				: 8;	/* 35:28 */
+		uint64_t rsvd_y				: 8;	/* 27:20 */
+		uint64_t rtid				: 5;	/* 19:15 */
+		uint64_t snid				: 4;	/* 14:11 */
+		uint64_t opcode				: 6;	/* 10:5 */
+		uint64_t stripe				: 1;	/* 4 */
+		uint64_t dnid				: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_ca_first_packet_0_u;
+
+#define	wci_ca_first_packet_0_addr	\
+	bit.addr
+#define	wci_ca_first_packet_0_rtransid	\
+	bit.rtransid
+#define	wci_ca_first_packet_0_scnid	\
+	bit.scnid
+#define	wci_ca_first_packet_0_rtid	\
+	bit.rtid
+#define	wci_ca_first_packet_0_snid	\
+	bit.snid
+#define	wci_ca_first_packet_0_opcode	\
+	bit.opcode
+#define	wci_ca_first_packet_0_stripe	\
+	bit.stripe
+#define	wci_ca_first_packet_0_dnid	\
+	bit.dnid
+
+
+/*
+ * wci_ca_first_packet_1
+ */
+typedef union {
+	struct wci_ca_first_packet_1 {
+		uint64_t rsvd_z				: 33;	/* 63:31 */
+		uint64_t addr				: 31;	/* 30:0 */
+	} bit;
+	uint64_t val;
+} wci_ca_first_packet_1_u;
+
+#define	wci_ca_first_packet_1_addr	\
+	bit.addr
+
+
+/*
+ * wci_ca_ecc_address
+ */
+typedef union {
+	struct wci_ca_ecc_address {
+		uint64_t data				: 1;	/* 63 */
+		uint64_t ue				: 1;	/* 62 */
+		uint64_t passthru			: 1;	/* 61 */
+		uint64_t rsvd_z				: 24;	/* 60:37 */
+		uint64_t addr				: 37;	/* 36:0 */
+	} bit;
+	uint64_t val;
+} wci_ca_ecc_address_u;
+
+#define	wci_ca_ecc_address_data	\
+	bit.data
+#define	wci_ca_ecc_address_ue	\
+	bit.ue
+#define	wci_ca_ecc_address_passthru	\
+	bit.passthru
+#define	wci_ca_ecc_address_addr	\
+	bit.addr
+
+
+/*
+ * wci_ca_error_transaction
+ */
+typedef union {
+	struct wci_ca_error_transaction {
+		uint64_t status				: 4;	/* 63:60 */
+		uint64_t esr_reg			: 1;	/* 59 */
+		uint64_t esr_index			: 4;	/* 58:55 */
+		uint64_t ctid				: 5;	/* 54:50 */
+		uint64_t targid				: 9;	/* 49:41 */
+		uint64_t second_atransid		: 4;	/* 40:37 */
+		uint64_t first_atransid			: 4;	/* 36:33 */
+		uint64_t cmd_grant_1			: 1;	/* 32 */
+		uint64_t cmd_grant_2			: 1;	/* 31 */
+		uint64_t reissue_pending_1		: 1;	/* 30 */
+		uint64_t reissue_pending_2		: 1;	/* 29 */
+		uint64_t transid_released		: 1;	/* 28 */
+		uint64_t const_grant			: 1;	/* 27 */
+		uint64_t map_grant			: 1;	/* 26 */
+		uint64_t map_queued			: 1;	/* 25 */
+		uint64_t reuse_timeout			: 1;	/* 24 */
+		uint64_t data_timeout			: 1;	/* 23 */
+		uint64_t aphase_timeout			: 1;	/* 22 */
+		uint64_t pkt_sent			: 1;	/* 21 */
+		uint64_t pkt_queued			: 1;	/* 20 */
+		uint64_t cpi_inval			: 1;	/* 19 */
+		uint64_t cpi_queued			: 1;	/* 18 */
+		uint64_t cpi_err			: 1;	/* 17 */
+		uint64_t cpi_rcv2			: 1;	/* 16 */
+		uint64_t cpi_rcv1			: 1;	/* 15 */
+		uint64_t dc_atom_err			: 1;	/* 14 */
+		uint64_t dc_snd2			: 1;	/* 13 */
+		uint64_t dc_rcv2			: 1;	/* 12 */
+		uint64_t dc_err1			: 1;	/* 11 */
+		uint64_t pull_late			: 1;	/* 10 */
+		uint64_t pull_timeout			: 1;	/* 9 */
+		uint64_t pull_cleared			: 1;	/* 8 */
+		uint64_t pull_err			: 1;	/* 7 */
+		uint64_t pull_ok			: 1;	/* 6 */
+		uint64_t snoop_late			: 1;	/* 5 */
+		uint64_t snoop2				: 2;	/* 4:3 */
+		uint64_t snoop1				: 3;	/* 2:0 */
+	} bit;
+	uint64_t val;
+} wci_ca_error_transaction_u;
+
+#define	wci_ca_error_transaction_status	\
+	bit.status
+#define	wci_ca_error_transaction_esr_reg	\
+	bit.esr_reg
+#define	wci_ca_error_transaction_esr_index	\
+	bit.esr_index
+#define	wci_ca_error_transaction_ctid	\
+	bit.ctid
+#define	wci_ca_error_transaction_targid	\
+	bit.targid
+#define	wci_ca_error_transaction_second_atransid	\
+	bit.second_atransid
+#define	wci_ca_error_transaction_first_atransid	\
+	bit.first_atransid
+#define	wci_ca_error_transaction_cmd_grant_1	\
+	bit.cmd_grant_1
+#define	wci_ca_error_transaction_cmd_grant_2	\
+	bit.cmd_grant_2
+#define	wci_ca_error_transaction_reissue_pending_1	\
+	bit.reissue_pending_1
+#define	wci_ca_error_transaction_reissue_pending_2	\
+	bit.reissue_pending_2
+#define	wci_ca_error_transaction_transid_released	\
+	bit.transid_released
+#define	wci_ca_error_transaction_const_grant	\
+	bit.const_grant
+#define	wci_ca_error_transaction_map_grant	\
+	bit.map_grant
+#define	wci_ca_error_transaction_map_queued	\
+	bit.map_queued
+#define	wci_ca_error_transaction_reuse_timeout	\
+	bit.reuse_timeout
+#define	wci_ca_error_transaction_data_timeout	\
+	bit.data_timeout
+#define	wci_ca_error_transaction_aphase_timeout	\
+	bit.aphase_timeout
+#define	wci_ca_error_transaction_pkt_sent	\
+	bit.pkt_sent
+#define	wci_ca_error_transaction_pkt_queued	\
+	bit.pkt_queued
+#define	wci_ca_error_transaction_cpi_inval	\
+	bit.cpi_inval
+#define	wci_ca_error_transaction_cpi_queued	\
+	bit.cpi_queued
+#define	wci_ca_error_transaction_cpi_err	\
+	bit.cpi_err
+#define	wci_ca_error_transaction_cpi_rcv2	\
+	bit.cpi_rcv2
+#define	wci_ca_error_transaction_cpi_rcv1	\
+	bit.cpi_rcv1
+#define	wci_ca_error_transaction_dc_atom_err	\
+	bit.dc_atom_err
+#define	wci_ca_error_transaction_dc_snd2	\
+	bit.dc_snd2
+#define	wci_ca_error_transaction_dc_rcv2	\
+	bit.dc_rcv2
+#define	wci_ca_error_transaction_dc_err1	\
+	bit.dc_err1
+#define	wci_ca_error_transaction_pull_late	\
+	bit.pull_late
+#define	wci_ca_error_transaction_pull_timeout	\
+	bit.pull_timeout
+#define	wci_ca_error_transaction_pull_cleared	\
+	bit.pull_cleared
+#define	wci_ca_error_transaction_pull_err	\
+	bit.pull_err
+#define	wci_ca_error_transaction_pull_ok	\
+	bit.pull_ok
+#define	wci_ca_error_transaction_snoop_late	\
+	bit.snoop_late
+#define	wci_ca_error_transaction_snoop2	\
+	bit.snoop2
+#define	wci_ca_error_transaction_snoop1	\
+	bit.snoop1
+
+
+/*
+ * wci_ca_timeout_config
+ */
+typedef union {
+	struct wci_ca_timeout_config {
+		uint64_t rsvd_z				: 6;	/* 63:58 */
+		uint64_t dphase_disable			: 1;	/* 57 */
+		uint64_t dphase_freeze			: 1;	/* 56 */
+		uint64_t rsvd_y				: 2;	/* 55:54 */
+		uint64_t dphase_dest_mag		: 2;	/* 53:52 */
+		uint64_t dphase_dest_val		: 8;	/* 51:44 */
+		uint64_t rsvd_x				: 2;	/* 43:42 */
+		uint64_t dphase_pass_mag		: 2;	/* 41:40 */
+		uint64_t dphase_pass_val		: 8;	/* 39:32 */
+		uint64_t rsvd_w				: 2;	/* 31:30 */
+		uint64_t aphase_disable			: 1;	/* 29 */
+		uint64_t aphase_freeze			: 1;	/* 28 */
+		uint64_t rsvd_v				: 2;	/* 27:26 */
+		uint64_t aphase_mag			: 2;	/* 25:24 */
+		uint64_t aphase_val			: 8;	/* 23:16 */
+		uint64_t rsvd_u				: 1;	/* 15 */
+		uint64_t reuse_disable			: 1;	/* 14 */
+		uint64_t reuse_freeze			: 1;	/* 13 */
+		uint64_t reuse_mag			: 2;	/* 12:11 */
+		uint64_t reuse_val			: 11;	/* 10:0 */
+	} bit;
+	uint64_t val;
+} wci_ca_timeout_config_u;
+
+#define	wci_ca_timeout_config_dphase_disable	\
+	bit.dphase_disable
+#define	wci_ca_timeout_config_dphase_freeze	\
+	bit.dphase_freeze
+#define	wci_ca_timeout_config_dphase_dest_mag	\
+	bit.dphase_dest_mag
+#define	wci_ca_timeout_config_dphase_dest_val	\
+	bit.dphase_dest_val
+#define	wci_ca_timeout_config_dphase_pass_mag	\
+	bit.dphase_pass_mag
+#define	wci_ca_timeout_config_dphase_pass_val	\
+	bit.dphase_pass_val
+#define	wci_ca_timeout_config_aphase_disable	\
+	bit.aphase_disable
+#define	wci_ca_timeout_config_aphase_freeze	\
+	bit.aphase_freeze
+#define	wci_ca_timeout_config_aphase_mag	\
+	bit.aphase_mag
+#define	wci_ca_timeout_config_aphase_val	\
+	bit.aphase_val
+#define	wci_ca_timeout_config_reuse_disable	\
+	bit.reuse_disable
+#define	wci_ca_timeout_config_reuse_freeze	\
+	bit.reuse_freeze
+#define	wci_ca_timeout_config_reuse_mag	\
+	bit.reuse_mag
+#define	wci_ca_timeout_config_reuse_val	\
+	bit.reuse_val
+
+
+/*
+ * wci_ca_config
+ */
+typedef union {
+	struct wci_ca_config {
+		uint64_t rsvd_z				: 58;	/* 63:6 */
+		uint64_t cluster_disable		: 1;	/* 5 */
+		uint64_t reuse_timeout_limit		: 5;	/* 4:0 */
+	} bit;
+	uint64_t val;
+} wci_ca_config_u;
+
+#define	wci_ca_config_cluster_disable	\
+	bit.cluster_disable
+#define	wci_ca_config_reuse_timeout_limit	\
+	bit.reuse_timeout_limit
+
+
+/*
+ * wci_ca_esr_0
+ */
+typedef union {
+	struct wci_ca_esr_0 {
+		uint64_t rsvd_z				: 33;	/* 63:31 */
+		uint64_t acc_unexpect_cpi_ack		: 1;	/* 30 */
+		uint64_t acc_unexpect_dc_ack		: 1;	/* 29 */
+		uint64_t acc_unexpect_pull		: 1;	/* 28 */
+		uint64_t acc_unexpect_reissue		: 1;	/* 27 */
+		uint64_t acc_atomic_map_mismatch	: 1;	/* 26 */
+		uint64_t acc_unmapped			: 1;	/* 25 */
+		uint64_t acc_uncorrectable_mtag_error	: 1;	/* 24 */
+		uint64_t acc_uncorrectable_data_error	: 1;	/* 23 */
+		uint64_t acc_correctable_mtag_error	: 1;	/* 22 */
+		uint64_t acc_correctable_data_error	: 1;	/* 21 */
+		uint64_t acc_dstat_inconsistent		: 1;	/* 20 */
+		uint64_t acc_mtag_mismatch_within_hcl	: 1;	/* 19 */
+		uint64_t acc_mtag_mismatch_between_hcls	: 1;	/* 18 */
+		uint64_t acc_remote_timeout		: 1;	/* 17 */
+		uint64_t acc_local_timeout		: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t unexpect_cpi_ack		: 1;	/* 14 */
+		uint64_t unexpect_dc_ack		: 1;	/* 13 */
+		uint64_t unexpect_pull			: 1;	/* 12 */
+		uint64_t unexpect_reissue		: 1;	/* 11 */
+		uint64_t atomic_map_mismatch		: 1;	/* 10 */
+		uint64_t unmapped			: 1;	/* 9 */
+		uint64_t uncorrectable_mtag_error	: 1;	/* 8 */
+		uint64_t uncorrectable_data_error	: 1;	/* 7 */
+		uint64_t correctable_mtag_error		: 1;	/* 6 */
+		uint64_t correctable_data_error		: 1;	/* 5 */
+		uint64_t dstat_inconsistent		: 1;	/* 4 */
+		uint64_t mtag_mismatch_within_hcl	: 1;	/* 3 */
+		uint64_t mtag_mismatch_between_hcls	: 1;	/* 2 */
+		uint64_t remote_timeout			: 1;	/* 1 */
+		uint64_t local_timeout			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_ca_esr_0_u;
+
+#define	wci_ca_esr_0_acc_unexpect_cpi_ack	\
+	bit.acc_unexpect_cpi_ack
+#define	wci_ca_esr_0_acc_unexpect_dc_ack	\
+	bit.acc_unexpect_dc_ack
+#define	wci_ca_esr_0_acc_unexpect_pull	\
+	bit.acc_unexpect_pull
+#define	wci_ca_esr_0_acc_unexpect_reissue	\
+	bit.acc_unexpect_reissue
+#define	wci_ca_esr_0_acc_atomic_map_mismatch	\
+	bit.acc_atomic_map_mismatch
+#define	wci_ca_esr_0_acc_unmapped	\
+	bit.acc_unmapped
+#define	wci_ca_esr_0_acc_uncorrectable_mtag_error	\
+	bit.acc_uncorrectable_mtag_error
+#define	wci_ca_esr_0_acc_uncorrectable_data_error	\
+	bit.acc_uncorrectable_data_error
+#define	wci_ca_esr_0_acc_correctable_mtag_error	\
+	bit.acc_correctable_mtag_error
+#define	wci_ca_esr_0_acc_correctable_data_error	\
+	bit.acc_correctable_data_error
+#define	wci_ca_esr_0_acc_dstat_inconsistent	\
+	bit.acc_dstat_inconsistent
+#define	wci_ca_esr_0_acc_mtag_mismatch_within_hcl	\
+	bit.acc_mtag_mismatch_within_hcl
+#define	wci_ca_esr_0_acc_mtag_mismatch_between_hcls	\
+	bit.acc_mtag_mismatch_between_hcls
+#define	wci_ca_esr_0_acc_remote_timeout	\
+	bit.acc_remote_timeout
+#define	wci_ca_esr_0_acc_local_timeout	\
+	bit.acc_local_timeout
+#define	wci_ca_esr_0_first_error	\
+	bit.first_error
+#define	wci_ca_esr_0_unexpect_cpi_ack	\
+	bit.unexpect_cpi_ack
+#define	wci_ca_esr_0_unexpect_dc_ack	\
+	bit.unexpect_dc_ack
+#define	wci_ca_esr_0_unexpect_pull	\
+	bit.unexpect_pull
+#define	wci_ca_esr_0_unexpect_reissue	\
+	bit.unexpect_reissue
+#define	wci_ca_esr_0_atomic_map_mismatch	\
+	bit.atomic_map_mismatch
+#define	wci_ca_esr_0_unmapped	\
+	bit.unmapped
+#define	wci_ca_esr_0_uncorrectable_mtag_error	\
+	bit.uncorrectable_mtag_error
+#define	wci_ca_esr_0_uncorrectable_data_error	\
+	bit.uncorrectable_data_error
+#define	wci_ca_esr_0_correctable_mtag_error	\
+	bit.correctable_mtag_error
+#define	wci_ca_esr_0_correctable_data_error	\
+	bit.correctable_data_error
+#define	wci_ca_esr_0_dstat_inconsistent	\
+	bit.dstat_inconsistent
+#define	wci_ca_esr_0_mtag_mismatch_within_hcl	\
+	bit.mtag_mismatch_within_hcl
+#define	wci_ca_esr_0_mtag_mismatch_between_hcls	\
+	bit.mtag_mismatch_between_hcls
+#define	wci_ca_esr_0_remote_timeout	\
+	bit.remote_timeout
+#define	wci_ca_esr_0_local_timeout	\
+	bit.local_timeout
+
+
+/*
+ * wci_ca_esr_1
+ */
+typedef union {
+	struct wci_ca_esr_1 {
+		uint64_t rsvd_z				: 43;	/* 63:21 */
+		uint64_t acc_qlimit_timeout		: 1;	/* 20 */
+		uint64_t acc_internal_error		: 1;	/* 19 */
+		uint64_t acc_cmmu_ecc_error		: 1;	/* 18 */
+		uint64_t acc_wrong_cmd			: 1;	/* 17 */
+		uint64_t acc_data_phase_timeout		: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t rsvd_y				: 10;	/* 14:5 */
+		uint64_t qlimit_timeout			: 1;	/* 4 */
+		uint64_t internal_error			: 1;	/* 3 */
+		uint64_t cmmu_ecc_error			: 1;	/* 2 */
+		uint64_t wrong_cmd			: 1;	/* 1 */
+		uint64_t data_phase_timeout		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_ca_esr_1_u;
+
+#define	wci_ca_esr_1_acc_qlimit_timeout	\
+	bit.acc_qlimit_timeout
+#define	wci_ca_esr_1_acc_internal_error	\
+	bit.acc_internal_error
+#define	wci_ca_esr_1_acc_cmmu_ecc_error	\
+	bit.acc_cmmu_ecc_error
+#define	wci_ca_esr_1_acc_wrong_cmd	\
+	bit.acc_wrong_cmd
+#define	wci_ca_esr_1_acc_data_phase_timeout	\
+	bit.acc_data_phase_timeout
+#define	wci_ca_esr_1_first_error	\
+	bit.first_error
+#define	wci_ca_esr_1_qlimit_timeout	\
+	bit.qlimit_timeout
+#define	wci_ca_esr_1_internal_error	\
+	bit.internal_error
+#define	wci_ca_esr_1_cmmu_ecc_error	\
+	bit.cmmu_ecc_error
+#define	wci_ca_esr_1_wrong_cmd	\
+	bit.wrong_cmd
+#define	wci_ca_esr_1_data_phase_timeout	\
+	bit.data_phase_timeout
+
+
+/*
+ * wci_ca_esr_mask
+ */
+typedef union {
+	struct wci_ca_esr_mask {
+		uint64_t rsvd_z				: 43;	/* 63:21 */
+		uint64_t qlimit_timeout			: 1;	/* 20 */
+		uint64_t internal_error			: 1;	/* 19 */
+		uint64_t cmmu_ecc_error			: 1;	/* 18 */
+		uint64_t wrong_cmd			: 1;	/* 17 */
+		uint64_t data_phase_timeout		: 1;	/* 16 */
+		uint64_t rsvd_y				: 1;	/* 15 */
+		uint64_t unexpect_cpi_ack		: 1;	/* 14 */
+		uint64_t unexpect_dc_ack		: 1;	/* 13 */
+		uint64_t unexpect_pull			: 1;	/* 12 */
+		uint64_t unexpect_reissue		: 1;	/* 11 */
+		uint64_t atomic_map_mismatch		: 1;	/* 10 */
+		uint64_t unmapped			: 1;	/* 9 */
+		uint64_t uncorrectable_mtag_error	: 1;	/* 8 */
+		uint64_t uncorrectable_data_error	: 1;	/* 7 */
+		uint64_t correctable_mtag_error		: 1;	/* 6 */
+		uint64_t correctable_data_error		: 1;	/* 5 */
+		uint64_t dstat_inconsistent		: 1;	/* 4 */
+		uint64_t mtag_mismatch_within_hcl	: 1;	/* 3 */
+		uint64_t mtag_mismatch_between_hcls	: 1;	/* 2 */
+		uint64_t remote_timeout			: 1;	/* 1 */
+		uint64_t local_timeout			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_ca_esr_mask_u;
+
+#define	wci_ca_esr_mask_qlimit_timeout	\
+	bit.qlimit_timeout
+#define	wci_ca_esr_mask_internal_error	\
+	bit.internal_error
+#define	wci_ca_esr_mask_cmmu_ecc_error	\
+	bit.cmmu_ecc_error
+#define	wci_ca_esr_mask_wrong_cmd	\
+	bit.wrong_cmd
+#define	wci_ca_esr_mask_data_phase_timeout	\
+	bit.data_phase_timeout
+#define	wci_ca_esr_mask_unexpect_cpi_ack	\
+	bit.unexpect_cpi_ack
+#define	wci_ca_esr_mask_unexpect_dc_ack	\
+	bit.unexpect_dc_ack
+#define	wci_ca_esr_mask_unexpect_pull	\
+	bit.unexpect_pull
+#define	wci_ca_esr_mask_unexpect_reissue	\
+	bit.unexpect_reissue
+#define	wci_ca_esr_mask_atomic_map_mismatch	\
+	bit.atomic_map_mismatch
+#define	wci_ca_esr_mask_unmapped	\
+	bit.unmapped
+#define	wci_ca_esr_mask_uncorrectable_mtag_error	\
+	bit.uncorrectable_mtag_error
+#define	wci_ca_esr_mask_uncorrectable_data_error	\
+	bit.uncorrectable_data_error
+#define	wci_ca_esr_mask_correctable_mtag_error	\
+	bit.correctable_mtag_error
+#define	wci_ca_esr_mask_correctable_data_error	\
+	bit.correctable_data_error
+#define	wci_ca_esr_mask_dstat_inconsistent	\
+	bit.dstat_inconsistent
+#define	wci_ca_esr_mask_mtag_mismatch_within_hcl	\
+	bit.mtag_mismatch_within_hcl
+#define	wci_ca_esr_mask_mtag_mismatch_between_hcls	\
+	bit.mtag_mismatch_between_hcls
+#define	wci_ca_esr_mask_remote_timeout	\
+	bit.remote_timeout
+#define	wci_ca_esr_mask_local_timeout	\
+	bit.local_timeout
+
+
+/*
+ * wci_cluster_sync
+ */
+typedef union {
+	struct wci_cluster_sync {
+		uint64_t sync_in_progress		: 1;	/* 63 */
+		uint64_t rsvd_z				: 31;	/* 62:32 */
+		uint64_t cag_busy			: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_cluster_sync_u;
+
+#define	wci_cluster_sync_sync_in_progress	\
+	bit.sync_in_progress
+#define	wci_cluster_sync_cag_busy	\
+	bit.cag_busy
+
+
+/*
+ * wci_ca_timeout_config_2
+ */
+typedef union {
+	struct wci_ca_timeout_config_2 {
+		uint64_t rsvd_z				: 39;	/* 63:25 */
+		uint64_t sfi_targid_timeout_disable	: 1;	/* 24 */
+		uint64_t rsvd_y				: 1;	/* 23 */
+		uint64_t sfi_targid_timeout_sel		: 3;	/* 22:20 */
+		uint64_t rsvd_x				: 6;	/* 19:14 */
+		uint64_t loc_reuse_mag			: 2;	/* 13:12 */
+		uint64_t rsvd_w				: 1;	/* 11 */
+		uint64_t loc_reuse_val			: 11;	/* 10:0 */
+	} bit;
+	uint64_t val;
+} wci_ca_timeout_config_2_u;
+
+#define	wci_ca_timeout_config_2_sfi_targid_timeout_disable	\
+	bit.sfi_targid_timeout_disable
+#define	wci_ca_timeout_config_2_sfi_targid_timeout_sel	\
+	bit.sfi_targid_timeout_sel
+#define	wci_ca_timeout_config_2_loc_reuse_mag	\
+	bit.loc_reuse_mag
+#define	wci_ca_timeout_config_2_loc_reuse_val	\
+	bit.loc_reuse_val
+
+
+/*
+ * wci_ca_error_transaction_2
+ */
+typedef union {
+	struct wci_ca_error_transaction_2 {
+		uint64_t rsvd_z				: 60;	/* 63:4 */
+		uint64_t snoop2_late_reissue		: 1;	/* 3 */
+		uint64_t dc_rcv2_barrier		: 1;	/* 2 */
+		uint64_t cpi_barrier			: 1;	/* 1 */
+		uint64_t cpi_rcv2_barrier		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_ca_error_transaction_2_u;
+
+#define	wci_ca_error_transaction_2_snoop2_late_reissue	\
+	bit.snoop2_late_reissue
+#define	wci_ca_error_transaction_2_dc_rcv2_barrier	\
+	bit.dc_rcv2_barrier
+#define	wci_ca_error_transaction_2_cpi_barrier	\
+	bit.cpi_barrier
+#define	wci_ca_error_transaction_2_cpi_rcv2_barrier	\
+	bit.cpi_rcv2_barrier
+
+
+/*
+ * wci_qlim_config_cag
+ */
+typedef union {
+	struct wci_qlim_config_cag {
+		uint64_t freeze				: 1;	/* 63 */
+		uint64_t disable			: 1;	/* 62 */
+		uint64_t rsvd_z				: 9;	/* 61:53 */
+		uint64_t max_discard			: 13;	/* 52:40 */
+		uint64_t rsvd_y				: 2;	/* 39:38 */
+		uint64_t num2discard			: 10;	/* 37:28 */
+		uint64_t rsvd_x				: 11;	/* 27:17 */
+		uint64_t tmin_mag			: 13;	/* 16:4 */
+		uint64_t rsvd_w				: 1;	/* 3 */
+		uint64_t hwmark_exp			: 3;	/* 2:0 */
+	} bit;
+	uint64_t val;
+} wci_qlim_config_cag_u;
+
+#define	wci_qlim_config_cag_freeze	\
+	bit.freeze
+#define	wci_qlim_config_cag_disable	\
+	bit.disable
+#define	wci_qlim_config_cag_max_discard	\
+	bit.max_discard
+#define	wci_qlim_config_cag_num2discard	\
+	bit.num2discard
+#define	wci_qlim_config_cag_tmin_mag	\
+	bit.tmin_mag
+#define	wci_qlim_config_cag_hwmark_exp	\
+	bit.hwmark_exp
+
+
+/*
+ * wci_qlim_cag_timer
+ */
+typedef union {
+	struct wci_qlim_cag_timer {
+		uint64_t rsvd_z				: 35;	/* 63:29 */
+		uint64_t value				: 29;	/* 28:0 */
+	} bit;
+	uint64_t val;
+} wci_qlim_cag_timer_u;
+
+#define	wci_qlim_cag_timer_value	\
+	bit.value
+
+
+/*
+ * wci_board2cnid_array
+ */
+typedef union {
+	struct wci_board2cnid_array {
+		uint64_t rsvd_z				: 56;	/* 63:8 */
+		uint64_t data				: 8;	/* 7:0 */
+	} bit;
+	uint64_t val;
+} wci_board2cnid_array_u;
+
+#define	wci_board2cnid_array_data	\
+	bit.data
+
+
+/*
+ * wci_inid2dnid_array
+ */
+typedef union {
+	struct wci_inid2dnid_array {
+		uint64_t rsvd_z				: 60;	/* 63:4 */
+		uint64_t dnid				: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_inid2dnid_array_u;
+
+#define	wci_inid2dnid_array_dnid	\
+	bit.dnid
+
+
+/*
+ * wci_ra_freeze
+ */
+typedef union {
+	struct wci_ra_freeze {
+		uint64_t rsvd_z				: 32;	/* 63:32 */
+		uint64_t vector				: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_ra_freeze_u;
+
+#define	wci_ra_freeze_vector	\
+	bit.vector
+
+
+/*
+ * wci_ra_busy
+ */
+typedef union {
+	struct wci_ra_busy {
+		uint64_t request_synch			: 32;	/* 63:32 */
+		uint64_t vector				: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_ra_busy_u;
+
+#define	wci_ra_busy_request_synch	\
+	bit.request_synch
+#define	wci_ra_busy_vector	\
+	bit.vector
+
+
+/*
+ * wci_ra_first_error_agent
+ */
+typedef union {
+	struct wci_ra_first_error_agent {
+		uint64_t esr_reg			: 1;	/* 63 */
+		uint64_t esr_index			: 4;	/* 62:59 */
+		uint64_t rsvd_z				: 54;	/* 58:5 */
+		uint64_t instance			: 5;	/* 4:0 */
+	} bit;
+	uint64_t val;
+} wci_ra_first_error_agent_u;
+
+#define	wci_ra_first_error_agent_esr_reg	\
+	bit.esr_reg
+#define	wci_ra_first_error_agent_esr_index	\
+	bit.esr_index
+#define	wci_ra_first_error_agent_instance	\
+	bit.instance
+
+
+/*
+ * wci_ra_first_packet_0
+ */
+typedef union {
+	struct wci_ra_first_packet_0 {
+		uint64_t lo				: 64;	/* 63:0 */
+	} bit;
+	uint64_t val;
+} wci_ra_first_packet_0_u;
+
+#define	wci_ra_first_packet_0_lo	\
+	bit.lo
+
+
+/*
+ * wci_ra_first_packet_1
+ */
+typedef union {
+	struct wci_ra_first_packet_1 {
+		uint64_t esr_reg			: 1;	/* 63 */
+		uint64_t esr_index			: 4;	/* 62:59 */
+		uint64_t sfq_input			: 2;	/* 58:57 */
+		uint64_t transaction_type		: 6;	/* 56:51 */
+		uint64_t rsvd_z				: 20;	/* 50:31 */
+		uint64_t hi				: 31;	/* 30:0 */
+	} bit;
+	uint64_t val;
+} wci_ra_first_packet_1_u;
+
+#define	wci_ra_first_packet_1_esr_reg	\
+	bit.esr_reg
+#define	wci_ra_first_packet_1_esr_index	\
+	bit.esr_index
+#define	wci_ra_first_packet_1_sfq_input	\
+	bit.sfq_input
+#define	wci_ra_first_packet_1_transaction_type	\
+	bit.transaction_type
+#define	wci_ra_first_packet_1_hi	\
+	bit.hi
+
+
+/*
+ * wci_ra_ecc_address
+ */
+typedef union {
+	struct wci_ra_ecc_address {
+		uint64_t data				: 1;	/* 63 */
+		uint64_t ue				: 1;	/* 62 */
+		uint64_t atransid			: 9;	/* 61:53 */
+		uint64_t transaction_type		: 6;	/* 52:47 */
+		uint64_t rsvd_z				: 4;	/* 46:43 */
+		uint64_t addr				: 39;	/* 42:4 */
+		uint64_t rsvd_y				: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_ra_ecc_address_u;
+
+#define	wci_ra_ecc_address_data	\
+	bit.data
+#define	wci_ra_ecc_address_ue	\
+	bit.ue
+#define	wci_ra_ecc_address_atransid	\
+	bit.atransid
+#define	wci_ra_ecc_address_transaction_type	\
+	bit.transaction_type
+#define	wci_ra_ecc_address_addr	\
+	bit.addr
+
+
+/*
+ * wci_ra_error_transaction_0
+ */
+typedef union {
+	struct wci_ra_error_transaction_0 {
+		uint64_t esr_reg			: 1;	/* 63 */
+		uint64_t esr_index			: 4;	/* 62:59 */
+		uint64_t rsvd_z				: 3;	/* 58:56 */
+		uint64_t cesr_index			: 8;	/* 55:48 */
+		uint64_t atransid			: 9;	/* 47:39 */
+		uint64_t addr				: 39;	/* 38:0 */
+	} bit;
+	uint64_t val;
+} wci_ra_error_transaction_0_u;
+
+#define	wci_ra_error_transaction_0_esr_reg	\
+	bit.esr_reg
+#define	wci_ra_error_transaction_0_esr_index	\
+	bit.esr_index
+#define	wci_ra_error_transaction_0_cesr_index	\
+	bit.cesr_index
+#define	wci_ra_error_transaction_0_atransid	\
+	bit.atransid
+#define	wci_ra_error_transaction_0_addr	\
+	bit.addr
+
+
+/*
+ * wci_ra_error_transaction_1
+ */
+typedef union {
+	struct wci_ra_error_transaction_1 {
+		uint64_t fsm_state			: 7;	/* 63:57 */
+		uint64_t rsvd_z				: 25;	/* 56:32 */
+		uint64_t rtid				: 4;	/* 31:28 */
+		uint64_t rsvd_y				: 1;	/* 27 */
+		uint64_t dh_errors			: 7;	/* 26:20 */
+		uint64_t error_code			: 4;	/* 19:16 */
+		uint64_t rcv_cntr			: 2;	/* 15:14 */
+		uint64_t snd_cntr			: 2;	/* 13:12 */
+		uint64_t tmot_err			: 1;	/* 11 */
+		uint64_t rh_err				: 1;	/* 10 */
+		uint64_t transaction_type		: 6;	/* 9:4 */
+		uint64_t rsvd_x				: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_ra_error_transaction_1_u;
+
+#define	wci_ra_error_transaction_1_fsm_state	\
+	bit.fsm_state
+#define	wci_ra_error_transaction_1_rtid	\
+	bit.rtid
+#define	wci_ra_error_transaction_1_dh_errors	\
+	bit.dh_errors
+#define	wci_ra_error_transaction_1_error_code	\
+	bit.error_code
+#define	wci_ra_error_transaction_1_rcv_cntr	\
+	bit.rcv_cntr
+#define	wci_ra_error_transaction_1_snd_cntr	\
+	bit.snd_cntr
+#define	wci_ra_error_transaction_1_tmot_err	\
+	bit.tmot_err
+#define	wci_ra_error_transaction_1_rh_err	\
+	bit.rh_err
+#define	wci_ra_error_transaction_1_transaction_type	\
+	bit.transaction_type
+
+
+/*
+ * wci_ra_timeout_config
+ */
+typedef union {
+	struct wci_ra_timeout_config {
+		uint64_t rsvd_z				: 22;	/* 63:42 */
+		uint64_t clus_disable			: 1;	/* 41 */
+		uint64_t clus_freeze			: 1;	/* 40 */
+		uint64_t rsvd_y				: 2;	/* 39:38 */
+		uint64_t clus_aphase_mag		: 2;	/* 37:36 */
+		uint64_t rsvd_x				: 2;	/* 35:34 */
+		uint64_t clus_aphase_val		: 8;	/* 33:26 */
+		uint64_t clus_dphase_mag		: 2;	/* 25:24 */
+		uint64_t clus_dphase_val		: 8;	/* 23:16 */
+		uint64_t rsvd_w				: 2;	/* 15:14 */
+		uint64_t ssm_disable			: 1;	/* 13 */
+		uint64_t ssm_freeze			: 1;	/* 12 */
+		uint64_t rsvd_v				: 2;	/* 11:10 */
+		uint64_t ssm_mag			: 2;	/* 9:8 */
+		uint64_t ssm_val			: 8;	/* 7:0 */
+	} bit;
+	uint64_t val;
+} wci_ra_timeout_config_u;
+
+#define	wci_ra_timeout_config_clus_disable	\
+	bit.clus_disable
+#define	wci_ra_timeout_config_clus_freeze	\
+	bit.clus_freeze
+#define	wci_ra_timeout_config_clus_aphase_mag	\
+	bit.clus_aphase_mag
+#define	wci_ra_timeout_config_clus_aphase_val	\
+	bit.clus_aphase_val
+#define	wci_ra_timeout_config_clus_dphase_mag	\
+	bit.clus_dphase_mag
+#define	wci_ra_timeout_config_clus_dphase_val	\
+	bit.clus_dphase_val
+#define	wci_ra_timeout_config_ssm_disable	\
+	bit.ssm_disable
+#define	wci_ra_timeout_config_ssm_freeze	\
+	bit.ssm_freeze
+#define	wci_ra_timeout_config_ssm_mag	\
+	bit.ssm_mag
+#define	wci_ra_timeout_config_ssm_val	\
+	bit.ssm_val
+
+
+/*
+ * wci_ra_esr_0
+ */
+typedef union {
+	struct wci_ra_esr_0 {
+		uint64_t rsvd_z				: 33;	/* 63:31 */
+		uint64_t acc_ssm_timeout		: 1;	/* 30 */
+		uint64_t acc_wrong_reply		: 1;	/* 29 */
+		uint64_t acc_illegal_sender		: 1;	/* 28 */
+		uint64_t acc_not_expected_reply		: 1;	/* 27 */
+		uint64_t acc_qlimit_timeout		: 1;	/* 26 */
+		uint64_t acc_unexpected_snid		: 1;	/* 25 */
+		uint64_t acc_wrong_safari_command	: 1;	/* 24 */
+		uint64_t acc_non_block_trans		: 1;	/* 23 */
+		uint64_t acc_cesr_error_wrong		: 1;	/* 22 */
+		uint64_t acc_cluster_local_timeout	: 1;	/* 21 */
+		uint64_t acc_cluster_remote_timeout	: 1;	/* 20 */
+		uint64_t acc_mtag_mismatch_between_hcls	: 1;	/* 19 */
+		uint64_t acc_mtag_mismatch_within_hcl	: 1;	/* 18 */
+		uint64_t acc_dstat_inconsistent		: 1;	/* 17 */
+		uint64_t acc_mtag_not_gm		: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t ssm_timeout			: 1;	/* 14 */
+		uint64_t wrong_reply			: 1;	/* 13 */
+		uint64_t illegal_sender			: 1;	/* 12 */
+		uint64_t not_expected_reply		: 1;	/* 11 */
+		uint64_t qlimit_timeout			: 1;	/* 10 */
+		uint64_t unexpected_snid		: 1;	/* 9 */
+		uint64_t wrong_safari_command		: 1;	/* 8 */
+		uint64_t non_block_trans		: 1;	/* 7 */
+		uint64_t cesr_error_wrong		: 1;	/* 6 */
+		uint64_t cluster_local_timeout		: 1;	/* 5 */
+		uint64_t cluster_remote_timeout		: 1;	/* 4 */
+		uint64_t mtag_mismatch_between_hcls	: 1;	/* 3 */
+		uint64_t mtag_mismatch_within_hcl	: 1;	/* 2 */
+		uint64_t dstat_inconsistent		: 1;	/* 1 */
+		uint64_t mtag_not_gm			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_ra_esr_0_u;
+
+#define	wci_ra_esr_0_acc_ssm_timeout	\
+	bit.acc_ssm_timeout
+#define	wci_ra_esr_0_acc_wrong_reply	\
+	bit.acc_wrong_reply
+#define	wci_ra_esr_0_acc_illegal_sender	\
+	bit.acc_illegal_sender
+#define	wci_ra_esr_0_acc_not_expected_reply	\
+	bit.acc_not_expected_reply
+#define	wci_ra_esr_0_acc_qlimit_timeout	\
+	bit.acc_qlimit_timeout
+#define	wci_ra_esr_0_acc_unexpected_snid	\
+	bit.acc_unexpected_snid
+#define	wci_ra_esr_0_acc_wrong_safari_command	\
+	bit.acc_wrong_safari_command
+#define	wci_ra_esr_0_acc_non_block_trans	\
+	bit.acc_non_block_trans
+#define	wci_ra_esr_0_acc_cesr_error_wrong	\
+	bit.acc_cesr_error_wrong
+#define	wci_ra_esr_0_acc_cluster_local_timeout	\
+	bit.acc_cluster_local_timeout
+#define	wci_ra_esr_0_acc_cluster_remote_timeout	\
+	bit.acc_cluster_remote_timeout
+#define	wci_ra_esr_0_acc_mtag_mismatch_between_hcls	\
+	bit.acc_mtag_mismatch_between_hcls
+#define	wci_ra_esr_0_acc_mtag_mismatch_within_hcl	\
+	bit.acc_mtag_mismatch_within_hcl
+#define	wci_ra_esr_0_acc_dstat_inconsistent	\
+	bit.acc_dstat_inconsistent
+#define	wci_ra_esr_0_acc_mtag_not_gm	\
+	bit.acc_mtag_not_gm
+#define	wci_ra_esr_0_first_error	\
+	bit.first_error
+#define	wci_ra_esr_0_ssm_timeout	\
+	bit.ssm_timeout
+#define	wci_ra_esr_0_wrong_reply	\
+	bit.wrong_reply
+#define	wci_ra_esr_0_illegal_sender	\
+	bit.illegal_sender
+#define	wci_ra_esr_0_not_expected_reply	\
+	bit.not_expected_reply
+#define	wci_ra_esr_0_qlimit_timeout	\
+	bit.qlimit_timeout
+#define	wci_ra_esr_0_unexpected_snid	\
+	bit.unexpected_snid
+#define	wci_ra_esr_0_wrong_safari_command	\
+	bit.wrong_safari_command
+#define	wci_ra_esr_0_non_block_trans	\
+	bit.non_block_trans
+#define	wci_ra_esr_0_cesr_error_wrong	\
+	bit.cesr_error_wrong
+#define	wci_ra_esr_0_cluster_local_timeout	\
+	bit.cluster_local_timeout
+#define	wci_ra_esr_0_cluster_remote_timeout	\
+	bit.cluster_remote_timeout
+#define	wci_ra_esr_0_mtag_mismatch_between_hcls	\
+	bit.mtag_mismatch_between_hcls
+#define	wci_ra_esr_0_mtag_mismatch_within_hcl	\
+	bit.mtag_mismatch_within_hcl
+#define	wci_ra_esr_0_dstat_inconsistent	\
+	bit.dstat_inconsistent
+#define	wci_ra_esr_0_mtag_not_gm	\
+	bit.mtag_not_gm
+
+
+/*
+ * wci_ra_esr_1
+ */
+typedef union {
+	struct wci_ra_esr_1 {
+		uint64_t rsvd_z				: 33;	/* 63:31 */
+		uint64_t acc_write_lockout		: 1;	/* 30 */
+		uint64_t acc_unexpected_mtag		: 1;	/* 29 */
+		uint64_t acc_address_not_mapped		: 1;	/* 28 */
+		uint64_t acc_illegal_home_node		: 1;	/* 27 */
+		uint64_t acc_lpa2ga_ecc_error		: 1;	/* 26 */
+		uint64_t acc_lpa2ga_violation		: 1;	/* 25 */
+		uint64_t acc_unexpected_send_ack	: 1;	/* 24 */
+		uint64_t acc_unexpected_receive_ack	: 1;	/* 23 */
+		uint64_t acc_invalid_reply_pattern	: 1;	/* 22 */
+		uint64_t acc_hw_protocol_error		: 1;	/* 21 */
+		uint64_t acc_hw_fifo_ovfl_unfl		: 1;	/* 20 */
+		uint64_t acc_correctable_mtag_error	: 1;	/* 19 */
+		uint64_t acc_correctable_data_error	: 1;	/* 18 */
+		uint64_t acc_uncorrectable_mtag_error	: 1;	/* 17 */
+		uint64_t acc_uncorrectable_data_error	: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t write_lockout			: 1;	/* 14 */
+		uint64_t unexpected_mtag		: 1;	/* 13 */
+		uint64_t address_not_mapped		: 1;	/* 12 */
+		uint64_t illegal_home_node		: 1;	/* 11 */
+		uint64_t lpa2ga_ecc_error		: 1;	/* 10 */
+		uint64_t lpa2ga_violation		: 1;	/* 9 */
+		uint64_t unexpected_send_ack		: 1;	/* 8 */
+		uint64_t unexpected_receive_ack		: 1;	/* 7 */
+		uint64_t invalid_reply_pattern		: 1;	/* 6 */
+		uint64_t hw_protocol_error		: 1;	/* 5 */
+		uint64_t hw_fifo_ovfl_unfl		: 1;	/* 4 */
+		uint64_t correctable_mtag_error		: 1;	/* 3 */
+		uint64_t correctable_data_error		: 1;	/* 2 */
+		uint64_t uncorrectable_mtag_error	: 1;	/* 1 */
+		uint64_t uncorrectable_data_error	: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_ra_esr_1_u;
+
+#define	wci_ra_esr_1_acc_write_lockout	\
+	bit.acc_write_lockout
+#define	wci_ra_esr_1_acc_unexpected_mtag	\
+	bit.acc_unexpected_mtag
+#define	wci_ra_esr_1_acc_address_not_mapped	\
+	bit.acc_address_not_mapped
+#define	wci_ra_esr_1_acc_illegal_home_node	\
+	bit.acc_illegal_home_node
+#define	wci_ra_esr_1_acc_lpa2ga_ecc_error	\
+	bit.acc_lpa2ga_ecc_error
+#define	wci_ra_esr_1_acc_lpa2ga_violation	\
+	bit.acc_lpa2ga_violation
+#define	wci_ra_esr_1_acc_unexpected_send_ack	\
+	bit.acc_unexpected_send_ack
+#define	wci_ra_esr_1_acc_unexpected_receive_ack	\
+	bit.acc_unexpected_receive_ack
+#define	wci_ra_esr_1_acc_invalid_reply_pattern	\
+	bit.acc_invalid_reply_pattern
+#define	wci_ra_esr_1_acc_hw_protocol_error	\
+	bit.acc_hw_protocol_error
+#define	wci_ra_esr_1_acc_hw_fifo_ovfl_unfl	\
+	bit.acc_hw_fifo_ovfl_unfl
+#define	wci_ra_esr_1_acc_correctable_mtag_error	\
+	bit.acc_correctable_mtag_error
+#define	wci_ra_esr_1_acc_correctable_data_error	\
+	bit.acc_correctable_data_error
+#define	wci_ra_esr_1_acc_uncorrectable_mtag_error	\
+	bit.acc_uncorrectable_mtag_error
+#define	wci_ra_esr_1_acc_uncorrectable_data_error	\
+	bit.acc_uncorrectable_data_error
+#define	wci_ra_esr_1_first_error	\
+	bit.first_error
+#define	wci_ra_esr_1_write_lockout	\
+	bit.write_lockout
+#define	wci_ra_esr_1_unexpected_mtag	\
+	bit.unexpected_mtag
+#define	wci_ra_esr_1_address_not_mapped	\
+	bit.address_not_mapped
+#define	wci_ra_esr_1_illegal_home_node	\
+	bit.illegal_home_node
+#define	wci_ra_esr_1_lpa2ga_ecc_error	\
+	bit.lpa2ga_ecc_error
+#define	wci_ra_esr_1_lpa2ga_violation	\
+	bit.lpa2ga_violation
+#define	wci_ra_esr_1_unexpected_send_ack	\
+	bit.unexpected_send_ack
+#define	wci_ra_esr_1_unexpected_receive_ack	\
+	bit.unexpected_receive_ack
+#define	wci_ra_esr_1_invalid_reply_pattern	\
+	bit.invalid_reply_pattern
+#define	wci_ra_esr_1_hw_protocol_error	\
+	bit.hw_protocol_error
+#define	wci_ra_esr_1_hw_fifo_ovfl_unfl	\
+	bit.hw_fifo_ovfl_unfl
+#define	wci_ra_esr_1_correctable_mtag_error	\
+	bit.correctable_mtag_error
+#define	wci_ra_esr_1_correctable_data_error	\
+	bit.correctable_data_error
+#define	wci_ra_esr_1_uncorrectable_mtag_error	\
+	bit.uncorrectable_mtag_error
+#define	wci_ra_esr_1_uncorrectable_data_error	\
+	bit.uncorrectable_data_error
+
+
+/*
+ * wci_ra_esr_mask
+ */
+typedef union {
+	struct wci_ra_esr_mask {
+		uint64_t rsvd_z				: 33;	/* 63:31 */
+		uint64_t write_lockout			: 1;	/* 30 */
+		uint64_t unexpected_mtag		: 1;	/* 29 */
+		uint64_t address_not_mapped		: 1;	/* 28 */
+		uint64_t illegal_home_node		: 1;	/* 27 */
+		uint64_t lpa2ga_ecc_error		: 1;	/* 26 */
+		uint64_t lpa2ga_violation		: 1;	/* 25 */
+		uint64_t unexpected_send_ack		: 1;	/* 24 */
+		uint64_t unexpected_receive_ack		: 1;	/* 23 */
+		uint64_t invalid_reply_pattern		: 1;	/* 22 */
+		uint64_t hw_protocol_error		: 1;	/* 21 */
+		uint64_t hw_fifo_ovfl_unfl		: 1;	/* 20 */
+		uint64_t correctable_mtag_error		: 1;	/* 19 */
+		uint64_t correctable_data_error		: 1;	/* 18 */
+		uint64_t uncorrectable_mtag_error	: 1;	/* 17 */
+		uint64_t uncorrectable_data_error	: 1;	/* 16 */
+		uint64_t rsvd_y				: 1;	/* 15 */
+		uint64_t ssm_timeout			: 1;	/* 14 */
+		uint64_t wrong_reply			: 1;	/* 13 */
+		uint64_t illegal_sender			: 1;	/* 12 */
+		uint64_t not_expected_reply		: 1;	/* 11 */
+		uint64_t qlimit_timeout			: 1;	/* 10 */
+		uint64_t unexpected_snid		: 1;	/* 9 */
+		uint64_t wrong_safari_command		: 1;	/* 8 */
+		uint64_t non_block_trans		: 1;	/* 7 */
+		uint64_t cesr_error_wrong		: 1;	/* 6 */
+		uint64_t cluster_local_timeout		: 1;	/* 5 */
+		uint64_t cluster_remote_timeout		: 1;	/* 4 */
+		uint64_t mtag_mismatch_between_hcls	: 1;	/* 3 */
+		uint64_t mtag_mismatch_within_hcl	: 1;	/* 2 */
+		uint64_t dstat_inconsistent		: 1;	/* 1 */
+		uint64_t mtag_not_gm			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_ra_esr_mask_u;
+
+#define	wci_ra_esr_mask_write_lockout	\
+	bit.write_lockout
+#define	wci_ra_esr_mask_unexpected_mtag	\
+	bit.unexpected_mtag
+#define	wci_ra_esr_mask_address_not_mapped	\
+	bit.address_not_mapped
+#define	wci_ra_esr_mask_illegal_home_node	\
+	bit.illegal_home_node
+#define	wci_ra_esr_mask_lpa2ga_ecc_error	\
+	bit.lpa2ga_ecc_error
+#define	wci_ra_esr_mask_lpa2ga_violation	\
+	bit.lpa2ga_violation
+#define	wci_ra_esr_mask_unexpected_send_ack	\
+	bit.unexpected_send_ack
+#define	wci_ra_esr_mask_unexpected_receive_ack	\
+	bit.unexpected_receive_ack
+#define	wci_ra_esr_mask_invalid_reply_pattern	\
+	bit.invalid_reply_pattern
+#define	wci_ra_esr_mask_hw_protocol_error	\
+	bit.hw_protocol_error
+#define	wci_ra_esr_mask_hw_fifo_ovfl_unfl	\
+	bit.hw_fifo_ovfl_unfl
+#define	wci_ra_esr_mask_correctable_mtag_error	\
+	bit.correctable_mtag_error
+#define	wci_ra_esr_mask_correctable_data_error	\
+	bit.correctable_data_error
+#define	wci_ra_esr_mask_uncorrectable_mtag_error	\
+	bit.uncorrectable_mtag_error
+#define	wci_ra_esr_mask_uncorrectable_data_error	\
+	bit.uncorrectable_data_error
+#define	wci_ra_esr_mask_ssm_timeout	\
+	bit.ssm_timeout
+#define	wci_ra_esr_mask_wrong_reply	\
+	bit.wrong_reply
+#define	wci_ra_esr_mask_illegal_sender	\
+	bit.illegal_sender
+#define	wci_ra_esr_mask_not_expected_reply	\
+	bit.not_expected_reply
+#define	wci_ra_esr_mask_qlimit_timeout	\
+	bit.qlimit_timeout
+#define	wci_ra_esr_mask_unexpected_snid	\
+	bit.unexpected_snid
+#define	wci_ra_esr_mask_wrong_safari_command	\
+	bit.wrong_safari_command
+#define	wci_ra_esr_mask_non_block_trans	\
+	bit.non_block_trans
+#define	wci_ra_esr_mask_cesr_error_wrong	\
+	bit.cesr_error_wrong
+#define	wci_ra_esr_mask_cluster_local_timeout	\
+	bit.cluster_local_timeout
+#define	wci_ra_esr_mask_cluster_remote_timeout	\
+	bit.cluster_remote_timeout
+#define	wci_ra_esr_mask_mtag_mismatch_between_hcls	\
+	bit.mtag_mismatch_between_hcls
+#define	wci_ra_esr_mask_mtag_mismatch_within_hcl	\
+	bit.mtag_mismatch_within_hcl
+#define	wci_ra_esr_mask_dstat_inconsistent	\
+	bit.dstat_inconsistent
+#define	wci_ra_esr_mask_mtag_not_gm	\
+	bit.mtag_not_gm
+
+
+/*
+ * wci_ra_status_array
+ */
+typedef union {
+	struct wci_ra_status_array {
+		uint64_t fsm_state			: 7;	/* 63:57 */
+		uint64_t dtargid			: 9;	/* 56:48 */
+		uint64_t atransid			: 9;	/* 47:39 */
+		uint64_t addr				: 39;	/* 38:0 */
+	} bit;
+	uint64_t val;
+} wci_ra_status_array_u;
+
+#define	wci_ra_status_array_fsm_state	\
+	bit.fsm_state
+#define	wci_ra_status_array_dtargid	\
+	bit.dtargid
+#define	wci_ra_status_array_atransid	\
+	bit.atransid
+#define	wci_ra_status_array_addr	\
+	bit.addr
+
+
+/*
+ * wci_ra_status_2_array
+ */
+typedef union {
+	struct wci_ra_status_2_array {
+		uint64_t tflg_ecc			: 1;	/* 63 */
+		uint64_t replies_rcvd_vld		: 1;	/* 62 */
+		uint64_t stripe				: 1;	/* 61 */
+		uint64_t rh_sm				: 2;	/* 60:59 */
+		uint64_t rcvd_mtag			: 3;	/* 58:56 */
+		uint64_t cesr_index			: 8;	/* 55:48 */
+		uint64_t ntransid			: 9;	/* 47:39 */
+		uint64_t dtarg				: 1;	/* 38 */
+		uint64_t saw_s_ack			: 1;	/* 37 */
+		uint64_t saw_h_d			: 1;	/* 36 */
+		uint64_t saw_s_d			: 1;	/* 35 */
+		uint64_t saw_h_pull			: 1;	/* 34 */
+		uint64_t saw_h_pull_m			: 1;	/* 33 */
+		uint64_t saw_h_pull_i			: 1;	/* 32 */
+		uint64_t replies_rcvd			: 16;	/* 31:16 */
+		uint64_t rcv_cntr			: 2;	/* 15:14 */
+		uint64_t snd_cntr			: 2;	/* 13:12 */
+		uint64_t saw_h_nack			: 1;	/* 11 */
+		uint64_t saw_h_err			: 1;	/* 10 */
+		uint64_t transaction_type		: 6;	/* 9:4 */
+		uint64_t hnid				: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_ra_status_2_array_u;
+
+#define	wci_ra_status_2_array_tflg_ecc	\
+	bit.tflg_ecc
+#define	wci_ra_status_2_array_replies_rcvd_vld	\
+	bit.replies_rcvd_vld
+#define	wci_ra_status_2_array_stripe	\
+	bit.stripe
+#define	wci_ra_status_2_array_rh_sm	\
+	bit.rh_sm
+#define	wci_ra_status_2_array_rcvd_mtag	\
+	bit.rcvd_mtag
+#define	wci_ra_status_2_array_cesr_index	\
+	bit.cesr_index
+#define	wci_ra_status_2_array_ntransid	\
+	bit.ntransid
+#define	wci_ra_status_2_array_dtarg	\
+	bit.dtarg
+#define	wci_ra_status_2_array_saw_s_ack	\
+	bit.saw_s_ack
+#define	wci_ra_status_2_array_saw_h_d	\
+	bit.saw_h_d
+#define	wci_ra_status_2_array_saw_s_d	\
+	bit.saw_s_d
+#define	wci_ra_status_2_array_saw_h_pull	\
+	bit.saw_h_pull
+#define	wci_ra_status_2_array_saw_h_pull_m	\
+	bit.saw_h_pull_m
+#define	wci_ra_status_2_array_saw_h_pull_i	\
+	bit.saw_h_pull_i
+#define	wci_ra_status_2_array_replies_rcvd	\
+	bit.replies_rcvd
+#define	wci_ra_status_2_array_rcv_cntr	\
+	bit.rcv_cntr
+#define	wci_ra_status_2_array_snd_cntr	\
+	bit.snd_cntr
+#define	wci_ra_status_2_array_saw_h_nack	\
+	bit.saw_h_nack
+#define	wci_ra_status_2_array_saw_h_err	\
+	bit.saw_h_err
+#define	wci_ra_status_2_array_transaction_type	\
+	bit.transaction_type
+#define	wci_ra_status_2_array_hnid	\
+	bit.hnid
+
+
+/*
+ * wci_ra_write_lockout_status
+ */
+typedef union {
+	struct wci_ra_write_lockout_status {
+		uint64_t rsvd_z				: 54;	/* 63:10 */
+		uint64_t link_stripe			: 2;	/* 9:8 */
+		uint64_t nc_slice			: 8;	/* 7:0 */
+	} bit;
+	uint64_t val;
+} wci_ra_write_lockout_status_u;
+
+#define	wci_ra_write_lockout_status_link_stripe	\
+	bit.link_stripe
+#define	wci_ra_write_lockout_status_nc_slice	\
+	bit.nc_slice
+
+
+/*
+ * wci_rag_route_map0
+ */
+typedef union {
+	struct wci_rag_route_map0 {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_rag_route_map0_u;
+
+#define	wci_rag_route_map0_node15_tlink	\
+	bit.node15_tlink
+#define	wci_rag_route_map0_node14_tlink	\
+	bit.node14_tlink
+#define	wci_rag_route_map0_node13_tlink	\
+	bit.node13_tlink
+#define	wci_rag_route_map0_node12_tlink	\
+	bit.node12_tlink
+#define	wci_rag_route_map0_node11_tlink	\
+	bit.node11_tlink
+#define	wci_rag_route_map0_node10_tlink	\
+	bit.node10_tlink
+#define	wci_rag_route_map0_node9_tlink	\
+	bit.node9_tlink
+#define	wci_rag_route_map0_node8_tlink	\
+	bit.node8_tlink
+#define	wci_rag_route_map0_node7_tlink	\
+	bit.node7_tlink
+#define	wci_rag_route_map0_node6_tlink	\
+	bit.node6_tlink
+#define	wci_rag_route_map0_node5_tlink	\
+	bit.node5_tlink
+#define	wci_rag_route_map0_node4_tlink	\
+	bit.node4_tlink
+#define	wci_rag_route_map0_node3_tlink	\
+	bit.node3_tlink
+#define	wci_rag_route_map0_node2_tlink	\
+	bit.node2_tlink
+#define	wci_rag_route_map0_node1_tlink	\
+	bit.node1_tlink
+#define	wci_rag_route_map0_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_rag_route_map1
+ */
+typedef union {
+	struct wci_rag_route_map1 {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_rag_route_map1_u;
+
+#define	wci_rag_route_map1_node15_tlink	\
+	bit.node15_tlink
+#define	wci_rag_route_map1_node14_tlink	\
+	bit.node14_tlink
+#define	wci_rag_route_map1_node13_tlink	\
+	bit.node13_tlink
+#define	wci_rag_route_map1_node12_tlink	\
+	bit.node12_tlink
+#define	wci_rag_route_map1_node11_tlink	\
+	bit.node11_tlink
+#define	wci_rag_route_map1_node10_tlink	\
+	bit.node10_tlink
+#define	wci_rag_route_map1_node9_tlink	\
+	bit.node9_tlink
+#define	wci_rag_route_map1_node8_tlink	\
+	bit.node8_tlink
+#define	wci_rag_route_map1_node7_tlink	\
+	bit.node7_tlink
+#define	wci_rag_route_map1_node6_tlink	\
+	bit.node6_tlink
+#define	wci_rag_route_map1_node5_tlink	\
+	bit.node5_tlink
+#define	wci_rag_route_map1_node4_tlink	\
+	bit.node4_tlink
+#define	wci_rag_route_map1_node3_tlink	\
+	bit.node3_tlink
+#define	wci_rag_route_map1_node2_tlink	\
+	bit.node2_tlink
+#define	wci_rag_route_map1_node1_tlink	\
+	bit.node1_tlink
+#define	wci_rag_route_map1_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_cluster_error_status_array
+ */
+typedef union {
+	struct wci_cluster_error_status_array {
+		uint64_t rsvd_z				: 58;	/* 63:6 */
+		uint64_t disable_fail_fast		: 1;	/* 5 */
+		uint64_t not_valid			: 1;	/* 4 */
+		uint64_t value				: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_cluster_error_status_array_u;
+
+#define	wci_cluster_error_status_array_disable_fail_fast	\
+	bit.disable_fail_fast
+#define	wci_cluster_error_status_array_not_valid	\
+	bit.not_valid
+#define	wci_cluster_error_status_array_value	\
+	bit.value
+
+
+/*
+ * wci_cluster_error_count
+ */
+typedef union {
+	struct wci_cluster_error_count {
+		uint64_t value				: 64;	/* 63:0 */
+	} bit;
+	uint64_t val;
+} wci_cluster_error_count_u;
+
+#define	wci_cluster_error_count_value	\
+	bit.value
+
+
+/*
+ * wci_int_dest_busy_count
+ */
+typedef union {
+	struct wci_int_dest_busy_count {
+		uint64_t value				: 64;	/* 63:0 */
+	} bit;
+	uint64_t val;
+} wci_int_dest_busy_count_u;
+
+#define	wci_int_dest_busy_count_value	\
+	bit.value
+
+
+/*
+ * wci_qlim_3req_priority
+ */
+typedef union {
+	struct wci_qlim_3req_priority {
+		uint64_t rsvd_z				: 28;	/* 63:36 */
+		uint64_t num_slots			: 4;	/* 35:32 */
+		uint64_t arb_slots			: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_qlim_3req_priority_u;
+
+#define	wci_qlim_3req_priority_num_slots	\
+	bit.num_slots
+#define	wci_qlim_3req_priority_arb_slots	\
+	bit.arb_slots
+
+
+/*
+ * wci_qlim_2req_priority
+ */
+typedef union {
+	struct wci_qlim_2req_priority {
+		uint64_t rsvd_z				: 4;	/* 63:60 */
+		uint64_t ciq_niq_num_slots		: 4;	/* 59:56 */
+		uint64_t piq_ciq_num_slots		: 4;	/* 55:52 */
+		uint64_t niq_piq_num_slots		: 4;	/* 51:48 */
+		uint64_t ciq_niq_arb_slots		: 16;	/* 47:32 */
+		uint64_t piq_ciq_arb_slots		: 16;	/* 31:16 */
+		uint64_t niq_piq_arb_slots		: 16;	/* 15:0 */
+	} bit;
+	uint64_t val;
+} wci_qlim_2req_priority_u;
+
+#define	wci_qlim_2req_priority_ciq_niq_num_slots	\
+	bit.ciq_niq_num_slots
+#define	wci_qlim_2req_priority_piq_ciq_num_slots	\
+	bit.piq_ciq_num_slots
+#define	wci_qlim_2req_priority_niq_piq_num_slots	\
+	bit.niq_piq_num_slots
+#define	wci_qlim_2req_priority_ciq_niq_arb_slots	\
+	bit.ciq_niq_arb_slots
+#define	wci_qlim_2req_priority_piq_ciq_arb_slots	\
+	bit.piq_ciq_arb_slots
+#define	wci_qlim_2req_priority_niq_piq_arb_slots	\
+	bit.niq_piq_arb_slots
+
+
+/*
+ * wci_qlim_config_piq
+ */
+typedef union {
+	struct wci_qlim_config_piq {
+		uint64_t freeze				: 1;	/* 63 */
+		uint64_t disable			: 1;	/* 62 */
+		uint64_t rsvd_z				: 2;	/* 61:60 */
+		uint64_t discard_cnt_timer_en		: 1;	/* 59 */
+		uint64_t discard_cnt_timer_mag		: 3;	/* 58:56 */
+		uint64_t discard_cnt_timer_val		: 3;	/* 55:53 */
+		uint64_t max_discard			: 13;	/* 52:40 */
+		uint64_t rsvd_y				: 2;	/* 39:38 */
+		uint64_t num2discard			: 10;	/* 37:28 */
+		uint64_t rsvd_x				: 4;	/* 27:24 */
+		uint64_t decay				: 4;	/* 23:20 */
+		uint64_t rsvd_w				: 3;	/* 19:17 */
+		uint64_t tmin_mag			: 13;	/* 16:4 */
+		uint64_t rsvd_v				: 1;	/* 3 */
+		uint64_t hwmark_exp			: 3;	/* 2:0 */
+	} bit;
+	uint64_t val;
+} wci_qlim_config_piq_u;
+
+#define	wci_qlim_config_piq_freeze	\
+	bit.freeze
+#define	wci_qlim_config_piq_disable	\
+	bit.disable
+#define	wci_qlim_config_piq_discard_cnt_timer_en	\
+	bit.discard_cnt_timer_en
+#define	wci_qlim_config_piq_discard_cnt_timer_mag	\
+	bit.discard_cnt_timer_mag
+#define	wci_qlim_config_piq_discard_cnt_timer_val	\
+	bit.discard_cnt_timer_val
+#define	wci_qlim_config_piq_max_discard	\
+	bit.max_discard
+#define	wci_qlim_config_piq_num2discard	\
+	bit.num2discard
+#define	wci_qlim_config_piq_decay	\
+	bit.decay
+#define	wci_qlim_config_piq_tmin_mag	\
+	bit.tmin_mag
+#define	wci_qlim_config_piq_hwmark_exp	\
+	bit.hwmark_exp
+
+
+/*
+ * wci_qlim_config_niq
+ */
+typedef union {
+	struct wci_qlim_config_niq {
+		uint64_t freeze				: 1;	/* 63 */
+		uint64_t disable			: 1;	/* 62 */
+		uint64_t rsvd_z				: 2;	/* 61:60 */
+		uint64_t discard_cnt_timer_en		: 1;	/* 59 */
+		uint64_t discard_cnt_timer_mag		: 3;	/* 58:56 */
+		uint64_t discard_cnt_timer_val		: 3;	/* 55:53 */
+		uint64_t max_discard			: 13;	/* 52:40 */
+		uint64_t rsvd_y				: 2;	/* 39:38 */
+		uint64_t num2discard			: 10;	/* 37:28 */
+		uint64_t rsvd_x				: 4;	/* 27:24 */
+		uint64_t decay				: 4;	/* 23:20 */
+		uint64_t rsvd_w				: 3;	/* 19:17 */
+		uint64_t tmin_mag			: 13;	/* 16:4 */
+		uint64_t rsvd_v				: 1;	/* 3 */
+		uint64_t hwmark_exp			: 3;	/* 2:0 */
+	} bit;
+	uint64_t val;
+} wci_qlim_config_niq_u;
+
+#define	wci_qlim_config_niq_freeze	\
+	bit.freeze
+#define	wci_qlim_config_niq_disable	\
+	bit.disable
+#define	wci_qlim_config_niq_discard_cnt_timer_en	\
+	bit.discard_cnt_timer_en
+#define	wci_qlim_config_niq_discard_cnt_timer_mag	\
+	bit.discard_cnt_timer_mag
+#define	wci_qlim_config_niq_discard_cnt_timer_val	\
+	bit.discard_cnt_timer_val
+#define	wci_qlim_config_niq_max_discard	\
+	bit.max_discard
+#define	wci_qlim_config_niq_num2discard	\
+	bit.num2discard
+#define	wci_qlim_config_niq_decay	\
+	bit.decay
+#define	wci_qlim_config_niq_tmin_mag	\
+	bit.tmin_mag
+#define	wci_qlim_config_niq_hwmark_exp	\
+	bit.hwmark_exp
+
+
+/*
+ * wci_qlim_config_ciq
+ */
+typedef union {
+	struct wci_qlim_config_ciq {
+		uint64_t freeze				: 1;	/* 63 */
+		uint64_t disable			: 1;	/* 62 */
+		uint64_t rsvd_z				: 2;	/* 61:60 */
+		uint64_t discard_cnt_timer_en		: 1;	/* 59 */
+		uint64_t discard_cnt_timer_mag		: 3;	/* 58:56 */
+		uint64_t discard_cnt_timer_val		: 3;	/* 55:53 */
+		uint64_t max_discard			: 13;	/* 52:40 */
+		uint64_t rsvd_y				: 2;	/* 39:38 */
+		uint64_t num2discard			: 10;	/* 37:28 */
+		uint64_t rsvd_x				: 4;	/* 27:24 */
+		uint64_t decay				: 4;	/* 23:20 */
+		uint64_t rsvd_w				: 3;	/* 19:17 */
+		uint64_t tmin_mag			: 13;	/* 16:4 */
+		uint64_t rsvd_v				: 1;	/* 3 */
+		uint64_t hwmark_exp			: 3;	/* 2:0 */
+	} bit;
+	uint64_t val;
+} wci_qlim_config_ciq_u;
+
+#define	wci_qlim_config_ciq_freeze	\
+	bit.freeze
+#define	wci_qlim_config_ciq_disable	\
+	bit.disable
+#define	wci_qlim_config_ciq_discard_cnt_timer_en	\
+	bit.discard_cnt_timer_en
+#define	wci_qlim_config_ciq_discard_cnt_timer_mag	\
+	bit.discard_cnt_timer_mag
+#define	wci_qlim_config_ciq_discard_cnt_timer_val	\
+	bit.discard_cnt_timer_val
+#define	wci_qlim_config_ciq_max_discard	\
+	bit.max_discard
+#define	wci_qlim_config_ciq_num2discard	\
+	bit.num2discard
+#define	wci_qlim_config_ciq_decay	\
+	bit.decay
+#define	wci_qlim_config_ciq_tmin_mag	\
+	bit.tmin_mag
+#define	wci_qlim_config_ciq_hwmark_exp	\
+	bit.hwmark_exp
+
+
+/*
+ * wci_qlim_piq_timer
+ */
+typedef union {
+	struct wci_qlim_piq_timer {
+		uint64_t rsvd_z				: 35;	/* 63:29 */
+		uint64_t value				: 29;	/* 28:0 */
+	} bit;
+	uint64_t val;
+} wci_qlim_piq_timer_u;
+
+#define	wci_qlim_piq_timer_value	\
+	bit.value
+
+
+/*
+ * wci_qlim_niq_timer
+ */
+typedef union {
+	struct wci_qlim_niq_timer {
+		uint64_t rsvd_z				: 35;	/* 63:29 */
+		uint64_t value				: 29;	/* 28:0 */
+	} bit;
+	uint64_t val;
+} wci_qlim_niq_timer_u;
+
+#define	wci_qlim_niq_timer_value	\
+	bit.value
+
+
+/*
+ * wci_qlim_ciq_timer
+ */
+typedef union {
+	struct wci_qlim_ciq_timer {
+		uint64_t rsvd_z				: 35;	/* 63:29 */
+		uint64_t value				: 29;	/* 28:0 */
+	} bit;
+	uint64_t val;
+} wci_qlim_ciq_timer_u;
+
+#define	wci_qlim_ciq_timer_value	\
+	bit.value
+
+
+/*
+ * wci_os_cluster_disable
+ */
+typedef union {
+	struct wci_os_cluster_disable {
+		uint64_t rsvd_z				: 60;	/* 63:4 */
+		uint64_t ca_cluster_disable		: 1;	/* 3 */
+		uint64_t ra_piq_disable			: 1;	/* 2 */
+		uint64_t ra_niq_disable			: 1;	/* 1 */
+		uint64_t ra_ciq_disable			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_os_cluster_disable_u;
+
+#define	wci_os_cluster_disable_ca_cluster_disable	\
+	bit.ca_cluster_disable
+#define	wci_os_cluster_disable_ra_piq_disable	\
+	bit.ra_piq_disable
+#define	wci_os_cluster_disable_ra_niq_disable	\
+	bit.ra_niq_disable
+#define	wci_os_cluster_disable_ra_ciq_disable	\
+	bit.ra_ciq_disable
+
+
+/*
+ * wci_sc_cluster_disable
+ */
+typedef union {
+	struct wci_sc_cluster_disable {
+		uint64_t rsvd_z				: 60;	/* 63:4 */
+		uint64_t ca_cluster_disable		: 1;	/* 3 */
+		uint64_t ra_piq_disable			: 1;	/* 2 */
+		uint64_t ra_niq_disable			: 1;	/* 1 */
+		uint64_t ra_ciq_disable			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sc_cluster_disable_u;
+
+#define	wci_sc_cluster_disable_ca_cluster_disable	\
+	bit.ca_cluster_disable
+#define	wci_sc_cluster_disable_ra_piq_disable	\
+	bit.ra_piq_disable
+#define	wci_sc_cluster_disable_ra_niq_disable	\
+	bit.ra_niq_disable
+#define	wci_sc_cluster_disable_ra_ciq_disable	\
+	bit.ra_ciq_disable
+
+
+/*
+ * wci_ha_freeze
+ */
+typedef union {
+	struct wci_ha_freeze {
+		uint64_t rsvd_z				: 48;	/* 63:16 */
+		uint64_t vector				: 16;	/* 15:0 */
+	} bit;
+	uint64_t val;
+} wci_ha_freeze_u;
+
+#define	wci_ha_freeze_vector	\
+	bit.vector
+
+
+/*
+ * wci_ha_busy
+ */
+typedef union {
+	struct wci_ha_busy {
+		uint64_t rsvd_z				: 48;	/* 63:16 */
+		uint64_t vector				: 16;	/* 15:0 */
+	} bit;
+	uint64_t val;
+} wci_ha_busy_u;
+
+#define	wci_ha_busy_vector	\
+	bit.vector
+
+
+/*
+ * wci_ha_first_error_agent
+ */
+typedef union {
+	struct wci_ha_first_error_agent {
+		uint64_t esr_reg			: 1;	/* 63 */
+		uint64_t esr_index			: 4;	/* 62:59 */
+		uint64_t rsvd_z				: 54;	/* 58:5 */
+		uint64_t instance			: 5;	/* 4:0 */
+	} bit;
+	uint64_t val;
+} wci_ha_first_error_agent_u;
+
+#define	wci_ha_first_error_agent_esr_reg	\
+	bit.esr_reg
+#define	wci_ha_first_error_agent_esr_index	\
+	bit.esr_index
+#define	wci_ha_first_error_agent_instance	\
+	bit.instance
+
+
+/*
+ * wci_ha_first_packet_0
+ */
+typedef union {
+	struct wci_ha_first_packet_0 {
+		uint64_t lo_a				: 28;	/* 63:36 */
+		uint64_t rsvd_z				: 8;	/* 35:28 */
+		uint64_t lo_b				: 28;	/* 27:0 */
+	} bit;
+	uint64_t val;
+} wci_ha_first_packet_0_u;
+
+#define	wci_ha_first_packet_0_lo_a	\
+	bit.lo_a
+#define	wci_ha_first_packet_0_lo_b	\
+	bit.lo_b
+
+
+/*
+ * wci_ha_first_packet_1
+ */
+typedef union {
+	struct wci_ha_first_packet_1 {
+		uint64_t esr_reg			: 1;	/* 63 */
+		uint64_t esr_index			: 4;	/* 62:59 */
+		uint64_t rsvd_z				: 28;	/* 58:31 */
+		uint64_t hi				: 31;	/* 30:0 */
+	} bit;
+	uint64_t val;
+} wci_ha_first_packet_1_u;
+
+#define	wci_ha_first_packet_1_esr_reg	\
+	bit.esr_reg
+#define	wci_ha_first_packet_1_esr_index	\
+	bit.esr_index
+#define	wci_ha_first_packet_1_hi	\
+	bit.hi
+
+
+/*
+ * wci_ha_ecc_address
+ */
+typedef union {
+	struct wci_ha_ecc_address {
+		uint64_t data				: 1;	/* 63 */
+		uint64_t ue				: 1;	/* 62 */
+		uint64_t rsvd_z				: 19;	/* 61:43 */
+		uint64_t addr				: 39;	/* 42:4 */
+		uint64_t rsvd_y				: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_ha_ecc_address_u;
+
+#define	wci_ha_ecc_address_data	\
+	bit.data
+#define	wci_ha_ecc_address_ue	\
+	bit.ue
+#define	wci_ha_ecc_address_addr	\
+	bit.addr
+
+
+/*
+ * wci_ha_error_address
+ */
+typedef union {
+	struct wci_ha_error_address {
+		uint64_t esr_reg			: 1;	/* 63 */
+		uint64_t esr_index			: 4;	/* 62:59 */
+		uint64_t rsvd_z				: 16;	/* 58:43 */
+		uint64_t addr				: 39;	/* 42:4 */
+		uint64_t rsvd_y				: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_ha_error_address_u;
+
+#define	wci_ha_error_address_esr_reg	\
+	bit.esr_reg
+#define	wci_ha_error_address_esr_index	\
+	bit.esr_index
+#define	wci_ha_error_address_addr	\
+	bit.addr
+
+
+/*
+ * wci_ha_timeout_config
+ */
+typedef union {
+	struct wci_ha_timeout_config {
+		uint64_t rsvd_z				: 50;	/* 63:14 */
+		uint64_t ssm_disable			: 1;	/* 13 */
+		uint64_t ssm_freeze			: 1;	/* 12 */
+		uint64_t rsvd_y				: 2;	/* 11:10 */
+		uint64_t ssm_mag			: 2;	/* 9:8 */
+		uint64_t ssm_val			: 8;	/* 7:0 */
+	} bit;
+	uint64_t val;
+} wci_ha_timeout_config_u;
+
+#define	wci_ha_timeout_config_ssm_disable	\
+	bit.ssm_disable
+#define	wci_ha_timeout_config_ssm_freeze	\
+	bit.ssm_freeze
+#define	wci_ha_timeout_config_ssm_mag	\
+	bit.ssm_mag
+#define	wci_ha_timeout_config_ssm_val	\
+	bit.ssm_val
+
+
+/*
+ * wci_ha_esr_0
+ */
+typedef union {
+	struct wci_ha_esr_0 {
+		uint64_t rsvd_z				: 35;	/* 63:29 */
+		uint64_t acc_unexpected_snid		: 1;	/* 28 */
+		uint64_t acc_address_not_mapped_io	: 1;	/* 27 */
+		uint64_t acc_dir_parity_error		: 1;	/* 26 */
+		uint64_t acc_not_expected_compl		: 1;	/* 25 */
+		uint64_t acc_illegal_sender		: 1;	/* 24 */
+		uint64_t acc_wrong_cmd			: 1;	/* 23 */
+		uint64_t acc_uncorrectable_mtag_error	: 1;	/* 22 */
+		uint64_t acc_uncorrectable_data_error	: 1;	/* 21 */
+		uint64_t acc_correctable_mtag_error	: 1;	/* 20 */
+		uint64_t acc_correctable_data_error	: 1;	/* 19 */
+		uint64_t acc_mtag_mismatch_within_hcl	: 1;	/* 18 */
+		uint64_t acc_mtag_mismatch_between_hcls	: 1;	/* 17 */
+		uint64_t acc_timeout			: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t rsvd_y				: 2;	/* 14:13 */
+		uint64_t unexpected_snid		: 1;	/* 12 */
+		uint64_t address_not_mapped_io		: 1;	/* 11 */
+		uint64_t dir_parity_error		: 1;	/* 10 */
+		uint64_t not_expected_compl		: 1;	/* 9 */
+		uint64_t illegal_sender			: 1;	/* 8 */
+		uint64_t wrong_cmd			: 1;	/* 7 */
+		uint64_t uncorrectable_mtag_error	: 1;	/* 6 */
+		uint64_t uncorrectable_data_error	: 1;	/* 5 */
+		uint64_t correctable_mtag_error		: 1;	/* 4 */
+		uint64_t correctable_data_error		: 1;	/* 3 */
+		uint64_t mtag_mismatch_within_hcl	: 1;	/* 2 */
+		uint64_t mtag_mismatch_between_hcls	: 1;	/* 1 */
+		uint64_t timeout			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_ha_esr_0_u;
+
+#define	wci_ha_esr_0_acc_unexpected_snid	\
+	bit.acc_unexpected_snid
+#define	wci_ha_esr_0_acc_address_not_mapped_io	\
+	bit.acc_address_not_mapped_io
+#define	wci_ha_esr_0_acc_dir_parity_error	\
+	bit.acc_dir_parity_error
+#define	wci_ha_esr_0_acc_not_expected_compl	\
+	bit.acc_not_expected_compl
+#define	wci_ha_esr_0_acc_illegal_sender	\
+	bit.acc_illegal_sender
+#define	wci_ha_esr_0_acc_wrong_cmd	\
+	bit.acc_wrong_cmd
+#define	wci_ha_esr_0_acc_uncorrectable_mtag_error	\
+	bit.acc_uncorrectable_mtag_error
+#define	wci_ha_esr_0_acc_uncorrectable_data_error	\
+	bit.acc_uncorrectable_data_error
+#define	wci_ha_esr_0_acc_correctable_mtag_error	\
+	bit.acc_correctable_mtag_error
+#define	wci_ha_esr_0_acc_correctable_data_error	\
+	bit.acc_correctable_data_error
+#define	wci_ha_esr_0_acc_mtag_mismatch_within_hcl	\
+	bit.acc_mtag_mismatch_within_hcl
+#define	wci_ha_esr_0_acc_mtag_mismatch_between_hcls	\
+	bit.acc_mtag_mismatch_between_hcls
+#define	wci_ha_esr_0_acc_timeout	\
+	bit.acc_timeout
+#define	wci_ha_esr_0_first_error	\
+	bit.first_error
+#define	wci_ha_esr_0_unexpected_snid	\
+	bit.unexpected_snid
+#define	wci_ha_esr_0_address_not_mapped_io	\
+	bit.address_not_mapped_io
+#define	wci_ha_esr_0_dir_parity_error	\
+	bit.dir_parity_error
+#define	wci_ha_esr_0_not_expected_compl	\
+	bit.not_expected_compl
+#define	wci_ha_esr_0_illegal_sender	\
+	bit.illegal_sender
+#define	wci_ha_esr_0_wrong_cmd	\
+	bit.wrong_cmd
+#define	wci_ha_esr_0_uncorrectable_mtag_error	\
+	bit.uncorrectable_mtag_error
+#define	wci_ha_esr_0_uncorrectable_data_error	\
+	bit.uncorrectable_data_error
+#define	wci_ha_esr_0_correctable_mtag_error	\
+	bit.correctable_mtag_error
+#define	wci_ha_esr_0_correctable_data_error	\
+	bit.correctable_data_error
+#define	wci_ha_esr_0_mtag_mismatch_within_hcl	\
+	bit.mtag_mismatch_within_hcl
+#define	wci_ha_esr_0_mtag_mismatch_between_hcls	\
+	bit.mtag_mismatch_between_hcls
+#define	wci_ha_esr_0_timeout	\
+	bit.timeout
+
+
+/*
+ * wci_ha_esr_1
+ */
+typedef union {
+	struct wci_ha_esr_1 {
+		uint64_t rsvd_z				: 42;	/* 63:22 */
+		uint64_t acc_gnr_err			: 1;	/* 21 */
+		uint64_t acc_hw_err			: 1;	/* 20 */
+		uint64_t acc_address_not_mapped		: 1;	/* 19 */
+		uint64_t acc_dstat_inconsistent		: 1;	/* 18 */
+		uint64_t acc_mtag_not_gm		: 1;	/* 17 */
+		uint64_t acc_unexpected_mtag		: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t rsvd_y				: 9;	/* 14:6 */
+		uint64_t gnr_err			: 1;	/* 5 */
+		uint64_t hw_err				: 1;	/* 4 */
+		uint64_t address_not_mapped		: 1;	/* 3 */
+		uint64_t dstat_inconsistent		: 1;	/* 2 */
+		uint64_t mtag_not_gm			: 1;	/* 1 */
+		uint64_t unexpected_mtag		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_ha_esr_1_u;
+
+#define	wci_ha_esr_1_acc_gnr_err	\
+	bit.acc_gnr_err
+#define	wci_ha_esr_1_acc_hw_err	\
+	bit.acc_hw_err
+#define	wci_ha_esr_1_acc_address_not_mapped	\
+	bit.acc_address_not_mapped
+#define	wci_ha_esr_1_acc_dstat_inconsistent	\
+	bit.acc_dstat_inconsistent
+#define	wci_ha_esr_1_acc_mtag_not_gm	\
+	bit.acc_mtag_not_gm
+#define	wci_ha_esr_1_acc_unexpected_mtag	\
+	bit.acc_unexpected_mtag
+#define	wci_ha_esr_1_first_error	\
+	bit.first_error
+#define	wci_ha_esr_1_gnr_err	\
+	bit.gnr_err
+#define	wci_ha_esr_1_hw_err	\
+	bit.hw_err
+#define	wci_ha_esr_1_address_not_mapped	\
+	bit.address_not_mapped
+#define	wci_ha_esr_1_dstat_inconsistent	\
+	bit.dstat_inconsistent
+#define	wci_ha_esr_1_mtag_not_gm	\
+	bit.mtag_not_gm
+#define	wci_ha_esr_1_unexpected_mtag	\
+	bit.unexpected_mtag
+
+
+/*
+ * wci_ha_hw_err_status
+ */
+typedef union {
+	struct wci_ha_hw_err_status {
+		uint64_t rsvd_z				: 45;	/* 63:19 */
+		uint64_t oh_error_case_fall_through	: 1;	/* 18 */
+		uint64_t dir_fetchq_ovfl		: 1;	/* 17 */
+		uint64_t dir_fetchq_unfl		: 1;	/* 16 */
+		uint64_t srq4_errors_ovfl		: 1;	/* 15 */
+		uint64_t srq4_errors_unfl		: 1;	/* 14 */
+		uint64_t srq3_errors_ovfl		: 1;	/* 13 */
+		uint64_t srq3_errors_unfl		: 1;	/* 12 */
+		uint64_t srq2_errors_ovfl		: 1;	/* 11 */
+		uint64_t srq2_errors_unfl		: 1;	/* 10 */
+		uint64_t srq1_errors_ovfl		: 1;	/* 9 */
+		uint64_t srq1_errors_unfl		: 1;	/* 8 */
+		uint64_t kmapq_errors_ovfl		: 1;	/* 7 */
+		uint64_t kmapq_errors_unfl		: 1;	/* 6 */
+		uint64_t ohq_errors_ovfl		: 1;	/* 5 */
+		uint64_t ohq_errors_unfl		: 1;	/* 4 */
+		uint64_t shq_errors_ovfl		: 1;	/* 3 */
+		uint64_t shq_errors_unfl		: 1;	/* 2 */
+		uint64_t dhc_all_uexp_rcv_error		: 1;	/* 1 */
+		uint64_t dhc_all_uexp_snd_error		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_ha_hw_err_status_u;
+
+#define	wci_ha_hw_err_status_oh_error_case_fall_through	\
+	bit.oh_error_case_fall_through
+#define	wci_ha_hw_err_status_dir_fetchq_ovfl	\
+	bit.dir_fetchq_ovfl
+#define	wci_ha_hw_err_status_dir_fetchq_unfl	\
+	bit.dir_fetchq_unfl
+#define	wci_ha_hw_err_status_srq4_errors_ovfl	\
+	bit.srq4_errors_ovfl
+#define	wci_ha_hw_err_status_srq4_errors_unfl	\
+	bit.srq4_errors_unfl
+#define	wci_ha_hw_err_status_srq3_errors_ovfl	\
+	bit.srq3_errors_ovfl
+#define	wci_ha_hw_err_status_srq3_errors_unfl	\
+	bit.srq3_errors_unfl
+#define	wci_ha_hw_err_status_srq2_errors_ovfl	\
+	bit.srq2_errors_ovfl
+#define	wci_ha_hw_err_status_srq2_errors_unfl	\
+	bit.srq2_errors_unfl
+#define	wci_ha_hw_err_status_srq1_errors_ovfl	\
+	bit.srq1_errors_ovfl
+#define	wci_ha_hw_err_status_srq1_errors_unfl	\
+	bit.srq1_errors_unfl
+#define	wci_ha_hw_err_status_kmapq_errors_ovfl	\
+	bit.kmapq_errors_ovfl
+#define	wci_ha_hw_err_status_kmapq_errors_unfl	\
+	bit.kmapq_errors_unfl
+#define	wci_ha_hw_err_status_ohq_errors_ovfl	\
+	bit.ohq_errors_ovfl
+#define	wci_ha_hw_err_status_ohq_errors_unfl	\
+	bit.ohq_errors_unfl
+#define	wci_ha_hw_err_status_shq_errors_ovfl	\
+	bit.shq_errors_ovfl
+#define	wci_ha_hw_err_status_shq_errors_unfl	\
+	bit.shq_errors_unfl
+#define	wci_ha_hw_err_status_dhc_all_uexp_rcv_error	\
+	bit.dhc_all_uexp_rcv_error
+#define	wci_ha_hw_err_status_dhc_all_uexp_snd_error	\
+	bit.dhc_all_uexp_snd_error
+
+
+/*
+ * wci_ha_esr_mask
+ */
+typedef union {
+	struct wci_ha_esr_mask {
+		uint64_t rsvd_z				: 42;	/* 63:22 */
+		uint64_t gnr_err			: 1;	/* 21 */
+		uint64_t hw_err				: 1;	/* 20 */
+		uint64_t address_not_mapped		: 1;	/* 19 */
+		uint64_t dstat_inconsistent		: 1;	/* 18 */
+		uint64_t mtag_not_gm			: 1;	/* 17 */
+		uint64_t unexpected_mtag		: 1;	/* 16 */
+		uint64_t rsvd_y				: 3;	/* 15:13 */
+		uint64_t unexpected_snid		: 1;	/* 12 */
+		uint64_t address_not_mapped_io		: 1;	/* 11 */
+		uint64_t dir_parity_error		: 1;	/* 10 */
+		uint64_t not_expected_compl		: 1;	/* 9 */
+		uint64_t illegal_sender			: 1;	/* 8 */
+		uint64_t wrong_cmd			: 1;	/* 7 */
+		uint64_t uncorrectable_mtag_error	: 1;	/* 6 */
+		uint64_t uncorrectable_data_error	: 1;	/* 5 */
+		uint64_t correctable_mtag_error		: 1;	/* 4 */
+		uint64_t correctable_data_error		: 1;	/* 3 */
+		uint64_t mtag_mismatch_within_hcl	: 1;	/* 2 */
+		uint64_t mtag_mismatch_between_hcls	: 1;	/* 1 */
+		uint64_t timeout			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_ha_esr_mask_u;
+
+#define	wci_ha_esr_mask_gnr_err	\
+	bit.gnr_err
+#define	wci_ha_esr_mask_hw_err	\
+	bit.hw_err
+#define	wci_ha_esr_mask_address_not_mapped	\
+	bit.address_not_mapped
+#define	wci_ha_esr_mask_dstat_inconsistent	\
+	bit.dstat_inconsistent
+#define	wci_ha_esr_mask_mtag_not_gm	\
+	bit.mtag_not_gm
+#define	wci_ha_esr_mask_unexpected_mtag	\
+	bit.unexpected_mtag
+#define	wci_ha_esr_mask_unexpected_snid	\
+	bit.unexpected_snid
+#define	wci_ha_esr_mask_address_not_mapped_io	\
+	bit.address_not_mapped_io
+#define	wci_ha_esr_mask_dir_parity_error	\
+	bit.dir_parity_error
+#define	wci_ha_esr_mask_not_expected_compl	\
+	bit.not_expected_compl
+#define	wci_ha_esr_mask_illegal_sender	\
+	bit.illegal_sender
+#define	wci_ha_esr_mask_wrong_cmd	\
+	bit.wrong_cmd
+#define	wci_ha_esr_mask_uncorrectable_mtag_error	\
+	bit.uncorrectable_mtag_error
+#define	wci_ha_esr_mask_uncorrectable_data_error	\
+	bit.uncorrectable_data_error
+#define	wci_ha_esr_mask_correctable_mtag_error	\
+	bit.correctable_mtag_error
+#define	wci_ha_esr_mask_correctable_data_error	\
+	bit.correctable_data_error
+#define	wci_ha_esr_mask_mtag_mismatch_within_hcl	\
+	bit.mtag_mismatch_within_hcl
+#define	wci_ha_esr_mask_mtag_mismatch_between_hcls	\
+	bit.mtag_mismatch_between_hcls
+#define	wci_ha_esr_mask_timeout	\
+	bit.timeout
+
+
+/*
+ * wci_probe_memory
+ */
+typedef union {
+	struct wci_probe_memory {
+		uint64_t done				: 1;	/* 63 */
+		uint64_t in_progress			: 1;	/* 62 */
+		uint64_t rsvd_z				: 15;	/* 61:47 */
+		uint64_t mtag				: 3;	/* 46:44 */
+		uint64_t rsvd_y				: 1;	/* 43 */
+		uint64_t address			: 39;	/* 42:4 */
+		uint64_t rsvd_x				: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_probe_memory_u;
+
+#define	wci_probe_memory_done	\
+	bit.done
+#define	wci_probe_memory_in_progress	\
+	bit.in_progress
+#define	wci_probe_memory_mtag	\
+	bit.mtag
+#define	wci_probe_memory_address	\
+	bit.address
+
+
+/*
+ * wci_ha_status_array
+ */
+typedef union {
+	struct wci_ha_status_array {
+		uint64_t orig_atransid			: 9;	/* 63:55 */
+		uint64_t orig_rtid			: 5;	/* 54:50 */
+		uint64_t dispatched_op			: 6;	/* 49:44 */
+		uint64_t rsvd_z				: 1;	/* 43 */
+		uint64_t orig_addr			: 39;	/* 42:4 */
+		uint64_t orig_snid			: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_ha_status_array_u;
+
+#define	wci_ha_status_array_orig_atransid	\
+	bit.orig_atransid
+#define	wci_ha_status_array_orig_rtid	\
+	bit.orig_rtid
+#define	wci_ha_status_array_dispatched_op	\
+	bit.dispatched_op
+#define	wci_ha_status_array_orig_addr	\
+	bit.orig_addr
+#define	wci_ha_status_array_orig_snid	\
+	bit.orig_snid
+
+
+/*
+ * wci_ha_status_2_array
+ */
+typedef union {
+	struct wci_ha_status_2_array {
+		uint64_t rsvd_z				: 30;	/* 63:34 */
+		uint64_t dir_vld			: 1;	/* 33 */
+		uint64_t dir_hit			: 1;	/* 32 */
+		uint64_t old_dir_entry			: 12;	/* 31:20 */
+		uint64_t rsvd_y				: 1;	/* 19 */
+		uint64_t old_mtag			: 3;	/* 18:16 */
+		uint64_t dir_copt			: 2;	/* 15:14 */
+		uint64_t data_copt			: 2;	/* 13:12 */
+		uint64_t rsvd_x				: 3;	/* 11:9 */
+		uint64_t safari_thread			: 1;	/* 8 */
+		uint64_t auxid_thread			: 1;	/* 7 */
+		uint64_t cmpl_thread			: 1;	/* 6 */
+		uint64_t data_sent_thread		: 1;	/* 5 */
+		uint64_t data_rcvd_thread		: 1;	/* 4 */
+		uint64_t dob_clrd_thread		: 1;	/* 3 */
+		uint64_t hdr_sent_thread		: 1;	/* 2 */
+		uint64_t constmap_thread		: 1;	/* 1 */
+		uint64_t pull_seen_thread		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_ha_status_2_array_u;
+
+#define	wci_ha_status_2_array_dir_vld	\
+	bit.dir_vld
+#define	wci_ha_status_2_array_dir_hit	\
+	bit.dir_hit
+#define	wci_ha_status_2_array_old_dir_entry	\
+	bit.old_dir_entry
+#define	wci_ha_status_2_array_old_mtag	\
+	bit.old_mtag
+#define	wci_ha_status_2_array_dir_copt	\
+	bit.dir_copt
+#define	wci_ha_status_2_array_data_copt	\
+	bit.data_copt
+#define	wci_ha_status_2_array_safari_thread	\
+	bit.safari_thread
+#define	wci_ha_status_2_array_auxid_thread	\
+	bit.auxid_thread
+#define	wci_ha_status_2_array_cmpl_thread	\
+	bit.cmpl_thread
+#define	wci_ha_status_2_array_data_sent_thread	\
+	bit.data_sent_thread
+#define	wci_ha_status_2_array_data_rcvd_thread	\
+	bit.data_rcvd_thread
+#define	wci_ha_status_2_array_dob_clrd_thread	\
+	bit.dob_clrd_thread
+#define	wci_ha_status_2_array_hdr_sent_thread	\
+	bit.hdr_sent_thread
+#define	wci_ha_status_2_array_constmap_thread	\
+	bit.constmap_thread
+#define	wci_ha_status_2_array_pull_seen_thread	\
+	bit.pull_seen_thread
+
+
+/*
+ * wci_ha_config
+ */
+typedef union {
+	struct wci_ha_config {
+		uint64_t rsvd_z				: 55;	/* 63:9 */
+		uint64_t snid_in_mask			: 1;	/* 8 */
+		uint64_t disable_same_box_opt		: 1;	/* 7 */
+		uint64_t migratory_sharing_ctrl		: 7;	/* 6:0 */
+	} bit;
+	uint64_t val;
+} wci_ha_config_u;
+
+#define	wci_ha_config_snid_in_mask	\
+	bit.snid_in_mask
+#define	wci_ha_config_disable_same_box_opt	\
+	bit.disable_same_box_opt
+#define	wci_ha_config_migratory_sharing_ctrl	\
+	bit.migratory_sharing_ctrl
+
+
+/*
+ * wci_hag_route_map0
+ */
+typedef union {
+	struct wci_hag_route_map0 {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_hag_route_map0_u;
+
+#define	wci_hag_route_map0_node15_tlink	\
+	bit.node15_tlink
+#define	wci_hag_route_map0_node14_tlink	\
+	bit.node14_tlink
+#define	wci_hag_route_map0_node13_tlink	\
+	bit.node13_tlink
+#define	wci_hag_route_map0_node12_tlink	\
+	bit.node12_tlink
+#define	wci_hag_route_map0_node11_tlink	\
+	bit.node11_tlink
+#define	wci_hag_route_map0_node10_tlink	\
+	bit.node10_tlink
+#define	wci_hag_route_map0_node9_tlink	\
+	bit.node9_tlink
+#define	wci_hag_route_map0_node8_tlink	\
+	bit.node8_tlink
+#define	wci_hag_route_map0_node7_tlink	\
+	bit.node7_tlink
+#define	wci_hag_route_map0_node6_tlink	\
+	bit.node6_tlink
+#define	wci_hag_route_map0_node5_tlink	\
+	bit.node5_tlink
+#define	wci_hag_route_map0_node4_tlink	\
+	bit.node4_tlink
+#define	wci_hag_route_map0_node3_tlink	\
+	bit.node3_tlink
+#define	wci_hag_route_map0_node2_tlink	\
+	bit.node2_tlink
+#define	wci_hag_route_map0_node1_tlink	\
+	bit.node1_tlink
+#define	wci_hag_route_map0_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_hag_route_map1
+ */
+typedef union {
+	struct wci_hag_route_map1 {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_hag_route_map1_u;
+
+#define	wci_hag_route_map1_node15_tlink	\
+	bit.node15_tlink
+#define	wci_hag_route_map1_node14_tlink	\
+	bit.node14_tlink
+#define	wci_hag_route_map1_node13_tlink	\
+	bit.node13_tlink
+#define	wci_hag_route_map1_node12_tlink	\
+	bit.node12_tlink
+#define	wci_hag_route_map1_node11_tlink	\
+	bit.node11_tlink
+#define	wci_hag_route_map1_node10_tlink	\
+	bit.node10_tlink
+#define	wci_hag_route_map1_node9_tlink	\
+	bit.node9_tlink
+#define	wci_hag_route_map1_node8_tlink	\
+	bit.node8_tlink
+#define	wci_hag_route_map1_node7_tlink	\
+	bit.node7_tlink
+#define	wci_hag_route_map1_node6_tlink	\
+	bit.node6_tlink
+#define	wci_hag_route_map1_node5_tlink	\
+	bit.node5_tlink
+#define	wci_hag_route_map1_node4_tlink	\
+	bit.node4_tlink
+#define	wci_hag_route_map1_node3_tlink	\
+	bit.node3_tlink
+#define	wci_hag_route_map1_node2_tlink	\
+	bit.node2_tlink
+#define	wci_hag_route_map1_node1_tlink	\
+	bit.node1_tlink
+#define	wci_hag_route_map1_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_emiss_cntl_array
+ */
+typedef union {
+	struct wci_emiss_cntl_array {
+		uint64_t rsvd_z				: 13;	/* 63:51 */
+		uint64_t auto_reset_active		: 1;	/* 50 */
+		uint64_t enabled			: 1;	/* 49 */
+		uint64_t address			: 37;	/* 48:12 */
+		uint64_t nid				: 4;	/* 11:8 */
+		uint64_t length				: 2;	/* 7:6 */
+		uint64_t event0				: 3;	/* 5:3 */
+		uint64_t event1				: 3;	/* 2:0 */
+	} bit;
+	uint64_t val;
+} wci_emiss_cntl_array_u;
+
+#define	wci_emiss_cntl_array_auto_reset_active	\
+	bit.auto_reset_active
+#define	wci_emiss_cntl_array_enabled	\
+	bit.enabled
+#define	wci_emiss_cntl_array_address	\
+	bit.address
+#define	wci_emiss_cntl_array_nid	\
+	bit.nid
+#define	wci_emiss_cntl_array_length	\
+	bit.length
+#define	wci_emiss_cntl_array_event0	\
+	bit.event0
+#define	wci_emiss_cntl_array_event1	\
+	bit.event1
+
+
+/*
+ * wci_emiss_data_array
+ */
+typedef union {
+	struct wci_emiss_data_array {
+		uint64_t rsvd_z				: 20;	/* 63:44 */
+		uint64_t event0_count			: 10;	/* 43:34 */
+		uint64_t event1_count			: 10;	/* 33:24 */
+		uint64_t event0_count_all		: 12;	/* 23:12 */
+		uint64_t event1_count_all		: 12;	/* 11:0 */
+	} bit;
+	uint64_t val;
+} wci_emiss_data_array_u;
+
+#define	wci_emiss_data_array_event0_count	\
+	bit.event0_count
+#define	wci_emiss_data_array_event1_count	\
+	bit.event1_count
+#define	wci_emiss_data_array_event0_count_all	\
+	bit.event0_count_all
+#define	wci_emiss_data_array_event1_count_all	\
+	bit.event1_count_all
+
+
+/*
+ * wci_emiss_reset_ctl
+ */
+typedef union {
+	struct wci_emiss_reset_ctl {
+		uint64_t rsvd_z				: 42;	/* 63:22 */
+		uint64_t auto_reset_mask		: 10;	/* 21:12 */
+		uint64_t count				: 12;	/* 11:0 */
+	} bit;
+	uint64_t val;
+} wci_emiss_reset_ctl_u;
+
+#define	wci_emiss_reset_ctl_auto_reset_mask	\
+	bit.auto_reset_mask
+#define	wci_emiss_reset_ctl_count	\
+	bit.count
+
+
+/*
+ * wci_global_emiss_counter
+ */
+typedef union {
+	struct wci_global_emiss_counter {
+		uint64_t rsvd_z				: 40;	/* 63:24 */
+		uint64_t count				: 24;	/* 23:0 */
+	} bit;
+	uint64_t val;
+} wci_global_emiss_counter_u;
+
+#define	wci_global_emiss_counter_count	\
+	bit.count
+
+
+/*
+ * wci_sa_freeze
+ */
+typedef union {
+	struct wci_sa_freeze {
+		uint64_t rsvd_z				: 56;	/* 63:8 */
+		uint64_t vector				: 8;	/* 7:0 */
+	} bit;
+	uint64_t val;
+} wci_sa_freeze_u;
+
+#define	wci_sa_freeze_vector	\
+	bit.vector
+
+
+/*
+ * wci_sa_busy
+ */
+typedef union {
+	struct wci_sa_busy {
+		uint64_t rsvd_z				: 56;	/* 63:8 */
+		uint64_t vector				: 8;	/* 7:0 */
+	} bit;
+	uint64_t val;
+} wci_sa_busy_u;
+
+#define	wci_sa_busy_vector	\
+	bit.vector
+
+
+/*
+ * wci_sa_first_error_agent
+ */
+typedef union {
+	struct wci_sa_first_error_agent {
+		uint64_t esr_reg			: 1;	/* 63 */
+		uint64_t esr_index			: 4;	/* 62:59 */
+		uint64_t rsvd_z				: 56;	/* 58:3 */
+		uint64_t instance			: 3;	/* 2:0 */
+	} bit;
+	uint64_t val;
+} wci_sa_first_error_agent_u;
+
+#define	wci_sa_first_error_agent_esr_reg	\
+	bit.esr_reg
+#define	wci_sa_first_error_agent_esr_index	\
+	bit.esr_index
+#define	wci_sa_first_error_agent_instance	\
+	bit.instance
+
+
+/*
+ * wci_sa_first_packet_0
+ */
+typedef union {
+	struct wci_sa_first_packet_0 {
+		uint64_t rsvd_z				: 7;	/* 63:57 */
+		uint64_t ntransid			: 9;	/* 56:48 */
+		uint64_t rsvd_y				: 2;	/* 47:46 */
+		uint64_t cmr				: 1;	/* 45 */
+		uint64_t otransid			: 9;	/* 44:36 */
+		uint64_t rsvd_x				: 2;	/* 35:34 */
+		uint64_t rnid				: 4;	/* 33:30 */
+		uint64_t r2e				: 4;	/* 29:26 */
+		uint64_t emiss				: 1;	/* 25 */
+		uint64_t rsvd_w				: 1;	/* 24 */
+		uint64_t htid				: 4;	/* 23:20 */
+		uint64_t rtid				: 5;	/* 19:15 */
+		uint64_t snid				: 4;	/* 14:11 */
+		uint64_t msgop				: 4;	/* 10:7 */
+		uint64_t htyp				: 2;	/* 6:5 */
+		uint64_t stripe				: 1;	/* 4 */
+		uint64_t dnid				: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_sa_first_packet_0_u;
+
+#define	wci_sa_first_packet_0_ntransid	\
+	bit.ntransid
+#define	wci_sa_first_packet_0_cmr	\
+	bit.cmr
+#define	wci_sa_first_packet_0_otransid	\
+	bit.otransid
+#define	wci_sa_first_packet_0_rnid	\
+	bit.rnid
+#define	wci_sa_first_packet_0_r2e	\
+	bit.r2e
+#define	wci_sa_first_packet_0_emiss	\
+	bit.emiss
+#define	wci_sa_first_packet_0_htid	\
+	bit.htid
+#define	wci_sa_first_packet_0_rtid	\
+	bit.rtid
+#define	wci_sa_first_packet_0_snid	\
+	bit.snid
+#define	wci_sa_first_packet_0_msgop	\
+	bit.msgop
+#define	wci_sa_first_packet_0_htyp	\
+	bit.htyp
+#define	wci_sa_first_packet_0_stripe	\
+	bit.stripe
+#define	wci_sa_first_packet_0_dnid	\
+	bit.dnid
+
+
+/*
+ * wci_sa_first_packet_1
+ */
+typedef union {
+	struct wci_sa_first_packet_1 {
+		uint64_t esr_reg			: 1;	/* 63 */
+		uint64_t esr_index			: 4;	/* 62:59 */
+		uint64_t a_entry			: 1;	/* 58 */
+		uint64_t s_entry			: 1;	/* 57 */
+		uint64_t rsvd_z				: 14;	/* 56:43 */
+		uint64_t ga				: 38;	/* 42:5 */
+		uint64_t rsvd_y				: 5;	/* 4:0 */
+	} bit;
+	uint64_t val;
+} wci_sa_first_packet_1_u;
+
+#define	wci_sa_first_packet_1_esr_reg	\
+	bit.esr_reg
+#define	wci_sa_first_packet_1_esr_index	\
+	bit.esr_index
+#define	wci_sa_first_packet_1_a_entry	\
+	bit.a_entry
+#define	wci_sa_first_packet_1_s_entry	\
+	bit.s_entry
+#define	wci_sa_first_packet_1_ga	\
+	bit.ga
+
+
+/*
+ * wci_sa_ecc_address
+ */
+typedef union {
+	struct wci_sa_ecc_address {
+		uint64_t data				: 1;	/* 63 */
+		uint64_t ue				: 1;	/* 62 */
+		uint64_t rsvd_z				: 19;	/* 61:43 */
+		uint64_t addr				: 38;	/* 42:5 */
+		uint64_t rsvd_y				: 5;	/* 4:0 */
+	} bit;
+	uint64_t val;
+} wci_sa_ecc_address_u;
+
+#define	wci_sa_ecc_address_data	\
+	bit.data
+#define	wci_sa_ecc_address_ue	\
+	bit.ue
+#define	wci_sa_ecc_address_addr	\
+	bit.addr
+
+
+/*
+ * wci_sa_timeout_config
+ */
+typedef union {
+	struct wci_sa_timeout_config {
+		uint64_t rsvd_z				: 50;	/* 63:14 */
+		uint64_t ssm_disable			: 1;	/* 13 */
+		uint64_t ssm_freeze			: 1;	/* 12 */
+		uint64_t rsvd_y				: 2;	/* 11:10 */
+		uint64_t ssm_mag			: 2;	/* 9:8 */
+		uint64_t ssm_val			: 8;	/* 7:0 */
+	} bit;
+	uint64_t val;
+} wci_sa_timeout_config_u;
+
+#define	wci_sa_timeout_config_ssm_disable	\
+	bit.ssm_disable
+#define	wci_sa_timeout_config_ssm_freeze	\
+	bit.ssm_freeze
+#define	wci_sa_timeout_config_ssm_mag	\
+	bit.ssm_mag
+#define	wci_sa_timeout_config_ssm_val	\
+	bit.ssm_val
+
+
+/*
+ * wci_sa_esr_0
+ */
+typedef union {
+	struct wci_sa_esr_0 {
+		uint64_t rsvd_z				: 33;	/* 63:31 */
+		uint64_t acc_hw_err			: 1;	/* 30 */
+		uint64_t acc_address_not_owned		: 1;	/* 29 */
+		uint64_t acc_address_not_mapped		: 1;	/* 28 */
+		uint64_t acc_ga2lpa_ecc_error		: 1;	/* 27 */
+		uint64_t acc_rip_multi_hit		: 1;	/* 26 */
+		uint64_t acc_illegal_sender		: 1;	/* 25 */
+		uint64_t acc_wrong_demand		: 1;	/* 24 */
+		uint64_t acc_uncorrectable_mtag_error	: 1;	/* 23 */
+		uint64_t acc_uncorrectable_data_error	: 1;	/* 22 */
+		uint64_t acc_correctable_mtag_error	: 1;	/* 21 */
+		uint64_t acc_correctable_data_error	: 1;	/* 20 */
+		uint64_t acc_mtag_mismatch_within_hcl	: 1;	/* 19 */
+		uint64_t acc_mtag_mismatch_between_hcls	: 1;	/* 18 */
+		uint64_t acc_unexpected_mtag		: 1;	/* 17 */
+		uint64_t acc_timeout			: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t hw_err				: 1;	/* 14 */
+		uint64_t address_not_owned		: 1;	/* 13 */
+		uint64_t address_not_mapped		: 1;	/* 12 */
+		uint64_t ga2lpa_ecc_error		: 1;	/* 11 */
+		uint64_t rip_multi_hit			: 1;	/* 10 */
+		uint64_t illegal_sender			: 1;	/* 9 */
+		uint64_t wrong_demand			: 1;	/* 8 */
+		uint64_t uncorrectable_mtag_error	: 1;	/* 7 */
+		uint64_t uncorrectable_data_error	: 1;	/* 6 */
+		uint64_t correctable_mtag_error		: 1;	/* 5 */
+		uint64_t correctable_data_error		: 1;	/* 4 */
+		uint64_t mtag_mismatch_within_hcl	: 1;	/* 3 */
+		uint64_t mtag_mismatch_between_hcls	: 1;	/* 2 */
+		uint64_t unexpected_mtag		: 1;	/* 1 */
+		uint64_t timeout			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sa_esr_0_u;
+
+#define	wci_sa_esr_0_acc_hw_err	\
+	bit.acc_hw_err
+#define	wci_sa_esr_0_acc_address_not_owned	\
+	bit.acc_address_not_owned
+#define	wci_sa_esr_0_acc_address_not_mapped	\
+	bit.acc_address_not_mapped
+#define	wci_sa_esr_0_acc_ga2lpa_ecc_error	\
+	bit.acc_ga2lpa_ecc_error
+#define	wci_sa_esr_0_acc_rip_multi_hit	\
+	bit.acc_rip_multi_hit
+#define	wci_sa_esr_0_acc_illegal_sender	\
+	bit.acc_illegal_sender
+#define	wci_sa_esr_0_acc_wrong_demand	\
+	bit.acc_wrong_demand
+#define	wci_sa_esr_0_acc_uncorrectable_mtag_error	\
+	bit.acc_uncorrectable_mtag_error
+#define	wci_sa_esr_0_acc_uncorrectable_data_error	\
+	bit.acc_uncorrectable_data_error
+#define	wci_sa_esr_0_acc_correctable_mtag_error	\
+	bit.acc_correctable_mtag_error
+#define	wci_sa_esr_0_acc_correctable_data_error	\
+	bit.acc_correctable_data_error
+#define	wci_sa_esr_0_acc_mtag_mismatch_within_hcl	\
+	bit.acc_mtag_mismatch_within_hcl
+#define	wci_sa_esr_0_acc_mtag_mismatch_between_hcls	\
+	bit.acc_mtag_mismatch_between_hcls
+#define	wci_sa_esr_0_acc_unexpected_mtag	\
+	bit.acc_unexpected_mtag
+#define	wci_sa_esr_0_acc_timeout	\
+	bit.acc_timeout
+#define	wci_sa_esr_0_first_error	\
+	bit.first_error
+#define	wci_sa_esr_0_hw_err	\
+	bit.hw_err
+#define	wci_sa_esr_0_address_not_owned	\
+	bit.address_not_owned
+#define	wci_sa_esr_0_address_not_mapped	\
+	bit.address_not_mapped
+#define	wci_sa_esr_0_ga2lpa_ecc_error	\
+	bit.ga2lpa_ecc_error
+#define	wci_sa_esr_0_rip_multi_hit	\
+	bit.rip_multi_hit
+#define	wci_sa_esr_0_illegal_sender	\
+	bit.illegal_sender
+#define	wci_sa_esr_0_wrong_demand	\
+	bit.wrong_demand
+#define	wci_sa_esr_0_uncorrectable_mtag_error	\
+	bit.uncorrectable_mtag_error
+#define	wci_sa_esr_0_uncorrectable_data_error	\
+	bit.uncorrectable_data_error
+#define	wci_sa_esr_0_correctable_mtag_error	\
+	bit.correctable_mtag_error
+#define	wci_sa_esr_0_correctable_data_error	\
+	bit.correctable_data_error
+#define	wci_sa_esr_0_mtag_mismatch_within_hcl	\
+	bit.mtag_mismatch_within_hcl
+#define	wci_sa_esr_0_mtag_mismatch_between_hcls	\
+	bit.mtag_mismatch_between_hcls
+#define	wci_sa_esr_0_unexpected_mtag	\
+	bit.unexpected_mtag
+#define	wci_sa_esr_0_timeout	\
+	bit.timeout
+
+
+/*
+ * wci_sa_hw_err_state
+ */
+typedef union {
+	struct wci_sa_hw_err_state {
+		uint64_t rsvd_z				: 56;	/* 63:8 */
+		uint64_t sh_queue_overflow		: 1;	/* 7 */
+		uint64_t sh_wrong_stid			: 1;	/* 6 */
+		uint64_t sh_unexpected_snoop		: 1;	/* 5 */
+		uint64_t oh_queue_overflow		: 1;	/* 4 */
+		uint64_t oh_wrong_stid			: 1;	/* 3 */
+		uint64_t oh_unexpected_ordered		: 1;	/* 2 */
+		uint64_t unexpected_send_ack		: 1;	/* 1 */
+		uint64_t unexpected_receive_ack		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sa_hw_err_state_u;
+
+#define	wci_sa_hw_err_state_sh_queue_overflow	\
+	bit.sh_queue_overflow
+#define	wci_sa_hw_err_state_sh_wrong_stid	\
+	bit.sh_wrong_stid
+#define	wci_sa_hw_err_state_sh_unexpected_snoop	\
+	bit.sh_unexpected_snoop
+#define	wci_sa_hw_err_state_oh_queue_overflow	\
+	bit.oh_queue_overflow
+#define	wci_sa_hw_err_state_oh_wrong_stid	\
+	bit.oh_wrong_stid
+#define	wci_sa_hw_err_state_oh_unexpected_ordered	\
+	bit.oh_unexpected_ordered
+#define	wci_sa_hw_err_state_unexpected_send_ack	\
+	bit.unexpected_send_ack
+#define	wci_sa_hw_err_state_unexpected_receive_ack	\
+	bit.unexpected_receive_ack
+
+
+/*
+ * wci_sa_esr_mask
+ */
+typedef union {
+	struct wci_sa_esr_mask {
+		uint64_t rsvd_z				: 49;	/* 63:15 */
+		uint64_t hw_err				: 1;	/* 14 */
+		uint64_t address_not_owned		: 1;	/* 13 */
+		uint64_t address_not_mapped		: 1;	/* 12 */
+		uint64_t ga2lpa_ecc_error		: 1;	/* 11 */
+		uint64_t rip_multi_hit			: 1;	/* 10 */
+		uint64_t illegal_sender			: 1;	/* 9 */
+		uint64_t wrong_demand			: 1;	/* 8 */
+		uint64_t uncorrectable_mtag_error	: 1;	/* 7 */
+		uint64_t uncorrectable_data_error	: 1;	/* 6 */
+		uint64_t correctable_mtag_error		: 1;	/* 5 */
+		uint64_t correctable_data_error		: 1;	/* 4 */
+		uint64_t mtag_mismatch_within_hcl	: 1;	/* 3 */
+		uint64_t mtag_mismatch_between_hcls	: 1;	/* 2 */
+		uint64_t unexpected_mtag		: 1;	/* 1 */
+		uint64_t timeout			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sa_esr_mask_u;
+
+#define	wci_sa_esr_mask_hw_err	\
+	bit.hw_err
+#define	wci_sa_esr_mask_address_not_owned	\
+	bit.address_not_owned
+#define	wci_sa_esr_mask_address_not_mapped	\
+	bit.address_not_mapped
+#define	wci_sa_esr_mask_ga2lpa_ecc_error	\
+	bit.ga2lpa_ecc_error
+#define	wci_sa_esr_mask_rip_multi_hit	\
+	bit.rip_multi_hit
+#define	wci_sa_esr_mask_illegal_sender	\
+	bit.illegal_sender
+#define	wci_sa_esr_mask_wrong_demand	\
+	bit.wrong_demand
+#define	wci_sa_esr_mask_uncorrectable_mtag_error	\
+	bit.uncorrectable_mtag_error
+#define	wci_sa_esr_mask_uncorrectable_data_error	\
+	bit.uncorrectable_data_error
+#define	wci_sa_esr_mask_correctable_mtag_error	\
+	bit.correctable_mtag_error
+#define	wci_sa_esr_mask_correctable_data_error	\
+	bit.correctable_data_error
+#define	wci_sa_esr_mask_mtag_mismatch_within_hcl	\
+	bit.mtag_mismatch_within_hcl
+#define	wci_sa_esr_mask_mtag_mismatch_between_hcls	\
+	bit.mtag_mismatch_between_hcls
+#define	wci_sa_esr_mask_unexpected_mtag	\
+	bit.unexpected_mtag
+#define	wci_sa_esr_mask_timeout	\
+	bit.timeout
+
+
+/*
+ * wci_sa_status_array
+ */
+typedef union {
+	struct wci_sa_status_array {
+		uint64_t rsvd_z				: 43;	/* 63:21 */
+		uint64_t receive_count			: 2;	/* 20:19 */
+		uint64_t send_count			: 3;	/* 18:16 */
+		uint64_t owned				: 1;	/* 15 */
+		uint64_t first_mtag			: 3;	/* 14:12 */
+		uint64_t atransid_3_0			: 4;	/* 11:8 */
+		uint64_t rsvd_y				: 2;	/* 7:6 */
+		uint64_t ga2lpa_status			: 2;	/* 5:4 */
+		uint64_t msgop				: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_sa_status_array_u;
+
+#define	wci_sa_status_array_receive_count	\
+	bit.receive_count
+#define	wci_sa_status_array_send_count	\
+	bit.send_count
+#define	wci_sa_status_array_owned	\
+	bit.owned
+#define	wci_sa_status_array_first_mtag	\
+	bit.first_mtag
+#define	wci_sa_status_array_atransid_3_0	\
+	bit.atransid_3_0
+#define	wci_sa_status_array_ga2lpa_status	\
+	bit.ga2lpa_status
+#define	wci_sa_status_array_msgop	\
+	bit.msgop
+
+
+/*
+ * wci_sa_status_2_array
+ */
+typedef union {
+	struct wci_sa_status_2_array {
+		uint64_t rsvd_z				: 53;	/* 63:11 */
+		uint64_t send_done			: 1;	/* 10 */
+		uint64_t ph_done			: 1;	/* 9 */
+		uint64_t got_2nd_snoop			: 1;	/* 8 */
+		uint64_t got_1st_snoop			: 1;	/* 7 */
+		uint64_t got_2nd_ord			: 1;	/* 6 */
+		uint64_t got_1st_ord			: 1;	/* 5 */
+		uint64_t sf_3_done			: 1;	/* 4 */
+		uint64_t sf_2_done			: 1;	/* 3 */
+		uint64_t dsh_done			: 1;	/* 2 */
+		uint64_t drh_done			: 1;	/* 1 */
+		uint64_t req_done			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sa_status_2_array_u;
+
+#define	wci_sa_status_2_array_send_done	\
+	bit.send_done
+#define	wci_sa_status_2_array_ph_done	\
+	bit.ph_done
+#define	wci_sa_status_2_array_got_2nd_snoop	\
+	bit.got_2nd_snoop
+#define	wci_sa_status_2_array_got_1st_snoop	\
+	bit.got_1st_snoop
+#define	wci_sa_status_2_array_got_2nd_ord	\
+	bit.got_2nd_ord
+#define	wci_sa_status_2_array_got_1st_ord	\
+	bit.got_1st_ord
+#define	wci_sa_status_2_array_sf_3_done	\
+	bit.sf_3_done
+#define	wci_sa_status_2_array_sf_2_done	\
+	bit.sf_2_done
+#define	wci_sa_status_2_array_dsh_done	\
+	bit.dsh_done
+#define	wci_sa_status_2_array_drh_done	\
+	bit.drh_done
+#define	wci_sa_status_2_array_req_done	\
+	bit.req_done
+
+
+/*
+ * wci_sa_status_3_array
+ */
+typedef union {
+	struct wci_sa_status_3_array {
+		uint64_t rsvd_z				: 51;	/* 63:13 */
+		uint64_t ntransid			: 9;	/* 12:4 */
+		uint64_t snid				: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_sa_status_3_array_u;
+
+#define	wci_sa_status_3_array_ntransid	\
+	bit.ntransid
+#define	wci_sa_status_3_array_snid	\
+	bit.snid
+
+
+/*
+ * wci_sa_status_4_array
+ */
+typedef union {
+	struct wci_sa_status_4_array {
+		uint64_t rsvd_z				: 31;	/* 63:33 */
+		uint64_t otransid			: 9;	/* 32:24 */
+		uint64_t rnid				: 4;	/* 23:20 */
+		uint64_t replies_2_exp			: 4;	/* 19:16 */
+		uint64_t htid				: 4;	/* 15:12 */
+		uint64_t rsvd_y				: 3;	/* 11:9 */
+		uint64_t rtid				: 5;	/* 8:4 */
+		uint64_t rsvd_x				: 2;	/* 3:2 */
+		uint64_t emiss				: 1;	/* 1 */
+		uint64_t stripe				: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sa_status_4_array_u;
+
+#define	wci_sa_status_4_array_otransid	\
+	bit.otransid
+#define	wci_sa_status_4_array_rnid	\
+	bit.rnid
+#define	wci_sa_status_4_array_replies_2_exp	\
+	bit.replies_2_exp
+#define	wci_sa_status_4_array_htid	\
+	bit.htid
+#define	wci_sa_status_4_array_rtid	\
+	bit.rtid
+#define	wci_sa_status_4_array_emiss	\
+	bit.emiss
+#define	wci_sa_status_4_array_stripe	\
+	bit.stripe
+
+
+/*
+ * wci_sa_status_5_array
+ */
+typedef union {
+	struct wci_sa_status_5_array {
+		uint64_t rsvd_z				: 21;	/* 63:43 */
+		uint64_t original_ga			: 30;	/* 42:13 */
+		uint64_t rsvd_y				: 12;	/* 12:1 */
+		uint64_t cmr				: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sa_status_5_array_u;
+
+#define	wci_sa_status_5_array_original_ga	\
+	bit.original_ga
+#define	wci_sa_status_5_array_cmr	\
+	bit.cmr
+
+
+/*
+ * wci_sa_status_6_array
+ */
+typedef union {
+	struct wci_sa_status_6_array {
+		uint64_t rsvd_z				: 21;	/* 63:43 */
+		uint64_t safari_addr_42			: 1;	/* 42 */
+		uint64_t safari_addr_41_38		: 4;	/* 41:38 */
+		uint64_t safari_addr_37			: 1;	/* 37 */
+		uint64_t safari_addr_36_5		: 32;	/* 36:5 */
+		uint64_t rsvd_y				: 5;	/* 4:0 */
+	} bit;
+	uint64_t val;
+} wci_sa_status_6_array_u;
+
+#define	wci_sa_status_6_array_safari_addr_42	\
+	bit.safari_addr_42
+#define	wci_sa_status_6_array_safari_addr_41_38	\
+	bit.safari_addr_41_38
+#define	wci_sa_status_6_array_safari_addr_37	\
+	bit.safari_addr_37
+#define	wci_sa_status_6_array_safari_addr_36_5	\
+	bit.safari_addr_36_5
+
+
+/*
+ * wci_sag_route_map0
+ */
+typedef union {
+	struct wci_sag_route_map0 {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_sag_route_map0_u;
+
+#define	wci_sag_route_map0_node15_tlink	\
+	bit.node15_tlink
+#define	wci_sag_route_map0_node14_tlink	\
+	bit.node14_tlink
+#define	wci_sag_route_map0_node13_tlink	\
+	bit.node13_tlink
+#define	wci_sag_route_map0_node12_tlink	\
+	bit.node12_tlink
+#define	wci_sag_route_map0_node11_tlink	\
+	bit.node11_tlink
+#define	wci_sag_route_map0_node10_tlink	\
+	bit.node10_tlink
+#define	wci_sag_route_map0_node9_tlink	\
+	bit.node9_tlink
+#define	wci_sag_route_map0_node8_tlink	\
+	bit.node8_tlink
+#define	wci_sag_route_map0_node7_tlink	\
+	bit.node7_tlink
+#define	wci_sag_route_map0_node6_tlink	\
+	bit.node6_tlink
+#define	wci_sag_route_map0_node5_tlink	\
+	bit.node5_tlink
+#define	wci_sag_route_map0_node4_tlink	\
+	bit.node4_tlink
+#define	wci_sag_route_map0_node3_tlink	\
+	bit.node3_tlink
+#define	wci_sag_route_map0_node2_tlink	\
+	bit.node2_tlink
+#define	wci_sag_route_map0_node1_tlink	\
+	bit.node1_tlink
+#define	wci_sag_route_map0_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_sag_route_map1
+ */
+typedef union {
+	struct wci_sag_route_map1 {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_sag_route_map1_u;
+
+#define	wci_sag_route_map1_node15_tlink	\
+	bit.node15_tlink
+#define	wci_sag_route_map1_node14_tlink	\
+	bit.node14_tlink
+#define	wci_sag_route_map1_node13_tlink	\
+	bit.node13_tlink
+#define	wci_sag_route_map1_node12_tlink	\
+	bit.node12_tlink
+#define	wci_sag_route_map1_node11_tlink	\
+	bit.node11_tlink
+#define	wci_sag_route_map1_node10_tlink	\
+	bit.node10_tlink
+#define	wci_sag_route_map1_node9_tlink	\
+	bit.node9_tlink
+#define	wci_sag_route_map1_node8_tlink	\
+	bit.node8_tlink
+#define	wci_sag_route_map1_node7_tlink	\
+	bit.node7_tlink
+#define	wci_sag_route_map1_node6_tlink	\
+	bit.node6_tlink
+#define	wci_sag_route_map1_node5_tlink	\
+	bit.node5_tlink
+#define	wci_sag_route_map1_node4_tlink	\
+	bit.node4_tlink
+#define	wci_sag_route_map1_node3_tlink	\
+	bit.node3_tlink
+#define	wci_sag_route_map1_node2_tlink	\
+	bit.node2_tlink
+#define	wci_sag_route_map1_node1_tlink	\
+	bit.node1_tlink
+#define	wci_sag_route_map1_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_nc2nid_array
+ */
+typedef union {
+	struct wci_nc2nid_array {
+		uint64_t rsvd_z				: 56;	/* 63:8 */
+		uint64_t no_stripe			: 1;	/* 7 */
+		uint64_t encode_cluster_origin_tag	: 1;	/* 6 */
+		uint64_t launch_remote			: 1;	/* 5 */
+		uint64_t launch_local_sram		: 1;	/* 4 */
+		uint64_t dest_node_id			: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_nc2nid_array_u;
+
+#define	wci_nc2nid_array_no_stripe	\
+	bit.no_stripe
+#define	wci_nc2nid_array_encode_cluster_origin_tag	\
+	bit.encode_cluster_origin_tag
+#define	wci_nc2nid_array_launch_remote	\
+	bit.launch_remote
+#define	wci_nc2nid_array_launch_local_sram	\
+	bit.launch_local_sram
+#define	wci_nc2nid_array_dest_node_id	\
+	bit.dest_node_id
+
+
+/*
+ * wci_sfi_transid_alloc
+ */
+typedef union {
+	struct wci_sfi_transid_alloc {
+		uint64_t rsvd_z				: 33;	/* 63:31 */
+		uint64_t targid_available		: 15;	/* 30:16 */
+		uint64_t atransid_available		: 15;	/* 15:1 */
+		uint64_t rsvd_y				: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sfi_transid_alloc_u;
+
+#define	wci_sfi_transid_alloc_targid_available	\
+	bit.targid_available
+#define	wci_sfi_transid_alloc_atransid_available	\
+	bit.atransid_available
+
+
+/*
+ * wci_sfi_esr
+ */
+typedef union {
+	struct wci_sfi_esr {
+		uint64_t rsvd_z				: 38;	/* 63:26 */
+		uint64_t acc_targid_timeout		: 1;	/* 25 */
+		uint64_t acc_nc2nid_misconfig		: 1;	/* 24 */
+		uint64_t acc_addr_pty			: 1;	/* 23 */
+		uint64_t acc_incoming_prereq_conflict	: 1;	/* 22 */
+		uint64_t acc_modcam_clr_set_conflict	: 1;	/* 21 */
+		uint64_t acc_modcam_multi_hit		: 1;	/* 20 */
+		uint64_t acc_modcam_set_set		: 1;	/* 19 */
+		uint64_t acc_unexpected_incoming	: 1;	/* 18 */
+		uint64_t acc_unexpected_targarbgnt	: 1;	/* 17 */
+		uint64_t acc_transid_unalloc_released	: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t rsvd_y				: 5;	/* 14:10 */
+		uint64_t targid_timeout			: 1;	/* 9 */
+		uint64_t nc2nid_misconfig		: 1;	/* 8 */
+		uint64_t addr_pty			: 1;	/* 7 */
+		uint64_t incoming_prereq_conflict	: 1;	/* 6 */
+		uint64_t modcam_clr_set_conflict	: 1;	/* 5 */
+		uint64_t modcam_multi_hit		: 1;	/* 4 */
+		uint64_t modcam_set_set			: 1;	/* 3 */
+		uint64_t unexpected_incoming		: 1;	/* 2 */
+		uint64_t unexpected_targarbgnt		: 1;	/* 1 */
+		uint64_t transid_unalloc_released	: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sfi_esr_u;
+
+#define	wci_sfi_esr_acc_targid_timeout	\
+	bit.acc_targid_timeout
+#define	wci_sfi_esr_acc_nc2nid_misconfig	\
+	bit.acc_nc2nid_misconfig
+#define	wci_sfi_esr_acc_addr_pty	\
+	bit.acc_addr_pty
+#define	wci_sfi_esr_acc_incoming_prereq_conflict	\
+	bit.acc_incoming_prereq_conflict
+#define	wci_sfi_esr_acc_modcam_clr_set_conflict	\
+	bit.acc_modcam_clr_set_conflict
+#define	wci_sfi_esr_acc_modcam_multi_hit	\
+	bit.acc_modcam_multi_hit
+#define	wci_sfi_esr_acc_modcam_set_set	\
+	bit.acc_modcam_set_set
+#define	wci_sfi_esr_acc_unexpected_incoming	\
+	bit.acc_unexpected_incoming
+#define	wci_sfi_esr_acc_unexpected_targarbgnt	\
+	bit.acc_unexpected_targarbgnt
+#define	wci_sfi_esr_acc_transid_unalloc_released	\
+	bit.acc_transid_unalloc_released
+#define	wci_sfi_esr_first_error	\
+	bit.first_error
+#define	wci_sfi_esr_targid_timeout	\
+	bit.targid_timeout
+#define	wci_sfi_esr_nc2nid_misconfig	\
+	bit.nc2nid_misconfig
+#define	wci_sfi_esr_addr_pty	\
+	bit.addr_pty
+#define	wci_sfi_esr_incoming_prereq_conflict	\
+	bit.incoming_prereq_conflict
+#define	wci_sfi_esr_modcam_clr_set_conflict	\
+	bit.modcam_clr_set_conflict
+#define	wci_sfi_esr_modcam_multi_hit	\
+	bit.modcam_multi_hit
+#define	wci_sfi_esr_modcam_set_set	\
+	bit.modcam_set_set
+#define	wci_sfi_esr_unexpected_incoming	\
+	bit.unexpected_incoming
+#define	wci_sfi_esr_unexpected_targarbgnt	\
+	bit.unexpected_targarbgnt
+#define	wci_sfi_esr_transid_unalloc_released	\
+	bit.transid_unalloc_released
+
+
+/*
+ * wci_sfi_esr_mask
+ */
+typedef union {
+	struct wci_sfi_esr_mask {
+		uint64_t rsvd_z				: 54;	/* 63:10 */
+		uint64_t targid_timeout			: 1;	/* 9 */
+		uint64_t nc2nid_misconfig		: 1;	/* 8 */
+		uint64_t addr_pty			: 1;	/* 7 */
+		uint64_t incoming_prereq_conflict	: 1;	/* 6 */
+		uint64_t modcam_clr_set_conflict	: 1;	/* 5 */
+		uint64_t modcam_multi_hit		: 1;	/* 4 */
+		uint64_t modcam_set_set			: 1;	/* 3 */
+		uint64_t unexpected_incoming		: 1;	/* 2 */
+		uint64_t unexpected_targarbgnt		: 1;	/* 1 */
+		uint64_t transid_unalloc_released	: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sfi_esr_mask_u;
+
+#define	wci_sfi_esr_mask_targid_timeout	\
+	bit.targid_timeout
+#define	wci_sfi_esr_mask_nc2nid_misconfig	\
+	bit.nc2nid_misconfig
+#define	wci_sfi_esr_mask_addr_pty	\
+	bit.addr_pty
+#define	wci_sfi_esr_mask_incoming_prereq_conflict	\
+	bit.incoming_prereq_conflict
+#define	wci_sfi_esr_mask_modcam_clr_set_conflict	\
+	bit.modcam_clr_set_conflict
+#define	wci_sfi_esr_mask_modcam_multi_hit	\
+	bit.modcam_multi_hit
+#define	wci_sfi_esr_mask_modcam_set_set	\
+	bit.modcam_set_set
+#define	wci_sfi_esr_mask_unexpected_incoming	\
+	bit.unexpected_incoming
+#define	wci_sfi_esr_mask_unexpected_targarbgnt	\
+	bit.unexpected_targarbgnt
+#define	wci_sfi_esr_mask_transid_unalloc_released	\
+	bit.transid_unalloc_released
+
+
+/*
+ * wci_sfi_state
+ */
+typedef union {
+	struct wci_sfi_state {
+		uint64_t rsvd_z				: 1;	/* 63 */
+		uint64_t esr_index			: 4;	/* 62:59 */
+		uint64_t rsvd_y				: 10;	/* 58:49 */
+		uint64_t wci_issued			: 1;	/* 48 */
+		uint64_t agent_id			: 7;	/* 47:41 */
+		uint64_t modcam_index			: 4;	/* 40:37 */
+		uint64_t modcam_addr			: 31;	/* 36:6 */
+		uint64_t sf_cmd				: 2;	/* 5:4 */
+		uint64_t sf_mask_3_to_0			: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_sfi_state_u;
+
+#define	wci_sfi_state_esr_index	\
+	bit.esr_index
+#define	wci_sfi_state_wci_issued	\
+	bit.wci_issued
+#define	wci_sfi_state_agent_id	\
+	bit.agent_id
+#define	wci_sfi_state_modcam_index	\
+	bit.modcam_index
+#define	wci_sfi_state_modcam_addr	\
+	bit.modcam_addr
+#define	wci_sfi_state_sf_cmd	\
+	bit.sf_cmd
+#define	wci_sfi_state_sf_mask_3_to_0	\
+	bit.sf_mask_3_to_0
+
+
+/*
+ * wci_sfi_state1
+ */
+typedef union {
+	struct wci_sfi_state1 {
+		uint64_t rsvd_z				: 1;	/* 63 */
+		uint64_t esr_index			: 4;	/* 62:59 */
+		uint64_t rsvd_y				: 8;	/* 58:51 */
+		uint64_t unalloc_release_agents		: 5;	/* 50:46 */
+		uint64_t unalloc_targids_released	: 15;	/* 45:31 */
+		uint64_t unalloc_atransids_released	: 15;	/* 30:16 */
+		uint64_t nc2nid_index			: 8;	/* 15:8 */
+		uint64_t nc2nid_data			: 8;	/* 7:0 */
+	} bit;
+	uint64_t val;
+} wci_sfi_state1_u;
+
+#define	wci_sfi_state1_esr_index	\
+	bit.esr_index
+#define	wci_sfi_state1_unalloc_release_agents	\
+	bit.unalloc_release_agents
+#define	wci_sfi_state1_unalloc_targids_released	\
+	bit.unalloc_targids_released
+#define	wci_sfi_state1_unalloc_atransids_released	\
+	bit.unalloc_atransids_released
+#define	wci_sfi_state1_nc2nid_index	\
+	bit.nc2nid_index
+#define	wci_sfi_state1_nc2nid_data	\
+	bit.nc2nid_data
+
+
+/*
+ * wci_sfi_ctr1_mask
+ */
+typedef union {
+	struct wci_sfi_ctr1_mask {
+		uint64_t rsvd_z				: 6;	/* 63:58 */
+		uint64_t mask				: 10;	/* 57:48 */
+		uint64_t atransid			: 9;	/* 47:39 */
+		uint64_t address			: 39;	/* 38:0 */
+	} bit;
+	uint64_t val;
+} wci_sfi_ctr1_mask_u;
+
+#define	wci_sfi_ctr1_mask_mask	\
+	bit.mask
+#define	wci_sfi_ctr1_mask_atransid	\
+	bit.atransid
+#define	wci_sfi_ctr1_mask_address	\
+	bit.address
+
+
+/*
+ * wci_sfi_ctr1_match_transaction
+ */
+typedef union {
+	struct wci_sfi_ctr1_match_transaction {
+		uint64_t rsvd_z				: 45;	/* 63:19 */
+		uint64_t rts				: 1;	/* 18 */
+		uint64_t rto				: 1;	/* 17 */
+		uint64_t rs				: 1;	/* 16 */
+		uint64_t ws				: 1;	/* 15 */
+		uint64_t rtsr				: 1;	/* 14 */
+		uint64_t rtor				: 1;	/* 13 */
+		uint64_t rsr				: 1;	/* 12 */
+		uint64_t wb				: 1;	/* 11 */
+		uint64_t rtsm				: 1;	/* 10 */
+		uint64_t interrupt			: 1;	/* 9 */
+		uint64_t r_rts				: 1;	/* 8 */
+		uint64_t r_rto				: 1;	/* 7 */
+		uint64_t r_rs				: 1;	/* 6 */
+		uint64_t r_ws				: 1;	/* 5 */
+		uint64_t r_wb				: 1;	/* 4 */
+		uint64_t rbio				: 1;	/* 3 */
+		uint64_t rio				: 1;	/* 2 */
+		uint64_t wbio				: 1;	/* 1 */
+		uint64_t wio				: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sfi_ctr1_match_transaction_u;
+
+#define	wci_sfi_ctr1_match_transaction_rts	\
+	bit.rts
+#define	wci_sfi_ctr1_match_transaction_rto	\
+	bit.rto
+#define	wci_sfi_ctr1_match_transaction_rs	\
+	bit.rs
+#define	wci_sfi_ctr1_match_transaction_ws	\
+	bit.ws
+#define	wci_sfi_ctr1_match_transaction_rtsr	\
+	bit.rtsr
+#define	wci_sfi_ctr1_match_transaction_rtor	\
+	bit.rtor
+#define	wci_sfi_ctr1_match_transaction_rsr	\
+	bit.rsr
+#define	wci_sfi_ctr1_match_transaction_wb	\
+	bit.wb
+#define	wci_sfi_ctr1_match_transaction_rtsm	\
+	bit.rtsm
+#define	wci_sfi_ctr1_match_transaction_interrupt	\
+	bit.interrupt
+#define	wci_sfi_ctr1_match_transaction_r_rts	\
+	bit.r_rts
+#define	wci_sfi_ctr1_match_transaction_r_rto	\
+	bit.r_rto
+#define	wci_sfi_ctr1_match_transaction_r_rs	\
+	bit.r_rs
+#define	wci_sfi_ctr1_match_transaction_r_ws	\
+	bit.r_ws
+#define	wci_sfi_ctr1_match_transaction_r_wb	\
+	bit.r_wb
+#define	wci_sfi_ctr1_match_transaction_rbio	\
+	bit.rbio
+#define	wci_sfi_ctr1_match_transaction_rio	\
+	bit.rio
+#define	wci_sfi_ctr1_match_transaction_wbio	\
+	bit.wbio
+#define	wci_sfi_ctr1_match_transaction_wio	\
+	bit.wio
+
+
+/*
+ * wci_sfi_ctr1_match
+ */
+typedef union {
+	struct wci_sfi_ctr1_match {
+		uint64_t rsvd_z				: 6;	/* 63:58 */
+		uint64_t mask				: 10;	/* 57:48 */
+		uint64_t atransid			: 9;	/* 47:39 */
+		uint64_t address			: 39;	/* 38:0 */
+	} bit;
+	uint64_t val;
+} wci_sfi_ctr1_match_u;
+
+#define	wci_sfi_ctr1_match_mask	\
+	bit.mask
+#define	wci_sfi_ctr1_match_atransid	\
+	bit.atransid
+#define	wci_sfi_ctr1_match_address	\
+	bit.address
+
+
+/*
+ * wci_sfi_ctr0_mask
+ */
+typedef union {
+	struct wci_sfi_ctr0_mask {
+		uint64_t rsvd_z				: 6;	/* 63:58 */
+		uint64_t mask				: 10;	/* 57:48 */
+		uint64_t atransid			: 9;	/* 47:39 */
+		uint64_t address			: 39;	/* 38:0 */
+	} bit;
+	uint64_t val;
+} wci_sfi_ctr0_mask_u;
+
+#define	wci_sfi_ctr0_mask_mask	\
+	bit.mask
+#define	wci_sfi_ctr0_mask_atransid	\
+	bit.atransid
+#define	wci_sfi_ctr0_mask_address	\
+	bit.address
+
+
+/*
+ * wci_sfi_ctr0_match_transaction
+ */
+typedef union {
+	struct wci_sfi_ctr0_match_transaction {
+		uint64_t rsvd_z				: 45;	/* 63:19 */
+		uint64_t rts				: 1;	/* 18 */
+		uint64_t rto				: 1;	/* 17 */
+		uint64_t rs				: 1;	/* 16 */
+		uint64_t ws				: 1;	/* 15 */
+		uint64_t rtsr				: 1;	/* 14 */
+		uint64_t rtor				: 1;	/* 13 */
+		uint64_t rsr				: 1;	/* 12 */
+		uint64_t wb				: 1;	/* 11 */
+		uint64_t rtsm				: 1;	/* 10 */
+		uint64_t interrupt			: 1;	/* 9 */
+		uint64_t r_rts				: 1;	/* 8 */
+		uint64_t r_rto				: 1;	/* 7 */
+		uint64_t r_rs				: 1;	/* 6 */
+		uint64_t r_ws				: 1;	/* 5 */
+		uint64_t r_wb				: 1;	/* 4 */
+		uint64_t rbio				: 1;	/* 3 */
+		uint64_t rio				: 1;	/* 2 */
+		uint64_t wbio				: 1;	/* 1 */
+		uint64_t wio				: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sfi_ctr0_match_transaction_u;
+
+#define	wci_sfi_ctr0_match_transaction_rts	\
+	bit.rts
+#define	wci_sfi_ctr0_match_transaction_rto	\
+	bit.rto
+#define	wci_sfi_ctr0_match_transaction_rs	\
+	bit.rs
+#define	wci_sfi_ctr0_match_transaction_ws	\
+	bit.ws
+#define	wci_sfi_ctr0_match_transaction_rtsr	\
+	bit.rtsr
+#define	wci_sfi_ctr0_match_transaction_rtor	\
+	bit.rtor
+#define	wci_sfi_ctr0_match_transaction_rsr	\
+	bit.rsr
+#define	wci_sfi_ctr0_match_transaction_wb	\
+	bit.wb
+#define	wci_sfi_ctr0_match_transaction_rtsm	\
+	bit.rtsm
+#define	wci_sfi_ctr0_match_transaction_interrupt	\
+	bit.interrupt
+#define	wci_sfi_ctr0_match_transaction_r_rts	\
+	bit.r_rts
+#define	wci_sfi_ctr0_match_transaction_r_rto	\
+	bit.r_rto
+#define	wci_sfi_ctr0_match_transaction_r_rs	\
+	bit.r_rs
+#define	wci_sfi_ctr0_match_transaction_r_ws	\
+	bit.r_ws
+#define	wci_sfi_ctr0_match_transaction_r_wb	\
+	bit.r_wb
+#define	wci_sfi_ctr0_match_transaction_rbio	\
+	bit.rbio
+#define	wci_sfi_ctr0_match_transaction_rio	\
+	bit.rio
+#define	wci_sfi_ctr0_match_transaction_wbio	\
+	bit.wbio
+#define	wci_sfi_ctr0_match_transaction_wio	\
+	bit.wio
+
+
+/*
+ * wci_sfi_ctr0_match
+ */
+typedef union {
+	struct wci_sfi_ctr0_match {
+		uint64_t rsvd_z				: 6;	/* 63:58 */
+		uint64_t mask				: 10;	/* 57:48 */
+		uint64_t atransid			: 9;	/* 47:39 */
+		uint64_t address			: 39;	/* 38:0 */
+	} bit;
+	uint64_t val;
+} wci_sfi_ctr0_match_u;
+
+#define	wci_sfi_ctr0_match_mask	\
+	bit.mask
+#define	wci_sfi_ctr0_match_atransid	\
+	bit.atransid
+#define	wci_sfi_ctr0_match_address	\
+	bit.address
+
+
+/*
+ * wci_sfi_analyzer
+ */
+typedef union {
+	struct wci_sfi_analyzer {
+		uint64_t valid				: 1;	/* 63 */
+		uint64_t in_use				: 1;	/* 62 */
+		uint64_t shared				: 1;	/* 61 */
+		uint64_t owned				: 1;	/* 60 */
+		uint64_t mapped				: 1;	/* 59 */
+		uint64_t overflow			: 6;	/* 58:53 */
+		uint64_t address			: 39;	/* 52:14 */
+		uint64_t mask				: 4;	/* 13:10 */
+		uint64_t command			: 1;	/* 9 */
+		uint64_t atransid			: 9;	/* 8:0 */
+	} bit;
+	uint64_t val;
+} wci_sfi_analyzer_u;
+
+#define	wci_sfi_analyzer_valid	\
+	bit.valid
+#define	wci_sfi_analyzer_in_use	\
+	bit.in_use
+#define	wci_sfi_analyzer_shared	\
+	bit.shared
+#define	wci_sfi_analyzer_owned	\
+	bit.owned
+#define	wci_sfi_analyzer_mapped	\
+	bit.mapped
+#define	wci_sfi_analyzer_overflow	\
+	bit.overflow
+#define	wci_sfi_analyzer_address	\
+	bit.address
+#define	wci_sfi_analyzer_mask	\
+	bit.mask
+#define	wci_sfi_analyzer_command	\
+	bit.command
+#define	wci_sfi_analyzer_atransid	\
+	bit.atransid
+
+
+/*
+ * wci_sfi_route_map0
+ */
+typedef union {
+	struct wci_sfi_route_map0 {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_sfi_route_map0_u;
+
+#define	wci_sfi_route_map0_node15_tlink	\
+	bit.node15_tlink
+#define	wci_sfi_route_map0_node14_tlink	\
+	bit.node14_tlink
+#define	wci_sfi_route_map0_node13_tlink	\
+	bit.node13_tlink
+#define	wci_sfi_route_map0_node12_tlink	\
+	bit.node12_tlink
+#define	wci_sfi_route_map0_node11_tlink	\
+	bit.node11_tlink
+#define	wci_sfi_route_map0_node10_tlink	\
+	bit.node10_tlink
+#define	wci_sfi_route_map0_node9_tlink	\
+	bit.node9_tlink
+#define	wci_sfi_route_map0_node8_tlink	\
+	bit.node8_tlink
+#define	wci_sfi_route_map0_node7_tlink	\
+	bit.node7_tlink
+#define	wci_sfi_route_map0_node6_tlink	\
+	bit.node6_tlink
+#define	wci_sfi_route_map0_node5_tlink	\
+	bit.node5_tlink
+#define	wci_sfi_route_map0_node4_tlink	\
+	bit.node4_tlink
+#define	wci_sfi_route_map0_node3_tlink	\
+	bit.node3_tlink
+#define	wci_sfi_route_map0_node2_tlink	\
+	bit.node2_tlink
+#define	wci_sfi_route_map0_node1_tlink	\
+	bit.node1_tlink
+#define	wci_sfi_route_map0_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_sfi_route_map1
+ */
+typedef union {
+	struct wci_sfi_route_map1 {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_sfi_route_map1_u;
+
+#define	wci_sfi_route_map1_node15_tlink	\
+	bit.node15_tlink
+#define	wci_sfi_route_map1_node14_tlink	\
+	bit.node14_tlink
+#define	wci_sfi_route_map1_node13_tlink	\
+	bit.node13_tlink
+#define	wci_sfi_route_map1_node12_tlink	\
+	bit.node12_tlink
+#define	wci_sfi_route_map1_node11_tlink	\
+	bit.node11_tlink
+#define	wci_sfi_route_map1_node10_tlink	\
+	bit.node10_tlink
+#define	wci_sfi_route_map1_node9_tlink	\
+	bit.node9_tlink
+#define	wci_sfi_route_map1_node8_tlink	\
+	bit.node8_tlink
+#define	wci_sfi_route_map1_node7_tlink	\
+	bit.node7_tlink
+#define	wci_sfi_route_map1_node6_tlink	\
+	bit.node6_tlink
+#define	wci_sfi_route_map1_node5_tlink	\
+	bit.node5_tlink
+#define	wci_sfi_route_map1_node4_tlink	\
+	bit.node4_tlink
+#define	wci_sfi_route_map1_node3_tlink	\
+	bit.node3_tlink
+#define	wci_sfi_route_map1_node2_tlink	\
+	bit.node2_tlink
+#define	wci_sfi_route_map1_node1_tlink	\
+	bit.node1_tlink
+#define	wci_sfi_route_map1_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_qlim_sort_piq
+ */
+typedef union {
+	struct wci_qlim_sort_piq {
+		uint64_t rsvd_z				: 32;	/* 63:32 */
+		uint64_t dev_id_vec			: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_qlim_sort_piq_u;
+
+#define	wci_qlim_sort_piq_dev_id_vec	\
+	bit.dev_id_vec
+
+
+/*
+ * wci_qlim_sort_niq
+ */
+typedef union {
+	struct wci_qlim_sort_niq {
+		uint64_t rsvd_z				: 32;	/* 63:32 */
+		uint64_t dev_id_vec			: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_qlim_sort_niq_u;
+
+#define	wci_qlim_sort_niq_dev_id_vec	\
+	bit.dev_id_vec
+
+
+/*
+ * wci_qlim_sort_ciq
+ */
+typedef union {
+	struct wci_qlim_sort_ciq {
+		uint64_t rsvd_z				: 32;	/* 63:32 */
+		uint64_t dev_id_vec			: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_qlim_sort_ciq_u;
+
+#define	wci_qlim_sort_ciq_dev_id_vec	\
+	bit.dev_id_vec
+
+
+/*
+ * wci_link_esr
+ */
+typedef union {
+	struct wci_link_esr {
+		uint64_t rsvd_z				: 40;	/* 63:24 */
+		uint64_t acc_link_2_illegal_gnid	: 1;	/* 23 */
+		uint64_t acc_link_2_illegal_link	: 1;	/* 22 */
+		uint64_t rsvd_y				: 1;	/* 21 */
+		uint64_t acc_link_1_illegal_gnid	: 1;	/* 20 */
+		uint64_t acc_link_1_illegal_link	: 1;	/* 19 */
+		uint64_t rsvd_x				: 1;	/* 18 */
+		uint64_t acc_link_0_illegal_gnid	: 1;	/* 17 */
+		uint64_t acc_link_0_illegal_link	: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t rsvd_w				: 7;	/* 14:8 */
+		uint64_t link_2_illegal_gnid		: 1;	/* 7 */
+		uint64_t link_2_illegal_link		: 1;	/* 6 */
+		uint64_t rsvd_v				: 1;	/* 5 */
+		uint64_t link_1_illegal_gnid		: 1;	/* 4 */
+		uint64_t link_1_illegal_link		: 1;	/* 3 */
+		uint64_t rsvd_u				: 1;	/* 2 */
+		uint64_t link_0_illegal_gnid		: 1;	/* 1 */
+		uint64_t link_0_illegal_link		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_link_esr_u;
+
+#define	wci_link_esr_acc_link_2_illegal_gnid	\
+	bit.acc_link_2_illegal_gnid
+#define	wci_link_esr_acc_link_2_illegal_link	\
+	bit.acc_link_2_illegal_link
+#define	wci_link_esr_acc_link_1_illegal_gnid	\
+	bit.acc_link_1_illegal_gnid
+#define	wci_link_esr_acc_link_1_illegal_link	\
+	bit.acc_link_1_illegal_link
+#define	wci_link_esr_acc_link_0_illegal_gnid	\
+	bit.acc_link_0_illegal_gnid
+#define	wci_link_esr_acc_link_0_illegal_link	\
+	bit.acc_link_0_illegal_link
+#define	wci_link_esr_first_error	\
+	bit.first_error
+#define	wci_link_esr_link_2_illegal_gnid	\
+	bit.link_2_illegal_gnid
+#define	wci_link_esr_link_2_illegal_link	\
+	bit.link_2_illegal_link
+#define	wci_link_esr_link_1_illegal_gnid	\
+	bit.link_1_illegal_gnid
+#define	wci_link_esr_link_1_illegal_link	\
+	bit.link_1_illegal_link
+#define	wci_link_esr_link_0_illegal_gnid	\
+	bit.link_0_illegal_gnid
+#define	wci_link_esr_link_0_illegal_link	\
+	bit.link_0_illegal_link
+
+
+/*
+ * wci_link_esr_mask
+ */
+typedef union {
+	struct wci_link_esr_mask {
+		uint64_t rsvd_z				: 56;	/* 63:8 */
+		uint64_t link_2_illegal_gnid		: 1;	/* 7 */
+		uint64_t link_2_illegal_link		: 1;	/* 6 */
+		uint64_t rsvd_y				: 1;	/* 5 */
+		uint64_t link_1_illegal_gnid		: 1;	/* 4 */
+		uint64_t link_1_illegal_link		: 1;	/* 3 */
+		uint64_t rsvd_x				: 1;	/* 2 */
+		uint64_t link_0_illegal_gnid		: 1;	/* 1 */
+		uint64_t link_0_illegal_link		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_link_esr_mask_u;
+
+#define	wci_link_esr_mask_link_2_illegal_gnid	\
+	bit.link_2_illegal_gnid
+#define	wci_link_esr_mask_link_2_illegal_link	\
+	bit.link_2_illegal_link
+#define	wci_link_esr_mask_link_1_illegal_gnid	\
+	bit.link_1_illegal_gnid
+#define	wci_link_esr_mask_link_1_illegal_link	\
+	bit.link_1_illegal_link
+#define	wci_link_esr_mask_link_0_illegal_gnid	\
+	bit.link_0_illegal_gnid
+#define	wci_link_esr_mask_link_0_illegal_link	\
+	bit.link_0_illegal_link
+
+
+/*
+ * wci_sw_esr
+ */
+typedef union {
+	struct wci_sw_esr {
+		uint64_t rsvd_z				: 36;	/* 63:28 */
+		uint64_t acc_link_2_failover		: 1;	/* 27 */
+		uint64_t acc_link_1_failover		: 1;	/* 26 */
+		uint64_t acc_link_0_failover		: 1;	/* 25 */
+		uint64_t rsvd_y				: 2;	/* 24:23 */
+		uint64_t acc_link_2_auto_shut		: 1;	/* 22 */
+		uint64_t acc_link_1_auto_shut		: 1;	/* 21 */
+		uint64_t acc_link_0_auto_shut		: 1;	/* 20 */
+		uint64_t acc_addr_lpbk_illegal_gnid	: 1;	/* 19 */
+		uint64_t acc_error_pause_broadcast	: 1;	/* 18 */
+		uint64_t acc_addr_lpbk_fifo_ovf		: 1;	/* 17 */
+		uint64_t acc_data_lpbk_fifo_ovf		: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t rsvd_x				: 3;	/* 14:12 */
+		uint64_t link_2_failover		: 1;	/* 11 */
+		uint64_t link_1_failover		: 1;	/* 10 */
+		uint64_t link_0_failover		: 1;	/* 9 */
+		uint64_t rsvd_w				: 2;	/* 8:7 */
+		uint64_t link_2_auto_shut		: 1;	/* 6 */
+		uint64_t link_1_auto_shut		: 1;	/* 5 */
+		uint64_t link_0_auto_shut		: 1;	/* 4 */
+		uint64_t addr_lpbk_illegal_gnid		: 1;	/* 3 */
+		uint64_t error_pause_broadcast		: 1;	/* 2 */
+		uint64_t addr_lpbk_fifo_ovf		: 1;	/* 1 */
+		uint64_t data_lpbk_fifo_ovf		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sw_esr_u;
+
+#define	wci_sw_esr_acc_link_2_failover	\
+	bit.acc_link_2_failover
+#define	wci_sw_esr_acc_link_1_failover	\
+	bit.acc_link_1_failover
+#define	wci_sw_esr_acc_link_0_failover	\
+	bit.acc_link_0_failover
+#define	wci_sw_esr_acc_link_2_auto_shut	\
+	bit.acc_link_2_auto_shut
+#define	wci_sw_esr_acc_link_1_auto_shut	\
+	bit.acc_link_1_auto_shut
+#define	wci_sw_esr_acc_link_0_auto_shut	\
+	bit.acc_link_0_auto_shut
+#define	wci_sw_esr_acc_addr_lpbk_illegal_gnid	\
+	bit.acc_addr_lpbk_illegal_gnid
+#define	wci_sw_esr_acc_error_pause_broadcast	\
+	bit.acc_error_pause_broadcast
+#define	wci_sw_esr_acc_addr_lpbk_fifo_ovf	\
+	bit.acc_addr_lpbk_fifo_ovf
+#define	wci_sw_esr_acc_data_lpbk_fifo_ovf	\
+	bit.acc_data_lpbk_fifo_ovf
+#define	wci_sw_esr_first_error	\
+	bit.first_error
+#define	wci_sw_esr_link_2_failover	\
+	bit.link_2_failover
+#define	wci_sw_esr_link_1_failover	\
+	bit.link_1_failover
+#define	wci_sw_esr_link_0_failover	\
+	bit.link_0_failover
+#define	wci_sw_esr_link_2_auto_shut	\
+	bit.link_2_auto_shut
+#define	wci_sw_esr_link_1_auto_shut	\
+	bit.link_1_auto_shut
+#define	wci_sw_esr_link_0_auto_shut	\
+	bit.link_0_auto_shut
+#define	wci_sw_esr_addr_lpbk_illegal_gnid	\
+	bit.addr_lpbk_illegal_gnid
+#define	wci_sw_esr_error_pause_broadcast	\
+	bit.error_pause_broadcast
+#define	wci_sw_esr_addr_lpbk_fifo_ovf	\
+	bit.addr_lpbk_fifo_ovf
+#define	wci_sw_esr_data_lpbk_fifo_ovf	\
+	bit.data_lpbk_fifo_ovf
+
+
+/*
+ * wci_sw_esr_mask
+ */
+typedef union {
+	struct wci_sw_esr_mask {
+		uint64_t rsvd_z				: 52;	/* 63:12 */
+		uint64_t link_2_failover		: 1;	/* 11 */
+		uint64_t link_1_failover		: 1;	/* 10 */
+		uint64_t link_0_failover		: 1;	/* 9 */
+		uint64_t rsvd_y				: 2;	/* 8:7 */
+		uint64_t link_2_auto_shut		: 1;	/* 6 */
+		uint64_t link_1_auto_shut		: 1;	/* 5 */
+		uint64_t link_0_auto_shut		: 1;	/* 4 */
+		uint64_t addr_lpbk_illegal_gnid		: 1;	/* 3 */
+		uint64_t error_pause_broadcast		: 1;	/* 2 */
+		uint64_t addr_lpbk_fifo_ovf		: 1;	/* 1 */
+		uint64_t data_lpbk_fifo_ovf		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sw_esr_mask_u;
+
+#define	wci_sw_esr_mask_link_2_failover	\
+	bit.link_2_failover
+#define	wci_sw_esr_mask_link_1_failover	\
+	bit.link_1_failover
+#define	wci_sw_esr_mask_link_0_failover	\
+	bit.link_0_failover
+#define	wci_sw_esr_mask_link_2_auto_shut	\
+	bit.link_2_auto_shut
+#define	wci_sw_esr_mask_link_1_auto_shut	\
+	bit.link_1_auto_shut
+#define	wci_sw_esr_mask_link_0_auto_shut	\
+	bit.link_0_auto_shut
+#define	wci_sw_esr_mask_addr_lpbk_illegal_gnid	\
+	bit.addr_lpbk_illegal_gnid
+#define	wci_sw_esr_mask_error_pause_broadcast	\
+	bit.error_pause_broadcast
+#define	wci_sw_esr_mask_addr_lpbk_fifo_ovf	\
+	bit.addr_lpbk_fifo_ovf
+#define	wci_sw_esr_mask_data_lpbk_fifo_ovf	\
+	bit.data_lpbk_fifo_ovf
+
+
+/*
+ * wci_sw_link_control
+ */
+typedef union {
+	struct wci_sw_link_control {
+		uint64_t rsvd_z				: 9;	/* 63:55 */
+		uint64_t rexmit_freeze			: 1;	/* 54 */
+		uint64_t rexmit_mag			: 2;	/* 53:52 */
+		uint64_t rexmit_val			: 8;	/* 51:44 */
+		uint64_t error_inducement		: 2;	/* 43:42 */
+		uint64_t xmit_timeout			: 8;	/* 41:34 */
+		uint64_t usr_data_2			: 2;	/* 33:32 */
+		uint64_t usr_data_1			: 16;	/* 31:16 */
+		uint64_t rsvd_y				: 3;	/* 15:13 */
+		uint64_t xmit_enable			: 1;	/* 12 */
+		uint64_t ustat_src			: 2;	/* 11:10 */
+		uint64_t in_domain			: 1;	/* 9 */
+		uint64_t paroli_tck_enable		: 1;	/* 8 */
+		uint64_t laser_enable			: 1;	/* 7 */
+		uint64_t rsvd_x				: 1;	/* 6 */
+		uint64_t rexmit_shutdown_en		: 1;	/* 5 */
+		uint64_t near_end_shutdown_lock		: 1;	/* 4 */
+		uint64_t failover_en			: 1;	/* 3 */
+		uint64_t auto_shut_en			: 1;	/* 2 */
+		uint64_t link_state			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_sw_link_control_u;
+
+#define	wci_sw_link_control_rexmit_freeze	\
+	bit.rexmit_freeze
+#define	wci_sw_link_control_rexmit_mag	\
+	bit.rexmit_mag
+#define	wci_sw_link_control_rexmit_val	\
+	bit.rexmit_val
+#define	wci_sw_link_control_error_inducement	\
+	bit.error_inducement
+#define	wci_sw_link_control_xmit_timeout	\
+	bit.xmit_timeout
+#define	wci_sw_link_control_usr_data_2	\
+	bit.usr_data_2
+#define	wci_sw_link_control_usr_data_1	\
+	bit.usr_data_1
+#define	wci_sw_link_control_xmit_enable	\
+	bit.xmit_enable
+#define	wci_sw_link_control_ustat_src	\
+	bit.ustat_src
+#define	wci_sw_link_control_in_domain	\
+	bit.in_domain
+#define	wci_sw_link_control_paroli_tck_enable	\
+	bit.paroli_tck_enable
+#define	wci_sw_link_control_laser_enable	\
+	bit.laser_enable
+#define	wci_sw_link_control_rexmit_shutdown_en	\
+	bit.rexmit_shutdown_en
+#define	wci_sw_link_control_near_end_shutdown_lock	\
+	bit.near_end_shutdown_lock
+#define	wci_sw_link_control_failover_en	\
+	bit.failover_en
+#define	wci_sw_link_control_auto_shut_en	\
+	bit.auto_shut_en
+#define	wci_sw_link_control_link_state	\
+	bit.link_state
+
+
+/*
+ * wci_sw_link_error_count
+ */
+typedef union {
+	struct wci_sw_link_error_count {
+		uint64_t error_count			: 24;	/* 63:40 */
+		uint64_t rsvd_z				: 40;	/* 39:0 */
+	} bit;
+	uint64_t val;
+} wci_sw_link_error_count_u;
+
+#define	wci_sw_link_error_count_error_count	\
+	bit.error_count
+
+
+/*
+ * wci_sw_link_status
+ */
+typedef union {
+	struct wci_sw_link_status {
+		uint64_t rsvd_z				: 9;	/* 63:55 */
+		uint64_t paroli_present			: 1;	/* 54 */
+		uint64_t bad_gnid			: 4;	/* 53:50 */
+		uint64_t farend_ustat_2			: 2;	/* 49:48 */
+		uint64_t farend_ustat_1			: 16;	/* 47:32 */
+		uint64_t ustat_1			: 16;	/* 31:16 */
+		uint64_t shutdown_cause			: 2;	/* 15:14 */
+		uint64_t got_fo_pkt			: 1;	/* 13 */
+		uint64_t multiple_link_failover		: 1;	/* 12 */
+		uint64_t failover_cause			: 1;	/* 11 */
+		uint64_t link_idle			: 1;	/* 10 */
+		uint64_t sync_locked			: 1;	/* 9 */
+		uint64_t optical_signal_detect		: 1;	/* 8 */
+		uint64_t reset_pending			: 1;	/* 7 */
+		uint64_t framing_error			: 1;	/* 6 */
+		uint64_t clocking_error			: 1;	/* 5 */
+		uint64_t end_status			: 2;	/* 4:3 */
+		uint64_t crc_error			: 1;	/* 2 */
+		uint64_t rsvd_y				: 1;	/* 1 */
+		uint64_t packets_discarded		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sw_link_status_u;
+
+#define	wci_sw_link_status_paroli_present	\
+	bit.paroli_present
+#define	wci_sw_link_status_bad_gnid	\
+	bit.bad_gnid
+#define	wci_sw_link_status_farend_ustat_2	\
+	bit.farend_ustat_2
+#define	wci_sw_link_status_farend_ustat_1	\
+	bit.farend_ustat_1
+#define	wci_sw_link_status_ustat_1	\
+	bit.ustat_1
+#define	wci_sw_link_status_shutdown_cause	\
+	bit.shutdown_cause
+#define	wci_sw_link_status_got_fo_pkt	\
+	bit.got_fo_pkt
+#define	wci_sw_link_status_multiple_link_failover	\
+	bit.multiple_link_failover
+#define	wci_sw_link_status_failover_cause	\
+	bit.failover_cause
+#define	wci_sw_link_status_link_idle	\
+	bit.link_idle
+#define	wci_sw_link_status_sync_locked	\
+	bit.sync_locked
+#define	wci_sw_link_status_optical_signal_detect	\
+	bit.optical_signal_detect
+#define	wci_sw_link_status_reset_pending	\
+	bit.reset_pending
+#define	wci_sw_link_status_framing_error	\
+	bit.framing_error
+#define	wci_sw_link_status_clocking_error	\
+	bit.clocking_error
+#define	wci_sw_link_status_end_status	\
+	bit.end_status
+#define	wci_sw_link_status_crc_error	\
+	bit.crc_error
+#define	wci_sw_link_status_packets_discarded	\
+	bit.packets_discarded
+
+
+/*
+ * wci_sw_config
+ */
+typedef union {
+	struct wci_sw_config {
+		uint64_t max_errors			: 24;	/* 63:40 */
+		uint64_t rsvd_z				: 23;	/* 39:17 */
+		uint64_t error_pause_shutdown_en	: 1;	/* 16 */
+		uint64_t partner_gnid			: 4;	/* 15:12 */
+		uint64_t gnid				: 4;	/* 11:8 */
+		uint64_t failover_en			: 1;	/* 7 */
+		uint64_t drop_illegal_gnid		: 1;	/* 6 */
+		uint64_t sync_buffer_safety_level	: 2;	/* 5:4 */
+		uint64_t mask_originate_broadcast	: 1;	/* 3 */
+		uint64_t xmit_arb_policy		: 2;	/* 2:1 */
+		uint64_t enable_dx_shortcut		: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sw_config_u;
+
+#define	wci_sw_config_max_errors	\
+	bit.max_errors
+#define	wci_sw_config_error_pause_shutdown_en	\
+	bit.error_pause_shutdown_en
+#define	wci_sw_config_partner_gnid	\
+	bit.partner_gnid
+#define	wci_sw_config_gnid	\
+	bit.gnid
+#define	wci_sw_config_failover_en	\
+	bit.failover_en
+#define	wci_sw_config_drop_illegal_gnid	\
+	bit.drop_illegal_gnid
+#define	wci_sw_config_sync_buffer_safety_level	\
+	bit.sync_buffer_safety_level
+#define	wci_sw_config_mask_originate_broadcast	\
+	bit.mask_originate_broadcast
+#define	wci_sw_config_xmit_arb_policy	\
+	bit.xmit_arb_policy
+#define	wci_sw_config_enable_dx_shortcut	\
+	bit.enable_dx_shortcut
+
+
+/*
+ * wci_sw_status
+ */
+typedef union {
+	struct wci_sw_status {
+		uint64_t rsvd_z				: 55;	/* 63:9 */
+		uint64_t addr_lpbk_illegal_gnid		: 4;	/* 8:5 */
+		uint64_t error_pause_broadcast_status	: 3;	/* 4:2 */
+		uint64_t originate			: 1;	/* 1 */
+		uint64_t local_source			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sw_status_u;
+
+#define	wci_sw_status_addr_lpbk_illegal_gnid	\
+	bit.addr_lpbk_illegal_gnid
+#define	wci_sw_status_error_pause_broadcast_status	\
+	bit.error_pause_broadcast_status
+#define	wci_sw_status_originate	\
+	bit.originate
+#define	wci_sw_status_local_source	\
+	bit.local_source
+
+
+/*
+ * wci_link_ctr_ctl
+ */
+typedef union {
+	struct wci_link_ctr_ctl {
+		uint64_t rsvd_z				: 33;	/* 63:31 */
+		uint64_t cnt1_source_select		: 2;	/* 30:29 */
+		uint64_t cnt1_gnid_target		: 4;	/* 28:25 */
+		uint64_t cnt1_snid_target		: 4;	/* 24:21 */
+		uint64_t cnt1_rcvd_admin_packet		: 1;	/* 20 */
+		uint64_t cnt1_rejected_normal_flit	: 1;	/* 19 */
+		uint64_t cnt1_data_rcvd_data_packet	: 1;	/* 18 */
+		uint64_t cnt1_mhop_rcvd_data_packet	: 1;	/* 17 */
+		uint64_t cnt1_xmitting_admin_packet	: 1;	/* 16 */
+		uint64_t rsvd_y				: 1;	/* 15 */
+		uint64_t cnt0_source_select		: 2;	/* 14:13 */
+		uint64_t cnt0_gnid_target		: 4;	/* 12:9 */
+		uint64_t cnt0_snid_target		: 4;	/* 8:5 */
+		uint64_t cnt0_rcvd_admin_packet		: 1;	/* 4 */
+		uint64_t cnt0_rejected_normal_flit	: 1;	/* 3 */
+		uint64_t cnt0_data_rcvd_data_packet	: 1;	/* 2 */
+		uint64_t cnt0_mhop_rcvd_data_packet	: 1;	/* 1 */
+		uint64_t cnt0_xmitting_admin_packet	: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_link_ctr_ctl_u;
+
+#define	wci_link_ctr_ctl_cnt1_source_select	\
+	bit.cnt1_source_select
+#define	wci_link_ctr_ctl_cnt1_gnid_target	\
+	bit.cnt1_gnid_target
+#define	wci_link_ctr_ctl_cnt1_snid_target	\
+	bit.cnt1_snid_target
+#define	wci_link_ctr_ctl_cnt1_rcvd_admin_packet	\
+	bit.cnt1_rcvd_admin_packet
+#define	wci_link_ctr_ctl_cnt1_rejected_normal_flit	\
+	bit.cnt1_rejected_normal_flit
+#define	wci_link_ctr_ctl_cnt1_data_rcvd_data_packet	\
+	bit.cnt1_data_rcvd_data_packet
+#define	wci_link_ctr_ctl_cnt1_mhop_rcvd_data_packet	\
+	bit.cnt1_mhop_rcvd_data_packet
+#define	wci_link_ctr_ctl_cnt1_xmitting_admin_packet	\
+	bit.cnt1_xmitting_admin_packet
+#define	wci_link_ctr_ctl_cnt0_source_select	\
+	bit.cnt0_source_select
+#define	wci_link_ctr_ctl_cnt0_gnid_target	\
+	bit.cnt0_gnid_target
+#define	wci_link_ctr_ctl_cnt0_snid_target	\
+	bit.cnt0_snid_target
+#define	wci_link_ctr_ctl_cnt0_rcvd_admin_packet	\
+	bit.cnt0_rcvd_admin_packet
+#define	wci_link_ctr_ctl_cnt0_rejected_normal_flit	\
+	bit.cnt0_rejected_normal_flit
+#define	wci_link_ctr_ctl_cnt0_data_rcvd_data_packet	\
+	bit.cnt0_data_rcvd_data_packet
+#define	wci_link_ctr_ctl_cnt0_mhop_rcvd_data_packet	\
+	bit.cnt0_mhop_rcvd_data_packet
+#define	wci_link_ctr_ctl_cnt0_xmitting_admin_packet	\
+	bit.cnt0_xmitting_admin_packet
+
+
+/*
+ * wci_lpbk_ctr_ctl
+ */
+typedef union {
+	struct wci_lpbk_ctr_ctl {
+		uint64_t rsvd_z				: 38;	/* 63:26 */
+		uint64_t cnt1_data_gnid_source_select	: 1;	/* 25 */
+		uint64_t cnt1_data_gnid_target		: 4;	/* 24:21 */
+		uint64_t cnt1_addr_lpbk_full		: 1;	/* 20 */
+		uint64_t cnt1_data_lpbk_full		: 1;	/* 19 */
+		uint64_t cnt1_addr_lpbk_rcvd_addr_1_packet	: 1;	/* 18 */
+		uint64_t cnt1_addr_lpbk_rcvd_addr_2_packet	: 1;	/* 17 */
+		uint64_t cnt1_data_lpbk_rcvd_data_packet	: 1;	/* 16 */
+		uint64_t rsvd_y				: 6;	/* 15:10 */
+		uint64_t cnt0_data_gnid_source_select	: 1;	/* 9 */
+		uint64_t cnt0_data_gnid_target		: 4;	/* 8:5 */
+		uint64_t cnt0_addr_lpbk_full		: 1;	/* 4 */
+		uint64_t cnt0_data_lpbk_full		: 1;	/* 3 */
+		uint64_t cnt0_addr_lpbk_rcvd_addr_1_packet	: 1;	/* 2 */
+		uint64_t cnt0_addr_lpbk_rcvd_addr_2_packet	: 1;	/* 1 */
+		uint64_t cnt0_data_lpbk_rcvd_data_packet	: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_lpbk_ctr_ctl_u;
+
+#define	wci_lpbk_ctr_ctl_cnt1_data_gnid_source_select	\
+	bit.cnt1_data_gnid_source_select
+#define	wci_lpbk_ctr_ctl_cnt1_data_gnid_target	\
+	bit.cnt1_data_gnid_target
+#define	wci_lpbk_ctr_ctl_cnt1_addr_lpbk_full	\
+	bit.cnt1_addr_lpbk_full
+#define	wci_lpbk_ctr_ctl_cnt1_data_lpbk_full	\
+	bit.cnt1_data_lpbk_full
+#define	wci_lpbk_ctr_ctl_cnt1_addr_lpbk_rcvd_addr_1_packet	\
+	bit.cnt1_addr_lpbk_rcvd_addr_1_packet
+#define	wci_lpbk_ctr_ctl_cnt1_addr_lpbk_rcvd_addr_2_packet	\
+	bit.cnt1_addr_lpbk_rcvd_addr_2_packet
+#define	wci_lpbk_ctr_ctl_cnt1_data_lpbk_rcvd_data_packet	\
+	bit.cnt1_data_lpbk_rcvd_data_packet
+#define	wci_lpbk_ctr_ctl_cnt0_data_gnid_source_select	\
+	bit.cnt0_data_gnid_source_select
+#define	wci_lpbk_ctr_ctl_cnt0_data_gnid_target	\
+	bit.cnt0_data_gnid_target
+#define	wci_lpbk_ctr_ctl_cnt0_addr_lpbk_full	\
+	bit.cnt0_addr_lpbk_full
+#define	wci_lpbk_ctr_ctl_cnt0_data_lpbk_full	\
+	bit.cnt0_data_lpbk_full
+#define	wci_lpbk_ctr_ctl_cnt0_addr_lpbk_rcvd_addr_1_packet	\
+	bit.cnt0_addr_lpbk_rcvd_addr_1_packet
+#define	wci_lpbk_ctr_ctl_cnt0_addr_lpbk_rcvd_addr_2_packet	\
+	bit.cnt0_addr_lpbk_rcvd_addr_2_packet
+#define	wci_lpbk_ctr_ctl_cnt0_data_lpbk_rcvd_data_packet	\
+	bit.cnt0_data_lpbk_rcvd_data_packet
+
+
+/*
+ * wci_link_ctr
+ */
+typedef union {
+	struct wci_link_ctr {
+		uint64_t cnt1				: 32;	/* 63:32 */
+		uint64_t cnt0				: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_link_ctr_u;
+
+#define	wci_link_ctr_cnt1	\
+	bit.cnt1
+#define	wci_link_ctr_cnt0	\
+	bit.cnt0
+
+
+/*
+ * wci_lpbk_ctr
+ */
+typedef union {
+	struct wci_lpbk_ctr {
+		uint64_t cnt1				: 32;	/* 63:32 */
+		uint64_t cnt0				: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_lpbk_ctr_u;
+
+#define	wci_lpbk_ctr_cnt1	\
+	bit.cnt1
+#define	wci_lpbk_ctr_cnt0	\
+	bit.cnt0
+
+
+/*
+ * wci_sw_esr_a
+ */
+typedef union {
+	struct wci_sw_esr_a {
+		uint64_t rsvd_z				: 46;	/* 63:18 */
+		uint64_t acc_fo_b_fifo_ovf		: 1;	/* 17 */
+		uint64_t acc_fo_a_fifo_ovf		: 1;	/* 16 */
+		uint64_t first_error			: 1;	/* 15 */
+		uint64_t rsvd_y				: 13;	/* 14:2 */
+		uint64_t fo_b_fifo_ovf			: 1;	/* 1 */
+		uint64_t fo_a_fifo_ovf			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sw_esr_a_u;
+
+#define	wci_sw_esr_a_acc_fo_b_fifo_ovf	\
+	bit.acc_fo_b_fifo_ovf
+#define	wci_sw_esr_a_acc_fo_a_fifo_ovf	\
+	bit.acc_fo_a_fifo_ovf
+#define	wci_sw_esr_a_first_error	\
+	bit.first_error
+#define	wci_sw_esr_a_fo_b_fifo_ovf	\
+	bit.fo_b_fifo_ovf
+#define	wci_sw_esr_a_fo_a_fifo_ovf	\
+	bit.fo_a_fifo_ovf
+
+
+/*
+ * wci_sw_esr_a_mask
+ */
+typedef union {
+	struct wci_sw_esr_a_mask {
+		uint64_t rsvd_z				: 62;	/* 63:2 */
+		uint64_t fo_b_fifo_ovf			: 1;	/* 1 */
+		uint64_t fo_a_fifo_ovf			: 1;	/* 0 */
+	} bit;
+	uint64_t val;
+} wci_sw_esr_a_mask_u;
+
+#define	wci_sw_esr_a_mask_fo_b_fifo_ovf	\
+	bit.fo_b_fifo_ovf
+#define	wci_sw_esr_a_mask_fo_a_fifo_ovf	\
+	bit.fo_a_fifo_ovf
+
+
+/*
+ * wci_gnid_map0
+ */
+typedef union {
+	struct wci_gnid_map0 {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_gnid_map0_u;
+
+#define	wci_gnid_map0_node15_tlink	\
+	bit.node15_tlink
+#define	wci_gnid_map0_node14_tlink	\
+	bit.node14_tlink
+#define	wci_gnid_map0_node13_tlink	\
+	bit.node13_tlink
+#define	wci_gnid_map0_node12_tlink	\
+	bit.node12_tlink
+#define	wci_gnid_map0_node11_tlink	\
+	bit.node11_tlink
+#define	wci_gnid_map0_node10_tlink	\
+	bit.node10_tlink
+#define	wci_gnid_map0_node9_tlink	\
+	bit.node9_tlink
+#define	wci_gnid_map0_node8_tlink	\
+	bit.node8_tlink
+#define	wci_gnid_map0_node7_tlink	\
+	bit.node7_tlink
+#define	wci_gnid_map0_node6_tlink	\
+	bit.node6_tlink
+#define	wci_gnid_map0_node5_tlink	\
+	bit.node5_tlink
+#define	wci_gnid_map0_node4_tlink	\
+	bit.node4_tlink
+#define	wci_gnid_map0_node3_tlink	\
+	bit.node3_tlink
+#define	wci_gnid_map0_node2_tlink	\
+	bit.node2_tlink
+#define	wci_gnid_map0_node1_tlink	\
+	bit.node1_tlink
+#define	wci_gnid_map0_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_gnid_map1
+ */
+typedef union {
+	struct wci_gnid_map1 {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_gnid_map1_u;
+
+#define	wci_gnid_map1_node15_tlink	\
+	bit.node15_tlink
+#define	wci_gnid_map1_node14_tlink	\
+	bit.node14_tlink
+#define	wci_gnid_map1_node13_tlink	\
+	bit.node13_tlink
+#define	wci_gnid_map1_node12_tlink	\
+	bit.node12_tlink
+#define	wci_gnid_map1_node11_tlink	\
+	bit.node11_tlink
+#define	wci_gnid_map1_node10_tlink	\
+	bit.node10_tlink
+#define	wci_gnid_map1_node9_tlink	\
+	bit.node9_tlink
+#define	wci_gnid_map1_node8_tlink	\
+	bit.node8_tlink
+#define	wci_gnid_map1_node7_tlink	\
+	bit.node7_tlink
+#define	wci_gnid_map1_node6_tlink	\
+	bit.node6_tlink
+#define	wci_gnid_map1_node5_tlink	\
+	bit.node5_tlink
+#define	wci_gnid_map1_node4_tlink	\
+	bit.node4_tlink
+#define	wci_gnid_map1_node3_tlink	\
+	bit.node3_tlink
+#define	wci_gnid_map1_node2_tlink	\
+	bit.node2_tlink
+#define	wci_gnid_map1_node1_tlink	\
+	bit.node1_tlink
+#define	wci_gnid_map1_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_fo_route_map
+ */
+typedef union {
+	struct wci_fo_route_map {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_fo_route_map_u;
+
+#define	wci_fo_route_map_node15_tlink	\
+	bit.node15_tlink
+#define	wci_fo_route_map_node14_tlink	\
+	bit.node14_tlink
+#define	wci_fo_route_map_node13_tlink	\
+	bit.node13_tlink
+#define	wci_fo_route_map_node12_tlink	\
+	bit.node12_tlink
+#define	wci_fo_route_map_node11_tlink	\
+	bit.node11_tlink
+#define	wci_fo_route_map_node10_tlink	\
+	bit.node10_tlink
+#define	wci_fo_route_map_node9_tlink	\
+	bit.node9_tlink
+#define	wci_fo_route_map_node8_tlink	\
+	bit.node8_tlink
+#define	wci_fo_route_map_node7_tlink	\
+	bit.node7_tlink
+#define	wci_fo_route_map_node6_tlink	\
+	bit.node6_tlink
+#define	wci_fo_route_map_node5_tlink	\
+	bit.node5_tlink
+#define	wci_fo_route_map_node4_tlink	\
+	bit.node4_tlink
+#define	wci_fo_route_map_node3_tlink	\
+	bit.node3_tlink
+#define	wci_fo_route_map_node2_tlink	\
+	bit.node2_tlink
+#define	wci_fo_route_map_node1_tlink	\
+	bit.node1_tlink
+#define	wci_fo_route_map_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_sec_fo_route_map
+ */
+typedef union {
+	struct wci_sec_fo_route_map {
+		uint64_t rsvd_z				: 17;	/* 63:47 */
+		uint64_t node15_tlink			: 2;	/* 46:45 */
+		uint64_t rsvd_y				: 1;	/* 44 */
+		uint64_t node14_tlink			: 2;	/* 43:42 */
+		uint64_t rsvd_x				: 1;	/* 41 */
+		uint64_t node13_tlink			: 2;	/* 40:39 */
+		uint64_t rsvd_w				: 1;	/* 38 */
+		uint64_t node12_tlink			: 2;	/* 37:36 */
+		uint64_t rsvd_v				: 1;	/* 35 */
+		uint64_t node11_tlink			: 2;	/* 34:33 */
+		uint64_t rsvd_u				: 1;	/* 32 */
+		uint64_t node10_tlink			: 2;	/* 31:30 */
+		uint64_t rsvd_t				: 1;	/* 29 */
+		uint64_t node9_tlink			: 2;	/* 28:27 */
+		uint64_t rsvd_s				: 1;	/* 26 */
+		uint64_t node8_tlink			: 2;	/* 25:24 */
+		uint64_t rsvd_r				: 1;	/* 23 */
+		uint64_t node7_tlink			: 2;	/* 22:21 */
+		uint64_t rsvd_q				: 1;	/* 20 */
+		uint64_t node6_tlink			: 2;	/* 19:18 */
+		uint64_t rsvd_p				: 1;	/* 17 */
+		uint64_t node5_tlink			: 2;	/* 16:15 */
+		uint64_t rsvd_o				: 1;	/* 14 */
+		uint64_t node4_tlink			: 2;	/* 13:12 */
+		uint64_t rsvd_n				: 1;	/* 11 */
+		uint64_t node3_tlink			: 2;	/* 10:9 */
+		uint64_t rsvd_m				: 1;	/* 8 */
+		uint64_t node2_tlink			: 2;	/* 7:6 */
+		uint64_t rsvd_l				: 1;	/* 5 */
+		uint64_t node1_tlink			: 2;	/* 4:3 */
+		uint64_t rsvd_k				: 1;	/* 2 */
+		uint64_t node0_tlink			: 2;	/* 1:0 */
+	} bit;
+	uint64_t val;
+} wci_sec_fo_route_map_u;
+
+#define	wci_sec_fo_route_map_node15_tlink	\
+	bit.node15_tlink
+#define	wci_sec_fo_route_map_node14_tlink	\
+	bit.node14_tlink
+#define	wci_sec_fo_route_map_node13_tlink	\
+	bit.node13_tlink
+#define	wci_sec_fo_route_map_node12_tlink	\
+	bit.node12_tlink
+#define	wci_sec_fo_route_map_node11_tlink	\
+	bit.node11_tlink
+#define	wci_sec_fo_route_map_node10_tlink	\
+	bit.node10_tlink
+#define	wci_sec_fo_route_map_node9_tlink	\
+	bit.node9_tlink
+#define	wci_sec_fo_route_map_node8_tlink	\
+	bit.node8_tlink
+#define	wci_sec_fo_route_map_node7_tlink	\
+	bit.node7_tlink
+#define	wci_sec_fo_route_map_node6_tlink	\
+	bit.node6_tlink
+#define	wci_sec_fo_route_map_node5_tlink	\
+	bit.node5_tlink
+#define	wci_sec_fo_route_map_node4_tlink	\
+	bit.node4_tlink
+#define	wci_sec_fo_route_map_node3_tlink	\
+	bit.node3_tlink
+#define	wci_sec_fo_route_map_node2_tlink	\
+	bit.node2_tlink
+#define	wci_sec_fo_route_map_node1_tlink	\
+	bit.node1_tlink
+#define	wci_sec_fo_route_map_node0_tlink	\
+	bit.node0_tlink
+
+
+/*
+ * wci_fo_tnid_map
+ */
+typedef union {
+	struct wci_fo_tnid_map {
+		uint64_t rsvd_z				: 52;	/* 63:12 */
+		uint64_t link2_tnid			: 4;	/* 11:8 */
+		uint64_t link1_tnid			: 4;	/* 7:4 */
+		uint64_t link0_tnid			: 4;	/* 3:0 */
+	} bit;
+	uint64_t val;
+} wci_fo_tnid_map_u;
+
+#define	wci_fo_tnid_map_link2_tnid	\
+	bit.link2_tnid
+#define	wci_fo_tnid_map_link1_tnid	\
+	bit.link1_tnid
+#define	wci_fo_tnid_map_link0_tnid	\
+	bit.link0_tnid
+
+/*
+ * wci_sw_link_rexmit
+ */
+typedef union {
+	struct wci_sw_link_rexmit {
+		uint64_t rsvd_z				: 32;	/* 63:32 */
+		uint64_t rexmit_count			: 32;	/* 31:0 */
+	} bit;
+	uint64_t val;
+} wci_sw_link_rexmit_u;
+
+#define	wci_sw_link_rexmit_rexmit_count	\
+	bit.rexmit_count
+
+
+/*
+ * wci_dnid2gnid
+ */
+typedef union {
+	struct wci_dnid2gnid {
+		uint64_t dnid2gnid			: 64;	/* 63:0 */
+	} bit;
+	uint64_t val;
+} wci_dnid2gnid_u;
+
+#define	wci_dnid2gnid_dnid2gnid	\
+	bit.dnid2gnid
+
+
+/* For compatibility with WCI-1 */
+#define	ADDR_WCI_ROUTE_MAP0 ADDR_WCI_JNK_ROUTE_MAP0
+#define	ADDR_WCI_ROUTE_MAP1 ADDR_WCI_JNK_ROUTE_MAP1
+typedef wci_jnk_route_map0_u wci_route_map0_u;
+typedef wci_jnk_route_map1_u wci_route_map1_u;
+
+#endif /* _KERNEL && !_ASM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_WCI_REGS_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm.h b/usr/src/uts/sun4u/sys/wrsm.h
new file mode 100644
index 0000000000..61f7ad7268
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm.h
@@ -0,0 +1,360 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _SYS_WRSM_H
+#define	_SYS_WRSM_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/kstat.h>
+#include <sys/wrsm_types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define	WRSM_CLASS "wrsm"
+#define	WRSM_SUBCLASS_LINKUP "link-up"
+#define	WRSM_SUBCLASS_LINKDOWN "link-down"
+#define	WRSM_SUBCLASS_NEW_NODE "new-node-route"
+#define	WRSM_SUBCLASS_LOST_NODE "lost-node-route"
+#define	WRSM_SUBCLASS_NEW_CONFIG "new-config"
+
+/*
+ * WRSM ioctl interface.
+ */
+
+#define	WRSM_IOC		('W'<<8)
+
+/* Admin device ioctls */
+#define	WRSM_CONTROLLERS	(WRSM_IOC|0)	/* # of registered rsmctlrs */
+#define	WRSM_REPLACECFG		(WRSM_IOC|1)
+#define	WRSM_CHECKCFG		(WRSM_IOC|2)
+#define	WRSM_INSTALLCFG		(WRSM_IOC|3)
+#define	WRSM_INITIALCFG		(WRSM_IOC|4)
+#define	WRSM_REMOVECFG		(WRSM_IOC|5)
+#define	WRSM_GETCFG		(WRSM_IOC|6)
+#define	WRSM_ENABLECFG		(WRSM_IOC|7)
+#define	WRSM_STARTCFG		(WRSM_IOC|8)
+#define	WRSM_STOPCFG		(WRSM_IOC|9)
+
+/* WCI device ioctls */
+#define	WRSM_LC_READCSR		(WRSM_IOC|20)
+#define	WRSM_LC_WRITECSR	(WRSM_IOC|21)
+#define	WRSM_LC_READCESR	(WRSM_IOC|22)
+#define	WRSM_LC_WRITECESR	(WRSM_IOC|23)
+#define	WRSM_LC_UPDATECMMU	(WRSM_IOC|24)
+#define	WRSM_LC_READCMMU	(WRSM_IOC|25)
+
+/* RSM-controller device ioctls */
+#define	WRSM_CTLR_PING		(WRSM_IOC|30)
+#define	WRSM_CTLR_MBOX		(WRSM_IOC|31)
+#define	WRSM_CTLR_SESS		(WRSM_IOC|38)
+
+/* WCI device ioctl to support link loopback testing */
+#define	WRSM_WCI_LOOPBACK_ON	(WRSM_IOC|40)  /* enable loopback link */
+#define	WRSM_WCI_LOOPBACK_OFF	(WRSM_IOC|41)  /* disable loopback link */
+#define	WRSM_WCI_LINKTEST	(WRSM_IOC|42)  /* test loopback link */
+#define	WRSM_WCI_CLAIM		(WRSM_IOC|43)  /* reserve WCI for testing */
+#define	WRSM_WCI_RELEASE	(WRSM_IOC|44)
+#define	WRSM_WCI_LINKUP		(WRSM_IOC|45)
+#define	WRSM_WCI_LINKDOWN	(WRSM_IOC|46)
+
+#define	WRSM_CTLR_MEM_LOOPBACK	(WRSM_IOC|50)	/* memory loopback test */
+
+/* Mailbox ioctl sub-commands */
+#define	WRSM_CTLR_UPLINK	1
+#define	WRSM_CTLR_DOWNLINK	2
+#define	WRSM_CTLR_SET_LED	3
+#define	WRSM_CTLR_ALLOC_SLICES	4
+#define	WRSM_CTLR_SET_SEPROM	5
+
+/* Plugin librsmwrsm.so ioctls to request small_puts of the driver */
+#define	WRSM_CTLR_PLUGIN_SMALLPUT	7
+#define	WRSM_CTLR_PLUGIN_GETLOCALNODE	8
+
+/* Session ioctl sub-commands */
+#define	WRSM_CTLR_SESS_START	1
+#define	WRSM_CTLR_SESS_END	2
+#define	WRSM_CTLR_SESS_ENABLE	3
+#define	WRSM_CTLR_SESS_DISABLE	4
+#define	WRSM_CTLR_SESS_GET	5
+
+typedef struct wrsm_linktest_arg {
+	uint16_t link_num;	/* link to test */
+	uint32_t pattern;	/* data to send via user_data (max 18 bits) */
+	uint64_t link_error_count; /* copy of wci_sw_link_error_count */
+	uint64_t link_status;	/* copy of wci_sw_link_status */
+	uint64_t link_esr;	/* copy of wci_link_esr */
+	uint64_t sw_esr;	/* copy of wci_sw_esr */
+	uint64_t link_control;	/* copy of wci_sw_link_control */
+} wrsm_linktest_arg_t;
+
+
+/*
+ * 8 pages are allocated, exported through the WCI, and imported from the
+ * local node.  Each requested pattern is written then read in sequential
+ * 64 byte chunks, starting at offset 0, until the entire page has been
+ * read/written.  (One pattern is completed across the entire page before
+ * the next is started.) The starting physical address of the first
+ * allocated page is stored in the paddr field of the arg parameter on
+ * return from the ioctl.
+ *
+ * Around each pattern, a barrier is opened and closed to detect network
+ * errors.  If a barrier close detects an error, the ioctl fails and errno
+ * is set to ENETRESET.
+ *
+ * If a read does not return the written pattern, the ioctl fails and errno
+ * is set to EIO.  The pattern encountering the error is stored in the
+ * pattern_error field of the arg parameter, and the local physical address
+ * of the exact 64 byte region with the error is stored in the paddr field.
+ *
+ * Other errnos may be returned; these typically indicate problems in the
+ * OS or with the caller's input.
+ *
+ */
+
+#define	WRSM_SSO_PATTERN	0x01
+#define	WRSM_SLOWMARCH_PATTERN	0x02
+#define	WRSM_FASTMARCH_PATTERN	0x04
+#define	WRSM_XTALK_PATTERN	0x08
+
+#define	WRSM_MAX_PATTERN	4		/* number of valid bits */
+
+
+typedef struct wrsm_memloopback_arg {
+	uint_t patterns;
+	uint64_t paddr;
+	uint64_t error_pattern;
+	unsigned char expected_data[64];
+	unsigned char actual_data[64];
+} wrsm_memloopback_arg_t;
+
+/*
+ * There are 3 kstats associated with RSM:
+ *    1. A WCI and its links (status)
+ *    2. Routes
+ *    3. RSM controller (rsmpi_stat)
+ */
+
+/* There are two kstat modules */
+#define	WRSM_KSTAT_WRSM		"wrsm"
+#define	WRSM_KSTAT_WRSM_ROUTE	"wrsm_route"
+
+/* The following are the names for the kstats */
+#define	WRSM_KSTAT_STATUS	"status"
+
+/*
+ * The name of the route kstat is defined dynamically
+ * as "FM-node-name" -- this is a name of a remote node.
+ */
+
+/*
+ * LC Link States
+ */
+typedef enum {
+	lc_up,			/* lasers have been established */
+	lc_down,		/* paroli present, lasers are not on */
+	lc_not_there,		/* no paroli is present */
+	sc_wait_down,		/* waiting for SC to take down link */
+	sc_wait_up,		/* waiting for SC to bring up link */
+	sc_wait_errdown		/* link down wait on sc due to error */
+} wrsm_link_req_state_t;
+
+/* event types for sys event daemon: syseventd */
+typedef enum {
+	link_up,
+	link_down,
+	new_node_route, /* new or modified routes to get to remote host */
+	lost_node_route, /* driver removes route to a remote host */
+	new_config /* new configuration has occured */
+} wrsm_sys_event_t;
+
+
+/*
+ * Phys Link States
+ */
+typedef enum {
+	phys_off,		/* link is off */
+	phys_failover,		/* failover mode */
+	phys_seek,		/* link is in seek state */
+	phys_in_use		/* link is in use */
+} wrsm_phys_link_state_t;
+
+/* Names for fields in the status kstat */
+#define	WRSMKS_WCI_VERSION_NAMED	"wci_version"
+#define	WRSMKS_CONTROLLER_ID_NAMED	"controller_id"
+#define	WRSMKS_PORTID			"portid"
+#define	WRSMKS_ERROR_LIMIT		"error_limit"
+#define	WRSMKS_ERRSTAT_INTERVAL		"errstat_interval"
+#define	WRSMKS_INTERVALS_PER_LT		"intervals_per_lt"
+#define	WRSMKS_AVG_WEIGHT		"avg_weight"
+#define	WRSMKS_VALID_LINK		"valid_link_%d"
+#define	WRSMKS_REMOTE_CNODE_ID		"remote_cnode_id_%d"
+#define	WRSMKS_REMOTE_WNODE		"remote_wnode_id_%d"
+#define	WRSMKS_REMOTE_WCI_PORTID	"remote_wci_portid_%d"
+#define	WRSMKS_REMOTE_LINKNUM		"remote_linknum_%d"
+#define	WRSMKS_LC_LINK_STATE		"LC_link_state_%d"
+#define	WRSMKS_PHYS_LINK_STATE		"phys_link_state_%d"
+#define	WRSMKS_PHYS_LASER_ENABLE	"laser enabled_%d"
+#define	WRSMKS_PHYS_XMIT_ENABLE		"transmit enable_%d"
+#define	WRSMKS_LINK_STATE		"link_state_%d"
+#define	WRSMKS_LINK_ERR_TAKEDOWNS	"link_err_takedowns_%d"
+#define	WRSMKS_LAST_LINK_ERR_TAKEDOWNS	"last_link_err_takedowns_%d"
+#define	WRSMKS_MAX_LINK_ERR_TAKEDOWNS	"max_link_err_takedowns_%d"
+#define	WRSMKS_AVG_LINK_ERR_TAKEDOWNS	"avg_link_err_takedowns_%d"
+#define	WRSMKS_LINK_DISCON_TAKEDOWNS 	"link_disconnected_takedowns_%d"
+#define	WRSMKS_LINK_CFG_TAKEDOWNS	"link_cfg_takedowns_%d"
+#define	WRSMKS_LINK_FAILED_BRINGUPS	"link_failed_bringups_%d"
+#define	WRSMKS_LINK_INTERVAL_COUNT	"link_interval_count_%d"
+#define	WRSMKS_LINK_ENABLED		"link_enabled_%d"
+#define	WRSMKS_LINK_ERRORS		"link_errors_%d"
+#define	WRSMKS_LAST_LINK_ERRORS		"last_link_errors_%d"
+#define	WRSMKS_MAX_LINK_ERRORS		"max_link_errors_%d"
+#define	WRSMKS_AVG_LINK_ERRORS		"avg_link_errors_%d"
+#define	WRSMKS_LAST_LT_LINK_ERRORS	"last_lt_link_errors_%d"
+#define	WRSMKS_MAX_LT_LINK_ERRORS	"max_lt_link_errors_%d"
+#define	WRSMKS_AVG_LT_LINK_ERRORS	"avg_lt_link_errors_%d"
+#define	WRSMKS_AUTO_SHUTDOWN_EN		"auto_shutdown_en_%d"
+#define	WRSMKS_CLUSTER_ERROR_COUNT	"cluster_error_count"
+#define	WRSMKS_UC_SRAM_ECC_ERROR	"uc_sram_ecc_error"
+#define	WRSMKS_SRAM_ECC_ERRORS		"sram_ecc_errors"
+#define	WRSMKS_LAST_SRAM_ECC_ERRORS	"last_sram_ecc_errors"
+#define	WRSMKS_MAX_SRAM_ECC_ERRORS	"max_sram_ecc_errors"
+#define	WRSMKS_AVG_SRAM_ECC_ERRORS	"avg_sram_ecc_errors"
+
+#define	WRSM_KSTAT_NO_CTRLR	-1
+#define	WRSMKS_LINK_PRESENT	1
+#define	WRSMKS_LINK_NOT_PRESENT	0
+
+typedef struct wrsm_status_kstat {
+	kstat_named_t ks_version;
+	kstat_named_t controller_id;
+	kstat_named_t portid;
+	kstat_named_t error_limit;
+	kstat_named_t errstat_interval;
+	kstat_named_t intervals_per_lt;
+	kstat_named_t avg_weight;
+	kstat_named_t valid_link[WRSM_LINKS_PER_WCI];
+	kstat_named_t remote_cnode_id[WRSM_LINKS_PER_WCI];
+	kstat_named_t remote_wnode_id[WRSM_LINKS_PER_WCI];
+	kstat_named_t remote_wci_portid[WRSM_LINKS_PER_WCI];
+	kstat_named_t remote_linknum[WRSM_LINKS_PER_WCI];
+	kstat_named_t state[WRSM_LINKS_PER_WCI];
+	kstat_named_t laser[WRSM_LINKS_PER_WCI];
+	kstat_named_t xmit_enable[WRSM_LINKS_PER_WCI];
+	kstat_named_t link_state[WRSM_LINKS_PER_WCI];
+	kstat_named_t link_err_takedowns[WRSM_LINKS_PER_WCI];
+	kstat_named_t last_link_err_takedowns[WRSM_LINKS_PER_WCI];
+	kstat_named_t max_link_err_takedowns[WRSM_LINKS_PER_WCI];
+	kstat_named_t avg_link_err_takedowns[WRSM_LINKS_PER_WCI];
+	kstat_named_t link_disconnected_takedowns[WRSM_LINKS_PER_WCI];
+	kstat_named_t link_cfg_takedowns[WRSM_LINKS_PER_WCI];
+	kstat_named_t link_failed_bringups[WRSM_LINKS_PER_WCI];
+	kstat_named_t link_interval_count[WRSM_LINKS_PER_WCI];
+	kstat_named_t link_enabled[WRSM_LINKS_PER_WCI];
+	kstat_named_t link_errors[WRSM_LINKS_PER_WCI];
+	kstat_named_t last_link_errors[WRSM_LINKS_PER_WCI];
+	kstat_named_t max_link_errors[WRSM_LINKS_PER_WCI];
+	kstat_named_t avg_link_errors[WRSM_LINKS_PER_WCI];
+	kstat_named_t last_lt_link_errors[WRSM_LINKS_PER_WCI];
+	kstat_named_t max_lt_link_errors[WRSM_LINKS_PER_WCI];
+	kstat_named_t avg_lt_link_errors[WRSM_LINKS_PER_WCI];
+	kstat_named_t auto_shutdown_en[WRSM_LINKS_PER_WCI];
+	kstat_named_t cluster_error_count;
+	kstat_named_t uc_sram_ecc_error;
+	kstat_named_t sram_ecc_errors;
+	kstat_named_t last_sram_ecc_errors;
+	kstat_named_t max_sram_ecc_errors;
+	kstat_named_t avg_sram_ecc_errors;
+} wrsm_status_kstat_t;
+
+/*
+ * wrsm routes kstat names and struct
+ */
+#define	WRSMKS_CONFIG_VERSION_NAMED	"config-version"
+#define	WRSMKS_ROUTE_TYPE_NAMED		"route-type"
+#define	WRSMKS_NUM_WCIS			"num_wcis"
+#define	WRSMKS_NUM_STRIPES		"num_stripes"
+#define	WRSMKS_NUMCHANGES		"num_changes"
+#define	WRSMKS_CNODEID			"cnodeid"
+#define	WRSMKS_FMNODEID			"fmnodeid"
+#define	WRSMKS_ROUTE_PORTID		"route%d_portid"
+#define	WRSMKS_ROUTE_INSTANCE		"route%d_instance"
+#define	WRSMKS_ROUTE_NUMHOPS		"route%d_numhops"
+#define	WRSMKS_ROUTE_NUMLINKS		"route%d_numlinks"
+#define	WRSMKS_ROUTE_LINKID		"route%d_linkid%d"
+#define	WRSMKS_ROUTE_NODEID		"route%d_nodeid%d"
+#define	WRSMKS_ROUTE_GNID		"route%d_gnid%d"
+
+typedef struct wrsm_route_kstat {
+	kstat_named_t version;
+	kstat_named_t type;
+	kstat_named_t num_wcis;
+	kstat_named_t num_stripes;
+	kstat_named_t num_changes;
+	kstat_named_t cnodeid;
+	kstat_named_t fmnodeid;
+	kstat_named_t portid[WRSM_MAX_WCIS_PER_STRIPE];
+	kstat_named_t instance[WRSM_MAX_WCIS_PER_STRIPE];
+	kstat_named_t numhops[WRSM_MAX_WCIS_PER_STRIPE];
+	kstat_named_t numlinks[WRSM_MAX_WCIS_PER_STRIPE];
+	kstat_named_t linkid[WRSM_MAX_WCIS_PER_STRIPE][WRSM_MAX_DNIDS];
+	kstat_named_t nodeid[WRSM_MAX_WCIS_PER_STRIPE][WRSM_MAX_DNIDS];
+	kstat_named_t gnid[WRSM_MAX_WCIS_PER_STRIPE][WRSM_MAX_DNIDS];
+} wrsm_route_kstat_t;
+
+/*
+ * rsmpi_stat kstat
+ * plus four wrsm specific fields
+ */
+
+#define	WRSMKS_FREE_CMMU_ENTRIES	"free_cmmu_entries"
+#define	WRSMKS_NUM_RECONFIGS		"num_reconfigs"
+#define	WRSMKS_RSM_NUM_WCIS		"num_wcis"
+#define	WRSMKS_RSM_AVAIL_WCIS		"avail_wcis"
+
+typedef struct wrsm_rsmpi_stat {
+	kstat_named_t num_reconfigs;
+	kstat_named_t num_wcis;
+	kstat_named_t avail_wcis;
+	kstat_named_t free_cmmu_entries;
+	kstat_named_t ctlr_state;		/* required by rsmpi */
+	kstat_named_t addr;			/* required by rsmpi */
+	kstat_named_t ex_memsegs;		/* required by rsmpi */
+	kstat_named_t ex_memsegs_pub;		/* required by rsmpi */
+	kstat_named_t ex_memsegs_con;		/* required by rsmpi */
+	kstat_named_t bytes_bound;		/* required by rsmpi */
+	kstat_named_t im_memsegs_con;		/* required by rsmpi */
+	kstat_named_t sendqs;			/* required by rmspi */
+	kstat_named_t handlers;			/* required by rsmpi */
+} wrsm_rsmpi_stat_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _SYS_WRSM_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_barrier.h b/usr/src/uts/sun4u/sys/wrsm_barrier.h
new file mode 100644
index 0000000000..60c631876d
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_barrier.h
@@ -0,0 +1,89 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _WRSM_BARRIER_H
+#define	_WRSM_BARRIER_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <sys/rsm/rsm_common.h>
+#include <sys/rsm/rsmpi.h>
+
+/*
+ * Span of time barriers
+ */
+int wrsm_open_barrier_ctrl(rsm_controller_handle_t, rsm_barrier_t *);
+int wrsm_open_barrier_node(rsm_controller_handle_t, rsm_addr_t,
+    rsm_barrier_t *);
+int wrsm_open_barrier_region(rsm_memseg_import_handle_t, rsm_barrier_t *);
+int wrsm_open_barrier_regions(rsm_memseg_import_handle_t *, uint_t num_regions,
+    rsm_barrier_t *);
+
+/*
+ * Thread of code barriers
+ */
+int wrsm_open_barrier_ctrl_thr(rsm_controller_handle_t, rsm_barrier_t *);
+int wrsm_open_barrier_node_thr(rsm_controller_handle_t, rsm_addr_t,
+    rsm_barrier_t *);
+int wrsm_open_barrier_region_thr(rsm_memseg_import_handle_t, rsm_barrier_t *);
+int wrsm_open_barrier_regions_thr(rsm_memseg_import_handle_t *,
+    uint_t num_regions, rsm_barrier_t *);
+
+/*
+ * Barrier close/reopen/ordering
+ */
+int wrsm_close_barrier(rsm_barrier_t *);
+int wrsm_reopen_barrier(rsm_barrier_t *);
+int wrsm_order_barrier(rsm_barrier_t *);
+
+/*
+ * Thread of code init/fini.
+ */
+int wrsm_thread_init(rsm_controller_handle_t);
+int wrsm_thread_fini(rsm_controller_handle_t);
+
+/*
+ * Memseg barrier mode control.
+ */
+int wrsm_get_barrier_mode(rsm_memseg_import_handle_t, rsm_barrier_mode_t *);
+int wrsm_set_barrier_mode(rsm_memseg_import_handle_t, rsm_barrier_mode_t);
+
+/*
+ * Debug functions.
+ */
+#ifdef DEBUG
+void wrsm_print_barrier(rsm_barrier_t *);
+#endif /* DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WRSM_BARRIER_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_cf.h b/usr/src/uts/sun4u/sys/wrsm_cf.h
new file mode 100644
index 0000000000..5029fc5a97
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_cf.h
@@ -0,0 +1,80 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _WRSM_CF_H
+#define	_WRSM_CF_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * This file defines the interfaces between the config layer and
+ * the other components of the wrsm driver.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <sys/cred.h>
+#include <sys/wrsm_config.h>
+#include <sys/wrsm_common.h>
+
+#define	WRSM_BAD_RSM_ID 0xffffffff
+#define	WRSM_LOOPBACK_ID 0xfffffffe
+
+/*
+ * functions exported to the LC
+ */
+int wrsm_cf_newwci(lcwci_handle_t lcwci, safari_port_t port);
+int wrsm_cf_remove_wci(lcwci_handle_t lcwci);
+void wrsm_cf_is_enabled(uint32_t controller_id);
+lcwci_handle_t wrsm_cf_lookup_wci(safari_port_t port);
+int wrsm_cf_claim_wci(uint32_t controller_id, safari_port_t wci_id);
+void wrsm_cf_release_wci(safari_port_t wci_id);
+uint32_t wrsm_cf_wci_owner(safari_port_t wci_id);
+boolean_t wrsm_cf_cnode_is_switch(wrsm_controller_t *cont);
+
+/*
+ * functions exported to the core driver (wrsm_driver.c)
+ */
+void wrsm_cf_init(void);
+void wrsm_cf_fini(void);
+int wrsm_cf_new_controller(int cont_id, dev_info_t *devi);
+int wrsm_cf_remove_controller(int cont_id);
+int wrsm_cf_admin_ioctl(struct wrsm_soft_state *softsp, int cmd,
+    intptr_t arg, int flag, cred_t *cred_p, int *rval_p);
+int wrsm_cf_ctlr_ioctl(int cont_id, int cmd, intptr_t arg, int flag,
+    cred_t *cred_p, int *rval_p);
+void *wrsm_cf_pack(wrsm_controller_t *cont, int *sizep);
+wrsm_controller_t *wrsm_cf_unpack(char *data);
+void wrsm_cf_sc_failed(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WRSM_CF_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_cf_impl.h b/usr/src/uts/sun4u/sys/wrsm_cf_impl.h
new file mode 100644
index 0000000000..d99b306816
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_cf_impl.h
@@ -0,0 +1,79 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _WRSM_CONFIG_IMPL_H
+#define	_WRSM_CONFIG_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * Definitions private to the config layer of the wrsm driver.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <sys/wrsm_config.h>
+#include <sys/wrsm_nc.h>
+
+enum wrsm_cf_state {
+	cf_invalid,	/* no such controller yet */
+	cf_replaced,	/* REPLACECFG succeeded */
+	cf_installed,	/* INSTALCFG succeeded */
+	cf_enabled	/* ENABLECFG succeeded */
+};
+
+typedef struct wrsm_wci_dev {
+	wci_ids_t id;
+	struct wrsm_wci_dev *next;
+	uint32_t controller_id;
+	boolean_t attached;	/* _attach has been called on this WCI */
+} wrsm_wci_dev_t;
+
+typedef struct wrsm_controller_dev {
+	kmutex_t lock;
+	boolean_t in_ioctl;	/* An ioctl is operating on this controller */
+	uint32_t controller_id;
+	size_t nbytes;		/* size of the conroller configuration data */
+	size_t pending_nbytes;	/* size of the pending configuration */
+	dev_info_t *devi;
+	wrsm_controller_t *controller;
+	wrsm_controller_t *pending;
+	ncslice_bitmask_t ncslices;	/* ncslices used in config */
+	ncslice_bitmask_t pending_ncslices; /* pending config ncslices */
+	struct wrsm_controller_dev *next;
+	enum wrsm_cf_state state;
+} wrsm_controller_dev_t;
+
+void wrsm_cf_free(wrsm_controller_t *cont);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WRSM_CONFIG_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_cmmu.h b/usr/src/uts/sun4u/sys/wrsm_cmmu.h
new file mode 100644
index 0000000000..386503d7b5
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_cmmu.h
@@ -0,0 +1,198 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _WRSM_CMMU_H
+#define	_WRSM_CMMU_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/wrsm_config.h>
+#include <sys/wrsm_lc.h>
+#include <sys/wrsm_nc.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef uint32_t wrsm_cmmu_index_t;
+typedef caddr_t wrsm_cmmu_offset_t;
+
+typedef wrsm_ncslice_mode_t wrsm_cmmu_page_size_t;
+#define	CMMU_PAGE_SIZE_SMALL ncslice_small_page
+#define	CMMU_PAGE_SIZE_LARGE ncslice_large_page
+
+#define	CMMU_SMALL_PAGE_SIZE	0x00002000	/* 8K Bytes */
+#define	CMMU_SMALL_PAGE_MASK	0x00001fff
+#define	CMMU_SMALL_PAGE_SHIFT	13
+#define	CMMU_LARGE_PAGE_SIZE	0x00400000	/* 4M Bytes */
+#define	CMMU_LARGE_PAGE_MASK	0x003fffff
+#define	CMMU_LARGE_PAGE_SHIFT	22
+
+#define	CMMU_NCSLICE_SHIFT	34
+#define	CMMU_NCSLICE_OFFSET_MASK ((uint64_t)0x3ffffffff)
+#define	CMMU_PADDR2NCSLICE(pa)	(((pa) >> CMMU_NCSLICE_SHIFT) & 0xff)
+#define	CMMU_PADDR2OFFSET(pa)	((pa) & CMMU_NCSLICE_OFFSET_MASK)
+
+/*
+ * Structure defining the <ncslice, index, count> tuple.
+ */
+struct wrsm_cmmu_tuple {
+	ncslice_t ncslice;
+	wrsm_cmmu_offset_t offset;
+	wrsm_cmmu_index_t index;
+	unsigned  count;
+};
+
+/*
+ * Initializes the CMMU allocator, including providing an initialial list
+ * of WCIs. This initial list is used to determine the max CMMU entries
+ * for this instance of the CMMU allocator.
+ */
+void wrsm_cmmu_init(wrsm_network_t *, unsigned nwcis, struct wci_ids wcis[]);
+
+/*
+ * Destroys the CMMU allocator and frees any data structures.
+ */
+void wrsm_cmmu_fini(wrsm_network_t *);
+
+/*
+ * Informs the CMMU allocator of a new WCI. Returns non-zero if the
+ * new WCI doesn't support a large enough CMMU.
+ */
+int wrsm_cmmu_newwci(wrsm_network_t *, lcwci_handle_t);
+
+/*
+ * Informs the CMMU allocator that a WCI is no longer part of this
+ * RSM controller.
+ */
+int wrsm_cmmu_delwci(wrsm_network_t *, lcwci_handle_t);
+
+/*
+ * Allocates a range of entries, and allocates and returns a buffer containing
+ * the tuples describing the CMMU entries and the ncslice they map to. The
+ * caller frees the CMMU entries AND the buffer by calling wrsm_cmmu_free.
+ * Arguments:
+ *   net - Pointer to this network.
+ *   page_size - Desired page size, small or large.
+ *   nentries - The number of CMMU entries being requested.
+ *   tuples - An array of tuples allocated by the function. The memory will
+ *       be freed in wrsm_cmmu_free.
+ *   ntuples - The number of tuples actually written by this function.
+ * Returns: ENOMEM if there aren't enough free CMMU entries for the request.
+ */
+int wrsm_cmmu_alloc(wrsm_network_t *net, wrsm_cmmu_page_size_t page_size,
+    unsigned nentries, wrsm_cmmu_tuple_t **tuples, unsigned *ntuples,
+    boolean_t sleep);
+
+/*
+ * Frees a range of entries allocated with wrsm_cmmu_alloc(). The tuples
+ * pointer must be the unaltered buffer allocated in wrsm_cmmu_alloc. This
+ * function will free the CMMU entries and free the tuples buffer.
+ */
+void wrsm_cmmu_free(wrsm_network_t *, unsigned ntuples,
+    wrsm_cmmu_tuple_t *tuples);
+
+/*
+ * Allocates a CMMU entry for driver communication at a specific
+ * ncslice/offset. Unlike wrsm_cmmu_alloc, this function does not
+ * allocate any memory -- the caller must provide a single tuple
+ * buffer where the result is placed. CMMU entries allocated
+ * with this function must be freed by wrsm_cmmu_comm_free.
+ * Arguments:
+ *   net - Pointer to this network.
+ *   ncslice - Desired ncslice.
+ *   offset - Desired offset.
+ *   tuple - Returned value indicating ncslice/offset/index/count. The ncslice
+ *	and offset will match the values passed in, and the count will be 1.
+ */
+int wrsm_cmmu_comm_alloc(wrsm_network_t *net, ncslice_t ncslice,
+    wrsm_cmmu_offset_t offset, wrsm_cmmu_tuple_t *tuple);
+
+
+/*
+ * Frees a single cmmu entry allocated by wrsm_cmmu_comm_alloc(). Since
+ * wrsm_cmmu_comm_alloc does not allocate memory, this function does not
+ * free the memory pointed to by tuple.
+ */
+void wrsm_cmmu_comm_free(wrsm_network_t *net, wrsm_cmmu_tuple_t *tuple);
+
+/*
+ * Writes an entry, only updating the fields specified by the flags
+ * parameter. Does not check to make sure the CMMU entry has been allocated.
+ */
+void wrsm_cmmu_update(wrsm_network_t *, wrsm_cmmu_t *entry,
+	wrsm_cmmu_index_t index, wrsm_cmmu_flags_t);
+
+/*
+ * Reads a CMMU entry, uses an arbitrary WCI.
+ */
+void wrsm_cmmu_read(wrsm_network_t *, wrsm_cmmu_t *entry, wrsm_cmmu_index_t);
+
+/*
+ * Other RSM controller-wide register functions. These don't specifically
+ * modify the CMMU, but act across all WCIs, like the CMMU manipulation
+ * functions do.
+ */
+
+/*
+ * Sets the bit for a particular cnode in the cluster member bits of
+ * all WCIs associated with this RSM network.
+ */
+void wrsm_clustermember_add(wrsm_network_t *, cnodeid_t cnode);
+
+/*
+ * Clears the bit for a particular cnode in the clsuter member bits of
+ * all WCIs associated with this RSM network.
+ */
+void wrsm_clustermember_delete(wrsm_network_t *, cnodeid_t cnode);
+
+/*
+ * Returns a list of all cnode bits set in the cluster member bits register.
+ * Uses a specific WCI's cluster_member_bits register, but all WCIs should
+ * have the same setting.
+ */
+void wrsm_clustermember_list(wrsm_network_t *,  cnode_bitmask_t *);
+
+/*
+ * Sets the mode of a particular ncslice in the wci_nc_slice_config_array.
+ */
+void wrsm_ncsliceconfig_set(wrsm_network_t *, ncslice_t ncslice,
+			wrsm_ncslice_mode_t mode);
+/*
+ * Returns the mode of the given ncslice.
+ */
+wrsm_ncslice_mode_t wrsm_ncsliceconfig_get(wrsm_network_t *, ncslice_t);
+
+/*
+ * Returns the number of free cmmu entires
+ */
+wrsm_cmmu_index_t wrsm_cmmu_num_free(wrsm_network_t *);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _WRSM_CMMU_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_common.h b/usr/src/uts/sun4u/sys/wrsm_common.h
new file mode 100644
index 0000000000..d509ba242f
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_common.h
@@ -0,0 +1,358 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2001-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _WRSM_COMMON_H
+#define	_WRSM_COMMON_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/dditypes.h>
+#include <sys/mutex.h>
+#include <sys/condvar.h>
+#include <sys/thread.h>
+#include <sys/kstat.h>
+
+#ifdef _KERNEL
+#include <vm/page.h>
+#include <sys/ddidevmap.h>
+#include <sys/rsm/rsmpi.h>
+#endif
+#include <sys/wci_offsets.h>
+#include <sys/wrsm_types.h>
+
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef wrsm_ncslice_bitmask_t ncslice_bitmask_t;
+typedef wrsm_cnode_bitmask_t cnode_bitmask_t;
+typedef wrsm_wnode_bitmask_t wnode_bitmask_t;
+typedef wrsm_fmnodeid_t fmnodeid_t;
+typedef wrsm_cnodeid_t cnodeid_t;
+typedef wrsm_wnodeid_t wnodeid_t;
+typedef wrsm_gnid_t gnid_t;
+typedef wrsm_ncslice_t ncslice_t;
+typedef wrsm_linkid_t linkid_t;
+typedef wrsm_safari_port_t safari_port_t;
+
+/*
+ * Cacheline-size related constants
+ */
+#define	WRSM_CACHELINE_SIZE	64
+#define	WRSM_CACHELINE_SHIFT	6
+#define	WRSM_CACHELINE_MASK	(WRSM_CACHELINE_SIZE - 1)
+
+/*
+ * This is a more meaningful name for the errno return value of 0. It
+ * is used by functions that return/expect errno values.
+ */
+#define	WRSM_SUCCESS	0
+
+/*
+ * Hash for fmnodeid to node pointer mapping.
+ * Most likely the fmnodeid will be a low integer.
+ */
+#define	WRSM_CNODE_HASH_SIZE	0x100	/*  number of entries in hash table */
+#define	WRSM_CNODE_HASH_MASK	(WRSM_CNODE_HASH_SIZE - 1)
+#define	WRSM_CNODE_HASH_FUNC(r) \
+		(((uint_t)r) & WRSM_CNODE_HASH_MASK)
+
+/*
+ * 8 is the lower bound allowed before we are required to start freezing
+ * Request Agent (RAG) instances per PRM
+ */
+#define	WRSM_RAG_FREEZE_NODE_LIMIT 8
+/*
+ * additional bit mask manipulation macros
+ */
+uint_t wrsmset_cmp(uint32_t *s1, uint32_t *s2, int masksize);
+uint_t wrsmset_isnull(uint32_t *s, int masksize);
+
+/* Copy bits from set1 to set2 */
+#define	WRSMSET_COPY(src, dest) bcopy(&(src), &(dest), sizeof (src))
+#define	WRSMSET_ISEQUAL(set1, set2) \
+	(wrsmset_cmp((uint32_t *)&(set1), (uint32_t *)&(set2),	\
+	WRSMMASKSIZE(set1)))
+#define	WRSMSET_ISNULL(set) \
+	(wrsmset_isnull((uint32_t *)&(set), WRSMMASKSIZE(set)))
+
+#define	WRSMSET_OR(set1, set2) {				\
+		int _i;						\
+		uint32_t *_s1 = (uint32_t *)&(set1);		\
+		uint32_t *_s2 = (uint32_t *)&(set2);		\
+		for (_i = 0; _i < WRSMMASKSIZE(set1); _i++)	\
+			*_s1++ |= *_s2++;			\
+	}
+
+#define	WRSMSET_AND(set1, set2) {				\
+		int _i;						\
+		uint32_t *_s1 = (uint32_t *)&(set1);		\
+		uint32_t *_s2 = (uint32_t *)&(set2);		\
+		for (_i = 0; _i < WRSMMASKSIZE(set1); _i++)	\
+			*_s1++ &= *_s2++;			\
+	}
+
+#define	WRSMSET_DIFF(set1, set2) {				\
+		int _i;						\
+		uint32_t *_s1 = (uint32_t *)&(set1);		\
+		uint32_t *_s2 = (uint32_t *)&(set2);		\
+		for (_i = 0; _i < WRSMMASKSIZE(set1); _i++)	\
+			*_s1++ &= ~*_s2++;			\
+	}
+
+
+/*
+ * in the node->link_stripes field, this is the number of bits to
+ * shift to get to the bit referring to the next link in the same wci
+ */
+#define	BBIT_LINK_STRIDE	4
+
+
+/* opaque type for LC's handle */
+typedef struct wrsm_soft_state *lcwci_handle_t;
+/* opaque type for NC's handle */
+typedef struct wrsm_ncwci *ncwci_handle_t;
+
+
+/*
+ * typedefs for opaque structure definitions (for structures private to
+ * particular wrsm modules, declared in module specific header files)
+ */
+typedef struct wrsm_node_routeinfo wrsm_node_routeinfo_t;
+typedef struct wrsm_node_memseg wrsm_node_memseg_t;
+
+typedef struct wrsm_transport wrsm_transport_t;
+typedef struct wrsm_session wrsm_session_t;
+typedef struct wrsm_cmmu_alloc wrsm_cmmu_alloc_t;
+typedef struct wrsm_interrupt wrsm_interrupt_t;
+typedef struct wrsm_nr wrsm_nr_t;
+typedef struct wrsm_memseg wrsm_memseg_t;
+
+typedef struct __rsm_controller_handle wrsm_network_t;
+typedef struct wrsm_node wrsm_node_t;
+
+typedef struct wrsm_cmmu_tuple wrsm_cmmu_tuple_t;
+
+
+
+/*
+ * configuration states
+ */
+typedef enum {
+	wrsm_disabled,	/* new config, no ncslice rerouting allowed */
+	wrsm_pending,	/* can reroute using old/new config intersection */
+	wrsm_installed,	/* ncslice routes are not using old config */
+	wrsm_installed_up,	/* all links in new config are up */
+	wrsm_enabled		/* ncslice routes are using new config */
+} wrsm_availability_t;
+
+#define	WRSM_INSTALLED(n)			\
+	((n)->availability == wrsm_enabled ||	\
+	(n)->availability == wrsm_installed ||	\
+	(n)->availability == wrsm_installed_up)
+
+/*
+ * state of communication to node
+ */
+typedef enum {
+	wrsm_node_needroute,	/* no ncslice routes to node */
+	wrsm_node_haveroute	/* ncslice route set up */
+} wrsm_node_comm_state_t;
+
+#define	WRSM_NODE_HAVE_ROUTE(n) ((n)->state == wrsm_node_haveroute)
+
+
+
+/*
+ * information about a remote node participating in an RSM network
+ */
+struct wrsm_node {
+	wrsm_network_t *network;		/* this node's RSM network */
+	wrsm_net_member_t *config;		/* node config info */
+	wrsm_availability_t availability;	/* configuration state */
+	wrsm_node_comm_state_t state;		/* communication state */
+	uint32_t *link_stripesp;		/* stripe info for barrier */
+
+	/*
+	 * wrsm module private info about node
+	 */
+	wrsm_node_routeinfo_t *routeinfo;	/* routing config for node */
+
+	/*
+	 * The following structures are for tracking RSMPI data structures.
+	 */
+	wrsm_node_memseg_t *memseg;		/* RSMPI segments */
+	caddr_t cesr_vaddr;		/* vaddr of WCI CESRs for barriers */
+	caddr_t lockout_vaddr;		/* vaddr of write lockout page */
+
+	/*
+	 * links
+	 */
+	struct wrsm_node *hash;		/* linked list for hash table */
+};
+
+
+
+
+/*
+ * The RSM controller's view of the RSM network it is participating in.
+ */
+#ifdef _KERNEL
+struct __rsm_controller_handle {
+	uint32_t rsm_ctlr_id;		/* ctlr id == device instance # */
+	kmutex_t lock;
+	dev_info_t *dip;		/* dev_info_t for controller */
+	uint64_t version_stamp;		/* configuration version number */
+	boolean_t registered;		/* registered with RSMPI module */
+	wrsm_availability_t availability; /* state of the configuration */
+	cnodeid_t cnodeid;		/* local node's cnodeid */
+	wrsm_node_t *mynode;		/* local node info */
+	wrsm_node_ncslice_array_t exported_ncslices;
+					/* ncslices local node exports */
+	int wrsm_ncslice_users[WRSM_MAX_NCSLICES];
+					/* per ncslice count of ncslice users */
+	boolean_t have_lg_page_ncslice;	/* any ncslices for large pages? */
+	wrsm_cmmu_tuple_t *errorpage_tuple; /* loopback error CMMU entry */
+	pfn_t errorpage_pfn;		/* pfn for loopback error page */
+	kmutex_t errorpage_lock;	/* updating errorpage_mappings */
+	uint_t errorpage_mappings;	/* # mappings to error page */
+
+	wrsm_node_t *nodes[WRSM_MAX_CNODES]; /* array of remote node info */
+	wrsm_node_t *node_hash[WRSM_CNODE_HASH_SIZE]; /* nodeinfo hashtable */
+
+	/*
+	 * route_umem is the kernel allocated address space that
+	 * can also be mapped to user space. both route_countp
+	 * and reroutingp will point to an address range within
+	 * route_umem. the wrsm plug-in uses this address range
+	 * when it mmaps route_counter and rerouting to user space
+	 * the plug-in requires these fields when it must preform
+	 * explicit barriers, as the plugin must check to see if the
+	 * routing has changed.
+	 */
+	void *route_umem;		/* returned by ddi_umem_alloc  */
+	uint32_t *route_counterp;	/* increment on ncslice route change */
+	uint32_t *reroutingp;		/* in process of ncslice rerouting */
+	ddi_umem_cookie_t route_cookie; /* cookie needed to free *route_umem */
+	uint_t passthrough_routes;	/* how many PT routes been set up? */
+
+	/* keeps track of controller opened by plugin library */
+	boolean_t is_controller_open;
+
+	/*
+	 * wrsm module private info about network
+	 */
+	wrsm_interrupt_t *interrupt;
+	wrsm_transport_t *transport;	/* transport info */
+	wrsm_session_t *session;	/* session info */
+	wrsm_cmmu_alloc_t *cmmu;	/* cmmu allocator info */
+	wrsm_nr_t *nr;			/* network router info */
+	int wrsm_num_nodes;		/* number of nodes in this network */
+	boolean_t free_rag_instance;	/* frozen RAG instances can be freed */
+
+	/*
+	 * NC info
+	 */
+	boolean_t auto_enable;		/* links-up/timeout enables network */
+	timeout_id_t enable_timeout_id;
+
+	/*
+	 * links
+	 */
+	wrsm_network_t *next;
+
+	/*
+	 * RSMPI information
+	 */
+	wrsm_memseg_t *memseg;		/* RSMPI segments */
+	rsm_controller_attr_t attr;	/* RSMPI controller attributes */
+
+	/*
+	 * Kstat for the controller
+	 */
+	kstat_t *wrsm_rsmpi_stat_ksp;
+	uint_t num_reconfigs;
+	uint_t sendqs_num;
+	uint_t handler_num;
+};
+
+#endif /* KERNEL */
+
+extern dev_info_t *wrsm_ncslice_dip;	/* devinfo for ncslice mappings */
+#define	PROTOCOLS_SUPPORTED	1
+/*
+ * The protocol_versions_supported is a bit mask representing all the
+ * protocol versions that this driver supports.
+ */
+extern uint32_t protocol_versions_supported;
+extern int protocol_version;		/* version native to this driver */
+
+wrsm_node_t *
+wrsm_fmnodeid_to_node(wrsm_network_t *network,
+    fmnodeid_t fmnodeid);
+
+int
+wrsm_fmnodeid_to_cnodeid(wrsm_network_t *network,
+    fmnodeid_t fmnodeid, cnodeid_t *cnodeidp);
+
+wrsm_network_t *wrsm_dip_to_network(dev_info_t *dip);
+
+/*
+ * initialization and teardown functions for WRSM modules - called from
+ * driver _init and _fini
+ */
+extern void wrsm_nc_init(void);
+extern int wrsm_nc_fini(void);
+/*
+ * Functions which make up wrsm_nc_fini() - these can be called individually
+ * to separate checks from cleanup - called from driver _fini
+ */
+extern int wrsm_nc_check(void);
+extern void wrsm_nc_cleanup(void);
+
+#ifdef DEBUG
+#define	DEBUG_LOG
+extern void dprintnodes(cnode_bitmask_t);
+#define	DPRINTNODES(c) dprintnodes(c)
+extern kmutex_t wrsmdbglock;
+extern int wrsmdbginit;
+extern char wrsmdbgbuf[];
+extern int wrsmdbgsize;
+extern int wrsmdbgnext;
+void wrsmdprintf(int ce, const char *fmt, ...);
+#else
+#define	DPRINTNODES(c)
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _WRSM_COMMON_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_config.h b/usr/src/uts/sun4u/sys/wrsm_config.h
new file mode 100644
index 0000000000..7377a06e97
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_config.h
@@ -0,0 +1,386 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _WRSM_CONFIG_H
+#define	_WRSM_CONFIG_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifndef _ASM
+#include <sys/types.h>
+#include <sys/wrsm_types.h>
+#endif /* _ASM */
+
+/*
+ * Macro to guarantee proper pointer alignment in 32 or 64 bit mode
+ */
+#if defined(_LP64)
+#define	WRSM_ALIGN_64(t, n) t n
+#define	WRSM_ALIGN_PTR(n) n
+#else
+#define	WRSM_ALIGN_64(t, n) union {  struct {uint32_t pad; t n; } val; \
+				uint64_t align; } u_##n
+#define	WRSM_ALIGN_PTR(n) u_##n.val.##n
+#endif
+/*
+ * If any of the data structures in this file are changed,
+ * WRSM_CF_IOCTL_VERSION must be incremented.
+ */
+#define	WRSM_CF_IOCTL_VERSION 0x0e
+#define	CONFIG_PROTOCOL_VERSION 0x2
+
+#define	WRSM_MAX_WCIS		(18 * 3) /* CPU WIB + IO WIB in Starcat */
+#define	WRSM_MAX_SWITCHES	38
+#define	WRSM_HOSTNAMELEN	255
+
+#ifndef _ASM
+
+/*
+ *  network routing methods used by preferred_route
+ */
+typedef enum {
+	routing_multihop,
+	routing_passthrough
+} wrsm_routing_method_t;
+
+/*
+ *  network topology types used to give hints to the multihop routing
+ *  algorithm.
+ */
+typedef enum {
+	topology_central_switch,
+	topology_distributed_switch,
+	topology_san_switch
+} wrsm_topology_t;
+
+typedef enum {
+	ncslice_invalid = 0x0,
+	ncslice_passthrough = 0x1,
+	ncslice_small_page = 0x2,
+	ncslice_large_page = 0x3
+} wrsm_ncslice_mode_t;
+
+/*
+ * information about each link attached to a wci
+ */
+typedef struct wrsm_link_data {
+	boolean_t present;	 /* does this link exist? */
+	wrsm_gnid_t remote_gnid; /* gnid of wci on remote side */
+	wrsm_safari_port_t remote_port; /* bus port number of remote wci */
+	uint32_t remote_link_num;
+} wrsm_link_data_t;
+
+
+/*
+ * routing related information about each wci
+ */
+struct wrsm_wci_data {
+	/*
+	 * bus port number - unique within a chassis
+	 */
+	wrsm_safari_port_t port;
+	wrsm_wnodeid_t local_wnode;
+	wrsm_gnid_t local_gnid;	 /* This Wci's gnid */
+	boolean_t route_map_striping;
+	wrsm_topology_t topology_type;
+	/* cnodes potentially accessible through this WCI, indexed by wnodeid */
+	wrsm_cnodeid_t reachable[WRSM_MAX_WNODES];
+	/* gnid to wnode mapping for this WCI, indexed by gnid */
+	wrsm_wnodeid_t gnid_to_wnode[WRSM_MAX_WNODES];
+	/*
+	 * if wnode_reachable[n] == B_TRUE then reachable[n]
+	 * contains a valid reachable cnodeid and gnid_to_wnode[n]
+	 * contains a valid wnode.
+	 */
+	boolean_t wnode_reachable[WRSM_MAX_WNODES];
+	/* Data about links directly connected to this WCI. */
+	wrsm_link_data_t links[WRSM_MAX_LINKS_PER_WCI];
+};
+
+/*
+ * identify wcis which may be used together for striping
+ */
+typedef struct wrsm_stripe_group {
+	uint32_t group_id;
+	int nwcis;
+	/*
+	 * The order of the wcis in this list determines which address
+	 * stripe each wci is assigned.  For Starcat, it is required that
+	 * the wcis are in adjacent expanders, that the lower wci is
+	 * specified first, and that the first expander has an expander id
+	 * that's divisible by 2 (0,2,4..).  Also, for Starcat a maximum of
+	 * 2 wcis can be striped.
+	 */
+	wrsm_safari_port_t wcis[WRSM_MAX_WCIS_PER_STRIPE];
+} wrsm_stripe_group_t;
+
+/*
+ * Description of one possible method to route data to a remote node.
+ */
+typedef struct wrsm_preferred_route {
+	int striping_level;   /* level of striping desired */
+	wrsm_routing_method_t method;
+	/*
+	 * ordered list of preferred passthrough cnodeids
+	 */
+	int nswitches;
+	wrsm_cnodeid_t switches[WRSM_MAX_SWITCHES];
+	/*
+	 * A preferred route may indicate either a WCI
+	 * to use or a stripe group, but not both.
+	 */
+	enum {
+		route_stripe_group = 1,
+		route_wci
+	} route_type;
+	union {
+		uint_t stripe_group_id;
+		wrsm_safari_port_t wci_id;
+	} route;
+} wrsm_preferred_route_t;
+
+/*
+ * Information about how to route data to remote network members.
+ */
+typedef struct wrsm_routing_policy {
+	wrsm_cnodeid_t cnodeid;	  /* destination cnodeid */
+	/*
+	 * must the number of links per WCI be equal?
+	 */
+	boolean_t wcis_balanced;
+	/*
+	 * Is the number of stripes more important than the order of
+	 * the preferred routes?
+	 */
+	boolean_t striping_important;
+	/*
+	 * is passthrough forwarding to this node allowed?
+	 */
+	boolean_t forwarding_allowed;
+	/*
+	 * If forwarding is allowed, this bitmask contains import ncslice ids
+	 * each remote network member uses to access ncslices exported by this
+	 * node.
+	 */
+	wrsm_ncslice_bitmask_t forwarding_ncslices;
+
+	int nroutes;		  /* number of preferred routes */
+	WRSM_ALIGN_64(wrsm_preferred_route_t **, preferred_routes);
+} wrsm_routing_policy_t;
+
+/*
+ * Information on how to communicate with all the remote rsm nodes.
+ */
+typedef struct wrsm_routing_data {
+	int nwcis;
+	int ngroups;
+	int npolicy;
+	boolean_t other_routes_allowed;
+
+	/*
+	 * WCIs owned by this controller, sorted in ascending
+	 * order by the safari port id of the wci.
+	 */
+	WRSM_ALIGN_64(wrsm_wci_data_t **, wcis);
+	/*
+	 * List of stripe groups sorted in ascending
+	 * order by stripe group id.
+	 */
+	WRSM_ALIGN_64(wrsm_stripe_group_t **, stripe_groups);
+	/*
+	 * list of routing policies for each remote cnode,
+	 * sorted in ascending order by cnodeid.
+	 */
+	WRSM_ALIGN_64(wrsm_routing_policy_t **, policy);
+	/*
+	 * Are routes not explicitly listed permitted given the
+	 * available connectivity in the network?
+	 */
+} wrsm_routing_data_t;
+
+/*
+ * Information the local node needs to know about every other rsm node
+ * in the network.
+ */
+struct wrsm_net_member {
+	wrsm_cnodeid_t cnodeid;		/* wrsm_net member's cnode id */
+	wrsm_fmnodeid_t fmnodeid;	/* FM node id */
+	char hostname[WRSM_HOSTNAMELEN];
+
+	/*
+	 * Exported_ncslices is the ncslices the remote node (the node this
+	 * wrsm_net_member is describing) exports memory through; these are
+	 * the ncslices the local node (the node that is using the config
+	 * containing this wrsm_net_member) uses to import the remote
+	 * node's memory.
+	 */
+	wrsm_node_ncslice_array_t exported_ncslices;
+
+	/*
+	 * Imported ncslices is the set of ncslices the remote node uses to
+	 * access the local node's exported memory.  Each node may use
+	 * different ncslices to import memory from the local node.  The
+	 * local node sets up the WCI hardware to allow access using these
+	 * ncslices.
+	 */
+	wrsm_node_ncslice_array_t imported_ncslices;
+
+	/*
+	 * ncslice and offset to use to send interrupt based communication to
+	 * wrsm_net_member's driver
+	 */
+	wrsm_ncslice_t comm_ncslice;
+	uint64_t comm_offset;
+	/*
+	 * offset that should be set up to allow interrupts to be received
+	 * from wrsm_net_member's driver (the ncslice is the small page
+	 * ncslice specified in the exported_ncslices structure of the
+	 * wrsm_net_member structure for the local controller).
+	 */
+	uint64_t local_offset;
+};
+
+
+/*
+ * Configuration data about a particular rsm controller.
+ *
+ * An RSM network is a set of communicating RSM nodes.  A "controller" is
+ * the node-local view of an RSM network.  The wrsm_controller_t structure
+ * contains the configuration information the node needs to participate in
+ * the network.  There is one controller for each node in a network, and
+ * the controller_id of each communicating controller matches the network
+ * id of the network it is part of.
+ */
+typedef struct wrsm_controller {
+	/*
+	 * version number to track changes in the definition of
+	 * the data structures in this file.
+	 */
+	uint32_t config_protocol_version;
+	uint32_t controller_id;		/* RSM network id */
+	wrsm_fmnodeid_t fmnodeid;  	/* FM node id */
+	char hostname[WRSM_HOSTNAMELEN]; /* solaris hostname of local node */
+	/*
+	 * version number to identify the version of the RSM network
+	 * this wrsm_controller_t is participating in.
+	 */
+	uint64_t version_stamp;
+	wrsm_cnodeid_t cnodeid;
+	int nmembers;	/* number of elements in the members list */
+	/*
+	 * routing data
+	 */
+	WRSM_ALIGN_64(wrsm_routing_data_t *, routing);
+	/*
+	 * List of network members sorted by cnodeid
+	 */
+	WRSM_ALIGN_64(wrsm_net_member_t **, members);
+} wrsm_controller_t;
+
+
+
+/*
+ * Used as argument to INITIALCFG, REPLACECFG and GETCFG ioctls
+ */
+typedef struct wrsm_admin_arg_config {
+	uint32_t ioctl_version;
+	uint32_t controller_id;
+	uint64_t controller_data_size;
+	WRSM_ALIGN_64(wrsm_controller_t *, controller);
+} wrsm_admin_arg_config_t;
+
+/*
+ * Used as argument to INSTALLCFG, CHECKCFG, and ENABLECFG ioctls
+ */
+typedef struct wrsm_admin_arg_wci {
+	uint32_t ioctl_version;
+	uint32_t controller_id;
+	uint64_t nwcis;
+	WRSM_ALIGN_64(wrsm_safari_port_t *, wci_ids);
+} wrsm_admin_arg_wci_t;
+
+/*
+ * Used as argument to CTLR_PING ioctl
+ */
+typedef struct wrsm_ping_arg {
+	uint32_t ioctl_version;
+	wrsm_cnodeid_t target;
+	uint32_t count;
+	uint64_t time;   /* total ping time in us */
+} wrsm_ping_arg_t;
+
+/*
+ * Used as argument to CTLR_MBOX ioctl
+ */
+typedef struct wrsm_link_arg {
+	uint32_t ioctl_version;
+	int cmd;
+	wrsm_safari_port_t wci_id;
+	wrsm_linkid_t link_num;
+	uint32_t led_state;
+	uint32_t link_state;
+} wrsm_link_arg_t;
+
+
+/*
+ * Used as argument to CTLR_SEG ioctl
+ */
+typedef struct wrsm_seg_arg {
+	uint32_t ioctl_version;
+	int cmd;
+	uint_t segid;
+	uint_t addr;
+	uint64_t bytes;
+	uint64_t offset;
+	uint64_t length;
+	char *datap;
+	uint_t barrier_mode;
+} wrsm_seg_arg_t;
+
+
+/*
+ * Used as argument to CTLR_SESS ioctls
+ */
+typedef struct wrsm_sess_arg {
+	uint32_t ioctl_version;
+	int cmd;
+	wrsm_cnodeid_t cnodeid;
+	wrsm_cnode_bitmask_t cnode_bitmask;
+} wrsm_sess_arg_t;
+
+extern void *wrsm_cf_pack(wrsm_controller_t *cont, int *sizep);
+
+#endif /* _ASM */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _WRSM_CONFIG_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_driver.h b/usr/src/uts/sun4u/sys/wrsm_driver.h
new file mode 100644
index 0000000000..5251d0bb7b
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_driver.h
@@ -0,0 +1,251 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _SYS_WRSM_DRIVER_H
+#define	_SYS_WRSM_DRIVER_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/wci_offsets.h>
+#include <sys/wrsm_common.h>
+#include <sys/wrsm_config.h>
+#include <sys/wci_common.h>
+#include <sys/wrsm.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * only wrsm_driver.c should include this header.
+ * all others should include wrsm_lc.c
+ */
+
+/*
+ * Timeout periods in seconds.  (Multiplied by MICROSEC to get the number
+ * of microsecs for the requested number of seconds - for drv_to_hz().)
+ */
+#define	WRSM_POLL_TIMEOUT_USEC (1 * MICROSEC) /* interval for polling links */
+#define	WRSM_RESTART_TIMEOUT_USEC (120 * MICROSEC) /* link restart timeout */
+/* shortterm interval is given in minutes */
+#define	WRSM_SHORTTERM_USEC (wrsm_shortterm_interval * 60 * MICROSEC)
+#define	WRSM_LINK_MAX_WAIT_COUNT	60 /* Poll periods */
+#define	WRSM_AVG_WEIGHT			10
+#define	WRSM_SHORTTERM_INTERVAL		60
+#define	WRSM_SHORTS_PER_LONGTERM	24
+
+
+/*
+ * index of register ranges in "registers" property
+ */
+#define	WRSM_REGS	0
+#define	WRSM_SRAM	1
+#define	ROUTEMAPRESET	0x0FFFFFFFFFFFFULL	/* set 16 link 3 bits = 0x7 */
+#define	CE_CNTMAX	0xFF			/* reset value for ce_count */
+#define	REGMASK		0x1F			/* mask for lower reg bits */
+
+#define	UNMASKALL	0x0ULL			/* unmask all bit fields */
+#define	MASKALL		0xFFFFFFFFFFFFFFFFULL
+
+/*
+ * WRSM  OBP properties
+ */
+
+#define	OBP_WRSM_PORTID	"portid"
+#define	WRSM_RSM_CTR 	"rsm_controller"
+#define	WRSM_ADMIN  	"admin"
+
+#define	MAXERRORS	1000
+
+typedef union {
+	struct {
+		boolean_t bad_linknum : 1;
+		boolean_t bad_safari_port_id : 1;
+		boolean_t bad_gnid : 1;
+		boolean_t bad_cnode : 1;
+		boolean_t bad_ctlr_version : 1;
+		boolean_t bad_ctlr_id : 1;
+		boolean_t bad_reachablewnode : 1;
+		boolean_t bad_common_version : 1;
+	} reasons;
+	uint32_t val;
+} wrsm_linkbadconfig_reasons_t;
+
+typedef enum {
+	wrsm_device,		/* a real WCI */
+	wrsm_rsm_controller,	/* a pseudo dev for an RSM controller */
+	wrsm_admin		/* the wrsm admin pseudo dev */
+} wrsm_devi_type_t;
+
+
+typedef struct {
+	volatile uint64_t *wrsm_link_err_cnt_addr; /* pre-calc offset */
+	wrsm_link_req_state_t link_req_state; /* link state */
+	wrsm_linkbadconfig_reasons_t badconfig_reasons;
+	boolean_t tell_mh_link_is_up;	/* if TRUE call call mh_link_is_up */
+					/* for links just coming up */
+	boolean_t user_down_requested;	/* user ioctl requested link down */
+	boolean_t loopback_test_mode;
+	wnodeid_t remote_wnode;
+	uint32_t interval_count;
+	uint32_t cont_errs;	/* # of times in a row polling found errors */
+	uint32_t err_takedown_sum;
+	uint32_t num_err_takedown;
+	uint32_t last_err_takedown;
+	uint32_t max_err_takedown;
+	uint32_t avg_err_takedown;
+	uint32_t num_cfg_takedown;
+	uint32_t num_disconnected_takedown;
+	uint32_t num_requested_bringups;
+	uint32_t num_completed_bringups;
+	uint32_t num_errors;
+	uint32_t shortterm_errsum;
+	uint32_t shortterm_last_errors;
+	uint32_t shortterm_max_errors;
+	uint32_t shortterm_avg_errors;
+	uint32_t longterm_shortterms;
+	uint32_t longterm_errsum;
+	uint32_t longterm_last_errors;
+	uint32_t longterm_max_errors;
+	uint32_t longterm_avg_errors;
+	uint16_t remote_gnids_active;
+	uint32_t waiting_count;
+	boolean_t poll_reachable;  /* remote end is wcx ready to be polled */
+} link_t;
+
+/* globals */
+/* weight of old average in error average */
+extern uint_t wrsm_avg_weight;
+/* minutes in shortterm error interval */
+extern uint_t wrsm_shortterm_interval;
+/* number of shortterm intervals per long term interval */
+extern uint_t wrsm_shorts_per_longterm;
+
+/*
+ * lc_mutex primarily is used to secure changes to the link states
+ * however, in addition to protecting per link states changes, the counters:
+ * oldlink_waitdown_cnt and newlink_waitup_cnt must also
+ * be protected from changes of different threads. lc_mutex is also
+ * used to protect any access to softsp->config.
+ * newlink_waitup_cnt is important for keeping track of the NEW bringup
+ * link requested initiated in lc_installconfig.
+ * oldlink_waitdown_cnt is important for keeping track of the lc_cleanconfig
+ * initiated takedown request.
+ * the count of oldlink_waitdown_cnt & newlink_waitup_cnt is how the LC
+ * differentiates between events in the LC forcing takedowns and bringup
+ * and external events requesting takedown and bringups. These two counters
+ * increment on request and they are decremented when the task is done.
+ * They are both 0 when there are no pending external request.
+ * Polling on a link starts in wciinit and ends in wcifini
+ */
+struct wrsm_soft_state {
+	dev_info_t *dip;		/* dev info of myself */
+	timeout_id_t err_timeout_id;	/* non-zero means link polling active */
+	boolean_t need_err_timeout;	/* err timeout was DDI_SUSPENDED */
+	timeout_id_t restart_timeout_id; /* timeout handle for link restart */
+	boolean_t need_restart_timeout;	/* restart timeout was DDI_SUSPENDED */
+	boolean_t suspended;		/* ddi-suspended */
+	int instance;			/* DDI instance */
+	int minor;			/* device minor number */
+	int board;			/* Board number */
+	cnodeid_t local_cnode;
+	wnodeid_t local_wnode;
+	gnid_t    local_gnid;
+	wnodeid_t gnid_to_wnode[WRSM_MAX_WNODES];
+
+	safari_port_t portid;		/* safari extended agent id */
+	kmutex_t lc_mutex;		/* lock for link related task */
+	kmutex_t wrsm_mutex;		/* mutex to protect open file flag */
+	kmutex_t cmmu_mutex;		/* CMMU FLUSH mutex */
+	kcondvar_t goinstallconfig;	/* condition var to signal */
+					/* lc_installconfig clear to go */
+	int oldlink_waitdown_cnt;	/* cnt of takedown request on old */
+					/* links/existing links */
+	int newlink_waitup_cnt;		/* cnt of new bringup link request */
+	int open;			/* flag indicates if device is open */
+	link_t links[WRSM_LINKS_PER_WCI];	/* optical links */
+	clock_t shortterm_start;
+	wrsm_devi_type_t type;		/* type of device  */
+
+	off_t sramsize;
+	unsigned char *wrsm_sram;	/* paddr for SRAM */
+	volatile unsigned char *wrsm_regs;	/* vaddr WRSM regs */
+
+	/*
+	 * wci revision: wci1, wci2 or wci3 where
+	 * wci 1 wci_id.parid = 0x4776
+	 * wci 2 wci_id.parid =  0x4147
+	 * wci 3 wci_id.parid =  0x4063
+	 */
+	int wci_rev;			/* wci1, wci2, wci3 .. ? */
+	/* pre-calc offset of ecc registers */
+	volatile uint64_t *wci_dco_ce_cnt_vaddr;
+	volatile uint64_t *wci_dc_esr_vaddr;
+	volatile uint64_t *wci_dco_state_vaddr;
+
+	volatile uint64_t *wci_ca_esr_0_vaddr;
+	volatile uint64_t *wci_ra_esr_1_vaddr;
+
+	volatile uint64_t *wci_ca_ecc_addr_vaddr;
+	volatile uint64_t *wci_ra_ecc_addr_vaddr;
+
+	volatile uint64_t *wci_cci_esr_vaddr;
+
+	wrsm_wci_data_t *config;	/* configuration data for wci */
+	wrsm_controller_t *ctlr_config;	/* config for entire controller */
+	ncwci_handle_t  nc;		/* opaque NC handles */
+
+	/* WCI common soft state */
+	struct wci_common_soft_state wci_common_softst;
+
+	/* kstat structs */
+	kstat_t *wrsm_wci_ksp;
+	/* kstat saved values */
+	uint32_t uc_sram_ecc_error;
+	uint32_t sram_ecc_errsum;
+	uint32_t num_sram_ecc_errors;
+	uint32_t last_sram_ecc_errors;
+	uint32_t max_sram_ecc_errors;
+	uint32_t avg_sram_ecc_errors;	/* weighted average */
+};
+
+
+typedef struct wrsm_soft_state wrsm_softstate_t;
+
+/* Use physical address for SRAM loads/stores */
+#define	LOADPHYS(a, b) ((a) = lddphysio((uint64_t)(b)))
+#define	STOREPHYS(a, b) stdphysio((uint64_t)(b), (a))
+
+/*
+ * wrsm open flag
+ */
+#define	WRSM_OPEN_EXCLUSIVE	(-1)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_WRSM_DRIVER_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_intr.h b/usr/src/uts/sun4u/sys/wrsm_intr.h
new file mode 100644
index 0000000000..00792dcbb6
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_intr.h
@@ -0,0 +1,178 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_WRSM_INTR_H
+#define	_WRSM_INTR_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifndef _ASM
+
+#include <sys/wrsm_common.h>
+#include <sys/wrsm_cmmu.h>
+#include <sys/processor.h>
+#include <sys/rsm/rsmpi.h>
+
+#endif /* _ASM */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Limit for rsm_intr_t */
+#define	WRSM_INTR_TYPE_MAX	RSM_INTR_T_NSVC
+#define	WRSM_TL_INTR_TYPE	(RSM_INTR_T_DRV_BASE + 1) /* transport */
+#define	WRSM_SMPUT_INTR_TYPE	(RSM_INTR_T_DRV_BASE + 2) /* small put */
+
+/* Flags for wrsm_intr_create_recvq */
+#define	WRSM_CREATE_RECVQ_NOFLAGS	0x0
+#define	WRSM_CREATE_RECVQ_SLEEP		0x1
+#define	WRSM_CREATE_RECVQ_USER		0x2
+#define	WRSM_CREATE_RECVQ_INVALID	0x4
+
+/* Default value for is_wait in wrsm_intr_send() */
+#define	WRSM_INTR_WAIT_DEFAULT	-1
+
+#ifndef _ASM
+
+/*
+ * Receive Queue structures
+ */
+struct wrsm_intr_recvq;
+typedef struct wrsm_intr_recvq wrsm_intr_recvq_t;
+
+/*
+ * Client functions
+ */
+
+/* Initialize the interrupt component for this network */
+int wrsm_intr_init(wrsm_network_t *);
+
+/* Destroy the interrupt component for this network */
+void wrsm_intr_fini(wrsm_network_t *);
+
+/* The following prints all intr data structures, for debug only */
+void wrsm_intr_print(wrsm_network_t *);
+
+/*
+ * WCI Functions
+ */
+
+/* Inform the interrupt component of a new WCI. Returns -1 if add_intr fails */
+int wrsm_intr_newwci(wrsm_network_t *, lcwci_handle_t);
+
+/* Inform the interrupt component that a WCI is going away */
+void wrsm_intr_delwci(wrsm_network_t *, lcwci_handle_t);
+
+/*
+ * Handler Management Functions
+ */
+
+/* Registers a handler for a specific interrupt type - rsmpi function */
+int wrsmrsm_register_handler(rsm_controller_handle_t,
+    rsm_controller_object_t *controller_obj, rsm_intr_t type, rsm_intr_hand_t,
+    rsm_intr_hand_arg_t, rsm_addr_t senders_list[],
+    uint_t senders_list_length);
+
+/* Registers a handler for a specific interrupt type - driver function */
+int wrsm_register_handler(wrsm_network_t *,
+    rsm_controller_object_t *controller_obj, rsm_intr_t type, rsm_intr_hand_t,
+    rsm_intr_hand_arg_t, rsm_addr_t senders_list[],
+    uint_t senders_list_length);
+
+/* Unregisters a handler - rsmpi function */
+int wrsmrsm_unregister_handler(rsm_controller_handle_t, rsm_intr_t type,
+    rsm_intr_hand_t, rsm_intr_hand_arg_t);
+
+/* Unregisters a handler - driver function */
+int wrsm_unregister_handler(wrsm_network_t *, rsm_intr_t type, rsm_intr_hand_t,
+    rsm_intr_hand_arg_t);
+
+/*
+ * Receive Queue Functions
+ */
+
+/*
+ * Creates a receive queue of a given type. User must have allocated a
+ * CMMU tuple in advance.
+ */
+int wrsm_intr_create_recvq(wrsm_network_t *, rsm_intr_t type,
+    size_t num_packets, wrsm_cmmu_index_t cmmu_index, wrsm_intr_recvq_t **,
+    cnodeid_t from_cnode, void *exportseg, int flags);
+
+/* Destroys the receive queue. Caller must free the CMMU tuple. */
+void wrsm_intr_destroy_recvq(wrsm_network_t *, wrsm_intr_recvq_t *);
+
+/* Flushes in progress interrupts for the receive queue. */
+void wrsm_intr_flush_recvq(wrsm_intr_recvq_t *);
+
+/* Sends a message */
+int wrsm_intr_send(wrsm_network_t *, void *remote_addr, cnodeid_t remote_cnode,
+    void *aligned_buf, int is_flags, clock_t is_wait, int sendq_flags);
+
+/*
+ * RSMPI Functions
+ */
+
+/* Initializes RSMPI portions of intr */
+void wrsm_intr_rsminit(wrsm_network_t *);
+
+/* Cleans-up RSMPI portions of intr */
+void wrsm_intr_rsmfini(wrsm_network_t *);
+
+/* Creates a send queue */
+int wrsm_sendq_create(rsm_controller_handle_t, rsm_addr_t, rsm_intr_t,
+    rsm_intr_pri_t, size_t qdepth, uint_t flags, rsm_resource_callback_t,
+    rsm_resource_callback_arg_t, rsm_send_q_handle_t *);
+
+/* Reconfigure some of the attributes of an interrupt queue */
+int wrsm_sendq_config(rsm_send_q_handle_t, rsm_intr_pri_t, size_t qdepth,
+    uint_t flags, rsm_resource_callback_t, rsm_resource_callback_arg_t);
+
+/* Destroys an interrupt queue, freeing all resources allocated */
+int wrsm_sendq_destroy(rsm_send_q_handle_t);
+
+/* Enqueues a datagram on an interrupt queue */
+int wrsm_send(rsm_send_q_handle_t, rsm_send_t *, rsm_barrier_t *);
+
+/*
+ * Performs a 64-byte block remote read.
+ * Assumes source addressis 64-byte aligned, and does no checking.
+ */
+void wrsm_blkread(void *src, void *dst, size_t num_blocks);
+/*
+ * Performs a 64-byte block write.
+ * Assumes destination address is 64-byte aligned, and does no checking.
+ */
+void wrsm_blkwrite(void *src, void *dst, size_t num_blocks);
+
+#endif /* _ASM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WRSM_INTR_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_intr_impl.h b/usr/src/uts/sun4u/sys/wrsm_intr_impl.h
new file mode 100644
index 0000000000..fb7ff8498d
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_intr_impl.h
@@ -0,0 +1,327 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2001-2002 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_WRSM_INTR_IMPL_H
+#define	_WRSM_INTR_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Setting up recvq overflow */
+#define	WRSM_CMMU_0_ERROR_BIT	0x2
+#define	WRSM_CMMU_0_VALID	0x4000000
+#define	WRSM_CMMU_0_TYPE	(2 << 24)
+#define	WRSM_CMMU_0_FROMALL	(1 << 27)
+#define	WRSM_CMMU_0_WRITABLE	(1 << 28)
+#define	WRSM_CMMU_0_DISABLE	(WRSM_CMMU_0_ERROR_BIT | WRSM_CMMU_0_VALID | \
+				WRSM_CMMU_0_TYPE | WRSM_CMMU_0_FROMALL | \
+				WRSM_CMMU_0_WRITABLE)
+
+/*
+ * Recvq pointers are stored in a 2-level tree, implemented as an array of
+ * pointers to an array of recvq pointers. The recvq_tables array gives access
+ * to a table of 256 pointers. Each entry in recvq_tables will remain NULL
+ * until all the entries in all the existing tables are used, and a new
+ * table needs to be allocated. Tables will never be deleted to eliminate the
+ * need to lock a table from a TL1 interrupt. Given a 16-bit mondo vector
+ * argument, the macro MONDOARG2TABLE generates the index into recvq_tables,
+ * while the macro MONDOARG2TABLEINDEX generates the index into the selected
+ * table, which provides the recvq pointer.
+ *
+ *
+ *       recvq_tables[256]
+ *        _____________________________..__________
+ *       |0  |1  |2  |3  |4  |5  |6  |     |254|255|
+ *       | * |nul|nul|nul|nul|nul|nul|     |nul|nul|
+ *       |_|_|___|___|___|___|___|___|_..__|___|___|
+ *         |
+ *         | table[256]
+ *        _V_
+ *       |0  |
+ *       | *-+--> recvq with mondo arg 0
+ *       |___|
+ *       |1  |
+ *       | *-+--> recvq with mondo arg 1
+ *       |___|
+ *       |2  |
+ *       |nul|
+ *       |___|
+ *       |   |
+ *       ~   ~
+ *       |   |
+ *       |___|
+ *       |255|
+ *       |nul|
+ *       |___|
+ *
+ */
+#define	WRSM_INTR_RECVQ_TABLE_SIZE	256
+#define	WRSM_INTR_RECVQ_TABLES		256
+#define	WRSM_INTR_TABLE_MASK		0xff
+#define	WRSM_INTR_TABLE_SHIFT		8
+#define	WRSM_INTR_INDEX_MASK		0xff
+#define	WRSM_INTR_INDEX_SHIFT		0
+
+/* Values for the PSL when it is empty */
+
+/* Empty, but softint is active */
+#define	WRSM_INTR_PSL_EMPTY		(wrsm_intr_recvq_t *)2
+/* Empty and no softint running; can't cast, as used in wrsm_trap.s */
+#define	WRSM_INTR_PSL_IDLE		1
+
+
+#define	WRSM_MONDO2TABLE(m) \
+	(((m) >> WRSM_INTR_TABLE_SHIFT) & WRSM_INTR_TABLE_MASK)
+#define	WRSM_MONDO2INDEX(m) \
+	(((m) >> WRSM_INTR_INDEX_SHIFT) & WRSM_INTR_INDEX_MASK)
+
+/* Each table array contains pointers to WRSM_INTR_RECVQ_TABLES tables */
+#define	WRSM_INTR_RECVQ_TABLES_ARRAY_SIZE \
+	(WRSM_INTR_RECVQ_TABLES * sizeof (void *))
+
+#define	WRSM_INTR_PACKET_SIZE	64
+
+#ifndef _ASM
+
+/*
+ * Receive Queue structures
+ */
+typedef struct __rsm_send_q_handle wrsm_sendq_t;
+
+typedef uint64_t wrsm_intr_packet_t[WRSM_INTR_PACKET_SIZE/sizeof (uint64_t)];
+
+/* Describes an interrupt drainer (software interrupt thread) */
+typedef struct wrsm_intr_drainer {
+	uint_t drainer_inum;	/* Softint vector for drainer */
+	struct wrsm_intr_recvq *drainer_psl;
+	struct wrsm_intr_drainer *next; /* Next in circular list */
+} wrsm_intr_drainer_t;
+
+/* Describes an interrupt target CPU */
+typedef struct wrsm_intr_target {
+	processorid_t cpu_id;
+	struct wrsm_intr_recvq *recvq_list;
+	wrsm_intr_drainer_t *drainer;
+	uint32_t index;
+	int intr_dist_mondo;
+	struct wrsm_intr_target *next; /* Next in circular list */
+} wrsm_intr_target_t;
+
+/* An element in a linked-list of intr handlers, part of wrsm_intr_service */
+typedef struct wrsm_intr_handler {
+	rsm_intr_hand_t func;
+	rsm_intr_hand_arg_t arg;
+	rsm_controller_object_t *controller_obj;
+	cnode_bitmask_t cnodes;
+	struct wrsm_intr_handler *next;
+} wrsm_intr_handler_t;
+
+/* Describes an interrupt service, including list of handlers and a recvq */
+typedef struct wrsm_intr_service {
+	wrsm_network_t *net;
+	rsm_intr_t type;
+	wrsm_intr_handler_t *handler_list;
+	kmutex_t handler_mutex; /* Protects access to handler_list */
+	struct wrsm_intr_recvq *recvq_list;
+	kmutex_t recvq_mutex;   /* Protects access to recvq_list */
+} wrsm_intr_service_t;
+
+/* State of packet ring. Must be 64-bits for casx */
+typedef struct {
+	uint16_t lock;	/* If non-zero, trap is running */
+	uint16_t head;	/* Next available packet */
+	uint16_t tail;	/* Last consumed packet */
+	uint16_t size;	/* Size, in packets */
+} wrsm_intr_packet_ring_info_t;
+
+typedef union {
+	wrsm_intr_packet_ring_info_t info;
+	uint64_t val;
+} wrsm_intr_packet_ring_union_t;
+
+/* The receive queue structure */
+struct wrsm_intr_recvq {
+	wrsm_intr_packet_t *packet_ring; /* Pointer to packet ring */
+	wrsm_intr_packet_ring_union_t packet_ring_info;
+	uint32_t high_water_mark;    	/* If head-tail>hwm, set user_err */
+	uint32_t low_water_mark;	/* If head-tail<lwm, clear user_err */
+	caddr_t *sram_paddr;		/* Points to array of WCI sram addr */
+
+	boolean_t in_use;
+	boolean_t delete_me;
+
+	uint_t cmmu_mondo;
+	wrsm_cmmu_index_t cmmu_index;
+	cnodeid_t from_cnode;
+
+	wrsm_intr_drainer_t *drainer;	/* Drainer of this recvq */
+	wrsm_intr_target_t *target;	/* Target CPU of this recvq */
+	wrsm_intr_service_t *service;	/* Service for this recvq */
+
+	/* Pointers for various linked lists */
+	struct wrsm_intr_recvq *service_next;
+	struct wrsm_intr_recvq *target_next;
+	struct wrsm_intr_recvq *drainer_next;
+	struct wrsm_intr_recvq *recvq_next;
+
+	boolean_t user_interrupt;
+	void *exportseg;		/* info for small puts */
+	wrsm_cmmu_tuple_t *tuples;	/* used for remote recvq destroys */
+	kmutex_t mutex;
+
+	wrsm_network_t *net;
+	/* count of how often high-water mark has been reached */
+	uint64_t high_water_count;
+};
+
+/*
+ * Used to map a DMV argument (16-bits) to a recvq struct pointer. The
+ * The wrsm_interrupt_t structure contains an array of 256 pointers to
+ * recvq_table, which contains 256 recvq pointers. Use the macros
+ * MONDOARG2TABLE to get the table pointer from the wrsm_interrupt structure,
+ * the the macro MONDOARG2TABLEINDEX to index into the wrsm_intr_recvq_table
+ * to select the correct recvq pointer.
+ */
+typedef wrsm_intr_recvq_t *wrsm_intr_recvq_table_t[WRSM_INTR_RECVQ_TABLE_SIZE];
+
+/* The sendq structure */
+struct __rsm_send_q_handle {
+	wrsm_network_t *net;
+	caddr_t vaddr;
+	uint_t nc_slice;
+	off_t nc_off;
+	uint_t offset;
+	uint64_t qid;
+	uint_t mondo;
+	kmutex_t mutex;
+	cnodeid_t dest_cnode;
+	size_t qdepth;
+	rsm_intr_t service;
+	int flags;
+	boolean_t net_reset;
+	boolean_t fence_up;
+	wrsm_sendq_t *next;
+};
+
+/*
+ * Interrupt Structure part of wrsm_network_t
+ */
+struct wrsm_interrupt {
+	wrsm_intr_recvq_table_t *recvq_tables[WRSM_INTR_RECVQ_TABLES];
+	wrsm_intr_service_t services[WRSM_INTR_TYPE_MAX];
+	wrsm_intr_drainer_t *drainers;		/* Circular list of drainers */
+	wrsm_intr_target_t *targets;		/* Circular list of targets */
+	wrsm_intr_recvq_t *recvq_list[WRSM_MAX_CNODES];	/* List of recvqs */
+	wrsm_sendq_t *sendq_list[WRSM_MAX_CNODES]; /* List of sendq's */
+	kmutex_t mutex; /* Take before any other interrupt locks */
+	kcondvar_t resource_cv;
+	safari_port_t wci_safari_port; /* Sample WCI used for DMV inums */
+	/*
+	 * The following arrays is used for flow control. If the trap
+	 * handler detects a high water condition on a recvq, it must
+	 * set the user_error flag in that recvq's cmmu for all WCIs
+	 * (actually, it's sufficient to set the cmmu entry to valid
+	 * and user_error). To do that, it must know the address of
+	 * the sram. The array cmmu_paddr contains the physical address
+	 * of the CMMU entry in sram (or NULL) for every WCI in this
+	 * controller.
+	 */
+	caddr_t sram_paddr[WRSM_MAX_WCIS];
+	safari_port_t wci_ids[WRSM_MAX_WCIS];
+};
+
+/*
+ * Local Function Prototypes
+ */
+static void handler_init(wrsm_intr_handler_t *, rsm_intr_hand_t,
+    rsm_intr_hand_arg_t, cnode_bitmask_t, rsm_controller_object_t *);
+static void handler_fini(wrsm_intr_handler_t *);
+static rsm_intr_hand_ret_t handler_callback(wrsm_intr_handler_t *,
+    rsm_intr_q_op_t q_op, cnodeid_t, void *, size_t);
+
+static void service_init(wrsm_intr_service_t *, wrsm_network_t *, rsm_intr_t);
+static void service_fini(wrsm_intr_service_t *);
+static void service_add_recvq(wrsm_intr_service_t *, wrsm_intr_recvq_t *);
+static void service_rem_recvq(wrsm_intr_service_t *, wrsm_intr_recvq_t *);
+static void service_add_handler(wrsm_intr_service_t *, wrsm_intr_handler_t *);
+static wrsm_intr_handler_t *service_rem_handler(wrsm_intr_service_t *,
+    rsm_intr_hand_t, rsm_intr_hand_arg_t);
+static void service_callback(wrsm_intr_service_t *, void *, size_t, cnodeid_t);
+
+static void service_list_init(wrsm_interrupt_t *, wrsm_network_t *);
+static void service_list_fini(wrsm_interrupt_t *);
+
+static void target_init(wrsm_intr_target_t *, wrsm_intr_drainer_t *, uint32_t);
+static void target_fini(wrsm_intr_target_t *);
+static void target_readd_cpu(wrsm_network_t *, wrsm_intr_target_t *);
+static void target_retarget(wrsm_network_t *, wrsm_intr_target_t *);
+static void target_add_recvq(wrsm_intr_target_t *, wrsm_intr_recvq_t *);
+static void target_rem_recvq(wrsm_intr_target_t *, wrsm_intr_recvq_t *);
+static void target_print(wrsm_intr_target_t *);
+
+static void target_list_init(wrsm_interrupt_t *);
+static void target_list_fini(wrsm_interrupt_t *);
+static void target_list_readd_cpu(wrsm_network_t *net);
+static wrsm_intr_target_t *target_list_get_next(wrsm_interrupt_t *);
+static void target_list_print(wrsm_interrupt_t *);
+
+static int  drainer_init(wrsm_intr_drainer_t *);
+static void drainer_fini(wrsm_intr_drainer_t *);
+static uint_t drainer_handler(caddr_t arg);
+static void drainer_print(wrsm_intr_drainer_t *);
+
+static int  drainer_list_init(wrsm_interrupt_t *);
+static void drainer_list_fini(wrsm_interrupt_t *);
+static wrsm_intr_drainer_t *drainer_list_get_next(wrsm_interrupt_t *);
+static void drainer_list_print(wrsm_interrupt_t *);
+
+static void recvq_fini(wrsm_network_t *, wrsm_intr_recvq_t *);
+static size_t recvq_get_packet(wrsm_intr_recvq_t *, wrsm_intr_packet_t,
+    uint32_t *num_packets);
+static void recvq_callback(wrsm_intr_recvq_t *);
+static void recvq_print(wrsm_intr_recvq_t *);
+
+static void recvq_table_init(wrsm_interrupt_t *);
+static void recvq_table_fini(wrsm_interrupt_t *, wrsm_network_t *);
+static void recvq_table_alloc_table(wrsm_interrupt_t *, unsigned table);
+static int  recvq_table_alloc_entry(wrsm_interrupt_t *);
+static void recvq_table_free_entry(wrsm_interrupt_t *, int cmmu_mondo);
+static void recvq_table_set(wrsm_interrupt_t *, int pos, wrsm_intr_recvq_t *);
+static void recvq_table_print(wrsm_interrupt_t *);
+
+extern void wrsm_tl1_handler();
+
+
+#endif /* _ASM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WRSM_INTR_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_lc.h b/usr/src/uts/sun4u/sys/wrsm_lc.h
new file mode 100644
index 0000000000..5880f7e6a2
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_lc.h
@@ -0,0 +1,154 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _SYS_WRSM_LC_H
+#define	_SYS_WRSM_LC_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/types.h>
+#include <sys/wci_cmmu.h>
+#include <sys/wrsm.h>
+#include <sys/wrsm_driver.h>
+#include <sys/wrsm_config.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * function return values
+ */
+#define	WRSM_LC_SUCCESS		0
+#define	WRSM_LC_NOPAROLI	1
+#define	WRSM_LC_INVALIDARG	2
+
+typedef enum {
+	CMMU_TYPE_CACHEABLE = 0,
+	CMMU_TYPE_STICK = 1,
+	CMMU_TYPE_INTERRUPT = 2,
+	CMMU_TYPE_ATOMIC = 3
+} wrsm_cmmu_type_t;
+
+/* Declaration of abstract CMMU entry */
+typedef struct {
+	wci_sram_array_as_cmmu_0_u entry_0;
+	union {
+		struct wci_sram_array_as_cmmu_1_int intr;
+		struct wci_sram_array_as_cmmu_1_addr addr;
+		uint64_t val;
+	} entry_1;
+} wrsm_cmmu_t;
+
+#define	WRSM_GNID_IS_WCX(w)	(w >= WRSM_MAX_WNODES)
+
+/* cmmu_update flags */
+#define	CMMU_UPDATE_MONDO	0x00001
+#define	CMMU_UPDATE_FROMNODE	0x00002
+#define	CMMU_UPDATE_TYPE	0x00004
+#define	CMMU_UPDATE_VALID	0x00008
+#define	CMMU_UPDATE_FROMALL	0x00010
+#define	CMMU_UPDATE_WRITABLE	0x00020
+#define	CMMU_UPDATE_USERERROR	0x00040
+#define	CMMU_UPDATE_LARGEPAGE	0x00080
+#define	CMMU_UPDATE_ENABLEPERF	0x00100
+#define	CMMU_UPDATE_LPA		0x00200
+#define	CMMU_UPDATE_INTRDEST	0x00400
+#define	CMMU_UPDATE_FLUSH	0x08000
+#define	CMMU_UPDATE_ALL		0x0FFFF
+#define	CMMU_UPDATE_WRITEONLY	0x10000
+#define	CMMU_UPDATE_WRITE_0	0x20000
+#define	CMMU_UPDATE_WRITE_1	0x40000
+
+typedef uint32_t wrsm_cmmu_flags_t;
+
+int wrsm_lc_loopback_enable(wrsm_softstate_t *softsp,
+    uint32_t local_link_num);
+int wrsm_lc_loopback_disable(wrsm_softstate_t *softsp,
+    uint32_t local_link_num);
+int wrsm_lc_linktest(wrsm_softstate_t *softsp,
+    wrsm_linktest_arg_t *local_link_num);
+int wrsm_lc_user_linkdown(wrsm_softstate_t *softsp, int linkno);
+int wrsm_lc_user_linkup(wrsm_softstate_t *softsp, int linkno);
+
+void wrsm_lc_setup_timeout_speeds(void);
+safari_port_t wrsm_lc_get_safid(lcwci_handle_t lcwci);
+int wrsm_lc_get_instance(lcwci_handle_t lcwci);
+boolean_t wrsm_lc_verifyconfig(lcwci_handle_t lcwci, wrsm_wci_data_t *config);
+void wrsm_lc_replaceconfig(lcwci_handle_t lcwci, ncwci_handle_t nc,
+	wrsm_wci_data_t *config, wrsm_controller_t *ctlr_config);
+void wrsm_lc_cleanconfig(lcwci_handle_t lcwci);
+void wrsm_lc_installconfig(lcwci_handle_t lcwci);
+void wrsm_lc_enableconfig(lcwci_handle_t lcwci);
+
+/* for DDI_SUSPEND, DDI_RESUME */
+void wrsm_lc_suspend(wrsm_softstate_t *softsp);
+void wrsm_lc_resume(wrsm_softstate_t *softsp);
+
+/* register manipulation functions - read/write */
+void wrsm_lc_cesr_read(lcwci_handle_t lc, safari_port_t dev_id,
+    uint64_t *entry);
+void wrsm_lc_cesr_write(lcwci_handle_t lc, safari_port_t dev_id,
+    uint64_t entry);
+void wrsm_lc_csr_read(lcwci_handle_t lc, uint64_t reg_offset, uint64_t *entry);
+void wrsm_lc_csr_write(lcwci_handle_t lc, uint64_t reg_offset, uint64_t entry);
+
+void wrsm_lc_cmmu_read(lcwci_handle_t lc, wrsm_cmmu_t *cmmu_entry,
+    uint32_t index);
+void wrsm_lc_cmmu_update(lcwci_handle_t lc, wrsm_cmmu_t *cmmu_entry,
+    uint32_t index, wrsm_cmmu_flags_t flag);
+int wrsm_lc_num_cmmu_entries_get(lcwci_handle_t lc);
+
+void wrsm_lc_phys_link_up(safari_port_t local_port, uint32_t local_link_num,
+    fmnodeid_t remote_fmnodeid, gnid_t remote_gnid,
+    uint32_t remote_link_num, safari_port_t remote_port,
+    uint64_t remote_partition_version, uint32_t remote_partition_id);
+void wrsm_lc_phys_link_down(safari_port_t local_port, uint32_t local_link_num);
+void wrsm_lc_sc_crash(lcwci_handle_t lc);
+
+/* the following are supplied for the mh to modify the map registers */
+void wrsm_lc_set_route(wrsm_softstate_t *softsp, wnodeid_t wnode,
+    linkid_t linknum, int map);
+linkid_t wrsm_lc_get_route(wrsm_softstate_t *softsp, wnodeid_t wnode, int map);
+
+/* The following is for the interrupt trap handler only */
+caddr_t wrsm_lc_get_sram_paddr(lcwci_handle_t lc);
+
+/* the following is for standalone use, when system controller can't be used */
+void get_remote_config_data(safari_port_t wci_id, uint32_t link_num,
+    fmnodeid_t *remote_fmnodeid, gnid_t *remote_gnid, linkid_t *remote_link,
+    safari_port_t *remote_port, volatile uchar_t **wrsm_regs);
+
+/* the following handles ioctl requests to modify wci registers */
+int wrsm_lc_register_ioctl(wrsm_softstate_t *softsp, int cmd,
+    intptr_t arg, int flag, cred_t *cred_p, int *rval_p);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_WRSM_LC_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_memseg.h b/usr/src/uts/sun4u/sys/wrsm_memseg.h
new file mode 100644
index 0000000000..cee9c8bcd8
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_memseg.h
@@ -0,0 +1,158 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _WRSM_MEMSEG_H
+#define	_WRSM_MEMSEG_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * stuff exported by the RSMPI memseg module
+ */
+
+#include <sys/rsm/rsmpi.h>
+#include <sys/wrsm_transport.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+void wrsm_memseg_init(void);
+void wrsm_memseg_fini(void);
+void wrsm_memseg_network_init(wrsm_network_t *);
+void wrsm_memseg_network_fini(wrsm_network_t *);
+void wrsm_memseg_node_init(wrsm_node_t *);
+void wrsm_memseg_node_fini(wrsm_node_t *);
+void *wrsm_alloc(size_t, int);
+void wrsm_free(void *, size_t);
+
+int wrsmrsm_seg_create(rsm_controller_handle_t controller,
+    rsm_memseg_export_handle_t *memsegp,
+    size_t size, uint_t flags, rsm_memory_local_t *memory,
+    rsm_resource_callback_t callback,
+    rsm_resource_callback_arg_t callback_arg);
+
+int wrsmrsm_seg_destroy(rsm_memseg_export_handle_t handle);
+
+int wrsmrsm_bind(rsm_memseg_export_handle_t memseg,
+    off_t offset,
+    rsm_memory_local_t *memory,
+    rsm_resource_callback_t callback,
+    rsm_resource_callback_arg_t callback_arg);
+
+int wrsmrsm_unbind(rsm_memseg_export_handle_t memseg, off_t offset,
+    size_t length);
+
+int wrsmrsm_rebind(rsm_memseg_export_handle_t memseg, off_t offset,
+    rsm_memory_local_t *memory, rsm_resource_callback_t callback,
+    rsm_resource_callback_arg_t callback_arg);
+
+int wrsmrsm_publish(rsm_memseg_export_handle_t memseg,
+    rsm_access_entry_t access_list[],
+    uint_t access_list_length,
+    rsm_memseg_id_t segid,
+    rsm_resource_callback_t callback,
+    rsm_resource_callback_arg_t callback_arg);
+
+int wrsmrsm_unpublish(rsm_memseg_export_handle_t memseg);
+
+int wrsmrsm_republish(rsm_memseg_export_handle_t memseg,
+    rsm_access_entry_t access_list[], uint_t access_list_length,
+    rsm_resource_callback_t callback, rsm_resource_callback_arg_t callback_arg);
+
+int wrsmrsm_connect(rsm_controller_handle_t controller,
+    rsm_addr_t addr, rsm_memseg_id_t segid,
+    rsm_memseg_import_handle_t *im_memseg);
+
+int wrsmrsm_disconnect(rsm_memseg_import_handle_t im_memseg);
+
+int wrsmrsm_map(rsm_memseg_import_handle_t im_memseg, off_t offset,
+    size_t len, size_t *map_len, dev_info_t **dipp, uint_t *dev_register,
+    off_t *dev_offset, rsm_resource_callback_t callback,
+    rsm_resource_callback_arg_t arg);
+
+int wrsmrsm_unmap(rsm_memseg_import_handle_t im_memseg);
+
+int wrsmrsm_put(rsm_memseg_import_handle_t im_memseg, off_t offset,
+    void *datap, size_t length);
+int wrsmrsm_put8(rsm_memseg_import_handle_t im_memseg, off_t offset,
+    uint8_t *data, ulong_t rep_cnt, boolean_t byte_swap);
+int wrsmrsm_put16(rsm_memseg_import_handle_t im_memseg, off_t offset,
+    uint16_t *data, ulong_t rep_cnt, boolean_t byte_swap);
+int wrsmrsm_put32(rsm_memseg_import_handle_t im_memseg, off_t offset,
+    uint32_t *data, ulong_t rep_cnt, boolean_t byte_swap);
+int wrsmrsm_put64(rsm_memseg_import_handle_t im_memseg, off_t offset,
+    uint64_t *data, ulong_t rep_cnt, boolean_t byte_swap);
+
+int wrsmrsm_get(rsm_memseg_import_handle_t im_memseg, off_t offset,
+    void *datap, size_t length);
+int wrsmrsm_get8(rsm_memseg_import_handle_t im_memseg, off_t offset,
+    uint8_t *datap, ulong_t rep_cnt, boolean_t byte_swap);
+int wrsmrsm_get16(rsm_memseg_import_handle_t im_memseg, off_t offset,
+    uint16_t *datap, ulong_t rep_cnt, boolean_t byte_swap);
+int wrsmrsm_get32(rsm_memseg_import_handle_t im_memseg, off_t offset,
+    uint32_t *datap, ulong_t rep_cnt, boolean_t byte_swap);
+int wrsmrsm_get64(rsm_memseg_import_handle_t im_memseg, off_t offset,
+    uint64_t *datap, ulong_t rep_cnt, boolean_t byte_swap);
+
+
+void wrsm_free_exportsegs(wrsm_network_t *network);
+void wrsm_free_importsegs(wrsm_network_t *network);
+
+/* for controller kstat */
+typedef struct memseg_stat_data {
+	uint_t export_count;
+	uint_t import_count;
+	uint_t export_published;
+	uint_t export_connected;
+	uint_t bytes_bound;
+} wrsm_memseg_stat_data_t;
+
+void wrsm_memseg_stat(wrsm_network_t *network, wrsm_memseg_stat_data_t *data);
+
+typedef struct wrsm_memseg_evt_args {
+	wrsm_network_t *network;
+	wrsm_message_t msg;
+} wrsm_memseg_evt_args_t;
+
+/*
+ * event functions for delivering incoming remote messages asynchronously
+ */
+boolean_t wrsm_memseg_msg_hdlr(wrsm_network_t *network, wrsm_message_t *msg);
+void wrsm_connect_msg_evt(void *arg);
+void wrsm_smallputmap_msg_evt(void *arg);
+void wrsm_barriermap_msg_evt(void *arg);
+void wrsm_segmap_msg_evt(void *arg);
+void wrsm_disconnect_msg_evt(void *arg);
+void wrsm_unpublish_msg_evt(void *arg);
+void wrsm_access_msg_evt(void *arg);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _WRSM_MEMSEG_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_memseg_impl.h b/usr/src/uts/sun4u/sys/wrsm_memseg_impl.h
new file mode 100644
index 0000000000..65c926bc09
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_memseg_impl.h
@@ -0,0 +1,436 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2001-2003 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _WRSM_MEMSEG_IMPL_H
+#define	_WRSM_MEMSEG_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * this file is included by the RSM memory segment module
+ */
+
+#ifndef _ASM
+
+#include <sys/wrsm_common.h>
+#include <sys/wrsm_cmmu.h>
+#include <sys/wrsm_transport.h>
+#include <sys/wrsm_intr.h>
+
+#endif /* _ASM */
+
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+#define	WRSM_SMPUT_PACKETRING_SIZE	50
+
+#define	WRSM_LONG_SIZE		(sizeof (long))
+#define	WRSM_LONG_SHIFT		3
+#define	WRSM_LONG_MASK		(sizeof (long) - 1)
+
+
+#ifndef _ASM
+
+/*
+ * Hash for segid to iseginfo pointer mapping.
+ * Hash for segid to exportseg pointer mapping.
+ * Hash for segid to importset pointer mapping.
+ *
+ * Most likely the segid will be a low integer, so use lower bits
+ * of dev_t for hash index.
+ */
+#define	WRSM_SEGID_HASH_SIZE		0x100	/* # of entries in hash table */
+#define	WRSM_SEGID_HASH_SHIFT		0
+#define	WRSM_SEGID_HASH_MASK \
+	((WRSM_SEGID_HASH_SIZE - 1) << WRSM_SEGID_HASH_SHIFT)
+#define	WRSM_SEGID_HASH_FUNC(r) \
+	((((uint_t)r) & WRSM_SEGID_HASH_MASK) >> WRSM_SEGID_HASH_SHIFT)
+
+
+
+
+/*
+ * choose some middle bits of the pointer for the hash index
+ */
+#define	WRSM_PTR_HASH_SIZE		0x100	/* # of entries in hash table */
+#define	WRSM_PTR_HASH_SHIFT		7
+#define	WRSM_PTR_HASH_MASK \
+	((WRSM_PTR_HASH_SIZE - 1) << WRSM_PTR_HASH_SHIFT)
+#define	WRSM_PTR_HASH_FUNC(r) \
+	((((uint_t)r) & WRSM_PTR_HASH_MASK) >> WRSM_PTR_HASH_SHIFT)
+
+
+
+typedef struct __rsm_memseg_export_handle exportseg_t;
+typedef struct __rsm_memseg_import_handle importseg_t;
+typedef struct iseginfo iseginfo_t;
+
+
+/*
+ * list of cmmu entries, all one page size
+ */
+typedef struct cmmugrp {
+	off_t offset;			/* offset into segment */
+	off_t len;			/* length (bytes)  of region mapped */
+	size_t pgbytes;			/* size of page cmmu entry maps */
+	unsigned num_tuples;		/* number of cmmu tuples */
+	wrsm_cmmu_tuple_t *tuples;	/* array of cmmu tuples */
+	struct cmmugrp *next;
+} cmmugrp_t;
+
+
+typedef struct mseg_intr_page {
+	wrsm_cmmu_tuple_t *tuple;
+	wrsm_intr_recvq_t *recvq;
+} mseg_intr_page_t;
+
+
+typedef struct barrier_page {
+	wrsm_cmmu_tuple_t *tuple;
+	caddr_t vaddr;
+} barrier_page_t;
+
+
+typedef struct mseg_node_export {
+	boolean_t allow_import;		/* this node can access this seg? */
+	rsm_permission_t perms;		/* last set permissions for node */
+	rsm_permission_t actual_perms;	/* actual permissions for node */
+	boolean_t inuse;		/* is node connected to this seg? */
+
+	/*
+	 * if hardware access protection is used, need to set up
+	 * private cmmu entries for this node
+	 */
+	cmmugrp_t *hw_cmmugrps;	/* node private cmmu entries */
+	mseg_intr_page_t hw_small_put_intr; /* node private intr page */
+	barrier_page_t hw_barrier_page;	/* node private barrier page */
+} mseg_node_export_t;
+
+
+/* flags for cmmu_update_fields() function */
+typedef enum {
+	memseg_set_valid,
+	memseg_unset_valid,
+	memseg_set_writeable,
+	memseg_unset_writeable
+} memseg_cmmufield_t;
+
+#define	CMMU_UPDATE_STR(a)						\
+	(((a) == memseg_set_valid) ? "memseg_set_valid" :		\
+	((a) == memseg_unset_valid) ? "memseg_unset_valid" :		\
+	((a) == memseg_set_writeable) ? "memseg_set_writeable" :	\
+	((a) == memseg_unset_writeable) ? "memseg_unset_writeable" :	\
+	"unknown")
+
+
+typedef enum {
+	memseg_unpublished,			/* unpublished */
+	memseg_wait_for_disconnects,		/* unpublishing */
+	memseg_published			/* published */
+} exportseg_state_t;
+
+/*
+ * an exportseg structure is create for each segment created with
+ * rsm_create_seg().
+ */
+struct __rsm_memseg_export_handle {
+	kmutex_t lock;
+	boolean_t valid;		/* is exportseg being removed? */
+	wrsm_network_t *network;
+	exportseg_state_t state;	/* is segment published? */
+	rsm_memseg_id_t segid;		/* user assigned segment id */
+	size_t size;			/* length of segment */
+	int num_pages;			/* number of 8k pages in segment */
+	pfn_t *pfn_list;		/* 8k pfns backing the segment */
+	boolean_t allow_rebind;		/* unbind/rebind allowed? */
+	int total_tuples;		/* total number of cmmu tuples */
+	int num_cmmugrps;		/* # of cmmugrps */
+	cmmugrp_t *cmmugrps;		/* linked list of cmmugrps */
+	mseg_intr_page_t small_put_intr; /* CMMU/handler for small put intr */
+	barrier_page_t barrier_page;	/* page/CMMU for barriers */
+	mseg_node_export_t nodes[WRSM_MAX_CNODES]; /* per node info */
+	cnode_bitmask_t import_bitmask;	/* nodes with import permission */
+	uint_t wait_for_disconnects;	/* post-unpublish node cleanup count */
+	boolean_t writeable;		/* how to set generic CMMU entries */
+	exportseg_t *segid_next;	/* linked list for segid hash table */
+	exportseg_t *all_next;		/* all_exportsegs_hash pointer */
+};
+
+
+
+typedef struct import_ncslice {
+	off_t seg_offset;
+	ncslice_t ncslice;
+	off_t ncslice_offset;
+	size_t  len;
+} import_ncslice_t;
+
+
+
+/*
+ * each connection to a segment is represented with an importseg structure
+ */
+struct __rsm_memseg_import_handle {
+	krwlock_t rw_lock;		/* lock for put/get and disconnect */
+	boolean_t valid;		/* is importseg being removed? */
+	boolean_t unpublished;		/* is segment still published? */
+	iseginfo_t *iseginfo;		/* iseginfo for this segment */
+	wrsm_network_t *network;	/* local controller info */
+	boolean_t kernel_user;		/* is a kernel thread using put/get? */
+	rsm_barrier_mode_t barrier_mode; /* barrier mode for this connection */
+	boolean_t mappings;		/* user has mappings of segment */
+	void *barrier_page;		/* user as mapping of barrier page */
+	void *intr_page;		/* user as mapping of interrupt page */
+	void *cesr_page;		/* user as mapping of CESR regs */
+	void *reroute_page;		/* user as mapping of reroutecounters */
+	boolean_t have_mappings;	/* segment mapped into user vaddr */
+	rsm_resource_callback_t mapping_callback; /* callwhen segment invalid */
+	rsm_resource_callback_arg_t mapping_callback_arg; /* arg for callback */
+
+	importseg_t *iseg_next;		/* linked list off iseginfo */
+	importseg_t *all_next;		/* all_importsegs_hash pointer */
+};
+
+
+
+/*
+ * if a connection is requested by a kernel RSMPI client, the following
+ * mappings are automatically set up
+ */
+#define	MEMSEG_DEVLOAD_ATTRS	(HAT_NEVERSWAP | HAT_STRICTORDER)
+
+typedef struct mseg_kmap {
+	caddr_t seg;			/* hidden segment mapping */
+	caddr_t barrier_page;		/* kernel mapping of barrier page */
+	caddr_t small_put_intr;		/* kernel mapping of interrupt page */
+	caddr_t small_put_offset;	/* address for striped small puts */
+} mseg_kmap_t;
+
+
+typedef struct errorpage_t {
+	wrsm_cmmu_tuple_t *tuple;
+	pfn_t pfn;
+} wrsm_errorpage_t;
+
+
+/*
+ * An iseginfo structure is created the first time a segment is imported
+ * from a remote node through rsm_import_connect_memseg().  It is destroyed
+ * after the last disconnect, when a session is torn down, or when the
+ * remote node removes this node's access to the segment.
+ */
+struct iseginfo {
+	kmutex_t lock;
+	wrsm_network_t *network;	/* this iseginfo's network */
+	cnodeid_t cnodeid;		/* cnodeid of exporting node */
+	rsm_memseg_id_t segid;		/* segment id */
+	size_t size;			/* length of segment */
+	boolean_t unpublished;		/* node unpublished the segment */
+	boolean_t send_disconnect;	/* notify when disconnecting */
+	rsm_permission_t perms;		/* last set permissions for node */
+	uint_t num_seg_tuples;		/* # of tuples in seg_tuples */
+	import_ncslice_t *seg_tuples;	/* array of ncslice tuples for seg */
+	pfn_t *pfns;			/* array of pfns for kernel mapping */
+	import_ncslice_t barrier_tuple;	/* ncslice/offset for barrier page */
+	import_ncslice_t small_put_tuple; /* ncslice/offset for smallput intr */
+	mseg_kmap_t kernel_mapping;	/* kernel mapping info */
+	int kernel_users;		/* # kernel connections (imports) */
+	int errorpages;			/* reserved error pages */
+	wrsm_errorpage_t *errorpage_info; /* error pages for kernel mapping */
+	uint_t transfer_errors;		/* count of non-EIO errors on seg */
+	int last_transfer_error;	/* reason transfer_errors incremented */
+	importseg_t *importsegs;	/* connections to imported segment */
+	uint_t wait_for_unmaps;		/* number of outstanding client maps */
+	struct iseginfo *segid_next;	/* linked list for hash table */
+};
+
+
+
+
+/*
+ * local node's RSMPI memory segment information (in network structure)
+ */
+struct wrsm_memseg {
+	uint_t transfer_errors;		/* count of non-EIO errors */
+	int last_transfer_error;	/* reason transfer_errors incremented */
+	uint_t import_count;		/* # of importsegs for this network */
+	uint_t export_count;		/* # of exportsegs for this network */
+	uint_t export_published;	/* # of exportsegs published */
+	uint_t export_connected;	/* # of connections (one per node) */
+	uint_t bytes_bound;		/* total bound memory */
+	exportseg_t *exportseg_hash[WRSM_SEGID_HASH_SIZE];
+					/* published exportsegs */
+};
+
+
+kmutex_t	all_exportsegs_lock;
+kmutex_t	all_importsegs_lock;
+
+
+/*
+ * remote node info
+ */
+
+typedef struct connect_info {
+	exportseg_t *exportseg;
+	struct connect_info *next;
+} connect_info_t;
+
+
+struct wrsm_node_memseg {
+	kmutex_t lock;
+	boolean_t removing_session;	/* removing session to node */
+	connect_info_t *connected;	/* local segments node has imported */
+	iseginfo_t *iseginfo_hash[WRSM_SEGID_HASH_SIZE];
+					/* segments imported from node */
+	uint_t wait_for_unmaps;		/* importsegs with client maps */
+	uint_t transfer_errors;		/* count of non-EIO errors */
+	int last_transfer_error;	/* reason transfer_errors incremented */
+};
+
+
+
+/*
+ * messages
+ */
+
+typedef struct connect_msg {
+	rsm_memseg_id_t segid;
+} connect_msg_t;
+
+
+typedef struct connect_resp {
+	uint_t err;
+	rsm_permission_t perms;
+	size_t size;
+	uint_t num_seg_tuples;
+} connect_resp_t;
+
+
+typedef struct smallputmap_msg {
+	rsm_memseg_id_t segid;
+} smallputmap_msg_t;
+
+typedef struct smallputmap_resp {
+	uint_t err;
+	import_ncslice_t small_put_tuple;
+} smallputmap_resp_t;
+
+
+typedef struct barriermap_msg {
+	rsm_memseg_id_t segid;
+} barriermap_msg_t;
+
+typedef struct barriermap_resp {
+	uint_t err;
+	import_ncslice_t barrier_tuple;
+} barriermap_resp_t;
+
+
+typedef struct segmap_msg {
+	rsm_memseg_id_t segid;
+	uint_t tuple_index;
+} segmap_msg_t;
+
+#define	MAP_MSG_TUPLES	((WRSM_MESSAGE_BODY_SIZE - (2 * sizeof (uint_t))) \
+	/ sizeof (import_ncslice_t))
+
+typedef struct segmap_resp {
+	uint_t err;
+	uint_t num_tuples;
+	import_ncslice_t tuples[MAP_MSG_TUPLES];
+} segmap_resp_t;
+
+
+typedef struct disconnect_msg {
+	rsm_memseg_id_t segid;
+} disconnect_msg_t;
+
+typedef struct unpublish_msg {
+	rsm_memseg_id_t segid;
+} unpublish_msg_t;
+
+typedef struct unpublish_resp {
+	int status;
+} unpublish_resp_t;
+
+/* status values for unpublish_resp */
+#define	WC_DISCONNECTED	0x01
+#define	WC_CONNECTED	0x02
+
+
+typedef struct access_msg {
+	rsm_memseg_id_t segid;
+	rsm_permission_t perms;
+} access_msg_t;
+
+int wrsm_lock_importseg(importseg_t *importseg, krw_t rw);
+boolean_t iseginfo_sess_teardown(wrsm_node_t *node);
+int create_segment_mapping(iseginfo_t *iseginfo);
+
+boolean_t exportseg_sess_teardown(wrsm_node_t *node);
+
+/* Support for plugin library for RSMAPI */
+int
+wrsm_memseg_remote_node_to_iseginfo(uint32_t ctrl_num,
+    cnodeid_t remote_cnode, rsm_memseg_id_t segid, iseginfo_t **iseginfo);
+int wrsm_memseg_segmap(dev_t dev, off_t off, struct as *asp, caddr_t *addrp,
+    off_t len, unsigned int prot, unsigned int maxprot,
+    unsigned int flags, cred_t *cred);
+int wrsm_memseg_devmap(dev_t dev, devmap_cookie_t handle, offset_t off,
+    size_t len, size_t *maplen, uint_t model);
+int wrsm_smallput_plugin_ioctl(int minor, int cmd, intptr_t arg, int flag,
+    cred_t *cred_p, int *rval_p);
+
+typedef struct smallput_header {
+	uint32_t reserved;	/* reserved for DMV interrupt info */
+	uint8_t	len;		/* value ranges from 1 - 64 */
+	uint8_t	start;		/* start byte in putdata (to allow alignment) */
+	uint8_t sending_cnode;
+	uint8_t byte_filler;
+	off_t	offset;
+} smallput_header_t;
+
+#define	WRSM_SMALLPUT_BODY_SIZE (WRSM_TL_MSG_SIZE - \
+				sizeof (smallput_header_t))
+
+typedef struct wrsm_smallput_msg {
+	smallput_header_t header;
+	uint8_t putdata[WRSM_SMALLPUT_BODY_SIZE];
+} wrsm_smallput_msg_t;
+
+
+
+#endif /* _ASM */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _WRSM_MEMSEG_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_nc.h b/usr/src/uts/sun4u/sys/wrsm_nc.h
new file mode 100644
index 0000000000..033c735ff9
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_nc.h
@@ -0,0 +1,294 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _WRSM_NC_H
+#define	_WRSM_NC_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * this file is include by consumers of NC interfaces
+ */
+
+#include <sys/wrsm_config.h>
+#include <sys/wrsm_common.h>
+#include <sys/wrsm.h>
+#include <sys/wrsm_transport.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef struct wci_ids {
+	int port;		/* safari port id */
+	lcwci_handle_t lcwci;
+} wci_ids_t;
+
+
+/*
+ * wrsm_mh data structures
+ */
+
+typedef struct wrsm_mh_reachable {
+	int nhops[WRSM_MAX_WNODES];
+	int stripes[WRSM_MAX_WNODES];
+	boolean_t changed[WRSM_MAX_WNODES];
+	wnodeid_t first_hop[WRSM_MAX_WNODES];
+} wrsm_mh_reachable_t;
+
+
+/*
+ * The following data structures are to support for queueing events to the
+ * per controller NR event thread.
+ */
+
+typedef enum {
+	wrsm_evt_mhdirect,
+	wrsm_evt_mhreroute,
+	wrsm_evt_force_reroute,
+	wrsm_evt_add_passthrough,
+	wrsm_evt_send_ptlist,
+	wrsm_evt_recv_ptlist,
+	wrsm_evt_wakeup,
+	wrsm_evt_sessup,
+	wrsm_evt_sessdown,
+	wrsm_evt_connect,
+	wrsm_evt_smallputmap,
+	wrsm_evt_barriermap,
+	wrsm_evt_segmap,
+	wrsm_evt_disconnect,
+	wrsm_evt_unpublish,
+	wrsm_evt_access
+} wrsm_nr_event_type_t;
+
+#ifdef DEBUG
+#define	WRSM_EVTSTRING(e)					\
+	((e == wrsm_evt_mhdirect) ? "mhdirect" :		\
+	(e == wrsm_evt_mhreroute) ? "mhreroute" :		\
+	(e == wrsm_evt_force_reroute) ? "force_reroute" :	\
+	(e == wrsm_evt_add_passthrough) ? "add_passthrough" :	\
+	(e == wrsm_evt_send_ptlist) ? "send_ptlist" :		\
+	(e == wrsm_evt_recv_ptlist) ? "recv_ptlist" :		\
+	(e == wrsm_evt_sessup) ? "sessup" :			\
+	(e == wrsm_evt_sessdown) ? "sessdown" :			\
+	(e == wrsm_evt_connect) ? "connect" :			\
+	(e == wrsm_evt_smallputmap) ? "smallputmap" :		\
+	(e == wrsm_evt_barriermap) ? "barriermap" :		\
+	(e == wrsm_evt_segmap) ? "segmap" :			\
+	(e == wrsm_evt_disconnect) ? "disconnect" :		\
+	(e == wrsm_evt_unpublish) ? "unpublish" :		\
+	(e == wrsm_evt_access) ? "access" :		\
+	(e == wrsm_evt_wakeup) ? "wakeup" : "unknown")
+#endif
+
+
+typedef struct wrsm_evt_mhevent {
+	ncwci_handle_t wci;
+	wrsm_mh_reachable_t mh_reachable;
+} wrsm_evt_mhevent_t;
+
+typedef struct wrsm_evt_forcereroute {
+	ncwci_handle_t wci;
+} wrsm_evt_forcereroute_t;
+
+typedef struct wrsm_evt_addpt {
+	wrsm_node_t *node;
+} wrsm_evt_addpt_t;
+
+typedef struct wrsm_evt_send_ptlist {
+	cnode_bitmask_t list;		/* cnodes to send pt_counter msg to */
+} wrsm_evt_send_ptlist_t;
+
+typedef struct wrsm_evt_recv_ptlist {
+	cnodeid_t cnodeid;
+	cnode_bitmask_t pt_provided;	/* cnodes allowed PT forwarding */
+	int pt_route_counter;		/* incr when pt_provided changes */
+} wrsm_evt_recv_ptlist_t;
+
+typedef struct wrsm_evt_sess {
+	cnodeid_t cnodeid;
+} wrsm_evt_sess_t;
+
+typedef struct wrsm_nr_event {
+	wrsm_nr_event_type_t type;
+	union {
+		wrsm_evt_mhevent_t mhevent;
+		wrsm_evt_forcereroute_t forcereroute;
+		wrsm_evt_addpt_t addpt;
+		wrsm_evt_send_ptlist_t send_ptlist;
+		wrsm_evt_recv_ptlist_t recv_ptlist;
+		wrsm_evt_sess_t sess;
+		wrsm_message_t msg;
+	} data;
+	struct wrsm_nr_event *next;
+} wrsm_nr_event_t;
+
+void wrsm_nr_add_event(wrsm_network_t *network, wrsm_nr_event_t *event_data,
+    boolean_t release_lock);
+
+
+
+/*
+ * the following functions are used by the Config Layer
+ */
+
+/*
+ * find network structure from controller id or dev_info_t pointer
+ */
+wrsm_network_t *wrsm_nc_ctlr_to_network(uint32_t rsm_ctrl_id);
+wrsm_network_t *wrsm_nc_cnodeid_to_network(cnodeid_t);
+
+/*
+ * save away new config info; disable current config
+ */
+int wrsm_nc_replaceconfig(uint32_t rsm_ctlr_id,
+    wrsm_controller_t *config, dev_info_t *dip, int num_attached,
+    wci_ids_t *attached_wcis);
+
+/*
+ * clean up/stop using old nodes, wcis, links
+ */
+int wrsm_nc_cleanconfig(uint32_t rsm_ctlr_id, int num_reconfig,
+    wci_ids_t *reconfig_wcis);
+
+/*
+ * make sure all old links are down; bring up new links
+ */
+int wrsm_nc_installconfig(uint32_t rsm_ctlr_id);
+
+/*
+ * start using new links
+ */
+int wrsm_nc_enableconfig(uint32_t rsm_ctlr_id, int num_reconfig,
+    wci_ids_t *reconfig_wcis);
+
+/*
+ * check whether config is in installed_up state
+ */
+boolean_t wrsm_nc_is_installed_up(uint_t rsm_ctlr_id);
+
+
+/*
+ * install and enable new config
+ */
+int wrsm_nc_initialconfig(uint32_t rsm_ctlr_id,
+    wrsm_controller_t *config, dev_info_t *dip, int num_attached,
+    wci_ids_t *attached_wcis);
+
+/*
+ * uninstall config for an RSM controller; delete RSM controller
+ */
+int wrsm_nc_removeconfig(uint32_t rsm_ctlr_id);
+
+/*
+ * enable sessions in RSM controller
+ */
+int wrsm_nc_startconfig(uint32_t rsm_ctlr_id);
+
+/*
+ * enable sessions in RSM controller
+ */
+int wrsm_nc_stopconfig(uint32_t rsm_ctlr_id);
+
+/*
+ * notify the NR that all links on a WCI are up
+ */
+void wrsm_nr_all_links_up(ncwci_handle_t nc);
+
+/*
+ * find out if node connected to a link has a valid session
+ */
+int wrsm_nr_session_up(ncwci_handle_t ncwci, wnodeid_t wnid);
+
+/*
+ * clear cluster write lockout on a remote cnode
+ */
+void wrsm_nr_clear_lockout(ncwci_handle_t wci, ncslice_t ncslice);
+
+/*
+ * a new WCI has been attached
+ */
+int wrsm_nc_newwci(uint32_t rsm_ctlr_id, safari_port_t safid,
+    lcwci_handle_t lcwci, wrsm_controller_t *config);
+
+/*
+ * an attached wci is being detached
+ */
+int wrsm_nc_removewci(uint32_t rsm_ctlr_id, safari_port_t safid);
+
+/*
+ * the following functions are used by memory segments
+ */
+int wrsm_nc_create_errorpage(wrsm_network_t *network,
+    wrsm_cmmu_tuple_t **errorpage_tuplep, pfn_t *errorpage_pfnp,
+    boolean_t sleep);
+
+
+/*
+ * the following functions are used by the LC
+ */
+void wrsm_mh_link_is_up(ncwci_handle_t ncwci, uint32_t
+    local_linknum, wnodeid_t remote_wnode);
+void wrsm_mh_link_is_down(ncwci_handle_t ncwci, uint32_t
+    local_linknum, wnodeid_t remote_wnode);
+
+/*
+ * the following functions are used by the driver
+ */
+
+int wrsm_nc_suspend(uint_t rsm_ctlr_id);
+int wrsm_nc_resume(uint_t rsm_ctlr_id);
+
+
+/* this is an RSMPI function */
+int wrsm_get_peers(rsm_controller_handle_t controller, rsm_addr_t *addr_list,
+    uint_t count, uint_t *num_addrs);
+
+/*
+ * returns controller number given nc handle. Used by lc since the lc
+ * cannot dereference the config fields in softstate as they may be null
+ */
+uint32_t wrsm_nr_getcontroller_id(ncwci_handle_t ncwci);
+/*
+ * The plugin library (librsmwrsm) opens controllers, in order to prevent the
+ * the config layer from removing a controller (network) that the plugin is
+ * using, the driver must return busy. open and close controller below
+ * increment/decrement a counter for the removeconfig to check before removing
+ * a config.
+ */
+int wrsm_nc_open_controller(uint_t rsm_ctlr_id);
+void wrsm_nc_close_controller(uint_t rsm_ctlr_id);
+int wrsm_nc_getlocalnode_ioctl(int minor, int cmd, intptr_t arg, int flag,
+    cred_t *cred_p, int *rval_p);
+
+/* logs system events for use by user applications via the sysdaemond to see */
+void wrsm_nr_logevent(wrsm_network_t *network, wrsm_node_t *node,
+    wrsm_sys_event_t eventtype, char *reason);
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _WRSM_NC_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_nc_impl.h b/usr/src/uts/sun4u/sys/wrsm_nc_impl.h
new file mode 100644
index 0000000000..638873e153
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_nc_impl.h
@@ -0,0 +1,333 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _WRSM_NC_IMPL_H
+#define	_WRSM_NC_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * this file is included by modules that are part of the NC
+ */
+
+#include <sys/wrsm_common.h>
+#include <sys/wrsm_config.h>
+#include <sys/wrsm_plat.h>
+
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	WRSM_PTRETRY_TIMEOUT	(10 * hz)
+#define	WRSM_ENABLE_TIMEOUT	(5 * hz)
+
+#define	WRSM_INID2DNID_ENTRIES	16
+#define	WRSM_MAX_STRIPEWCIS	4
+#define	WNODE_UNREACHABLE	(-1)
+
+typedef unsigned char wrsm_linknum_t;
+typedef unsigned char inid_t;
+
+typedef struct wrsm_mh_reroute_state wrsm_mh_reroute_state_t;
+typedef struct wrsm_nc_strgrp wrsm_nc_strgrp_t;
+
+
+
+
+/*
+ * arg to wci_routechange()
+ *
+ * controls how the gain or loss of a wnode route affects which
+ * nodes have their ncslice routes re-evaluated.
+ */
+typedef enum {
+	wci_reroute_all,	/* route eval on all interested nodes */
+	wci_reroute_direct,	/* route eval only on direct connect nodes */
+	wci_reroute_pending,	/* only route eval nodes using lost routes */
+	wci_reroute_disabled,	/* teardown routes on nodes using lost routes */
+	wci_reroute_force	/* reroute_all, changed and unchanged wnodes */
+} wrsm_wci_reroute_t;
+
+#ifdef DEBUG
+#define	WCI_RTSTRING(e)							\
+	((e == wci_reroute_all) ? "reroute_all" :			\
+	(e == wci_reroute_direct) ? "reroute_direct" :			\
+	(e == wci_reroute_pending) ? "reroute_pending" :		\
+	(e == wci_reroute_disabled) ? "reroute_disabled" :		\
+	(e == wci_reroute_force) ? "reroute_force" :	"unknown")
+#endif
+
+
+typedef enum {
+	wci_rerouted,			/* no multi-hop reroute needed */
+	wci_in_reroute,			/* MH currently recalculating routes */
+	wci_need_reroute,		/* wci needs an MH reroute */
+	wci_force_reroute		/* force an MH reroute */
+} wrsm_wci_state_t;
+
+
+typedef struct wrsm_inid2dnid_entry {
+	int stripes;			/* 0 - unique wnodes: 1, 2, 3, or 4 */
+	boolean_t changed;		/* different than the installed entry */
+	wnode_bitmask_t wnode_bitmask;	/* wnodes this inid uses */
+	wnodeid_t  wnode_list[WRSM_MAX_DNIDS]; /* wnodes this inid uses */
+	cnode_bitmask_t cnode_routes;	/* cnodes this inid routes to */
+	cnode_bitmask_t users;		/* cnodes using this route */
+	cnode_bitmask_t reserved;	/* cnodes that plan to use this route */
+} wrsm_inid2dnid_entry_t;
+
+typedef struct wrsm_wnodeinfo {
+	boolean_t valid;		/* valid wnode in this configuration */
+	cnodeid_t cnodeid;		/* cnode this wnode routes to */
+	cnode_bitmask_t interested;	/* cnodes that could use this route */
+	cnode_bitmask_t users;		/* cnodes using this route */
+	cnode_bitmask_t reserved;	/* cnodes that plan to use this route */
+} wrsm_wnodeinfo_t;
+
+
+/*
+ * wci related information private to the NR
+ */
+typedef struct nrwci {
+	wrsm_mh_reachable_t mh_reachable; /* wnode reachability */
+	wrsm_wnodeinfo_t wnodeinfo[WRSM_MAX_WNODES]; /* wrsm_node, users */
+	wrsm_inid2dnid_entry_t inid2dnid[WRSM_INID2DNID_ENTRIES];
+					/* inid2dnid table settings */
+	boolean_t using_inids;		/* current/new routes use inids */
+	boolean_t reserved_inids;	/* reserved inids for 1-wnode routes */
+	boolean_t inids_enabled;	/* inids enabled in the hardware */
+	boolean_t need_hw_update;	/* # inids changed since HW write */
+	wrsm_nc_strgrp_t *sg;		/* stripe group wci is in */
+	cnode_bitmask_t cnode_retry;	/* cnodes should retry using this wci */
+} nr_wci_t;
+
+
+typedef struct wrsm_ncwci {
+	wrsm_network_t *network;	/* RSM controller this belongs to */
+	lcwci_handle_t lcwci;		/* LC's handle for this wci */
+	wrsm_availability_t availability; /* configuration state */
+	wrsm_wci_state_t reroute_state;	/* multi-hop rereroute needed? */
+	wrsm_wci_data_t *config;	/* configuration data for wci links */
+	nr_wci_t nr;				/* NR state */
+	wrsm_mh_reroute_state_t *mh_state; 	/* MH state */
+	boolean_t linksup;		/* used during install/enable */
+	struct wrsm_ncwci *next;	/* next wci in controller */
+} wrsm_ncwci_t;
+
+
+struct wrsm_nc_strgrp {
+	wrsm_network_t *network;	/* RSM controller this belongs to */
+	wrsm_stripe_group_t *config;	/* config info */
+	wrsm_availability_t availability; /* configuration state */
+	int attached_wcis;		/* attached wcis in stripe group */
+	boolean_t striping_on;		/* are wcis programmed to stripe? */
+	wrsm_ncwci_t *wcis[WRSM_MAX_STRIPEWCIS]; /* wcis in stripe order */
+	ncslice_bitmask_t wci_ncslices[WRSM_MAX_STRIPEWCIS];
+					/* ncslices forced onto single wci */
+	cnode_bitmask_t users;		/* cnodes using this stripe group */
+	cnode_bitmask_t cnode_retry;	/* cnodes should try using this sg */
+	struct wrsm_nc_strgrp *next;	/* next stripe group in ctlr */
+};
+
+
+typedef struct inidwnode_route {
+	wrsm_ncwci_t *wci;
+	enum {
+		nid_route_inid,
+		nid_route_wnode
+	} route_type;
+	wnodeid_t id;	/* inids and wnids are the same size */
+} inidwnode_route_t;
+
+
+typedef struct ncslice_route {
+	wrsm_preferred_route_t *proute;	/* preferred route used */
+	wrsm_nc_strgrp_t *sg;
+	/*
+	 * total # links used in ncslice route; combined striping provided
+	 * by route map striping, inid2dnid striping, and wci striping
+	 */
+	int stripes;
+	int nwcis;		/* number of wcis used */
+	cnode_bitmask_t switches;	/* switches used by this route */
+	/*
+	 * the actual inid/wnode routes used; one per wci
+	 */
+	inidwnode_route_t wroutes[WRSM_MAX_STRIPEWCIS];
+	boolean_t nostripe;	/* is wci striping disabled on this route? */
+} ncslice_route_t;
+
+/*
+ * This state is used by ncslice_apply_routes to update ncslice routes for
+ * each node.
+ */
+typedef enum {
+	ncslice_use_current,		/* current route is still ok */
+	ncslice_use_new_route,		/* use a new route */
+	ncslice_remove_route,		/* remove route (to remove node) */
+	ncslice_use_errloopback,	/* use errloopack route */
+	ncslice_no_route		/* route has been removed */
+} reroute_type_t;
+
+#ifdef DEBUG
+#define	ROUTEINFO_MSGSTRING(e)					\
+	((e == ncslice_use_current) ? "use_current" :		\
+	(e == ncslice_use_new_route) ? "use_new_route" :	\
+	(e == ncslice_remove_route) ? "remove_route" :		\
+	(e == ncslice_use_errloopback) ? "use_errloopback" :\
+	(e == ncslice_no_route) ? "no_route" :	"unknown")
+#endif
+
+struct wrsm_node_routeinfo {
+	wrsm_routing_policy_t *policy;	/* routing config policy */
+	boolean_t check_route;		/* route needs to be checked */
+	reroute_type_t route_state;	/* what routing should be applied? */
+	ncslice_route_t current_route;	/* installed route */
+	ncslice_route_t new_route;	/* newly chosen route */
+	boolean_t direct_connect;	/* using a direct connect route */
+	cnode_bitmask_t pt_provided;	/* cnodes allowed PT forwarding */
+	int pt_route_counter;		/* incr when pt_provided changes */
+	int pt_rerouting;		/* remote node is rerouting */
+	cnode_bitmask_t pt_interested;	/* cnodes could use this PT route */
+	cnode_bitmask_t pt_users;	/* cnodes using this PT route */
+	wrsm_preferred_route_t *extended_routes; /* wci loopback routes */
+	wrsm_preferred_route_t **orig_routes; /* policy supplied routes */
+	int orig_nroutes;		/* count of policy supplied routes */
+	uint32_t num_rte_changes;	/* count of route changes */
+	kstat_t *wrsm_route_ksp;	/* pointer to route kstat */
+};
+
+
+typedef enum {
+	pt_route_counter,
+	pt_reroute_start,
+	pt_reroute_finish
+} pt_msgtype_t;
+
+typedef struct wrsm_ptlist_msg {
+	cnode_bitmask_t pt_provided;	/* cnodes allowed PT forwarding */
+	int pt_route_counter;		/* incr when pt_provided changes */
+	pt_msgtype_t pt_msgtype;	/* routechange, or rerouting? */
+} wrsm_ptlist_msg_t;
+
+#ifdef DEBUG
+#define	PT_MSGSTRING(e)						\
+	((e == pt_route_counter) ? "route_counter" :		\
+	(e == pt_reroute_start) ? "reroute_start" :		\
+	(e == pt_reroute_finish) ? "reroute_finish" :	"unknown")
+#endif
+
+
+/*
+ * wcis and stripe groups are linked lists. wci list is ordered by
+ * (safari) port, and stripe group list is ordered by stripe group id
+ */
+struct wrsm_nr {
+	kmutex_t lock;
+	wrsm_ncwci_t *wcis;		/* pointers to wcis */
+	krwlock_t wcilist_rw;		/* protects wcis linked list */
+	wrsm_nc_strgrp_t *sgs;		/* pointer to stripe groups */
+	cnode_bitmask_t pt_provided;	/* passthru to these nodes is on */
+	cnode_bitmask_t pt_retrylist;	/* need to send pt message to these */
+	timeout_id_t pt_retry_timeout_id; /* timeout to resend pt messages */
+	boolean_t need_pt_retry_timeout; /* resched timeout after suspend */
+	int pt_route_counter;		/* incr when pt_provided changes */
+	boolean_t init_cmmu;		/* cmmu init needed on new config */
+	kthread_t *event_thread;
+	kcondvar_t event_cv;		/* cv for event thread */
+	boolean_t stop_event_thr;	/* flag telling event thread to exit */
+	uint64_t event_thr_loopcnt;	/* number of time evt thr has looped */
+	wrsm_nr_event_t *events;	/* events to be processed */
+	wrsm_nr_event_t *last_event;	/* last event on queue */
+	boolean_t wait_wcis_rerouting;	/* waiting for wci reroutes */
+	boolean_t wait_eventdrain;	/* waiting for event drain */
+	uint_t wait_pause;		/* waiting for evt thr to pause */
+	boolean_t pausing;		/* evt thread is paused */
+	kcondvar_t config_cv;		/* cv for config related events */
+	timeout_id_t wcireroute_timeout_id; /* wci reroute timeout */
+	boolean_t need_wcireroute_timeout; /* resched timeout after suspend */
+	int waiting_linksup;		/* # wcis whose links aren't all up */
+	int suspended;			/* controller is suspended */
+	wrsm_ncowner_map_t ncslice_responder[WRSM_MAX_NCSLICES];
+					/*
+					 * which wci/stripe group responds
+					 * to this ncslice
+					 */
+};
+
+/*
+ * counting wcis for kstats
+ */
+void wrsm_get_wci_num(wrsm_network_t *network, uint_t *num_wcis,
+	uint_t *avail_wcis);
+
+/*
+ * register control interfaces
+ */
+void wrsm_nc_config_linksup(void *arg);
+
+/*
+ * NR interfaces
+ */
+int wrsm_nr_verifyconfig(wrsm_network_t *network, wrsm_controller_t *config,
+    int attached_cnt, wci_ids_t *attached_wcis);
+boolean_t wrsm_nr_initialconfig(wrsm_network_t *network, int attached_cnt,
+    wci_ids_t *attached_wcis);
+int wrsm_nr_replaceconfig(wrsm_network_t *network, wrsm_controller_t *config,
+    int num_wcis, wci_ids_t *attached_wcis);
+int wrsm_nr_cleanconfig(wrsm_network_t *network, int num_wcis,
+    wci_ids_t *reroute_wcis);
+int wrsm_nr_installconfig(wrsm_network_t *network);
+int wrsm_nr_enableconfig(wrsm_network_t *network, int num_wcis,
+    wci_ids_t *reroute_wcis);
+void wrsm_nr_removeconfig(wrsm_network_t *network);
+int wrsm_nr_attachwci(wrsm_network_t *network, safari_port_t saf_id,
+    lcwci_handle_t lcwci, wrsm_controller_t *config, boolean_t init_cmmu,
+    boolean_t pause_evt_thread);
+int wrsm_nr_enablewci(wrsm_network_t *network, safari_port_t saf_id,
+    boolean_t dr_attach);
+int wrsm_nr_detachwci(wrsm_network_t *network, safari_port_t saf_id,
+    boolean_t force);
+void wrsm_nr_mhdirect(wrsm_ncwci_t *wci, wrsm_mh_reachable_t *reachable);
+void wrsm_nr_mhreroute(wrsm_ncwci_t *wci, wrsm_mh_reachable_t *reachable);
+int wrsm_nr_suspend(wrsm_network_t *network);
+int wrsm_nr_resume(wrsm_network_t *network);
+
+/*
+ * MH interfaces
+ */
+void wrsm_mh_new_wci(wrsm_ncwci_t *wci);
+void wrsm_mh_remove_wci(wrsm_ncwci_t *wci);
+boolean_t wrsm_mh_reroute(wrsm_ncwci_t *wci);
+int wrsm_mh_wnode_to_link(ncwci_handle_t ncwci, int wnodeid);
+boolean_t wrsm_mh_link_to_wnode(ncwci_handle_t ncwci, int link, int wnodeid);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _WRSM_NC_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_plat.h b/usr/src/uts/sun4u/sys/wrsm_plat.h
new file mode 100644
index 0000000000..d24192867e
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_plat.h
@@ -0,0 +1,160 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2001-2003 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _WRSM_PLAT_H
+#define	_WRSM_PLAT_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * WildCat RSM driver platform-specific module interface
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <sys/wrsm.h>
+#include <sys/wrsm_types.h>
+#include <sys/wrsm_common.h>
+
+/* Possible per-link LED states */
+#define	LEDBOTHOFF	0
+#define	LEDLOWERON	1
+#define	LEDUPPERON	2
+#define	LEDBOTHON	3
+
+/* Possible values for link_state */
+#define	LINK_STATE_OFF		0
+#define	LINK_STATE_SEEK		2
+#define	LINK_STATE_IN_USE	3
+#define	LINK_STATE_NO_CHANGE	4
+
+#define	END_STATUS_NOT_READY	0
+#define	END_STATUS_NEAR_READY	1
+#define	END_STATUS_ALL_READY	3
+
+/*
+ * remote wnode argument to _uplink and _downlink to indicate link
+ * should be in loopback mode
+ */
+#define	LOOPBACK_WNODE	WRSM_MAX_WNODES+1
+
+/* I have no idea how big this should actually be */
+#define	WIB_SEPROM_MSG_SIZE 64
+
+/* Typedefs for ncslice programming */
+typedef enum {
+	WRSM_NCOWNER_NOT_CLAIMED = 0,
+	WRSM_NCOWNER_NONE = 1,
+	WRSM_NCOWNER_WCI = 2,
+	WRSM_NCOWNER_STRIPEGROUP = 3
+} wrsm_ncowner_t;
+
+typedef enum {
+	wrsm_node_serengeti,
+	wrsm_node_wssm,
+	wrsm_node_starcat
+} wrsm_node_types_t;
+
+typedef union {
+	safari_port_t wci_id;
+	wrsm_stripe_group_t *stripe_group;
+} wrsm_ncowner_id_t;
+
+typedef struct {
+	wrsm_ncowner_t owner_type;
+	wrsm_ncowner_id_t owner;
+} wrsm_ncowner_map_t;
+
+typedef struct wrsm_plat_ops {
+	void (*link_up)(safari_port_t wci_id, uint32_t link_num,
+	    fmnodeid_t remote_fmnodeid, gnid_t remote_gnid,
+	    uint32_t remote_link_num, safari_port_t remote_port,
+	    uint64_t remote_partition_version, uint32_t remote_partition_id);
+
+	void (*link_down)(safari_port_t wci_id, uint32_t local_link_num);
+	void (*sc_failed)();
+
+	/* The following callbacks are for testing purposes only */
+	struct wrsm_soft_state *(*get_softstate)(safari_port_t
+	    wci_id);
+	void (*get_remote_data)(safari_port_t wci_id,
+	    uint32_t link_num, fmnodeid_t *remote_fmnodeid,
+	    gnid_t *remote_gnid, linkid_t *remote_link,
+	    safari_port_t *remote_port, volatile uchar_t **wrsm_regs);
+} wrsm_plat_ops_t;
+
+/* Format of data for wrsmplat_set_seprom data */
+typedef struct wrsm_wib_ecc_error {
+	uint32_t ce : 1;
+	uint32_t syndrome : 7;
+	uint32_t address : 24;
+} wrsm_wib_ecc_error_t;
+
+#define	WRSM_WIB_SEPROM_TYPE_ECCERR	1
+
+typedef struct wrsm_seprom_data {
+	uint32_t type;
+	union {
+		wrsm_wib_ecc_error_t eccerr;
+	} data;
+
+} wrsm_seprom_data_t;
+
+int wrsmplat_reg_callbacks(wrsm_plat_ops_t *ops);
+int wrsmplat_unreg_callbacks(void);
+void wrsmplat_suspend(safari_port_t wci);
+void wrsmplat_resume(safari_port_t wci);
+
+int wrsmplat_uplink(safari_port_t wci, linkid_t link, gnid_t gnid,
+    fmnodeid_t fmnodeid, uint64_t partition_version, uint32_t controller_id,
+    boolean_t loopback);
+int wrsmplat_downlink(safari_port_t wci, linkid_t link, boolean_t loopback);
+int wrsmplat_set_led(safari_port_t wci, linkid_t link, int led_state);
+int wrsmplat_alloc_slices(ncslice_bitmask_t requested,
+    ncslice_bitmask_t *granted);
+int wrsmplat_set_seprom(safari_port_t wci, uchar_t *seprom_data, size_t
+    length);
+int wrsmplat_linktest(safari_port_t wci, wrsm_linktest_arg_t *linktest);
+
+int wrsmplat_stripegroup_verify(const wrsm_stripe_group_t *);
+void wrsmplat_ncslice_setup(wrsm_ncowner_map_t owner[WRSM_MAX_NCSLICES]);
+void wrsmplat_ncslice_enter(void);
+void wrsmplat_ncslice_exit(void);
+
+void wrsmplat_xt_sync(int cpu_id);
+wrsm_node_types_t wrsmplat_get_node_type(void);
+void wrsmplat_wci_init(volatile uchar_t *wrsm_regs);
+
+void wrsmplat_set_asi_cesr_id(void);
+void wrsmplat_clr_asi_cesr_id(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WRSM_PLAT_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_plat_impl.h b/usr/src/uts/sun4u/sys/wrsm_plat_impl.h
new file mode 100644
index 0000000000..7ba23094f6
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_plat_impl.h
@@ -0,0 +1,141 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _WRSM_PLAT_IMPL_H
+#define	_WRSM_PLAT_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/*
+ * Private definitions for the wrsm_plat module
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <sys/wrsm_plat.h>
+
+/* LC to SC message types */
+/* (message codes defined in firmware - do not change) */
+
+#define	UPLINK		0x3000	/* Request that a link be brought up */
+#define	DOWNLINK 	0x3001	/* Request that a link be brought down */
+#define	LINKDATA	0x3002	/* Get discovery data for specified link */
+#define	NCSLICE		0x3003 	/* Request allocation of NC slices */
+#define	SETLEDSTATE	0x3004 	/* Set the LED to specified state */
+#define	SETSEPROM	0x3005 	/* Set SEPROM with error message */
+
+/* Asynchronous SC to LC message types */
+#define	LINKISUP	0x000e	/* Link has come up */
+
+/*
+ * During UPLINK request LC fills this in with local data.  During
+ * LINKDATA request, SC fills this in with data from the remote node.
+ */
+typedef struct wrsm_uplink_data {
+	uint64_t partition_version;
+	uint32_t partition_id;
+	uint32_t fmnodeid;
+	uint32_t gnid;
+} wrsm_uplink_data_t;
+/*
+ * In the comments below, a request is any message from the kernel to
+ * the SC and a response is any message from the SC to the kernel.
+ */
+
+/* Message body for UPLINK and LINKDATA request/response  */
+typedef struct wrsm_uplink_msg {
+	wrsm_uplink_data_t config_data;
+	uint32_t wci_port_id;
+	uint32_t link_num;
+	uint32_t status;
+} wrsm_uplink_msg_t;
+
+/*
+ * A synchronous response message from the SC acknowledging a message.  The
+ * format of the message body is defined by the wrsm_status_msg_t structure.
+ * A status of 0 indicates the SC was able to process the message as expected.
+ * NOTE: not used on a serengeti platform, errors are reported using the
+ * provided mechanism of returing an error code from the mailbox function call
+ */
+typedef struct wrsm_status_msg {
+	uint32_t status;
+} wrsm_status_msg_t;
+
+/*
+ * Message body used for DOWNLINK request
+ */
+typedef struct wrsm_link_msg {
+	uint32_t wci_port_id;
+	uint32_t link_num;
+} wrsm_link_msg_t;
+
+/* Message body used for NCSLICE request/response */
+typedef struct wrsm_ncslice_claim_msg {
+	uint32_t status;
+	ncslice_bitmask_t requested_ncslices;
+} wrsm_ncslice_claim_msg_t;
+
+/* Message body used for SETLEDSTATE request/response */
+typedef struct wrsm_link_led_msg {
+	uint32_t wci_port_id;
+	uint32_t link_num;
+	uint32_t led_state;
+} wrsm_link_led_msg_t;
+
+/* Message body used for SETSEPROM request */
+typedef struct wrsm_wib_seprom_msg {
+	uint32_t wci_port_id;
+	uchar_t seprom_data[WIB_SEPROM_MSG_SIZE];
+} wrsm_wib_seprom_msg_t;
+
+/*
+ * A synchronous response message from the SC acknowledges the message.  The
+ * format of the message body is defined by the wrsm_status_msg_t structure
+ * (above).  A status of 0 indicates the SC was able to process the message as
+ * expected.
+ */
+
+/*
+ * This message is sent by the SC to the wrmsplat module when link activation
+ * is complete.  This message is only sent in response to an UPLINK message.
+ * The format of the message body is defined by the wrsm_linkisup_msg_t
+ * structure.  The async_msg_type field is set to 1, and the link_info
+ * structure is filled in with the wci portid and link number of the link on
+ * which activiation is complete.
+ */
+
+typedef struct wrsm_linkisup_msg {
+	uint32_t async_msg_type;
+	wrsm_link_msg_t link_info;
+} wrsm_linkisup_msg_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WRSM_PLAT_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_plugin.h b/usr/src/uts/sun4u/sys/wrsm_plugin.h
new file mode 100644
index 0000000000..58fbb411ef
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_plugin.h
@@ -0,0 +1,94 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _SYS_WRSM_PLUGIN_H
+#define	_SYS_WRSM_PLUGIN_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/types32.h>
+#include <sys/rsm/rsm_common.h>
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * the plugin_offset is passed by mmap to the wrsm driver. the driver
+ * breaks the offset into pieces to accurately determine the real offset
+ * required to map in the page(s) the plugin (librsmwrsm.so) is requesting
+ * The following represent valid values for page_type:
+ * 0X0 = interrupt INTR page map type (small put)
+ * 0x2000 = BARRIER page
+ * 0x4000 BARRIER_REGS  - wci_cluster_error_count register and CESR
+ * 0x6000 RECONFIG - network->reroutingp and network->route_count to check
+ * for configuration changes.
+ */
+
+#define	WRSM_PAGESIZE 0x2000 /* 8 k */
+
+
+#define	WRSM_MMAP_BARRIER_SCRATCH	0x2000
+#define	WRSM_MMAP_BARRIER_REGS	0x4000
+#define	WRSM_MMAP_RECONFIG	0x6000
+
+/* structure used to pass PUT args between plugin and driver */
+typedef struct msg_pluginput_args {
+	rsm_memseg_id_t	segment_id;
+	caddr_t buf;
+	uint64_t len;
+	off64_t offset;
+	uint64_t remote_cnodeid;
+} msg_pluginput_args_t;
+
+typedef struct msg_pluginput_args32 {
+	rsm_memseg_id_t segment_id;
+	caddr32_t buf;
+	uint64_t len;
+	off64_t offset;
+	uint64_t remote_cnodeid;
+} msg_pluginput_args32_t;
+/*
+ * The plugin (librsmwrsm.so) creates an wrsm_plugin_offset_t to pass to the
+ * driver during mmap with the offset arg. The driver breaks down the
+ * components of wrsm_plugin_offset_t to determine the real offset of the page
+ * requested by the plug-in.
+ */
+
+typedef union {
+	struct plugin_offset {
+		rsm_memseg_id_t segment_id	: 32;	/* 63:32 */
+		unsigned char export_cnodeid	: 8;	/* 31:24 */
+		uint32_t page_type		: 24;	/* 23:0 */
+	} bit;
+	off64_t val;
+} wrsm_plugin_offset_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _SYS_WRSM_PLUGIN_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_rsmpi.h b/usr/src/uts/sun4u/sys/wrsm_rsmpi.h
new file mode 100644
index 0000000000..4d55afe0ce
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_rsmpi.h
@@ -0,0 +1,50 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _SYS_WRSM_RSMPI_H
+#define	_SYS_WRSM_RSMPI_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/wrsm_common.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int wrsmrsm_get_controller_handler(const char *name, uint32_t number,
+    rsm_controller_object_t *controller, uint32_t version);
+
+int wrsmrsm_release_controller_handler(const char *name, uint32_t number,
+    rsm_controller_object_t *controller);
+
+void wrsm_rsm_setup_controller_attr(wrsm_network_t *network);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_WRSM_RSMPI_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_sess_impl.h b/usr/src/uts/sun4u/sys/wrsm_sess_impl.h
new file mode 100644
index 0000000000..7d53585524
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_sess_impl.h
@@ -0,0 +1,113 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _WRSM_SESS_IMPL_H
+#define	_WRSM_SESS_IMPL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/wrsm_common.h>
+#include <sys/wrsm_session.h>
+#include <sys/wrsm_cmmu.h>
+#include <sys/wrsm_transport.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define	SESS_SUCCESS	0
+#define	SESS_TIMEOUT	1000000 /* in usec */
+
+/*
+ * Type declarations
+ */
+
+/*
+ * Session state to a remote cnode
+ * Note: there is an array of session statea strings used for debugging
+ * purposes that must be kept in sync with this enum.
+ */
+typedef enum {
+	SESS_STATE_UNREACH,	/* newcnode not reachable */
+	SESS_STATE_DOWN,	/* No valid session */
+	SESS_STATE_ESTAB,	/* Waiting for reply to sess_start message */
+	SESS_STATE_UP		/* A valid session exists */
+} sess_state;
+
+/* Per-remote-cnode state structure */
+typedef struct wrsm_node_session {
+	cnodeid_t cnodeid;
+	kmutex_t mutex;
+	kcondvar_t cv_session_up;
+	boolean_t enabled;
+	sess_state state;
+	boolean_t state_changing;
+	boolean_t event_queued;
+	kcondvar_t cv_state_changing;
+	wrsm_sessionid_t session_id;
+	wrsm_sessionid_t last_session_id;
+	caddr_t barrier_page;
+	caddr_t barrier_mem;
+	wrsm_cmmu_tuple_t *barrier_tuple;
+	wrsm_cmmu_tuple_t remote_tuple;
+	uint_t dereferences_needed;
+	kcondvar_t cv_await_dereferences;
+} wrsm_node_session_t;
+
+/* Session state structure */
+#define	MAX_CLIENTS	10
+struct wrsm_session {
+	wrsm_network_t *network;
+	wrsm_sess_func_t cb[MAX_CLIENTS];
+	wrsm_node_session_t node[WRSM_MAX_CNODES];
+};
+
+/* Message formats */
+typedef struct {
+	wrsm_message_header_t header;
+	wrsm_sessionid_t session_id;
+	ncslice_t barrier_ncslice;
+	wrsm_cmmu_offset_t barrier_offset;
+} msg_session_start_t;
+
+typedef struct {
+	wrsm_message_header_t header;
+	wrsm_sessionid_t session_id;
+	ncslice_t barrier_ncslice;
+	off_t barrier_offset;
+	int result;
+} msg_session_start_rsp_t;
+
+typedef struct {
+	wrsm_message_header_t header;
+	wrsm_sessionid_t session_id;
+} msg_session_end_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WRSM_SESS_IMPL_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_session.h b/usr/src/uts/sun4u/sys/wrsm_session.h
new file mode 100644
index 0000000000..18a5d2bdfa
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_session.h
@@ -0,0 +1,128 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _WRSM_SESS_H
+#define	_WRSM_SESS_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <sys/wrsm_transport.h>
+
+/*
+ * Type Declarations
+ */
+
+typedef enum {
+	SESSION_UP,
+	SESSION_DOWN
+} wrsm_sess_state;
+
+
+/*
+ * Definition of the user's callback function.
+ *
+ * The boolean return value should be set to true if teardown is complete,
+ * or false if there are still references to this node from this subsystem.
+ * If false was returned, the client should eventually call
+ * wrsm_sess_unreferenced() to indicate when teardown is finally complete.
+ */
+typedef boolean_t (*wrsm_sess_func_t)(wrsm_network_t *, cnodeid_t,
+    wrsm_sess_state);
+
+
+/*
+ * Config functions, should be called by transport.
+ */
+
+/* Init function. */
+void wrsm_sess_init(wrsm_network_t *);
+
+/* Fini function. */
+void wrsm_sess_fini(wrsm_network_t *);
+
+/* Informs session that a new cnode is reachable */
+void wrsm_sess_reachable(wrsm_network_t *, cnodeid_t);
+
+/* Informs session that a cnode is no longer reachable */
+void wrsm_sess_unreachable(wrsm_network_t *, cnodeid_t);
+
+/* Establishes a session with a remote cnode, if enabled. */
+wrsm_sessionid_t wrsm_sess_establish(wrsm_network_t *, cnodeid_t);
+
+/* Asynchronously tears down a session to a cnode. */
+void wrsm_sess_teardown(wrsm_network_t *, cnodeid_t);
+
+/* Returns the current session. */
+wrsm_sessionid_t wrsm_sess_get(wrsm_network_t *, cnodeid_t);
+
+/*
+ * Functions for client use.
+ */
+
+/* Allows user to register for callbacks. */
+void wrsm_sess_register(wrsm_network_t *, wrsm_sess_func_t);
+
+/* Removes a user callback registration. */
+void wrsm_sess_unregister(wrsm_network_t *, wrsm_sess_func_t);
+
+/*
+ * Notify session layer of final dereference of node,
+ * completing earlier session down callback.
+ */
+void wrsm_sess_unreferenced(wrsm_network_t *net, cnodeid_t cnode);
+
+/*
+ * Functions for use by some topology management entitiy.
+ */
+
+/* Enables communication with a cnode. */
+void wrsm_sess_enable(wrsm_network_t *, cnodeid_t);
+
+/* Disables communication with a cnode. May cause a teardown. */
+int wrsm_sess_disable(wrsm_network_t *, cnodeid_t);
+
+/* Returns a cnode bitmask indicating which cnodes have valid sessions */
+void wrsm_sess_get_cnodes(wrsm_network_t *, cnode_bitmask_t *);
+
+/*
+ * call to initiate an immediate session establish/teardown
+ */
+void wrsm_sess_establish_immediate(wrsm_network_t *net, cnodeid_t cnodeid);
+void wrsm_sess_teardown_immediate(wrsm_network_t *net, cnodeid_t cnodeid);
+
+/* Does write/read to remote node */
+int wrsm_sess_touch_node(wrsm_network_t *net, cnodeid_t cnodeid,
+    uint32_t stripes);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WRSM_SESS_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_transport.h b/usr/src/uts/sun4u/sys/wrsm_transport.h
new file mode 100644
index 0000000000..fe7c37af6e
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_transport.h
@@ -0,0 +1,245 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef	_WRSM_TRANSPORT_H
+#define	_WRSM_TRANSPORT_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#include <sys/wrsm_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * WRSM_TL_VERSION - If any message formats change, this constant must
+ * change in the next release, to ensure that imcompatible drivers
+ * recognize the version skew.
+ */
+#define	WRSM_TL_VERSION	0x1
+
+/*
+ * Messagetypes
+ * When you add a message here, remember to add it to fuction
+ * messagetypes2string in wrsm_tl.c.
+ */
+enum {
+	/* Common message types */
+	WRSM_MSG_ACK,
+	WRSM_MSG_NACK,
+	WRSM_MSG_PING,
+	WRSM_MSG_PING_RESPONSE,
+	/* Config message types */
+	WRSM_MSG_CONFIG_COOKIE,
+	WRSM_MSG_CONFIG_PASSTHROUGH_LIST,
+	WRSM_MSG_CONFIG_PASSTHROUGH_LIST_RESPONSE,
+	WRSM_MSG_CONFIG_CNODE_ACCESS,
+	/* Multihop message types */
+	/* Session message types */
+	WRSM_MSG_SESSION_START,
+	WRSM_MSG_SESSION_START_RESPONSE,
+	WRSM_MSG_SESSION_END,
+	/* RSMPI Segment message types */
+	WRSM_MSG_SEGMENT_CONNECT,
+	WRSM_MSG_SEGMENT_CONNECT_RESPONSE,
+	WRSM_MSG_SEGMENT_SMALLPUTMAP,
+	WRSM_MSG_SEGMENT_SMALLPUTMAP_RESPONSE,
+	WRSM_MSG_SEGMENT_BARRIERMAP,
+	WRSM_MSG_SEGMENT_BARRIERMAP_RESPONSE,
+	WRSM_MSG_SEGMENT_SEGMAP,
+	WRSM_MSG_SEGMENT_SEGMAP_RESPONSE,
+	WRSM_MSG_SEGMENT_DISCONNECT,
+	WRSM_MSG_SEGMENT_UNPUBLISH,
+	WRSM_MSG_SEGMENT_UNPUBLISH_RESPONSE,
+	WRSM_MSG_SEGMENT_ACCESS,
+	WRSM_MSG_SEGMENT_ACCESS_RESPONSE,
+	/* RSMPI Interrupt message types */
+	WRSM_MSG_INTR_RECVQ_CREATE,
+	WRSM_MSG_INTR_RECVQ_CREATE_RESPONSE,
+	WRSM_MSG_INTR_RECVQ_CONFIG,
+	WRSM_MSG_INTR_RECVQ_CONFIG_RESPONSE,
+	WRSM_MSG_INTR_RECVQ_DESTROY,
+	/* RSMPI Barrier message types */
+	/* RSMAPI Segment message types */
+	/* RSMAPI Interrupt message types */
+	/* RSMAPI Barrier message types */
+	WRSM_MSG_TYPES_MAX
+};
+typedef uint8_t  wrsm_message_type_t;
+
+/*
+ * Format of messages
+ */
+#define	WRSM_TL_MSG_SIZE	(WRSM_CACHELINE_SIZE)
+
+typedef uint32_t wrsm_messageid_t;
+typedef uint8_t  wrsm_version_t;
+typedef uint8_t  wrsm_sessionid_t;
+#define	SESS_ID_INVALID	0
+
+typedef struct wrsm_message_header {
+	uint32_t		reserved1;
+	wrsm_version_t		version;
+	wrsm_sessionid_t	session_id;
+	cnodeid_t		source_cnode;
+	wrsm_message_type_t	message_type;
+	wrsm_messageid_t	message_id;
+	uint32_t		reserved2;
+} wrsm_message_header_t;
+
+#define	WRSM_MESSAGE_BODY_SIZE (WRSM_TL_MSG_SIZE - \
+				sizeof (wrsm_message_header_t))
+
+/*
+ * An object of type wrsm_message_t must be 64-byte aligned. The user can
+ * cast the body to message-specific structures.
+ */
+typedef struct wrsm_message {
+	wrsm_message_header_t  header;
+	uint8_t		 body[WRSM_MESSAGE_BODY_SIZE];
+} wrsm_message_t;
+
+/*
+ * The following type may be allocated on the stack, it has the
+ * right size for the wrsm message, optimal aignment for wrsm_blkread/blkwrite
+ * and can be casted into either wrsm_message_t type or wrsm_smallput_msg.
+ * The wrsm_message_t requires 32 bit allignment, the wrsm_raw_message
+ * is declared as an array of uint64_t - giving it 8 byte alignment
+ */
+typedef uint64_t wrsm_raw_message_t[WRSM_TL_MSG_SIZE / sizeof (uint64_t)];
+
+/*
+ * Definition of the user's message handler function. rxhandler is called
+ * when a given message type is received. Returns boolean to indicate
+ * if the message was successfully processed. For datagrams, the return
+ * value is ignored. For RPC messages, this function is called before the
+ * thread calling rpc() is awakened, so returning FALSE will result in the
+ * message being ignored, and the pending thread will eventually timeout.
+ * The message buffer will be allcoated and freed by the transport, and
+ * should not be freed by the user.
+ */
+typedef boolean_t (*wrsm_message_rxhandler_t)(wrsm_network_t *network,
+					wrsm_message_t *message);
+
+/*
+ * Definition of the user's message handler function. txhandler is used for
+ * formatting any transmit messages. Returns boolean to indicate if the
+ * message was successfully processed. Returning FALSE will cause the
+ * message to be discarded without being sent to the remote node (used,
+ * for example, if a session cannot be established with the remote cnode).
+ * The message buffer will be allcoated and freed by the
+ * transport, and should not be freed by the user.
+ */
+typedef boolean_t (*wrsm_message_txhandler_t)(wrsm_network_t *network,
+					cnodeid_t destination,
+					wrsm_message_t *message);
+
+/*
+ * Transport functions
+ *
+ * The following functions return 0 for success.
+ */
+
+/* Initializes the transport for a specific RSM network */
+int wrsm_tl_init(wrsm_network_t *rsm_network);
+
+/* Cleans-up the transport for a specific RSM network */
+void wrsm_tl_fini(wrsm_network_t *rsm_network);
+
+/* Informs the transport that a new cnode is part of the config */
+int wrsm_tl_newcnode(wrsm_network_t *rsm_network, cnodeid_t cnodeid);
+
+/* Informs the transport that a cnode is no longer part of config */
+int wrsm_tl_removecnode(wrsm_network_t *rsm_network, cnodeid_t cnodeid);
+
+/* Informs the transport that a cnode is reachable */
+void wrsm_tl_reachable(wrsm_network_t *rsm_network, cnodeid_t cnodeid);
+
+/* Informs the transport that a cnode is no longer reachable */
+void wrsm_tl_unreachable(wrsm_network_t *rsm_network, cnodeid_t cnodeid);
+
+/* Adds user-defined handlers for a specific message type */
+int wrsm_tl_add_handler(wrsm_network_t *rsm_network, wrsm_message_type_t,
+    wrsm_message_txhandler_t send_func, wrsm_message_rxhandler_t receive_func);
+
+/* Sends a datagram. Caller must allocate and free msg buffer. */
+int wrsm_tl_dg(wrsm_network_t *rsm_network, cnodeid_t destination,
+    wrsm_message_t *msg);
+
+/*
+ * Sends a message, waits for a response. If successful (return code is 0),
+ * the response structure will contain the message from the remote node.
+ * The caller must allocate and free both the msg and response buffer.
+ * The caller may use the same message buffer for both the msg and response,
+ * and the response will overwrite the original message.
+ */
+int wrsm_tl_rpc(wrsm_network_t *rsm_network, cnodeid_t destination,
+    wrsm_message_t *msg, wrsm_message_t *response);
+
+/*
+ * Response to an rpc message, called by a receive message handler. The
+ * orig_msg must be an unmodified version of the message buffer provided
+ * to the receive message handler. The caller must allocate and free the
+ * response buffer.
+ */
+int wrsm_tl_rsp(wrsm_network_t *rsm_network, wrsm_message_t *orig_msg,
+    wrsm_message_t *response);
+
+/*
+ * The macro WRSM_TL_DUMP_MESSAGE dumps the contents of a message to the
+ * console for debugging. If DEBUG is not defined, the macro results in
+ * no code being generated.
+ */
+#ifdef DEBUG
+#define	WRSM_TL_DUMP_MESSAGE(txt, msg) wrsm_tl_dump_message(txt, msg)
+void wrsm_tl_dump_message(char *txt, wrsm_message_t *msg);
+#else
+#define	WRSM_TL_DUMP_MESSAGE(txt, msg)
+#endif /* DEBUG */
+/*
+ * Standard handler functions
+ */
+
+/* Use WRSM_TL_NO_HANDLER if you don't need a send/receive handler. */
+#define	WRSM_TL_NO_HANDLER	NULL
+
+/*
+ * Adds the session id to the message header. If there is currently no
+ * session with the destination node, it will attempt to establish a new
+ * session.
+ */
+boolean_t wrsm_tl_txhandler_sessionid(wrsm_network_t *, cnodeid_t,
+    wrsm_message_t *);
+
+/* Validates the session id for an incoming rpc response. */
+boolean_t wrsm_tl_rxhandler_sessionid(wrsm_network_t *, wrsm_message_t *);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WRSM_TRANSPORT_H */
diff --git a/usr/src/uts/sun4u/sys/wrsm_types.h b/usr/src/uts/sun4u/sys/wrsm_types.h
new file mode 100644
index 0000000000..8a256b1bc3
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/wrsm_types.h
@@ -0,0 +1,126 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ */
+
+#ifndef _WRSM_TYPES_H
+#define	_WRSM_TYPES_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+
+#include <sys/types.h>
+
+#ifdef _KERNEL
+#include <sys/rsm/rsmpi.h>
+#endif
+#include <sys/wci_offsets.h>
+
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	WRSM_NAME "wrsm"
+#define	WRSM_MAX_RAG_INSTANCE 32
+#define	WRSM_MAX_CNODES	256
+#define	WRSM_MAX_NCSLICES 256
+#define	WRSM_MAX_WNODES 16
+#define	WRSM_LINKS_PER_WCI ENTRIES_WCI_SW_LINK_STATUS
+#define	WRSM_MAX_LINKS_PER_WCI 3
+#define	WRSM_MAX_WCIS_PER_STRIPE 4
+#define	WRSM_MAX_DNIDS 4
+#define	WRSM_NODE_NCSLICES	8
+
+/*
+ * macros for manipulating bitmask sets that use arrays of 32-bit ints
+ * (lifted from cpuvar.h)
+ */
+#define	WRSMBPM		(sizeof (uint32_t) * NBBY) /* Number of bits in mask */
+#define	WRSMSHIFT	5			/* divide by 32 */
+#define	WRSMBPM		(sizeof (uint32_t) * NBBY) /* Number of bits in mask */
+#define	WRSMBIT(bit)		((uint32_t)1 << (((uint32_t)bit) & 0x1f))
+#define	WRSMMASKS(x, y)	(((x)+((y)-1))/(y))	/* Number of masks in set */
+#define	WRSMMASKSIZE(set) (sizeof (set) / sizeof (uint32_t))
+
+/*
+ * bit mask manipulation macros
+ */
+#define	WRSM_IN_SET(set, bit)	(((set).b[(bit)>>WRSMSHIFT]) & WRSMBIT(bit))
+#define	WRSMSET_ADD(set, bit)	(((set).b[(bit)>>WRSMSHIFT]) |= WRSMBIT(bit))
+#define	WRSMSET_DEL(set, bit)	(((set).b[(bit)>>WRSMSHIFT]) &= ~WRSMBIT(bit))
+#define	WRSMSET_ZERO(set)	bzero(&(set), sizeof (set))
+
+
+#define	NCSLICE_MASKS	WRSMMASKS(WRSM_MAX_NCSLICES, WRSMBPM)
+typedef struct wrsm_ncslice_bitmask {
+	uint32_t	b[NCSLICE_MASKS];
+} wrsm_ncslice_bitmask_t;
+
+#define	CNODE_MASKS	WRSMMASKS(WRSM_MAX_CNODES, WRSMBPM)
+typedef struct wrsm_cnode_bitmask {
+	uint32_t	b[CNODE_MASKS];
+} wrsm_cnode_bitmask_t;
+
+#define	WNODE_MASKS	WRSMMASKS(WRSM_MAX_WNODES, WRSMBPM)
+typedef struct wrsm_wnode_bitmask {
+	uint32_t	b[WNODE_MASKS];
+} wrsm_wnode_bitmask_t;
+
+
+typedef int64_t		wrsm_fmnodeid_t;
+typedef unsigned char	wrsm_cnodeid_t;
+typedef unsigned char	wrsm_wnodeid_t;
+typedef uint16_t	wrsm_gnid_t;
+typedef unsigned char	wrsm_ncslice_t;
+typedef unsigned char	wrsm_linkid_t;
+typedef uint32_t 	wrsm_safari_port_t;
+
+
+/*
+ * This is an ordered list.  The first entry (entry 0) is the small page
+ * ncslice.  The remaining 7 entries are large page slices; each entry maps
+ * to a well defined range of CMMU entries, as described in the WCI PRM.
+ * The ncslice for entry 1 must end with b'001', the ncslice for entry 2
+ * must end with b'010', entry 3 with b'011' and so on.  An ncslice value
+ * of 0 indicates that the entry is invalid.
+ */
+typedef struct node_ncslice_array {
+	wrsm_ncslice_t id[WRSM_NODE_NCSLICES];
+} wrsm_node_ncslice_array_t;
+
+
+/*
+ * typedefs for opaque structure definitions (for structures private to
+ * particular wrsm modules, declared in module specific header files)
+ */
+typedef struct wrsm_net_member wrsm_net_member_t;
+typedef struct wrsm_wci_data wrsm_wci_data_t;
+typedef struct wrsm_ncslice_info wrsm_ncslice_info_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* _WRSM_TYPES_H */
diff --git a/usr/src/uts/sun4u/sys/zulu_hat.h b/usr/src/uts/sun4u/sys/zulu_hat.h
new file mode 100644
index 0000000000..447d631944
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/zulu_hat.h
@@ -0,0 +1,214 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2003 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	__ZULU_HAT_INCL__
+#define	__ZULU_HAT_INCL__
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define	ZULU_TTE8K		0
+#define	ZULU_TTE64K		1
+#define	ZULU_TTE512K		2
+#define	ZULU_TTE4M		3
+#define	ZULUM_MAX_PG_SIZES	4
+
+#define	ZULU_CTX_MASK		0x1fff
+
+#ifndef _ASM
+
+#include <sys/types.h>
+#include <sys/atomic.h>
+#include <vm/xhat.h>
+#include <sys/avl.h>
+
+
+#define	ZULU_HAT_BP_SHIFT		13
+#define	ZULU_HAT_SZ_SHIFT(sz)		((sz) * 3)
+#define	ZULU_HAT_NUM_PGS(sz)		(1<<ZULU_HAT_SZ_SHIFT(sz))
+#define	ZULU_HAT_PGSHIFT(s)		(ZULU_HAT_BP_SHIFT + \
+					ZULU_HAT_SZ_SHIFT(s))
+#define	ZULU_HAT_PGSZ(s)		((uint64_t)1<<ZULU_HAT_PGSHIFT(s))
+#define	ZULU_HAT_PGOFFSET(s)		(ZULU_HAT_PGSZ(s) - 1)
+#define	ZULU_HAT_PGMASK(s)		(~ZULU_HAT_PGOFFSET((uint64_t)s))
+#define	ZULU_HAT_PGADDR(a, s)		((uintptr_t)(a) & ZULU_HAT_PGMASK(s))
+#define	ZULU_HAT_PGADDROFF(a, s)	((uintptr_t)(a) & ZULU_HAT_PGOFFSET(s))
+#define	ZULU_HAT_PGDIFF(a, s)		(ZULU_HAT_PGSZ(s) - \
+					ZULU_HAT_PGADDROFF(a, s))
+
+#define	ZULU_HAT_PFN_MASK(sz)		((1 << ZULU_HAT_SZ_SHIFT(sz)) - 1)
+#define	ZULU_HAT_ADJ_PFN(ttep, vaddr) \
+	((ttep->zulu_tte_pfn & ~ZULU_HAT_PFN_MASK(ttep->zulu_tte_size)) | \
+	(((uintptr_t)vaddr >> ZULU_HAT_BP_SHIFT) & \
+	ZULU_HAT_PFN_MASK(ttep->zulu_tte_size)))
+
+/*
+ * zulu_ctx_tab is an array of pointers to zulu hat structures.
+ * since the addresses are 8 byte aligned we use bit 0 as a lock flag.
+ * This will synchronize TL1 access to the tsb and the mappings.
+ */
+
+#define	ZULU_CTX_LOCK	0x1
+
+#define	ZULU_CTX_LOCK_INIT(c)		zulu_ctx_tab[c] = NULL
+#define	ZULU_CTX_IS_FREE(c)		(zulu_ctx_tab[c] == NULL)
+#define	ZULU_CTX_SET_HAT(c, h) 		zulu_ctx_tab[c] = h
+
+#define	ZULU_CTX_GET_HAT(c)	(struct zulu_hat *)((uint64_t) \
+				    zulu_ctx_tab[c] & ~ZULU_CTX_LOCK)
+
+struct zulu_tag {
+	uint64_t	zulu_tag_page:51;	/* [63:13] vpage */
+};
+
+struct zulu_tte {
+	union {
+		struct zulu_tag zulu_tte_tag;
+		uint64_t 	zulu_tte_addr;
+	} un;
+	uint_t	zulu_tte_valid  :1;
+	uint_t	zulu_tte_perm   :1;
+	uint_t	zulu_tte_size   :3;
+	uint_t	zulu_tte_locked :1;
+	uint_t	zulu_tte_pfn;
+};
+
+/*
+ * zulu hat stores its list of translation in a hash table.
+ * TODO: size this table. 256 buckets may be too small.
+ */
+#define	ZULU_HASH_TBL_NUM  0x100
+#define	ZULU_HASH_TBL_MASK (ZULU_HASH_TBL_NUM - 1)
+#define	ZULU_HASH_TBL_SHIFT(_s) (ZULU_HAT_BP_SHIFT + (3 * _s))
+#define	ZULU_HASH_TBL_SZ  (ZULU_HASH_TBL_NUM * sizeof (struct zulu_hat_blk *))
+#define	ZULU_MAP_HASH_VAL(_v, _s) (((_v) >> ZULU_HASH_TBL_SHIFT(_s)) & \
+							ZULU_HASH_TBL_MASK)
+#define	ZULU_MAP_HASH_HEAD(_zh, _v, _s) \
+		(_zh->hash_tbl[ZULU_MAP_HASH_VAL(_v, _s)])
+
+/*
+ *
+ * TODO: need finalize the number of entries in the TSB
+ * 32K tsb entries caused us to never get a tsb miss that didn't cause
+ * a page fault.
+ *
+ * Reducing TSB_NUM to 512 entries caused tsb_miss > tsb_hit
+ * in a yoyo run.
+ */
+#define	ZULU_TSB_NUM		4096
+#define	ZULU_TSB_SZ		(ZULU_TSB_NUM * sizeof (struct zulu_tte))
+#define	ZULU_TSB_HASH(a, ts, s)	(((uintptr_t)(a) >> ZULU_HAT_PGSHIFT(ts)) & \
+					(s-1))
+
+#define	ZULU_VADDR(tag)		(tag & ~ZULU_CTX_MASK)
+#define	ZULU_TTE_TO_PAGE(a)	a.un.zulu_tte_tag.zulu_tag_page
+
+
+struct zulu_hat_blk {
+	struct zulu_hat_blk	*zulu_hash_next;
+	struct zulu_hat_blk	*zulu_hash_prev;
+	struct zulu_shadow_blk  *zulu_shadow_blk;
+	struct zulu_tte		zulu_hat_blk_tte;
+};
+
+#define	zulu_hat_blk_vaddr	zulu_hat_blk_tte.un.zulu_tte_addr
+#define	zulu_hat_blk_pfn	zulu_hat_blk_tte.zulu_tte_pfn
+#define	zulu_hat_blk_page	ZULU_TTE_TO_PAGE(zulu_hat_blk_tte)
+#define	zulu_hat_blk_perm	zulu_hat_blk_tte.zulu_tte_perm
+#define	zulu_hat_blk_size	zulu_hat_blk_tte.zulu_tte_size
+#define	zulu_hat_blk_valid	zulu_hat_blk_tte.zulu_tte_valid
+
+/*
+ * for fast lookups by address, len we use an avl list to shadow occupied
+ * 4Mb regions that have mappings.
+ */
+#define	ZULU_SHADOW_BLK_RANGE 0x400000
+#define	ZULU_SHADOW_BLK_MASK (~(ZULU_SHADOW_BLK_RANGE - 1))
+
+struct zulu_shadow_blk {
+	avl_node_t	link;		/* must be at beginning of struct */
+	uint64_t	ivaddr;		/* base address of this node */
+	uint64_t	ref_count;
+	uint64_t	min_addr;
+	uint64_t	max_addr;
+};
+#define	ZULU_SHADOW_BLK_LINK_OFFSET (0)
+
+struct zulu_hat {
+	struct xhat		zulu_xhat;
+	kmutex_t		lock;
+	avl_tree_t		shadow_tree;
+	char			magic;	    /* =42 to mark our data for mdb */
+	unsigned		in_fault  : 1;
+	unsigned		freed	  : 1;
+	unsigned		map8k	  : 1;
+	unsigned		map64k	  : 1;
+	unsigned		map512k	  : 1;
+	unsigned		map4m	  : 1;
+	short			zulu_ctx;
+	unsigned short		zulu_tsb_size;	/* TODO why not a constant? */
+	struct zulu_hat_blk	**hash_tbl;
+	struct zulu_tte 	*zulu_tsb;
+	struct zulu_shadow_blk	*sblk_last;	/* last sblk looked up */
+	uint64_t		fault_ivaddr_last; /* last translation loaded */
+	caddr_t			vaddr_max;
+	hrtime_t		last_used;
+	void			*zdev;
+};
+
+#define	ZULU_HAT2AS(h)	((h)->zulu_xhat.xhat_as)
+
+/*
+ * Assembly language function for TSB lookups
+ */
+uint64_t zulu_hat_tsb_lookup_tl0(struct zulu_hat *zhat, caddr_t vaddr);
+
+/*
+ * zuluvm's interface to zulu_hat
+ */
+
+int zulu_hat_load(struct zulu_hat *zhat, caddr_t vaddr, enum seg_rw rw, int *);
+
+int zulu_hat_init();
+int zulu_hat_destroy();
+int zulu_hat_attach(void *arg);
+int zulu_hat_detach(void *arg);
+struct zulu_hat *zulu_hat_proc_attach(struct as *as, void *zdev);
+void zulu_hat_proc_detach(struct zulu_hat *zhat);
+
+void zulu_hat_validate_ctx(struct zulu_hat *zhat);
+void zulu_hat_terminate(struct zulu_hat *zhat);
+
+#endif /* _ASM */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* __ZULU_HAT_INCL__ */
diff --git a/usr/src/uts/sun4u/sys/zulumod.h b/usr/src/uts/sun4u/sys/zulumod.h
new file mode 100644
index 0000000000..9baf9f9982
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/zulumod.h
@@ -0,0 +1,263 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2003 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	__ZULUMOD_INCL__
+#define	__ZULUMOD_INCL__
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <sys/int_const.h>
+#include <sys/zuluvm.h>
+
+#ifndef _ASM
+
+#include <sys/zulu_hat.h>
+#include <sys/sysmacros.h>
+
+#define	ZULUVM_VERSION_STR(a)	#a
+#define	ZULUVM_VERSION(a)	ZULUVM_VERSION_STR(a)
+#define	ZULUVM_MOD_VERSION \
+	ZULUVM_VERSION(XHAT_PROVIDER_VERSION) ## "." ## \
+	ZULUVM_VERSION(ZULUVM_INTERFACE_VERSION)
+
+#define	ZULUDCHKFUNC(_p1, _p2, _p3) \
+	((_p1) != NULL && (_p1)->_p2 != NULL) ? \
+	(_p1)->_p2 _p3 : ZULUVM_NO_SUPPORT
+#define	ZULUDCHKPROC(_p1, _p2, _p3) \
+	if ((_p1) != NULL && (_p1)->_p2 != NULL) (_p1)->_p2 _p3
+
+#define	zulud_set_itlb_pc(_devp, _a, _b) \
+	ZULUDCHKPROC((_devp)->dops, set_itlb_pc, (_a, _b))
+#define	zulud_set_dtlb_pc(_devp, _a, _b) \
+	ZULUDCHKPROC((_devp)->dops, set_dtlb_pc, (_a, _b))
+#define	zulud_write_tte(_devp, _a, _b, _c, _d, _e, _f) \
+	ZULUDCHKFUNC((_devp)->dops, write_tte, (_a, _b, _c, _d, _e, _f))
+#define	zulud_tlb_done(_devp, _a, _b, _c) \
+	ZULUDCHKPROC((_devp)->dops, tlb_done, (_a, _b, _c))
+#define	zulud_demap_page(_devp, _a, _b, _c) \
+	ZULUDCHKPROC((_devp)->dops, demap_page, (_a, _b, _c))
+#define	zulud_demap_ctx(_devp, _a, _b) \
+	ZULUDCHKPROC((_devp)->dops, demap_ctx, (_a, _b))
+
+#endif
+
+#define	ZULUVM_DATA0_IDX	0
+#define	ZULUVM_DATA1_IDX	1
+#define	ZULUVM_DATA2_IDX	2
+#define	ZULUVM_DATA3_IDX	3
+#define	ZULUVM_DATA4_IDX	4
+#define	ZULUVM_DATA5_IDX	5
+#define	ZULUVM_DATA6_IDX	6
+#define	ZULUVM_DATA7_IDX	7
+
+#define	ZULUVM_IDX2FLAG(i)	(1 << (7 - i))
+#define	ZULUVM_DATA0_FLAG	ZULUVM_IDX2FLAG(ZULUVM_DATA0_IDX)
+#define	ZULUVM_DATA1_FLAG	ZULUVM_IDX2FLAG(ZULUVM_DATA1_IDX)
+#define	ZULUVM_DATA2_FLAG	ZULUVM_IDX2FLAG(ZULUVM_DATA2_IDX)
+#define	ZULUVM_DATA3_FLAG	ZULUVM_IDX2FLAG(ZULUVM_DATA3_IDX)
+#define	ZULUVM_DATA4_FLAG	ZULUVM_IDX2FLAG(ZULUVM_DATA4_IDX)
+#define	ZULUVM_DATA5_FLAG	ZULUVM_IDX2FLAG(ZULUVM_DATA5_IDX)
+#define	ZULUVM_DATA6_FLAG	ZULUVM_IDX2FLAG(ZULUVM_DATA6_IDX)
+#define	ZULUVM_DATA7_FLAG	ZULUVM_IDX2FLAG(ZULUVM_DATA7_IDX)
+
+#define	ZULUVM_TLB_ADDR_IDX	ZULUVM_DATA0_IDX
+#define	ZULUVM_TLB_TYPE_IDX	ZULUVM_DATA1_IDX
+#define	ZULUVM_TLB_TTE_IDX	ZULUVM_DATA2_IDX
+#define	ZULUVM_TLB_ERRCODE_IDX	ZULUVM_DATA3_IDX
+
+#define	ZULUVM_DATA_FLAGS	(ZULUVM_DATA1_FLAG | \
+				ZULUVM_DATA6_FLAG)
+
+#define	ZULUVM_GET_TLB_TTE(devp) \
+		(devp)->zvm.idata[ZULUVM_TLB_TTE_IDX]
+#define	ZULUVM_GET_TLB_ADDR(devp) \
+		(devp)->zvm.idata[ZULUVM_TLB_ADDR_IDX]
+#define	ZULUVM_GET_TLB_TYPE(devp) (ZULUVM_DMA_MASK & \
+		(devp)->zvm.idata[ZULUVM_TLB_TYPE_IDX])
+#define	ZULUVM_GET_TLB_ERRCODE(devp) (int)(0xffffffff & \
+		(devp)->zvm.idata[ZULUVM_TLB_ERRCODE_IDX])
+
+#define	ZULUVM_MAX_DEV		2
+#define	ZULUVM_PIL		PIL_2
+#define	ZULUVM_NUM_PGSZS	4
+
+#define	ZULUVM_STATE_IDLE		0
+#define	ZULUVM_STATE_STOPPED		1
+#define	ZULUVM_STATE_CANCELED		2
+#define	ZULUVM_STATE_TLB_PENDING	3
+#define	ZULUVM_STATE_INTR_QUEUED	4
+#define	ZULUVM_STATE_INTR_PENDING	5
+#define	ZULUVM_STATE_WRITE_TTE		6
+
+#ifndef _ASM
+
+typedef struct {
+	uint64_t	idata[4];	/* mondo pkt copy area */
+	void		*arg;		/* arg for device calls */
+	uint64_t	mmu_pa;		/* phy. addr of MMU regs */
+	struct zuluvm_proc *proc1;
+	struct zuluvm_proc *proc2;
+	volatile uint32_t state;	/* state of tlb miss handling */
+	short		intr_num;	/* our soft intr number */
+	short		dmv_intr;	/* dmv interrupt handle */
+#ifdef ZULUVM_STATS
+	int 		cancel;
+	int		tlb_miss[ZULUVM_NUM_PGSZS];
+	int		pagefault;
+	int		no_mapping;
+	int		preload;
+	int		migrate;
+	int		pagesize;
+	int		itlb1miss;
+	int		dtlb1miss;
+	int		itlb2miss;
+	int		dtlb2miss;
+	int		demap_page;
+	int		demap_ctx;
+#endif
+	uint64_t	pfnbuf[50];
+	int		pfncnt;
+} zuluvm_miss_t;
+
+#ifdef ZULUVM_STATS
+#define	ZULUVM_STATS_MISS(devp, sz)	(devp)->zvm.tlb_miss[sz]++
+#define	ZULUVM_STATS_PAGEFAULT(devp)	(devp)->zvm.pagefault++
+#define	ZULUVM_STATS_NOMAP(devp)	(devp)->zvm.no_mapping++
+#define	ZULUVM_STATS_PRELOAD(devp)	(devp)->zvm.preload++
+#define	ZULUVM_STATS_MIGRATE(devp)	(devp)->zvm.migrate++
+#define	ZULUVM_STATS_PAGEZISE(devp)	(devp)->zvm.pagesize++
+#define	ZULUVM_STATS_CANCEL(devp)	(devp)->zvm.cancel++
+#define	ZULUVM_STATS_DEMAP_PAGE(devp)	(devp)->zvm.demap_page++
+#define	ZULUVM_STATS_DEMAP_CTX(devp)	(devp)->zvm.demap_ctx++
+#else
+#define	ZULUVM_STATS_MISS(devp, sz)
+#define	ZULUVM_STATS_PAGEFAULT(devp)
+#define	ZULUVM_STATS_NOMAP(devp)
+#define	ZULUVM_STATS_PRELOAD(devp)
+#define	ZULUVM_STATS_MIGRATE(devp)
+#define	ZULUVM_STATS_PAGEZISE(devp)
+#define	ZULUVM_STATS_CANCEL(devp)
+#define	ZULUVM_STATS_DEMAP_PAGE(devp)
+#define	ZULUVM_STATS_DEMAP_CTX(devp)
+#endif
+
+#define	ZULUVM_MAX_INTR 32
+
+typedef struct {
+	short offset;
+	short ino;
+} zuluvm_intr_t;
+
+/*
+ * This structure contains per device data.
+ * It is protected by dev_lck.
+ */
+typedef struct {
+	zuluvm_miss_t		zvm;		/* tlb miss state */
+	volatile uint64_t	*imr;		/* intr mapping regs */
+	struct zuluvm_proc 	*procs; 	/* protected by proc_lck */
+	dev_info_t		*dip;		/* device driver instance */
+	zulud_ops_t		*dops;		/* device drv operations */
+	kmutex_t		load_lck;	/* protects in_intr */
+	kmutex_t		dev_lck;	/* protects this struct */
+	kmutex_t 		proc_lck;	/* protects active procs */
+	kcondvar_t 		intr_wait;	/* sync for as_free */
+	int			intr_flags;
+	int			in_intr;
+	kmutex_t		park_lck;	/* page fault thread */
+	kcondvar_t		park_cv;
+	int			parking;
+	int			agentid;	/* zulu's agent id */
+	zuluvm_intr_t		interrupts[ZULUVM_MAX_INTR];
+} zuluvm_state_t;
+
+#define	ZULUVM_INTR_OFFSET	offsetof(zuluvm_state_t, interrupts)
+#define	ZULUVM_INTR2INO(addr)	(((zuluvm_intr_t *)(addr))->ino)
+#define	ZULUVM_INTR2ZDEV(addr) \
+	(zuluvm_state_t *)((caddr_t)addr - (ZULUVM_INTR2INO(addr) * \
+	sizeof (zuluvm_intr_t)) - ZULUVM_INTR_OFFSET)
+
+typedef struct zuluvm_proc {
+	struct zulu_hat	*zhat;
+	zuluvm_state_t  *zdev;  /* back ptr to dev instance */
+	unsigned short	refcnt;	/* keep this until ref == 0 */
+	short		valid;	/* if valid is 0 then don't use */
+	struct zuluvm_proc *next;
+	struct zuluvm_proc *prev;
+} zuluvm_proc_t;
+
+#define	ZULUVM_DO_INTR1		INT32_C(1)
+#define	ZULUVM_WAIT_INTR1	INT32_C(2)
+#define	ZULUVM_DO_INTR2		INT32_C(4)
+#define	ZULUVM_WAIT_INTR2	INT32_C(8)
+
+int zuluvm_change_state(uint32_t *state_pa, int new, int assume);
+void zuluvm_demap_page(void *, struct hat *, short, caddr_t, uint_t);
+void zuluvm_demap_ctx(void *, short);
+void zuluvm_dmv_tlbmiss_tl1(void);
+void zuluvm_load_tte(struct zulu_hat *zhat, caddr_t addr, uint64_t pfn,
+		int perm, int size);
+
+
+#endif
+
+/*
+ * The following defines are copied from the ZFB and ZULU
+ * workspaces. We re-define them here since we can't have
+ * a dependency onto files outside our consolidation
+ */
+#define	ZULUVM_IMR_V_MASK	UINT64_C(0x0000000080000000)
+#define	ZULUVM_IMR_TARGET_SHIFT INT32_C(26)
+#define	ZULUVM_IMR_MAX		INT32_C(0x3f)
+
+#define	ZULUVM_ZFB_MMU_TLB_D_V_MASK	  0x8000000000000000
+#define	ZULUVM_ZFB_MMU_TLB_D_PA_SHIFT	  0xD	/* 13 bits */
+#define	ZULUVM_ZFB_MMU_TLB_D_C_MASK	  0x20
+#define	ZULUVM_ZFB_MMU_TLB_D_SZ_SHIFT	  0x3D	/* 61 */
+#define	ZULUVM_ZFB_MMU_TLB_D_SZ_MASK	  0x6000000000000000
+#define	ZULUVM_ZFB_MMU_TLB_D_W_MASK	  0x2
+#define	ZULUVM_ZFB_MMU_TLB_CR_IMISS_MASK  0x2
+#define	ZULUVM_ZFB_MMU_TLB_CR_DMISS_MASK  0x1
+#define	ZULUVM_ZFB_MMU_DTLB_PAGE_SZ_2_MASK  0xc /* DTLB2 Page size */
+#define	ZULUVM_ZFB_MMU_DTLB_PAGE_SZ_2_SHIFT 2
+#define	ZULUVM_DTLB_PAGE_SZ	0x8
+#define	ZULUVM_ITLB_DATA_IN	0x18
+#define	ZULUVM_DTLB_DATA_IN	0x28
+#define	ZULUVM_TLB_CONTROL	0
+#define	ZULUVM_ITLB_MISS_ICR	0x0
+#define	ZULUVM_DTLB_MISS_ICR	0x8
+#define	ZULUVM_DMA1_TSB_BASE	0x50
+#define	ZULUVM_DMA2_TSB_BASE	0x68
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* __ZULUMOD_INCL__ */
diff --git a/usr/src/uts/sun4u/sys/zuluvm.h b/usr/src/uts/sun4u/sys/zuluvm.h
new file mode 100644
index 0000000000..d36a63b9bc
--- /dev/null
+++ b/usr/src/uts/sun4u/sys/zuluvm.h
@@ -0,0 +1,121 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License, Version 1.0 only
+ * (the "License").  You may not use this file except in compliance
+ * with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright 2003 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	__ZULUVM_INCL__
+#define	__ZULUVM_INCL__
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* zulud interface */
+
+#ifndef _ASM
+
+#include <sys/dditypes.h>
+
+typedef struct {
+	caddr_t	addr;
+	size_t  len;
+	int	tlbtype;
+} zulud_preload_t;
+
+typedef struct {
+	int version;
+	int (*set_itlb_pc)(void *handle, uint64_t mondo);
+	int (*set_dtlb_pc)(void *handle, uint64_t mondo);
+	int (*set_suspendAck_pc)(void *handle, uint64_t mondo);
+	int (*write_tte)(void *handle, int ttesize, uint64_t tag,
+	    pfn_t pfn, int permission, int tlbtype);
+	int (*tlb_done)(void *handle, int tlbtype, int status);
+	int (*demap_page)(void *handle, caddr_t vaddr, short ctx);
+	int (*demap_ctx)(void *handle, short ctx);
+	int (*dma_suspend_ack)(void *handle);
+	int (*set_tsb)(void *handle, int tlbtype, uint64_t tsbreg);
+} zulud_ops_t;
+
+#endif
+
+#define	ZULUVM_SUCCESS		0
+#define	ZULUVM_ERROR		1
+#define	ZULUVM_NO_TTE		2
+#define	ZULUVM_INVALID_MISS	3
+#define	ZULUVM_NO_DEV		4
+#define	ZULUVM_NO_HAT		5
+#define	ZULUVM_NO_MAP		6
+#define	ZULUVM_VERSION_MISMATCH	7
+#define	ZULUVM_TTE_DELAY	8
+#define	ZULUVM_MISS_CANCELED	9
+#define	ZULUVM_BAD_IDX		10
+#define	ZULUVM_WATCH_POINT	11
+#define	ZULUVM_NO_SUPPORT	12
+#define	ZULUVM_CTX_LOCKED	13
+
+#define	ZULUVM_ITLB_FLAG	0x1
+#define	ZULUVM_DMA_FLAG		0x2
+#define	ZULUVM_DMA_MASK		0x3
+
+#define	ZULUVM_DMA1	0
+#define	ZULUVM_DMA2	ZULUVM_DMA_FLAG
+#define	ZULUVM_ITLB1	ZULUVM_ITLB_FLAG
+#define	ZULUVM_ITLB2	(ZULUVM_ITLB_FLAG | ZULUVM_DMA_FLAG)
+#define	ZULUVM_INVAL	0x4
+
+#ifndef _ASM
+
+/* zuluvm interface */
+
+#define	ZULUVM_INTERFACE_VERSION	1 /* inc with every intf change */
+
+typedef void * zuluvm_info_t;
+int zuluvm_init(zulud_ops_t *ops, int **pagesizes);
+int zuluvm_fini(void);
+int zuluvm_alloc_device(dev_info_t *devi, void *arg, zuluvm_info_t *devp,
+    caddr_t mmu, caddr_t imr);
+int zuluvm_free_device(zuluvm_info_t devp);
+int zuluvm_dma_add_proc(zuluvm_info_t devp, uint64_t *cookie);
+int zuluvm_dma_delete_proc(zuluvm_info_t devp, uint64_t cookie);
+int zuluvm_dma_alloc_ctx(zuluvm_info_t devp, int dma, short *ctx,
+    uint64_t *tsb);
+int zuluvm_dma_preload(zuluvm_info_t devp, int dma, int num,
+    zulud_preload_t *list);
+int zuluvm_dma_free_ctx(zuluvm_info_t devp, int dma);
+int zuluvm_add_intr(zuluvm_info_t devp, int ino, uint_t (*handler)(caddr_t),
+    caddr_t arg);
+int zuluvm_rem_intr(zuluvm_info_t devp, int ino);
+int zuluvm_enable_intr(zuluvm_info_t devp, int num);
+int zuluvm_disable_intr(zuluvm_info_t devp, int num);
+int zuluvm_park(zuluvm_info_t devp);
+
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* __ZULUVM_INCL__ */
author	stevel@tonic-gate <none@none>	2005-06-14 00:00:00 -0700
committer	stevel@tonic-gate <none@none>	2005-06-14 00:00:00 -0700
commit	7c478bd95313f5f23a4c958a745db2134aa03244 (patch)
tree	c871e58545497667cbb4b0a4f2daf204743e1fe7 /usr/src/uts/sun4u/sys
download	illumos-joyent-7c478bd95313f5f23a4c958a745db2134aa03244.tar.gz