PSARC/2008/181 Solaris Hotplug Framework

6837240 Solaris Hotplug Framework
6783012 Add support for PCIe Alternate Routing-ID Interpretation
6638136 remove obsolete ndi_ra_xxx logic from px_msi code
6695081 Race condition between pciehpc_intr() and pciehpc_init()

--HG--
rename : usr/src/uts/common/io/hotplug/pciehpc/pciehpc.c => usr/src/uts/common/io/pciex/hotplug/pciehpc.c
rename : usr/src/uts/common/io/hotplug/pcishpc/pcishpc.c => usr/src/uts/common/io/pciex/hotplug/pcishpc.c
rename : usr/src/uts/intel/io/hotplug/pciehpc/pciehpc_acpi.c => usr/src/uts/intel/io/pciex/hotplug/pciehpc_acpi.c
rename : usr/src/uts/intel/io/hotplug/pciehpc/pciehpc_acpi.h => usr/src/uts/intel/sys/hotplug/pci/pciehpc_acpi.h
rename : usr/src/uts/sparc/pcicfg.e/Makefile => usr/src/uts/sparc/pcicfg/Makefile
rename : usr/src/uts/sun4/io/pcicfg.e.c => usr/src/uts/sun4/io/pcicfg.c

11 files changed, 192 insertions, 183 deletions

diff --git a/usr/src/uts/sun4u/io/pci/pci.c b/usr/src/uts/sun4u/io/pci/pci.c
index 40efc968e2..30787b7fcd 100644
--- a/usr/src/uts/sun4u/io/pci/pci.c
+++ b/usr/src/uts/sun4u/io/pci/pci.c
@@ -23,7 +23,6 @@
  * Use is subject to license terms.
  */
 
-
 /*
  * PCI nexus driver interface
  */
@@ -124,9 +123,9 @@ static struct dev_ops pci_ops = {
 extern struct mod_ops mod_driverops;
 
 static struct modldrv modldrv = {
-	&mod_driverops, 	/* Type of module - driver */
-	"PCI Bus nexus driver",	/* Name of module. */
-	&pci_ops,		/* driver ops */
+	&mod_driverops, 			/* Type of module - driver */
+	"Sun4u Host to PCI nexus driver",	/* Name of module. */
+	&pci_ops,				/* driver ops */
 };
 
 static struct modlinkage modlinkage = {
@@ -296,7 +295,6 @@ pci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
 		pci_p->pci_dip = dip;
 		mutex_init(&pci_p->pci_mutex, NULL, MUTEX_DRIVER, NULL);
 		pci_p->pci_soft_state = PCI_SOFT_STATE_CLOSED;
-		pci_p->pci_open_count = 0;
 
 		/*
 		 * Get key properties of the pci bridge node and
diff --git a/usr/src/uts/sun4u/io/pci/pci_devctl.c b/usr/src/uts/sun4u/io/pci/pci_devctl.c
index 4bd413f06f..2872b8c24f 100644
--- a/usr/src/uts/sun4u/io/pci/pci_devctl.c
+++ b/usr/src/uts/sun4u/io/pci/pci_devctl.c
@@ -19,12 +19,10 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * PCI nexus HotPlug devctl interface
  */
@@ -130,7 +128,6 @@ pci_open(dev_t *devp, int flags, int otyp, cred_t *credp)
 		}
 	}
 
-	pci_p->pci_open_count++;
 	mutex_exit(&pci_p->pci_mutex);
 
 	return (0);
@@ -161,7 +158,6 @@ pci_close(dev_t dev, int flags, int otyp, cred_t *credp)
 		}
 
 	pci_p->pci_soft_state = PCI_SOFT_STATE_CLOSED;
-	pci_p->pci_open_count = 0;
 	mutex_exit(&pci_p->pci_mutex);
 	return (0);
 }
diff --git a/usr/src/uts/sun4u/io/pci/pci_pci.c b/usr/src/uts/sun4u/io/pci/pci_pci.c
index 9b1799feec..d2d4718fa1 100644
--- a/usr/src/uts/sun4u/io/pci/pci_pci.c
+++ b/usr/src/uts/sun4u/io/pci/pci_pci.c
@@ -23,7 +23,6 @@
  * Use is subject to license terms.
  */
 
-
 /*
  *	Sun4u PCI to PCI bus bridge nexus driver
  */
@@ -35,7 +34,7 @@
 #include <sys/autoconf.h>
 #include <sys/ddi_impldefs.h>
 #include <sys/ddi_subrdefs.h>
-#include <sys/pcie.h>
+#include <sys/pci_impl.h>
 #include <sys/pcie_impl.h>
 #include <sys/pci_cap.h>
 #include <sys/pci/pci_nexus.h>
@@ -47,6 +46,7 @@
 #include <sys/ddifm.h>
 #include <sys/pci/pci_pwr.h>
 #include <sys/pci/pci_debug.h>
+#include <sys/hotplug/pci/pcie_hp.h>
 #include <sys/hotplug/pci/pcihp.h>
 #include <sys/open.h>
 #include <sys/stat.h>
@@ -130,7 +130,8 @@ struct bus_ops ppb_bus_ops = {
 	ppb_bus_enter,			/* (*bus_enter)()		*/
 	ppb_bus_exit,			/* (*bus_exit)()		*/
 	ppb_bus_power,			/* (*bus_power)()		*/
-	ppb_intr_ops			/* (*bus_intr_op)(); 		*/
+	ppb_intr_ops,			/* (*bus_intr_op)(); 		*/
+	pcie_hp_common_ops		/* (*bus_hp_op)(); 		*/
 };
 
 static int ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp);
@@ -164,7 +165,7 @@ static struct cb_ops ppb_cb_ops = {
 static int ppb_probe(dev_info_t *);
 static int ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd);
 static int ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
-static int ppb_info(dev_info_t *dip, ddi_info_cmd_t infocmd,
+static int ppb_info(dev_info_t *dip, ddi_info_cmd_t cmd,
     void *arg, void **result);
 static int ppb_pwr(dev_info_t *dip, int component, int level);
 
@@ -238,9 +239,6 @@ typedef struct {
 
 	kmutex_t ppb_mutex;
 	uint_t ppb_soft_state;
-#define	PPB_SOFT_STATE_CLOSED		0x00
-#define	PPB_SOFT_STATE_OPEN		0x01
-#define	PPB_SOFT_STATE_OPEN_EXCL	0x02
 	int fm_cap;
 	ddi_iblock_cookie_t fm_ibc;
 
@@ -328,16 +326,18 @@ _info(struct modinfo *modinfop)
 
 /*ARGSUSED*/
 static int
-ppb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
+ppb_info(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result)
 {
-	ppb_devstate_t *ppb_p;	/* per ppb state pointer */
 	minor_t		minor = getminor((dev_t)arg);
-	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
-
-	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
+	int		instance = PCI_MINOR_NUM_TO_INSTANCE(minor);
+	ppb_devstate_t	*ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
 	    instance);
 
-	switch (infocmd) {
+
+	if (ppb_p->parent_bus != PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
+		return (pcihp_info(dip, cmd, arg, result));
+
+	switch (cmd) {
 	default:
 		return (DDI_FAILURE);
 
@@ -364,9 +364,12 @@ ppb_probe(register dev_info_t *devi)
 static int
 ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
 {
+	dev_info_t *root = ddi_root_node();
 	int instance;
 	ppb_devstate_t *ppb;
+	dev_info_t *pdip;
 	ddi_acc_handle_t config_handle;
+	char *bus;
 
 	switch (cmd) {
 	case DDI_ATTACH:
@@ -386,7 +389,7 @@ ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
 		ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, instance);
 		ppb->dip = devi;
 		mutex_init(&ppb->ppb_mutex, NULL, MUTEX_DRIVER, NULL);
-		ppb->ppb_soft_state = PPB_SOFT_STATE_CLOSED;
+		ppb->ppb_soft_state = PCI_SOFT_STATE_CLOSED;
 		if (pci_config_setup(devi, &config_handle) != DDI_SUCCESS) {
 			mutex_destroy(&ppb->ppb_mutex);
 			ddi_soft_state_free(ppb_state, instance);
@@ -435,30 +438,32 @@ ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);
 		}
 
+		ppb->parent_bus = PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO;
+		for (pdip = ddi_get_parent(ppb->dip); pdip && (pdip != root) &&
+		    (ppb->parent_bus != PCIE_PCIECAP_DEV_TYPE_PCIE_DEV);
+		    pdip = ddi_get_parent(pdip)) {
+			if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip,
+			    DDI_PROP_DONTPASS, "device_type", &bus) !=
+			    DDI_PROP_SUCCESS)
+				break;
+
+			if (strcmp(bus, "pciex") == 0)
+				ppb->parent_bus =
+				    PCIE_PCIECAP_DEV_TYPE_PCIE_DEV;
+
+			ddi_prop_free(bus);
+		}
+
 		/*
-		 * Initialize hotplug support on this bus. At minimum
-		 * (for non hotplug bus) this would create ":devctl" minor
-		 * node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls
-		 * to this bus. This all takes place if this nexus has hot-plug
-		 * slots and successfully initializes Hot Plug Framework.
+		 * Initialize hotplug support on this bus.
 		 */
-		ppb->hotplug_capable = B_FALSE;
-		ppb_init_hotplug(ppb);
-		if (ppb->hotplug_capable == B_FALSE) {
-			/*
-			 * create minor node for devctl interfaces
-			 */
-			if (ddi_create_minor_node(devi, "devctl", S_IFCHR,
-			    PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR),
-			    DDI_NT_NEXUS, 0) != DDI_SUCCESS) {
-				if (ppb->ppb_pwr_p != NULL) {
-					ppb_pwr_teardown(ppb, devi);
-				}
-				mutex_destroy(&ppb->ppb_mutex);
-				ddi_soft_state_free(ppb_state, instance);
+		if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
+			if (pcie_init(devi, NULL) != DDI_SUCCESS) {
+				(void) ppb_detach(devi, DDI_DETACH);
 				return (DDI_FAILURE);
 			}
-		}
+		else
+			ppb_init_hotplug(ppb);
 
 		DEBUG1(DBG_ATTACH, devi,
 		    "ppb_attach(): this nexus %s hotplug slots\n",
@@ -488,6 +493,7 @@ static int
 ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
 {
 	ppb_devstate_t *ppb;
+	int		ret = DDI_SUCCESS;
 
 	switch (cmd) {
 	case DDI_DETACH:
@@ -500,12 +506,16 @@ ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
 
 		ppb_fm_fini(ppb);
 
-		if (ppb->hotplug_capable == B_TRUE)
-			if (pcihp_uninit(devi) == DDI_FAILURE)
-				return (DDI_FAILURE);
+		if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
+			ret = pcie_uninit(devi);
+		else if (ppb->hotplug_capable == B_TRUE)
+			ret = pcihp_init(devi);
 		else
 			ddi_remove_minor_node(devi, "devctl");
 
+		if (ret != DDI_SUCCESS)
+			return (DDI_FAILURE);
+
 		(void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type");
 
 		if (ppb->ppb_pwr_p != NULL) {
@@ -1428,6 +1438,8 @@ ppb_pwr(dev_info_t *dip, int component, int lvl)
 static void
 ppb_init_hotplug(ppb_devstate_t *ppb)
 {
+	ppb->hotplug_capable = B_FALSE;
+
 	if (ddi_prop_exists(DDI_DEV_T_ANY, ppb->dip, DDI_PROP_DONTPASS,
 	    "hotplug-capable")) {
 		(void) modload("misc", "pcihp");
@@ -1441,6 +1453,18 @@ ppb_init_hotplug(ppb_devstate_t *ppb)
 			ppb->hotplug_capable = B_TRUE;
 	}
 
+	if (ppb->hotplug_capable == B_FALSE) {
+		/*
+		 * create minor node for devctl interfaces
+		 */
+		if (ddi_create_minor_node(ppb->dip, "devctl", S_IFCHR,
+		    PCI_MINOR_NUM(ddi_get_instance(ppb->dip), PCI_DEVCTL_MINOR),
+		    DDI_NT_NEXUS, 0) != DDI_SUCCESS)
+			cmn_err(CE_WARN,
+			    "%s #%d: Failed to create a minor node",
+			    ddi_driver_name(ppb->dip),
+			    ddi_get_instance(ppb->dip));
+	}
 }
 
 static void
@@ -1516,9 +1540,8 @@ ppb_create_ranges_prop(dev_info_t *dip,
 static int
 ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp)
 {
-	ppb_devstate_t *ppb_p;
-	minor_t		minor = getminor(*devp);
-	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
+	int		instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(*devp));
+	ppb_devstate_t	*ppb_p = ddi_get_soft_state(ppb_state, instance);
 
 	/*
 	 * Make sure the open is for the right file type.
@@ -1526,35 +1549,44 @@ ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp)
 	if (otyp != OTYP_CHR)
 		return (EINVAL);
 
+	if (ppb_p == NULL)
+		return (ENXIO);
+
+	mutex_enter(&ppb_p->ppb_mutex);
+
 	/*
-	 * Get the soft state structure for the device.
+	 * Ioctls will be handled by SPARC PCI Express framework for all
+	 * PCIe platforms
 	 */
-	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
-	    instance);
+	if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) {
+		int	rv;
 
-	if (ppb_p == NULL)
-		return (ENXIO);
+		rv = pcie_open(ppb_p->dip, devp, flags, otyp, credp);
+		mutex_exit(&ppb_p->ppb_mutex);
+
+		return (rv);
+	} else if (ppb_p->hotplug_capable == B_TRUE) {
+		mutex_exit(&ppb_p->ppb_mutex);
 
-	if (ppb_p->hotplug_capable == B_TRUE)
-		return ((pcihp_get_cb_ops())->cb_open(devp, flags,
-		    otyp, credp));
+		return ((pcihp_get_cb_ops())->cb_open(devp, flags, otyp,
+		    credp));
+	}
 
 	/*
 	 * Handle the open by tracking the device state.
 	 */
-	mutex_enter(&ppb_p->ppb_mutex);
 	if (flags & FEXCL) {
-		if (ppb_p->ppb_soft_state != PPB_SOFT_STATE_CLOSED) {
+		if (ppb_p->ppb_soft_state != PCI_SOFT_STATE_CLOSED) {
 			mutex_exit(&ppb_p->ppb_mutex);
 			return (EBUSY);
 		}
-		ppb_p->ppb_soft_state = PPB_SOFT_STATE_OPEN_EXCL;
+		ppb_p->ppb_soft_state = PCI_SOFT_STATE_OPEN_EXCL;
 	} else {
-		if (ppb_p->ppb_soft_state == PPB_SOFT_STATE_OPEN_EXCL) {
+		if (ppb_p->ppb_soft_state == PCI_SOFT_STATE_OPEN_EXCL) {
 			mutex_exit(&ppb_p->ppb_mutex);
 			return (EBUSY);
 		}
-		ppb_p->ppb_soft_state = PPB_SOFT_STATE_OPEN;
+		ppb_p->ppb_soft_state = PCI_SOFT_STATE_OPEN;
 	}
 	mutex_exit(&ppb_p->ppb_mutex);
 	return (0);
@@ -1565,25 +1597,34 @@ ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp)
 static int
 ppb_close(dev_t dev, int flags, int otyp, cred_t *credp)
 {
-	ppb_devstate_t *ppb_p;
-	minor_t		minor = getminor(dev);
-	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
+	int		instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev));
+	ppb_devstate_t	*ppb_p = ddi_get_soft_state(ppb_state, instance);
 
 	if (otyp != OTYP_CHR)
 		return (EINVAL);
 
-	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
-	    instance);
-
 	if (ppb_p == NULL)
 		return (ENXIO);
 
-	if (ppb_p->hotplug_capable == B_TRUE)
-		return ((pcihp_get_cb_ops())->cb_close(dev, flags,
-		    otyp, credp));
-
 	mutex_enter(&ppb_p->ppb_mutex);
-	ppb_p->ppb_soft_state = PPB_SOFT_STATE_CLOSED;
+	/*
+	 * Ioctls will be handled by SPARC PCI Express framework for all
+	 * PCIe platforms
+	 */
+	if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) {
+		int	rv;
+
+		rv = pcie_close(ppb_p->dip, dev, flags, otyp, credp);
+		mutex_exit(&ppb_p->ppb_mutex);
+
+		return (rv);
+	} else if (ppb_p->hotplug_capable == B_TRUE) {
+		mutex_exit(&ppb_p->ppb_mutex);
+		return ((pcihp_get_cb_ops())->cb_close(dev, flags, otyp,
+		    credp));
+	}
+
+	ppb_p->ppb_soft_state = PCI_SOFT_STATE_CLOSED;
 	mutex_exit(&ppb_p->ppb_mutex);
 	return (0);
 }
@@ -1597,23 +1638,26 @@ static int
 ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
 	int *rvalp)
 {
-	ppb_devstate_t *ppb_p;
-	dev_info_t *self;
+	int		instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev));
+	ppb_devstate_t	*ppb_p = ddi_get_soft_state(ppb_state, instance);
 	struct devctl_iocdata *dcp;
-	uint_t bus_state;
-	int rv = 0;
-	minor_t		minor = getminor(dev);
-	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
-
-	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
-	    instance);
+	uint_t		bus_state;
+	dev_info_t	*self;
+	int		rv = 0;
 
 	if (ppb_p == NULL)
 		return (ENXIO);
 
-	if (ppb_p->hotplug_capable == B_TRUE)
-		return ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd,
-		    arg, mode, credp, rvalp));
+	/*
+	 * Ioctls will be handled by SPARC PCI Express framework for all
+	 * PCIe platforms
+	 */
+	if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
+		return (pcie_ioctl(ppb_p->dip, dev, cmd, arg, mode, credp,
+		    rvalp));
+	else if (ppb_p->hotplug_capable == B_TRUE)
+		return ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd, arg, mode,
+		    credp, rvalp));
 
 	self = ppb_p->dip;
 
@@ -1670,24 +1714,23 @@ ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
 	return (rv);
 }
 
-static int ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
-    int flags, char *name, caddr_t valuep, int *lengthp)
+static int
+ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, int flags,
+    char *name, caddr_t valuep, int *lengthp)
 {
-	ppb_devstate_t *ppb_p;
-	minor_t		minor = getminor(dev);
-	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
-
-	ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
-	    instance);
+	int		instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev));
+	ppb_devstate_t	*ppb_p = (ppb_devstate_t *)
+	    ddi_get_soft_state(ppb_state, instance);
 
 	if (ppb_p == NULL)
 		return (ENXIO);
 
-	if (ppb_p->hotplug_capable == B_TRUE)
-		return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip, prop_op,
-		    flags, name, valuep, lengthp));
+	if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
+		return (pcie_prop_op(dev, dip, prop_op, flags, name,
+		    valuep, lengthp));
 
-	return (ddi_prop_op(dev, dip, prop_op, flags, name, valuep, lengthp));
+	return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip, prop_op, flags,
+	    name, valuep, lengthp));
 }
 
 /*
@@ -1696,10 +1739,6 @@ static int ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
 static void
 ppb_fm_init(ppb_devstate_t *ppb_p)
 {
-	dev_info_t *root = ddi_root_node();
-	dev_info_t *pdip;
-	char *bus;
-
 	ppb_p->fm_cap = DDI_FM_EREPORT_CAPABLE | DDI_FM_ERRCB_CAPABLE |
 	    DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE;
 
@@ -1717,21 +1756,6 @@ ppb_fm_init(ppb_devstate_t *ppb_p)
 	 * Register error callback with our parent.
 	 */
 	ddi_fm_handler_register(ppb_p->dip, ppb_err_callback, NULL);
-
-	ppb_p->parent_bus = PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO;
-	for (pdip = ddi_get_parent(ppb_p->dip); pdip && (pdip != root) &&
-	    (ppb_p->parent_bus != PCIE_PCIECAP_DEV_TYPE_PCIE_DEV);
-	    pdip = ddi_get_parent(pdip)) {
-		if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip,
-		    DDI_PROP_DONTPASS, "device_type", &bus) !=
-		    DDI_PROP_SUCCESS)
-			break;
-
-		if (strcmp(bus, "pciex") == 0)
-			ppb_p->parent_bus = PCIE_PCIECAP_DEV_TYPE_PCIE_DEV;
-
-		ddi_prop_free(bus);
-	}
 }
 
 /*
diff --git a/usr/src/uts/sun4u/io/px/oberon_regs.h b/usr/src/uts/sun4u/io/px/oberon_regs.h
index 29fed72c4d..7c2597d22b 100644
--- a/usr/src/uts/sun4u/io/px/oberon_regs.h
+++ b/usr/src/uts/sun4u/io/px/oberon_regs.h
@@ -19,15 +19,13 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
 #ifndef _SYS_OBERON_REGS_H
 #define	_SYS_OBERON_REGS_H
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -226,7 +224,6 @@ extern "C" {
 #define	DRAIN_CONTROL_STATUS					0x51100
 #define	DRAIN_CONTROL_STATUS_DRAIN				0
 
-#define	PX_PCIEHP_PIL (LOCK_LEVEL - 1)
 #ifdef	__cplusplus
 }
 #endif
diff --git a/usr/src/uts/sun4u/io/px/px_hlib.c b/usr/src/uts/sun4u/io/px/px_hlib.c
index a98657031c..732c7a5a5a 100644
--- a/usr/src/uts/sun4u/io/px/px_hlib.c
+++ b/usr/src/uts/sun4u/io/px/px_hlib.c
@@ -29,9 +29,8 @@
 #include <sys/vmem.h>
 #include <sys/machsystm.h>	/* lddphys() */
 #include <sys/iommutsb.h>
-#include <sys/pci.h>
-#include <sys/hotplug/pci/pciehpc.h>
 #include <px_obj.h>
+#include <sys/hotplug/pci/pcie_hp.h>
 #include "px_regs.h"
 #include "oberon_regs.h"
 #include "px_csr.h"
@@ -1389,6 +1388,7 @@ lpu_init(caddr_t csr_base, pxu_t *pxu_p)
 	    LPU_LTSSM_CONFIG4_DATA_RATE) |
 	    (LPU_LTSSM_CONFIG4_N_FTS_DEFAULT <<
 	    LPU_LTSSM_CONFIG4_N_FTS));
+
 	CSR_XS(csr_base, LPU_LTSSM_CONFIG4, val);
 	DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG4: 0x%llx\n",
 	    CSR_XR(csr_base, LPU_LTSSM_CONFIG4));
@@ -1734,7 +1734,8 @@ hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p)
 	 * Write the most significant 30 bits of the TSB physical address
 	 * and the encoded TSB table size.
 	 */
-	for (i = 8; i && (pxu_p->tsb_size < (0x2000 << i)); i--) {}
+	for (i = 8; i && (pxu_p->tsb_size < (0x2000 << i)); i--)
+		;
 
 	val = (((((va_to_pa(pxu_p->tsb_vaddr)) >> 13) << 13) |
 	    ((MMU_PAGE_SHIFT == 13) ? 0 : 1) << 8) | i);
@@ -2128,7 +2129,6 @@ uint64_t
 hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p, sysino_t sysino,
     cpuid_t cpuid)
 {
-
 	uint64_t	val, intr_controller;
 	uint32_t	ino = SYSINO_TO_DEVINO(sysino);
 
@@ -2162,8 +2162,7 @@ hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p, sysino_t sysino,
 	}
 
 	/* For EQ interrupts, set DATA MONDO bit */
-	if ((ino >= PX_DEFAULT_MSIQ_1ST_DEVINO) &&
-	    (ino < (PX_DEFAULT_MSIQ_1ST_DEVINO + PX_DEFAULT_MSIQ_CNT)))
+	if ((ino >= EQ_1ST_DEVINO) && (ino < (EQ_1ST_DEVINO + EQ_CNT)))
 		val |= (0x1ull << INTERRUPT_MAPPING_ENTRIES_MDO_MODE);
 
 	CSRA_XS((caddr_t)dev_hdl, INTERRUPT_MAPPING, ino, val);
@@ -3093,17 +3092,19 @@ oberon_hp_pwron(caddr_t csr_base)
 			delay(drv_usectohz(link_status_check));
 			reg = CSR_XR(csr_base, DLU_LINK_LAYER_STATUS);
 
-		    if ((((reg >> DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS) &
-			DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_MASK) ==
-			DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_FC_INIT_DONE) &&
-			(reg & (1ull << DLU_LINK_LAYER_STATUS_DLUP_STS)) &&
-			((reg & DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_MASK)
-			==
-			DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_DL_ACTIVE)) {
-			DBG(DBG_HP, NULL, "oberon_hp_pwron : link is up\n");
-				link_up = B_TRUE;
-		    } else
+		if ((((reg >> DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS) &
+		    DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_MASK) ==
+		    DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_FC_INIT_DONE) &&
+		    (reg & (1ull << DLU_LINK_LAYER_STATUS_DLUP_STS)) &&
+		    ((reg &
+		    DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_MASK) ==
+		    DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_DL_ACTIVE)) {
+			DBG(DBG_HP, NULL, "oberon_hp_pwron : "
+			    "link is up\n");
+			link_up = B_TRUE;
+		} else
 			link_retry = B_TRUE;
+
 		}
 		/* END CSTYLED */
 	}
@@ -3382,7 +3383,7 @@ oberon_hpreg_put(void *cookie, off_t off, uint_t val)
 int
 hvio_hotplug_init(dev_info_t *dip, void *arg)
 {
-	pciehpc_regops_t *regops = (pciehpc_regops_t *)arg;
+	pcie_hp_regops_t *regops = (pcie_hp_regops_t *)arg;
 	px_t	*px_p = DIP_TO_STATE(dip);
 	pxu_t	*pxu_p = (pxu_t *)px_p->px_plat_p;
 	volatile uint64_t reg;
diff --git a/usr/src/uts/sun4u/io/px/px_lib4u.c b/usr/src/uts/sun4u/io/px/px_lib4u.c
index a8c655d8e2..0a588ebe6e 100644
--- a/usr/src/uts/sun4u/io/px/px_lib4u.c
+++ b/usr/src/uts/sun4u/io/px/px_lib4u.c
@@ -40,7 +40,6 @@
 #include <sys/cpuvar.h>
 #include <sys/ivintr.h>
 #include <sys/byteorder.h>
-#include <sys/hotplug/pci/pciehpc.h>
 #include <sys/spl.h>
 #include <px_obj.h>
 #include <sys/pcie_pwr.h>
@@ -51,6 +50,7 @@
 #include "px_lib4u.h"
 #include "px_err.h"
 #include "oberon_regs.h"
+#include <sys/hotplug/pci/pcie_hp.h>
 
 #pragma weak jbus_stst_order
 
@@ -1495,7 +1495,7 @@ px_lib_clr_errs(px_t *px_p, dev_info_t *rdip, uint64_t addr)
 	int		rc_err, fab_err, i;
 	int		acctype = pec_p->pec_safeacc_type;
 	ddi_fm_error_t	derr;
-	px_ranges_t	*ranges_p;
+	pci_ranges_t	*ranges_p;
 	int		range_len;
 	uint32_t	addr_high, addr_low;
 	pcie_req_id_t	bdf = PCIE_INVALID_BDF;
@@ -1520,7 +1520,7 @@ px_lib_clr_errs(px_t *px_p, dev_info_t *rdip, uint64_t addr)
 	/* Figure out if this is a cfg or mem32 access */
 	addr_high = (uint32_t)(addr >> 32);
 	addr_low = (uint32_t)addr;
-	range_len = px_p->px_ranges_length / sizeof (px_ranges_t);
+	range_len = px_p->px_ranges_length / sizeof (pci_ranges_t);
 	i = 0;
 	for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) {
 		if (ranges_p->parent_high == addr_high) {
@@ -2350,7 +2350,7 @@ px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status)
 uint32_t
 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset)
 {
-	px_ranges_t	*rp = px_p->px_ranges_p;
+	pci_ranges_t	*rp = px_p->px_ranges_p;
 	uint64_t	range_prop, base_addr;
 	int		bank = PCI_REG_ADDR_G(PCI_ADDR_CONFIG);
 	uint32_t	val;
@@ -2369,7 +2369,7 @@ px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset)
 void
 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset,
     uint32_t val) {
-	px_ranges_t	*rp = px_p->px_ranges_p;
+	pci_ranges_t	*rp = px_p->px_ranges_p;
 	uint64_t	range_prop, base_addr;
 	int		bank = PCI_REG_ADDR_G(PCI_ADDR_CONFIG);
 
@@ -2509,7 +2509,7 @@ px_get_rng_parent_hi_mask(px_t *px_p)
  * fetch chip's range propery's value
  */
 uint64_t
-px_get_range_prop(px_t *px_p, px_ranges_t *rp, int bank)
+px_get_range_prop(px_t *px_p, pci_ranges_t *rp, int bank)
 {
 	uint64_t mask, range_prop;
 
@@ -2543,11 +2543,11 @@ px_cpr_rem_callb(px_t *px_p)
 static uint_t
 px_hp_intr(caddr_t arg1, caddr_t arg2)
 {
-	px_t	*px_p = (px_t *)arg1;
-	pxu_t 	*pxu_p = (pxu_t *)px_p->px_plat_p;
-	int	rval;
+	px_t		*px_p = (px_t *)arg1;
+	pxu_t		*pxu_p = (pxu_t *)px_p->px_plat_p;
+	int		rval;
 
-	rval = pciehpc_intr(px_p->px_dip);
+	rval = pcie_intr(px_p->px_dip);
 
 #ifdef  DEBUG
 	if (rval == DDI_INTR_UNCLAIMED)
@@ -2571,6 +2571,10 @@ px_lib_hotplug_init(dev_info_t *dip, void *arg)
 	pxu_t 	*pxu_p = (pxu_t *)px_p->px_plat_p;
 	uint64_t ret;
 
+	if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
+	    "hotplug-capable") == 0)
+		return (DDI_FAILURE);
+
 	if ((ret = hvio_hotplug_init(dip, arg)) == DDI_SUCCESS) {
 		if (px_lib_intr_devino_to_sysino(px_p->px_dip,
 		    px_p->px_inos[PX_INTR_HOTPLUG], &pxu_p->hp_sysino) !=
@@ -2583,7 +2587,7 @@ px_lib_hotplug_init(dev_info_t *dip, void *arg)
 			return (DDI_FAILURE);
 		}
 
-		VERIFY(add_ivintr(pxu_p->hp_sysino, PX_PCIEHP_PIL,
+		VERIFY(add_ivintr(pxu_p->hp_sysino, PCIE_INTR_PRI,
 		    (intrfunc)px_hp_intr, (caddr_t)px_p, NULL, NULL) == 0);
 
 		px_ib_intr_enable(px_p, intr_dist_cpuid(),
@@ -2603,7 +2607,7 @@ px_lib_hotplug_uninit(dev_info_t *dip)
 		px_ib_intr_disable(px_p->px_ib_p,
 		    px_p->px_inos[PX_INTR_HOTPLUG], IB_INTR_WAIT);
 
-		VERIFY(rem_ivintr(pxu_p->hp_sysino, PX_PCIEHP_PIL) == 0);
+		VERIFY(rem_ivintr(pxu_p->hp_sysino, PCIE_INTR_PRI) == 0);
 	}
 }
 
@@ -2613,7 +2617,9 @@ px_lib_hotplug_uninit(dev_info_t *dip)
 void
 px_hp_intr_redist(px_t *px_p)
 {
-	if (px_p && (px_p->px_dev_caps & PX_HOTPLUG_CAPABLE)) {
+	pcie_bus_t	*bus_p = PCIE_DIP2BUS(px_p->px_dip);
+
+	if (px_p && PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p)) {
 		px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(),
 		    px_p->px_inos[PX_INTR_HOTPLUG], B_FALSE);
 	}
diff --git a/usr/src/uts/sun4u/io/px/px_lib4u.h b/usr/src/uts/sun4u/io/px/px_lib4u.h
index e2b8bbbbf1..45c15ea65d 100644
--- a/usr/src/uts/sun4u/io/px/px_lib4u.h
+++ b/usr/src/uts/sun4u/io/px/px_lib4u.h
@@ -26,7 +26,6 @@
 #ifndef _SYS_PX_LIB4U_H
 #define	_SYS_PX_LIB4U_H
 
-
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -153,6 +152,14 @@ typedef	struct eq_rec {
 #define	EQ_ACTIVE_STATE	0x2			/* ACTIVE */
 #define	EQ_ERROR_STATE	0x4			/* ERROR */
 
+/*
+ * Default EQ Configurations
+ */
+#define	EQ_CNT		36
+#define	EQ_REC_CNT	128
+#define	EQ_1ST_ID	0
+#define	EQ_1ST_DEVINO	24
+
 #define	MMU_INVALID_TTE		0ull
 #define	MMU_TTE_VALID(tte)	(((tte) & MMU_TTE_V) == MMU_TTE_V)
 #define	MMU_OBERON_PADDR_MASK	0x7fffffffffff
@@ -324,7 +331,7 @@ extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, pxu_t *pxu_p,
     r_addr_t ra, io_attributes_t attr, io_addr_t *io_addr_p);
 extern uint64_t hvio_get_bypass_base(pxu_t *pxu_p);
 extern uint64_t hvio_get_bypass_end(pxu_t *pxu_p);
-extern uint64_t px_get_range_prop(px_t *px_p, px_ranges_t *rp, int bank);
+extern uint64_t px_get_range_prop(px_t *px_p, pci_ranges_t *rp, int bank);
 
 
 /*
diff --git a/usr/src/uts/sun4u/px/Makefile b/usr/src/uts/sun4u/px/Makefile
index 27bcdd2b1a..c14d4a2f29 100644
--- a/usr/src/uts/sun4u/px/Makefile
+++ b/usr/src/uts/sun4u/px/Makefile
@@ -21,11 +21,9 @@
 #
 # uts/sun4u/px/Makefile
 #
-# Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+# Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 # Use is subject to license terms.
 #
-#ident	"%Z%%M%	%I%	%E% SMI"
-#
 #	This makefile drives the production of the pci driver kernel module
 #
 #	sun4u implementation architecture dependent
@@ -87,7 +85,7 @@ LINTTAGS	+= -erroff=E_ASSIGN_NARROW_CONV
 #
 #	Dependency
 #
-LDFLAGS += -dy -Nmisc/busra -Nmisc/pcie -Nmisc/pcihp -Nmisc/pciehpc
+LDFLAGS += -dy -Nmisc/pcie
 
 #
 #	Default build targets.
diff --git a/usr/src/uts/sun4u/sys/pci/pci_obj.h b/usr/src/uts/sun4u/sys/pci/pci_obj.h
index 358ccd132d..d71c4942ab 100644
--- a/usr/src/uts/sun4u/sys/pci/pci_obj.h
+++ b/usr/src/uts/sun4u/sys/pci/pci_obj.h
@@ -2,9 +2,8 @@
  * CDDL HEADER START
  *
  * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License").  You may not use this file except in compliance
- * with the License.
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
  *
  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  * or http://www.opensolaris.org/os/licensing.
@@ -20,20 +19,19 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
 #ifndef	_SYS_PCI_OBJ_H
 #define	_SYS_PCI_OBJ_H
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #ifdef	__cplusplus
 extern "C" {
 #endif
 
 #include <sys/pci.h>
+#include <sys/pci_impl.h>
 #include <sys/pci_intr_lib.h>
 #include <sys/pci/pci_nexus.h>
 #include <sys/pci/pci_types.h>
diff --git a/usr/src/uts/sun4u/sys/pci/pci_tools_ext.h b/usr/src/uts/sun4u/sys/pci/pci_tools_ext.h
index 74be3a6dd0..8658013f7b 100644
--- a/usr/src/uts/sun4u/sys/pci/pci_tools_ext.h
+++ b/usr/src/uts/sun4u/sys/pci/pci_tools_ext.h
@@ -2,9 +2,8 @@
  * CDDL HEADER START
  *
  * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License").  You may not use this file except in compliance
- * with the License.
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
  *
  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  * or http://www.opensolaris.org/os/licensing.
@@ -20,15 +19,13 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
 #ifndef _SYS_PCI_TOOLS_EXT_H
 #define	_SYS_PCI_TOOLS_EXT_H
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -36,13 +33,6 @@ extern "C" {
 /* This file contains pcitool defs exported to other modules of a PCI driver. */
 
 /*
- * Minor numbers for dedicated pcitool nodes.
- * Note that FF and FE minor numbers are used for other minor nodes.
- */
-#define	PCI_TOOL_REG_MINOR_NUM	0xFD
-#define	PCI_TOOL_INTR_MINOR_NUM	0xFC
-
-/*
  * Functions exported from the pci_tools.c module.
  */
 extern int pcitool_dev_reg_ops(dev_t dev, void *arg, int cmd, int mode);
diff --git a/usr/src/uts/sun4u/sys/pci/pci_var.h b/usr/src/uts/sun4u/sys/pci/pci_var.h
index 53d12a538e..fb43a92061 100644
--- a/usr/src/uts/sun4u/sys/pci/pci_var.h
+++ b/usr/src/uts/sun4u/sys/pci/pci_var.h
@@ -19,15 +19,13 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
 #ifndef _SYS_PCI_VAR_H
 #define	_SYS_PCI_VAR_H
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -126,10 +124,6 @@ struct pci {
 	 */
 	pci_state_t pci_state;
 	uint_t pci_soft_state;
-#define	PCI_SOFT_STATE_OPEN		0x01
-#define	PCI_SOFT_STATE_OPEN_EXCL	0x02
-#define	PCI_SOFT_STATE_CLOSED		0x04
-	uint_t pci_open_count;
 	uint16_t pci_tsb_cookie;	/* IOMMU TSB allocation */
 	kmutex_t pci_mutex;