6900487 bad unknown trap at TL 1

2 files changed, 16 insertions, 21 deletions

diff --git a/usr/src/uts/sun4u/opl/io/oplpanel/oplpanel.c b/usr/src/uts/sun4u/opl/io/oplpanel/oplpanel.c
index 6e443c4c82..d42cb990c8 100644
--- a/usr/src/uts/sun4u/opl/io/oplpanel/oplpanel.c
+++ b/usr/src/uts/sun4u/opl/io/oplpanel/oplpanel.c
@@ -24,8 +24,7 @@
  */
 
 /*
- * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
- * Use is subject to license terms.
+ * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
  */
 
 
@@ -375,26 +374,9 @@ panel_intr(caddr_t arg)
 	(void) ddi_get8(statep->panel_regs_handle, statep->panelregs);
 
 	if (panel_enable) {
-		uint_t pstate_save;
-
 		/* avoid double panic */
 		panel_enable 	= 0;
 
-		/*
-		 * Re-enqueue the cpc interrupt handler for PIL15 here since we
-		 * are not unwinding back to the interrupt handler subsystem.
-		 * This is to allow potential cpc overflow interrupts to
-		 * function while we go thru the panic flow. Note that this
-		 * logic could be implemented in panic_enter_hw(), we do
-		 * it here for now as it is less risky. This particular
-		 * condition is only specific to OPL hardware and we want
-		 * to minimize exposure of this new logic to other existing
-		 * platforms.
-		 */
-		pstate_save = disable_vec_intr();
-		intr_enqueue_req(PIL_15, cpc_level15_inum);
-		enable_vec_intr(pstate_save);
-
 		cmn_err(CE_PANIC,
 		    "System Panel Driver: Emergency panic request "
 		    "detected!");
diff --git a/usr/src/uts/sun4u/os/mach_cpu_states.c b/usr/src/uts/sun4u/os/mach_cpu_states.c
index 684e8d607e..449d187f37 100644
--- a/usr/src/uts/sun4u/os/mach_cpu_states.c
+++ b/usr/src/uts/sun4u/os/mach_cpu_states.c
@@ -19,7 +19,8 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
+ *
  * Use is subject to license terms.
  */
 
@@ -49,6 +50,7 @@ u_longlong_t panic_tick;
 extern u_longlong_t	gettick();
 static void reboot_machine(char *);
 int disable_watchdog_on_exit = 0;
+extern uint64_t		cpc_level15_inum;
 
 /*
  * Machine dependent code to reboot.
@@ -272,12 +274,18 @@ panic_stopcpus(cpu_t *cp, kthread_t *t, int spl)
  * was made and so we re-enqueue an interrupt request structure to allow
  * further level 14 interrupts to be processed once we lower PIL.  This allows
  * us to handle panics from the deadman() CY_HIGH_LEVEL cyclic.
+ *
+ * In case we panic at level 15, ensure that the cpc handler has been
+ * reinstalled otherwise we could run the risk of hitting a missing interrupt
+ * handler when this thread drops PIL and the cpc counter overflows.
  */
 void
 panic_enter_hw(int spl)
 {
+	uint_t opstate;
+
 	if (spl == ipltospl(PIL_14)) {
-		uint_t opstate = disable_vec_intr();
+		opstate = disable_vec_intr();
 
 		if (curthread->t_panic_trap != NULL) {
 			tickcmpr_disable();
@@ -295,6 +303,11 @@ panic_enter_hw(int spl)
 		}
 
 		enable_vec_intr(opstate);
+	} else if (spl == ipltospl(PIL_15)) {
+		opstate = disable_vec_intr();
+		intr_enqueue_req(PIL_15, cpc_level15_inum);
+		wr_clr_softint(1 << PIL_15);
+		enable_vec_intr(opstate);
 	}
 }