13687 want tool for PCIe device, config space display

Reviewed by: Andy Fiddaman <andy@omnios.org>
Reviewed by: Ryan Zezeski <ryan@oxide.computer>
Approved by: Dan McDonald <danmcd@joyent.com>

3 files changed, 42 insertions, 6 deletions

diff --git a/usr/src/uts/common/io/pciex/pcie.c b/usr/src/uts/common/io/pciex/pcie.c
index 35a0190be7..df6b2d189b 100644
--- a/usr/src/uts/common/io/pciex/pcie.c
+++ b/usr/src/uts/common/io/pciex/pcie.c
@@ -22,6 +22,7 @@
 /*
  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
  * Copyright 2019 Joyent, Inc.
+ * Copyright 2021 Oxide Computer Company
  */
 
 #include <sys/sysmacros.h>
@@ -1189,11 +1190,18 @@ pcie_capture_speeds(dev_info_t *dip)
 	uint16_t	vers, status;
 	uint32_t	cap, cap2, ctl2;
 	pcie_bus_t	*bus_p = PCIE_DIP2BUS(dip);
+	dev_info_t	*rcdip;
 
 	if (!PCIE_IS_PCIE(bus_p))
 		return;
 
-	vers = PCIE_CAP_GET(16, bus_p, PCIE_PCIECAP);
+	rcdip = pcie_get_rc_dip(dip);
+	if (bus_p->bus_cfg_hdl == NULL) {
+		vers = pci_cfgacc_get16(rcdip, bus_p->bus_bdf,
+		    bus_p->bus_pcie_off + PCIE_PCIECAP);
+	} else {
+		vers = PCIE_CAP_GET(16, bus_p, PCIE_PCIECAP);
+	}
 	if (vers == PCI_EINVAL16)
 		return;
 	vers &= PCIE_PCIECAP_VER_MASK;
@@ -1207,10 +1215,17 @@ pcie_capture_speeds(dev_info_t *dip)
 		ctl2 = 0;
 		break;
 	case PCIE_PCIECAP_VER_2_0:
-		cap2 = PCIE_CAP_GET(32, bus_p, PCIE_LINKCAP2);
+		if (bus_p->bus_cfg_hdl == NULL) {
+			cap2 = pci_cfgacc_get32(rcdip, bus_p->bus_bdf,
+			    bus_p->bus_pcie_off + PCIE_LINKCAP2);
+			ctl2 = pci_cfgacc_get16(rcdip, bus_p->bus_bdf,
+			    bus_p->bus_pcie_off + PCIE_LINKCTL2);
+		} else {
+			cap2 = PCIE_CAP_GET(32, bus_p, PCIE_LINKCAP2);
+			ctl2 = PCIE_CAP_GET(16, bus_p, PCIE_LINKCTL2);
+		}
 		if (cap2 == PCI_EINVAL32)
 			cap2 = 0;
-		ctl2 = PCIE_CAP_GET(16, bus_p, PCIE_LINKCTL2);
 		if (ctl2 == PCI_EINVAL16)
 			ctl2 = 0;
 		break;
@@ -1219,8 +1234,15 @@ pcie_capture_speeds(dev_info_t *dip)
 		return;
 	}
 
-	status = PCIE_CAP_GET(16, bus_p, PCIE_LINKSTS);
-	cap = PCIE_CAP_GET(32, bus_p, PCIE_LINKCAP);
+	if (bus_p->bus_cfg_hdl == NULL) {
+		status = pci_cfgacc_get16(rcdip, bus_p->bus_bdf,
+		    bus_p->bus_pcie_off + PCIE_LINKSTS);
+		cap = pci_cfgacc_get32(rcdip, bus_p->bus_bdf,
+		    bus_p->bus_pcie_off + PCIE_LINKCAP);
+	} else {
+		status = PCIE_CAP_GET(16, bus_p, PCIE_LINKSTS);
+		cap = PCIE_CAP_GET(32, bus_p, PCIE_LINKCAP);
+	}
 	if (status == PCI_EINVAL16 || cap == PCI_EINVAL32)
 		return;
 
@@ -1659,6 +1681,8 @@ initial_done:
 
 	pcie_init_plat(dip);
 
+	pcie_capture_speeds(dip);
+
 final_done:
 
 	PCIE_DBG("Add %s(dip 0x%p, bdf 0x%x, secbus 0x%x)\n",
diff --git a/usr/src/uts/common/sys/pci.h b/usr/src/uts/common/sys/pci.h
index d62d19c3a5..5dd6762ab5 100644
--- a/usr/src/uts/common/sys/pci.h
+++ b/usr/src/uts/common/sys/pci.h
@@ -621,6 +621,8 @@ extern "C" {
 #define	PCI_CAP_ID_MSI_X	0x11	/* MSI-X supported */
 #define	PCI_CAP_ID_SATA		0x12	/* SATA Data/Index Config supported */
 #define	PCI_CAP_ID_FLR		0x13	/* Function Level Reset supported */
+#define	PCI_CAP_ID_EA		0x14	/* Enhanced Allocation */
+#define	PCI_CAP_ID_FPB		0x15	/* Flattening Portal Bridge */
 
 /*
  * Capability next entry pointer values
@@ -909,13 +911,16 @@ typedef struct pcix_attr {
 #define	PCI_MSI_CTRL		0x02	/* MSI control register, 2 bytes */
 #define	PCI_MSI_ADDR_OFFSET	0x04	/* MSI 32-bit msg address, 4 bytes */
 #define	PCI_MSI_32BIT_DATA	0x08	/* MSI 32-bit msg data, 2 bytes */
+#define	PCI_MSI_32BIT_EXTDATA	0x0A	/* MSI 32-bit msg ext data, 2 bytes */
 #define	PCI_MSI_32BIT_MASK	0x0C	/* MSI 32-bit mask bits, 4 bytes */
 #define	PCI_MSI_32BIT_PENDING	0x10	/* MSI 32-bit pending bits, 4 bytes */
 
 /*
  * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit
  */
+#define	PCI_MSI_64BIT_ADDR	0x08	/* MSI 64-bit upper address, 4 bytes */
 #define	PCI_MSI_64BIT_DATA	0x0C	/* MSI 64-bit msg data, 2 bytes */
+#define	PCI_MSI_64BIT_EXTDATA	0x0E	/* MSI 64-bit msg ext data, 2 bytes */
 #define	PCI_MSI_64BIT_MASKBITS	0x10	/* MSI 64-bit mask bits, 4 bytes */
 #define	PCI_MSI_64BIT_PENDING	0x14	/* MSI 64-bit pending bits, 4 bytes */
 
diff --git a/usr/src/uts/common/sys/pcie.h b/usr/src/uts/common/sys/pcie.h
index e8f91a1390..840c31a328 100644
--- a/usr/src/uts/common/sys/pcie.h
+++ b/usr/src/uts/common/sys/pcie.h
@@ -536,6 +536,7 @@ extern "C" {
 #define	PCIE_EXT_CAP_NEXT_PTR_MASK	0xFFF
 
 #define	PCIE_EXT_CAP_NEXT_PTR_NULL	0x0
+#define	PCIE_EXT_CAP_MAX_PTR		0x3c0	/* max. number of caps */
 
 /*
  * PCI-Express Enhanced Capability Identifier Values
@@ -559,6 +560,7 @@ extern "C" {
 #define	PCIE_EXT_CAP_ID_SRIOV		0x10	/* Single Root I/O Virt. */
 #define	PCIE_EXT_CAP_ID_MRIOV		0x11	/* Multi Root I/O Virt. */
 #define	PCIE_EXT_CAP_ID_MULTICAST	0x12	/* Multicast Services */
+#define	PCIE_EXT_CAP_ID_PGREQ		0x13	/* Page Request */
 #define	PCIE_EXT_CAP_ID_EA		0x14	/* Enhanced Allocation */
 #define	PCIE_EXT_CAP_ID_RESIZE_BAR	0x15	/* Resizable BAR */
 #define	PCIE_EXT_CAP_ID_DPA		0x16	/* Dynamic Power Allocation */
@@ -573,11 +575,15 @@ extern "C" {
 #define	PCIE_EXT_CAP_ID_FRS		0x21	/* Function Ready Stat. Queue */
 #define	PCIE_EXT_CAP_ID_RTR		0x22	/* Readiness Time Reporting */
 #define	PCIE_EXT_CAP_ID_DVS		0x23	/* Designated Vendor-Specific */
+#define	PCIE_EXT_CAP_ID_VFRBAR		0x24	/* VF Resizable BAR */
 #define	PCIE_EXT_CAP_ID_DLF		0x25	/* Data Link Feature */
-#define	PCIE_EXT_CAP_ID_PL16GTE		0x26	/* Physical Layer 16.0 GT/s */
+#define	PCIE_EXT_CAP_ID_PL16GT		0x26	/* Physical Layer 16.0 GT/s */
 #define	PCIE_EXT_CAP_ID_LANE_MARGIN	0x27	/* Lane Margining */
 #define	PCIE_EXT_CAP_ID_HIEARCHY_ID	0x28	/* Hierarchy ID */
 #define	PCIE_EXT_CAP_ID_NPEM		0x29	/* Native PCIe Enclosure Mgmt */
+#define	PCIE_EXT_CAP_ID_PL32GT		0x2A	/* Physical Layer 32.0 GT/s */
+#define	PCIE_EXT_CAP_ID_AP		0x2B	/* Alternate Protocol */
+#define	PCIE_EXT_CAP_ID_SFI		0x2C	/* Sys. Firmware Intermediary */
 
 /*
  * PCI-Express Advanced Error Reporting Extended Capability Offsets
@@ -596,6 +602,7 @@ extern "C" {
 #define	PCIE_AER_RE_STS			0x30	/* Root Error Status */
 #define	PCIE_AER_CE_SRC_ID		0x34	/* Error Source ID */
 #define	PCIE_AER_ERR_SRC_ID		0x36	/* Error Source ID */
+#define	PCIE_AER_TLP_PRE_LOG		0x38	/* TLP Prefix Log */
 
 /* Bridges Only */
 #define	PCIE_AER_SUCE_STS		0x2c	/* Secondary UCE Status */