6486288 x64: create pcie(7d) module for PCIe error handling

6486415 time for pci.h and pcie.h to catch up with PCI SIG ID changes ..

15 files changed, 261 insertions, 84 deletions

diff --git a/usr/src/common/pci/pci_strings.c b/usr/src/common/pci/pci_strings.c
index 805f999e21..42501f5e05 100644
--- a/usr/src/common/pci/pci_strings.c
+++ b/usr/src/common/pci/pci_strings.c
@@ -2,9 +2,8 @@
  * CDDL HEADER START
  *
  * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License").  You may not use this file except in compliance
- * with the License.
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
  *
  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  * or http://www.opensolaris.org/os/licensing.
@@ -21,7 +20,7 @@
  */
 
 /*
- * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
@@ -43,6 +42,10 @@ const pci_class_strings_t class_pci[] = {
 	1, 5, 0x20,	"ATA controller with single DMA",	"ata",
 	1, 5, 0x30,	"ATA controller with chained DMA",	"ata",
 	1, 6, 0,	"Serial ATA Direct Port Access (DPA)",	"sata",
+	1, 6, 1,	"SATA AHCI 1.0 Interface",		"sata",
+	1, 6, 2,	"Serial Storage Bus Interface",		"sata",
+	1, 7, 0,	"Serial Attached SCSI Controller",	"sas",
+	1, 7, 1,	"Serial Storage Bus Interface",		"sas",
 	1, 0x80, 0,	"Mass storage controller",		"unknown",
 
 	2, 0, 0,	"Ethernet controller",			"etherne",
@@ -63,6 +66,7 @@ const pci_class_strings_t class_pci[] = {
 	4, 0, 0,	"Video device",				"video",
 	4, 1, 0,	"Audio device",				"audio",
 	4, 2, 0,	"Computer Telephony device",		"teleph",
+	4, 3, 0,	"Mixed Mode device",			"mixed",
 	4, 0x80, 0,	"Multimedia device",			"unknown",
 
 	5, 0, 0,	"Ram",					"ram",
@@ -83,6 +87,8 @@ const pci_class_strings_t class_pci[] = {
 	6, 9, 0x40,	"Semi-transparent PCI-PCI primary bridge",   "stpci",
 	6, 9, 0x80,	"Semi-transparent PCI-PCI secondary bridge", "stpci",
 	6, 0xA, 0,	"Infiniband-PCI bridge",		"ib-pci",
+	6, 0xB, 0,	"AS Custom Interface bridge",		"as-pci",
+	6, 0xB, 1,	"ASI-SIG Defined Portal Interface",	"as-pci",
 	6, 0x80, 0,	"Bridge device",			"unknown",
 
 	7, 0, 0,	"Serial controller",			"serial",
@@ -118,9 +124,12 @@ const pci_class_strings_t class_pci[] = {
 	8, 2, 0,	"8254 system timer",			"timer",
 	8, 2, 1,	"ISA system timer",			"timer",
 	8, 2, 2,	"EISA system timers",			"timer",
+	8, 2, 3,	"High Performance Event timer",		"timer",
 	8, 3, 0,	"Real time clock",			"rtc",
 	8, 3, 1,	"ISA real time clock",			"rtc",
 	8, 4, 0,	"PCI Hot-Plug controller",		"pcihp",
+	8, 5, 0,	"SD Host controller",			"sd-hc",
+	8, 6, 0,	"IOMMU controller",			"iommu",
 	8, 0x80, 0,	"System peripheral",			"unknown",
 
 	9, 0, 0,	"Keyboard controller",			"keyboar",
@@ -128,7 +137,7 @@ const pci_class_strings_t class_pci[] = {
 	9, 2, 0,	"Mouse controller",			"mouse",
 	9, 3, 0,	"Scanner controller",			"scanner",
 	9, 4, 0,	"Gameport controller",			"gamepor",
-	9, 4, 1,	"Gameport Legacy controller",		"gamepor",
+	9, 4, 0x10,	"Gameport Legacy controller",		"gamepor",
 	9, 0x80, 0,	"Input controller",			"unknown",
 
 	10, 0, 0,	"Generic Docking station",		"docking",
@@ -141,6 +150,7 @@ const pci_class_strings_t class_pci[] = {
 	11, 0x20, 0,	"Power-PC",				"powerpc",
 	11, 0x30, 0,	"MIPS",					"mips",
 	11, 0x40, 0,	"Co-processor",				"coproc",
+	11, 0x80, 0,	"Processor",				"unknown",
 
 	12, 0, 0,	"FireWire (IEEE 1394)",			"1394",
 	12, 0, 0x10,	"FireWire (IEEE 1394) OpenHCI compliant", "1394",
@@ -159,9 +169,11 @@ const pci_class_strings_t class_pci[] = {
 	12, 7, 2,	"IPMI Block Transfer Interface",	"ipmi",
 	12, 8, 0,	"SERCOS Interface Standard",		"sercos",
 	12, 9, 0,	"CANbus",				"canbus",
+	12, 0x80, 0,	"Serial Bus Controller",		"unknown",
 
 	13, 0, 0,	"IRDA Wireless controller",		"irda",
 	13, 1, 0,	"Consumer IR Wireless controller",	"ir",
+	13, 1, 0x10,	"UWB Radio  controller",		"ir-uwb",
 	13, 0x10, 0,	"RF Wireless controller",		"rf",
 	13, 0x11, 0,	"Bluetooth Wireless controller",	"btooth",
 	13, 0x12, 0,	"Broadband Wireless controller",	"brdband",
@@ -170,11 +182,13 @@ const pci_class_strings_t class_pci[] = {
 	13, 0x80, 0,	"Wireless controller",			"unknown",
 
 	14, 0, 0,	"I20 controller",			"i2o",
+	14, 0, 1,	"I20 Arch Specification 1.0",		"i2o",
 
 	15, 1, 0,	"TV Satellite controller",		"tv",
 	15, 2, 0,	"Audio Satellite controller",		"audio",
 	15, 3, 0,	"Voice Satellite controller",		"voice",
 	15, 4, 0,	"Data Satellite controller",		"data",
+	15, 0x80, 0,	"Satellite Comm controller",		"unknown",
 
 	16, 0, 0,	"Network and computing en/decryption",	"netcryp",
 	16, 1, 0,	"Entertainment en/decryption",		"entcryp",
diff --git a/usr/src/pkgdefs/SUNWcakr.i/prototype_com b/usr/src/pkgdefs/SUNWcakr.i/prototype_com
index 0ac50cb7ca..2f83aab47d 100644
--- a/usr/src/pkgdefs/SUNWcakr.i/prototype_com
+++ b/usr/src/pkgdefs/SUNWcakr.i/prototype_com
@@ -108,10 +108,12 @@ f none platform/i86pc/kernel/misc/amd64/agpmaster 755 root sys
 f none platform/i86pc/kernel/misc/amd64/bootdev 755 root sys
 f none platform/i86pc/kernel/misc/amd64/gfx_private 755 root sys
 f none platform/i86pc/kernel/misc/amd64/pci_autoconfig 755 root sys
+f none platform/i86pc/kernel/misc/amd64/pcie 755 root sys
 f none platform/i86pc/kernel/misc/amd64/pciehpc 755 root sys
 f none platform/i86pc/kernel/misc/agpmaster 755 root sys
 f none platform/i86pc/kernel/misc/bootdev 755 root sys
 f none platform/i86pc/kernel/misc/gfx_private 755 root sys
 f none platform/i86pc/kernel/misc/pci_autoconfig 755 root sys
 f none platform/i86pc/kernel/misc/pciehpc 755 root sys
+f none platform/i86pc/kernel/misc/pcie 755 root sys
 f none platform/i86pc/kernel/unix 755 root sys
diff --git a/usr/src/uts/common/sys/pci.h b/usr/src/uts/common/sys/pci.h
index 4bb48b00da..858fdfa164 100644
--- a/usr/src/uts/common/sys/pci.h
+++ b/usr/src/uts/common/sys/pci.h
@@ -221,11 +221,12 @@ extern "C" {
  */
 #define	PCI_MASS_SCSI		0x0	/* SCSI bus Controller */
 #define	PCI_MASS_IDE		0x1	/* IDE Controller */
-#define	PCI_MASS_FD		0x2	/* floppy disk Controller */
+#define	PCI_MASS_FD		0x2	/* Floppy disk Controller */
 #define	PCI_MASS_IPI		0x3	/* IPI bus Controller */
 #define	PCI_MASS_RAID		0x4	/* RAID Controller */
 #define	PCI_MASS_ATA		0x5	/* ATA Controller */
 #define	PCI_MASS_SATA		0x6	/* Serial ATA */
+#define	PCI_MASS_SAS		0x7	/* Serial Attached SCSI (SAS) Cntrlr */
 #define	PCI_MASS_OTHER		0x80	/* Other Mass Storage Controller */
 
 /*
@@ -245,6 +246,19 @@ extern "C" {
 #define	PCI_ATA_IF_CHAINED_DMA	0x30	/* ATA controller with chained DMA */
 
 /*
+ * programming interface for ATA (subclass 6) for SATA
+ */
+#define	PCI_SATA_VS_INTERFACE	0x0	/* SATA Ctlr Vendor Specific Intfc */
+#define	PCI_SATA_AHCI_INTERFACE	0x1	/* SATA Ctlr AHCI 1.0 Interface */
+#define	PCI_SATA_SSB_INTERFACE	0x2	/* Serial Storage Bus Interface */
+
+/*
+ * programming interface for ATA (subclass 7) for SAS
+ */
+#define	PCI_SAS_CONTROLLER	0x0	/* SAS Controller */
+#define	PCI_SAS_BUS_INTERFACE	0x1	/* Serial Storage Bus Interface */
+
+/*
  * PCI Sub-class codes - base class 0x2 (Network controllers)
  */
 #define	PCI_NET_ENET		0x0	/* Ethernet Controller */
@@ -276,6 +290,7 @@ extern "C" {
 #define	PCI_MM_VIDEO		0x0	/* Video device */
 #define	PCI_MM_AUDIO		0x1	/* Audio device */
 #define	PCI_MM_TELEPHONY	0x2	/* Computer Telephony device */
+#define	PCI_MM_MIXED_MODE	0x3	/* Mixed Mode device */
 #define	PCI_MM_OTHER		0x80	/* Other Multimedia Device */
 
 /*
@@ -299,6 +314,7 @@ extern "C" {
 #define	PCI_BRIDGE_RACE		0x8	/* RACE-way Bridge */
 #define	PCI_BRIDGE_STPCI	0x9	/* Semi-transparent PCI/PCI Bridge */
 #define	PCI_BRIDGE_IB		0xA	/* InfiniBand/PCI host Bridge */
+#define	PCI_BRIDGE_AS		0xB	/* AS/PCI host Bridge */
 #define	PCI_BRIDGE_OTHER	0x80	/* PCI/Other Bridge Device */
 
 /*
@@ -324,6 +340,12 @@ extern "C" {
 						/* facing system processor */
 
 /*
+ * programming interface for Bridges class 0x6 (subclass 0B) AS bridge
+ */
+#define	PCI_BRIDGE_AS_CUSTOM_INTFC	0x0	/* Custom interface */
+#define	PCI_BRIDGE_AS_PORTAL_INTFC	0x1	/* ASI-SIG Portal Interface */
+
+/*
  * PCI Sub-class codes - base class 0x7 (communication devices)
  */
 #define	PCI_COMM_GENERIC_XT	0x0	/* XT Compatible Serial Controller */
@@ -370,7 +392,9 @@ extern "C" {
 #define	PCI_PERIPH_DMA		0x1	/* Generic DMA Controller */
 #define	PCI_PERIPH_TIMER	0x2	/* Generic System Timer Controller */
 #define	PCI_PERIPH_RTC		0x3	/* Generic RTC Controller */
-#define	PCI_PERIPH_HPC		0x3	/* Generic PCI Hot-Plug Controller */
+#define	PCI_PERIPH_HPC		0x4	/* Generic PCI Hot-Plug Controller */
+#define	PCI_PERIPH_SD_HC	0x5	/* SD Host Controller */
+#define	PCI_PERIPH_IOMMU	0x6	/* IOMMU */
 #define	PCI_PERIPH_OTHER	0x80	/* Other System Peripheral */
 
 /*
@@ -395,6 +419,7 @@ extern "C" {
 #define	PCI_PERIPH_TIMER_IF_GENERIC	0x0	/* Generic 8254 system timer */
 #define	PCI_PERIPH_TIMER_IF_ISA		0x1	/* ISA system timers */
 #define	PCI_PERIPH_TIMER_IF_EISA	0x2	/* EISA system timers (two) */
+#define	PCI_PERIPH_TIMER_IF_HPET	0x3	/* High Perf Event timer */
 
 /*
  * Programming interfaces for class 0x8 / subclass 0x3 (realtime clock)
@@ -419,13 +444,13 @@ extern "C" {
 #define	PCI_INPUT_GAMEPORT_IF_LEGACY	0x10	/* Legacy controller */
 
 /*
- * PCI Sub-class codes - base class 0xa
+ * PCI Sub-class codes - base class 0xA
  */
 #define	PCI_DOCK_GENERIC	0x00	/* Generic Docking Station */
 #define	PCI_DOCK_OTHER		0x80	/* Other Type of Docking Station */
 
 /*
- * PCI Sub-class codes - base class 0xb
+ * PCI Sub-class codes - base class 0xB
  */
 #define	PCI_PROCESSOR_386	0x0	/* 386 */
 #define	PCI_PROCESSOR_486	0x1	/* 486 */
@@ -434,9 +459,10 @@ extern "C" {
 #define	PCI_PROCESSOR_POWERPC	0x20	/* PowerPC */
 #define	PCI_PROCESSOR_MIPS	0x30	/* MIPS */
 #define	PCI_PROCESSOR_COPROC	0x40	/* Co-processor */
+#define	PCI_PROCESSOR_OTHER	0x80	/* Other processors */
 
 /*
- * PCI Sub-class codes - base class 0xc (Serial Controllers)
+ * PCI Sub-class codes - base class 0xC (Serial Controllers)
  */
 #define	PCI_SERIAL_FIRE		0x0	/* FireWire (IEEE 1394) */
 #define	PCI_SERIAL_ACCESS	0x1	/* ACCESS.bus */
@@ -448,6 +474,13 @@ extern "C" {
 #define	PCI_SERIAL_IPMI		0x7	/* IPMI */
 #define	PCI_SERIAL_SERCOS	0x8	/* SERCOS Interface Std (IEC 61491) */
 #define	PCI_SERIAL_CANBUS	0x9	/* CANbus */
+#define	PCI_SERIAL_OTHER	0x80	/* Other Serial Bus Controllers */
+
+/*
+ * Programming interfaces for class 0xC / subclass 0x0 (Firewire)
+ */
+#define	PCI_SERIAL_FIRE_WIRE  		0x00	/* IEEE 1394 (Firewire) */
+#define	PCI_SERIAL_FIRE_1394_HCI 	0x10	/* 1394 OpenHCI Host Cntrlr */
 
 /*
  * Programming interfaces for class 0xC / subclass 0x3 (USB controller)
@@ -466,7 +499,7 @@ extern "C" {
 #define	PCI_SERIAL_IPMI_IF_BTI		0x2	/* Block Transfer Interface */
 
 /*
- * PCI Sub-class codes - base class 0xd (Wireless controllers)
+ * PCI Sub-class codes - base class 0xD (Wireless controllers)
  */
 #define	PCI_WIRELESS_IRDA		0x0	/* iRDA Compatible Controller */
 #define	PCI_WIRELESS_IR			0x1	/* Consumer IR Controller */
@@ -478,17 +511,25 @@ extern "C" {
 #define	PCI_WIRELESS_OTHER		0x80	/* Other Wireless Controllers */
 
 /*
- * PCI Sub-class codes - base class 0xe (Intelligent I/O controllers)
+ * Programming interfaces for class 0xD / subclass 0x1 (Consumer IR controller)
+ */
+#define	PCI_WIRELESS_IR_CONSUMER 	0x00	/* Consumer IR Controller */
+#define	PCI_WIRELESS_IR_UWB_RC 		0x10	/* UWB Radio Controller */
+
+/*
+ * PCI Sub-class codes - base class 0xE (Intelligent I/O controllers)
  */
+#define	PCI_INTIO_MSG_FIFO		0x0	/* Message FIFO at off 40h */
 #define	PCI_INTIO_I20			0x1	/* I20 Arch Spec 1.0 */
 
 /*
- * PCI Sub-class codes - base class 0xf (Satellite Communication controllers)
+ * PCI Sub-class codes - base class 0xF (Satellite Communication controllers)
  */
 #define	PCI_SATELLITE_COMM_TV		0x01	/* TV */
 #define	PCI_SATELLITE_COMM_AUDIO	0x02	/* Audio */
 #define	PCI_SATELLITE_COMM_VOICE	0x03	/* Voice */
 #define	PCI_SATELLITE_COMM_DATA		0x04	/* DATA */
+#define	PCI_SATELLITE_COMM_OTHER	0x80	/* Other Satelite Comm Cntrlr */
 
 /*
  * PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers)
@@ -562,10 +603,13 @@ extern "C" {
 #define	PCI_CAP_ID_DEBUG_PORT	0xA	/* Debug Port supported */
 #define	PCI_CAP_ID_cPCI_CRC	0xB	/* CompactPCI central resource ctrl */
 #define	PCI_CAP_ID_PCI_HOTPLUG	0xC	/* PCI Hot Plug supported */
+#define	PCI_CAP_ID_P2P_SUBSYS	0xD	/* PCI bridge Sub-system ID */
 #define	PCI_CAP_ID_AGP_8X	0xE	/* AGP 8X supported */
 #define	PCI_CAP_ID_SECURE_DEV	0xF	/* Secure Device supported */
 #define	PCI_CAP_ID_PCI_E	0x10	/* PCI Express supported */
 #define	PCI_CAP_ID_MSI_X	0x11	/* MSI-X supported */
+#define	PCI_CAP_ID_SATA		0x12	/* SATA Data/Index Config supported */
+#define	PCI_CAP_ID_FLR		0x13	/* Function Level Reset supported */
 
 /*
  * Capability next entry pointer values
diff --git a/usr/src/uts/common/sys/pcie.h b/usr/src/uts/common/sys/pcie.h
index c2c7652fa8..2818d86595 100644
--- a/usr/src/uts/common/sys/pcie.h
+++ b/usr/src/uts/common/sys/pcie.h
@@ -119,6 +119,8 @@ extern "C" {
 #define	PCIE_DEVCAP_ATTN_INDICATOR	0x2000	/* Attn Indicator Present */
 #define	PCIE_DEVCAP_PWR_INDICATOR	0x4000	/* Power Indicator Present */
 
+#define	PCIE_DEVCAP_ROLE_BASED_ERR_REP	0x8000	/* Role Based Error Reporting */
+
 #define	PCIE_DEVCAP_PLMT_VAL_SHIFT	18	/* Power Limit Value Shift */
 #define	PCIE_DEVCAP_PLMT_VAL_MASK	0xFF	/* Power Limit Value Mask */
 
@@ -363,9 +365,21 @@ extern "C" {
  * PCI-Express Enhanced Capability Identifier Values
  */
 #define	PCIE_EXT_CAP_ID_AER		0x1	/* Advanced Error Handling */
-#define	PCIE_EXT_CAP_ID_VC		0x2	/* Virtual Channel */
+#define	PCIE_EXT_CAP_ID_VC		0x2	/* Virtual Channel, no MFVC */
 #define	PCIE_EXT_CAP_ID_SER		0x3	/* Serial Number */
 #define	PCIE_EXT_CAP_ID_PWR_BUDGET	0x4	/* Power Budgeting */
+#define	PCIE_EXT_CAP_ID_RC_LINK_DECL	0x5	/* RC Link Declaration */
+#define	PCIE_EXT_CAP_ID_RC_INT_LINKCTRL	0x6	/* RC Internal Link Control */
+#define	PCIE_EXT_CAP_ID_RC_EVNT_CEA	0x7	/* RC Event Collector */
+						/* Endpoint Association */
+#define	PCIE_EXT_CAP_ID_MFVC		0x8	/* Multi-func Virtual Channel */
+#define	PCIE_EXT_CAP_ID_VC_WITH_MFVC	0x9	/* Virtual Channel w/ MFVC */
+#define	PCIE_EXT_CAP_ID_RCRB		0xA	/* Root Complex Register Blck */
+#define	PCIE_EXT_CAP_ID_VS		0xB	/* Vendor Spec Extended Cap */
+#define	PCIE_EXT_CAP_ID_CAC		0xC	/* Config Access Correlation */
+#define	PCIE_EXT_CAP_ID_ACS		0xD	/* Access Control Services */
+#define	PCIE_EXT_CAP_ID_ARI		0xE	/* Alternative Routing ID */
+#define	PCIE_EXT_CAP_ID_ATS		0xF	/* Address Translation Svcs */
 
 /*
  * PCI-Express Advanced Error Reporting Extended Capability Offsets
diff --git a/usr/src/uts/i86pc/Makefile.files b/usr/src/uts/i86pc/Makefile.files
index a82851d393..ebbb9934aa 100644
--- a/usr/src/uts/i86pc/Makefile.files
+++ b/usr/src/uts/i86pc/Makefile.files
@@ -149,10 +149,11 @@ MCAMD_OBJS	+= \
 #
 #	PCI-Express driver modules
 #
+PCI_E_MISC_OBJS += pcie_error.o
 PCI_E_NEXUS_OBJS += npe.o npe_misc.o 
-PCI_E_NEXUS_OBJS += pci_common.o pci_kstats.o pci_tools.o pcie_error.o
-PCI_E_PCINEXUS_OBJS += pcie_pci.o pcie_error.o
-PCIEHPCNEXUS_OBJS += pciehpc_x86.o pciehpc_acpi.o pciehpc_nvidia.o pcie_error.o
+PCI_E_NEXUS_OBJS += pci_common.o pci_kstats.o pci_tools.o
+PCI_E_PCINEXUS_OBJS += pcie_pci.o
+PCIEHPCNEXUS_OBJS += pciehpc_x86.o pciehpc_acpi.o pciehpc_nvidia.o
 
 #
 #	platform specific modules
diff --git a/usr/src/uts/i86pc/Makefile.i86pc.shared b/usr/src/uts/i86pc/Makefile.i86pc.shared
index b857ff1e62..aae56c8ea4 100644
--- a/usr/src/uts/i86pc/Makefile.i86pc.shared
+++ b/usr/src/uts/i86pc/Makefile.i86pc.shared
@@ -322,7 +322,7 @@ SYS_KMODS	+=
 #
 #	'Misc' Modules (/kernel/misc):
 #
-MISC_KMODS	+= pci_autoconfig bootdev acpica pciehpc gfx_private \
+MISC_KMODS	+= pci_autoconfig bootdev acpica pcie pciehpc gfx_private \
 		agpmaster drm
 
 #
diff --git a/usr/src/uts/i86pc/io/pciex/npe.c b/usr/src/uts/i86pc/io/pciex/npe.c
index f02490615f..80ff196f44 100644
--- a/usr/src/uts/i86pc/io/pciex/npe.c
+++ b/usr/src/uts/i86pc/io/pciex/npe.c
@@ -156,7 +156,7 @@ static int npe_initchild(dev_info_t *child);
  * External support routine
  */
 extern void	npe_query_acpi_mcfg(dev_info_t *dip);
-extern void	npe_ck804_fix_aer_ptr(dev_info_t *child);
+extern void	npe_ck804_fix_aer_ptr(ddi_acc_handle_t cfg_hdl);
 extern int	npe_disable_empty_bridges_workaround(dev_info_t *child);
 
 /*
@@ -685,7 +685,8 @@ npe_intr_ops(dev_info_t *pdip, dev_info_t *rdip, ddi_intr_op_t intr_op,
 static int
 npe_initchild(dev_info_t *child)
 {
-	char	name[80];
+	char			name[80];
+	ddi_acc_handle_t	cfg_hdl;
 
 	/*
 	 * Do not bind drivers to empty bridges.
@@ -760,11 +761,13 @@ npe_initchild(dev_info_t *child)
 		ddi_set_parent_data(child, NULL);
 
 	/*
-	 * Enable AER next pointer being displayed
+	 * Enable AER next pointer being displayed and PCIe Error initilization
 	 */
-	npe_ck804_fix_aer_ptr(child);
-
-	(void) pcie_error_init(child);
+	if (pci_config_setup(child, &cfg_hdl) == DDI_SUCCESS) {
+		npe_ck804_fix_aer_ptr(cfg_hdl);
+		(void) pcie_error_enable(child, cfg_hdl);
+		pci_config_teardown(&cfg_hdl);
+	}
 
 	return (DDI_SUCCESS);
 }
@@ -773,13 +776,17 @@ npe_initchild(dev_info_t *child)
 static int
 npe_removechild(dev_info_t *dip)
 {
-	struct ddi_parent_private_data *pdptr;
+	ddi_acc_handle_t		cfg_hdl;
+	struct ddi_parent_private_data	*pdptr;
 
 	/*
 	 * Do it way early.
 	 * Otherwise ddi_map() call form pcie_error_fini crashes
 	 */
-	pcie_error_fini(dip);
+	if (pci_config_setup(dip, &cfg_hdl) == DDI_SUCCESS) {
+		pcie_error_disable(dip, cfg_hdl);
+		pci_config_teardown(&cfg_hdl);
+	}
 
 	if ((pdptr = ddi_get_parent_data(dip)) != NULL) {
 		kmem_free(pdptr, (sizeof (*pdptr) + sizeof (struct intrspec)));
diff --git a/usr/src/uts/i86pc/io/pciex/npe_misc.c b/usr/src/uts/i86pc/io/pciex/npe_misc.c
index 8f5857936e..8ec68b3ea3 100644
--- a/usr/src/uts/i86pc/io/pciex/npe_misc.c
+++ b/usr/src/uts/i86pc/io/pciex/npe_misc.c
@@ -42,7 +42,7 @@
  * Prototype declaration
  */
 void	npe_query_acpi_mcfg(dev_info_t *dip);
-void	npe_ck804_fix_aer_ptr(dev_info_t *child);
+void	npe_ck804_fix_aer_ptr(ddi_acc_handle_t cfg_hdl);
 int	npe_disable_empty_bridges_workaround(dev_info_t *child);
 
 /*
@@ -101,28 +101,19 @@ npe_query_acpi_mcfg(dev_info_t *dip)
  * NOTE: BIOS is disabling this, it needs to be enabled temporarily
  */
 void
-npe_ck804_fix_aer_ptr(dev_info_t *child)
+npe_ck804_fix_aer_ptr(ddi_acc_handle_t cfg_hdl)
 {
-	ushort_t		cya1;
-	ddi_acc_handle_t	config_handle;
+	ushort_t cya1;
 
-	if (pci_config_setup(child, &config_handle) != DDI_SUCCESS)
+	if ((pci_config_get16(cfg_hdl, PCI_CONF_VENID) != NVIDIA_VENDOR_ID) &&
+	    (pci_config_get16(cfg_hdl, PCI_CONF_DEVID) !=
+	    NVIDIA_CK804_DEVICE_ID))
 		return;
 
-	if ((pci_config_get16(config_handle, PCI_CONF_VENID) !=
-	    NVIDIA_VENDOR_ID) && (pci_config_get16(config_handle,
-	    PCI_CONF_DEVID) != NVIDIA_CK804_DEVICE_ID)) {
-		pci_config_teardown(&config_handle);
-		return;
-	}
-
-	cya1 =  pci_config_get16(config_handle, NVIDIA_CK804_VEND_CYA1_OFF);
+	cya1 =  pci_config_get16(cfg_hdl, NVIDIA_CK804_VEND_CYA1_OFF);
 	if (!(cya1 & ~NVIDIA_CK804_VEND_CYA1_ERPT_MASK))
-		(void) pci_config_put16(config_handle,
-		    NVIDIA_CK804_VEND_CYA1_OFF,
+		(void) pci_config_put16(cfg_hdl, NVIDIA_CK804_VEND_CYA1_OFF,
 		    cya1 | NVIDIA_CK804_VEND_CYA1_ERPT_VAL);
-
-	pci_config_teardown(&config_handle);
 }
 
 
diff --git a/usr/src/uts/i86pc/io/pciex/pcie_error.c b/usr/src/uts/i86pc/io/pciex/pcie_error.c
index e7b1a5b5f1..139559ff95 100644
--- a/usr/src/uts/i86pc/io/pciex/pcie_error.c
+++ b/usr/src/uts/i86pc/io/pciex/pcie_error.c
@@ -36,9 +36,7 @@
 #include <sys/modctl.h>
 #include <sys/pci.h>
 #include <sys/pci_impl.h>
-#include <sys/sunddi.h>
 #include <sys/sunndi.h>
-#include <sys/sysmacros.h>
 #include <sys/pcie.h>
 #include <sys/pcie_impl.h>
 #include <sys/promif.h>
@@ -150,40 +148,41 @@ static void	pcie_nvidia_error_init(dev_info_t *, ddi_acc_handle_t,
 static void	pcie_nvidia_error_fini(ddi_acc_handle_t, uint16_t, uint16_t);
 
 /*
- * PCI-Express error initialization.
+ * modload support
  */
-int
-pcie_error_init(dev_info_t *cdip)
-{
-	ddi_acc_handle_t	cfg_hdl;
-	int status;
 
-	if (pci_config_setup(cdip, &cfg_hdl) != DDI_SUCCESS)
-		return (DDI_FAILURE);
+struct modlmisc modlmisc	= {
+	&mod_miscops,	/* Type	of module */
+	"PCI Express Error Support %I%"
+};
 
-	status = pcie_error_enable(cdip, cfg_hdl);
+struct modlinkage modlinkage = {
+	MODREV_1, (void	*)&modlmisc, NULL
+};
 
-	pci_config_teardown(&cfg_hdl);
-	return (status);
+int
+_init(void)
+{
+	return (mod_install(&modlinkage));
 }
 
-/*
- * PCI-Express CK8-04 child device de-initialization.
- */
-void
-pcie_error_fini(dev_info_t *cdip)
+int
+_fini()
 {
-	ddi_acc_handle_t	cfg_hdl;
-
-	if (pci_config_setup(cdip, &cfg_hdl) != DDI_SUCCESS)
-		return;
-
-	pcie_error_disable(cdip, cfg_hdl);
+	return (mod_remove(&modlinkage));
+}
 
-	pci_config_teardown(&cfg_hdl);
+int
+_info(struct modinfo *modinfop)
+{
+	return (mod_info(&modlinkage, modinfop));
 }
 
 /*
+ * PCI-Express error initialization.
+ */
+
+/*
  * Enable generic pci-express interrupts and error handling.
  */
 int
diff --git a/usr/src/uts/i86pc/io/pciex/pcie_error.h b/usr/src/uts/i86pc/io/pciex/pcie_error.h
index 16950f1453..b829525850 100644
--- a/usr/src/uts/i86pc/io/pciex/pcie_error.h
+++ b/usr/src/uts/i86pc/io/pciex/pcie_error.h
@@ -2,9 +2,8 @@
  * CDDL HEADER START
  *
  * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License").  You may not use this file except in compliance
- * with the License.
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
  *
  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  * or http://www.opensolaris.org/os/licensing.
@@ -21,7 +20,7 @@
  */
 
 /*
- * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
@@ -44,8 +43,6 @@ extern "C" {
  * Error related library functions
  */
 
-int		pcie_error_init(dev_info_t *cdip);
-void		pcie_error_fini(dev_info_t *cdip);
 int		pcie_error_enable(dev_info_t *cdip, ddi_acc_handle_t cfg_hdl);
 void		pcie_error_disable(dev_info_t *cdip, ddi_acc_handle_t cfg_hdl);
 
diff --git a/usr/src/uts/i86pc/io/pciex/pcie_pci.c b/usr/src/uts/i86pc/io/pciex/pcie_pci.c
index 7d7f0e2db7..fa3d22172f 100644
--- a/usr/src/uts/i86pc/io/pciex/pcie_pci.c
+++ b/usr/src/uts/i86pc/io/pciex/pcie_pci.c
@@ -621,6 +621,7 @@ static int
 pepb_initchild(dev_info_t *child)
 {
 	struct ddi_parent_private_data *pdptr;
+	ddi_acc_handle_t cfg_hdl;
 	char name[MAXNAMELEN];
 
 	if (pepb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS)
@@ -676,8 +677,10 @@ pepb_initchild(dev_info_t *child)
 	} else
 		ddi_set_parent_data(child, NULL);
 
-	if (pcie_error_init(child) != DDI_SUCCESS)
-		return (DDI_FAILURE);
+	if (pci_config_setup(child, &cfg_hdl) == DDI_SUCCESS) {
+		(void) pcie_error_enable(child, cfg_hdl);
+		pci_config_teardown(&cfg_hdl);
+	}
 
 	return (DDI_SUCCESS);
 }
@@ -685,13 +688,17 @@ pepb_initchild(dev_info_t *child)
 static void
 pepb_uninitchild(dev_info_t *dip)
 {
-	struct ddi_parent_private_data *pdptr;
+	ddi_acc_handle_t		cfg_hdl;
+	struct ddi_parent_private_data	*pdptr;
 
 	/*
 	 * Do it way early.
 	 * Otherwise ddi_map() call form pcie_error_fini crashes
 	 */
-	pcie_error_fini(dip);
+	if (pci_config_setup(dip, &cfg_hdl) == DDI_SUCCESS) {
+		pcie_error_disable(dip, cfg_hdl);
+		pci_config_teardown(&cfg_hdl);
+	}
 
 	if ((pdptr = ddi_get_parent_data(dip)) != NULL) {
 		kmem_free(pdptr, (sizeof (*pdptr) + sizeof (struct intrspec)));
diff --git a/usr/src/uts/i86pc/npe/Makefile b/usr/src/uts/i86pc/npe/Makefile
index 6c2f1aa131..ba35955760 100644
--- a/usr/src/uts/i86pc/npe/Makefile
+++ b/usr/src/uts/i86pc/npe/Makefile
@@ -20,6 +20,7 @@
 #
 #
 # uts/i86pc/npe/Makefile
+#
 # Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
 # Use is subject to license terms.
 #
@@ -56,14 +57,16 @@ LINT_TARGET	= $(MODULE).lint
 INSTALL_TARGET	= $(BINARY) $(ROOTMODULE)
 
 #
-# depends on misc/pcihp misc/acpica
+# depends on misc/pcihp, misc/acpica and misc/pcie
 #
 # For PCI Hotplug support, the misc/pcihp module provides devctl control
 # device and cb_ops functions to support hotplug operations.
 #
 # acpica supplies ACPI access routines
 #
-LDFLAGS	+= -dy -Nmisc/pcihp -Nmisc/acpica
+# pcie supplies PCI Express fabric error support
+#
+LDFLAGS	+= -dy -Nmisc/pcihp -Nmisc/acpica -Nmisc/pcie
 
 #
 # Name of the module is needed by the source, to distinguish from other
diff --git a/usr/src/uts/i86pc/pcie/Makefile b/usr/src/uts/i86pc/pcie/Makefile
new file mode 100644
index 0000000000..0359e61b0e
--- /dev/null
+++ b/usr/src/uts/i86pc/pcie/Makefile
@@ -0,0 +1,84 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+#
+# uts/i86pc/pcie/Makefile
+#
+# Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+# Use is subject to license terms.
+#
+#ident	"%Z%%M%	%I%	%E% SMI"
+#
+#	This makefile drives the production of the kernel/misc/pcie module
+#	for PCI-E Error handling support in PCI-E nexus drivers.
+#
+#	i86pc implementation architecture dependent
+#
+
+#
+#	Path to the base of the uts directory tree (usually /usr/src/uts).
+#
+UTSBASE	= ../..
+
+#
+#	Define the module and object file sets.
+#
+MODULE		= pcie
+OBJECTS		= $(PCI_E_MISC_OBJS:%=$(OBJS_DIR)/%)
+LINTS		= $(PCI_E_MISC_OBJS:%.o=$(LINTS_DIR)/%.ln)
+ROOTMODULE	= $(ROOT_PSM_MISC_DIR)/$(MODULE)
+
+#
+#	Include common rules.
+#
+include $(UTSBASE)/i86pc/Makefile.i86pc
+
+#
+#	Define targets
+#
+ALL_TARGET	= $(BINARY)
+LINT_TARGET	= $(MODULE).lint
+INSTALL_TARGET	= $(BINARY) $(ROOTMODULE)
+
+#
+#	Default build targets.
+#
+.KEEP_STATE:
+
+def:		$(DEF_DEPS)
+
+all:		$(ALL_DEPS)
+
+clean:		$(CLEAN_DEPS)
+
+clobber:	$(CLOBBER_DEPS)
+
+lint:		$(LINT_DEPS)
+
+modlintlib:	$(MODLINTLIB_DEPS)
+
+clean.lint:	$(CLEAN_LINT_DEPS)
+
+install:	$(INSTALL_DEPS)
+
+#
+#	Include common targets.
+#
+include $(UTSBASE)/i86pc/Makefile.targ
diff --git a/usr/src/uts/i86pc/pcie_pci/Makefile b/usr/src/uts/i86pc/pcie_pci/Makefile
index 20c11a1345..1a7bcef5b9 100644
--- a/usr/src/uts/i86pc/pcie_pci/Makefile
+++ b/usr/src/uts/i86pc/pcie_pci/Makefile
@@ -57,9 +57,14 @@ LINT_TARGET	= $(MODULE).lint
 INSTALL_TARGET	= $(BINARY) $(ROOTMODULE) $(ROOT_CONFFILE)
 
 #
-#	Dependency
+# depends on misc/pcihp and misc/pcie
 #
-LDFLAGS		+= -dy -Nmisc/pcihp
+# For PCI Hotplug support, the misc/pcihp module provides devctl control
+# device and cb_ops functions to support hotplug operations.
+#
+# pcie supplies PCI Express fabric error support
+#
+LDFLAGS		+= -dy -Nmisc/pcihp -Nmisc/pcie
 
 #
 #	Override defaults to build a unique, local modstubs.o.
diff --git a/usr/src/uts/i86pc/pciehpc/Makefile b/usr/src/uts/i86pc/pciehpc/Makefile
index 8f7f5d5349..c1515fca13 100644
--- a/usr/src/uts/i86pc/pciehpc/Makefile
+++ b/usr/src/uts/i86pc/pciehpc/Makefile
@@ -56,9 +56,18 @@ LINT_TARGET	= $(MODULE).lint
 INSTALL_TARGET	= $(BINARY) $(ROOTMODULE)
 
 #
-#	Dependency
+# depends on misc/hpcsvc, misc/acpica and misc/pcie
 #
-LDFLAGS		+= -dy -Nmisc/hpcsvc -Nmisc/acpica
+# For Hotplug support, the misc/hpcsvc module provides various hooks
+# to support hotplug operations.
+#
+# acpica supplies ACPI access routines
+#
+# pcie supplies PCI Express fabric error support
+#
+
+#
+LDFLAGS		+= -dy -Nmisc/hpcsvc -Nmisc/acpica -Nmisc/pcie
 
 #
 # For now, disable these lint checks; maintainers should endeavor