6684221 Remove confusing nvidea error setup code

6691142 Certain PCIE devices on connected to Intel 631xESB/632xESB southbridge can hang or panic

3 files changed, 27 insertions, 14 deletions

diff --git a/usr/src/uts/common/io/pcie.c b/usr/src/uts/common/io/pcie.c
index 60d12684ab..c8ee57d828 100644
--- a/usr/src/uts/common/io/pcie.c
+++ b/usr/src/uts/common/io/pcie.c
@@ -777,7 +777,6 @@ pcie_enable_errors(dev_info_t *dip)
 		    reg32);
 	}
 
-	/* x86 doesn't do this except for RC */
 	/* Enable ECRC generation and checking */
 	if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_CTL)) !=
 	    PCI_CAP_EINVAL32) {
diff --git a/usr/src/uts/i86pc/io/pciex/npe.c b/usr/src/uts/i86pc/io/pciex/npe.c
index 3ca09deb31..a910147b4a 100644
--- a/usr/src/uts/i86pc/io/pciex/npe.c
+++ b/usr/src/uts/i86pc/io/pciex/npe.c
@@ -169,6 +169,7 @@ extern void	npe_query_acpi_mcfg(dev_info_t *dip);
 extern void	npe_ck804_fix_aer_ptr(ddi_acc_handle_t cfg_hdl);
 extern int	npe_disable_empty_bridges_workaround(dev_info_t *child);
 extern void	npe_nvidia_error_mask(ddi_acc_handle_t cfg_hdl);
+extern void	npe_intel_error_mask(ddi_acc_handle_t cfg_hdl);
 
 /*
  * Module linkage information for the kernel.
@@ -857,6 +858,7 @@ npe_initchild(dev_info_t *child)
 	if (pci_config_setup(child, &cfg_hdl) == DDI_SUCCESS) {
 		npe_ck804_fix_aer_ptr(cfg_hdl);
 		npe_nvidia_error_mask(cfg_hdl);
+		npe_intel_error_mask(cfg_hdl);
 		pci_config_teardown(&cfg_hdl);
 	}
 
@@ -873,19 +875,6 @@ npe_initchild(dev_info_t *child)
 			bus_p->bus_aer_off = 0;
 
 		(void) pcie_initchild(child);
-
-		/* If device is an NVIDIA RC do device specific error setup */
-		if ((vendor_id == NVIDIA_VENDOR_ID) &&
-		    NVIDIA_PCIE_RC_DEV_ID(device_id)) {
-			ddi_acc_handle_t cfg_hdl = bus_p->bus_cfg_hdl;
-			uint16_t rc_ctl;
-
-			rc_ctl = pci_config_get16(cfg_hdl, NVIDIA_INTR_BCR_OFF +
-			    0x2);
-			pci_config_put16(cfg_hdl, NVIDIA_INTR_BCR_OFF + 0x2,
-			    rc_ctl | NVIDIA_INTR_BCR_SERR_FORWARD_BIT);
-		}
-
 	}
 
 	return (DDI_SUCCESS);
diff --git a/usr/src/uts/i86pc/io/pciex/npe_misc.c b/usr/src/uts/i86pc/io/pciex/npe_misc.c
index 24e6096f7d..775eb97e0b 100644
--- a/usr/src/uts/i86pc/io/pciex/npe_misc.c
+++ b/usr/src/uts/i86pc/io/pciex/npe_misc.c
@@ -39,6 +39,7 @@
 #include <sys/pci_cap.h>
 #include <sys/pcie_impl.h>
 #include <io/pciex/pcie_nvidia.h>
+#include <io/pciex/pcie_nb5000.h>
 
 /*
  * Prototype declaration
@@ -47,6 +48,7 @@ void	npe_query_acpi_mcfg(dev_info_t *dip);
 void	npe_ck804_fix_aer_ptr(ddi_acc_handle_t cfg_hdl);
 int	npe_disable_empty_bridges_workaround(dev_info_t *child);
 void	npe_nvidia_error_mask(ddi_acc_handle_t cfg_hdl);
+void	npe_intel_error_mask(ddi_acc_handle_t cfg_hdl);
 
 /*
  * Default ecfga base address
@@ -162,3 +164,26 @@ npe_nvidia_error_mask(ddi_acc_handle_t cfg_hdl) {
 		pcie_full_scan = B_TRUE;
 	}
 }
+
+void
+npe_intel_error_mask(ddi_acc_handle_t cfg_hdl) {
+	uint32_t regs;
+	uint16_t vendor_id = pci_config_get16(cfg_hdl, PCI_CONF_VENID);
+
+	if (vendor_id == INTEL_VENDOR_ID) {
+		/*
+		 * Due to an errata in Intel's ESB2 southbridge, all ECRCs
+		 * generation/checking need to be disabled.  There is a
+		 * workaround by setting a proprietary bit in the ESB2, but it
+		 * is not well documented or understood.  If that bit is set in
+		 * the future, then ECRC generation/checking should be enabled
+		 * again.
+		 *
+		 * Disable ECRC generation/checking by masking ECRC in the AER
+		 * UE Mask.  The pcie misc module would then automatically
+		 * disable ECRC generation/checking in the AER Control register.
+		 */
+		regs = pcie_get_aer_uce_mask() | PCIE_AER_UCE_ECRC;
+		pcie_set_aer_uce_mask(regs);
+	}
+}