14957 pcieadm overloads header1.iobasehi

Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Dan McDonald <danmcd@mnx.io>

1 files changed, 14 insertions, 14 deletions

diff --git a/usr/src/cmd/pcieadm/pcieadm_cfgspace.c b/usr/src/cmd/pcieadm/pcieadm_cfgspace.c
index d6a4a931b1..7ee88a6d58 100644
--- a/usr/src/cmd/pcieadm/pcieadm_cfgspace.c
+++ b/usr/src/cmd/pcieadm/pcieadm_cfgspace.c
@@ -722,7 +722,7 @@ pcieadm_cfgspace_print_bars(pcieadm_cfgspace_walk_t *walkp,
 				break;
 			}
 
-			pcieadm_field_printf(walkp, "addr", "Address", addr,
+			pcieadm_field_printf(walkp, "type", "Memory Type", addr,
 			    "%s (0x%x)\n", locstr, type >> 1);
 			pcieadm_field_printf(walkp, "prefetch", "Prefetchable",
 			    pre != 0, "%s (0x%x)\n", pre != 0 ? "yes" : "no",
@@ -1100,7 +1100,7 @@ static const pcieadm_cfgspace_print_t pcieadm_cfgspace_type1[] = {
 	    pcieadm_cfgspace_print_hex },
 	{ PCI_BCNF_IO_BASE_HI, 2, "iobasehi", "I/O Base Upper 16 bits",
 	    pcieadm_cfgspace_print_hex },
-	{ PCI_BCNF_IO_LIMIT_HI, 2, "iobasehi", "I/O Limit Upper 16 bits",
+	{ PCI_BCNF_IO_LIMIT_HI, 2, "iolimithi", "I/O Limit Upper 16 bits",
 	    pcieadm_cfgspace_print_hex },
 	{ PCI_BCNF_CAP_PTR, 1, "cap", "Capabilities Pointer",
 	    pcieadm_cfgspace_print_hex },
@@ -1494,7 +1494,7 @@ static const pcieadm_regdef_t pcieadm_regdef_pcie_slotcap[] = {
 	    .prd_val = { .prdv_strval = { "no", "yes" } } },
 	{ 3, 3, "attnind", "Attention Indicator Present", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { "no", "yes" } } },
-	{ 4, 4, "powind", "Power Indicator Present", PRDV_STRVAL,
+	{ 4, 4, "pwrind", "Power Indicator Present", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { "no", "yes" } } },
 	{ 5, 5, "hpsup", "Hot-Plug Surprise", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { "unsupported", "supported" } } },
@@ -1513,11 +1513,11 @@ static const pcieadm_regdef_t pcieadm_regdef_pcie_slotcap[] = {
 static const pcieadm_regdef_t pcieadm_regdef_pcie_slotctl[] = {
 	{ 0, 0, "attnbtn", "Attention Button Pressed", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { "disabled", "enabled" } } },
-	{ 1, 1, "powflt", "Power Fault Detected", PRDV_STRVAL,
+	{ 1, 1, "pwrflt", "Power Fault Detected", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { "disabled", "enabled" } } },
-	{ 2, 2, "mrlsen", "MRL Sensor Changed", PRDV_STRVAL,
+	{ 2, 2, "mrlchg", "MRL Sensor Changed", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { "disabled", "enabled" } } },
-	{ 3, 3, "presdet", "Presence Detect Changed", PRDV_STRVAL,
+	{ 3, 3, "preschg", "Presence Detect Changed", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { "disabled", "enabled" } } },
 	{ 4, 4, "ccmpltint", "Command Complete Interrupt", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { "disabled", "Enabled" } } },
@@ -1525,7 +1525,7 @@ static const pcieadm_regdef_t pcieadm_regdef_pcie_slotctl[] = {
 	    .prd_val = { .prdv_strval = { "disabled", "enabled" } } },
 	{ 6, 7, "attnind", "Attention Indicator Control", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { NULL, "on", "blink", "off" } } },
-	{ 8, 9, "powin", "Power Indicator Control", PRDV_STRVAL,
+	{ 8, 9, "pwrin", "Power Indicator Control", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { NULL, "on", "blink", "off" } } },
 	{ 10, 10, "pwrctrl", "Power Controller Control", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { "power on", "power off" } } },
@@ -1542,11 +1542,11 @@ static const pcieadm_regdef_t pcieadm_regdef_pcie_slotctl[] = {
 static const pcieadm_regdef_t pcieadm_regdef_pcie_slotsts[] = {
 	{ 0, 0, "attnbtn", "Attention Button Pressed", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { "no", "yes" } } },
-	{ 1, 1, "powflt", "Power Fault Detected", PRDV_STRVAL,
+	{ 1, 1, "pwrflt", "Power Fault Detected", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { "no", "yes" } } },
-	{ 2, 2, "mrlsen", "MRL Sensor Changed", PRDV_STRVAL,
+	{ 2, 2, "mrlchg", "MRL Sensor Changed", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { "no", "yes" } } },
-	{ 3, 3, "presdet", "Presence Detect Changed", PRDV_STRVAL,
+	{ 3, 3, "preschg", "Presence Detect Changed", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { "no", "yes" } } },
 	{ 4, 4, "ccmplt", "Command Complete", PRDV_STRVAL,
 	    .prd_val = { .prdv_strval = { "no", "yes" } } },
@@ -2373,7 +2373,7 @@ static const pcieadm_cfgspace_print_t pcieadm_cap_l1pm_v1[] = {
 	    pcieadm_cfgspace_print_regdef, pcieadm_regdef_l1pm_cap },
 	{ 0x8, 4, "ctl1", "L1 PM Substates Control 1",
 	    pcieadm_cfgspace_print_regdef, pcieadm_regdef_l1pm_ctl1 },
-	{ 0xc, 4, "ctl1", "L1 PM Substates Control 2",
+	{ 0xc, 4, "ctl2", "L1 PM Substates Control 2",
 	    pcieadm_cfgspace_print_regdef, pcieadm_regdef_l1pm_ctl2 },
 	{ -1, -1, NULL }
 };
@@ -2385,7 +2385,7 @@ static const pcieadm_cfgspace_print_t pcieadm_cap_l1pm_v2[] = {
 	    pcieadm_cfgspace_print_regdef, pcieadm_regdef_l1pm_cap },
 	{ 0x8, 4, "ctl1", "L1 PM Substates Control 1",
 	    pcieadm_cfgspace_print_regdef, pcieadm_regdef_l1pm_ctl1 },
-	{ 0xc, 4, "ctl1", "L1 PM Substates Control 2",
+	{ 0xc, 4, "ctl2", "L1 PM Substates Control 2",
 	    pcieadm_cfgspace_print_regdef, pcieadm_regdef_l1pm_ctl2 },
 	{ 0x10, 4, "sts", "L1 PM Substates Status",
 	    pcieadm_cfgspace_print_regdef, pcieadm_regdef_l1pm_sts },
@@ -2408,7 +2408,7 @@ static const pcieadm_cfgspace_print_t pcieadm_cap_ltr[] = {
 	    pcieadm_cfgspace_print_regdef, pcieadm_regdef_pcie_caphdr },
 	{ 0x4, 2, "snoop", "Max Snoop Latency",
 	    pcieadm_cfgspace_print_regdef, pcieadm_regdef_ltr },
-	{ 0x6, 2, "snoop", "Max No-Snoop Latency",
+	{ 0x6, 2, "nosnoop", "Max No-Snoop Latency",
 	    pcieadm_cfgspace_print_regdef, pcieadm_regdef_ltr },
 	{ -1, -1, NULL }
 };
@@ -4743,7 +4743,7 @@ static const pcieadm_pci_cap_t pcieadm_pcie_caps[] = {
 	    { { 0x1, 0x1c, pcieadm_cap_vc } } },
 	{ PCIE_EXT_CAP_ID_SER, "sn", "Serial Number", pcieadm_cap_info_vers,
 	    { { 1, 0xc, pcieadm_cap_sn } } },
-	{ PCIE_EXT_CAP_ID_PWR_BUDGET, "powbudg", "Power Budgeting",
+	{ PCIE_EXT_CAP_ID_PWR_BUDGET, "pwrbudg", "Power Budgeting",
 	    pcieadm_cap_info_vers, { { 1, 0x10, pcieadm_cap_powbudg } } },
 	{ PCIE_EXT_CAP_ID_RC_LINK_DECL, "rcld",
 	    "Root Complex Link Declaration",  pcieadm_cap_info_vers,