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-rw-r--r--usr/src/cmd/pcieadm/pcieadm_cfgspace.c12
-rw-r--r--usr/src/cmd/pcieb/pcieb.c11
-rw-r--r--usr/src/uts/common/io/pciex/pcie.c53
-rw-r--r--usr/src/uts/common/io/pciex/pcieb.c12
-rw-r--r--usr/src/uts/common/io/pciex/pcieb_ioctl.h3
-rw-r--r--usr/src/uts/common/sys/pcie.h16
-rw-r--r--usr/src/uts/common/sys/pcie_impl.h6
7 files changed, 103 insertions, 10 deletions
diff --git a/usr/src/cmd/pcieadm/pcieadm_cfgspace.c b/usr/src/cmd/pcieadm/pcieadm_cfgspace.c
index 739c45cef5..7fc2103ce7 100644
--- a/usr/src/cmd/pcieadm/pcieadm_cfgspace.c
+++ b/usr/src/cmd/pcieadm/pcieadm_cfgspace.c
@@ -1412,7 +1412,7 @@ static pcieadm_regdef_t pcieadm_regdef_pcie_devsts[] = {
static pcieadm_regdef_t pcieadm_regdef_pcie_linkcap[] = {
{ 0, 3, "maxspeed", "Maximum Link Speed", PRDV_STRVAL,
.prd_val = { .prdv_strval = { NULL, "2.5 GT/s", "5.0 GT/s",
- "8.0 GT/s", "16.0 GT/s", "32.0 GT/s" } } },
+ "8.0 GT/s", "16.0 GT/s", "32.0 GT/s", "64.0 GT/s" } } },
{ 4, 9, "maxwidth", "Maximum Link Width", PRDV_HEX },
{ 10, 11, "aspm", "ASPM Support", PRDV_STRVAL,
.prd_val = { .prdv_strval = { "None", "L0s", "L1", "L0s/L1" } } },
@@ -1469,7 +1469,7 @@ static pcieadm_regdef_t pcieadm_regdef_pcie_linkctl[] = {
static pcieadm_regdef_t pcieadm_regdef_pcie_linksts[] = {
{ 0, 3, "speed", "Link Speed", PRDV_STRVAL,
.prd_val = { .prdv_strval = { NULL, "2.5 GT/s", "5.0 GT/s",
- "8.0 GT/s", "16.0 GT/s", "32.0 GT/s" } } },
+ "8.0 GT/s", "16.0 GT/s", "32.0 GT/s", "64.0 GT/s" } } },
{ 4, 9, "width", "Link Width", PRDV_HEX },
{ 11, 11, "training", "Link Training", PRDV_STRVAL,
.prd_val = { .prdv_strval = { "no", "yes" } } },
@@ -1678,17 +1678,17 @@ static pcieadm_regdef_t pcieadm_regdef_pcie_devsts2[] = {
static pcieadm_regdef_t pcieadm_regdef_pcie_linkcap2[] = {
{ 1, 7, "supspeeds", "Supported Link Speeds", PRDV_BITFIELD,
.prd_val = { .prdv_strval = { "2.5 GT/s", "5.0 GT/s", "8.0 GT/s",
- "16.0 GT/s", "32.0 GT/s" } } },
+ "16.0 GT/s", "32.0 GT/s", "64.0 GT/s" } } },
{ 8, 8, "crosslink", "Crosslink", PRDV_STRVAL,
.prd_val = { .prdv_strval = { "unsupported", "supported" } } },
{ 9, 15, "skposgen", "Lower SKP OS Generation Supported Speeds Vector",
PRDV_BITFIELD,
.prd_val = { .prdv_strval = { "2.5 GT/s", "5.0 GT/s", "8.0 GT/s",
- "16.0 GT/s", "32.0 GT/s" } } },
+ "16.0 GT/s", "32.0 GT/s", "64.0 GT/s" } } },
{ 16, 22, "skposrecv", "Lower SKP OS Reception Supported Speeds Vector",
PRDV_BITFIELD,
.prd_val = { .prdv_strval = { "2.5 GT/s", "5.0 GT/s", "8.0 GT/s",
- "16.0 GT/s", "32.0 GT/s" } } },
+ "16.0 GT/s", "32.0 GT/s", "64.0 GT/s" } } },
{ 23, 23, "retimedet", "Retimer Presence Detect Supported", PRDV_STRVAL,
.prd_val = { .prdv_strval = { "unsupported", "supported" } } },
{ 24, 24, "retime2det", "Two Retimers Presence Detect Supported",
@@ -1702,7 +1702,7 @@ static pcieadm_regdef_t pcieadm_regdef_pcie_linkcap2[] = {
static pcieadm_regdef_t pcieadm_regdef_pcie_linkctl2[] = {
{ 0, 3, "targspeed", "Target Link Speed", PRDV_STRVAL,
.prd_val = { .prdv_strval = { NULL, "2.5 GT/s", "5.0 GT/s",
- "8.0 GT/s", "16.0 GT/s", "32.0 GT/s" } } },
+ "8.0 GT/s", "16.0 GT/s", "32.0 GT/s", "64.0 GT/s" } } },
{ 4, 4, "comp", "Enter Compliance", PRDV_STRVAL,
.prd_val = { .prdv_strval = { "no", "yes" } } },
{ 5, 5, "hwautosp", "Hardware Autonomous Speed Disable", PRDV_STRVAL,
diff --git a/usr/src/cmd/pcieb/pcieb.c b/usr/src/cmd/pcieb/pcieb.c
index 0c829e8a51..70b71704e0 100644
--- a/usr/src/cmd/pcieb/pcieb.c
+++ b/usr/src/cmd/pcieb/pcieb.c
@@ -11,6 +11,7 @@
/*
* Copyright 2019 Joyent, Inc.
+ * Copyright 2022 Oxide Computer Company
*/
/*
@@ -64,6 +65,10 @@ pcieb_parse_speed(const char *s)
return (PCIEB_LINK_SPEED_GEN3);
} else if (strcasecmp(s, "16") == 0 || strcasecmp(s, "gen4") == 0) {
return (PCIEB_LINK_SPEED_GEN4);
+ } else if (strcasecmp(s, "32") == 0 || strcasecmp(s, "gen5") == 0) {
+ return (PCIEB_LINK_SPEED_GEN5);
+ } else if (strcasecmp(s, "64") == 0 || strcasecmp(s, "gen6") == 0) {
+ return (PCIEB_LINK_SPEED_GEN6);
} else {
errx(EXIT_FAILURE, "invalid speed: %s", s);
}
@@ -153,6 +158,12 @@ main(int argc, char *argv[])
case PCIEB_LINK_SPEED_GEN4:
(void) printf("16.0 GT/s (gen4)\n");
break;
+ case PCIEB_LINK_SPEED_GEN5:
+ (void) printf("32.0 GT/s (gen5)\n");
+ break;
+ case PCIEB_LINK_SPEED_GEN6:
+ (void) printf("64.0 GT/s (gen6)\n");
+ break;
default:
(void) printf("Unknown Value: 0x%x\n", pits.pits_speed);
}
diff --git a/usr/src/uts/common/io/pciex/pcie.c b/usr/src/uts/common/io/pciex/pcie.c
index c40055809a..acf2e3880c 100644
--- a/usr/src/uts/common/io/pciex/pcie.c
+++ b/usr/src/uts/common/io/pciex/pcie.c
@@ -1538,6 +1538,10 @@ pcie_speed_to_int(pcie_link_speed_t speed)
return (8000000000LL);
case PCIE_LINK_SPEED_16:
return (16000000000LL);
+ case PCIE_LINK_SPEED_32:
+ return (32000000000LL);
+ case PCIE_LINK_SPEED_64:
+ return (64000000000LL);
default:
return (0);
}
@@ -1585,7 +1589,7 @@ pcie_speeds_to_devinfo(dev_info_t *dip, pcie_bus_t *bus_p)
}
if (bus_p->bus_sup_speed != PCIE_LINK_SPEED_UNKNOWN) {
- int64_t speeds[4];
+ int64_t speeds[PCIE_NSPEEDS];
uint_t nspeeds = 0;
if (bus_p->bus_sup_speed & PCIE_LINK_SPEED_2_5) {
@@ -1608,6 +1612,16 @@ pcie_speeds_to_devinfo(dev_info_t *dip, pcie_bus_t *bus_p)
pcie_speed_to_int(PCIE_LINK_SPEED_16);
}
+ if (bus_p->bus_sup_speed & PCIE_LINK_SPEED_32) {
+ speeds[nspeeds++] =
+ pcie_speed_to_int(PCIE_LINK_SPEED_32);
+ }
+
+ if (bus_p->bus_sup_speed & PCIE_LINK_SPEED_64) {
+ speeds[nspeeds++] =
+ pcie_speed_to_int(PCIE_LINK_SPEED_64);
+ }
+
(void) ndi_prop_update_int64_array(DDI_DEV_T_NONE, dip,
"pcie-link-supported-speeds", speeds, nspeeds);
}
@@ -1706,6 +1720,12 @@ pcie_capture_speeds(dev_info_t *dip)
case PCIE_LINKSTS_SPEED_16:
bus_p->bus_cur_speed = PCIE_LINK_SPEED_16;
break;
+ case PCIE_LINKSTS_SPEED_32:
+ bus_p->bus_cur_speed = PCIE_LINK_SPEED_32;
+ break;
+ case PCIE_LINKSTS_SPEED_64:
+ bus_p->bus_cur_speed = PCIE_LINK_SPEED_64;
+ break;
default:
bus_p->bus_cur_speed = PCIE_LINK_SPEED_UNKNOWN;
break;
@@ -1782,6 +1802,10 @@ pcie_capture_speeds(dev_info_t *dip)
bus_p->bus_sup_speed |= PCIE_LINK_SPEED_8;
if (cap2 & PCIE_LINKCAP2_SPEED_16)
bus_p->bus_sup_speed |= PCIE_LINK_SPEED_16;
+ if (cap2 & PCIE_LINKCAP2_SPEED_32)
+ bus_p->bus_sup_speed |= PCIE_LINK_SPEED_32;
+ if (cap2 & PCIE_LINKCAP2_SPEED_64)
+ bus_p->bus_sup_speed |= PCIE_LINK_SPEED_64;
switch (cap & PCIE_LINKCAP_MAX_SPEED_MASK) {
case PCIE_LINKCAP_MAX_SPEED_2_5:
@@ -1796,6 +1820,12 @@ pcie_capture_speeds(dev_info_t *dip)
case PCIE_LINKCAP_MAX_SPEED_16:
bus_p->bus_max_speed = PCIE_LINK_SPEED_16;
break;
+ case PCIE_LINKCAP_MAX_SPEED_32:
+ bus_p->bus_max_speed = PCIE_LINK_SPEED_32;
+ break;
+ case PCIE_LINKCAP_MAX_SPEED_64:
+ bus_p->bus_max_speed = PCIE_LINK_SPEED_64;
+ break;
default:
bus_p->bus_max_speed = PCIE_LINK_SPEED_UNKNOWN;
break;
@@ -1824,6 +1854,12 @@ pcie_capture_speeds(dev_info_t *dip)
case PCIE_LINKCTL2_TARGET_SPEED_16:
bus_p->bus_target_speed = PCIE_LINK_SPEED_16;
break;
+ case PCIE_LINKCTL2_TARGET_SPEED_32:
+ bus_p->bus_target_speed = PCIE_LINK_SPEED_32;
+ break;
+ case PCIE_LINKCTL2_TARGET_SPEED_64:
+ bus_p->bus_target_speed = PCIE_LINK_SPEED_64;
+ break;
default:
bus_p->bus_target_speed = PCIE_LINK_SPEED_UNKNOWN;
break;
@@ -3399,6 +3435,10 @@ pcie_link_set_target(dev_info_t *dip, pcie_link_speed_t speed)
return (ENOTSUP);
}
+ if (bus_p->bus_pcie_vers < 2) {
+ return (ENOTSUP);
+ }
+
switch (speed) {
case PCIE_LINK_SPEED_2_5:
rval = PCIE_LINKCTL2_TARGET_SPEED_2_5;
@@ -3412,11 +3452,22 @@ pcie_link_set_target(dev_info_t *dip, pcie_link_speed_t speed)
case PCIE_LINK_SPEED_16:
rval = PCIE_LINKCTL2_TARGET_SPEED_16;
break;
+ case PCIE_LINK_SPEED_32:
+ rval = PCIE_LINKCTL2_TARGET_SPEED_32;
+ break;
+ case PCIE_LINK_SPEED_64:
+ rval = PCIE_LINKCTL2_TARGET_SPEED_64;
+ break;
default:
return (EINVAL);
}
mutex_enter(&bus_p->bus_speed_mutex);
+ if ((bus_p->bus_sup_speed & speed) == 0) {
+ mutex_exit(&bus_p->bus_speed_mutex);
+ return (ENOTSUP);
+ }
+
bus_p->bus_target_speed = speed;
bus_p->bus_speed_flags |= PCIE_LINK_F_ADMIN_TARGET;
diff --git a/usr/src/uts/common/io/pciex/pcieb.c b/usr/src/uts/common/io/pciex/pcieb.c
index 8ca85e6543..513b6dae3b 100644
--- a/usr/src/uts/common/io/pciex/pcieb.c
+++ b/usr/src/uts/common/io/pciex/pcieb.c
@@ -1546,6 +1546,12 @@ pcieb_ioctl_get_speed(pcieb_devstate_t *pcieb, intptr_t arg, int mode,
case PCIE_LINK_SPEED_16:
pits.pits_speed = PCIEB_LINK_SPEED_GEN4;
break;
+ case PCIE_LINK_SPEED_32:
+ pits.pits_speed = PCIEB_LINK_SPEED_GEN5;
+ break;
+ case PCIE_LINK_SPEED_64:
+ pits.pits_speed = PCIEB_LINK_SPEED_GEN6;
+ break;
default:
pits.pits_speed = PCIEB_LINK_SPEED_UNKNOWN;
break;
@@ -1602,6 +1608,12 @@ pcieb_ioctl_set_speed(pcieb_devstate_t *pcieb, intptr_t arg, int mode,
case PCIEB_LINK_SPEED_GEN4:
speed = PCIE_LINK_SPEED_16;
break;
+ case PCIEB_LINK_SPEED_GEN5:
+ speed = PCIE_LINK_SPEED_32;
+ break;
+ case PCIEB_LINK_SPEED_GEN6:
+ speed = PCIE_LINK_SPEED_64;
+ break;
default:
return (EINVAL);
}
diff --git a/usr/src/uts/common/io/pciex/pcieb_ioctl.h b/usr/src/uts/common/io/pciex/pcieb_ioctl.h
index 40134037a4..cb39a53a11 100644
--- a/usr/src/uts/common/io/pciex/pcieb_ioctl.h
+++ b/usr/src/uts/common/io/pciex/pcieb_ioctl.h
@@ -11,6 +11,7 @@
/*
* Copyright 2019 Joyent, Inc.
+ * Copyright 2022 Oxide Computer Company
*/
#ifndef _IO_PCIE_PCIEB_IOCTL_H
@@ -56,6 +57,8 @@ typedef struct pcieb_ioctl_target_speed {
#define PCIEB_LINK_SPEED_GEN2 0x02
#define PCIEB_LINK_SPEED_GEN3 0x03
#define PCIEB_LINK_SPEED_GEN4 0x04
+#define PCIEB_LINK_SPEED_GEN5 0x05
+#define PCIEB_LINK_SPEED_GEN6 0x06
#ifdef __cplusplus
}
diff --git a/usr/src/uts/common/sys/pcie.h b/usr/src/uts/common/sys/pcie.h
index 751fb449e0..1889b98e47 100644
--- a/usr/src/uts/common/sys/pcie.h
+++ b/usr/src/uts/common/sys/pcie.h
@@ -205,11 +205,13 @@ extern "C" {
/*
* In version 2 of PCI express, this indicated that both 5.0 GT/s and 2.5 GT/s
* speeds were supported. The use of this as the maximum link speed was added
- * with PCIex v3.
+ * with PCIe v3.
*/
#define PCIE_LINKCAP_MAX_SPEED_5 0x2 /* 5.0 GT/s Speed */
#define PCIE_LINKCAP_MAX_SPEED_8 0x3 /* 8.0 GT/s Speed */
#define PCIE_LINKCAP_MAX_SPEED_16 0x4 /* 16.0 GT/s Speed */
+#define PCIE_LINKCAP_MAX_SPEED_32 0x5 /* 32.0 GT/s Speed */
+#define PCIE_LINKCAP_MAX_SPEED_64 0x6 /* 64.0 GT/s Speed */
#define PCIE_LINKCAP_MAX_SPEED_MASK 0xF /* Maximum Link Speed */
#define PCIE_LINKCAP_MAX_WIDTH_X1 0x010
#define PCIE_LINKCAP_MAX_WIDTH_X2 0x020
@@ -290,6 +292,8 @@ extern "C" {
#define PCIE_LINKSTS_SPEED_5 0x2 /* 5.0 GT/s Link Speed */
#define PCIE_LINKSTS_SPEED_8 0x3 /* 8.0 GT/s Link Speed */
#define PCIE_LINKSTS_SPEED_16 0x4 /* 16.0 GT/s Link Speed */
+#define PCIE_LINKSTS_SPEED_32 0x5 /* 32.0 GT/s Link Speed */
+#define PCIE_LINKSTS_SPEED_64 0x6 /* 64.0 GT/s Link Speed */
#define PCIE_LINKSTS_SPEED_MASK 0xF /* Link Speed */
#define PCIE_LINKSTS_NEG_WIDTH_X1 0x010
@@ -470,12 +474,14 @@ extern "C" {
/*
- * Link Capability 2 Register (4 bytes)
+ * Link Capabilities 2 Register (4 bytes)
*/
#define PCIE_LINKCAP2_SPEED_2_5 0x02
#define PCIE_LINKCAP2_SPEED_5 0x04
#define PCIE_LINKCAP2_SPEED_8 0x08
#define PCIE_LINKCAP2_SPEED_16 0x10
+#define PCIE_LINKCAP2_SPEED_32 0x20
+#define PCIE_LINKCAP2_SPEED_64 0x40
#define PCIE_LINKCAP2_SPEED_MASK 0xfe
#define PCIE_LINKCAP2_CROSSLINK 0x100
#define PCIE_LINKCAP2_LSKP_OSGSS_MASK 0xfe00
@@ -483,11 +489,15 @@ extern "C" {
#define PCIE_LINKCAP2_LKSP_OSGSS_5 0x0400
#define PCIE_LINKCAP2_LKSP_OSGSS_8 0x0800
#define PCIE_LINKCAP2_LKSP_OSGSS_16 0x1000
+#define PCIE_LINKCAP2_LKSP_OSGSS_32 0x2000
+#define PCIE_LINKCAP2_LKSP_OSGSS_64 0x4000
#define PCIE_LINKCAP2_LKSP_OSRSS_MASK 0x7f0000
#define PCIE_LINKCAP2_LKSP_OSRSS_2_5 0x010000
#define PCIE_LINKCAP2_LKSP_OSRSS_5 0x020000
#define PCIE_LINKCAP2_LKSP_OSRSS_8 0x040000
#define PCIE_LINKCAP2_LKSP_OSRSS_16 0x080000
+#define PCIE_LINKCAP2_LKSP_OSRSS_32 0x100000
+#define PCIE_LINKCAP2_LKSP_OSRSS_64 0x200000
#define PCIE_LINKCAP2_RTPD_SUP 0x800000
#define PCIE_LINKCAP2_TRTPD_SUP 0x01000000
#define PCIE_LINKCAP2_DRS 0x80000000
@@ -500,6 +510,8 @@ extern "C" {
#define PCIE_LINKCTL2_TARGET_SPEED_5 0x2 /* 5.0 GT/s Speed */
#define PCIE_LINKCTL2_TARGET_SPEED_8 0x3 /* 8.0 GT/s Speed */
#define PCIE_LINKCTL2_TARGET_SPEED_16 0x4 /* 16.0 GT/s Speed */
+#define PCIE_LINKCTL2_TARGET_SPEED_32 0x5 /* 32.0 GT/s Speed */
+#define PCIE_LINKCTL2_TARGET_SPEED_64 0x6 /* 64.0 GT/s Speed */
#define PCIE_LINKCTL2_TARGET_SPEED_MASK 0x000f
#define PICE_LINKCTL2_ENTER_COMPLIANCE 0x0010
#define PCIE_LINKCTL2_HW_AUTO_SPEED_DIS 0x0020
diff --git a/usr/src/uts/common/sys/pcie_impl.h b/usr/src/uts/common/sys/pcie_impl.h
index 501d9839b0..5e18952cbf 100644
--- a/usr/src/uts/common/sys/pcie_impl.h
+++ b/usr/src/uts/common/sys/pcie_impl.h
@@ -317,9 +317,13 @@ typedef enum pcie_link_speed {
PCIE_LINK_SPEED_2_5 = 1 << 0,
PCIE_LINK_SPEED_5 = 1 << 1,
PCIE_LINK_SPEED_8 = 1 << 2,
- PCIE_LINK_SPEED_16 = 1 << 3
+ PCIE_LINK_SPEED_16 = 1 << 3,
+ PCIE_LINK_SPEED_32 = 1 << 4,
+ PCIE_LINK_SPEED_64 = 1 << 5
} pcie_link_speed_t;
+#define PCIE_NSPEEDS 6
+
typedef enum pcie_link_flags {
PCIE_LINK_F_ADMIN_TARGET = 1 << 1
} pcie_link_flags_t;
generated by cgit v1.2.3 (git 2.46.0) at 2026-01-06 09:56:21 +0000