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-rw-r--r--usr/src/lib/libc/Makefile2
-rw-r--r--usr/src/lib/libc/inc/base_inlines.h67
-rw-r--r--usr/src/lib/libc/inc/thr_inlines.h240
-rw-r--r--usr/src/lib/libc/port/sys/zone.c5
-rw-r--r--usr/src/lib/libc/sparc/Makefile.com5
-rw-r--r--usr/src/lib/libc/sparc/crt/_rtld.c11
-rw-r--r--usr/src/lib/libc/sparcv9/Makefile.com5
7 files changed, 175 insertions, 160 deletions
diff --git a/usr/src/lib/libc/Makefile b/usr/src/lib/libc/Makefile
index b75390cbcc..93934954dd 100644
--- a/usr/src/lib/libc/Makefile
+++ b/usr/src/lib/libc/Makefile
@@ -127,7 +127,7 @@ $(ROOTVARIANTDIR64)/$(VAR1_DYNLIB64) := FILEMODE= 755
.KEEP_STATE:
-all: lib32 $(BUILD64) .WAIT lib64 .WAIT etc THIRDPARTYLICENSE
+all: all_h lib32 $(BUILD64) .WAIT lib64 .WAIT etc THIRDPARTYLICENSE
THIRDPARTYLICENSE: extract-copyright
$(RM) $@
diff --git a/usr/src/lib/libc/inc/base_inlines.h b/usr/src/lib/libc/inc/base_inlines.h
index 1753a3e044..c9bf36a90c 100644
--- a/usr/src/lib/libc/inc/base_inlines.h
+++ b/usr/src/lib/libc/inc/base_inlines.h
@@ -27,8 +27,7 @@
#ifndef _BASE_INLINES_H
#define _BASE_INLINES_H
-#pragma ident "%Z%%M% %I% %E% SMI"
-
+#include <sys/ccompile.h>
#include <sys/types.h>
#if !defined(__lint) && defined(__GNUC__)
@@ -41,7 +40,7 @@
*/
#if defined(__sparc)
-extern __inline__ double
+extern __GNU_INLINE double
__mul_set(double x, double y, int *pe)
{
double __result;
@@ -49,19 +48,19 @@ __mul_set(double x, double y, int *pe)
uint32_t *__addr = &__fsr;
__asm__ __volatile__(
- "fmuld %4, %5, %0\n\t"
- "st %%fsr, %3\n\t"
- "ld %3, %2\n\t"
- "and %2, 1, %2\n\t"
- "st %2, %1"
- : "=&e" (__result), "=m" (*pe), "=r" (__fsr), "=m" (*__addr)
- : "e" (x), "e" (y));
+ "fmuld %4, %5, %0\n\t"
+ "st %%fsr, %3\n\t"
+ "ld %3, %2\n\t"
+ "and %2, 1, %2\n\t"
+ "st %2, %1"
+ : "=&e" (__result), "=m" (*pe), "=r" (__fsr), "=m" (*__addr)
+ : "e" (x), "e" (y));
return (__result);
}
#endif /* __sparc */
#if defined(__sparc)
-extern __inline__ double
+extern __GNU_INLINE double
__div_set(double x, double y, int *pe)
{
double __result;
@@ -69,37 +68,37 @@ __div_set(double x, double y, int *pe)
uint32_t *__addr = &__fsr;
__asm__ __volatile__(
- "fdivd %4, %5, %0\n\t"
- "st %%fsr, %3\n\t"
- "ld %3, %2\n\t"
- "and %2, 1, %2\n\t"
- "st %2, %1"
- : "=&e" (__result), "=m" (*pe), "=r" (__fsr), "=m" (*__addr)
- : "e" (x), "e" (y));
+ "fdivd %4, %5, %0\n\t"
+ "st %%fsr, %3\n\t"
+ "ld %3, %2\n\t"
+ "and %2, 1, %2\n\t"
+ "st %2, %1"
+ : "=&e" (__result), "=m" (*pe), "=r" (__fsr), "=m" (*__addr)
+ : "e" (x), "e" (y));
return (__result);
}
#endif /* __sparc */
#if defined(__sparc)
-extern __inline__ double
+extern __GNU_INLINE double
__dabs(double *x)
{
double __result;
__asm__ __volatile__(
#if defined(__sparcv9)
- "fabsd %1, %0"
+ "fabsd %1, %0"
#else
- "fabss %1, %0"
+ "fabss %1, %0"
#endif
- : "=e" (__result)
- : "0" (*x));
+ : "=e" (__result)
+ : "0" (*x));
return (__result);
}
#endif /* __sparc */
#if defined(__sparc)
-extern __inline__ void
+extern __GNU_INLINE void
__get_ieee_flags(__ieee_flags_type *b)
{
uint32_t __fsr;
@@ -109,16 +108,16 @@ __get_ieee_flags(__ieee_flags_type *b)
* needed; however, it warns as it does so. Add them here for now.
*/
__asm__ __volatile__(
- "st %%fsr, %0\n\t"
- "st %%g0, %1\n\t"
- "ld %1, %%fsr\n\t"
- "nop; nop; nop"
- : "=m" (*b), "=m" (__fsr));
+ "st %%fsr, %0\n\t"
+ "st %%g0, %1\n\t"
+ "ld %1, %%fsr\n\t"
+ "nop; nop; nop"
+ : "=m" (*b), "=m" (__fsr));
}
#endif /* __sparc */
#if defined(__sparc)
-extern __inline__ void
+extern __GNU_INLINE void
__set_ieee_flags(__ieee_flags_type *b)
{
/*
@@ -126,10 +125,10 @@ __set_ieee_flags(__ieee_flags_type *b)
* needed; however, it warns as it does so. Add them here for now.
*/
__asm__ __volatile__(
- "ld %0, %%fsr\n\t"
- "nop; nop; nop"
- : /* no outputs */
- : "m" (*b));
+ "ld %0, %%fsr\n\t"
+ "nop; nop; nop"
+ : /* no outputs */
+ : "m" (*b));
}
#endif /* __sparc */
diff --git a/usr/src/lib/libc/inc/thr_inlines.h b/usr/src/lib/libc/inc/thr_inlines.h
index 55bd645428..7376109aa5 100644
--- a/usr/src/lib/libc/inc/thr_inlines.h
+++ b/usr/src/lib/libc/inc/thr_inlines.h
@@ -27,54 +27,56 @@
#ifndef _THR_INLINES_H
#define _THR_INLINES_H
-#pragma ident "%Z%%M% %I% %E% SMI"
+#include <sys/ccompile.h>
#if !defined(__lint) && defined(__GNUC__)
/* inlines for gcc */
-extern __inline__ ulwp_t *
+extern __GNU_INLINE ulwp_t *
_curthread(void)
{
-#if defined(__amd64)
ulwp_t *__value;
- __asm__ __volatile__("movq %%fs:0, %0" : "=r" (__value));
+ __asm__ __volatile__(
+#if defined(__amd64)
+ "movq %%fs:0, %0\n\t"
#elif defined(__i386)
- ulwp_t *__value;
- __asm__ __volatile__("movl %%gs:0, %0" : "=r" (__value));
+ "movl %%gs:0, %0\n\t"
#elif defined(__sparc)
- register ulwp_t *__value __asm__("g7");
+ ".register %%g7, #scratch\n\t"
+ "mov %%g7, %0\n\t"
#else
#error "port me"
#endif
+ : "=r" (__value));
return (__value);
}
-extern __inline__ ulwp_t *
+extern __GNU_INLINE ulwp_t *
__curthread(void)
{
ulwp_t *__value;
__asm__ __volatile__(
#if defined(__amd64)
- "movq %%fs:0, %0\n\t"
+ "movq %%fs:0, %0\n\t"
#elif defined(__i386)
- "movl %%gs:0, %0\n\t"
+ "movl %%gs:0, %0\n\t"
#elif defined(__sparcv9)
- ".register %%g7, #scratch\n\t"
- "ldx [%%g7 + 80], %0\n\t"
+ ".register %%g7, #scratch\n\t"
+ "ldx [%%g7 + 80], %0\n\t"
#elif defined(__sparc)
- ".register %%g7, #scratch\n\t"
- "ld [%%g7 + 80], %0\n\t"
+ ".register %%g7, #scratch\n\t"
+ "ld [%%g7 + 80], %0\n\t"
#else
#error "port me"
#endif
- "1:"
- : "=r" (__value)
- : : "cc");
+ "1:"
+ : "=r" (__value)
+ : : "cc");
return (__value);
}
-extern __inline__ greg_t
+extern __GNU_INLINE greg_t
stkptr(void)
{
#if defined(__amd64)
@@ -89,207 +91,207 @@ stkptr(void)
return (__value);
}
-extern __inline__ hrtime_t
+extern __GNU_INLINE hrtime_t
gethrtime(void) /* note: caller-saved registers are trashed */
{
#if defined(__amd64)
hrtime_t __value;
__asm__ __volatile__(
- "movl $3, %%eax\n\t"
- "int $0xd2"
- : "=a" (__value)
- : : "rcx", "rdx", "rsi", "rdi", "r8", "r9", "r10", "r11", "cc");
+ "movl $3, %%eax\n\t"
+ "int $0xd2"
+ : "=a" (__value)
+ : : "rcx", "rdx", "rsi", "rdi", "r8", "r9", "r10", "r11", "cc");
#elif defined(__i386)
hrtime_t __value;
__asm__ __volatile__(
- "movl $3, %%eax\n\t"
- "int $0xd2"
- : "=A" (__value)
- : : "ecx", "cc");
+ "movl $3, %%eax\n\t"
+ "int $0xd2"
+ : "=A" (__value)
+ : : "ecx", "cc");
#elif defined(__sparcv9)
register hrtime_t __value __asm__("o0");
__asm__ __volatile__(
- "ta 0x24\n\t"
- "sllx %%o0, 32, %0\n\t"
- "or %%o1, %0, %0"
- : "=r" (__value)
- : : "o1", "o2", "o3", "o4", "o5", "cc");
+ "ta 0x24\n\t"
+ "sllx %%o0, 32, %0\n\t"
+ "or %%o1, %0, %0"
+ : "=r" (__value)
+ : : "o1", "o2", "o3", "o4", "o5", "cc");
#elif defined(__sparc)
register hrtime_t __value __asm__("o0");
__asm__ __volatile__(
- "ta 0x24"
- : "=r" (__value)
- : : "o2", "o3", "o4", "o5", "cc");
+ "ta 0x24"
+ : "=r" (__value)
+ : : "o2", "o3", "o4", "o5", "cc");
#else
#error "port me"
#endif
return (__value);
}
-extern __inline__ int
+extern __GNU_INLINE int
set_lock_byte(volatile uint8_t *__lockp)
{
int __value;
#if defined(__x86)
__asm__ __volatile__(
- "movl $1, %0\n\t"
- "xchgb %%dl, %1"
- : "+d" (__value), "+m" (*__lockp));
+ "movl $1, %0\n\t"
+ "xchgb %%dl, %1"
+ : "+d" (__value), "+m" (*__lockp));
#elif defined(__sparc)
__asm__ __volatile__(
- "ldstub %1, %0\n\t"
- "membar #LoadLoad"
- : "=r" (__value), "+m" (*__lockp));
+ "ldstub %1, %0\n\t"
+ "membar #LoadLoad"
+ : "=r" (__value), "+m" (*__lockp));
#else
#error "port me"
#endif
return (__value);
}
-extern __inline__ uint32_t
+extern __GNU_INLINE uint32_t
atomic_swap_32(volatile uint32_t *__memory, uint32_t __value)
{
#if defined(__x86)
__asm__ __volatile__(
- "xchgl %0, %1"
- : "+q" (__value), "+m" (*__memory));
+ "xchgl %0, %1"
+ : "+q" (__value), "+m" (*__memory));
return (__value);
#elif defined(__sparc)
uint32_t __tmp1, __tmp2;
__asm__ __volatile__(
- "ld [%3], %0\n\t"
- "1:\n\t"
- "mov %4, %1\n\t"
- "cas [%3], %0, %1\n\t"
- "cmp %0, %1\n\t"
- "bne,a,pn %%icc, 1b\n\t"
- " mov %1, %0"
- : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory)
- : "r" (__memory), "r" (__value)
- : "cc");
+ "ld [%3], %0\n\t"
+ "1:\n\t"
+ "mov %4, %1\n\t"
+ "cas [%3], %0, %1\n\t"
+ "cmp %0, %1\n\t"
+ "bne,a,pn %%icc, 1b\n\t"
+ " mov %1, %0"
+ : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory)
+ : "r" (__memory), "r" (__value)
+ : "cc");
return (__tmp2);
#else
#error "port me"
#endif
}
-extern __inline__ uint32_t
+extern __GNU_INLINE uint32_t
atomic_cas_32(volatile uint32_t *__memory, uint32_t __cmp, uint32_t __newvalue)
{
uint32_t __oldvalue;
#if defined(__x86)
__asm__ __volatile__(
- "lock; cmpxchgl %3, %0"
- : "=m" (*__memory), "=a" (__oldvalue)
- : "a" (__cmp), "r" (__newvalue));
+ "lock; cmpxchgl %3, %0"
+ : "=m" (*__memory), "=a" (__oldvalue)
+ : "a" (__cmp), "r" (__newvalue));
#elif defined(__sparc)
__asm__ __volatile__(
- "cas [%2], %3, %1"
- : "=m" (*__memory), "=&r" (__oldvalue)
- : "r" (__memory), "r" (__cmp), "1" (__newvalue));
+ "cas [%2], %3, %1"
+ : "=m" (*__memory), "=&r" (__oldvalue)
+ : "r" (__memory), "r" (__cmp), "1" (__newvalue));
#else
#error "port me"
#endif
return (__oldvalue);
}
-extern __inline__ void
+extern __GNU_INLINE void
atomic_inc_32(volatile uint32_t *__memory)
{
#if defined(__x86)
__asm__ __volatile__(
- "lock; incl %0"
- : "+m" (*__memory));
+ "lock; incl %0"
+ : "+m" (*__memory));
#elif defined(__sparc)
uint32_t __tmp1, __tmp2;
__asm__ __volatile__(
- "ld [%3], %0\n\t"
- "1:\n\t"
- "add %0, 1, %1\n\t"
- "cas [%3], %0, %1\n\t"
- "cmp %0, %1\n\t"
- "bne,a,pn %%icc, 1b\n\t"
- " mov %1, %0"
- : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory)
- : "r" (__memory)
- : "cc");
+ "ld [%3], %0\n\t"
+ "1:\n\t"
+ "add %0, 1, %1\n\t"
+ "cas [%3], %0, %1\n\t"
+ "cmp %0, %1\n\t"
+ "bne,a,pn %%icc, 1b\n\t"
+ " mov %1, %0"
+ : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory)
+ : "r" (__memory)
+ : "cc");
#else
#error "port me"
#endif
}
-extern __inline__ void
+extern __GNU_INLINE void
atomic_dec_32(volatile uint32_t *__memory)
{
#if defined(__x86)
__asm__ __volatile__(
- "lock; decl %0"
- : "+m" (*__memory));
+ "lock; decl %0"
+ : "+m" (*__memory));
#elif defined(__sparc)
uint32_t __tmp1, __tmp2;
__asm__ __volatile__(
- "ld [%3], %0\n\t"
- "1:\n\t"
- "sub %0, 1, %1\n\t"
- "cas [%3], %0, %1\n\t"
- "cmp %0, %1\n\t"
- "bne,a,pn %%icc, 1b\n\t"
- " mov %1, %0"
- : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory)
- : "r" (__memory)
- : "cc");
+ "ld [%3], %0\n\t"
+ "1:\n\t"
+ "sub %0, 1, %1\n\t"
+ "cas [%3], %0, %1\n\t"
+ "cmp %0, %1\n\t"
+ "bne,a,pn %%icc, 1b\n\t"
+ " mov %1, %0"
+ : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory)
+ : "r" (__memory)
+ : "cc");
#else
#error "port me"
#endif
}
-extern __inline__ void
+extern __GNU_INLINE void
atomic_and_32(volatile uint32_t *__memory, uint32_t __bits)
{
#if defined(__x86)
__asm__ __volatile__(
- "lock; andl %1, %0"
- : "+m" (*__memory)
- : "r" (__bits));
+ "lock; andl %1, %0"
+ : "+m" (*__memory)
+ : "r" (__bits));
#elif defined(__sparc)
uint32_t __tmp1, __tmp2;
__asm__ __volatile__(
- "ld [%3], %0\n\t"
- "1:\n\t"
- "and %0, %4, %1\n\t"
- "cas [%3], %0, %1\n\t"
- "cmp %0, %1\n\t"
- "bne,a,pn %%icc, 1b\n\t"
- " mov %1, %0"
- : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory)
- : "r" (__memory), "r" (__bits)
- : "cc");
+ "ld [%3], %0\n\t"
+ "1:\n\t"
+ "and %0, %4, %1\n\t"
+ "cas [%3], %0, %1\n\t"
+ "cmp %0, %1\n\t"
+ "bne,a,pn %%icc, 1b\n\t"
+ " mov %1, %0"
+ : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory)
+ : "r" (__memory), "r" (__bits)
+ : "cc");
#else
#error "port me"
#endif
}
-extern __inline__ void
+extern __GNU_INLINE void
atomic_or_32(volatile uint32_t *__memory, uint32_t __bits)
{
#if defined(__x86)
__asm__ __volatile__(
- "lock; orl %1, %0"
- : "+m" (*__memory)
- : "r" (__bits));
+ "lock; orl %1, %0"
+ : "+m" (*__memory)
+ : "r" (__bits));
#elif defined(__sparc)
uint32_t __tmp1, __tmp2;
__asm__ __volatile__(
- "ld [%3], %0\n\t"
- "1:\n\t"
- "or %0, %4, %1\n\t"
- "cas [%3], %0, %1\n\t"
- "cmp %0, %1\n\t"
- "bne,a,pn %%icc, 1b\n\t"
- " mov %1, %0"
- : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory)
- : "r" (__memory), "r" (__bits)
- : "cc");
+ "ld [%3], %0\n\t"
+ "1:\n\t"
+ "or %0, %4, %1\n\t"
+ "cas [%3], %0, %1\n\t"
+ "cmp %0, %1\n\t"
+ "bne,a,pn %%icc, 1b\n\t"
+ " mov %1, %0"
+ : "=&r" (__tmp1), "=&r" (__tmp2), "=m" (*__memory)
+ : "r" (__memory), "r" (__bits)
+ : "cc");
#else
#error "port me"
#endif
@@ -297,14 +299,14 @@ atomic_or_32(volatile uint32_t *__memory, uint32_t __bits)
#if defined(__sparc) /* only needed on sparc */
-extern __inline__ ulong_t
+extern __GNU_INLINE ulong_t
caller(void)
{
register ulong_t __value __asm__("i7");
return (__value);
}
-extern __inline__ ulong_t
+extern __GNU_INLINE ulong_t
getfp(void)
{
register ulong_t __value __asm__("fp");
@@ -315,7 +317,7 @@ getfp(void)
#if defined(__x86) /* only needed on x86 */
-extern __inline__ void
+extern __GNU_INLINE void
ht_pause(void)
{
__asm__ __volatile__("rep; nop");
diff --git a/usr/src/lib/libc/port/sys/zone.c b/usr/src/lib/libc/port/sys/zone.c
index 4a4c70043d..182a7f22f7 100644
--- a/usr/src/lib/libc/port/sys/zone.c
+++ b/usr/src/lib/libc/port/sys/zone.c
@@ -22,6 +22,7 @@
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
+ * Copyright 2011 Joyent Inc. All rights reserved.
*/
#include "lint.h"
@@ -39,7 +40,8 @@
zoneid_t
zone_create(const char *name, const char *root, const struct priv_set *privs,
const char *rctls, size_t rctlsz, const char *zfs, size_t zfssz,
- int *extended_error, int match, int doi, const bslabel_t *label, int flags)
+ int *extended_error, int match, int doi, const bslabel_t *label, int flags,
+ zoneid_t req_zoneid)
{
zone_def zd;
priv_data_t *d;
@@ -59,6 +61,7 @@ zone_create(const char *name, const char *root, const struct priv_set *privs,
zd.doi = doi;
zd.label = label;
zd.flags = flags;
+ zd.zoneid = req_zoneid;
return ((zoneid_t)syscall(SYS_zone, ZONE_CREATE, &zd));
}
diff --git a/usr/src/lib/libc/sparc/Makefile.com b/usr/src/lib/libc/sparc/Makefile.com
index f1ed31ea41..97aa14a7d6 100644
--- a/usr/src/lib/libc/sparc/Makefile.com
+++ b/usr/src/lib/libc/sparc/Makefile.com
@@ -1204,8 +1204,9 @@ TIL= \
$(TIL:%=pics/%) := CFLAGS += $(LIBCBASE)/threads/sparc.il
-# This hack is needed until the sparc gcc is fixed for TLS
-pics/tls_data.o := CC = env 'CW_NO_SHADOW=1' $(ONBLD_TOOLS)/bin/$(MACH)/cw -_cc
+# This hack is needed because sparc GCC3 generates DWARF data about TLS which
+# The Sun assembler cannot process
+$(__GNUC3)pics/tls_data.o := CC = env 'CW_NO_SHADOW=1' $(ONBLD_TOOLS)/bin/$(MACH)/cw -_cc
# special kludge for inlines with 'cas':
pics/rwlock.o pics/synch.o pics/lwp.o pics/door_calls.o := \
diff --git a/usr/src/lib/libc/sparc/crt/_rtld.c b/usr/src/lib/libc/sparc/crt/_rtld.c
index 132aad09c0..caa2919674 100644
--- a/usr/src/lib/libc/sparc/crt/_rtld.c
+++ b/usr/src/lib/libc/sparc/crt/_rtld.c
@@ -62,6 +62,15 @@
#define SYSCONFIG (*(funcs[SYSCONFIG_F]))
/*
+ * GCC will not emit unused static functions unless specifically told it must
+ */
+#ifdef __GNUC__
+#define __USED __attribute__((used))
+#else
+#define __USED
+#endif
+
+/*
* Alias ld.so entry point -- receives a bootstrap structure and a vector
* of strings. The vector is "well-known" to us, and consists of pointers
* to string constants. This aliasing bootstrap requires no relocation in
@@ -70,7 +79,7 @@
* order to maintain the "no bootstrapping" requirement -- it calls only
* local functions, uses no intrinsics, etc.
*/
-static void *
+static void * __USED
__rtld(Elf32_Boot *ebp, const char *strings[], int (*funcs[])())
{
int i, p; /* working */
diff --git a/usr/src/lib/libc/sparcv9/Makefile.com b/usr/src/lib/libc/sparcv9/Makefile.com
index 226547fa6d..462d07e8a2 100644
--- a/usr/src/lib/libc/sparcv9/Makefile.com
+++ b/usr/src/lib/libc/sparcv9/Makefile.com
@@ -1136,8 +1136,9 @@ TIL= \
$(TIL:%=pics/%) := CFLAGS64 += $(LIBCBASE)/threads/sparcv9.il
-# This hack is needed until the sparc gcc is fixed for TLS
-pics/tls_data.o := CC = env 'CW_NO_SHADOW=1' $(ONBLD_TOOLS)/bin/$(MACH)/cw -_cc
+# This hack is needed because sparc GCC3 generates DWARF data about TLS which
+# The Sun assembler cannot process
+$(__GNUC3)pics/tls_data.o := CC = env 'CW_NO_SHADOW=1' $(ONBLD_TOOLS)/bin/$(MACH)/cw -_cc
# Files in fp, port/fp subdirectories that need base.il inline template
IL= \
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-12 19:25:00 +0000