diff options
Diffstat (limited to 'usr/src/test/util-tests')
70 files changed, 5399 insertions, 6 deletions
diff --git a/usr/src/test/util-tests/tests/dis/Makefile b/usr/src/test/util-tests/tests/dis/Makefile index 53cf7ccd40..fb87bed44d 100644 --- a/usr/src/test/util-tests/tests/dis/Makefile +++ b/usr/src/test/util-tests/tests/dis/Makefile @@ -17,10 +17,56 @@ include $(SRC)/Makefile.master ROOTOPTPKG = $(ROOT)/opt/util-tests TESTDIR = $(ROOTOPTPKG)/tests/dis -ARCHS = i386 sparc +ARCHS = i386 sparc arm64 PROG = distest +ARM64_TESTS = \ + tst.branches \ + tst.data-imm \ + tst.data-reg \ + tst.load-store \ + tst.regs \ + tst.branch \ + tst.addsub-carry \ + tst.addsub-extreg \ + tst.addsub-imm \ + tst.addsub-shiftreg \ + tst.bitfield \ + tst.condcomp-imm \ + tst.condcomp-reg \ + tst.movwide-imm \ + tst.extract \ + tst.logical-imm \ + tst.logical-shiftreg \ + tst.ldst-reg-pair \ + tst.ldst-literal \ + tst.ldst-prfm \ + tst.ldst-noalloc \ + tst.dproc1 \ + tst.dproc2 \ + tst.condsel \ + tst.dproc3 \ + tst.exception \ + tst.system \ + tst.ldst-exclusive \ + tst.ldst-reg-imm-post \ + tst.ldst-reg-imm-pre \ + tst.ldst-reg-offset \ + tst.ldst-reg-unpriv \ + tst.ldst-reg-unscaled \ + tst.ldst-reg-unsigned \ + tst.ldst-simd \ + tst.simd-across \ + tst.simd-copy \ + tst.simd-ext \ + tst.simd-modimm \ + tst.simd-pairwise \ + tst.simd-scalarshift \ + tst.simd-tbl \ + tst.simd-trn + + SPARC_TESTS = \ tst.regs @@ -90,6 +136,9 @@ ROOTI386 = $(I386_FILES:%=$(TESTDIR)/i386/%) SPARC_FILES = $(SPARC_TESTS:%=%.s) $(SPARC_TESTS:%=%.out) ROOTSPARC = $(SPARC_FILES:%=$(TESTDIR)/sparc/%) +ARM64_FILES = $(ARM64_TESTS:%=%.s) $(ARM64_TESTS:%=%.out) +ROOTARM64 = $(ARM64_FILES:%=$(TESTDIR)/arm64/%) + include $(SRC)/cmd/Makefile.cmd include $(SRC)/test/Makefile.com @@ -97,7 +146,7 @@ ARCHDIRS = $(ARCHS:%=$(TESTDIR)/%) CMDS = $(PROG:%=$(TESTDIR)/%) $(CMDS) := FILEMODE = 0555 -install: $(CMDS) $(ROOTI386) $(ROOTSPARC) +install: $(CMDS) $(ROOTI386) $(ROOTSPARC) $(ROOTARM64) lint: @@ -105,7 +154,7 @@ clobber: clean clean: -$(CMDS) $(ROOTI386) $(ROOTSPARC): $(TESTDIR) $(ARCHDIRS) +$(CMDS) $(ROOTI386) $(ROOTSPARC) $(ROOTARM64): $(TESTDIR) $(ARCHDIRS) $(TESTDIR) $(ARCHDIRS): $(INS.dir) diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-carry.out b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-carry.out new file mode 100755 index 0000000000..564645f0f7 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-carry.out @@ -0,0 +1,32 @@ + libdis_test: e0 01 1e 1a adc w0, w15, w30 + libdis_test+0x4: ff 01 1e 1a adc wzr, w15, w30 + libdis_test+0x8: e0 03 1e 1a adc w0, wzr, w30 + libdis_test+0xc: e0 01 1f 1a adc w0, w15, wzr + libdis_test+0x10: e0 01 1e 9a adc x0, x15, x30 + libdis_test+0x14: ff 01 1e 9a adc xzr, x15, x30 + libdis_test+0x18: e0 03 1e 9a adc x0, xzr, x30 + libdis_test+0x1c: e0 01 1f 9a adc x0, x15, xzr + libdis_test+0x20: e0 01 1e 3a adcs w0, w15, w30 + libdis_test+0x24: ff 01 1e 3a adcs wzr, w15, w30 + libdis_test+0x28: e0 03 1e 3a adcs w0, wzr, w30 + libdis_test+0x2c: e0 01 1f 3a adcs w0, w15, wzr + libdis_test+0x30: e0 01 1e ba adcs x0, x15, x30 + libdis_test+0x34: ff 01 1e ba adcs xzr, x15, x30 + libdis_test+0x38: e0 03 1e ba adcs x0, xzr, x30 + libdis_test+0x3c: e0 01 1f ba adcs x0, x15, xzr + libdis_test+0x40: e0 01 1e 5a sbc w0, w15, w30 + libdis_test+0x44: ff 01 1e 5a sbc wzr, w15, w30 + libdis_test+0x48: e0 03 1e 5a sbc w0, wzr, w30 + libdis_test+0x4c: e0 01 1f 5a sbc w0, w15, wzr + libdis_test+0x50: e0 01 1e da sbc x0, x15, x30 + libdis_test+0x54: ff 01 1e da sbc xzr, x15, x30 + libdis_test+0x58: e0 03 1e da sbc x0, xzr, x30 + libdis_test+0x5c: e0 01 1f da sbc x0, x15, xzr + libdis_test+0x60: e0 01 1e 7a sbcs w0, w15, w30 + libdis_test+0x64: ff 01 1e 7a sbcs wzr, w15, w30 + libdis_test+0x68: e0 03 1e 7a sbcs w0, wzr, w30 + libdis_test+0x6c: e0 01 1f 7a sbcs w0, w15, wzr + libdis_test+0x70: e0 01 1e fa sbcs x0, x15, x30 + libdis_test+0x74: ff 01 1e fa sbcs xzr, x15, x30 + libdis_test+0x78: e0 03 1e fa sbcs x0, xzr, x30 + libdis_test+0x7c: e0 01 1f fa sbcs x0, x15, xzr diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-carry.s b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-carry.s new file mode 100755 index 0000000000..a7f3c64d1c --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-carry.s @@ -0,0 +1,54 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.5.3 Add/subtract (with carry) + */ +.macro addsub_carry op + /* 32-bit */ + \op w0, w15, w30 + \op wzr, w15, w30 + \op w0, wzr, w30 + \op w0, w15, wzr + /* 64-bit */ + \op x0, x15, x30 + \op xzr, x15, x30 + \op x0, xzr, x30 + \op x0, x15, xzr +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * C5.6.1 ADC + */ + addsub_carry adc + /* + * C5.6.2 ADCS + */ + addsub_carry adcs + /* + * C5.6.155 SBC + * C5.6.137 NGC (alias) + */ + addsub_carry sbc + /* + * C5.6.156 SBCS + * C5.6.138 NGCS (alias) + */ + addsub_carry sbcs +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-extreg.out b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-extreg.out new file mode 100755 index 0000000000..87be6c3784 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-extreg.out @@ -0,0 +1,976 @@ + libdis_test: e0 01 1e 0b add w0, w15, w30 + libdis_test+0x4: e0 01 3e 0b add w0, w15, w30, uxtb #0 + libdis_test+0x8: e0 01 3e 0b add w0, w15, w30, uxtb #0 + libdis_test+0xc: e0 05 3e 0b add w0, w15, w30, uxtb #1 + libdis_test+0x10: e0 09 3e 0b add w0, w15, w30, uxtb #2 + libdis_test+0x14: e0 0d 3e 0b add w0, w15, w30, uxtb #3 + libdis_test+0x18: e0 11 3e 0b add w0, w15, w30, uxtb #4 + libdis_test+0x1c: e0 43 3f 0b add w0, wsp, wzr, uxtw #0 + libdis_test+0x20: e0 03 3f 0b add w0, wsp, wzr, uxtb #0 + libdis_test+0x24: e0 03 3f 0b add w0, wsp, wzr, uxtb #0 + libdis_test+0x28: e0 07 3f 0b add w0, wsp, wzr, uxtb #1 + libdis_test+0x2c: e0 0b 3f 0b add w0, wsp, wzr, uxtb #2 + libdis_test+0x30: e0 0f 3f 0b add w0, wsp, wzr, uxtb #3 + libdis_test+0x34: e0 13 3f 0b add w0, wsp, wzr, uxtb #4 + libdis_test+0x38: e0 01 3e 8b add x0, x15, w30, uxtb #0 + libdis_test+0x3c: e0 01 3e 8b add x0, x15, w30, uxtb #0 + libdis_test+0x40: e0 05 3e 8b add x0, x15, w30, uxtb #1 + libdis_test+0x44: e0 09 3e 8b add x0, x15, w30, uxtb #2 + libdis_test+0x48: e0 0d 3e 8b add x0, x15, w30, uxtb #3 + libdis_test+0x4c: e0 11 3e 8b add x0, x15, w30, uxtb #4 + libdis_test+0x50: e0 43 3f 8b add x0, sp, wzr, uxtw #0 + libdis_test+0x54: e0 03 3f 8b add x0, sp, wzr, uxtb #0 + libdis_test+0x58: e0 03 3f 8b add x0, sp, wzr, uxtb #0 + libdis_test+0x5c: e0 07 3f 8b add x0, sp, wzr, uxtb #1 + libdis_test+0x60: e0 0b 3f 8b add x0, sp, wzr, uxtb #2 + libdis_test+0x64: e0 0f 3f 8b add x0, sp, wzr, uxtb #3 + libdis_test+0x68: e0 13 3f 8b add x0, sp, wzr, uxtb #4 + libdis_test+0x6c: ff 61 3e 8b add sp, x15, x30, lsl #0 + libdis_test+0x70: ff 01 3e 8b add sp, x15, w30, uxtb #0 + libdis_test+0x74: e0 01 1e 0b add w0, w15, w30 + libdis_test+0x78: e0 21 3e 0b add w0, w15, w30, uxth #0 + libdis_test+0x7c: e0 21 3e 0b add w0, w15, w30, uxth #0 + libdis_test+0x80: e0 25 3e 0b add w0, w15, w30, uxth #1 + libdis_test+0x84: e0 29 3e 0b add w0, w15, w30, uxth #2 + libdis_test+0x88: e0 2d 3e 0b add w0, w15, w30, uxth #3 + libdis_test+0x8c: e0 31 3e 0b add w0, w15, w30, uxth #4 + libdis_test+0x90: e0 43 3f 0b add w0, wsp, wzr, uxtw #0 + libdis_test+0x94: e0 23 3f 0b add w0, wsp, wzr, uxth #0 + libdis_test+0x98: e0 23 3f 0b add w0, wsp, wzr, uxth #0 + libdis_test+0x9c: e0 27 3f 0b add w0, wsp, wzr, uxth #1 + libdis_test+0xa0: e0 2b 3f 0b add w0, wsp, wzr, uxth #2 + libdis_test+0xa4: e0 2f 3f 0b add w0, wsp, wzr, uxth #3 + libdis_test+0xa8: e0 33 3f 0b add w0, wsp, wzr, uxth #4 + libdis_test+0xac: e0 21 3e 8b add x0, x15, w30, uxth #0 + libdis_test+0xb0: e0 21 3e 8b add x0, x15, w30, uxth #0 + libdis_test+0xb4: e0 25 3e 8b add x0, x15, w30, uxth #1 + libdis_test+0xb8: e0 29 3e 8b add x0, x15, w30, uxth #2 + libdis_test+0xbc: e0 2d 3e 8b add x0, x15, w30, uxth #3 + libdis_test+0xc0: e0 31 3e 8b add x0, x15, w30, uxth #4 + libdis_test+0xc4: e0 43 3f 8b add x0, sp, wzr, uxtw #0 + libdis_test+0xc8: e0 23 3f 8b add x0, sp, wzr, uxth #0 + libdis_test+0xcc: e0 23 3f 8b add x0, sp, wzr, uxth #0 + libdis_test+0xd0: e0 27 3f 8b add x0, sp, wzr, uxth #1 + libdis_test+0xd4: e0 2b 3f 8b add x0, sp, wzr, uxth #2 + libdis_test+0xd8: e0 2f 3f 8b add x0, sp, wzr, uxth #3 + libdis_test+0xdc: e0 33 3f 8b add x0, sp, wzr, uxth #4 + libdis_test+0xe0: ff 61 3e 8b add sp, x15, x30, lsl #0 + libdis_test+0xe4: ff 21 3e 8b add sp, x15, w30, uxth #0 + libdis_test+0xe8: e0 01 1e 0b add w0, w15, w30 + libdis_test+0xec: e0 41 3e 0b add w0, w15, w30, uxtw #0 + libdis_test+0xf0: e0 41 3e 0b add w0, w15, w30, uxtw #0 + libdis_test+0xf4: e0 45 3e 0b add w0, w15, w30, uxtw #1 + libdis_test+0xf8: e0 49 3e 0b add w0, w15, w30, uxtw #2 + libdis_test+0xfc: e0 4d 3e 0b add w0, w15, w30, uxtw #3 + libdis_test+0x100: e0 51 3e 0b add w0, w15, w30, uxtw #4 + libdis_test+0x104: e0 43 3f 0b add w0, wsp, wzr, uxtw #0 + libdis_test+0x108: e0 43 3f 0b add w0, wsp, wzr, uxtw #0 + libdis_test+0x10c: e0 43 3f 0b add w0, wsp, wzr, uxtw #0 + libdis_test+0x110: e0 47 3f 0b add w0, wsp, wzr, uxtw #1 + libdis_test+0x114: e0 4b 3f 0b add w0, wsp, wzr, uxtw #2 + libdis_test+0x118: e0 4f 3f 0b add w0, wsp, wzr, uxtw #3 + libdis_test+0x11c: e0 53 3f 0b add w0, wsp, wzr, uxtw #4 + libdis_test+0x120: e0 41 3e 8b add x0, x15, w30, uxtw #0 + libdis_test+0x124: e0 41 3e 8b add x0, x15, w30, uxtw #0 + libdis_test+0x128: e0 45 3e 8b add x0, x15, w30, uxtw #1 + libdis_test+0x12c: e0 49 3e 8b add x0, x15, w30, uxtw #2 + libdis_test+0x130: e0 4d 3e 8b add x0, x15, w30, uxtw #3 + libdis_test+0x134: e0 51 3e 8b add x0, x15, w30, uxtw #4 + libdis_test+0x138: e0 43 3f 8b add x0, sp, wzr, uxtw #0 + libdis_test+0x13c: e0 43 3f 8b add x0, sp, wzr, uxtw #0 + libdis_test+0x140: e0 43 3f 8b add x0, sp, wzr, uxtw #0 + libdis_test+0x144: e0 47 3f 8b add x0, sp, wzr, uxtw #1 + libdis_test+0x148: e0 4b 3f 8b add x0, sp, wzr, uxtw #2 + libdis_test+0x14c: e0 4f 3f 8b add x0, sp, wzr, uxtw #3 + libdis_test+0x150: e0 53 3f 8b add x0, sp, wzr, uxtw #4 + libdis_test+0x154: ff 61 3e 8b add sp, x15, x30, lsl #0 + libdis_test+0x158: ff 41 3e 8b add sp, x15, w30, uxtw #0 + libdis_test+0x15c: e0 01 1e 0b add w0, w15, w30 + libdis_test+0x160: e0 61 3e 0b add w0, w15, w30, uxtx #0 + libdis_test+0x164: e0 61 3e 0b add w0, w15, w30, uxtx #0 + libdis_test+0x168: e0 65 3e 0b add w0, w15, w30, uxtx #1 + libdis_test+0x16c: e0 69 3e 0b add w0, w15, w30, uxtx #2 + libdis_test+0x170: e0 6d 3e 0b add w0, w15, w30, uxtx #3 + libdis_test+0x174: e0 71 3e 0b add w0, w15, w30, uxtx #4 + libdis_test+0x178: e0 43 3f 0b add w0, wsp, wzr, uxtw #0 + libdis_test+0x17c: e0 63 3f 0b add w0, wsp, wzr, uxtx #0 + libdis_test+0x180: e0 63 3f 0b add w0, wsp, wzr, uxtx #0 + libdis_test+0x184: e0 67 3f 0b add w0, wsp, wzr, uxtx #1 + libdis_test+0x188: e0 6b 3f 0b add w0, wsp, wzr, uxtx #2 + libdis_test+0x18c: e0 6f 3f 0b add w0, wsp, wzr, uxtx #3 + libdis_test+0x190: e0 73 3f 0b add w0, wsp, wzr, uxtx #4 + libdis_test+0x194: e0 61 3e 8b add x0, x15, x30, uxtx #0 + libdis_test+0x198: e0 61 3e 8b add x0, x15, x30, uxtx #0 + libdis_test+0x19c: e0 65 3e 8b add x0, x15, x30, uxtx #1 + libdis_test+0x1a0: e0 69 3e 8b add x0, x15, x30, uxtx #2 + libdis_test+0x1a4: e0 6d 3e 8b add x0, x15, x30, uxtx #3 + libdis_test+0x1a8: e0 71 3e 8b add x0, x15, x30, uxtx #4 + libdis_test+0x1ac: e0 43 3f 8b add x0, sp, wzr, uxtw #0 + libdis_test+0x1b0: e0 63 3f 8b add x0, sp, xzr, uxtx #0 + libdis_test+0x1b4: e0 63 3f 8b add x0, sp, xzr, uxtx #0 + libdis_test+0x1b8: e0 67 3f 8b add x0, sp, xzr, uxtx #1 + libdis_test+0x1bc: e0 6b 3f 8b add x0, sp, xzr, uxtx #2 + libdis_test+0x1c0: e0 6f 3f 8b add x0, sp, xzr, uxtx #3 + libdis_test+0x1c4: e0 73 3f 8b add x0, sp, xzr, uxtx #4 + libdis_test+0x1c8: ff 61 3e 8b add sp, x15, x30, lsl #0 + libdis_test+0x1cc: ff 61 3e 8b add sp, x15, x30, lsl #0 + libdis_test+0x1d0: e0 01 1e 0b add w0, w15, w30 + libdis_test+0x1d4: e0 81 3e 0b add w0, w15, w30, sxtb #0 + libdis_test+0x1d8: e0 81 3e 0b add w0, w15, w30, sxtb #0 + libdis_test+0x1dc: e0 85 3e 0b add w0, w15, w30, sxtb #1 + libdis_test+0x1e0: e0 89 3e 0b add w0, w15, w30, sxtb #2 + libdis_test+0x1e4: e0 8d 3e 0b add w0, w15, w30, sxtb #3 + libdis_test+0x1e8: e0 91 3e 0b add w0, w15, w30, sxtb #4 + libdis_test+0x1ec: e0 43 3f 0b add w0, wsp, wzr, uxtw #0 + libdis_test+0x1f0: e0 83 3f 0b add w0, wsp, wzr, sxtb #0 + libdis_test+0x1f4: e0 83 3f 0b add w0, wsp, wzr, sxtb #0 + libdis_test+0x1f8: e0 87 3f 0b add w0, wsp, wzr, sxtb #1 + libdis_test+0x1fc: e0 8b 3f 0b add w0, wsp, wzr, sxtb #2 + libdis_test+0x200: e0 8f 3f 0b add w0, wsp, wzr, sxtb #3 + libdis_test+0x204: e0 93 3f 0b add w0, wsp, wzr, sxtb #4 + libdis_test+0x208: e0 81 3e 8b add x0, x15, w30, sxtb #0 + libdis_test+0x20c: e0 81 3e 8b add x0, x15, w30, sxtb #0 + libdis_test+0x210: e0 85 3e 8b add x0, x15, w30, sxtb #1 + libdis_test+0x214: e0 89 3e 8b add x0, x15, w30, sxtb #2 + libdis_test+0x218: e0 8d 3e 8b add x0, x15, w30, sxtb #3 + libdis_test+0x21c: e0 91 3e 8b add x0, x15, w30, sxtb #4 + libdis_test+0x220: e0 43 3f 8b add x0, sp, wzr, uxtw #0 + libdis_test+0x224: e0 83 3f 8b add x0, sp, wzr, sxtb #0 + libdis_test+0x228: e0 83 3f 8b add x0, sp, wzr, sxtb #0 + libdis_test+0x22c: e0 87 3f 8b add x0, sp, wzr, sxtb #1 + libdis_test+0x230: e0 8b 3f 8b add x0, sp, wzr, sxtb #2 + libdis_test+0x234: e0 8f 3f 8b add x0, sp, wzr, sxtb #3 + libdis_test+0x238: e0 93 3f 8b add x0, sp, wzr, sxtb #4 + libdis_test+0x23c: ff 61 3e 8b add sp, x15, x30, lsl #0 + libdis_test+0x240: ff 81 3e 8b add sp, x15, w30, sxtb #0 + libdis_test+0x244: e0 01 1e 0b add w0, w15, w30 + libdis_test+0x248: e0 a1 3e 0b add w0, w15, w30, sxth #0 + libdis_test+0x24c: e0 a1 3e 0b add w0, w15, w30, sxth #0 + libdis_test+0x250: e0 a5 3e 0b add w0, w15, w30, sxth #1 + libdis_test+0x254: e0 a9 3e 0b add w0, w15, w30, sxth #2 + libdis_test+0x258: e0 ad 3e 0b add w0, w15, w30, sxth #3 + libdis_test+0x25c: e0 b1 3e 0b add w0, w15, w30, sxth #4 + libdis_test+0x260: e0 43 3f 0b add w0, wsp, wzr, uxtw #0 + libdis_test+0x264: e0 a3 3f 0b add w0, wsp, wzr, sxth #0 + libdis_test+0x268: e0 a3 3f 0b add w0, wsp, wzr, sxth #0 + libdis_test+0x26c: e0 a7 3f 0b add w0, wsp, wzr, sxth #1 + libdis_test+0x270: e0 ab 3f 0b add w0, wsp, wzr, sxth #2 + libdis_test+0x274: e0 af 3f 0b add w0, wsp, wzr, sxth #3 + libdis_test+0x278: e0 b3 3f 0b add w0, wsp, wzr, sxth #4 + libdis_test+0x27c: e0 a1 3e 8b add x0, x15, w30, sxth #0 + libdis_test+0x280: e0 a1 3e 8b add x0, x15, w30, sxth #0 + libdis_test+0x284: e0 a5 3e 8b add x0, x15, w30, sxth #1 + libdis_test+0x288: e0 a9 3e 8b add x0, x15, w30, sxth #2 + libdis_test+0x28c: e0 ad 3e 8b add x0, x15, w30, sxth #3 + libdis_test+0x290: e0 b1 3e 8b add x0, x15, w30, sxth #4 + libdis_test+0x294: e0 43 3f 8b add x0, sp, wzr, uxtw #0 + libdis_test+0x298: e0 a3 3f 8b add x0, sp, wzr, sxth #0 + libdis_test+0x29c: e0 a3 3f 8b add x0, sp, wzr, sxth #0 + libdis_test+0x2a0: e0 a7 3f 8b add x0, sp, wzr, sxth #1 + libdis_test+0x2a4: e0 ab 3f 8b add x0, sp, wzr, sxth #2 + libdis_test+0x2a8: e0 af 3f 8b add x0, sp, wzr, sxth #3 + libdis_test+0x2ac: e0 b3 3f 8b add x0, sp, wzr, sxth #4 + libdis_test+0x2b0: ff 61 3e 8b add sp, x15, x30, lsl #0 + libdis_test+0x2b4: ff a1 3e 8b add sp, x15, w30, sxth #0 + libdis_test+0x2b8: e0 01 1e 0b add w0, w15, w30 + libdis_test+0x2bc: e0 c1 3e 0b add w0, w15, w30, sxtw #0 + libdis_test+0x2c0: e0 c1 3e 0b add w0, w15, w30, sxtw #0 + libdis_test+0x2c4: e0 c5 3e 0b add w0, w15, w30, sxtw #1 + libdis_test+0x2c8: e0 c9 3e 0b add w0, w15, w30, sxtw #2 + libdis_test+0x2cc: e0 cd 3e 0b add w0, w15, w30, sxtw #3 + libdis_test+0x2d0: e0 d1 3e 0b add w0, w15, w30, sxtw #4 + libdis_test+0x2d4: e0 43 3f 0b add w0, wsp, wzr, uxtw #0 + libdis_test+0x2d8: e0 c3 3f 0b add w0, wsp, wzr, sxtw #0 + libdis_test+0x2dc: e0 c3 3f 0b add w0, wsp, wzr, sxtw #0 + libdis_test+0x2e0: e0 c7 3f 0b add w0, wsp, wzr, sxtw #1 + libdis_test+0x2e4: e0 cb 3f 0b add w0, wsp, wzr, sxtw #2 + libdis_test+0x2e8: e0 cf 3f 0b add w0, wsp, wzr, sxtw #3 + libdis_test+0x2ec: e0 d3 3f 0b add w0, wsp, wzr, sxtw #4 + libdis_test+0x2f0: e0 c1 3e 8b add x0, x15, w30, sxtw #0 + libdis_test+0x2f4: e0 c1 3e 8b add x0, x15, w30, sxtw #0 + libdis_test+0x2f8: e0 c5 3e 8b add x0, x15, w30, sxtw #1 + libdis_test+0x2fc: e0 c9 3e 8b add x0, x15, w30, sxtw #2 + libdis_test+0x300: e0 cd 3e 8b add x0, x15, w30, sxtw #3 + libdis_test+0x304: e0 d1 3e 8b add x0, x15, w30, sxtw #4 + libdis_test+0x308: e0 43 3f 8b add x0, sp, wzr, uxtw #0 + libdis_test+0x30c: e0 c3 3f 8b add x0, sp, wzr, sxtw #0 + libdis_test+0x310: e0 c3 3f 8b add x0, sp, wzr, sxtw #0 + libdis_test+0x314: e0 c7 3f 8b add x0, sp, wzr, sxtw #1 + libdis_test+0x318: e0 cb 3f 8b add x0, sp, wzr, sxtw #2 + libdis_test+0x31c: e0 cf 3f 8b add x0, sp, wzr, sxtw #3 + libdis_test+0x320: e0 d3 3f 8b add x0, sp, wzr, sxtw #4 + libdis_test+0x324: ff 61 3e 8b add sp, x15, x30, lsl #0 + libdis_test+0x328: ff c1 3e 8b add sp, x15, w30, sxtw #0 + libdis_test+0x32c: e0 01 1e 0b add w0, w15, w30 + libdis_test+0x330: e0 e1 3e 0b add w0, w15, w30, sxtx #0 + libdis_test+0x334: e0 e1 3e 0b add w0, w15, w30, sxtx #0 + libdis_test+0x338: e0 e5 3e 0b add w0, w15, w30, sxtx #1 + libdis_test+0x33c: e0 e9 3e 0b add w0, w15, w30, sxtx #2 + libdis_test+0x340: e0 ed 3e 0b add w0, w15, w30, sxtx #3 + libdis_test+0x344: e0 f1 3e 0b add w0, w15, w30, sxtx #4 + libdis_test+0x348: e0 43 3f 0b add w0, wsp, wzr, uxtw #0 + libdis_test+0x34c: e0 e3 3f 0b add w0, wsp, wzr, sxtx #0 + libdis_test+0x350: e0 e3 3f 0b add w0, wsp, wzr, sxtx #0 + libdis_test+0x354: e0 e7 3f 0b add w0, wsp, wzr, sxtx #1 + libdis_test+0x358: e0 eb 3f 0b add w0, wsp, wzr, sxtx #2 + libdis_test+0x35c: e0 ef 3f 0b add w0, wsp, wzr, sxtx #3 + libdis_test+0x360: e0 f3 3f 0b add w0, wsp, wzr, sxtx #4 + libdis_test+0x364: e0 e1 3e 8b add x0, x15, x30, sxtx #0 + libdis_test+0x368: e0 e1 3e 8b add x0, x15, x30, sxtx #0 + libdis_test+0x36c: e0 e5 3e 8b add x0, x15, x30, sxtx #1 + libdis_test+0x370: e0 e9 3e 8b add x0, x15, x30, sxtx #2 + libdis_test+0x374: e0 ed 3e 8b add x0, x15, x30, sxtx #3 + libdis_test+0x378: e0 f1 3e 8b add x0, x15, x30, sxtx #4 + libdis_test+0x37c: e0 43 3f 8b add x0, sp, wzr, uxtw #0 + libdis_test+0x380: e0 e3 3f 8b add x0, sp, xzr, sxtx #0 + libdis_test+0x384: e0 e3 3f 8b add x0, sp, xzr, sxtx #0 + libdis_test+0x388: e0 e7 3f 8b add x0, sp, xzr, sxtx #1 + libdis_test+0x38c: e0 eb 3f 8b add x0, sp, xzr, sxtx #2 + libdis_test+0x390: e0 ef 3f 8b add x0, sp, xzr, sxtx #3 + libdis_test+0x394: e0 f3 3f 8b add x0, sp, xzr, sxtx #4 + libdis_test+0x398: ff 61 3e 8b add sp, x15, x30, lsl #0 + libdis_test+0x39c: ff e1 3e 8b add sp, x15, x30, sxtx #0 + libdis_test+0x3a0: e0 01 1e 2b adds w0, w15, w30 + libdis_test+0x3a4: e0 01 3e 2b adds w0, w15, w30, uxtb #0 + libdis_test+0x3a8: e0 01 3e 2b adds w0, w15, w30, uxtb #0 + libdis_test+0x3ac: e0 05 3e 2b adds w0, w15, w30, uxtb #1 + libdis_test+0x3b0: e0 09 3e 2b adds w0, w15, w30, uxtb #2 + libdis_test+0x3b4: e0 0d 3e 2b adds w0, w15, w30, uxtb #3 + libdis_test+0x3b8: e0 11 3e 2b adds w0, w15, w30, uxtb #4 + libdis_test+0x3bc: e0 43 3f 2b adds w0, wsp, wzr, uxtw #0 + libdis_test+0x3c0: e0 03 3f 2b adds w0, wsp, wzr, uxtb #0 + libdis_test+0x3c4: e0 03 3f 2b adds w0, wsp, wzr, uxtb #0 + libdis_test+0x3c8: e0 07 3f 2b adds w0, wsp, wzr, uxtb #1 + libdis_test+0x3cc: e0 0b 3f 2b adds w0, wsp, wzr, uxtb #2 + libdis_test+0x3d0: e0 0f 3f 2b adds w0, wsp, wzr, uxtb #3 + libdis_test+0x3d4: e0 13 3f 2b adds w0, wsp, wzr, uxtb #4 + libdis_test+0x3d8: e0 01 3e ab adds x0, x15, w30, uxtb #0 + libdis_test+0x3dc: e0 01 3e ab adds x0, x15, w30, uxtb #0 + libdis_test+0x3e0: e0 05 3e ab adds x0, x15, w30, uxtb #1 + libdis_test+0x3e4: e0 09 3e ab adds x0, x15, w30, uxtb #2 + libdis_test+0x3e8: e0 0d 3e ab adds x0, x15, w30, uxtb #3 + libdis_test+0x3ec: e0 11 3e ab adds x0, x15, w30, uxtb #4 + libdis_test+0x3f0: e0 43 3f ab adds x0, sp, wzr, uxtw #0 + libdis_test+0x3f4: e0 03 3f ab adds x0, sp, wzr, uxtb #0 + libdis_test+0x3f8: e0 03 3f ab adds x0, sp, wzr, uxtb #0 + libdis_test+0x3fc: e0 07 3f ab adds x0, sp, wzr, uxtb #1 + libdis_test+0x400: e0 0b 3f ab adds x0, sp, wzr, uxtb #2 + libdis_test+0x404: e0 0f 3f ab adds x0, sp, wzr, uxtb #3 + libdis_test+0x408: e0 13 3f ab adds x0, sp, wzr, uxtb #4 + libdis_test+0x40c: ff 01 3e ab adds sp, x15, w30, uxtb #0 + libdis_test+0x410: ff 05 3e ab adds sp, x15, w30, uxtb #1 + libdis_test+0x414: ff 09 3e ab adds sp, x15, w30, uxtb #2 + libdis_test+0x418: ff 0d 3e ab adds sp, x15, w30, uxtb #3 + libdis_test+0x41c: ff 11 3e ab adds sp, x15, w30, uxtb #4 + libdis_test+0x420: e0 01 1e 2b adds w0, w15, w30 + libdis_test+0x424: e0 21 3e 2b adds w0, w15, w30, uxth #0 + libdis_test+0x428: e0 21 3e 2b adds w0, w15, w30, uxth #0 + libdis_test+0x42c: e0 25 3e 2b adds w0, w15, w30, uxth #1 + libdis_test+0x430: e0 29 3e 2b adds w0, w15, w30, uxth #2 + libdis_test+0x434: e0 2d 3e 2b adds w0, w15, w30, uxth #3 + libdis_test+0x438: e0 31 3e 2b adds w0, w15, w30, uxth #4 + libdis_test+0x43c: e0 43 3f 2b adds w0, wsp, wzr, uxtw #0 + libdis_test+0x440: e0 23 3f 2b adds w0, wsp, wzr, uxth #0 + libdis_test+0x444: e0 23 3f 2b adds w0, wsp, wzr, uxth #0 + libdis_test+0x448: e0 27 3f 2b adds w0, wsp, wzr, uxth #1 + libdis_test+0x44c: e0 2b 3f 2b adds w0, wsp, wzr, uxth #2 + libdis_test+0x450: e0 2f 3f 2b adds w0, wsp, wzr, uxth #3 + libdis_test+0x454: e0 33 3f 2b adds w0, wsp, wzr, uxth #4 + libdis_test+0x458: e0 21 3e ab adds x0, x15, w30, uxth #0 + libdis_test+0x45c: e0 21 3e ab adds x0, x15, w30, uxth #0 + libdis_test+0x460: e0 25 3e ab adds x0, x15, w30, uxth #1 + libdis_test+0x464: e0 29 3e ab adds x0, x15, w30, uxth #2 + libdis_test+0x468: e0 2d 3e ab adds x0, x15, w30, uxth #3 + libdis_test+0x46c: e0 31 3e ab adds x0, x15, w30, uxth #4 + libdis_test+0x470: e0 43 3f ab adds x0, sp, wzr, uxtw #0 + libdis_test+0x474: e0 23 3f ab adds x0, sp, wzr, uxth #0 + libdis_test+0x478: e0 23 3f ab adds x0, sp, wzr, uxth #0 + libdis_test+0x47c: e0 27 3f ab adds x0, sp, wzr, uxth #1 + libdis_test+0x480: e0 2b 3f ab adds x0, sp, wzr, uxth #2 + libdis_test+0x484: e0 2f 3f ab adds x0, sp, wzr, uxth #3 + libdis_test+0x488: e0 33 3f ab adds x0, sp, wzr, uxth #4 + libdis_test+0x48c: ff 21 3e ab adds sp, x15, w30, uxth #0 + libdis_test+0x490: ff 25 3e ab adds sp, x15, w30, uxth #1 + libdis_test+0x494: ff 29 3e ab adds sp, x15, w30, uxth #2 + libdis_test+0x498: ff 2d 3e ab adds sp, x15, w30, uxth #3 + libdis_test+0x49c: ff 31 3e ab adds sp, x15, w30, uxth #4 + libdis_test+0x4a0: e0 01 1e 2b adds w0, w15, w30 + libdis_test+0x4a4: e0 41 3e 2b adds w0, w15, w30, uxtw #0 + libdis_test+0x4a8: e0 41 3e 2b adds w0, w15, w30, uxtw #0 + libdis_test+0x4ac: e0 45 3e 2b adds w0, w15, w30, uxtw #1 + libdis_test+0x4b0: e0 49 3e 2b adds w0, w15, w30, uxtw #2 + libdis_test+0x4b4: e0 4d 3e 2b adds w0, w15, w30, uxtw #3 + libdis_test+0x4b8: e0 51 3e 2b adds w0, w15, w30, uxtw #4 + libdis_test+0x4bc: e0 43 3f 2b adds w0, wsp, wzr, uxtw #0 + libdis_test+0x4c0: e0 43 3f 2b adds w0, wsp, wzr, uxtw #0 + libdis_test+0x4c4: e0 43 3f 2b adds w0, wsp, wzr, uxtw #0 + libdis_test+0x4c8: e0 47 3f 2b adds w0, wsp, wzr, uxtw #1 + libdis_test+0x4cc: e0 4b 3f 2b adds w0, wsp, wzr, uxtw #2 + libdis_test+0x4d0: e0 4f 3f 2b adds w0, wsp, wzr, uxtw #3 + libdis_test+0x4d4: e0 53 3f 2b adds w0, wsp, wzr, uxtw #4 + libdis_test+0x4d8: e0 41 3e ab adds x0, x15, w30, uxtw #0 + libdis_test+0x4dc: e0 41 3e ab adds x0, x15, w30, uxtw #0 + libdis_test+0x4e0: e0 45 3e ab adds x0, x15, w30, uxtw #1 + libdis_test+0x4e4: e0 49 3e ab adds x0, x15, w30, uxtw #2 + libdis_test+0x4e8: e0 4d 3e ab adds x0, x15, w30, uxtw #3 + libdis_test+0x4ec: e0 51 3e ab adds x0, x15, w30, uxtw #4 + libdis_test+0x4f0: e0 43 3f ab adds x0, sp, wzr, uxtw #0 + libdis_test+0x4f4: e0 43 3f ab adds x0, sp, wzr, uxtw #0 + libdis_test+0x4f8: e0 43 3f ab adds x0, sp, wzr, uxtw #0 + libdis_test+0x4fc: e0 47 3f ab adds x0, sp, wzr, uxtw #1 + libdis_test+0x500: e0 4b 3f ab adds x0, sp, wzr, uxtw #2 + libdis_test+0x504: e0 4f 3f ab adds x0, sp, wzr, uxtw #3 + libdis_test+0x508: e0 53 3f ab adds x0, sp, wzr, uxtw #4 + libdis_test+0x50c: ff 41 3e ab adds sp, x15, w30, uxtw #0 + libdis_test+0x510: ff 45 3e ab adds sp, x15, w30, uxtw #1 + libdis_test+0x514: ff 49 3e ab adds sp, x15, w30, uxtw #2 + libdis_test+0x518: ff 4d 3e ab adds sp, x15, w30, uxtw #3 + libdis_test+0x51c: ff 51 3e ab adds sp, x15, w30, uxtw #4 + libdis_test+0x520: e0 01 1e 2b adds w0, w15, w30 + libdis_test+0x524: e0 61 3e 2b adds w0, w15, w30, uxtx #0 + libdis_test+0x528: e0 61 3e 2b adds w0, w15, w30, uxtx #0 + libdis_test+0x52c: e0 65 3e 2b adds w0, w15, w30, uxtx #1 + libdis_test+0x530: e0 69 3e 2b adds w0, w15, w30, uxtx #2 + libdis_test+0x534: e0 6d 3e 2b adds w0, w15, w30, uxtx #3 + libdis_test+0x538: e0 71 3e 2b adds w0, w15, w30, uxtx #4 + libdis_test+0x53c: e0 43 3f 2b adds w0, wsp, wzr, uxtw #0 + libdis_test+0x540: e0 63 3f 2b adds w0, wsp, wzr, uxtx #0 + libdis_test+0x544: e0 63 3f 2b adds w0, wsp, wzr, uxtx #0 + libdis_test+0x548: e0 67 3f 2b adds w0, wsp, wzr, uxtx #1 + libdis_test+0x54c: e0 6b 3f 2b adds w0, wsp, wzr, uxtx #2 + libdis_test+0x550: e0 6f 3f 2b adds w0, wsp, wzr, uxtx #3 + libdis_test+0x554: e0 73 3f 2b adds w0, wsp, wzr, uxtx #4 + libdis_test+0x558: e0 61 3e ab adds x0, x15, x30, uxtx #0 + libdis_test+0x55c: e0 61 3e ab adds x0, x15, x30, uxtx #0 + libdis_test+0x560: e0 65 3e ab adds x0, x15, x30, uxtx #1 + libdis_test+0x564: e0 69 3e ab adds x0, x15, x30, uxtx #2 + libdis_test+0x568: e0 6d 3e ab adds x0, x15, x30, uxtx #3 + libdis_test+0x56c: e0 71 3e ab adds x0, x15, x30, uxtx #4 + libdis_test+0x570: e0 43 3f ab adds x0, sp, wzr, uxtw #0 + libdis_test+0x574: e0 63 3f ab adds x0, sp, xzr, uxtx #0 + libdis_test+0x578: e0 63 3f ab adds x0, sp, xzr, uxtx #0 + libdis_test+0x57c: e0 67 3f ab adds x0, sp, xzr, uxtx #1 + libdis_test+0x580: e0 6b 3f ab adds x0, sp, xzr, uxtx #2 + libdis_test+0x584: e0 6f 3f ab adds x0, sp, xzr, uxtx #3 + libdis_test+0x588: e0 73 3f ab adds x0, sp, xzr, uxtx #4 + libdis_test+0x58c: ff 61 3e ab adds sp, x15, x30, lsl #0 + libdis_test+0x590: ff 65 3e ab adds sp, x15, x30, lsl #1 + libdis_test+0x594: ff 69 3e ab adds sp, x15, x30, lsl #2 + libdis_test+0x598: ff 6d 3e ab adds sp, x15, x30, lsl #3 + libdis_test+0x59c: ff 71 3e ab adds sp, x15, x30, lsl #4 + libdis_test+0x5a0: e0 01 1e 2b adds w0, w15, w30 + libdis_test+0x5a4: e0 81 3e 2b adds w0, w15, w30, sxtb #0 + libdis_test+0x5a8: e0 81 3e 2b adds w0, w15, w30, sxtb #0 + libdis_test+0x5ac: e0 85 3e 2b adds w0, w15, w30, sxtb #1 + libdis_test+0x5b0: e0 89 3e 2b adds w0, w15, w30, sxtb #2 + libdis_test+0x5b4: e0 8d 3e 2b adds w0, w15, w30, sxtb #3 + libdis_test+0x5b8: e0 91 3e 2b adds w0, w15, w30, sxtb #4 + libdis_test+0x5bc: e0 43 3f 2b adds w0, wsp, wzr, uxtw #0 + libdis_test+0x5c0: e0 83 3f 2b adds w0, wsp, wzr, sxtb #0 + libdis_test+0x5c4: e0 83 3f 2b adds w0, wsp, wzr, sxtb #0 + libdis_test+0x5c8: e0 87 3f 2b adds w0, wsp, wzr, sxtb #1 + libdis_test+0x5cc: e0 8b 3f 2b adds w0, wsp, wzr, sxtb #2 + libdis_test+0x5d0: e0 8f 3f 2b adds w0, wsp, wzr, sxtb #3 + libdis_test+0x5d4: e0 93 3f 2b adds w0, wsp, wzr, sxtb #4 + libdis_test+0x5d8: e0 81 3e ab adds x0, x15, w30, sxtb #0 + libdis_test+0x5dc: e0 81 3e ab adds x0, x15, w30, sxtb #0 + libdis_test+0x5e0: e0 85 3e ab adds x0, x15, w30, sxtb #1 + libdis_test+0x5e4: e0 89 3e ab adds x0, x15, w30, sxtb #2 + libdis_test+0x5e8: e0 8d 3e ab adds x0, x15, w30, sxtb #3 + libdis_test+0x5ec: e0 91 3e ab adds x0, x15, w30, sxtb #4 + libdis_test+0x5f0: e0 43 3f ab adds x0, sp, wzr, uxtw #0 + libdis_test+0x5f4: e0 83 3f ab adds x0, sp, wzr, sxtb #0 + libdis_test+0x5f8: e0 83 3f ab adds x0, sp, wzr, sxtb #0 + libdis_test+0x5fc: e0 87 3f ab adds x0, sp, wzr, sxtb #1 + libdis_test+0x600: e0 8b 3f ab adds x0, sp, wzr, sxtb #2 + libdis_test+0x604: e0 8f 3f ab adds x0, sp, wzr, sxtb #3 + libdis_test+0x608: e0 93 3f ab adds x0, sp, wzr, sxtb #4 + libdis_test+0x60c: ff 81 3e ab adds sp, x15, w30, sxtb #0 + libdis_test+0x610: ff 85 3e ab adds sp, x15, w30, sxtb #1 + libdis_test+0x614: ff 89 3e ab adds sp, x15, w30, sxtb #2 + libdis_test+0x618: ff 8d 3e ab adds sp, x15, w30, sxtb #3 + libdis_test+0x61c: ff 91 3e ab adds sp, x15, w30, sxtb #4 + libdis_test+0x620: e0 01 1e 2b adds w0, w15, w30 + libdis_test+0x624: e0 a1 3e 2b adds w0, w15, w30, sxth #0 + libdis_test+0x628: e0 a1 3e 2b adds w0, w15, w30, sxth #0 + libdis_test+0x62c: e0 a5 3e 2b adds w0, w15, w30, sxth #1 + libdis_test+0x630: e0 a9 3e 2b adds w0, w15, w30, sxth #2 + libdis_test+0x634: e0 ad 3e 2b adds w0, w15, w30, sxth #3 + libdis_test+0x638: e0 b1 3e 2b adds w0, w15, w30, sxth #4 + libdis_test+0x63c: e0 43 3f 2b adds w0, wsp, wzr, uxtw #0 + libdis_test+0x640: e0 a3 3f 2b adds w0, wsp, wzr, sxth #0 + libdis_test+0x644: e0 a3 3f 2b adds w0, wsp, wzr, sxth #0 + libdis_test+0x648: e0 a7 3f 2b adds w0, wsp, wzr, sxth #1 + libdis_test+0x64c: e0 ab 3f 2b adds w0, wsp, wzr, sxth #2 + libdis_test+0x650: e0 af 3f 2b adds w0, wsp, wzr, sxth #3 + libdis_test+0x654: e0 b3 3f 2b adds w0, wsp, wzr, sxth #4 + libdis_test+0x658: e0 a1 3e ab adds x0, x15, w30, sxth #0 + libdis_test+0x65c: e0 a1 3e ab adds x0, x15, w30, sxth #0 + libdis_test+0x660: e0 a5 3e ab adds x0, x15, w30, sxth #1 + libdis_test+0x664: e0 a9 3e ab adds x0, x15, w30, sxth #2 + libdis_test+0x668: e0 ad 3e ab adds x0, x15, w30, sxth #3 + libdis_test+0x66c: e0 b1 3e ab adds x0, x15, w30, sxth #4 + libdis_test+0x670: e0 43 3f ab adds x0, sp, wzr, uxtw #0 + libdis_test+0x674: e0 a3 3f ab adds x0, sp, wzr, sxth #0 + libdis_test+0x678: e0 a3 3f ab adds x0, sp, wzr, sxth #0 + libdis_test+0x67c: e0 a7 3f ab adds x0, sp, wzr, sxth #1 + libdis_test+0x680: e0 ab 3f ab adds x0, sp, wzr, sxth #2 + libdis_test+0x684: e0 af 3f ab adds x0, sp, wzr, sxth #3 + libdis_test+0x688: e0 b3 3f ab adds x0, sp, wzr, sxth #4 + libdis_test+0x68c: ff a1 3e ab adds sp, x15, w30, sxth #0 + libdis_test+0x690: ff a5 3e ab adds sp, x15, w30, sxth #1 + libdis_test+0x694: ff a9 3e ab adds sp, x15, w30, sxth #2 + libdis_test+0x698: ff ad 3e ab adds sp, x15, w30, sxth #3 + libdis_test+0x69c: ff b1 3e ab adds sp, x15, w30, sxth #4 + libdis_test+0x6a0: e0 01 1e 2b adds w0, w15, w30 + libdis_test+0x6a4: e0 c1 3e 2b adds w0, w15, w30, sxtw #0 + libdis_test+0x6a8: e0 c1 3e 2b adds w0, w15, w30, sxtw #0 + libdis_test+0x6ac: e0 c5 3e 2b adds w0, w15, w30, sxtw #1 + libdis_test+0x6b0: e0 c9 3e 2b adds w0, w15, w30, sxtw #2 + libdis_test+0x6b4: e0 cd 3e 2b adds w0, w15, w30, sxtw #3 + libdis_test+0x6b8: e0 d1 3e 2b adds w0, w15, w30, sxtw #4 + libdis_test+0x6bc: e0 43 3f 2b adds w0, wsp, wzr, uxtw #0 + libdis_test+0x6c0: e0 c3 3f 2b adds w0, wsp, wzr, sxtw #0 + libdis_test+0x6c4: e0 c3 3f 2b adds w0, wsp, wzr, sxtw #0 + libdis_test+0x6c8: e0 c7 3f 2b adds w0, wsp, wzr, sxtw #1 + libdis_test+0x6cc: e0 cb 3f 2b adds w0, wsp, wzr, sxtw #2 + libdis_test+0x6d0: e0 cf 3f 2b adds w0, wsp, wzr, sxtw #3 + libdis_test+0x6d4: e0 d3 3f 2b adds w0, wsp, wzr, sxtw #4 + libdis_test+0x6d8: e0 c1 3e ab adds x0, x15, w30, sxtw #0 + libdis_test+0x6dc: e0 c1 3e ab adds x0, x15, w30, sxtw #0 + libdis_test+0x6e0: e0 c5 3e ab adds x0, x15, w30, sxtw #1 + libdis_test+0x6e4: e0 c9 3e ab adds x0, x15, w30, sxtw #2 + libdis_test+0x6e8: e0 cd 3e ab adds x0, x15, w30, sxtw #3 + libdis_test+0x6ec: e0 d1 3e ab adds x0, x15, w30, sxtw #4 + libdis_test+0x6f0: e0 43 3f ab adds x0, sp, wzr, uxtw #0 + libdis_test+0x6f4: e0 c3 3f ab adds x0, sp, wzr, sxtw #0 + libdis_test+0x6f8: e0 c3 3f ab adds x0, sp, wzr, sxtw #0 + libdis_test+0x6fc: e0 c7 3f ab adds x0, sp, wzr, sxtw #1 + libdis_test+0x700: e0 cb 3f ab adds x0, sp, wzr, sxtw #2 + libdis_test+0x704: e0 cf 3f ab adds x0, sp, wzr, sxtw #3 + libdis_test+0x708: e0 d3 3f ab adds x0, sp, wzr, sxtw #4 + libdis_test+0x70c: ff c1 3e ab adds sp, x15, w30, sxtw #0 + libdis_test+0x710: ff c5 3e ab adds sp, x15, w30, sxtw #1 + libdis_test+0x714: ff c9 3e ab adds sp, x15, w30, sxtw #2 + libdis_test+0x718: ff cd 3e ab adds sp, x15, w30, sxtw #3 + libdis_test+0x71c: ff d1 3e ab adds sp, x15, w30, sxtw #4 + libdis_test+0x720: e0 01 1e 2b adds w0, w15, w30 + libdis_test+0x724: e0 e1 3e 2b adds w0, w15, w30, sxtx #0 + libdis_test+0x728: e0 e1 3e 2b adds w0, w15, w30, sxtx #0 + libdis_test+0x72c: e0 e5 3e 2b adds w0, w15, w30, sxtx #1 + libdis_test+0x730: e0 e9 3e 2b adds w0, w15, w30, sxtx #2 + libdis_test+0x734: e0 ed 3e 2b adds w0, w15, w30, sxtx #3 + libdis_test+0x738: e0 f1 3e 2b adds w0, w15, w30, sxtx #4 + libdis_test+0x73c: e0 43 3f 2b adds w0, wsp, wzr, uxtw #0 + libdis_test+0x740: e0 e3 3f 2b adds w0, wsp, wzr, sxtx #0 + libdis_test+0x744: e0 e3 3f 2b adds w0, wsp, wzr, sxtx #0 + libdis_test+0x748: e0 e7 3f 2b adds w0, wsp, wzr, sxtx #1 + libdis_test+0x74c: e0 eb 3f 2b adds w0, wsp, wzr, sxtx #2 + libdis_test+0x750: e0 ef 3f 2b adds w0, wsp, wzr, sxtx #3 + libdis_test+0x754: e0 f3 3f 2b adds w0, wsp, wzr, sxtx #4 + libdis_test+0x758: e0 e1 3e ab adds x0, x15, x30, sxtx #0 + libdis_test+0x75c: e0 e1 3e ab adds x0, x15, x30, sxtx #0 + libdis_test+0x760: e0 e5 3e ab adds x0, x15, x30, sxtx #1 + libdis_test+0x764: e0 e9 3e ab adds x0, x15, x30, sxtx #2 + libdis_test+0x768: e0 ed 3e ab adds x0, x15, x30, sxtx #3 + libdis_test+0x76c: e0 f1 3e ab adds x0, x15, x30, sxtx #4 + libdis_test+0x770: e0 43 3f ab adds x0, sp, wzr, uxtw #0 + libdis_test+0x774: e0 e3 3f ab adds x0, sp, xzr, sxtx #0 + libdis_test+0x778: e0 e3 3f ab adds x0, sp, xzr, sxtx #0 + libdis_test+0x77c: e0 e7 3f ab adds x0, sp, xzr, sxtx #1 + libdis_test+0x780: e0 eb 3f ab adds x0, sp, xzr, sxtx #2 + libdis_test+0x784: e0 ef 3f ab adds x0, sp, xzr, sxtx #3 + libdis_test+0x788: e0 f3 3f ab adds x0, sp, xzr, sxtx #4 + libdis_test+0x78c: ff e1 3e ab adds sp, x15, x30, sxtx #0 + libdis_test+0x790: ff e5 3e ab adds sp, x15, x30, sxtx #1 + libdis_test+0x794: ff e9 3e ab adds sp, x15, x30, sxtx #2 + libdis_test+0x798: ff ed 3e ab adds sp, x15, x30, sxtx #3 + libdis_test+0x79c: ff f1 3e ab adds sp, x15, x30, sxtx #4 + libdis_test+0x7a0: e0 01 1e 4b sub w0, w15, w30 + libdis_test+0x7a4: e0 01 3e 4b sub w0, w15, w30, uxtb #0 + libdis_test+0x7a8: e0 01 3e 4b sub w0, w15, w30, uxtb #0 + libdis_test+0x7ac: e0 05 3e 4b sub w0, w15, w30, uxtb #1 + libdis_test+0x7b0: e0 09 3e 4b sub w0, w15, w30, uxtb #2 + libdis_test+0x7b4: e0 0d 3e 4b sub w0, w15, w30, uxtb #3 + libdis_test+0x7b8: e0 11 3e 4b sub w0, w15, w30, uxtb #4 + libdis_test+0x7bc: e0 43 3f 4b sub w0, wsp, wzr, uxtw #0 + libdis_test+0x7c0: e0 03 3f 4b sub w0, wsp, wzr, uxtb #0 + libdis_test+0x7c4: e0 03 3f 4b sub w0, wsp, wzr, uxtb #0 + libdis_test+0x7c8: e0 07 3f 4b sub w0, wsp, wzr, uxtb #1 + libdis_test+0x7cc: e0 0b 3f 4b sub w0, wsp, wzr, uxtb #2 + libdis_test+0x7d0: e0 0f 3f 4b sub w0, wsp, wzr, uxtb #3 + libdis_test+0x7d4: e0 13 3f 4b sub w0, wsp, wzr, uxtb #4 + libdis_test+0x7d8: e0 01 3e cb sub x0, x15, w30, uxtb #0 + libdis_test+0x7dc: e0 01 3e cb sub x0, x15, w30, uxtb #0 + libdis_test+0x7e0: e0 05 3e cb sub x0, x15, w30, uxtb #1 + libdis_test+0x7e4: e0 09 3e cb sub x0, x15, w30, uxtb #2 + libdis_test+0x7e8: e0 0d 3e cb sub x0, x15, w30, uxtb #3 + libdis_test+0x7ec: e0 11 3e cb sub x0, x15, w30, uxtb #4 + libdis_test+0x7f0: e0 43 3f cb sub x0, sp, wzr, uxtw #0 + libdis_test+0x7f4: e0 03 3f cb sub x0, sp, wzr, uxtb #0 + libdis_test+0x7f8: e0 03 3f cb sub x0, sp, wzr, uxtb #0 + libdis_test+0x7fc: e0 07 3f cb sub x0, sp, wzr, uxtb #1 + libdis_test+0x800: e0 0b 3f cb sub x0, sp, wzr, uxtb #2 + libdis_test+0x804: e0 0f 3f cb sub x0, sp, wzr, uxtb #3 + libdis_test+0x808: e0 13 3f cb sub x0, sp, wzr, uxtb #4 + libdis_test+0x80c: ff 61 3e cb sub sp, x15, x30, lsl #0 + libdis_test+0x810: ff 01 3e cb sub sp, x15, w30, uxtb #0 + libdis_test+0x814: e0 01 1e 4b sub w0, w15, w30 + libdis_test+0x818: e0 21 3e 4b sub w0, w15, w30, uxth #0 + libdis_test+0x81c: e0 21 3e 4b sub w0, w15, w30, uxth #0 + libdis_test+0x820: e0 25 3e 4b sub w0, w15, w30, uxth #1 + libdis_test+0x824: e0 29 3e 4b sub w0, w15, w30, uxth #2 + libdis_test+0x828: e0 2d 3e 4b sub w0, w15, w30, uxth #3 + libdis_test+0x82c: e0 31 3e 4b sub w0, w15, w30, uxth #4 + libdis_test+0x830: e0 43 3f 4b sub w0, wsp, wzr, uxtw #0 + libdis_test+0x834: e0 23 3f 4b sub w0, wsp, wzr, uxth #0 + libdis_test+0x838: e0 23 3f 4b sub w0, wsp, wzr, uxth #0 + libdis_test+0x83c: e0 27 3f 4b sub w0, wsp, wzr, uxth #1 + libdis_test+0x840: e0 2b 3f 4b sub w0, wsp, wzr, uxth #2 + libdis_test+0x844: e0 2f 3f 4b sub w0, wsp, wzr, uxth #3 + libdis_test+0x848: e0 33 3f 4b sub w0, wsp, wzr, uxth #4 + libdis_test+0x84c: e0 21 3e cb sub x0, x15, w30, uxth #0 + libdis_test+0x850: e0 21 3e cb sub x0, x15, w30, uxth #0 + libdis_test+0x854: e0 25 3e cb sub x0, x15, w30, uxth #1 + libdis_test+0x858: e0 29 3e cb sub x0, x15, w30, uxth #2 + libdis_test+0x85c: e0 2d 3e cb sub x0, x15, w30, uxth #3 + libdis_test+0x860: e0 31 3e cb sub x0, x15, w30, uxth #4 + libdis_test+0x864: e0 43 3f cb sub x0, sp, wzr, uxtw #0 + libdis_test+0x868: e0 23 3f cb sub x0, sp, wzr, uxth #0 + libdis_test+0x86c: e0 23 3f cb sub x0, sp, wzr, uxth #0 + libdis_test+0x870: e0 27 3f cb sub x0, sp, wzr, uxth #1 + libdis_test+0x874: e0 2b 3f cb sub x0, sp, wzr, uxth #2 + libdis_test+0x878: e0 2f 3f cb sub x0, sp, wzr, uxth #3 + libdis_test+0x87c: e0 33 3f cb sub x0, sp, wzr, uxth #4 + libdis_test+0x880: ff 61 3e cb sub sp, x15, x30, lsl #0 + libdis_test+0x884: ff 21 3e cb sub sp, x15, w30, uxth #0 + libdis_test+0x888: e0 01 1e 4b sub w0, w15, w30 + libdis_test+0x88c: e0 41 3e 4b sub w0, w15, w30, uxtw #0 + libdis_test+0x890: e0 41 3e 4b sub w0, w15, w30, uxtw #0 + libdis_test+0x894: e0 45 3e 4b sub w0, w15, w30, uxtw #1 + libdis_test+0x898: e0 49 3e 4b sub w0, w15, w30, uxtw #2 + libdis_test+0x89c: e0 4d 3e 4b sub w0, w15, w30, uxtw #3 + libdis_test+0x8a0: e0 51 3e 4b sub w0, w15, w30, uxtw #4 + libdis_test+0x8a4: e0 43 3f 4b sub w0, wsp, wzr, uxtw #0 + libdis_test+0x8a8: e0 43 3f 4b sub w0, wsp, wzr, uxtw #0 + libdis_test+0x8ac: e0 43 3f 4b sub w0, wsp, wzr, uxtw #0 + libdis_test+0x8b0: e0 47 3f 4b sub w0, wsp, wzr, uxtw #1 + libdis_test+0x8b4: e0 4b 3f 4b sub w0, wsp, wzr, uxtw #2 + libdis_test+0x8b8: e0 4f 3f 4b sub w0, wsp, wzr, uxtw #3 + libdis_test+0x8bc: e0 53 3f 4b sub w0, wsp, wzr, uxtw #4 + libdis_test+0x8c0: e0 41 3e cb sub x0, x15, w30, uxtw #0 + libdis_test+0x8c4: e0 41 3e cb sub x0, x15, w30, uxtw #0 + libdis_test+0x8c8: e0 45 3e cb sub x0, x15, w30, uxtw #1 + libdis_test+0x8cc: e0 49 3e cb sub x0, x15, w30, uxtw #2 + libdis_test+0x8d0: e0 4d 3e cb sub x0, x15, w30, uxtw #3 + libdis_test+0x8d4: e0 51 3e cb sub x0, x15, w30, uxtw #4 + libdis_test+0x8d8: e0 43 3f cb sub x0, sp, wzr, uxtw #0 + libdis_test+0x8dc: e0 43 3f cb sub x0, sp, wzr, uxtw #0 + libdis_test+0x8e0: e0 43 3f cb sub x0, sp, wzr, uxtw #0 + libdis_test+0x8e4: e0 47 3f cb sub x0, sp, wzr, uxtw #1 + libdis_test+0x8e8: e0 4b 3f cb sub x0, sp, wzr, uxtw #2 + libdis_test+0x8ec: e0 4f 3f cb sub x0, sp, wzr, uxtw #3 + libdis_test+0x8f0: e0 53 3f cb sub x0, sp, wzr, uxtw #4 + libdis_test+0x8f4: ff 61 3e cb sub sp, x15, x30, lsl #0 + libdis_test+0x8f8: ff 41 3e cb sub sp, x15, w30, uxtw #0 + libdis_test+0x8fc: e0 01 1e 4b sub w0, w15, w30 + libdis_test+0x900: e0 61 3e 4b sub w0, w15, w30, uxtx #0 + libdis_test+0x904: e0 61 3e 4b sub w0, w15, w30, uxtx #0 + libdis_test+0x908: e0 65 3e 4b sub w0, w15, w30, uxtx #1 + libdis_test+0x90c: e0 69 3e 4b sub w0, w15, w30, uxtx #2 + libdis_test+0x910: e0 6d 3e 4b sub w0, w15, w30, uxtx #3 + libdis_test+0x914: e0 71 3e 4b sub w0, w15, w30, uxtx #4 + libdis_test+0x918: e0 43 3f 4b sub w0, wsp, wzr, uxtw #0 + libdis_test+0x91c: e0 63 3f 4b sub w0, wsp, wzr, uxtx #0 + libdis_test+0x920: e0 63 3f 4b sub w0, wsp, wzr, uxtx #0 + libdis_test+0x924: e0 67 3f 4b sub w0, wsp, wzr, uxtx #1 + libdis_test+0x928: e0 6b 3f 4b sub w0, wsp, wzr, uxtx #2 + libdis_test+0x92c: e0 6f 3f 4b sub w0, wsp, wzr, uxtx #3 + libdis_test+0x930: e0 73 3f 4b sub w0, wsp, wzr, uxtx #4 + libdis_test+0x934: e0 61 3e cb sub x0, x15, x30, uxtx #0 + libdis_test+0x938: e0 61 3e cb sub x0, x15, x30, uxtx #0 + libdis_test+0x93c: e0 65 3e cb sub x0, x15, x30, uxtx #1 + libdis_test+0x940: e0 69 3e cb sub x0, x15, x30, uxtx #2 + libdis_test+0x944: e0 6d 3e cb sub x0, x15, x30, uxtx #3 + libdis_test+0x948: e0 71 3e cb sub x0, x15, x30, uxtx #4 + libdis_test+0x94c: e0 43 3f cb sub x0, sp, wzr, uxtw #0 + libdis_test+0x950: e0 63 3f cb sub x0, sp, xzr, uxtx #0 + libdis_test+0x954: e0 63 3f cb sub x0, sp, xzr, uxtx #0 + libdis_test+0x958: e0 67 3f cb sub x0, sp, xzr, uxtx #1 + libdis_test+0x95c: e0 6b 3f cb sub x0, sp, xzr, uxtx #2 + libdis_test+0x960: e0 6f 3f cb sub x0, sp, xzr, uxtx #3 + libdis_test+0x964: e0 73 3f cb sub x0, sp, xzr, uxtx #4 + libdis_test+0x968: ff 61 3e cb sub sp, x15, x30, lsl #0 + libdis_test+0x96c: ff 61 3e cb sub sp, x15, x30, lsl #0 + libdis_test+0x970: e0 01 1e 4b sub w0, w15, w30 + libdis_test+0x974: e0 81 3e 4b sub w0, w15, w30, sxtb #0 + libdis_test+0x978: e0 81 3e 4b sub w0, w15, w30, sxtb #0 + libdis_test+0x97c: e0 85 3e 4b sub w0, w15, w30, sxtb #1 + libdis_test+0x980: e0 89 3e 4b sub w0, w15, w30, sxtb #2 + libdis_test+0x984: e0 8d 3e 4b sub w0, w15, w30, sxtb #3 + libdis_test+0x988: e0 91 3e 4b sub w0, w15, w30, sxtb #4 + libdis_test+0x98c: e0 43 3f 4b sub w0, wsp, wzr, uxtw #0 + libdis_test+0x990: e0 83 3f 4b sub w0, wsp, wzr, sxtb #0 + libdis_test+0x994: e0 83 3f 4b sub w0, wsp, wzr, sxtb #0 + libdis_test+0x998: e0 87 3f 4b sub w0, wsp, wzr, sxtb #1 + libdis_test+0x99c: e0 8b 3f 4b sub w0, wsp, wzr, sxtb #2 + libdis_test+0x9a0: e0 8f 3f 4b sub w0, wsp, wzr, sxtb #3 + libdis_test+0x9a4: e0 93 3f 4b sub w0, wsp, wzr, sxtb #4 + libdis_test+0x9a8: e0 81 3e cb sub x0, x15, w30, sxtb #0 + libdis_test+0x9ac: e0 81 3e cb sub x0, x15, w30, sxtb #0 + libdis_test+0x9b0: e0 85 3e cb sub x0, x15, w30, sxtb #1 + libdis_test+0x9b4: e0 89 3e cb sub x0, x15, w30, sxtb #2 + libdis_test+0x9b8: e0 8d 3e cb sub x0, x15, w30, sxtb #3 + libdis_test+0x9bc: e0 91 3e cb sub x0, x15, w30, sxtb #4 + libdis_test+0x9c0: e0 43 3f cb sub x0, sp, wzr, uxtw #0 + libdis_test+0x9c4: e0 83 3f cb sub x0, sp, wzr, sxtb #0 + libdis_test+0x9c8: e0 83 3f cb sub x0, sp, wzr, sxtb #0 + libdis_test+0x9cc: e0 87 3f cb sub x0, sp, wzr, sxtb #1 + libdis_test+0x9d0: e0 8b 3f cb sub x0, sp, wzr, sxtb #2 + libdis_test+0x9d4: e0 8f 3f cb sub x0, sp, wzr, sxtb #3 + libdis_test+0x9d8: e0 93 3f cb sub x0, sp, wzr, sxtb #4 + libdis_test+0x9dc: ff 61 3e cb sub sp, x15, x30, lsl #0 + libdis_test+0x9e0: ff 81 3e cb sub sp, x15, w30, sxtb #0 + libdis_test+0x9e4: e0 01 1e 4b sub w0, w15, w30 + libdis_test+0x9e8: e0 a1 3e 4b sub w0, w15, w30, sxth #0 + libdis_test+0x9ec: e0 a1 3e 4b sub w0, w15, w30, sxth #0 + libdis_test+0x9f0: e0 a5 3e 4b sub w0, w15, w30, sxth #1 + libdis_test+0x9f4: e0 a9 3e 4b sub w0, w15, w30, sxth #2 + libdis_test+0x9f8: e0 ad 3e 4b sub w0, w15, w30, sxth #3 + libdis_test+0x9fc: e0 b1 3e 4b sub w0, w15, w30, sxth #4 + libdis_test+0xa00: e0 43 3f 4b sub w0, wsp, wzr, uxtw #0 + libdis_test+0xa04: e0 a3 3f 4b sub w0, wsp, wzr, sxth #0 + libdis_test+0xa08: e0 a3 3f 4b sub w0, wsp, wzr, sxth #0 + libdis_test+0xa0c: e0 a7 3f 4b sub w0, wsp, wzr, sxth #1 + libdis_test+0xa10: e0 ab 3f 4b sub w0, wsp, wzr, sxth #2 + libdis_test+0xa14: e0 af 3f 4b sub w0, wsp, wzr, sxth #3 + libdis_test+0xa18: e0 b3 3f 4b sub w0, wsp, wzr, sxth #4 + libdis_test+0xa1c: e0 a1 3e cb sub x0, x15, w30, sxth #0 + libdis_test+0xa20: e0 a1 3e cb sub x0, x15, w30, sxth #0 + libdis_test+0xa24: e0 a5 3e cb sub x0, x15, w30, sxth #1 + libdis_test+0xa28: e0 a9 3e cb sub x0, x15, w30, sxth #2 + libdis_test+0xa2c: e0 ad 3e cb sub x0, x15, w30, sxth #3 + libdis_test+0xa30: e0 b1 3e cb sub x0, x15, w30, sxth #4 + libdis_test+0xa34: e0 43 3f cb sub x0, sp, wzr, uxtw #0 + libdis_test+0xa38: e0 a3 3f cb sub x0, sp, wzr, sxth #0 + libdis_test+0xa3c: e0 a3 3f cb sub x0, sp, wzr, sxth #0 + libdis_test+0xa40: e0 a7 3f cb sub x0, sp, wzr, sxth #1 + libdis_test+0xa44: e0 ab 3f cb sub x0, sp, wzr, sxth #2 + libdis_test+0xa48: e0 af 3f cb sub x0, sp, wzr, sxth #3 + libdis_test+0xa4c: e0 b3 3f cb sub x0, sp, wzr, sxth #4 + libdis_test+0xa50: ff 61 3e cb sub sp, x15, x30, lsl #0 + libdis_test+0xa54: ff a1 3e cb sub sp, x15, w30, sxth #0 + libdis_test+0xa58: e0 01 1e 4b sub w0, w15, w30 + libdis_test+0xa5c: e0 c1 3e 4b sub w0, w15, w30, sxtw #0 + libdis_test+0xa60: e0 c1 3e 4b sub w0, w15, w30, sxtw #0 + libdis_test+0xa64: e0 c5 3e 4b sub w0, w15, w30, sxtw #1 + libdis_test+0xa68: e0 c9 3e 4b sub w0, w15, w30, sxtw #2 + libdis_test+0xa6c: e0 cd 3e 4b sub w0, w15, w30, sxtw #3 + libdis_test+0xa70: e0 d1 3e 4b sub w0, w15, w30, sxtw #4 + libdis_test+0xa74: e0 43 3f 4b sub w0, wsp, wzr, uxtw #0 + libdis_test+0xa78: e0 c3 3f 4b sub w0, wsp, wzr, sxtw #0 + libdis_test+0xa7c: e0 c3 3f 4b sub w0, wsp, wzr, sxtw #0 + libdis_test+0xa80: e0 c7 3f 4b sub w0, wsp, wzr, sxtw #1 + libdis_test+0xa84: e0 cb 3f 4b sub w0, wsp, wzr, sxtw #2 + libdis_test+0xa88: e0 cf 3f 4b sub w0, wsp, wzr, sxtw #3 + libdis_test+0xa8c: e0 d3 3f 4b sub w0, wsp, wzr, sxtw #4 + libdis_test+0xa90: e0 c1 3e cb sub x0, x15, w30, sxtw #0 + libdis_test+0xa94: e0 c1 3e cb sub x0, x15, w30, sxtw #0 + libdis_test+0xa98: e0 c5 3e cb sub x0, x15, w30, sxtw #1 + libdis_test+0xa9c: e0 c9 3e cb sub x0, x15, w30, sxtw #2 + libdis_test+0xaa0: e0 cd 3e cb sub x0, x15, w30, sxtw #3 + libdis_test+0xaa4: e0 d1 3e cb sub x0, x15, w30, sxtw #4 + libdis_test+0xaa8: e0 43 3f cb sub x0, sp, wzr, uxtw #0 + libdis_test+0xaac: e0 c3 3f cb sub x0, sp, wzr, sxtw #0 + libdis_test+0xab0: e0 c3 3f cb sub x0, sp, wzr, sxtw #0 + libdis_test+0xab4: e0 c7 3f cb sub x0, sp, wzr, sxtw #1 + libdis_test+0xab8: e0 cb 3f cb sub x0, sp, wzr, sxtw #2 + libdis_test+0xabc: e0 cf 3f cb sub x0, sp, wzr, sxtw #3 + libdis_test+0xac0: e0 d3 3f cb sub x0, sp, wzr, sxtw #4 + libdis_test+0xac4: ff 61 3e cb sub sp, x15, x30, lsl #0 + libdis_test+0xac8: ff c1 3e cb sub sp, x15, w30, sxtw #0 + libdis_test+0xacc: e0 01 1e 4b sub w0, w15, w30 + libdis_test+0xad0: e0 e1 3e 4b sub w0, w15, w30, sxtx #0 + libdis_test+0xad4: e0 e1 3e 4b sub w0, w15, w30, sxtx #0 + libdis_test+0xad8: e0 e5 3e 4b sub w0, w15, w30, sxtx #1 + libdis_test+0xadc: e0 e9 3e 4b sub w0, w15, w30, sxtx #2 + libdis_test+0xae0: e0 ed 3e 4b sub w0, w15, w30, sxtx #3 + libdis_test+0xae4: e0 f1 3e 4b sub w0, w15, w30, sxtx #4 + libdis_test+0xae8: e0 43 3f 4b sub w0, wsp, wzr, uxtw #0 + libdis_test+0xaec: e0 e3 3f 4b sub w0, wsp, wzr, sxtx #0 + libdis_test+0xaf0: e0 e3 3f 4b sub w0, wsp, wzr, sxtx #0 + libdis_test+0xaf4: e0 e7 3f 4b sub w0, wsp, wzr, sxtx #1 + libdis_test+0xaf8: e0 eb 3f 4b sub w0, wsp, wzr, sxtx #2 + libdis_test+0xafc: e0 ef 3f 4b sub w0, wsp, wzr, sxtx #3 + libdis_test+0xb00: e0 f3 3f 4b sub w0, wsp, wzr, sxtx #4 + libdis_test+0xb04: e0 e1 3e cb sub x0, x15, x30, sxtx #0 + libdis_test+0xb08: e0 e1 3e cb sub x0, x15, x30, sxtx #0 + libdis_test+0xb0c: e0 e5 3e cb sub x0, x15, x30, sxtx #1 + libdis_test+0xb10: e0 e9 3e cb sub x0, x15, x30, sxtx #2 + libdis_test+0xb14: e0 ed 3e cb sub x0, x15, x30, sxtx #3 + libdis_test+0xb18: e0 f1 3e cb sub x0, x15, x30, sxtx #4 + libdis_test+0xb1c: e0 43 3f cb sub x0, sp, wzr, uxtw #0 + libdis_test+0xb20: e0 e3 3f cb sub x0, sp, xzr, sxtx #0 + libdis_test+0xb24: e0 e3 3f cb sub x0, sp, xzr, sxtx #0 + libdis_test+0xb28: e0 e7 3f cb sub x0, sp, xzr, sxtx #1 + libdis_test+0xb2c: e0 eb 3f cb sub x0, sp, xzr, sxtx #2 + libdis_test+0xb30: e0 ef 3f cb sub x0, sp, xzr, sxtx #3 + libdis_test+0xb34: e0 f3 3f cb sub x0, sp, xzr, sxtx #4 + libdis_test+0xb38: ff 61 3e cb sub sp, x15, x30, lsl #0 + libdis_test+0xb3c: ff e1 3e cb sub sp, x15, x30, sxtx #0 + libdis_test+0xb40: e0 01 1e 6b subs w0, w15, w30 + libdis_test+0xb44: e0 01 3e 6b subs w0, w15, w30, uxtb #0 + libdis_test+0xb48: e0 01 3e 6b subs w0, w15, w30, uxtb #0 + libdis_test+0xb4c: e0 05 3e 6b subs w0, w15, w30, uxtb #1 + libdis_test+0xb50: e0 09 3e 6b subs w0, w15, w30, uxtb #2 + libdis_test+0xb54: e0 0d 3e 6b subs w0, w15, w30, uxtb #3 + libdis_test+0xb58: e0 11 3e 6b subs w0, w15, w30, uxtb #4 + libdis_test+0xb5c: e0 43 3f 6b subs w0, wsp, wzr, uxtw #0 + libdis_test+0xb60: e0 03 3f 6b subs w0, wsp, wzr, uxtb #0 + libdis_test+0xb64: e0 03 3f 6b subs w0, wsp, wzr, uxtb #0 + libdis_test+0xb68: e0 07 3f 6b subs w0, wsp, wzr, uxtb #1 + libdis_test+0xb6c: e0 0b 3f 6b subs w0, wsp, wzr, uxtb #2 + libdis_test+0xb70: e0 0f 3f 6b subs w0, wsp, wzr, uxtb #3 + libdis_test+0xb74: e0 13 3f 6b subs w0, wsp, wzr, uxtb #4 + libdis_test+0xb78: e0 01 3e eb subs x0, x15, w30, uxtb #0 + libdis_test+0xb7c: e0 01 3e eb subs x0, x15, w30, uxtb #0 + libdis_test+0xb80: e0 05 3e eb subs x0, x15, w30, uxtb #1 + libdis_test+0xb84: e0 09 3e eb subs x0, x15, w30, uxtb #2 + libdis_test+0xb88: e0 0d 3e eb subs x0, x15, w30, uxtb #3 + libdis_test+0xb8c: e0 11 3e eb subs x0, x15, w30, uxtb #4 + libdis_test+0xb90: e0 43 3f eb subs x0, sp, wzr, uxtw #0 + libdis_test+0xb94: e0 03 3f eb subs x0, sp, wzr, uxtb #0 + libdis_test+0xb98: e0 03 3f eb subs x0, sp, wzr, uxtb #0 + libdis_test+0xb9c: e0 07 3f eb subs x0, sp, wzr, uxtb #1 + libdis_test+0xba0: e0 0b 3f eb subs x0, sp, wzr, uxtb #2 + libdis_test+0xba4: e0 0f 3f eb subs x0, sp, wzr, uxtb #3 + libdis_test+0xba8: e0 13 3f eb subs x0, sp, wzr, uxtb #4 + libdis_test+0xbac: ff 01 3e eb subs sp, x15, w30, uxtb #0 + libdis_test+0xbb0: ff 05 3e eb subs sp, x15, w30, uxtb #1 + libdis_test+0xbb4: ff 09 3e eb subs sp, x15, w30, uxtb #2 + libdis_test+0xbb8: ff 0d 3e eb subs sp, x15, w30, uxtb #3 + libdis_test+0xbbc: ff 11 3e eb subs sp, x15, w30, uxtb #4 + libdis_test+0xbc0: e0 01 1e 6b subs w0, w15, w30 + libdis_test+0xbc4: e0 21 3e 6b subs w0, w15, w30, uxth #0 + libdis_test+0xbc8: e0 21 3e 6b subs w0, w15, w30, uxth #0 + libdis_test+0xbcc: e0 25 3e 6b subs w0, w15, w30, uxth #1 + libdis_test+0xbd0: e0 29 3e 6b subs w0, w15, w30, uxth #2 + libdis_test+0xbd4: e0 2d 3e 6b subs w0, w15, w30, uxth #3 + libdis_test+0xbd8: e0 31 3e 6b subs w0, w15, w30, uxth #4 + libdis_test+0xbdc: e0 43 3f 6b subs w0, wsp, wzr, uxtw #0 + libdis_test+0xbe0: e0 23 3f 6b subs w0, wsp, wzr, uxth #0 + libdis_test+0xbe4: e0 23 3f 6b subs w0, wsp, wzr, uxth #0 + libdis_test+0xbe8: e0 27 3f 6b subs w0, wsp, wzr, uxth #1 + libdis_test+0xbec: e0 2b 3f 6b subs w0, wsp, wzr, uxth #2 + libdis_test+0xbf0: e0 2f 3f 6b subs w0, wsp, wzr, uxth #3 + libdis_test+0xbf4: e0 33 3f 6b subs w0, wsp, wzr, uxth #4 + libdis_test+0xbf8: e0 21 3e eb subs x0, x15, w30, uxth #0 + libdis_test+0xbfc: e0 21 3e eb subs x0, x15, w30, uxth #0 + libdis_test+0xc00: e0 25 3e eb subs x0, x15, w30, uxth #1 + libdis_test+0xc04: e0 29 3e eb subs x0, x15, w30, uxth #2 + libdis_test+0xc08: e0 2d 3e eb subs x0, x15, w30, uxth #3 + libdis_test+0xc0c: e0 31 3e eb subs x0, x15, w30, uxth #4 + libdis_test+0xc10: e0 43 3f eb subs x0, sp, wzr, uxtw #0 + libdis_test+0xc14: e0 23 3f eb subs x0, sp, wzr, uxth #0 + libdis_test+0xc18: e0 23 3f eb subs x0, sp, wzr, uxth #0 + libdis_test+0xc1c: e0 27 3f eb subs x0, sp, wzr, uxth #1 + libdis_test+0xc20: e0 2b 3f eb subs x0, sp, wzr, uxth #2 + libdis_test+0xc24: e0 2f 3f eb subs x0, sp, wzr, uxth #3 + libdis_test+0xc28: e0 33 3f eb subs x0, sp, wzr, uxth #4 + libdis_test+0xc2c: ff 21 3e eb subs sp, x15, w30, uxth #0 + libdis_test+0xc30: ff 25 3e eb subs sp, x15, w30, uxth #1 + libdis_test+0xc34: ff 29 3e eb subs sp, x15, w30, uxth #2 + libdis_test+0xc38: ff 2d 3e eb subs sp, x15, w30, uxth #3 + libdis_test+0xc3c: ff 31 3e eb subs sp, x15, w30, uxth #4 + libdis_test+0xc40: e0 01 1e 6b subs w0, w15, w30 + libdis_test+0xc44: e0 41 3e 6b subs w0, w15, w30, uxtw #0 + libdis_test+0xc48: e0 41 3e 6b subs w0, w15, w30, uxtw #0 + libdis_test+0xc4c: e0 45 3e 6b subs w0, w15, w30, uxtw #1 + libdis_test+0xc50: e0 49 3e 6b subs w0, w15, w30, uxtw #2 + libdis_test+0xc54: e0 4d 3e 6b subs w0, w15, w30, uxtw #3 + libdis_test+0xc58: e0 51 3e 6b subs w0, w15, w30, uxtw #4 + libdis_test+0xc5c: e0 43 3f 6b subs w0, wsp, wzr, uxtw #0 + libdis_test+0xc60: e0 43 3f 6b subs w0, wsp, wzr, uxtw #0 + libdis_test+0xc64: e0 43 3f 6b subs w0, wsp, wzr, uxtw #0 + libdis_test+0xc68: e0 47 3f 6b subs w0, wsp, wzr, uxtw #1 + libdis_test+0xc6c: e0 4b 3f 6b subs w0, wsp, wzr, uxtw #2 + libdis_test+0xc70: e0 4f 3f 6b subs w0, wsp, wzr, uxtw #3 + libdis_test+0xc74: e0 53 3f 6b subs w0, wsp, wzr, uxtw #4 + libdis_test+0xc78: e0 41 3e eb subs x0, x15, w30, uxtw #0 + libdis_test+0xc7c: e0 41 3e eb subs x0, x15, w30, uxtw #0 + libdis_test+0xc80: e0 45 3e eb subs x0, x15, w30, uxtw #1 + libdis_test+0xc84: e0 49 3e eb subs x0, x15, w30, uxtw #2 + libdis_test+0xc88: e0 4d 3e eb subs x0, x15, w30, uxtw #3 + libdis_test+0xc8c: e0 51 3e eb subs x0, x15, w30, uxtw #4 + libdis_test+0xc90: e0 43 3f eb subs x0, sp, wzr, uxtw #0 + libdis_test+0xc94: e0 43 3f eb subs x0, sp, wzr, uxtw #0 + libdis_test+0xc98: e0 43 3f eb subs x0, sp, wzr, uxtw #0 + libdis_test+0xc9c: e0 47 3f eb subs x0, sp, wzr, uxtw #1 + libdis_test+0xca0: e0 4b 3f eb subs x0, sp, wzr, uxtw #2 + libdis_test+0xca4: e0 4f 3f eb subs x0, sp, wzr, uxtw #3 + libdis_test+0xca8: e0 53 3f eb subs x0, sp, wzr, uxtw #4 + libdis_test+0xcac: ff 41 3e eb subs sp, x15, w30, uxtw #0 + libdis_test+0xcb0: ff 45 3e eb subs sp, x15, w30, uxtw #1 + libdis_test+0xcb4: ff 49 3e eb subs sp, x15, w30, uxtw #2 + libdis_test+0xcb8: ff 4d 3e eb subs sp, x15, w30, uxtw #3 + libdis_test+0xcbc: ff 51 3e eb subs sp, x15, w30, uxtw #4 + libdis_test+0xcc0: e0 01 1e 6b subs w0, w15, w30 + libdis_test+0xcc4: e0 61 3e 6b subs w0, w15, w30, uxtx #0 + libdis_test+0xcc8: e0 61 3e 6b subs w0, w15, w30, uxtx #0 + libdis_test+0xccc: e0 65 3e 6b subs w0, w15, w30, uxtx #1 + libdis_test+0xcd0: e0 69 3e 6b subs w0, w15, w30, uxtx #2 + libdis_test+0xcd4: e0 6d 3e 6b subs w0, w15, w30, uxtx #3 + libdis_test+0xcd8: e0 71 3e 6b subs w0, w15, w30, uxtx #4 + libdis_test+0xcdc: e0 43 3f 6b subs w0, wsp, wzr, uxtw #0 + libdis_test+0xce0: e0 63 3f 6b subs w0, wsp, wzr, uxtx #0 + libdis_test+0xce4: e0 63 3f 6b subs w0, wsp, wzr, uxtx #0 + libdis_test+0xce8: e0 67 3f 6b subs w0, wsp, wzr, uxtx #1 + libdis_test+0xcec: e0 6b 3f 6b subs w0, wsp, wzr, uxtx #2 + libdis_test+0xcf0: e0 6f 3f 6b subs w0, wsp, wzr, uxtx #3 + libdis_test+0xcf4: e0 73 3f 6b subs w0, wsp, wzr, uxtx #4 + libdis_test+0xcf8: e0 61 3e eb subs x0, x15, x30, uxtx #0 + libdis_test+0xcfc: e0 61 3e eb subs x0, x15, x30, uxtx #0 + libdis_test+0xd00: e0 65 3e eb subs x0, x15, x30, uxtx #1 + libdis_test+0xd04: e0 69 3e eb subs x0, x15, x30, uxtx #2 + libdis_test+0xd08: e0 6d 3e eb subs x0, x15, x30, uxtx #3 + libdis_test+0xd0c: e0 71 3e eb subs x0, x15, x30, uxtx #4 + libdis_test+0xd10: e0 43 3f eb subs x0, sp, wzr, uxtw #0 + libdis_test+0xd14: e0 63 3f eb subs x0, sp, xzr, uxtx #0 + libdis_test+0xd18: e0 63 3f eb subs x0, sp, xzr, uxtx #0 + libdis_test+0xd1c: e0 67 3f eb subs x0, sp, xzr, uxtx #1 + libdis_test+0xd20: e0 6b 3f eb subs x0, sp, xzr, uxtx #2 + libdis_test+0xd24: e0 6f 3f eb subs x0, sp, xzr, uxtx #3 + libdis_test+0xd28: e0 73 3f eb subs x0, sp, xzr, uxtx #4 + libdis_test+0xd2c: ff 61 3e eb subs sp, x15, x30, lsl #0 + libdis_test+0xd30: ff 65 3e eb subs sp, x15, x30, lsl #1 + libdis_test+0xd34: ff 69 3e eb subs sp, x15, x30, lsl #2 + libdis_test+0xd38: ff 6d 3e eb subs sp, x15, x30, lsl #3 + libdis_test+0xd3c: ff 71 3e eb subs sp, x15, x30, lsl #4 + libdis_test+0xd40: e0 01 1e 6b subs w0, w15, w30 + libdis_test+0xd44: e0 81 3e 6b subs w0, w15, w30, sxtb #0 + libdis_test+0xd48: e0 81 3e 6b subs w0, w15, w30, sxtb #0 + libdis_test+0xd4c: e0 85 3e 6b subs w0, w15, w30, sxtb #1 + libdis_test+0xd50: e0 89 3e 6b subs w0, w15, w30, sxtb #2 + libdis_test+0xd54: e0 8d 3e 6b subs w0, w15, w30, sxtb #3 + libdis_test+0xd58: e0 91 3e 6b subs w0, w15, w30, sxtb #4 + libdis_test+0xd5c: e0 43 3f 6b subs w0, wsp, wzr, uxtw #0 + libdis_test+0xd60: e0 83 3f 6b subs w0, wsp, wzr, sxtb #0 + libdis_test+0xd64: e0 83 3f 6b subs w0, wsp, wzr, sxtb #0 + libdis_test+0xd68: e0 87 3f 6b subs w0, wsp, wzr, sxtb #1 + libdis_test+0xd6c: e0 8b 3f 6b subs w0, wsp, wzr, sxtb #2 + libdis_test+0xd70: e0 8f 3f 6b subs w0, wsp, wzr, sxtb #3 + libdis_test+0xd74: e0 93 3f 6b subs w0, wsp, wzr, sxtb #4 + libdis_test+0xd78: e0 81 3e eb subs x0, x15, w30, sxtb #0 + libdis_test+0xd7c: e0 81 3e eb subs x0, x15, w30, sxtb #0 + libdis_test+0xd80: e0 85 3e eb subs x0, x15, w30, sxtb #1 + libdis_test+0xd84: e0 89 3e eb subs x0, x15, w30, sxtb #2 + libdis_test+0xd88: e0 8d 3e eb subs x0, x15, w30, sxtb #3 + libdis_test+0xd8c: e0 91 3e eb subs x0, x15, w30, sxtb #4 + libdis_test+0xd90: e0 43 3f eb subs x0, sp, wzr, uxtw #0 + libdis_test+0xd94: e0 83 3f eb subs x0, sp, wzr, sxtb #0 + libdis_test+0xd98: e0 83 3f eb subs x0, sp, wzr, sxtb #0 + libdis_test+0xd9c: e0 87 3f eb subs x0, sp, wzr, sxtb #1 + libdis_test+0xda0: e0 8b 3f eb subs x0, sp, wzr, sxtb #2 + libdis_test+0xda4: e0 8f 3f eb subs x0, sp, wzr, sxtb #3 + libdis_test+0xda8: e0 93 3f eb subs x0, sp, wzr, sxtb #4 + libdis_test+0xdac: ff 81 3e eb subs sp, x15, w30, sxtb #0 + libdis_test+0xdb0: ff 85 3e eb subs sp, x15, w30, sxtb #1 + libdis_test+0xdb4: ff 89 3e eb subs sp, x15, w30, sxtb #2 + libdis_test+0xdb8: ff 8d 3e eb subs sp, x15, w30, sxtb #3 + libdis_test+0xdbc: ff 91 3e eb subs sp, x15, w30, sxtb #4 + libdis_test+0xdc0: e0 01 1e 6b subs w0, w15, w30 + libdis_test+0xdc4: e0 a1 3e 6b subs w0, w15, w30, sxth #0 + libdis_test+0xdc8: e0 a1 3e 6b subs w0, w15, w30, sxth #0 + libdis_test+0xdcc: e0 a5 3e 6b subs w0, w15, w30, sxth #1 + libdis_test+0xdd0: e0 a9 3e 6b subs w0, w15, w30, sxth #2 + libdis_test+0xdd4: e0 ad 3e 6b subs w0, w15, w30, sxth #3 + libdis_test+0xdd8: e0 b1 3e 6b subs w0, w15, w30, sxth #4 + libdis_test+0xddc: e0 43 3f 6b subs w0, wsp, wzr, uxtw #0 + libdis_test+0xde0: e0 a3 3f 6b subs w0, wsp, wzr, sxth #0 + libdis_test+0xde4: e0 a3 3f 6b subs w0, wsp, wzr, sxth #0 + libdis_test+0xde8: e0 a7 3f 6b subs w0, wsp, wzr, sxth #1 + libdis_test+0xdec: e0 ab 3f 6b subs w0, wsp, wzr, sxth #2 + libdis_test+0xdf0: e0 af 3f 6b subs w0, wsp, wzr, sxth #3 + libdis_test+0xdf4: e0 b3 3f 6b subs w0, wsp, wzr, sxth #4 + libdis_test+0xdf8: e0 a1 3e eb subs x0, x15, w30, sxth #0 + libdis_test+0xdfc: e0 a1 3e eb subs x0, x15, w30, sxth #0 + libdis_test+0xe00: e0 a5 3e eb subs x0, x15, w30, sxth #1 + libdis_test+0xe04: e0 a9 3e eb subs x0, x15, w30, sxth #2 + libdis_test+0xe08: e0 ad 3e eb subs x0, x15, w30, sxth #3 + libdis_test+0xe0c: e0 b1 3e eb subs x0, x15, w30, sxth #4 + libdis_test+0xe10: e0 43 3f eb subs x0, sp, wzr, uxtw #0 + libdis_test+0xe14: e0 a3 3f eb subs x0, sp, wzr, sxth #0 + libdis_test+0xe18: e0 a3 3f eb subs x0, sp, wzr, sxth #0 + libdis_test+0xe1c: e0 a7 3f eb subs x0, sp, wzr, sxth #1 + libdis_test+0xe20: e0 ab 3f eb subs x0, sp, wzr, sxth #2 + libdis_test+0xe24: e0 af 3f eb subs x0, sp, wzr, sxth #3 + libdis_test+0xe28: e0 b3 3f eb subs x0, sp, wzr, sxth #4 + libdis_test+0xe2c: ff a1 3e eb subs sp, x15, w30, sxth #0 + libdis_test+0xe30: ff a5 3e eb subs sp, x15, w30, sxth #1 + libdis_test+0xe34: ff a9 3e eb subs sp, x15, w30, sxth #2 + libdis_test+0xe38: ff ad 3e eb subs sp, x15, w30, sxth #3 + libdis_test+0xe3c: ff b1 3e eb subs sp, x15, w30, sxth #4 + libdis_test+0xe40: e0 01 1e 6b subs w0, w15, w30 + libdis_test+0xe44: e0 c1 3e 6b subs w0, w15, w30, sxtw #0 + libdis_test+0xe48: e0 c1 3e 6b subs w0, w15, w30, sxtw #0 + libdis_test+0xe4c: e0 c5 3e 6b subs w0, w15, w30, sxtw #1 + libdis_test+0xe50: e0 c9 3e 6b subs w0, w15, w30, sxtw #2 + libdis_test+0xe54: e0 cd 3e 6b subs w0, w15, w30, sxtw #3 + libdis_test+0xe58: e0 d1 3e 6b subs w0, w15, w30, sxtw #4 + libdis_test+0xe5c: e0 43 3f 6b subs w0, wsp, wzr, uxtw #0 + libdis_test+0xe60: e0 c3 3f 6b subs w0, wsp, wzr, sxtw #0 + libdis_test+0xe64: e0 c3 3f 6b subs w0, wsp, wzr, sxtw #0 + libdis_test+0xe68: e0 c7 3f 6b subs w0, wsp, wzr, sxtw #1 + libdis_test+0xe6c: e0 cb 3f 6b subs w0, wsp, wzr, sxtw #2 + libdis_test+0xe70: e0 cf 3f 6b subs w0, wsp, wzr, sxtw #3 + libdis_test+0xe74: e0 d3 3f 6b subs w0, wsp, wzr, sxtw #4 + libdis_test+0xe78: e0 c1 3e eb subs x0, x15, w30, sxtw #0 + libdis_test+0xe7c: e0 c1 3e eb subs x0, x15, w30, sxtw #0 + libdis_test+0xe80: e0 c5 3e eb subs x0, x15, w30, sxtw #1 + libdis_test+0xe84: e0 c9 3e eb subs x0, x15, w30, sxtw #2 + libdis_test+0xe88: e0 cd 3e eb subs x0, x15, w30, sxtw #3 + libdis_test+0xe8c: e0 d1 3e eb subs x0, x15, w30, sxtw #4 + libdis_test+0xe90: e0 43 3f eb subs x0, sp, wzr, uxtw #0 + libdis_test+0xe94: e0 c3 3f eb subs x0, sp, wzr, sxtw #0 + libdis_test+0xe98: e0 c3 3f eb subs x0, sp, wzr, sxtw #0 + libdis_test+0xe9c: e0 c7 3f eb subs x0, sp, wzr, sxtw #1 + libdis_test+0xea0: e0 cb 3f eb subs x0, sp, wzr, sxtw #2 + libdis_test+0xea4: e0 cf 3f eb subs x0, sp, wzr, sxtw #3 + libdis_test+0xea8: e0 d3 3f eb subs x0, sp, wzr, sxtw #4 + libdis_test+0xeac: ff c1 3e eb subs sp, x15, w30, sxtw #0 + libdis_test+0xeb0: ff c5 3e eb subs sp, x15, w30, sxtw #1 + libdis_test+0xeb4: ff c9 3e eb subs sp, x15, w30, sxtw #2 + libdis_test+0xeb8: ff cd 3e eb subs sp, x15, w30, sxtw #3 + libdis_test+0xebc: ff d1 3e eb subs sp, x15, w30, sxtw #4 + libdis_test+0xec0: e0 01 1e 6b subs w0, w15, w30 + libdis_test+0xec4: e0 e1 3e 6b subs w0, w15, w30, sxtx #0 + libdis_test+0xec8: e0 e1 3e 6b subs w0, w15, w30, sxtx #0 + libdis_test+0xecc: e0 e5 3e 6b subs w0, w15, w30, sxtx #1 + libdis_test+0xed0: e0 e9 3e 6b subs w0, w15, w30, sxtx #2 + libdis_test+0xed4: e0 ed 3e 6b subs w0, w15, w30, sxtx #3 + libdis_test+0xed8: e0 f1 3e 6b subs w0, w15, w30, sxtx #4 + libdis_test+0xedc: e0 43 3f 6b subs w0, wsp, wzr, uxtw #0 + libdis_test+0xee0: e0 e3 3f 6b subs w0, wsp, wzr, sxtx #0 + libdis_test+0xee4: e0 e3 3f 6b subs w0, wsp, wzr, sxtx #0 + libdis_test+0xee8: e0 e7 3f 6b subs w0, wsp, wzr, sxtx #1 + libdis_test+0xeec: e0 eb 3f 6b subs w0, wsp, wzr, sxtx #2 + libdis_test+0xef0: e0 ef 3f 6b subs w0, wsp, wzr, sxtx #3 + libdis_test+0xef4: e0 f3 3f 6b subs w0, wsp, wzr, sxtx #4 + libdis_test+0xef8: e0 e1 3e eb subs x0, x15, x30, sxtx #0 + libdis_test+0xefc: e0 e1 3e eb subs x0, x15, x30, sxtx #0 + libdis_test+0xf00: e0 e5 3e eb subs x0, x15, x30, sxtx #1 + libdis_test+0xf04: e0 e9 3e eb subs x0, x15, x30, sxtx #2 + libdis_test+0xf08: e0 ed 3e eb subs x0, x15, x30, sxtx #3 + libdis_test+0xf0c: e0 f1 3e eb subs x0, x15, x30, sxtx #4 + libdis_test+0xf10: e0 43 3f eb subs x0, sp, wzr, uxtw #0 + libdis_test+0xf14: e0 e3 3f eb subs x0, sp, xzr, sxtx #0 + libdis_test+0xf18: e0 e3 3f eb subs x0, sp, xzr, sxtx #0 + libdis_test+0xf1c: e0 e7 3f eb subs x0, sp, xzr, sxtx #1 + libdis_test+0xf20: e0 eb 3f eb subs x0, sp, xzr, sxtx #2 + libdis_test+0xf24: e0 ef 3f eb subs x0, sp, xzr, sxtx #3 + libdis_test+0xf28: e0 f3 3f eb subs x0, sp, xzr, sxtx #4 + libdis_test+0xf2c: ff e1 3e eb subs sp, x15, x30, sxtx #0 + libdis_test+0xf30: ff e5 3e eb subs sp, x15, x30, sxtx #1 + libdis_test+0xf34: ff e9 3e eb subs sp, x15, x30, sxtx #2 + libdis_test+0xf38: ff ed 3e eb subs sp, x15, x30, sxtx #3 + libdis_test+0xf3c: ff f1 3e eb subs sp, x15, x30, sxtx #4 diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-extreg.s b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-extreg.s new file mode 100755 index 0000000000..add6748595 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-extreg.s @@ -0,0 +1,99 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.5.1 Add/subtract (extended register) + */ + +/* + * Test all combinations of 32-bit/64-bit, source registers (SP/ZR/R*) and + * extends. The 64-bit form additionally supports <Wm>. + */ +.macro addsub_extreg_ext op extend zreg=0 + /* 32-bit */ + \op w0, w15, w30 + \op w0, w15, w30, \extend + \op w0, w15, w30, \extend #0 + \op w0, w15, w30, \extend #1 + \op w0, w15, w30, \extend #2 + \op w0, w15, w30, \extend #3 + \op w0, w15, w30, \extend #4 + \op w0, wsp, wzr + \op w0, wsp, wzr, \extend + \op w0, wsp, wzr, \extend #0 + \op w0, wsp, wzr, \extend #1 + \op w0, wsp, wzr, \extend #2 + \op w0, wsp, wzr, \extend #3 + \op w0, wsp, wzr, \extend #4 + /* 64-bit */ + \op x0, x15, w30, \extend + \op x0, x15, w30, \extend #0 + \op x0, x15, w30, \extend #1 + \op x0, x15, w30, \extend #2 + \op x0, x15, w30, \extend #3 + \op x0, x15, w30, \extend #4 + \op x0, sp, wzr + \op x0, sp, wzr, \extend + \op x0, sp, wzr, \extend #0 + \op x0, sp, wzr, \extend #1 + \op x0, sp, wzr, \extend #2 + \op x0, sp, wzr, \extend #3 + \op x0, sp, wzr, \extend #4 + .if \zreg + \op xzr, x15, w30, \extend #0 + \op xzr, x15, w30, \extend #1 + \op xzr, x15, w30, \extend #2 + \op xzr, x15, w30, \extend #3 + \op xzr, x15, w30, \extend #4 + .else + \op sp, x15, x30 + \op sp, x15, x30, \extend + .endif +.endm + +.macro addsub_extreg op zreg=0 + addsub_extreg_ext \op uxtb \zreg + addsub_extreg_ext \op uxth \zreg + addsub_extreg_ext \op uxtw \zreg + addsub_extreg_ext \op uxtx \zreg + addsub_extreg_ext \op sxtb \zreg + addsub_extreg_ext \op sxth \zreg + addsub_extreg_ext \op sxtw \zreg + addsub_extreg_ext \op sxtx \zreg +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * C5.6.3 ADD (extended register) + */ + addsub_extreg add + /* + * C5.6.6 ADDS (extended register) + * C5.6.41 CMN (extended register) (alias) + */ + addsub_extreg adds 1 + /* + * C5.6.194 SUB (extended register) + */ + addsub_extreg sub + /* + * C5.6.197 SUBS (extended register) + * C5.6.44 CMP (extended register) (alias) + */ + addsub_extreg subs 1 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-imm.out b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-imm.out new file mode 100755 index 0000000000..04b4e5488c --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-imm.out @@ -0,0 +1,96 @@ + libdis_test: c0 03 00 11 add w0, w30, #0x0 + libdis_test+0x4: c0 ff 3f 11 add w0, w30, #0xfff + libdis_test+0x8: c0 03 00 11 add w0, w30, #0x0 + libdis_test+0xc: c0 ff 3f 11 add w0, w30, #0xfff + libdis_test+0x10: c0 03 40 11 add w0, w30, #0x0, lsl #12 + libdis_test+0x14: c0 ff 7f 11 add w0, w30, #0xfff, lsl #12 + libdis_test+0x18: c0 03 00 91 add x0, x30, #0x0 + libdis_test+0x1c: c0 ff 3f 91 add x0, x30, #0xfff + libdis_test+0x20: c0 03 00 91 add x0, x30, #0x0 + libdis_test+0x24: c0 ff 3f 91 add x0, x30, #0xfff + libdis_test+0x28: c0 03 40 91 add x0, x30, #0x0, lsl #12 + libdis_test+0x2c: c0 ff 7f 91 add x0, x30, #0xfff, lsl #12 + libdis_test+0x30: e0 03 00 11 add w0, wsp, #0x0 + libdis_test+0x34: fe ff 7f 11 add w30, wsp, #0xfff, lsl #12 + libdis_test+0x38: e0 03 00 91 add x0, sp, #0x0 + libdis_test+0x3c: fe ff 7f 91 add x30, sp, #0xfff, lsl #12 + libdis_test+0x40: 1f 00 00 11 add wsp, w0, #0x0 + libdis_test+0x44: df ff 7f 11 add wsp, w30, #0xfff, lsl #12 + libdis_test+0x48: ff 03 00 11 add wsp, wsp, #0x0 + libdis_test+0x4c: ff ff 7f 11 add wsp, wsp, #0xfff, lsl #12 + libdis_test+0x50: 1f 00 00 91 add sp, x0, #0x0 + libdis_test+0x54: df ff 7f 91 add sp, x30, #0xfff, lsl #12 + libdis_test+0x58: ff 03 00 91 add sp, sp, #0x0 + libdis_test+0x5c: ff ff 7f 91 add sp, sp, #0xfff, lsl #12 + libdis_test+0x60: c0 03 00 31 adds w0, w30, #0x0 + libdis_test+0x64: c0 ff 3f 31 adds w0, w30, #0xfff + libdis_test+0x68: c0 03 00 31 adds w0, w30, #0x0 + libdis_test+0x6c: c0 ff 3f 31 adds w0, w30, #0xfff + libdis_test+0x70: c0 03 40 31 adds w0, w30, #0x0, lsl #12 + libdis_test+0x74: c0 ff 7f 31 adds w0, w30, #0xfff, lsl #12 + libdis_test+0x78: c0 03 00 b1 adds x0, x30, #0x0 + libdis_test+0x7c: c0 ff 3f b1 adds x0, x30, #0xfff + libdis_test+0x80: c0 03 00 b1 adds x0, x30, #0x0 + libdis_test+0x84: c0 ff 3f b1 adds x0, x30, #0xfff + libdis_test+0x88: c0 03 40 b1 adds x0, x30, #0x0, lsl #12 + libdis_test+0x8c: c0 ff 7f b1 adds x0, x30, #0xfff, lsl #12 + libdis_test+0x90: e0 03 00 31 adds w0, wsp, #0x0 + libdis_test+0x94: fe ff 7f 31 adds w30, wsp, #0xfff, lsl #12 + libdis_test+0x98: e0 03 00 b1 adds x0, sp, #0x0 + libdis_test+0x9c: fe ff 7f b1 adds x30, sp, #0xfff, lsl #12 + libdis_test+0xa0: 1f 00 00 31 adds wzr, w0, #0x0 + libdis_test+0xa4: df ff 7f 31 adds wzr, w30, #0xfff, lsl #12 + libdis_test+0xa8: ff 03 00 31 adds wzr, wsp, #0x0 + libdis_test+0xac: ff ff 7f 31 adds wzr, wsp, #0xfff, lsl #12 + libdis_test+0xb0: 1f 00 00 b1 adds xzr, x0, #0x0 + libdis_test+0xb4: df ff 7f b1 adds xzr, x30, #0xfff, lsl #12 + libdis_test+0xb8: ff 03 00 b1 adds xzr, sp, #0x0 + libdis_test+0xbc: ff ff 7f b1 adds xzr, sp, #0xfff, lsl #12 + libdis_test+0xc0: c0 03 00 51 sub w0, w30, #0x0 + libdis_test+0xc4: c0 ff 3f 51 sub w0, w30, #0xfff + libdis_test+0xc8: c0 03 00 51 sub w0, w30, #0x0 + libdis_test+0xcc: c0 ff 3f 51 sub w0, w30, #0xfff + libdis_test+0xd0: c0 03 40 51 sub w0, w30, #0x0, lsl #12 + libdis_test+0xd4: c0 ff 7f 51 sub w0, w30, #0xfff, lsl #12 + libdis_test+0xd8: c0 03 00 d1 sub x0, x30, #0x0 + libdis_test+0xdc: c0 ff 3f d1 sub x0, x30, #0xfff + libdis_test+0xe0: c0 03 00 d1 sub x0, x30, #0x0 + libdis_test+0xe4: c0 ff 3f d1 sub x0, x30, #0xfff + libdis_test+0xe8: c0 03 40 d1 sub x0, x30, #0x0, lsl #12 + libdis_test+0xec: c0 ff 7f d1 sub x0, x30, #0xfff, lsl #12 + libdis_test+0xf0: e0 03 00 51 sub w0, wsp, #0x0 + libdis_test+0xf4: fe ff 7f 51 sub w30, wsp, #0xfff, lsl #12 + libdis_test+0xf8: e0 03 00 d1 sub x0, sp, #0x0 + libdis_test+0xfc: fe ff 7f d1 sub x30, sp, #0xfff, lsl #12 + libdis_test+0x100: 1f 00 00 51 sub wsp, w0, #0x0 + libdis_test+0x104: df ff 7f 51 sub wsp, w30, #0xfff, lsl #12 + libdis_test+0x108: ff 03 00 51 sub wsp, wsp, #0x0 + libdis_test+0x10c: ff ff 7f 51 sub wsp, wsp, #0xfff, lsl #12 + libdis_test+0x110: 1f 00 00 d1 sub sp, x0, #0x0 + libdis_test+0x114: df ff 7f d1 sub sp, x30, #0xfff, lsl #12 + libdis_test+0x118: ff 03 00 d1 sub sp, sp, #0x0 + libdis_test+0x11c: ff ff 7f d1 sub sp, sp, #0xfff, lsl #12 + libdis_test+0x120: c0 03 00 71 subs w0, w30, #0x0 + libdis_test+0x124: c0 ff 3f 71 subs w0, w30, #0xfff + libdis_test+0x128: c0 03 00 71 subs w0, w30, #0x0 + libdis_test+0x12c: c0 ff 3f 71 subs w0, w30, #0xfff + libdis_test+0x130: c0 03 40 71 subs w0, w30, #0x0, lsl #12 + libdis_test+0x134: c0 ff 7f 71 subs w0, w30, #0xfff, lsl #12 + libdis_test+0x138: c0 03 00 f1 subs x0, x30, #0x0 + libdis_test+0x13c: c0 ff 3f f1 subs x0, x30, #0xfff + libdis_test+0x140: c0 03 00 f1 subs x0, x30, #0x0 + libdis_test+0x144: c0 ff 3f f1 subs x0, x30, #0xfff + libdis_test+0x148: c0 03 40 f1 subs x0, x30, #0x0, lsl #12 + libdis_test+0x14c: c0 ff 7f f1 subs x0, x30, #0xfff, lsl #12 + libdis_test+0x150: e0 03 00 71 subs w0, wsp, #0x0 + libdis_test+0x154: fe ff 7f 71 subs w30, wsp, #0xfff, lsl #12 + libdis_test+0x158: e0 03 00 f1 subs x0, sp, #0x0 + libdis_test+0x15c: fe ff 7f f1 subs x30, sp, #0xfff, lsl #12 + libdis_test+0x160: 1f 00 00 71 subs wzr, w0, #0x0 + libdis_test+0x164: df ff 7f 71 subs wzr, w30, #0xfff, lsl #12 + libdis_test+0x168: ff 03 00 71 subs wzr, wsp, #0x0 + libdis_test+0x16c: ff ff 7f 71 subs wzr, wsp, #0xfff, lsl #12 + libdis_test+0x170: 1f 00 00 f1 subs xzr, x0, #0x0 + libdis_test+0x174: df ff 7f f1 subs xzr, x30, #0xfff, lsl #12 + libdis_test+0x178: ff 03 00 f1 subs xzr, sp, #0x0 + libdis_test+0x17c: ff ff 7f f1 subs xzr, sp, #0xfff, lsl #12 diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-imm.s b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-imm.s new file mode 100755 index 0000000000..37d82a9ba7 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-imm.s @@ -0,0 +1,83 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.4.1 Add/subtract (immediate) + */ +.macro addsub_imm op zreg=0 + /* 32-bit */ + \op w0, w30, #0 + \op w0, w30, #4095 + \op w0, w30, #0, lsl #0 + \op w0, w30, #4095, lsl #0 + \op w0, w30, #0, lsl #12 + \op w0, w30, #4095, lsl #12 + /* 64-bit */ + \op x0, x30, #0 + \op x0, x30, #4095 + \op x0, x30, #0, lsl #0 + \op x0, x30, #4095, lsl #0 + \op x0, x30, #0, lsl #12 + \op x0, x30, #4095, lsl #12 + /* SP/ZR (aliases) */ + \op w0, wsp, #0 + \op w30, wsp, #4095, lsl #12 + \op x0, sp, #0 + \op x30, sp, #4095, lsl #12 + .if \zreg + \op wzr, w0, #0 + \op wzr, w30, #4095, lsl #12 + \op wzr, wsp, #0 + \op wzr, wsp, #4095, lsl #12 + \op xzr, x0, #0 + \op xzr, x30, #4095, lsl #12 + \op xzr, sp, #0 + \op xzr, sp, #4095, lsl #12 + .else + \op wsp, w0, #0 + \op wsp, w30, #4095, lsl #12 + \op wsp, wsp, #0 + \op wsp, wsp, #4095, lsl #12 + \op sp, x0, #0 + \op sp, x30, #4095, lsl #12 + \op sp, sp, #0 + \op sp, sp, #4095, lsl #12 + .endif +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * C5.6.4 ADD (immediate) + * C5.6.121 MOV (to/from SP) (alias) + */ + addsub_imm add + /* + * C5.6.7 ADDS (immediate) + * C5.6.42 CMN (immediate) (alias) + */ + addsub_imm adds 1 + /* + * C5.6.195 SUB (immediate) + */ + addsub_imm sub + /* + * C5.6.198 SUBS (immediate) + * C5.6.45 CMP (immediate) (alias) + */ + addsub_imm subs 1 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-shiftreg.out b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-shiftreg.out new file mode 100755 index 0000000000..67b52c884b --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-shiftreg.out @@ -0,0 +1,56 @@ + libdis_test: e0 01 1e 0b add w0, w15, w30 + libdis_test+0x4: ff 01 1e 0b add wzr, w15, w30 + libdis_test+0x8: e0 7f 1e 0b add w0, wzr, w30, lsl #31 + libdis_test+0xc: e0 01 5f 0b add w0, w15, wzr + libdis_test+0x10: ff 7f 5e 0b add wzr, wzr, w30, lsr #31 + libdis_test+0x14: e0 03 9f 0b add w0, wzr, wzr + libdis_test+0x18: ff 7f 9f 0b add wzr, wzr, wzr, asr #31 + libdis_test+0x1c: e0 01 1e 8b add x0, x15, x30 + libdis_test+0x20: ff 01 1e 8b add xzr, x15, x30 + libdis_test+0x24: e0 ff 1e 8b add x0, xzr, x30, lsl #63 + libdis_test+0x28: e0 01 5f 8b add x0, x15, xzr + libdis_test+0x2c: ff ff 5e 8b add xzr, xzr, x30, lsr #63 + libdis_test+0x30: e0 03 9f 8b add x0, xzr, xzr + libdis_test+0x34: ff ff 9f 8b add xzr, xzr, xzr, asr #63 + libdis_test+0x38: e0 01 1e 2b adds w0, w15, w30 + libdis_test+0x3c: ff 01 1e 2b adds wzr, w15, w30 + libdis_test+0x40: e0 7f 1e 2b adds w0, wzr, w30, lsl #31 + libdis_test+0x44: e0 01 5f 2b adds w0, w15, wzr + libdis_test+0x48: ff 7f 5e 2b adds wzr, wzr, w30, lsr #31 + libdis_test+0x4c: e0 03 9f 2b adds w0, wzr, wzr + libdis_test+0x50: ff 7f 9f 2b adds wzr, wzr, wzr, asr #31 + libdis_test+0x54: e0 01 1e ab adds x0, x15, x30 + libdis_test+0x58: ff 01 1e ab adds xzr, x15, x30 + libdis_test+0x5c: e0 ff 1e ab adds x0, xzr, x30, lsl #63 + libdis_test+0x60: e0 01 5f ab adds x0, x15, xzr + libdis_test+0x64: ff ff 5e ab adds xzr, xzr, x30, lsr #63 + libdis_test+0x68: e0 03 9f ab adds x0, xzr, xzr + libdis_test+0x6c: ff ff 9f ab adds xzr, xzr, xzr, asr #63 + libdis_test+0x70: e0 01 1e 4b sub w0, w15, w30 + libdis_test+0x74: ff 01 1e 4b sub wzr, w15, w30 + libdis_test+0x78: e0 7f 1e 4b sub w0, wzr, w30, lsl #31 + libdis_test+0x7c: e0 01 5f 4b sub w0, w15, wzr + libdis_test+0x80: ff 7f 5e 4b sub wzr, wzr, w30, lsr #31 + libdis_test+0x84: e0 03 9f 4b sub w0, wzr, wzr + libdis_test+0x88: ff 7f 9f 4b sub wzr, wzr, wzr, asr #31 + libdis_test+0x8c: e0 01 1e cb sub x0, x15, x30 + libdis_test+0x90: ff 01 1e cb sub xzr, x15, x30 + libdis_test+0x94: e0 ff 1e cb sub x0, xzr, x30, lsl #63 + libdis_test+0x98: e0 01 5f cb sub x0, x15, xzr + libdis_test+0x9c: ff ff 5e cb sub xzr, xzr, x30, lsr #63 + libdis_test+0xa0: e0 03 9f cb sub x0, xzr, xzr + libdis_test+0xa4: ff ff 9f cb sub xzr, xzr, xzr, asr #63 + libdis_test+0xa8: e0 01 1e 6b subs w0, w15, w30 + libdis_test+0xac: ff 01 1e 6b subs wzr, w15, w30 + libdis_test+0xb0: e0 7f 1e 6b subs w0, wzr, w30, lsl #31 + libdis_test+0xb4: e0 01 5f 6b subs w0, w15, wzr + libdis_test+0xb8: ff 7f 5e 6b subs wzr, wzr, w30, lsr #31 + libdis_test+0xbc: e0 03 9f 6b subs w0, wzr, wzr + libdis_test+0xc0: ff 7f 9f 6b subs wzr, wzr, wzr, asr #31 + libdis_test+0xc4: e0 01 1e eb subs x0, x15, x30 + libdis_test+0xc8: ff 01 1e eb subs xzr, x15, x30 + libdis_test+0xcc: e0 ff 1e eb subs x0, xzr, x30, lsl #63 + libdis_test+0xd0: e0 01 5f eb subs x0, x15, xzr + libdis_test+0xd4: ff ff 5e eb subs xzr, xzr, x30, lsr #63 + libdis_test+0xd8: e0 03 9f eb subs x0, xzr, xzr + libdis_test+0xdc: ff ff 9f eb subs xzr, xzr, xzr, asr #63 diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-shiftreg.s b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-shiftreg.s new file mode 100755 index 0000000000..3b41dd2a8e --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.addsub-shiftreg.s @@ -0,0 +1,62 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.5.2 Add/subtract (shifted register) + */ +.macro addsub_shiftreg op zreg=0 + /* 32-bit */ + \op w0, w15, w30 + \op wzr, w15, w30, lsl #0 + \op w0, wzr, w30, lsl #31 + \op w0, w15, wzr, lsr #0 + \op wzr, wzr, w30, lsr #31 + \op w0, wzr, wzr, asr #0 + \op wzr, wzr, wzr, asr #31 + /* 64-bit */ + \op x0, x15, x30 + \op xzr, x15, x30, lsl #0 + \op x0, xzr, x30, lsl #63 + \op x0, x15, xzr, lsr #0 + \op xzr, xzr, x30, lsr #63 + \op x0, xzr, xzr, asr #0 + \op xzr, xzr, xzr, asr #63 +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * C5.6.5 ADD (shifted register) + */ + addsub_shiftreg add + /* + * C5.6.8 ADDS (shifted register) + * C5.6.43 CMN (shifted register) (alias) + */ + addsub_shiftreg adds + /* + * C5.6.196 SUB (shifted register) + * C5.6.135 NEG (alias) + */ + addsub_shiftreg sub + /* + * C5.6.199 SUBS (shifted register) + * C5.6.46 CMP (shifted register) (alias) + * C5.6.136 NEGS (alias) + */ + addsub_shiftreg subs +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.bitfield.out b/usr/src/test/util-tests/tests/dis/arm64/tst.bitfield.out new file mode 100755 index 0000000000..5dc9d5f9d3 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.bitfield.out @@ -0,0 +1,42 @@ + libdis_test: e0 7f 1e 13 sbfm w0, wzr, #0x1e, #0x1f + libdis_test+0x4: e0 ff 5f 93 sbfm x0, xzr, #0x1f, #0x3f + libdis_test+0x8: e0 03 1f 13 sbfm w0, wzr, #0x1f, #0x0 + libdis_test+0xc: e0 03 7f 93 sbfm x0, xzr, #0x3f, #0x0 + libdis_test+0x10: e0 1f 00 13 sbfm w0, wzr, #0x0, #0x7 + libdis_test+0x14: e0 1f 40 93 sbfm x0, xzr, #0x0, #0x7 + libdis_test+0x18: e0 3f 00 13 sbfm w0, wzr, #0x0, #0xf + libdis_test+0x1c: e0 3f 40 93 sbfm x0, xzr, #0x0, #0xf + libdis_test+0x20: e0 7f 00 13 sbfm w0, wzr, #0x0, #0x1f + libdis_test+0x24: e0 7f 40 93 sbfm x0, xzr, #0x0, #0x1f + libdis_test+0x28: e0 7b 1f 13 sbfm w0, wzr, #0x1f, #0x1e + libdis_test+0x2c: e0 fb 7f 93 sbfm x0, xzr, #0x3f, #0x3e + libdis_test+0x30: e0 7b 1e 13 sbfm w0, wzr, #0x1e, #0x1e + libdis_test+0x34: e0 fb 7e 93 sbfm x0, xzr, #0x3e, #0x3e + libdis_test+0x38: e0 7f 1e 33 bfm w0, wzr, #0x1e, #0x1f + libdis_test+0x3c: e0 ff 5f b3 bfm x0, xzr, #0x1f, #0x3f + libdis_test+0x40: e0 03 1f 33 bfm w0, wzr, #0x1f, #0x0 + libdis_test+0x44: e0 03 7f b3 bfm x0, xzr, #0x3f, #0x0 + libdis_test+0x48: e0 1f 00 33 bfm w0, wzr, #0x0, #0x7 + libdis_test+0x4c: e0 1f 40 b3 bfm x0, xzr, #0x0, #0x7 + libdis_test+0x50: e0 3f 00 33 bfm w0, wzr, #0x0, #0xf + libdis_test+0x54: e0 3f 40 b3 bfm x0, xzr, #0x0, #0xf + libdis_test+0x58: e0 7f 00 33 bfm w0, wzr, #0x0, #0x1f + libdis_test+0x5c: e0 7f 40 b3 bfm x0, xzr, #0x0, #0x1f + libdis_test+0x60: e0 7b 1f 33 bfm w0, wzr, #0x1f, #0x1e + libdis_test+0x64: e0 fb 7f b3 bfm x0, xzr, #0x3f, #0x3e + libdis_test+0x68: e0 7b 1e 33 bfm w0, wzr, #0x1e, #0x1e + libdis_test+0x6c: e0 fb 7e b3 bfm x0, xzr, #0x3e, #0x3e + libdis_test+0x70: e0 7f 1e 53 ubfm w0, wzr, #0x1e, #0x1f + libdis_test+0x74: e0 ff 5f d3 ubfm x0, xzr, #0x1f, #0x3f + libdis_test+0x78: e0 03 1f 53 ubfm w0, wzr, #0x1f, #0x0 + libdis_test+0x7c: e0 03 7f d3 ubfm x0, xzr, #0x3f, #0x0 + libdis_test+0x80: e0 1f 00 53 ubfm w0, wzr, #0x0, #0x7 + libdis_test+0x84: e0 1f 40 d3 ubfm x0, xzr, #0x0, #0x7 + libdis_test+0x88: e0 3f 00 53 ubfm w0, wzr, #0x0, #0xf + libdis_test+0x8c: e0 3f 40 d3 ubfm x0, xzr, #0x0, #0xf + libdis_test+0x90: e0 7f 00 53 ubfm w0, wzr, #0x0, #0x1f + libdis_test+0x94: e0 7f 40 d3 ubfm x0, xzr, #0x0, #0x1f + libdis_test+0x98: e0 7b 1f 53 ubfm w0, wzr, #0x1f, #0x1e + libdis_test+0x9c: e0 fb 7f d3 ubfm x0, xzr, #0x3f, #0x3e + libdis_test+0xa0: e0 7b 1e 53 ubfm w0, wzr, #0x1e, #0x1e + libdis_test+0xa4: e0 fb 7e d3 ubfm x0, xzr, #0x3e, #0x3e diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.bitfield.s b/usr/src/test/util-tests/tests/dis/arm64/tst.bitfield.s new file mode 100755 index 0000000000..5fd2623eb9 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.bitfield.s @@ -0,0 +1,73 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.4.2 Bitfield + */ +.macro bitfield op + /* Test for SBFM -> ASR/UBFM -> LSR (imms == 31/63) */ + \op w0, wzr, #30, #31 + \op x0, xzr, #31, #63 + /* Test for SBFM -> SBFIZ/BFM -> BFI (imms < immr) */ + \op w0, wzr, #31, #0 + \op x0, xzr, #63, #0 + /* Test for SBFM -> SXTB/UBFM -> UXTB (immr == 0 && imms == 7) */ + \op w0, wzr, #0, #7 + \op x0, xzr, #0, #7 + /* Test for SBFM -> SXTH/UBFM -> UXTH (immr == 0 && imms == 15) */ + \op w0, wzr, #0, #15 + \op x0, xzr, #0, #15 + /* Test for SBFM -> SXTW (immr == 0 && imms == 31) */ + \op w0, wzr, #0, #31 + \op x0, xzr, #0, #31 + /* Test for UBFM -> LSL (imms != 31/63 && immr == imms+1) */ + \op w0, wzr, #31, #30 + \op x0, xzr, #63, #62 + /* Test for SBFM -> SBFIZ (any operation not already matched above) */ + \op w0, wzr, #30, #30 + \op x0, xzr, #62, #62 +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * C5.6.158 SBFM + * C5.6.16 ASR (immediate) (alias) + * C5.6.157 SBFIZ (alias) + * C5.6.159 SBFX (alias) + * C5.6.201 SXTB (alias) + * C5.6.202 SXTH (alias) + * C5.6.203 SXTW (alias) + */ + bitfield sbfm + /* + * C5.6.22 BFM + * C5.6.21 BFI (alias) + * C5.6.23 BFXIL (alias) + */ + bitfield bfm + /* + * C5.6.212 UBFM + * C5.6.114 LSL (immediate) (alias) + * C5.6.117 LSR (immediate) (alias) + * C5.6.211 UBFIZ (alias) + * C5.6.213 UBFX (alias) + * C5.6.220 UXTB (alias) + * C5.6.221 UXTH (alias) + */ + bitfield ubfm +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.branch.out b/usr/src/test/util-tests/tests/dis/arm64/tst.branch.out new file mode 100755 index 0000000000..70271d2bed --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.branch.out @@ -0,0 +1,31 @@ + libdis_test: 00 00 00 34 cbz w0, +0x0 <libdis_test> + libdis_test+0x4: 7f 00 00 b4 cbz xzr, +0xc <libdis_test+0x10> + libdis_test+0x8: df ff ff 35 cbnz wzr, -0x8 <libdis_test> + libdis_test+0xc: 1e 02 00 b5 cbnz x30, +0x40 <libdis_test+0x4c> + libdis_test+0x10: 00 00 00 54 b.eq +0x0 <libdis_test+0x10> + libdis_test+0x14: c1 01 00 54 b.ne +0x38 <libdis_test+0x4c> + libdis_test+0x18: c2 ff ff 54 b.cs -0x8 <libdis_test+0x10> + libdis_test+0x1c: 83 01 00 54 b.cc +0x30 <libdis_test+0x4c> + libdis_test+0x20: 84 ff ff 54 b.mi -0x10 <libdis_test+0x10> + libdis_test+0x24: 45 01 00 54 b.pl +0x28 <libdis_test+0x4c> + libdis_test+0x28: 46 ff ff 54 b.vs -0x18 <libdis_test+0x10> + libdis_test+0x2c: 07 01 00 54 b.vc +0x20 <libdis_test+0x4c> + libdis_test+0x30: 88 fe ff 54 b.hi -0x30 <libdis_test> + libdis_test+0x34: 49 01 00 54 b.ls +0x28 <libdis_test+0x5c> + libdis_test+0x38: 4a fe ff 54 b.ge -0x38 <libdis_test> + libdis_test+0x3c: 0b 01 00 54 b.lt +0x20 <libdis_test+0x5c> + libdis_test+0x40: 0c fe ff 54 b.gt -0x40 <libdis_test> + libdis_test+0x44: cd 00 00 54 b.le +0x18 <libdis_test+0x5c> + libdis_test+0x48: ce fd ff 54 b.al -0x48 <libdis_test> + libdis_test+0x4c: 20 fe 07 36 tbz w0, #0x0, -0x3c <libdis_test+0x10> + libdis_test+0x50: ff ff ff b6 tbz xzr, #0x3f, -0x4 <libdis_test+0x4c> + libdis_test+0x54: 7f fd 07 37 tbnz wzr, #0x0, -0x54 <libdis_test> + libdis_test+0x58: 3e 00 f8 b7 tbnz x30, #0x3f, +0x4 <libdis_test+0x5c> + libdis_test+0x5c: fc ff ff 17 b -0x10 <libdis_test+0x4c> + libdis_test+0x60: ff ff ff 97 bl -0x4 <libdis_test+0x5c> + libdis_test+0x64: 00 00 1f d6 br x0 + libdis_test+0x68: c0 03 3f d6 blr x30 + libdis_test+0x6c: c0 03 5f d6 ret + libdis_test+0x70: 00 00 5f d6 ret x0 + libdis_test+0x74: e0 03 9f d6 eret + libdis_test+0x78: e0 03 bf d6 drps diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.branch.s b/usr/src/test/util-tests/tests/dis/arm64/tst.branch.s new file mode 100755 index 0000000000..feec869ef3 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.branch.s @@ -0,0 +1,59 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.2 Branches + */ +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: +1: + cbz w0, 1b + cbz xzr, 2f + cbnz wzr, 1b + cbnz x30, 3f +2: + b.eq 2b + b.ne 3f + b.cs 2b + b.cc 3f + b.mi 2b + b.pl 3f + b.vs 2b + b.vc 3f + b.hi 1b + b.ls 4f + b.ge 1b + b.lt 4f + b.gt 1b + b.le 4f + b.al 1b +3: + tbz w0, #0, 2b + tbz xzr, #63, 3b + tbnz wzr, #0, 1b + tbnz x30, #63, 4f +4: + b 3b + bl 4b +5: + br x0 + blr x30 + ret + ret x0 + eret + drps +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.branches.out b/usr/src/test/util-tests/tests/dis/arm64/tst.branches.out new file mode 100644 index 0000000000..1009e895df --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.branches.out @@ -0,0 +1,34 @@ + libdis_test: 20 04 00 54 b.eq +0x84 <libdis_test+0x84> + libdis_test+0x4: 01 04 00 54 b.ne +0x80 <libdis_test+0x84> + libdis_test+0x8: e2 03 00 54 b.cs +0x7c <libdis_test+0x84> + libdis_test+0xc: c3 03 00 54 b.cc +0x78 <libdis_test+0x84> + libdis_test+0x10: a4 03 00 54 b.mi +0x74 <libdis_test+0x84> + libdis_test+0x14: 85 03 00 54 b.pl +0x70 <libdis_test+0x84> + libdis_test+0x18: 66 03 00 54 b.vs +0x6c <libdis_test+0x84> + libdis_test+0x1c: 47 03 00 54 b.vc +0x68 <libdis_test+0x84> + libdis_test+0x20: 28 03 00 54 b.hi +0x64 <libdis_test+0x84> + libdis_test+0x24: 09 03 00 54 b.ls +0x60 <libdis_test+0x84> + libdis_test+0x28: ea 02 00 54 b.ge +0x5c <libdis_test+0x84> + libdis_test+0x2c: cb 02 00 54 b.lt +0x58 <libdis_test+0x84> + libdis_test+0x30: ac 02 00 54 b.gt +0x54 <libdis_test+0x84> + libdis_test+0x34: 8d 02 00 54 b.le +0x50 <libdis_test+0x84> + libdis_test+0x38: 6e 02 00 54 b.al +0x4c <libdis_test+0x84> + libdis_test+0x3c: 4f 02 00 54 b.nv +0x48 <libdis_test+0x84> + libdis_test+0x40: 00 00 1f d6 br x0 + libdis_test+0x44: e0 03 1f d6 br xzr + libdis_test+0x48: 60 02 3f d6 blr x19 + libdis_test+0x4c: c0 03 5f d6 ret + libdis_test+0x50: 20 01 5f d6 ret x9 + libdis_test+0x54: e0 03 9f d6 eret + libdis_test+0x58: e0 03 bf d6 drps + libdis_test+0x5c: 0a 00 00 14 b +0x28 <libdis_test+0x84> + libdis_test+0x60: 09 00 00 94 bl +0x24 <libdis_test+0x84> + libdis_test+0x64: 13 01 00 34 cbz w19, +0x20 <libdis_test+0x84> + libdis_test+0x68: ff 00 00 b4 cbz xzr, +0x1c <libdis_test+0x84> + libdis_test+0x6c: c3 00 00 35 cbnz w3, +0x18 <libdis_test+0x84> + libdis_test+0x70: a2 00 00 b5 cbnz x2, +0x14 <libdis_test+0x84> + libdis_test+0x74: 9f 00 98 36 tbz wzr, #0x13, +0x10 <libdis_test+0x84> + libdis_test+0x78: 78 00 18 b6 tbz x24, #0x23, +0xc <libdis_test+0x84> + libdis_test+0x7c: 44 00 10 37 tbnz w4, #0x2, +0x8 <libdis_test+0x84> + libdis_test+0x80: 30 00 f0 b7 tbnz x16, #0x3e, +0x4 <libdis_test+0x84> + libdis_test+0x84: 00 00 00 8b add x0, x0, x0 diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.branches.s b/usr/src/test/util-tests/tests/dis/arm64/tst.branches.s new file mode 100644 index 0000000000..010e6bbea3 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.branches.s @@ -0,0 +1,70 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * Test Data - Immediate group dissassembly + */ + +.text +.align 16 +.globl libdis_test +.type libdis_test, %function +libdis_test: + /* Branch (conditional) */ + B.EQ branch_target + B.NE branch_target + B.CS branch_target + B.CC branch_target + B.MI branch_target + B.PL branch_target + B.VS branch_target + B.VC branch_target + B.HI branch_target + B.LS branch_target + B.GE branch_target + B.LT branch_target + B.GT branch_target + B.LE branch_target + B.AL branch_target + B.NV branch_target + + /* Unconditional Branch (register) */ + BR X0 + BR XZR + BLR X19 + RET /* Defaults to X30 */ + RET X9 + ERET + DRPS + + /* Unconditional Branch (immediate) */ + B branch_target + BL branch_target + + /* Compare and Branch (immediate) */ + CBZ W19, branch_target + CBZ XZR, branch_target + CBNZ W3, branch_target + CBNZ X2, branch_target + + /* Test and Branch (immediate) */ + TBZ WZR, #19, branch_target + TBZ X24, #35, branch_target + TBNZ W4, #2, branch_target + TBNZ X16, #62, branch_target + + branch_target: ADD X0, X0, X0 +.size libdis_test, [.-libdis_test] + diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.condcomp-imm.out b/usr/src/test/util-tests/tests/dis/arm64/tst.condcomp-imm.out new file mode 100755 index 0000000000..6667b45eb3 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.condcomp-imm.out @@ -0,0 +1,64 @@ + libdis_test: 00 08 40 3a ccmn w0, #0x0, #0x0, eq + libdis_test+0x4: 01 18 5f 3a ccmn w0, #0x1f, #0x1, ne + libdis_test+0x8: e2 2b 40 3a ccmn wzr, #0x0, #0x2, cs + libdis_test+0xc: e3 3b 5f 3a ccmn wzr, #0x1f, #0x3, cc + libdis_test+0x10: 04 48 40 3a ccmn w0, #0x0, #0x4, mi + libdis_test+0x14: 05 58 5f 3a ccmn w0, #0x1f, #0x5, pl + libdis_test+0x18: e6 6b 40 3a ccmn wzr, #0x0, #0x6, vs + libdis_test+0x1c: e7 7b 5f 3a ccmn wzr, #0x1f, #0x7, vc + libdis_test+0x20: 08 88 40 3a ccmn w0, #0x0, #0x8, hi + libdis_test+0x24: 09 98 5f 3a ccmn w0, #0x1f, #0x9, ls + libdis_test+0x28: ea ab 40 3a ccmn wzr, #0x0, #0xa, ge + libdis_test+0x2c: eb bb 5f 3a ccmn wzr, #0x1f, #0xb, lt + libdis_test+0x30: 0c c8 40 3a ccmn w0, #0x0, #0xc, gt + libdis_test+0x34: 0d d8 5f 3a ccmn w0, #0x1f, #0xd, le + libdis_test+0x38: ee eb 40 3a ccmn wzr, #0x0, #0xe, al + libdis_test+0x3c: ef fb 5f 3a ccmn wzr, #0x1f, #0xf, nv + libdis_test+0x40: 00 08 40 ba ccmn x0, #0x0, #0x0, eq + libdis_test+0x44: 01 18 5f ba ccmn x0, #0x1f, #0x1, ne + libdis_test+0x48: e2 2b 40 ba ccmn xzr, #0x0, #0x2, cs + libdis_test+0x4c: e3 3b 5f ba ccmn xzr, #0x1f, #0x3, cc + libdis_test+0x50: 04 48 40 ba ccmn x0, #0x0, #0x4, mi + libdis_test+0x54: 05 58 5f ba ccmn x0, #0x1f, #0x5, pl + libdis_test+0x58: e6 6b 40 ba ccmn xzr, #0x0, #0x6, vs + libdis_test+0x5c: e7 7b 5f ba ccmn xzr, #0x1f, #0x7, vc + libdis_test+0x60: 08 88 40 ba ccmn x0, #0x0, #0x8, hi + libdis_test+0x64: 09 98 5f ba ccmn x0, #0x1f, #0x9, ls + libdis_test+0x68: ea ab 40 ba ccmn xzr, #0x0, #0xa, ge + libdis_test+0x6c: eb bb 5f ba ccmn xzr, #0x1f, #0xb, lt + libdis_test+0x70: 0c c8 40 ba ccmn x0, #0x0, #0xc, gt + libdis_test+0x74: 0d d8 5f ba ccmn x0, #0x1f, #0xd, le + libdis_test+0x78: ee eb 40 ba ccmn xzr, #0x0, #0xe, al + libdis_test+0x7c: ef fb 5f ba ccmn xzr, #0x1f, #0xf, nv + libdis_test+0x80: 00 08 40 7a ccmp w0, #0x0, #0x0, eq + libdis_test+0x84: 01 18 5f 7a ccmp w0, #0x1f, #0x1, ne + libdis_test+0x88: e2 2b 40 7a ccmp wzr, #0x0, #0x2, cs + libdis_test+0x8c: e3 3b 5f 7a ccmp wzr, #0x1f, #0x3, cc + libdis_test+0x90: 04 48 40 7a ccmp w0, #0x0, #0x4, mi + libdis_test+0x94: 05 58 5f 7a ccmp w0, #0x1f, #0x5, pl + libdis_test+0x98: e6 6b 40 7a ccmp wzr, #0x0, #0x6, vs + libdis_test+0x9c: e7 7b 5f 7a ccmp wzr, #0x1f, #0x7, vc + libdis_test+0xa0: 08 88 40 7a ccmp w0, #0x0, #0x8, hi + libdis_test+0xa4: 09 98 5f 7a ccmp w0, #0x1f, #0x9, ls + libdis_test+0xa8: ea ab 40 7a ccmp wzr, #0x0, #0xa, ge + libdis_test+0xac: eb bb 5f 7a ccmp wzr, #0x1f, #0xb, lt + libdis_test+0xb0: 0c c8 40 7a ccmp w0, #0x0, #0xc, gt + libdis_test+0xb4: 0d d8 5f 7a ccmp w0, #0x1f, #0xd, le + libdis_test+0xb8: ee eb 40 7a ccmp wzr, #0x0, #0xe, al + libdis_test+0xbc: ef fb 5f 7a ccmp wzr, #0x1f, #0xf, nv + libdis_test+0xc0: 00 08 40 fa ccmp x0, #0x0, #0x0, eq + libdis_test+0xc4: 01 18 5f fa ccmp x0, #0x1f, #0x1, ne + libdis_test+0xc8: e2 2b 40 fa ccmp xzr, #0x0, #0x2, cs + libdis_test+0xcc: e3 3b 5f fa ccmp xzr, #0x1f, #0x3, cc + libdis_test+0xd0: 04 48 40 fa ccmp x0, #0x0, #0x4, mi + libdis_test+0xd4: 05 58 5f fa ccmp x0, #0x1f, #0x5, pl + libdis_test+0xd8: e6 6b 40 fa ccmp xzr, #0x0, #0x6, vs + libdis_test+0xdc: e7 7b 5f fa ccmp xzr, #0x1f, #0x7, vc + libdis_test+0xe0: 08 88 40 fa ccmp x0, #0x0, #0x8, hi + libdis_test+0xe4: 09 98 5f fa ccmp x0, #0x1f, #0x9, ls + libdis_test+0xe8: ea ab 40 fa ccmp xzr, #0x0, #0xa, ge + libdis_test+0xec: eb bb 5f fa ccmp xzr, #0x1f, #0xb, lt + libdis_test+0xf0: 0c c8 40 fa ccmp x0, #0x0, #0xc, gt + libdis_test+0xf4: 0d d8 5f fa ccmp x0, #0x1f, #0xd, le + libdis_test+0xf8: ee eb 40 fa ccmp xzr, #0x0, #0xe, al + libdis_test+0xfc: ef fb 5f fa ccmp xzr, #0x1f, #0xf, nv diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.condcomp-imm.s b/usr/src/test/util-tests/tests/dis/arm64/tst.condcomp-imm.s new file mode 100755 index 0000000000..5478383bd2 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.condcomp-imm.s @@ -0,0 +1,66 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.5.4 Conditional compare (immediate) + */ +.macro condcomp_imm op + /* 32-bit */ + \op w0, #0, #0, eq + \op w0, #31, #1, ne + \op wzr, #0, #2, cs + \op wzr, #31, #3, cc + \op w0, #0, #4, mi + \op w0, #31, #5, pl + \op wzr, #0, #6, vs + \op wzr, #31, #7, vc + \op w0, #0, #8, hi + \op w0, #31, #9, ls + \op wzr, #0, #10, ge + \op wzr, #31, #11, lt + \op w0, #0, #12, gt + \op w0, #31, #13, le + \op wzr, #0, #14, al + \op wzr, #31, #15, nv + /* 64-bit */ + \op x0, #0, #0, eq + \op x0, #31, #1, ne + \op xzr, #0, #2, cs + \op xzr, #31, #3, cc + \op x0, #0, #4, mi + \op x0, #31, #5, pl + \op xzr, #0, #6, vs + \op xzr, #31, #7, vc + \op x0, #0, #8, hi + \op x0, #31, #9, ls + \op xzr, #0, #10, ge + \op xzr, #31, #11, lt + \op x0, #0, #12, gt + \op x0, #31, #13, le + \op xzr, #0, #14, al + \op xzr, #31, #15, nv +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * C5.6.32 CCMN (immediate) + * C5.6.34 CCMP (immediate) + */ + condcomp_imm ccmn + condcomp_imm ccmp +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.condcomp-reg.out b/usr/src/test/util-tests/tests/dis/arm64/tst.condcomp-reg.out new file mode 100755 index 0000000000..a5451435e0 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.condcomp-reg.out @@ -0,0 +1,64 @@ + libdis_test: 00 00 40 3a ccmn w0, w0, #0x0, eq + libdis_test+0x4: 01 10 5f 3a ccmn w0, wzr, #0x1, ne + libdis_test+0x8: e2 23 40 3a ccmn wzr, w0, #0x2, cs + libdis_test+0xc: e3 33 5f 3a ccmn wzr, wzr, #0x3, cc + libdis_test+0x10: 04 40 40 3a ccmn w0, w0, #0x4, mi + libdis_test+0x14: 05 50 5f 3a ccmn w0, wzr, #0x5, pl + libdis_test+0x18: e6 63 40 3a ccmn wzr, w0, #0x6, vs + libdis_test+0x1c: e7 73 5f 3a ccmn wzr, wzr, #0x7, vc + libdis_test+0x20: 08 80 40 3a ccmn w0, w0, #0x8, hi + libdis_test+0x24: 09 90 5f 3a ccmn w0, wzr, #0x9, ls + libdis_test+0x28: ea a3 40 3a ccmn wzr, w0, #0xa, ge + libdis_test+0x2c: eb b3 5f 3a ccmn wzr, wzr, #0xb, lt + libdis_test+0x30: 0c c0 40 3a ccmn w0, w0, #0xc, gt + libdis_test+0x34: 0d d0 5f 3a ccmn w0, wzr, #0xd, le + libdis_test+0x38: ee e3 40 3a ccmn wzr, w0, #0xe, al + libdis_test+0x3c: ef f3 5f 3a ccmn wzr, wzr, #0xf, nv + libdis_test+0x40: 00 00 40 ba ccmn x0, x0, #0x0, eq + libdis_test+0x44: 01 10 5f ba ccmn x0, xzr, #0x1, ne + libdis_test+0x48: e2 23 40 ba ccmn xzr, x0, #0x2, cs + libdis_test+0x4c: e3 33 5f ba ccmn xzr, xzr, #0x3, cc + libdis_test+0x50: 04 40 40 ba ccmn x0, x0, #0x4, mi + libdis_test+0x54: 05 50 5f ba ccmn x0, xzr, #0x5, pl + libdis_test+0x58: e6 63 40 ba ccmn xzr, x0, #0x6, vs + libdis_test+0x5c: e7 73 5f ba ccmn xzr, xzr, #0x7, vc + libdis_test+0x60: 08 80 40 ba ccmn x0, x0, #0x8, hi + libdis_test+0x64: 09 90 5f ba ccmn x0, xzr, #0x9, ls + libdis_test+0x68: ea a3 40 ba ccmn xzr, x0, #0xa, ge + libdis_test+0x6c: eb b3 5f ba ccmn xzr, xzr, #0xb, lt + libdis_test+0x70: 0c c0 40 ba ccmn x0, x0, #0xc, gt + libdis_test+0x74: 0d d0 5f ba ccmn x0, xzr, #0xd, le + libdis_test+0x78: ee e3 40 ba ccmn xzr, x0, #0xe, al + libdis_test+0x7c: ef f3 5f ba ccmn xzr, xzr, #0xf, nv + libdis_test+0x80: 00 00 40 7a ccmp w0, w0, #0x0, eq + libdis_test+0x84: 01 10 5f 7a ccmp w0, wzr, #0x1, ne + libdis_test+0x88: e2 23 40 7a ccmp wzr, w0, #0x2, cs + libdis_test+0x8c: e3 33 5f 7a ccmp wzr, wzr, #0x3, cc + libdis_test+0x90: 04 40 40 7a ccmp w0, w0, #0x4, mi + libdis_test+0x94: 05 50 5f 7a ccmp w0, wzr, #0x5, pl + libdis_test+0x98: e6 63 40 7a ccmp wzr, w0, #0x6, vs + libdis_test+0x9c: e7 73 5f 7a ccmp wzr, wzr, #0x7, vc + libdis_test+0xa0: 08 80 40 7a ccmp w0, w0, #0x8, hi + libdis_test+0xa4: 09 90 5f 7a ccmp w0, wzr, #0x9, ls + libdis_test+0xa8: ea a3 40 7a ccmp wzr, w0, #0xa, ge + libdis_test+0xac: eb b3 5f 7a ccmp wzr, wzr, #0xb, lt + libdis_test+0xb0: 0c c0 40 7a ccmp w0, w0, #0xc, gt + libdis_test+0xb4: 0d d0 5f 7a ccmp w0, wzr, #0xd, le + libdis_test+0xb8: ee e3 40 7a ccmp wzr, w0, #0xe, al + libdis_test+0xbc: ef f3 5f 7a ccmp wzr, wzr, #0xf, nv + libdis_test+0xc0: 00 00 40 fa ccmp x0, x0, #0x0, eq + libdis_test+0xc4: 01 10 5f fa ccmp x0, xzr, #0x1, ne + libdis_test+0xc8: e2 23 40 fa ccmp xzr, x0, #0x2, cs + libdis_test+0xcc: e3 33 5f fa ccmp xzr, xzr, #0x3, cc + libdis_test+0xd0: 04 40 40 fa ccmp x0, x0, #0x4, mi + libdis_test+0xd4: 05 50 5f fa ccmp x0, xzr, #0x5, pl + libdis_test+0xd8: e6 63 40 fa ccmp xzr, x0, #0x6, vs + libdis_test+0xdc: e7 73 5f fa ccmp xzr, xzr, #0x7, vc + libdis_test+0xe0: 08 80 40 fa ccmp x0, x0, #0x8, hi + libdis_test+0xe4: 09 90 5f fa ccmp x0, xzr, #0x9, ls + libdis_test+0xe8: ea a3 40 fa ccmp xzr, x0, #0xa, ge + libdis_test+0xec: eb b3 5f fa ccmp xzr, xzr, #0xb, lt + libdis_test+0xf0: 0c c0 40 fa ccmp x0, x0, #0xc, gt + libdis_test+0xf4: 0d d0 5f fa ccmp x0, xzr, #0xd, le + libdis_test+0xf8: ee e3 40 fa ccmp xzr, x0, #0xe, al + libdis_test+0xfc: ef f3 5f fa ccmp xzr, xzr, #0xf, nv diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.condcomp-reg.s b/usr/src/test/util-tests/tests/dis/arm64/tst.condcomp-reg.s new file mode 100755 index 0000000000..6b61fb0c5f --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.condcomp-reg.s @@ -0,0 +1,66 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.5.5 Conditional compare (register) + */ +.macro condcomp_reg op + /* 32-bit */ + \op w0, w0, #0, eq + \op w0, wzr, #1, ne + \op wzr, w0, #2, cs + \op wzr, wzr, #3, cc + \op w0, w0, #4, mi + \op w0, wzr, #5, pl + \op wzr, w0, #6, vs + \op wzr, wzr, #7, vc + \op w0, w0, #8, hi + \op w0, wzr, #9, ls + \op wzr, w0, #10, ge + \op wzr, wzr, #11, lt + \op w0, w0, #12, gt + \op w0, wzr, #13, le + \op wzr, w0, #14, al + \op wzr, wzr, #15, nv + /* 64-bit */ + \op x0, x0, #0, eq + \op x0, xzr, #1, ne + \op xzr, x0, #2, cs + \op xzr, xzr, #3, cc + \op x0, x0, #4, mi + \op x0, xzr, #5, pl + \op xzr, x0, #6, vs + \op xzr, xzr, #7, vc + \op x0, x0, #8, hi + \op x0, xzr, #9, ls + \op xzr, x0, #10, ge + \op xzr, xzr, #11, lt + \op x0, x0, #12, gt + \op x0, xzr, #13, le + \op xzr, x0, #14, al + \op xzr, xzr, #15, nv +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * C5.6.33 CCMN (register) + * C5.6.35 CCMP (register) + */ + condcomp_reg ccmn + condcomp_reg ccmp +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.condsel.out b/usr/src/test/util-tests/tests/dis/arm64/tst.condsel.out new file mode 100755 index 0000000000..b0a66cf496 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.condsel.out @@ -0,0 +1,128 @@ + libdis_test: e0 01 9e 1a csel w0, w15, w30, eq + libdis_test+0x4: ff 11 9e 1a csel wzr, w15, w30, ne + libdis_test+0x8: e0 23 9e 1a csel w0, wzr, w30, cs + libdis_test+0xc: e0 31 9f 1a csel w0, w15, wzr, cc + libdis_test+0x10: ff 43 9e 1a csel wzr, wzr, w30, mi + libdis_test+0x14: ff 51 9f 1a csel wzr, w15, wzr, pl + libdis_test+0x18: e0 63 9f 1a csel w0, wzr, wzr, vs + libdis_test+0x1c: ff 73 9f 1a csel wzr, wzr, wzr, vc + libdis_test+0x20: e0 81 9e 1a csel w0, w15, w30, hi + libdis_test+0x24: 00 90 9e 1a csel w0, w0, w30, ls + libdis_test+0x28: e0 a1 80 1a csel w0, w15, w0, ge + libdis_test+0x2c: 00 b0 9e 1a csel w0, w0, w30, lt + libdis_test+0x30: 00 c0 80 1a csel w0, w0, w0, gt + libdis_test+0x34: e0 d1 80 1a csel w0, w15, w0, le + libdis_test+0x38: 00 e0 80 1a csel w0, w0, w0, al + libdis_test+0x3c: ff f3 9f 1a csel wzr, wzr, wzr, nv + libdis_test+0x40: e0 01 9e 9a csel x0, x15, x30, eq + libdis_test+0x44: ff 11 9e 9a csel xzr, x15, x30, ne + libdis_test+0x48: e0 23 9e 9a csel x0, xzr, x30, cs + libdis_test+0x4c: e0 31 9f 9a csel x0, x15, xzr, cc + libdis_test+0x50: ff 43 9e 9a csel xzr, xzr, x30, mi + libdis_test+0x54: ff 51 9f 9a csel xzr, x15, xzr, pl + libdis_test+0x58: e0 63 9f 9a csel x0, xzr, xzr, vs + libdis_test+0x5c: ff 73 9f 9a csel xzr, xzr, xzr, vc + libdis_test+0x60: e0 81 9e 9a csel x0, x15, x30, hi + libdis_test+0x64: 00 90 9e 9a csel x0, x0, x30, ls + libdis_test+0x68: e0 a1 80 9a csel x0, x15, x0, ge + libdis_test+0x6c: 00 b0 9e 9a csel x0, x0, x30, lt + libdis_test+0x70: 00 c0 80 9a csel x0, x0, x0, gt + libdis_test+0x74: e0 d1 80 9a csel x0, x15, x0, le + libdis_test+0x78: 00 e0 80 9a csel x0, x0, x0, al + libdis_test+0x7c: ff f3 9f 9a csel xzr, xzr, xzr, nv + libdis_test+0x80: e0 05 9e 1a csinc w0, w15, w30, eq + libdis_test+0x84: ff 15 9e 1a csinc wzr, w15, w30, ne + libdis_test+0x88: e0 27 9e 1a csinc w0, wzr, w30, cs + libdis_test+0x8c: e0 35 9f 1a csinc w0, w15, wzr, cc + libdis_test+0x90: ff 47 9e 1a csinc wzr, wzr, w30, mi + libdis_test+0x94: ff 55 9f 1a csinc wzr, w15, wzr, pl + libdis_test+0x98: e0 67 9f 1a csinc w0, wzr, wzr, vs + libdis_test+0x9c: ff 77 9f 1a csinc wzr, wzr, wzr, vc + libdis_test+0xa0: e0 85 9e 1a csinc w0, w15, w30, hi + libdis_test+0xa4: 00 94 9e 1a csinc w0, w0, w30, ls + libdis_test+0xa8: e0 a5 80 1a csinc w0, w15, w0, ge + libdis_test+0xac: 00 b4 9e 1a csinc w0, w0, w30, lt + libdis_test+0xb0: 00 c4 80 1a csinc w0, w0, w0, gt + libdis_test+0xb4: e0 d5 80 1a csinc w0, w15, w0, le + libdis_test+0xb8: 00 e4 80 1a csinc w0, w0, w0, al + libdis_test+0xbc: ff f7 9f 1a csinc wzr, wzr, wzr, nv + libdis_test+0xc0: e0 05 9e 9a csinc x0, x15, x30, eq + libdis_test+0xc4: ff 15 9e 9a csinc xzr, x15, x30, ne + libdis_test+0xc8: e0 27 9e 9a csinc x0, xzr, x30, cs + libdis_test+0xcc: e0 35 9f 9a csinc x0, x15, xzr, cc + libdis_test+0xd0: ff 47 9e 9a csinc xzr, xzr, x30, mi + libdis_test+0xd4: ff 55 9f 9a csinc xzr, x15, xzr, pl + libdis_test+0xd8: e0 67 9f 9a csinc x0, xzr, xzr, vs + libdis_test+0xdc: ff 77 9f 9a csinc xzr, xzr, xzr, vc + libdis_test+0xe0: e0 85 9e 9a csinc x0, x15, x30, hi + libdis_test+0xe4: 00 94 9e 9a csinc x0, x0, x30, ls + libdis_test+0xe8: e0 a5 80 9a csinc x0, x15, x0, ge + libdis_test+0xec: 00 b4 9e 9a csinc x0, x0, x30, lt + libdis_test+0xf0: 00 c4 80 9a csinc x0, x0, x0, gt + libdis_test+0xf4: e0 d5 80 9a csinc x0, x15, x0, le + libdis_test+0xf8: 00 e4 80 9a csinc x0, x0, x0, al + libdis_test+0xfc: ff f7 9f 9a csinc xzr, xzr, xzr, nv + libdis_test+0x100: e0 01 9e 5a csinv w0, w15, w30, eq + libdis_test+0x104: ff 11 9e 5a csinv wzr, w15, w30, ne + libdis_test+0x108: e0 23 9e 5a csinv w0, wzr, w30, cs + libdis_test+0x10c: e0 31 9f 5a csinv w0, w15, wzr, cc + libdis_test+0x110: ff 43 9e 5a csinv wzr, wzr, w30, mi + libdis_test+0x114: ff 51 9f 5a csinv wzr, w15, wzr, pl + libdis_test+0x118: e0 63 9f 5a csinv w0, wzr, wzr, vs + libdis_test+0x11c: ff 73 9f 5a csinv wzr, wzr, wzr, vc + libdis_test+0x120: e0 81 9e 5a csinv w0, w15, w30, hi + libdis_test+0x124: 00 90 9e 5a csinv w0, w0, w30, ls + libdis_test+0x128: e0 a1 80 5a csinv w0, w15, w0, ge + libdis_test+0x12c: 00 b0 9e 5a csinv w0, w0, w30, lt + libdis_test+0x130: 00 c0 80 5a csinv w0, w0, w0, gt + libdis_test+0x134: e0 d1 80 5a csinv w0, w15, w0, le + libdis_test+0x138: 00 e0 80 5a csinv w0, w0, w0, al + libdis_test+0x13c: ff f3 9f 5a csinv wzr, wzr, wzr, nv + libdis_test+0x140: e0 01 9e da csinv x0, x15, x30, eq + libdis_test+0x144: ff 11 9e da csinv xzr, x15, x30, ne + libdis_test+0x148: e0 23 9e da csinv x0, xzr, x30, cs + libdis_test+0x14c: e0 31 9f da csinv x0, x15, xzr, cc + libdis_test+0x150: ff 43 9e da csinv xzr, xzr, x30, mi + libdis_test+0x154: ff 51 9f da csinv xzr, x15, xzr, pl + libdis_test+0x158: e0 63 9f da csinv x0, xzr, xzr, vs + libdis_test+0x15c: ff 73 9f da csinv xzr, xzr, xzr, vc + libdis_test+0x160: e0 81 9e da csinv x0, x15, x30, hi + libdis_test+0x164: 00 90 9e da csinv x0, x0, x30, ls + libdis_test+0x168: e0 a1 80 da csinv x0, x15, x0, ge + libdis_test+0x16c: 00 b0 9e da csinv x0, x0, x30, lt + libdis_test+0x170: 00 c0 80 da csinv x0, x0, x0, gt + libdis_test+0x174: e0 d1 80 da csinv x0, x15, x0, le + libdis_test+0x178: 00 e0 80 da csinv x0, x0, x0, al + libdis_test+0x17c: ff f3 9f da csinv xzr, xzr, xzr, nv + libdis_test+0x180: e0 05 9e 5a csneg w0, w15, w30, eq + libdis_test+0x184: ff 15 9e 5a csneg wzr, w15, w30, ne + libdis_test+0x188: e0 27 9e 5a csneg w0, wzr, w30, cs + libdis_test+0x18c: e0 35 9f 5a csneg w0, w15, wzr, cc + libdis_test+0x190: ff 47 9e 5a csneg wzr, wzr, w30, mi + libdis_test+0x194: ff 55 9f 5a csneg wzr, w15, wzr, pl + libdis_test+0x198: e0 67 9f 5a csneg w0, wzr, wzr, vs + libdis_test+0x19c: ff 77 9f 5a csneg wzr, wzr, wzr, vc + libdis_test+0x1a0: e0 85 9e 5a csneg w0, w15, w30, hi + libdis_test+0x1a4: 00 94 9e 5a csneg w0, w0, w30, ls + libdis_test+0x1a8: e0 a5 80 5a csneg w0, w15, w0, ge + libdis_test+0x1ac: 00 b4 9e 5a csneg w0, w0, w30, lt + libdis_test+0x1b0: 00 c4 80 5a csneg w0, w0, w0, gt + libdis_test+0x1b4: e0 d5 80 5a csneg w0, w15, w0, le + libdis_test+0x1b8: 00 e4 80 5a csneg w0, w0, w0, al + libdis_test+0x1bc: ff f7 9f 5a csneg wzr, wzr, wzr, nv + libdis_test+0x1c0: e0 05 9e da csneg x0, x15, x30, eq + libdis_test+0x1c4: ff 15 9e da csneg xzr, x15, x30, ne + libdis_test+0x1c8: e0 27 9e da csneg x0, xzr, x30, cs + libdis_test+0x1cc: e0 35 9f da csneg x0, x15, xzr, cc + libdis_test+0x1d0: ff 47 9e da csneg xzr, xzr, x30, mi + libdis_test+0x1d4: ff 55 9f da csneg xzr, x15, xzr, pl + libdis_test+0x1d8: e0 67 9f da csneg x0, xzr, xzr, vs + libdis_test+0x1dc: ff 77 9f da csneg xzr, xzr, xzr, vc + libdis_test+0x1e0: e0 85 9e da csneg x0, x15, x30, hi + libdis_test+0x1e4: 00 94 9e da csneg x0, x0, x30, ls + libdis_test+0x1e8: e0 a5 80 da csneg x0, x15, x0, ge + libdis_test+0x1ec: 00 b4 9e da csneg x0, x0, x30, lt + libdis_test+0x1f0: 00 c4 80 da csneg x0, x0, x0, gt + libdis_test+0x1f4: e0 d5 80 da csneg x0, x15, x0, le + libdis_test+0x1f8: 00 e4 80 da csneg x0, x0, x0, al + libdis_test+0x1fc: ff f7 9f da csneg xzr, xzr, xzr, nv diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.condsel.s b/usr/src/test/util-tests/tests/dis/arm64/tst.condsel.s new file mode 100755 index 0000000000..bcc8805d2f --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.condsel.s @@ -0,0 +1,81 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.5.6 Conditional select + */ +.macro condsel op + /* 32-bit */ + \op w0, w15, w30, eq + \op wzr, w15, w30, ne + \op w0, wzr, w30, cs + \op w0, w15, wzr, cc + \op wzr, wzr, w30, mi + \op wzr, w15, wzr, pl + \op w0, wzr, wzr, vs + \op wzr, wzr, wzr, vc + \op w0, w15, w30, hi + \op w0, w0, w30, ls + \op w0, w15, w0, ge + \op w0, w0, w30, lt + \op w0, w0, w0, gt + \op w0, w15, w0, le + \op w0, w0, w0, al + \op wzr, wzr, wzr, nv + /* 64-bit */ + \op x0, x15, x30, eq + \op xzr, x15, x30, ne + \op x0, xzr, x30, cs + \op x0, x15, xzr, cc + \op xzr, xzr, x30, mi + \op xzr, x15, xzr, pl + \op x0, xzr, xzr, vs + \op xzr, xzr, xzr, vc + \op x0, x15, x30, hi + \op x0, x0, x30, ls + \op x0, x15, x0, ge + \op x0, x0, x30, lt + \op x0, x0, x0, gt + \op x0, x15, x0, le + \op x0, x0, x0, al + \op xzr, xzr, xzr, nv +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * C5.6.50 CSEL + */ + condsel csel + /* + * C5.6.53 CSINC + * C5.6.36 CINC (alias) + * C5.6.51 CSET (alias) + */ + condsel csinc + /* + * C5.6.54 CSINV + * C5.6.37 CINV (alias) + * C5.6.52 CSETM (alias) + */ + condsel csinv + /* + * C5.6.55 CSNEG + * C5.6.47 CNEG + */ + condsel csneg +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.data-imm.out b/usr/src/test/util-tests/tests/dis/arm64/tst.data-imm.out new file mode 100644 index 0000000000..ef7f41b8df --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.data-imm.out @@ -0,0 +1,27 @@ + libdis_test: 5f 03 00 10 adr xzr, +0x68 <libdis_test+0x68> + libdis_test+0x4: 00 00 00 90 adrp x0, -0x4 <libdis_test> + libdis_test+0x8: e0 13 00 11 add w0, wsp, #0x4 + libdis_test+0xc: 7f 06 40 11 add wsp, w19, #0x1, lsl #12 + libdis_test+0x10: 2a fc 03 b1 adds x10, x1, #0xff + libdis_test+0x14: ea ff 03 b1 adds x10, sp, #0xff + libdis_test+0x18: 3f 40 40 d1 sub sp, x1, #0x10, lsl #12 + libdis_test+0x1c: e0 23 00 f1 subs x0, sp, #0x8 + libdis_test+0x20: 04 bd bf 12 movn w4, #0xfde8, lsl #16 + libdis_test+0x24: ef 1f e0 92 movn x15, #0xff, lsl #48 + libdis_test+0x28: 24 00 80 52 movz w4, #0x1 + libdis_test+0x2c: 4d 00 c0 d2 movz x13, #0x2, lsl #32 + libdis_test+0x30: 1f 02 80 72 movk wzr, #0x10 + libdis_test+0x34: 80 00 a0 f2 movk x0, #0x4, lsl #16 + libdis_test+0x38: 24 01 00 13 sbfm w4, w9, #0x0, #0x0 + libdis_test+0x3c: 43 25 41 93 sbfm x3, x10, #0x1, #0x9 + libdis_test+0x40: 24 7d 00 33 bfm w4, w9, #0x0, #0x1f + libdis_test+0x44: ea e7 42 b3 bfm x10, xzr, #0x2, #0x39 + libdis_test+0x48: 21 0d 17 53 ubfm w1, w9, #0x17, #0x3 + libdis_test+0x4c: 1f 18 40 d3 ubfm xzr, x0, #0x0, #0x6 + libdis_test+0x50: 20 7c 9f 13 extr w0, w1, wzr, #0x1f + libdis_test+0x54: e0 13 81 13 extr w0, wzr, w1, #0x4 + libdis_test+0x58: bf 04 9e 13 extr wzr, w5, w30, #0x1 + libdis_test+0x5c: 2b f0 df 93 extr x11, x1, xzr, #0x3c + libdis_test+0x60: f2 af d3 93 extr x18, xzr, x19, #0x2b + libdis_test+0x64: 3f 0f de 93 extr xzr, x25, x30, #0x3 + libdis_test+0x68: 00 00 00 8b add x0, x0, x0 diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.data-imm.s b/usr/src/test/util-tests/tests/dis/arm64/tst.data-imm.s new file mode 100644 index 0000000000..a3d18ac7c0 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.data-imm.s @@ -0,0 +1,65 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * Test Data - Immediate group dissassembly + */ + +.text +.align 16 +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* ADR{P} */ + ADR XZR, branch_target + ADRP X0, libdis_test + + /* ADD/SUB - Immediate */ + ADD W0, WSP, #4 + ADD WSP, W19, #1, LSL #12 + ADDS X10, X1, #255 + ADDS X10, SP, #255 + SUB SP, X1, #16, LSL #12 + SUBS X0, SP, #8 + + /*TODO: Logical - immediate */ + + /* Move wide - immediate */ + MOVN W4, #65000, LSL #16 + MOVN X15, #255, LSL #48 + MOVZ W4, #1 + MOVZ X13, #2, LSL #32 + MOVK WZR, #16 + MOVK X0, #4, LSL #16 + + /* Bitfield - immediate */ + SBFM W4, W9, #0, #0 + SBFM X3, X10, #1, #9 + BFM W4, W9, #0, #31 + BFM X10, XZR, #2, #57 + UBFM W1, W9, #23, #3 + UBFM XZR, X0, #0, #6 + + /* Extract */ + EXTR W0, W1, WZR, #31 + EXTR W0, WZR, W1, #4 + EXTR WZR, W5, W30, #1 + EXTR X11, X1, XZR, #60 + EXTR X18, XZR, X19, #43 + EXTR XZR, X25, X30, #3 + + branch_target: ADD X0, X0, X0 + +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.data-reg.out b/usr/src/test/util-tests/tests/dis/arm64/tst.data-reg.out new file mode 100644 index 0000000000..770cd52669 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.data-reg.out @@ -0,0 +1,66 @@ + libdis_test: 29 00 c0 da rbit x9, x1 + libdis_test+0x4: 1f 00 c0 5a rbit wzr, w0 + libdis_test+0x8: c1 07 c0 da rev16 x1, x30 + libdis_test+0xc: e3 07 c0 5a rev16 w3, wzr + libdis_test+0x10: a6 08 c0 da rev32 x6, x5 + libdis_test+0x14: 9f 09 c0 da rev32 xzr, x12 + libdis_test+0x18: 77 08 c0 5a rev w23, w3 + libdis_test+0x1c: 84 0c c0 da rev x4, x4 + libdis_test+0x20: 29 11 c0 5a clz w9, w9 + libdis_test+0x24: ec 13 c0 da clz x12, xzr + libdis_test+0x28: 23 17 c0 5a cls w3, w25 + libdis_test+0x2c: 9d 17 c0 da cls x29, x28 + libdis_test+0x30: ec 0b c4 9a udiv x12, xzr, x4 + libdis_test+0x34: 82 08 df 1a udiv w2, w4, wzr + libdis_test+0x38: 3f 0c c4 9a sdiv xzr, x1, x4 + libdis_test+0x3c: 13 0c cf 1a sdiv w19, w0, w15 + libdis_test+0x40: 17 23 d9 9a lsl x23, x24, x25 + libdis_test+0x44: dd 23 c4 1a lsl w29, w30, w4 + libdis_test+0x48: 60 24 c1 9a lsr x0, x3, x1 + libdis_test+0x4c: e9 27 dd 1a lsr w9, wzr, w29 + libdis_test+0x50: 23 29 ca 9a asr x3, x9, x10 + libdis_test+0x54: 83 28 c8 1a asr w3, w4, w8 + libdis_test+0x58: 47 2c cc 9a ror x7, x2, x12 + libdis_test+0x5c: 87 2c c3 1a ror w7, w4, w3 + libdis_test+0x60: 38 fb 1a 8a and x24, x25, x26, lsl #62 + libdis_test+0x64: ee 51 50 0a and w14, w15, w16, lsr #20 + libdis_test+0x68: a4 80 a6 8a bic x4, x5, x6, asr #32 + libdis_test+0x6c: 61 0a f6 0a bic w1, w19, w22, ror #2 + libdis_test+0x70: ac 15 0e aa orr x12, x13, x14, lsl #5 + libdis_test+0x74: 61 04 5f 2a orr w1, w3, wzr, lsr #1 + libdis_test+0x78: 21 14 a1 aa orn x1, x1, x1, asr #5 + libdis_test+0x7c: 42 18 e2 2a orn w2, w2, w2, ror #6 + libdis_test+0x80: e7 cb 09 ca eor x7, xzr, x9, lsl #50 + libdis_test+0x84: 3f 30 43 4a eor wzr, w1, w3, lsr #12 + libdis_test+0x88: 40 38 a3 ca eon x0, x2, x3, asr #14 + libdis_test+0x8c: 40 50 e3 4a eon w0, w2, w3, ror #20 + libdis_test+0x90: 92 a9 0e ea ands x18, x12, x14, lsl #42 + libdis_test+0x94: 40 0c 58 6a ands w0, w2, w24, lsr #3 + libdis_test+0x98: 21 05 b3 ea bics x1, x9, x19, asr #1 + libdis_test+0x9c: 89 78 e1 6a bics w9, w4, w1, ror #30 + libdis_test+0xa0: 38 fb 1a 8b add x24, x25, x26, lsl #62 + libdis_test+0xa4: ee 51 50 0b add w14, w15, w16, lsr #20 + libdis_test+0xa8: a4 80 86 ab adds x4, x5, x6, asr #32 + libdis_test+0xac: 61 02 16 2b adds w1, w19, w22 + libdis_test+0xb0: ac 15 4e cb sub x12, x13, x14, lsr #5 + libdis_test+0xb4: 61 04 9f 4b sub w1, w3, wzr, asr #1 + libdis_test+0xb8: e1 17 01 eb subs x1, xzr, x1, lsl #5 + libdis_test+0xbc: 42 18 42 6b subs w2, w2, w2, lsr #6 + libdis_test+0xc0: e0 03 22 8b add x0, sp, w2, uxtb #0 + libdis_test+0xc4: 3e 24 3f ab adds x30, x1, wzr, uxth #1 + libdis_test+0xc8: 84 49 22 cb sub x4, x12, w2, uxtw #2 + libdis_test+0xcc: a3 6d 25 eb subs x3, x13, x5, uxtx #3 + libdis_test+0xd0: c5 91 22 0b add w5, w14, w2, sxtb #4 + libdis_test+0xd4: ea a3 22 2b adds w10, wsp, w2, sxth #0 + libdis_test+0xd8: ff c6 22 4b sub wsp, w23, w2, sxtw #1 + libdis_test+0xdc: c9 ea 2a 6b subs w9, w22, w10, sxtx #2 + libdis_test+0xe0: 9f 69 21 8b add sp, x12, x1, lsl #2 + libdis_test+0xe4: 3f 49 28 4b sub wsp, w9, w8, lsl #2 + libdis_test+0xe8: 29 01 0a 9a adc x9, x9, x10 + libdis_test+0xec: ec 03 13 1a adc w12, wzr, w19 + libdis_test+0xf0: 3f 00 00 ba adcs xzr, x1, x0 + libdis_test+0xf4: 83 00 1f 3a adcs w3, w4, wzr + libdis_test+0xf8: 41 00 03 da sbc x1, x2, x3 + libdis_test+0xfc: 83 00 05 5a sbc w3, w4, w5 + libdis_test+0x100: 49 01 0b fa sbcs x9, x10, x11 + libdis_test+0x104: b4 02 16 7a sbcs w20, w21, w22 diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.data-reg.s b/usr/src/test/util-tests/tests/dis/arm64/tst.data-reg.s new file mode 100644 index 0000000000..72a305bc5c --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.data-reg.s @@ -0,0 +1,111 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * Test Data - Immediate group dissassembly + */ + +.text +.align 16 +.globl libdis_test +.type libdis_test, @function +libdis_test: + + /* Data 1 Source */ + RBIT X9, X1 + RBIT WZR, W0 + REV16 X1, X30 + REV16 W3, WZR + REV32 X6, X5 + REV32 XZR, X12 + REV W23, W3 + REV X4, X4 + CLZ W9, W9 + CLZ X12, XZR + CLS W3, W25 + CLS X29, X28 + + /* Data 2 Source */ + UDIV X12, XZR, X4 + UDIV W2, W4, WZR + SDIV XZR, X1, X4 + SDIV W19, W0, W15 + LSLV X23, X24, X25 + LSLV W29, W30, W4 + LSRV X0, X3, X1 + LSRV W9, WZR, W29 + ASRV X3, X9, X10 + ASRV W3, W4, W8 + RORV X7, X2, X12 + RORV W7, W4, W3 + + /* Logic - Shifted Regs */ + AND X24, X25, X26, LSL #62 + AND W14, W15, W16, LSR #20 + BIC X4, X5, X6, ASR #32 + BIC W1, W19, W22, ROR #2 + ORR X12, X13, X14, LSL #5 + ORR W1, W3, WZR, LSR #1 + ORN X1, X1, X1, ASR #5 + ORN W2, W2, W2, ROR #6 + EOR X7, XZR, X9, LSL #50 + EOR WZR, W1, W3, LSR #12 + EON X0, X2, X3, ASR #14 + EON W0, W2, W3, ROR #20 + ANDS X18, X12, X14, LSL #42 + ANDS W0, W2, W24, LSR #3 + BICS X1, X9, X19, ASR #1 + BICS W9, W4, W1, ROR #30 + + /* Add/Sub Shifted Regs */ + ADD X24, X25, X26, LSL #62 + ADD W14, W15, W16, LSR #20 + ADDS X4, X5, X6, ASR #32 + ADDS W1, W19, W22, LSL #0 + SUB X12, X13, X14, LSR #5 + SUB W1, W3, WZR, ASR #1 + SUBS X1, XZR, X1, LSL #5 + SUBS W2, W2, W2, LSR #6 + + /* Add/Sub Extended Regs */ + ADD X0, SP, W2, UXTB #0 + ADDS X30, X1, WZR, UXTH #1 + SUB X4, X12, W2, UXTW #2 + SUBS X3, X13, X5, UXTX #3 + ADD W5, W14, W2, SXTB #4 + ADDS W10, WSP, W2, SXTH #0 + SUB WSP, W23, W2, SXTW #1 + SUBS W9, W22, W10, SXTX #2 + + ADD SP, X12, X1, LSL #2 + SUB WSP, W9, W8, LSL #2 + + + /* Add/Sub with Carry */ + ADC X9, X9, X10 + ADC W12, WZR, W19 + ADCS XZR, X1, X0 + ADCS W3, W4, WZR + SBC X1, X2, X3 + SBC W3, W4, W5 + SBCS X9, X10, X11 + SBCS W20, W21, W22 + + /* + * TODO: conditional compare (reg/immediate), + * conditional select, 3 source data + */ + +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.dproc1.out b/usr/src/test/util-tests/tests/dis/arm64/tst.dproc1.out new file mode 100755 index 0000000000..2a70b33b38 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.dproc1.out @@ -0,0 +1,22 @@ + libdis_test: 20 00 c0 5a rbit w0, w1 + libdis_test+0x4: fe 03 c0 5a rbit w30, wzr + libdis_test+0x8: 20 00 c0 da rbit x0, x1 + libdis_test+0xc: fe 03 c0 da rbit x30, xzr + libdis_test+0x10: 20 04 c0 5a rev16 w0, w1 + libdis_test+0x14: fe 07 c0 5a rev16 w30, wzr + libdis_test+0x18: 20 04 c0 da rev16 x0, x1 + libdis_test+0x1c: fe 07 c0 da rev16 x30, xzr + libdis_test+0x20: 20 08 c0 5a rev w0, w1 + libdis_test+0x24: fe 0b c0 5a rev w30, wzr + libdis_test+0x28: 20 0c c0 da rev x0, x1 + libdis_test+0x2c: fe 0f c0 da rev x30, xzr + libdis_test+0x30: 20 08 c0 da rev32 x0, x1 + libdis_test+0x34: fe 0b c0 da rev32 x30, xzr + libdis_test+0x38: 20 10 c0 5a clz w0, w1 + libdis_test+0x3c: fe 13 c0 5a clz w30, wzr + libdis_test+0x40: 20 10 c0 da clz x0, x1 + libdis_test+0x44: fe 13 c0 da clz x30, xzr + libdis_test+0x48: 20 14 c0 5a cls w0, w1 + libdis_test+0x4c: fe 17 c0 5a cls w30, wzr + libdis_test+0x50: 20 14 c0 da cls x0, x1 + libdis_test+0x54: fe 17 c0 da cls x30, xzr diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.dproc1.s b/usr/src/test/util-tests/tests/dis/arm64/tst.dproc1.s new file mode 100755 index 0000000000..abc20b917d --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.dproc1.s @@ -0,0 +1,56 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.5.7 Data-processing (1 source) + */ +.macro dproc op wreg=1 + /* Test 32-bit (except for rev32), 64-bit, and ZR */ +.if \wreg + \op w0, w1 + \op w30, wzr +.endif + \op x0, x1 + \op x30, xzr +.endm +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * C5.6.147 RBIT + */ + dproc rbit + /* + * C5.6.150 REV16 + */ + dproc rev16 + /* + * C5.6.149 REV + */ + dproc rev + /* + * C5.6.151 REV32 + */ + dproc rev32 0 + /* + * C5.6.40 CLZ + */ + dproc clz + /* + * C5.6.39 CLS + */ + dproc cls +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.dproc2.out b/usr/src/test/util-tests/tests/dis/arm64/tst.dproc2.out new file mode 100755 index 0000000000..34e39f44fd --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.dproc2.out @@ -0,0 +1,24 @@ + libdis_test: e0 09 de 1a udiv w0, w15, w30 + libdis_test+0x4: e0 09 de 9a udiv x0, x15, x30 + libdis_test+0x8: ff 0b df 1a udiv wzr, wzr, wzr + libdis_test+0xc: ff 0b df 9a udiv xzr, xzr, xzr + libdis_test+0x10: e0 0d de 1a sdiv w0, w15, w30 + libdis_test+0x14: e0 0d de 9a sdiv x0, x15, x30 + libdis_test+0x18: ff 0f df 1a sdiv wzr, wzr, wzr + libdis_test+0x1c: ff 0f df 9a sdiv xzr, xzr, xzr + libdis_test+0x20: e0 21 de 1a lsl w0, w15, w30 + libdis_test+0x24: e0 21 de 9a lsl x0, x15, x30 + libdis_test+0x28: ff 23 df 1a lsl wzr, wzr, wzr + libdis_test+0x2c: ff 23 df 9a lsl xzr, xzr, xzr + libdis_test+0x30: e0 25 de 1a lsr w0, w15, w30 + libdis_test+0x34: e0 25 de 9a lsr x0, x15, x30 + libdis_test+0x38: ff 27 df 1a lsr wzr, wzr, wzr + libdis_test+0x3c: ff 27 df 9a lsr xzr, xzr, xzr + libdis_test+0x40: e0 29 de 1a asr w0, w15, w30 + libdis_test+0x44: e0 29 de 9a asr x0, x15, x30 + libdis_test+0x48: ff 2b df 1a asr wzr, wzr, wzr + libdis_test+0x4c: ff 2b df 9a asr xzr, xzr, xzr + libdis_test+0x50: e0 2d de 1a ror w0, w15, w30 + libdis_test+0x54: e0 2d de 9a ror x0, x15, x30 + libdis_test+0x58: ff 2f df 1a ror wzr, wzr, wzr + libdis_test+0x5c: ff 2f df 9a ror xzr, xzr, xzr diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.dproc2.s b/usr/src/test/util-tests/tests/dis/arm64/tst.dproc2.s new file mode 100755 index 0000000000..29ac7d5ae8 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.dproc2.s @@ -0,0 +1,68 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.5.8 Data-processing (2 source) + */ +.macro dproc op + \op w0, w15, w30 + \op x0, x15, x30 + \op wzr, wzr, wzr + \op xzr, xzr, xzr +.endm +.macro dproc_crc op xreg=0 +.if \xreg + \op w0, w15, x30 + \op wzr, wzr, xzr +.else + \op w0, w15, w30 + \op wzr, wzr, wzr +.endif +.endm + +.text +.arch armv8-a+crc +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * C5.6.214 UDIV + */ + dproc udiv + /* + * C5.6.160 SDIV + */ + dproc sdiv + /* + * C5.6.115 LSLV + * C5.6.113 LSL (register) (alias) + */ + dproc lslv + /* + * C5.6.118 LSRV + * C5.6.116 LSR (register) (alias) + */ + dproc lsrv + /* + * C5.6.17 ASRV + * C5.6.15 ASR (register) (alias) + */ + dproc asrv + /* + * C5.6.154 RORV + * C5.6.153 ROR (register) (alias) + */ + dproc rorv +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.dproc3.out b/usr/src/test/util-tests/tests/dis/arm64/tst.dproc3.out new file mode 100755 index 0000000000..c440e75425 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.dproc3.out @@ -0,0 +1,20 @@ + libdis_test: 40 79 14 1b madd w0, w10, w20, w30 + libdis_test+0x4: 40 7d 14 1b madd w0, w10, w20, wzr + libdis_test+0x8: 40 79 14 9b madd x0, x10, x20, x30 + libdis_test+0xc: 40 7d 14 9b madd x0, x10, x20, xzr + libdis_test+0x10: 40 f9 14 1b msub w0, w10, w20, w30 + libdis_test+0x14: 40 fd 14 1b msub w0, w10, w20, wzr + libdis_test+0x18: 40 f9 14 9b msub x0, x10, x20, x30 + libdis_test+0x1c: 40 fd 14 9b msub x0, x10, x20, xzr + libdis_test+0x20: 00 78 3e 9b smaddl x0, w0, w30, x30 + libdis_test+0x24: 00 7c 3e 9b smaddl x0, w0, w30, xzr + libdis_test+0x28: 00 f8 3e 9b smsubl x0, w0, w30, x30 + libdis_test+0x2c: 00 fc 3e 9b smsubl x0, w0, w30, xzr + libdis_test+0x30: 00 78 be 9b umaddl x0, w0, w30, x30 + libdis_test+0x34: 00 7c be 9b umaddl x0, w0, w30, xzr + libdis_test+0x38: 00 f8 be 9b umsubl x0, w0, w30, x30 + libdis_test+0x3c: 00 fc be 9b umsubl x0, w0, w30, xzr + libdis_test+0x40: e0 7d 5e 9b smulh x0, x15, x30 + libdis_test+0x44: e0 7d 5f 9b smulh x0, x15, xzr + libdis_test+0x48: e0 7d de 9b umulh x0, x15, x30 + libdis_test+0x4c: e0 7d df 9b umulh x0, x15, xzr diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.dproc3.s b/usr/src/test/util-tests/tests/dis/arm64/tst.dproc3.s new file mode 100755 index 0000000000..7ec4d829d6 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.dproc3.s @@ -0,0 +1,52 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.5.9 Data-processing (3 source) + */ +.macro dproc_1 op + \op w0, w10, w20, w30 + \op w0, w10, w20, wzr + \op x0, x10, x20, x30 + \op x0, x10, x20, xzr +.endm + +.macro dproc_2 op + \op x0, w0, w30, x30 + \op x0, w0, w30, xzr +.endm + +.macro dproc_3 op + \op x0, x15, x30 + \op x0, x15, xzr +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * C5.6.119 MADD <Rd>, <Rn>, <Rm>, <Ra> + * C5.6.133 MUL <Rd>, <Rn>, <Rm> + */ + dproc_1 madd + dproc_1 msub + dproc_2 smaddl + dproc_2 smsubl + dproc_2 umaddl + dproc_2 umsubl + dproc_3 smulh + dproc_3 umulh +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.exception.out b/usr/src/test/util-tests/tests/dis/arm64/tst.exception.out new file mode 100755 index 0000000000..99617d86f6 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.exception.out @@ -0,0 +1,16 @@ + libdis_test: 01 00 00 d4 svc #0x0 + libdis_test+0x4: e1 ff 1f d4 svc #0xffff + libdis_test+0x8: 02 00 00 d4 hvc #0x0 + libdis_test+0xc: e2 ff 1f d4 hvc #0xffff + libdis_test+0x10: 03 00 00 d4 smc #0x0 + libdis_test+0x14: e3 ff 1f d4 smc #0xffff + libdis_test+0x18: 00 00 20 d4 brk #0x0 + libdis_test+0x1c: e0 ff 3f d4 brk #0xffff + libdis_test+0x20: 00 00 40 d4 hlt #0x0 + libdis_test+0x24: e0 ff 5f d4 hlt #0xffff + libdis_test+0x28: 01 00 a0 d4 dcps1 #0x0 + libdis_test+0x2c: e1 ff bf d4 dcps1 #0xffff + libdis_test+0x30: 02 00 a0 d4 dcps2 #0x0 + libdis_test+0x34: e2 ff bf d4 dcps2 #0xffff + libdis_test+0x38: 03 00 a0 d4 dcps3 #0x0 + libdis_test+0x3c: e3 ff bf d4 dcps3 #0xffff diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.exception.s b/usr/src/test/util-tests/tests/dis/arm64/tst.exception.s new file mode 100755 index 0000000000..4e3e215774 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.exception.s @@ -0,0 +1,40 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.2.3 Exception generation + */ +.macro exception op, immopt=0 + .if \immopt + \op + .else + \op #0 + .endif + \op #65535 +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + exception svc + exception hvc + exception smc + exception brk + exception hlt + exception dcps1 1 + exception dcps2 1 + exception dcps3 1 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.extract.out b/usr/src/test/util-tests/tests/dis/arm64/tst.extract.out new file mode 100755 index 0000000000..a21c025c9e --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.extract.out @@ -0,0 +1,8 @@ + libdis_test: e0 01 9f 13 extr w0, w15, wzr, #0x0 + libdis_test+0x4: e0 7d 9f 13 extr w0, w15, wzr, #0x1f + libdis_test+0x8: e0 01 df 93 extr x0, x15, xzr, #0x0 + libdis_test+0xc: e0 fd df 93 extr x0, x15, xzr, #0x3f + libdis_test+0x10: e0 03 9f 13 extr w0, wzr, wzr, #0x0 + libdis_test+0x14: e0 7f 9f 13 extr w0, wzr, wzr, #0x1f + libdis_test+0x18: e0 03 df 93 extr x0, xzr, xzr, #0x0 + libdis_test+0x1c: e0 7f df 93 extr x0, xzr, xzr, #0x1f diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.extract.s b/usr/src/test/util-tests/tests/dis/arm64/tst.extract.s new file mode 100755 index 0000000000..5444cac802 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.extract.s @@ -0,0 +1,36 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.4.3 Extract + */ +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * C5.6.67 EXTR + * C5.6.152 ROR (immediate) (alias) + */ + extr w0, w15, wzr, #0 + extr w0, w15, wzr, #31 + extr x0, x15, xzr, #0 + extr x0, x15, xzr, #63 + /* Test for ROR (Rn == Rm) */ + extr w0, wzr, wzr, #0 + extr w0, wzr, wzr, #31 + extr x0, xzr, xzr, #0 + extr x0, xzr, xzr, #31 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-exclusive.out b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-exclusive.out new file mode 100755 index 0000000000..5e826fcf19 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-exclusive.out @@ -0,0 +1,128 @@ + libdis_test: 00 7c 00 08 stxrb w0, w0, [x0] + libdis_test+0x4: 1e 7c 1e 08 stxrb w30, w30, [x0] + libdis_test+0x8: ff 7f 1f 08 stxrb wzr, wzr, [sp] + libdis_test+0xc: ff 7f 1f 08 stxrb wzr, wzr, [sp] + libdis_test+0x10: 00 fc 00 08 stlxrb w0, w0, [x0] + libdis_test+0x14: 1e fc 1e 08 stlxrb w30, w30, [x0] + libdis_test+0x18: ff ff 1f 08 stlxrb wzr, wzr, [sp] + libdis_test+0x1c: ff ff 1f 08 stlxrb wzr, wzr, [sp] + libdis_test+0x20: 00 7c 5f 08 ldxrb w0, [x0] + libdis_test+0x24: 1e 7c 5f 08 ldxrb w30, [x0] + libdis_test+0x28: ff 7f 5f 08 ldxrb wzr, [sp] + libdis_test+0x2c: ff 7f 5f 08 ldxrb wzr, [sp] + libdis_test+0x30: 00 fc 5f 08 ldaxrb w0, [x0] + libdis_test+0x34: 1e fc 5f 08 ldaxrb w30, [x0] + libdis_test+0x38: ff ff 5f 08 ldaxrb wzr, [sp] + libdis_test+0x3c: ff ff 5f 08 ldaxrb wzr, [sp] + libdis_test+0x40: 00 fc 9f 08 stlrb w0, [x0] + libdis_test+0x44: 1e fc 9f 08 stlrb w30, [x0] + libdis_test+0x48: ff ff 9f 08 stlrb wzr, [sp] + libdis_test+0x4c: ff ff 9f 08 stlrb wzr, [sp] + libdis_test+0x50: 00 fc df 08 ldarb w0, [x0] + libdis_test+0x54: 1e fc df 08 ldarb w30, [x0] + libdis_test+0x58: ff ff df 08 ldarb wzr, [sp] + libdis_test+0x5c: ff ff df 08 ldarb wzr, [sp] + libdis_test+0x60: 00 7c 00 48 stxrh w0, w0, [x0] + libdis_test+0x64: 1e 7c 1e 48 stxrh w30, w30, [x0] + libdis_test+0x68: ff 7f 1f 48 stxrh wzr, wzr, [sp] + libdis_test+0x6c: ff 7f 1f 48 stxrh wzr, wzr, [sp] + libdis_test+0x70: 00 fc 00 48 stlxrh w0, w0, [x0] + libdis_test+0x74: 1e fc 1e 48 stlxrh w30, w30, [x0] + libdis_test+0x78: ff ff 1f 48 stlxrh wzr, wzr, [sp] + libdis_test+0x7c: ff ff 1f 48 stlxrh wzr, wzr, [sp] + libdis_test+0x80: 00 7c 5f 48 ldxrh w0, [x0] + libdis_test+0x84: 1e 7c 5f 48 ldxrh w30, [x0] + libdis_test+0x88: ff 7f 5f 48 ldxrh wzr, [sp] + libdis_test+0x8c: ff 7f 5f 48 ldxrh wzr, [sp] + libdis_test+0x90: 00 fc 5f 48 ldaxrh w0, [x0] + libdis_test+0x94: 1e fc 5f 48 ldaxrh w30, [x0] + libdis_test+0x98: ff ff 5f 48 ldaxrh wzr, [sp] + libdis_test+0x9c: ff ff 5f 48 ldaxrh wzr, [sp] + libdis_test+0xa0: 00 fc 9f 48 stlrh w0, [x0] + libdis_test+0xa4: 1e fc 9f 48 stlrh w30, [x0] + libdis_test+0xa8: ff ff 9f 48 stlrh wzr, [sp] + libdis_test+0xac: ff ff 9f 48 stlrh wzr, [sp] + libdis_test+0xb0: 00 fc df 48 ldarh w0, [x0] + libdis_test+0xb4: 1e fc df 48 ldarh w30, [x0] + libdis_test+0xb8: ff ff df 48 ldarh wzr, [sp] + libdis_test+0xbc: ff ff df 48 ldarh wzr, [sp] + libdis_test+0xc0: 00 7c 00 88 stxr w0, w0, [x0] + libdis_test+0xc4: 1e 7c 1e 88 stxr w30, w30, [x0] + libdis_test+0xc8: ff 7f 1f 88 stxr wzr, wzr, [sp] + libdis_test+0xcc: ff 7f 1f 88 stxr wzr, wzr, [sp] + libdis_test+0xd0: 00 7c 00 c8 stxr w0, x0, [x0] + libdis_test+0xd4: 1e 7c 1e c8 stxr w30, x30, [x0] + libdis_test+0xd8: ff 7f 1f c8 stxr wzr, xzr, [sp] + libdis_test+0xdc: ff 7f 1f c8 stxr wzr, xzr, [sp] + libdis_test+0xe0: 00 fc 00 88 stlxr w0, w0, [x0] + libdis_test+0xe4: 1e fc 1e 88 stlxr w30, w30, [x0] + libdis_test+0xe8: ff ff 1f 88 stlxr wzr, wzr, [sp] + libdis_test+0xec: ff ff 1f 88 stlxr wzr, wzr, [sp] + libdis_test+0xf0: 00 fc 00 c8 stlxr w0, x0, [x0] + libdis_test+0xf4: 1e fc 1e c8 stlxr w30, x30, [x0] + libdis_test+0xf8: ff ff 1f c8 stlxr wzr, xzr, [sp] + libdis_test+0xfc: ff ff 1f c8 stlxr wzr, xzr, [sp] + libdis_test+0x100: 0f 78 20 88 stxp w0, w15, w30, [x0] + libdis_test+0x104: 0f 00 3e 88 stxp w30, w15, w0, [x0] + libdis_test+0x108: ff 7f 3f 88 stxp wzr, wzr, wzr, [sp] + libdis_test+0x10c: ff 7f 3f 88 stxp wzr, wzr, wzr, [sp] + libdis_test+0x110: 0f 78 20 c8 stxp w0, x15, x30, [x0] + libdis_test+0x114: 0f 00 3e c8 stxp w30, x15, x0, [x0] + libdis_test+0x118: ff 7f 3f c8 stxp wzr, xzr, xzr, [sp] + libdis_test+0x11c: ff 7f 3f c8 stxp wzr, xzr, xzr, [sp] + libdis_test+0x120: 0f f8 20 88 stlxp w0, w15, w30, [x0] + libdis_test+0x124: 0f 80 3e 88 stlxp w30, w15, w0, [x0] + libdis_test+0x128: ff ff 3f 88 stlxp wzr, wzr, wzr, [sp] + libdis_test+0x12c: ff ff 3f 88 stlxp wzr, wzr, wzr, [sp] + libdis_test+0x130: 0f f8 20 c8 stlxp w0, x15, x30, [x0] + libdis_test+0x134: 0f 80 3e c8 stlxp w30, x15, x0, [x0] + libdis_test+0x138: ff ff 3f c8 stlxp wzr, xzr, xzr, [sp] + libdis_test+0x13c: ff ff 3f c8 stlxp wzr, xzr, xzr, [sp] + libdis_test+0x140: 00 7c 5f 88 ldxr w0, [x0] + libdis_test+0x144: 1e 7c 5f 88 ldxr w30, [x0] + libdis_test+0x148: ff 7f 5f 88 ldxr wzr, [sp] + libdis_test+0x14c: ff 7f 5f 88 ldxr wzr, [sp] + libdis_test+0x150: 00 7c 5f c8 ldxr x0, [x0] + libdis_test+0x154: 1e 7c 5f c8 ldxr x30, [x0] + libdis_test+0x158: ff 7f 5f c8 ldxr xzr, [sp] + libdis_test+0x15c: ff 7f 5f c8 ldxr xzr, [sp] + libdis_test+0x160: 00 fc 5f 88 ldaxr w0, [x0] + libdis_test+0x164: 1e fc 5f 88 ldaxr w30, [x0] + libdis_test+0x168: ff ff 5f 88 ldaxr wzr, [sp] + libdis_test+0x16c: ff ff 5f 88 ldaxr wzr, [sp] + libdis_test+0x170: 00 fc 5f c8 ldaxr x0, [x0] + libdis_test+0x174: 1e fc 5f c8 ldaxr x30, [x0] + libdis_test+0x178: ff ff 5f c8 ldaxr xzr, [sp] + libdis_test+0x17c: ff ff 5f c8 ldaxr xzr, [sp] + libdis_test+0x180: 00 00 7f 88 ldxp w0, w0, [x0] + libdis_test+0x184: 1e 78 7f 88 ldxp w30, w30, [x0] + libdis_test+0x188: ff 7f 7f 88 ldxp wzr, wzr, [sp] + libdis_test+0x18c: ff 7f 7f 88 ldxp wzr, wzr, [sp] + libdis_test+0x190: 00 00 7f c8 ldxp x0, x0, [x0] + libdis_test+0x194: 1e 78 7f c8 ldxp x30, x30, [x0] + libdis_test+0x198: ff 7f 7f c8 ldxp xzr, xzr, [sp] + libdis_test+0x19c: ff 7f 7f c8 ldxp xzr, xzr, [sp] + libdis_test+0x1a0: 00 80 7f 88 ldaxp w0, w0, [x0] + libdis_test+0x1a4: 1e f8 7f 88 ldaxp w30, w30, [x0] + libdis_test+0x1a8: ff ff 7f 88 ldaxp wzr, wzr, [sp] + libdis_test+0x1ac: ff ff 7f 88 ldaxp wzr, wzr, [sp] + libdis_test+0x1b0: 00 80 7f c8 ldaxp x0, x0, [x0] + libdis_test+0x1b4: 1e f8 7f c8 ldaxp x30, x30, [x0] + libdis_test+0x1b8: ff ff 7f c8 ldaxp xzr, xzr, [sp] + libdis_test+0x1bc: ff ff 7f c8 ldaxp xzr, xzr, [sp] + libdis_test+0x1c0: 00 fc 9f 88 stlr w0, [x0] + libdis_test+0x1c4: 1e fc 9f 88 stlr w30, [x0] + libdis_test+0x1c8: ff ff 9f 88 stlr wzr, [sp] + libdis_test+0x1cc: ff ff 9f 88 stlr wzr, [sp] + libdis_test+0x1d0: 00 fc 9f c8 stlr x0, [x0] + libdis_test+0x1d4: 1e fc 9f c8 stlr x30, [x0] + libdis_test+0x1d8: ff ff 9f c8 stlr xzr, [sp] + libdis_test+0x1dc: ff ff 9f c8 stlr xzr, [sp] + libdis_test+0x1e0: 00 fc df 88 ldar w0, [x0] + libdis_test+0x1e4: 1e fc df 88 ldar w30, [x0] + libdis_test+0x1e8: ff ff df 88 ldar wzr, [sp] + libdis_test+0x1ec: ff ff df 88 ldar wzr, [sp] + libdis_test+0x1f0: 00 fc df c8 ldar x0, [x0] + libdis_test+0x1f4: 1e fc df c8 ldar x30, [x0] + libdis_test+0x1f8: ff ff df c8 ldar xzr, [sp] + libdis_test+0x1fc: ff ff df c8 ldar xzr, [sp] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-exclusive.s b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-exclusive.s new file mode 100755 index 0000000000..63257671cb --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-exclusive.s @@ -0,0 +1,100 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.3.6 Load/store exclusive + * + * Test the various combinations of register arguments: + * + * OP <32> <32> [.. + * OP <32> [.. + * OP <32> <32|64> [.. + * OP <32> <32|64> <32|64> [.. + * OP <32|64> [.. + * OP <32|64> <32|64> [.. + * + * #0 is optional and default. + */ + +.macro ldstexcl1 op test64=0 + \op w0, [x0] + \op w30, [x0, #0] + \op wzr, [sp] + \op wzr, [sp, #0] + .if \test64 + \op x0, [x0] + \op x30, [x0, #0] + \op xzr, [sp] + \op xzr, [sp, #0] + .endif +.endm + +.macro ldstexcl2 op test64_1=0 test64_2=0 + \op w0, w0, [x0] + \op w30, w30, [x0, #0] + \op wzr, wzr, [sp] + \op wzr, wzr, [sp, #0] + .if \test64_1 + \op w0, x0, [x0] + \op w30, x30, [x0, #0] + \op wzr, xzr, [sp] + \op wzr, xzr, [sp, #0] + .endif + .if \test64_2 + \op x0, x0, [x0] + \op x30, x30, [x0, #0] + \op xzr, xzr, [sp] + \op xzr, xzr, [sp, #0] + .endif +.endm + +.macro ldstexcl3 op + \op w0, w15, w30, [x0] + \op w30, w15, w0, [x0, #0] + \op wzr, wzr, wzr, [sp] + \op wzr, wzr, wzr, [sp, #0] + \op w0, x15, x30, [x0] + \op w30, x15, x0, [x0, #0] + \op wzr, xzr, xzr, [sp] + \op wzr, xzr, xzr, [sp, #0] +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + ldstexcl2 stxrb + ldstexcl2 stlxrb + ldstexcl1 ldxrb + ldstexcl1 ldaxrb + ldstexcl1 stlrb + ldstexcl1 ldarb + ldstexcl2 stxrh + ldstexcl2 stlxrh + ldstexcl1 ldxrh + ldstexcl1 ldaxrh + ldstexcl1 stlrh + ldstexcl1 ldarh + ldstexcl2 stxr 1 + ldstexcl2 stlxr 1 + ldstexcl3 stxp + ldstexcl3 stlxp + ldstexcl1 ldxr 1 + ldstexcl1 ldaxr 1 + ldstexcl2 ldxp 0 1 + ldstexcl2 ldaxp 0 1 + ldstexcl1 stlr 1 + ldstexcl1 ldar 1 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-literal.out b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-literal.out new file mode 100755 index 0000000000..03be9fe724 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-literal.out @@ -0,0 +1,3 @@ + libdis_test: 40 00 00 18 ldr w0, +0x8 <libdis_test+0x8> + libdis_test+0x4: ff ff ff 58 ldr xzr, -0x4 <libdis_test> + libdis_test+0x8: de ff ff 98 ldrsw x30, -0x8 <libdis_test> diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-literal.s b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-literal.s new file mode 100755 index 0000000000..9fe995fde4 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-literal.s @@ -0,0 +1,30 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.3.5 Load register (literal) + * + * C5.6.144 PRFM (literal) is handled by tst.ldst-prfm.s + */ +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: +1: + ldr w0, 2f + ldr xzr, 1b +2: + ldrsw x30, 1b +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-noalloc.out b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-noalloc.out new file mode 100755 index 0000000000..97eaffb904 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-noalloc.out @@ -0,0 +1,12 @@ + libdis_test: 00 00 00 28 stnp w0, w0, [x0] + libdis_test+0x4: de fb 1f 28 stnp w30, w30, [x30, #252] + libdis_test+0x8: ff 7f 20 28 stnp wzr, wzr, [sp, #-256] + libdis_test+0xc: 00 00 00 a8 stnp x0, x0, [x0] + libdis_test+0x10: de fb 1f a8 stnp x30, x30, [x30, #504] + libdis_test+0x14: ff 7f 20 a8 stnp xzr, xzr, [sp, #-512] + libdis_test+0x18: 00 00 40 28 ldnp w0, w0, [x0] + libdis_test+0x1c: de fb 5f 28 ldnp w30, w30, [x30, #252] + libdis_test+0x20: ff 7f 60 28 ldnp wzr, wzr, [sp, #-256] + libdis_test+0x24: 00 00 40 a8 ldnp x0, x0, [x0] + libdis_test+0x28: de fb 5f a8 ldnp x30, x30, [x30, #504] + libdis_test+0x2c: ff 7f 60 a8 ldnp xzr, xzr, [sp, #-512] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-noalloc.s b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-noalloc.s new file mode 100755 index 0000000000..005013701a --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-noalloc.s @@ -0,0 +1,47 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.3.7 Load/store no-allocate pair (offset) + * + * C5.6.176 STNP + * C5.6.80 LDNP + * C6.3.283 STNP (SIMD&FP) + * C6.3.164 LDNP (SIMD&FP) + * + * Test the minimum/maximum of registers and signed imm7. + */ +.macro ldstnoalloc1 op, reg, size, simd=0 + \op \reg\()0, \reg\()0, [x0] + \op \reg\()30, \reg\()30, [x30, #(\size*63)] + .if \simd + \op \reg\()31, \reg\()31, [sp, #(\size*-64)] + .else + \op \reg\()zr, \reg\()zr, [sp, #(\size*-64)] + .endif +.endm + +.macro ldstnoalloc op + ldstnoalloc1 \op, w, 4, + ldstnoalloc1 \op, x, 8, +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + ldstnoalloc stnp + ldstnoalloc ldnp +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-prfm.out b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-prfm.out new file mode 100755 index 0000000000..be031b4003 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-prfm.out @@ -0,0 +1,608 @@ + libdis_test: 00 00 00 d8 prfm pldl1keep, +0x0 <libdis_test> + libdis_test+0x4: 01 00 00 d8 prfm pldl1strm, +0x0 <libdis_test+0x4> + libdis_test+0x8: 02 00 00 d8 prfm pldl2keep, +0x0 <libdis_test+0x8> + libdis_test+0xc: 03 00 00 d8 prfm pldl2strm, +0x0 <libdis_test+0xc> + libdis_test+0x10: 04 00 00 d8 prfm pldl3keep, +0x0 <libdis_test+0x10> + libdis_test+0x14: 05 00 00 d8 prfm pldl3strm, +0x0 <libdis_test+0x14> + libdis_test+0x18: 06 00 00 d8 prfm #0x6, +0x0 <libdis_test+0x18> + libdis_test+0x1c: 07 00 00 d8 prfm #0x7, +0x0 <libdis_test+0x1c> + libdis_test+0x20: 08 00 00 d8 prfm plil1keep, +0x0 <libdis_test+0x20> + libdis_test+0x24: 09 00 00 d8 prfm plil1strm, +0x0 <libdis_test+0x24> + libdis_test+0x28: 0a 00 00 d8 prfm plil2keep, +0x0 <libdis_test+0x28> + libdis_test+0x2c: 0b 00 00 d8 prfm plil2strm, +0x0 <libdis_test+0x2c> + libdis_test+0x30: 0c 00 00 d8 prfm plil3keep, +0x0 <libdis_test+0x30> + libdis_test+0x34: 0d 00 00 d8 prfm plil3strm, +0x0 <libdis_test+0x34> + libdis_test+0x38: 0e 00 00 d8 prfm #0xe, +0x0 <libdis_test+0x38> + libdis_test+0x3c: 0f 00 00 d8 prfm #0xf, +0x0 <libdis_test+0x3c> + libdis_test+0x40: 10 02 00 d8 prfm pstl1keep, +0x40 <libdis_test+0x80> + libdis_test+0x44: f1 01 00 d8 prfm pstl1strm, +0x3c <libdis_test+0x80> + libdis_test+0x48: d2 01 00 d8 prfm pstl2keep, +0x38 <libdis_test+0x80> + libdis_test+0x4c: b3 01 00 d8 prfm pstl2strm, +0x34 <libdis_test+0x80> + libdis_test+0x50: 94 01 00 d8 prfm pstl3keep, +0x30 <libdis_test+0x80> + libdis_test+0x54: 75 01 00 d8 prfm pstl3strm, +0x2c <libdis_test+0x80> + libdis_test+0x58: 56 01 00 d8 prfm #0x16, +0x28 <libdis_test+0x80> + libdis_test+0x5c: 37 01 00 d8 prfm #0x17, +0x24 <libdis_test+0x80> + libdis_test+0x60: 18 01 00 d8 prfm #0x18, +0x20 <libdis_test+0x80> + libdis_test+0x64: f9 00 00 d8 prfm #0x19, +0x1c <libdis_test+0x80> + libdis_test+0x68: da 00 00 d8 prfm #0x1a, +0x18 <libdis_test+0x80> + libdis_test+0x6c: bb 00 00 d8 prfm #0x1b, +0x14 <libdis_test+0x80> + libdis_test+0x70: 9c 00 00 d8 prfm #0x1c, +0x10 <libdis_test+0x80> + libdis_test+0x74: 7d 00 00 d8 prfm #0x1d, +0xc <libdis_test+0x80> + libdis_test+0x78: 5e 00 00 d8 prfm #0x1e, +0x8 <libdis_test+0x80> + libdis_test+0x7c: 3f 00 00 d8 prfm #0x1f, +0x4 <libdis_test+0x80> + libdis_test+0x80: 00 68 a0 f8 prfm pldl1keep, [x0, x0] + libdis_test+0x84: 00 48 a0 f8 prfm pldl1keep, [x0, w0, uxtw] + libdis_test+0x88: e0 5b bf f8 prfm pldl1keep, [sp, wzr, uxtw #3] + libdis_test+0x8c: 00 68 a0 f8 prfm pldl1keep, [x0, x0] + libdis_test+0x90: e0 7b bf f8 prfm pldl1keep, [sp, xzr, lsl #3] + libdis_test+0x94: 00 c8 a0 f8 prfm pldl1keep, [x0, w0, sxtw] + libdis_test+0x98: e0 db bf f8 prfm pldl1keep, [sp, wzr, sxtw #3] + libdis_test+0x9c: 00 e8 a0 f8 prfm pldl1keep, [x0, x0, sxtx] + libdis_test+0xa0: e0 fb bf f8 prfm pldl1keep, [sp, xzr, sxtx #3] + libdis_test+0xa4: 01 68 a0 f8 prfm pldl1strm, [x0, x0] + libdis_test+0xa8: 01 48 a0 f8 prfm pldl1strm, [x0, w0, uxtw] + libdis_test+0xac: e1 5b bf f8 prfm pldl1strm, [sp, wzr, uxtw #3] + libdis_test+0xb0: 01 68 a0 f8 prfm pldl1strm, [x0, x0] + libdis_test+0xb4: e1 7b bf f8 prfm pldl1strm, [sp, xzr, lsl #3] + libdis_test+0xb8: 01 c8 a0 f8 prfm pldl1strm, [x0, w0, sxtw] + libdis_test+0xbc: e1 db bf f8 prfm pldl1strm, [sp, wzr, sxtw #3] + libdis_test+0xc0: 01 e8 a0 f8 prfm pldl1strm, [x0, x0, sxtx] + libdis_test+0xc4: e1 fb bf f8 prfm pldl1strm, [sp, xzr, sxtx #3] + libdis_test+0xc8: 02 68 a0 f8 prfm pldl2keep, [x0, x0] + libdis_test+0xcc: 02 48 a0 f8 prfm pldl2keep, [x0, w0, uxtw] + libdis_test+0xd0: e2 5b bf f8 prfm pldl2keep, [sp, wzr, uxtw #3] + libdis_test+0xd4: 02 68 a0 f8 prfm pldl2keep, [x0, x0] + libdis_test+0xd8: e2 7b bf f8 prfm pldl2keep, [sp, xzr, lsl #3] + libdis_test+0xdc: 02 c8 a0 f8 prfm pldl2keep, [x0, w0, sxtw] + libdis_test+0xe0: e2 db bf f8 prfm pldl2keep, [sp, wzr, sxtw #3] + libdis_test+0xe4: 02 e8 a0 f8 prfm pldl2keep, [x0, x0, sxtx] + libdis_test+0xe8: e2 fb bf f8 prfm pldl2keep, [sp, xzr, sxtx #3] + libdis_test+0xec: 03 68 a0 f8 prfm pldl2strm, [x0, x0] + libdis_test+0xf0: 03 48 a0 f8 prfm pldl2strm, [x0, w0, uxtw] + libdis_test+0xf4: e3 5b bf f8 prfm pldl2strm, [sp, wzr, uxtw #3] + libdis_test+0xf8: 03 68 a0 f8 prfm pldl2strm, [x0, x0] + libdis_test+0xfc: e3 7b bf f8 prfm pldl2strm, [sp, xzr, lsl #3] + libdis_test+0x100: 03 c8 a0 f8 prfm pldl2strm, [x0, w0, sxtw] + libdis_test+0x104: e3 db bf f8 prfm pldl2strm, [sp, wzr, sxtw #3] + libdis_test+0x108: 03 e8 a0 f8 prfm pldl2strm, [x0, x0, sxtx] + libdis_test+0x10c: e3 fb bf f8 prfm pldl2strm, [sp, xzr, sxtx #3] + libdis_test+0x110: 04 68 a0 f8 prfm pldl3keep, [x0, x0] + libdis_test+0x114: 04 48 a0 f8 prfm pldl3keep, [x0, w0, uxtw] + libdis_test+0x118: e4 5b bf f8 prfm pldl3keep, [sp, wzr, uxtw #3] + libdis_test+0x11c: 04 68 a0 f8 prfm pldl3keep, [x0, x0] + libdis_test+0x120: e4 7b bf f8 prfm pldl3keep, [sp, xzr, lsl #3] + libdis_test+0x124: 04 c8 a0 f8 prfm pldl3keep, [x0, w0, sxtw] + libdis_test+0x128: e4 db bf f8 prfm pldl3keep, [sp, wzr, sxtw #3] + libdis_test+0x12c: 04 e8 a0 f8 prfm pldl3keep, [x0, x0, sxtx] + libdis_test+0x130: e4 fb bf f8 prfm pldl3keep, [sp, xzr, sxtx #3] + libdis_test+0x134: 05 68 a0 f8 prfm pldl3strm, [x0, x0] + libdis_test+0x138: 05 48 a0 f8 prfm pldl3strm, [x0, w0, uxtw] + libdis_test+0x13c: e5 5b bf f8 prfm pldl3strm, [sp, wzr, uxtw #3] + libdis_test+0x140: 05 68 a0 f8 prfm pldl3strm, [x0, x0] + libdis_test+0x144: e5 7b bf f8 prfm pldl3strm, [sp, xzr, lsl #3] + libdis_test+0x148: 05 c8 a0 f8 prfm pldl3strm, [x0, w0, sxtw] + libdis_test+0x14c: e5 db bf f8 prfm pldl3strm, [sp, wzr, sxtw #3] + libdis_test+0x150: 05 e8 a0 f8 prfm pldl3strm, [x0, x0, sxtx] + libdis_test+0x154: e5 fb bf f8 prfm pldl3strm, [sp, xzr, sxtx #3] + libdis_test+0x158: 06 68 a0 f8 prfm #0x6, [x0, x0] + libdis_test+0x15c: 06 48 a0 f8 prfm #0x6, [x0, w0, uxtw] + libdis_test+0x160: e6 5b bf f8 prfm #0x6, [sp, wzr, uxtw #3] + libdis_test+0x164: 06 68 a0 f8 prfm #0x6, [x0, x0] + libdis_test+0x168: e6 7b bf f8 prfm #0x6, [sp, xzr, lsl #3] + libdis_test+0x16c: 06 c8 a0 f8 prfm #0x6, [x0, w0, sxtw] + libdis_test+0x170: e6 db bf f8 prfm #0x6, [sp, wzr, sxtw #3] + libdis_test+0x174: 06 e8 a0 f8 prfm #0x6, [x0, x0, sxtx] + libdis_test+0x178: e6 fb bf f8 prfm #0x6, [sp, xzr, sxtx #3] + libdis_test+0x17c: 07 68 a0 f8 prfm #0x7, [x0, x0] + libdis_test+0x180: 07 48 a0 f8 prfm #0x7, [x0, w0, uxtw] + libdis_test+0x184: e7 5b bf f8 prfm #0x7, [sp, wzr, uxtw #3] + libdis_test+0x188: 07 68 a0 f8 prfm #0x7, [x0, x0] + libdis_test+0x18c: e7 7b bf f8 prfm #0x7, [sp, xzr, lsl #3] + libdis_test+0x190: 07 c8 a0 f8 prfm #0x7, [x0, w0, sxtw] + libdis_test+0x194: e7 db bf f8 prfm #0x7, [sp, wzr, sxtw #3] + libdis_test+0x198: 07 e8 a0 f8 prfm #0x7, [x0, x0, sxtx] + libdis_test+0x19c: e7 fb bf f8 prfm #0x7, [sp, xzr, sxtx #3] + libdis_test+0x1a0: 08 68 a0 f8 prfm plil1keep, [x0, x0] + libdis_test+0x1a4: 08 48 a0 f8 prfm plil1keep, [x0, w0, uxtw] + libdis_test+0x1a8: e8 5b bf f8 prfm plil1keep, [sp, wzr, uxtw #3] + libdis_test+0x1ac: 08 68 a0 f8 prfm plil1keep, [x0, x0] + libdis_test+0x1b0: e8 7b bf f8 prfm plil1keep, [sp, xzr, lsl #3] + libdis_test+0x1b4: 08 c8 a0 f8 prfm plil1keep, [x0, w0, sxtw] + libdis_test+0x1b8: e8 db bf f8 prfm plil1keep, [sp, wzr, sxtw #3] + libdis_test+0x1bc: 08 e8 a0 f8 prfm plil1keep, [x0, x0, sxtx] + libdis_test+0x1c0: e8 fb bf f8 prfm plil1keep, [sp, xzr, sxtx #3] + libdis_test+0x1c4: 09 68 a0 f8 prfm plil1strm, [x0, x0] + libdis_test+0x1c8: 09 48 a0 f8 prfm plil1strm, [x0, w0, uxtw] + libdis_test+0x1cc: e9 5b bf f8 prfm plil1strm, [sp, wzr, uxtw #3] + libdis_test+0x1d0: 09 68 a0 f8 prfm plil1strm, [x0, x0] + libdis_test+0x1d4: e9 7b bf f8 prfm plil1strm, [sp, xzr, lsl #3] + libdis_test+0x1d8: 09 c8 a0 f8 prfm plil1strm, [x0, w0, sxtw] + libdis_test+0x1dc: e9 db bf f8 prfm plil1strm, [sp, wzr, sxtw #3] + libdis_test+0x1e0: 09 e8 a0 f8 prfm plil1strm, [x0, x0, sxtx] + libdis_test+0x1e4: e9 fb bf f8 prfm plil1strm, [sp, xzr, sxtx #3] + libdis_test+0x1e8: 0a 68 a0 f8 prfm plil2keep, [x0, x0] + libdis_test+0x1ec: 0a 48 a0 f8 prfm plil2keep, [x0, w0, uxtw] + libdis_test+0x1f0: ea 5b bf f8 prfm plil2keep, [sp, wzr, uxtw #3] + libdis_test+0x1f4: 0a 68 a0 f8 prfm plil2keep, [x0, x0] + libdis_test+0x1f8: ea 7b bf f8 prfm plil2keep, [sp, xzr, lsl #3] + libdis_test+0x1fc: 0a c8 a0 f8 prfm plil2keep, [x0, w0, sxtw] + libdis_test+0x200: ea db bf f8 prfm plil2keep, [sp, wzr, sxtw #3] + libdis_test+0x204: 0a e8 a0 f8 prfm plil2keep, [x0, x0, sxtx] + libdis_test+0x208: ea fb bf f8 prfm plil2keep, [sp, xzr, sxtx #3] + libdis_test+0x20c: 0b 68 a0 f8 prfm plil2strm, [x0, x0] + libdis_test+0x210: 0b 48 a0 f8 prfm plil2strm, [x0, w0, uxtw] + libdis_test+0x214: eb 5b bf f8 prfm plil2strm, [sp, wzr, uxtw #3] + libdis_test+0x218: 0b 68 a0 f8 prfm plil2strm, [x0, x0] + libdis_test+0x21c: eb 7b bf f8 prfm plil2strm, [sp, xzr, lsl #3] + libdis_test+0x220: 0b c8 a0 f8 prfm plil2strm, [x0, w0, sxtw] + libdis_test+0x224: eb db bf f8 prfm plil2strm, [sp, wzr, sxtw #3] + libdis_test+0x228: 0b e8 a0 f8 prfm plil2strm, [x0, x0, sxtx] + libdis_test+0x22c: eb fb bf f8 prfm plil2strm, [sp, xzr, sxtx #3] + libdis_test+0x230: 0c 68 a0 f8 prfm plil3keep, [x0, x0] + libdis_test+0x234: 0c 48 a0 f8 prfm plil3keep, [x0, w0, uxtw] + libdis_test+0x238: ec 5b bf f8 prfm plil3keep, [sp, wzr, uxtw #3] + libdis_test+0x23c: 0c 68 a0 f8 prfm plil3keep, [x0, x0] + libdis_test+0x240: ec 7b bf f8 prfm plil3keep, [sp, xzr, lsl #3] + libdis_test+0x244: 0c c8 a0 f8 prfm plil3keep, [x0, w0, sxtw] + libdis_test+0x248: ec db bf f8 prfm plil3keep, [sp, wzr, sxtw #3] + libdis_test+0x24c: 0c e8 a0 f8 prfm plil3keep, [x0, x0, sxtx] + libdis_test+0x250: ec fb bf f8 prfm plil3keep, [sp, xzr, sxtx #3] + libdis_test+0x254: 0d 68 a0 f8 prfm plil3strm, [x0, x0] + libdis_test+0x258: 0d 48 a0 f8 prfm plil3strm, [x0, w0, uxtw] + libdis_test+0x25c: ed 5b bf f8 prfm plil3strm, [sp, wzr, uxtw #3] + libdis_test+0x260: 0d 68 a0 f8 prfm plil3strm, [x0, x0] + libdis_test+0x264: ed 7b bf f8 prfm plil3strm, [sp, xzr, lsl #3] + libdis_test+0x268: 0d c8 a0 f8 prfm plil3strm, [x0, w0, sxtw] + libdis_test+0x26c: ed db bf f8 prfm plil3strm, [sp, wzr, sxtw #3] + libdis_test+0x270: 0d e8 a0 f8 prfm plil3strm, [x0, x0, sxtx] + libdis_test+0x274: ed fb bf f8 prfm plil3strm, [sp, xzr, sxtx #3] + libdis_test+0x278: 0e 68 a0 f8 prfm #0xe, [x0, x0] + libdis_test+0x27c: 0e 48 a0 f8 prfm #0xe, [x0, w0, uxtw] + libdis_test+0x280: ee 5b bf f8 prfm #0xe, [sp, wzr, uxtw #3] + libdis_test+0x284: 0e 68 a0 f8 prfm #0xe, [x0, x0] + libdis_test+0x288: ee 7b bf f8 prfm #0xe, [sp, xzr, lsl #3] + libdis_test+0x28c: 0e c8 a0 f8 prfm #0xe, [x0, w0, sxtw] + libdis_test+0x290: ee db bf f8 prfm #0xe, [sp, wzr, sxtw #3] + libdis_test+0x294: 0e e8 a0 f8 prfm #0xe, [x0, x0, sxtx] + libdis_test+0x298: ee fb bf f8 prfm #0xe, [sp, xzr, sxtx #3] + libdis_test+0x29c: 0f 68 a0 f8 prfm #0xf, [x0, x0] + libdis_test+0x2a0: 0f 48 a0 f8 prfm #0xf, [x0, w0, uxtw] + libdis_test+0x2a4: ef 5b bf f8 prfm #0xf, [sp, wzr, uxtw #3] + libdis_test+0x2a8: 0f 68 a0 f8 prfm #0xf, [x0, x0] + libdis_test+0x2ac: ef 7b bf f8 prfm #0xf, [sp, xzr, lsl #3] + libdis_test+0x2b0: 0f c8 a0 f8 prfm #0xf, [x0, w0, sxtw] + libdis_test+0x2b4: ef db bf f8 prfm #0xf, [sp, wzr, sxtw #3] + libdis_test+0x2b8: 0f e8 a0 f8 prfm #0xf, [x0, x0, sxtx] + libdis_test+0x2bc: ef fb bf f8 prfm #0xf, [sp, xzr, sxtx #3] + libdis_test+0x2c0: 10 68 a0 f8 prfm pstl1keep, [x0, x0] + libdis_test+0x2c4: 10 48 a0 f8 prfm pstl1keep, [x0, w0, uxtw] + libdis_test+0x2c8: f0 5b bf f8 prfm pstl1keep, [sp, wzr, uxtw #3] + libdis_test+0x2cc: 10 68 a0 f8 prfm pstl1keep, [x0, x0] + libdis_test+0x2d0: f0 7b bf f8 prfm pstl1keep, [sp, xzr, lsl #3] + libdis_test+0x2d4: 10 c8 a0 f8 prfm pstl1keep, [x0, w0, sxtw] + libdis_test+0x2d8: f0 db bf f8 prfm pstl1keep, [sp, wzr, sxtw #3] + libdis_test+0x2dc: 10 e8 a0 f8 prfm pstl1keep, [x0, x0, sxtx] + libdis_test+0x2e0: f0 fb bf f8 prfm pstl1keep, [sp, xzr, sxtx #3] + libdis_test+0x2e4: 11 68 a0 f8 prfm pstl1strm, [x0, x0] + libdis_test+0x2e8: 11 48 a0 f8 prfm pstl1strm, [x0, w0, uxtw] + libdis_test+0x2ec: f1 5b bf f8 prfm pstl1strm, [sp, wzr, uxtw #3] + libdis_test+0x2f0: 11 68 a0 f8 prfm pstl1strm, [x0, x0] + libdis_test+0x2f4: f1 7b bf f8 prfm pstl1strm, [sp, xzr, lsl #3] + libdis_test+0x2f8: 11 c8 a0 f8 prfm pstl1strm, [x0, w0, sxtw] + libdis_test+0x2fc: f1 db bf f8 prfm pstl1strm, [sp, wzr, sxtw #3] + libdis_test+0x300: 11 e8 a0 f8 prfm pstl1strm, [x0, x0, sxtx] + libdis_test+0x304: f1 fb bf f8 prfm pstl1strm, [sp, xzr, sxtx #3] + libdis_test+0x308: 12 68 a0 f8 prfm pstl2keep, [x0, x0] + libdis_test+0x30c: 12 48 a0 f8 prfm pstl2keep, [x0, w0, uxtw] + libdis_test+0x310: f2 5b bf f8 prfm pstl2keep, [sp, wzr, uxtw #3] + libdis_test+0x314: 12 68 a0 f8 prfm pstl2keep, [x0, x0] + libdis_test+0x318: f2 7b bf f8 prfm pstl2keep, [sp, xzr, lsl #3] + libdis_test+0x31c: 12 c8 a0 f8 prfm pstl2keep, [x0, w0, sxtw] + libdis_test+0x320: f2 db bf f8 prfm pstl2keep, [sp, wzr, sxtw #3] + libdis_test+0x324: 12 e8 a0 f8 prfm pstl2keep, [x0, x0, sxtx] + libdis_test+0x328: f2 fb bf f8 prfm pstl2keep, [sp, xzr, sxtx #3] + libdis_test+0x32c: 13 68 a0 f8 prfm pstl2strm, [x0, x0] + libdis_test+0x330: 13 48 a0 f8 prfm pstl2strm, [x0, w0, uxtw] + libdis_test+0x334: f3 5b bf f8 prfm pstl2strm, [sp, wzr, uxtw #3] + libdis_test+0x338: 13 68 a0 f8 prfm pstl2strm, [x0, x0] + libdis_test+0x33c: f3 7b bf f8 prfm pstl2strm, [sp, xzr, lsl #3] + libdis_test+0x340: 13 c8 a0 f8 prfm pstl2strm, [x0, w0, sxtw] + libdis_test+0x344: f3 db bf f8 prfm pstl2strm, [sp, wzr, sxtw #3] + libdis_test+0x348: 13 e8 a0 f8 prfm pstl2strm, [x0, x0, sxtx] + libdis_test+0x34c: f3 fb bf f8 prfm pstl2strm, [sp, xzr, sxtx #3] + libdis_test+0x350: 14 68 a0 f8 prfm pstl3keep, [x0, x0] + libdis_test+0x354: 14 48 a0 f8 prfm pstl3keep, [x0, w0, uxtw] + libdis_test+0x358: f4 5b bf f8 prfm pstl3keep, [sp, wzr, uxtw #3] + libdis_test+0x35c: 14 68 a0 f8 prfm pstl3keep, [x0, x0] + libdis_test+0x360: f4 7b bf f8 prfm pstl3keep, [sp, xzr, lsl #3] + libdis_test+0x364: 14 c8 a0 f8 prfm pstl3keep, [x0, w0, sxtw] + libdis_test+0x368: f4 db bf f8 prfm pstl3keep, [sp, wzr, sxtw #3] + libdis_test+0x36c: 14 e8 a0 f8 prfm pstl3keep, [x0, x0, sxtx] + libdis_test+0x370: f4 fb bf f8 prfm pstl3keep, [sp, xzr, sxtx #3] + libdis_test+0x374: 15 68 a0 f8 prfm pstl3strm, [x0, x0] + libdis_test+0x378: 15 48 a0 f8 prfm pstl3strm, [x0, w0, uxtw] + libdis_test+0x37c: f5 5b bf f8 prfm pstl3strm, [sp, wzr, uxtw #3] + libdis_test+0x380: 15 68 a0 f8 prfm pstl3strm, [x0, x0] + libdis_test+0x384: f5 7b bf f8 prfm pstl3strm, [sp, xzr, lsl #3] + libdis_test+0x388: 15 c8 a0 f8 prfm pstl3strm, [x0, w0, sxtw] + libdis_test+0x38c: f5 db bf f8 prfm pstl3strm, [sp, wzr, sxtw #3] + libdis_test+0x390: 15 e8 a0 f8 prfm pstl3strm, [x0, x0, sxtx] + libdis_test+0x394: f5 fb bf f8 prfm pstl3strm, [sp, xzr, sxtx #3] + libdis_test+0x398: 16 68 a0 f8 prfm #0x16, [x0, x0] + libdis_test+0x39c: 16 48 a0 f8 prfm #0x16, [x0, w0, uxtw] + libdis_test+0x3a0: f6 5b bf f8 prfm #0x16, [sp, wzr, uxtw #3] + libdis_test+0x3a4: 16 68 a0 f8 prfm #0x16, [x0, x0] + libdis_test+0x3a8: f6 7b bf f8 prfm #0x16, [sp, xzr, lsl #3] + libdis_test+0x3ac: 16 c8 a0 f8 prfm #0x16, [x0, w0, sxtw] + libdis_test+0x3b0: f6 db bf f8 prfm #0x16, [sp, wzr, sxtw #3] + libdis_test+0x3b4: 16 e8 a0 f8 prfm #0x16, [x0, x0, sxtx] + libdis_test+0x3b8: f6 fb bf f8 prfm #0x16, [sp, xzr, sxtx #3] + libdis_test+0x3bc: 17 68 a0 f8 prfm #0x17, [x0, x0] + libdis_test+0x3c0: 17 48 a0 f8 prfm #0x17, [x0, w0, uxtw] + libdis_test+0x3c4: f7 5b bf f8 prfm #0x17, [sp, wzr, uxtw #3] + libdis_test+0x3c8: 17 68 a0 f8 prfm #0x17, [x0, x0] + libdis_test+0x3cc: f7 7b bf f8 prfm #0x17, [sp, xzr, lsl #3] + libdis_test+0x3d0: 17 c8 a0 f8 prfm #0x17, [x0, w0, sxtw] + libdis_test+0x3d4: f7 db bf f8 prfm #0x17, [sp, wzr, sxtw #3] + libdis_test+0x3d8: 17 e8 a0 f8 prfm #0x17, [x0, x0, sxtx] + libdis_test+0x3dc: f7 fb bf f8 prfm #0x17, [sp, xzr, sxtx #3] + libdis_test+0x3e0: 18 68 a0 f8 prfm #0x18, [x0, x0] + libdis_test+0x3e4: 18 48 a0 f8 prfm #0x18, [x0, w0, uxtw] + libdis_test+0x3e8: f8 5b bf f8 prfm #0x18, [sp, wzr, uxtw #3] + libdis_test+0x3ec: 18 68 a0 f8 prfm #0x18, [x0, x0] + libdis_test+0x3f0: f8 7b bf f8 prfm #0x18, [sp, xzr, lsl #3] + libdis_test+0x3f4: 18 c8 a0 f8 prfm #0x18, [x0, w0, sxtw] + libdis_test+0x3f8: f8 db bf f8 prfm #0x18, [sp, wzr, sxtw #3] + libdis_test+0x3fc: 18 e8 a0 f8 prfm #0x18, [x0, x0, sxtx] + libdis_test+0x400: f8 fb bf f8 prfm #0x18, [sp, xzr, sxtx #3] + libdis_test+0x404: 19 68 a0 f8 prfm #0x19, [x0, x0] + libdis_test+0x408: 19 48 a0 f8 prfm #0x19, [x0, w0, uxtw] + libdis_test+0x40c: f9 5b bf f8 prfm #0x19, [sp, wzr, uxtw #3] + libdis_test+0x410: 19 68 a0 f8 prfm #0x19, [x0, x0] + libdis_test+0x414: f9 7b bf f8 prfm #0x19, [sp, xzr, lsl #3] + libdis_test+0x418: 19 c8 a0 f8 prfm #0x19, [x0, w0, sxtw] + libdis_test+0x41c: f9 db bf f8 prfm #0x19, [sp, wzr, sxtw #3] + libdis_test+0x420: 19 e8 a0 f8 prfm #0x19, [x0, x0, sxtx] + libdis_test+0x424: f9 fb bf f8 prfm #0x19, [sp, xzr, sxtx #3] + libdis_test+0x428: 1a 68 a0 f8 prfm #0x1a, [x0, x0] + libdis_test+0x42c: 1a 48 a0 f8 prfm #0x1a, [x0, w0, uxtw] + libdis_test+0x430: fa 5b bf f8 prfm #0x1a, [sp, wzr, uxtw #3] + libdis_test+0x434: 1a 68 a0 f8 prfm #0x1a, [x0, x0] + libdis_test+0x438: fa 7b bf f8 prfm #0x1a, [sp, xzr, lsl #3] + libdis_test+0x43c: 1a c8 a0 f8 prfm #0x1a, [x0, w0, sxtw] + libdis_test+0x440: fa db bf f8 prfm #0x1a, [sp, wzr, sxtw #3] + libdis_test+0x444: 1a e8 a0 f8 prfm #0x1a, [x0, x0, sxtx] + libdis_test+0x448: fa fb bf f8 prfm #0x1a, [sp, xzr, sxtx #3] + libdis_test+0x44c: 1b 68 a0 f8 prfm #0x1b, [x0, x0] + libdis_test+0x450: 1b 48 a0 f8 prfm #0x1b, [x0, w0, uxtw] + libdis_test+0x454: fb 5b bf f8 prfm #0x1b, [sp, wzr, uxtw #3] + libdis_test+0x458: 1b 68 a0 f8 prfm #0x1b, [x0, x0] + libdis_test+0x45c: fb 7b bf f8 prfm #0x1b, [sp, xzr, lsl #3] + libdis_test+0x460: 1b c8 a0 f8 prfm #0x1b, [x0, w0, sxtw] + libdis_test+0x464: fb db bf f8 prfm #0x1b, [sp, wzr, sxtw #3] + libdis_test+0x468: 1b e8 a0 f8 prfm #0x1b, [x0, x0, sxtx] + libdis_test+0x46c: fb fb bf f8 prfm #0x1b, [sp, xzr, sxtx #3] + libdis_test+0x470: 1c 68 a0 f8 prfm #0x1c, [x0, x0] + libdis_test+0x474: 1c 48 a0 f8 prfm #0x1c, [x0, w0, uxtw] + libdis_test+0x478: fc 5b bf f8 prfm #0x1c, [sp, wzr, uxtw #3] + libdis_test+0x47c: 1c 68 a0 f8 prfm #0x1c, [x0, x0] + libdis_test+0x480: fc 7b bf f8 prfm #0x1c, [sp, xzr, lsl #3] + libdis_test+0x484: 1c c8 a0 f8 prfm #0x1c, [x0, w0, sxtw] + libdis_test+0x488: fc db bf f8 prfm #0x1c, [sp, wzr, sxtw #3] + libdis_test+0x48c: 1c e8 a0 f8 prfm #0x1c, [x0, x0, sxtx] + libdis_test+0x490: fc fb bf f8 prfm #0x1c, [sp, xzr, sxtx #3] + libdis_test+0x494: 1d 68 a0 f8 prfm #0x1d, [x0, x0] + libdis_test+0x498: 1d 48 a0 f8 prfm #0x1d, [x0, w0, uxtw] + libdis_test+0x49c: fd 5b bf f8 prfm #0x1d, [sp, wzr, uxtw #3] + libdis_test+0x4a0: 1d 68 a0 f8 prfm #0x1d, [x0, x0] + libdis_test+0x4a4: fd 7b bf f8 prfm #0x1d, [sp, xzr, lsl #3] + libdis_test+0x4a8: 1d c8 a0 f8 prfm #0x1d, [x0, w0, sxtw] + libdis_test+0x4ac: fd db bf f8 prfm #0x1d, [sp, wzr, sxtw #3] + libdis_test+0x4b0: 1d e8 a0 f8 prfm #0x1d, [x0, x0, sxtx] + libdis_test+0x4b4: fd fb bf f8 prfm #0x1d, [sp, xzr, sxtx #3] + libdis_test+0x4b8: 1e 68 a0 f8 prfm #0x1e, [x0, x0] + libdis_test+0x4bc: 1e 48 a0 f8 prfm #0x1e, [x0, w0, uxtw] + libdis_test+0x4c0: fe 5b bf f8 prfm #0x1e, [sp, wzr, uxtw #3] + libdis_test+0x4c4: 1e 68 a0 f8 prfm #0x1e, [x0, x0] + libdis_test+0x4c8: fe 7b bf f8 prfm #0x1e, [sp, xzr, lsl #3] + libdis_test+0x4cc: 1e c8 a0 f8 prfm #0x1e, [x0, w0, sxtw] + libdis_test+0x4d0: fe db bf f8 prfm #0x1e, [sp, wzr, sxtw #3] + libdis_test+0x4d4: 1e e8 a0 f8 prfm #0x1e, [x0, x0, sxtx] + libdis_test+0x4d8: fe fb bf f8 prfm #0x1e, [sp, xzr, sxtx #3] + libdis_test+0x4dc: 1f 68 a0 f8 prfm #0x1f, [x0, x0] + libdis_test+0x4e0: 1f 48 a0 f8 prfm #0x1f, [x0, w0, uxtw] + libdis_test+0x4e4: ff 5b bf f8 prfm #0x1f, [sp, wzr, uxtw #3] + libdis_test+0x4e8: 1f 68 a0 f8 prfm #0x1f, [x0, x0] + libdis_test+0x4ec: ff 7b bf f8 prfm #0x1f, [sp, xzr, lsl #3] + libdis_test+0x4f0: 1f c8 a0 f8 prfm #0x1f, [x0, w0, sxtw] + libdis_test+0x4f4: ff db bf f8 prfm #0x1f, [sp, wzr, sxtw #3] + libdis_test+0x4f8: 1f e8 a0 f8 prfm #0x1f, [x0, x0, sxtx] + libdis_test+0x4fc: ff fb bf f8 prfm #0x1f, [sp, xzr, sxtx #3] + libdis_test+0x500: 00 00 80 f8 prfum pldl1keep, [x0] + libdis_test+0x504: e0 03 90 f8 prfum pldl1keep, [sp, #-256] + libdis_test+0x508: c0 f3 8f f8 prfum pldl1keep, [x30, #255] + libdis_test+0x50c: 20 10 80 f8 prfum pldl1keep, [x1, #1] + libdis_test+0x510: 20 f0 9f f8 prfum pldl1keep, [x1, #-1] + libdis_test+0x514: 01 00 80 f8 prfum pldl1strm, [x0] + libdis_test+0x518: e1 03 90 f8 prfum pldl1strm, [sp, #-256] + libdis_test+0x51c: c1 f3 8f f8 prfum pldl1strm, [x30, #255] + libdis_test+0x520: 21 10 80 f8 prfum pldl1strm, [x1, #1] + libdis_test+0x524: 21 f0 9f f8 prfum pldl1strm, [x1, #-1] + libdis_test+0x528: 02 00 80 f8 prfum pldl2keep, [x0] + libdis_test+0x52c: e2 03 90 f8 prfum pldl2keep, [sp, #-256] + libdis_test+0x530: c2 f3 8f f8 prfum pldl2keep, [x30, #255] + libdis_test+0x534: 22 10 80 f8 prfum pldl2keep, [x1, #1] + libdis_test+0x538: 22 f0 9f f8 prfum pldl2keep, [x1, #-1] + libdis_test+0x53c: 03 00 80 f8 prfum pldl2strm, [x0] + libdis_test+0x540: e3 03 90 f8 prfum pldl2strm, [sp, #-256] + libdis_test+0x544: c3 f3 8f f8 prfum pldl2strm, [x30, #255] + libdis_test+0x548: 23 10 80 f8 prfum pldl2strm, [x1, #1] + libdis_test+0x54c: 23 f0 9f f8 prfum pldl2strm, [x1, #-1] + libdis_test+0x550: 04 00 80 f8 prfum pldl3keep, [x0] + libdis_test+0x554: e4 03 90 f8 prfum pldl3keep, [sp, #-256] + libdis_test+0x558: c4 f3 8f f8 prfum pldl3keep, [x30, #255] + libdis_test+0x55c: 24 10 80 f8 prfum pldl3keep, [x1, #1] + libdis_test+0x560: 24 f0 9f f8 prfum pldl3keep, [x1, #-1] + libdis_test+0x564: 05 00 80 f8 prfum pldl3strm, [x0] + libdis_test+0x568: e5 03 90 f8 prfum pldl3strm, [sp, #-256] + libdis_test+0x56c: c5 f3 8f f8 prfum pldl3strm, [x30, #255] + libdis_test+0x570: 25 10 80 f8 prfum pldl3strm, [x1, #1] + libdis_test+0x574: 25 f0 9f f8 prfum pldl3strm, [x1, #-1] + libdis_test+0x578: 06 00 80 f8 prfum #0x6, [x0] + libdis_test+0x57c: e6 03 90 f8 prfum #0x6, [sp, #-256] + libdis_test+0x580: c6 f3 8f f8 prfum #0x6, [x30, #255] + libdis_test+0x584: 26 10 80 f8 prfum #0x6, [x1, #1] + libdis_test+0x588: 26 f0 9f f8 prfum #0x6, [x1, #-1] + libdis_test+0x58c: 07 00 80 f8 prfum #0x7, [x0] + libdis_test+0x590: e7 03 90 f8 prfum #0x7, [sp, #-256] + libdis_test+0x594: c7 f3 8f f8 prfum #0x7, [x30, #255] + libdis_test+0x598: 27 10 80 f8 prfum #0x7, [x1, #1] + libdis_test+0x59c: 27 f0 9f f8 prfum #0x7, [x1, #-1] + libdis_test+0x5a0: 08 00 80 f8 prfum plil1keep, [x0] + libdis_test+0x5a4: e8 03 90 f8 prfum plil1keep, [sp, #-256] + libdis_test+0x5a8: c8 f3 8f f8 prfum plil1keep, [x30, #255] + libdis_test+0x5ac: 28 10 80 f8 prfum plil1keep, [x1, #1] + libdis_test+0x5b0: 28 f0 9f f8 prfum plil1keep, [x1, #-1] + libdis_test+0x5b4: 09 00 80 f8 prfum plil1strm, [x0] + libdis_test+0x5b8: e9 03 90 f8 prfum plil1strm, [sp, #-256] + libdis_test+0x5bc: c9 f3 8f f8 prfum plil1strm, [x30, #255] + libdis_test+0x5c0: 29 10 80 f8 prfum plil1strm, [x1, #1] + libdis_test+0x5c4: 29 f0 9f f8 prfum plil1strm, [x1, #-1] + libdis_test+0x5c8: 0a 00 80 f8 prfum plil2keep, [x0] + libdis_test+0x5cc: ea 03 90 f8 prfum plil2keep, [sp, #-256] + libdis_test+0x5d0: ca f3 8f f8 prfum plil2keep, [x30, #255] + libdis_test+0x5d4: 2a 10 80 f8 prfum plil2keep, [x1, #1] + libdis_test+0x5d8: 2a f0 9f f8 prfum plil2keep, [x1, #-1] + libdis_test+0x5dc: 0b 00 80 f8 prfum plil2strm, [x0] + libdis_test+0x5e0: eb 03 90 f8 prfum plil2strm, [sp, #-256] + libdis_test+0x5e4: cb f3 8f f8 prfum plil2strm, [x30, #255] + libdis_test+0x5e8: 2b 10 80 f8 prfum plil2strm, [x1, #1] + libdis_test+0x5ec: 2b f0 9f f8 prfum plil2strm, [x1, #-1] + libdis_test+0x5f0: 0c 00 80 f8 prfum plil3keep, [x0] + libdis_test+0x5f4: ec 03 90 f8 prfum plil3keep, [sp, #-256] + libdis_test+0x5f8: cc f3 8f f8 prfum plil3keep, [x30, #255] + libdis_test+0x5fc: 2c 10 80 f8 prfum plil3keep, [x1, #1] + libdis_test+0x600: 2c f0 9f f8 prfum plil3keep, [x1, #-1] + libdis_test+0x604: 0d 00 80 f8 prfum plil3strm, [x0] + libdis_test+0x608: ed 03 90 f8 prfum plil3strm, [sp, #-256] + libdis_test+0x60c: cd f3 8f f8 prfum plil3strm, [x30, #255] + libdis_test+0x610: 2d 10 80 f8 prfum plil3strm, [x1, #1] + libdis_test+0x614: 2d f0 9f f8 prfum plil3strm, [x1, #-1] + libdis_test+0x618: 0e 00 80 f8 prfum #0xe, [x0] + libdis_test+0x61c: ee 03 90 f8 prfum #0xe, [sp, #-256] + libdis_test+0x620: ce f3 8f f8 prfum #0xe, [x30, #255] + libdis_test+0x624: 2e 10 80 f8 prfum #0xe, [x1, #1] + libdis_test+0x628: 2e f0 9f f8 prfum #0xe, [x1, #-1] + libdis_test+0x62c: 0f 00 80 f8 prfum #0xf, [x0] + libdis_test+0x630: ef 03 90 f8 prfum #0xf, [sp, #-256] + libdis_test+0x634: cf f3 8f f8 prfum #0xf, [x30, #255] + libdis_test+0x638: 2f 10 80 f8 prfum #0xf, [x1, #1] + libdis_test+0x63c: 2f f0 9f f8 prfum #0xf, [x1, #-1] + libdis_test+0x640: 10 00 80 f8 prfum pstl1keep, [x0] + libdis_test+0x644: f0 03 90 f8 prfum pstl1keep, [sp, #-256] + libdis_test+0x648: d0 f3 8f f8 prfum pstl1keep, [x30, #255] + libdis_test+0x64c: 30 10 80 f8 prfum pstl1keep, [x1, #1] + libdis_test+0x650: 30 f0 9f f8 prfum pstl1keep, [x1, #-1] + libdis_test+0x654: 11 00 80 f8 prfum pstl1strm, [x0] + libdis_test+0x658: f1 03 90 f8 prfum pstl1strm, [sp, #-256] + libdis_test+0x65c: d1 f3 8f f8 prfum pstl1strm, [x30, #255] + libdis_test+0x660: 31 10 80 f8 prfum pstl1strm, [x1, #1] + libdis_test+0x664: 31 f0 9f f8 prfum pstl1strm, [x1, #-1] + libdis_test+0x668: 12 00 80 f8 prfum pstl2keep, [x0] + libdis_test+0x66c: f2 03 90 f8 prfum pstl2keep, [sp, #-256] + libdis_test+0x670: d2 f3 8f f8 prfum pstl2keep, [x30, #255] + libdis_test+0x674: 32 10 80 f8 prfum pstl2keep, [x1, #1] + libdis_test+0x678: 32 f0 9f f8 prfum pstl2keep, [x1, #-1] + libdis_test+0x67c: 13 00 80 f8 prfum pstl2strm, [x0] + libdis_test+0x680: f3 03 90 f8 prfum pstl2strm, [sp, #-256] + libdis_test+0x684: d3 f3 8f f8 prfum pstl2strm, [x30, #255] + libdis_test+0x688: 33 10 80 f8 prfum pstl2strm, [x1, #1] + libdis_test+0x68c: 33 f0 9f f8 prfum pstl2strm, [x1, #-1] + libdis_test+0x690: 14 00 80 f8 prfum pstl3keep, [x0] + libdis_test+0x694: f4 03 90 f8 prfum pstl3keep, [sp, #-256] + libdis_test+0x698: d4 f3 8f f8 prfum pstl3keep, [x30, #255] + libdis_test+0x69c: 34 10 80 f8 prfum pstl3keep, [x1, #1] + libdis_test+0x6a0: 34 f0 9f f8 prfum pstl3keep, [x1, #-1] + libdis_test+0x6a4: 15 00 80 f8 prfum pstl3strm, [x0] + libdis_test+0x6a8: f5 03 90 f8 prfum pstl3strm, [sp, #-256] + libdis_test+0x6ac: d5 f3 8f f8 prfum pstl3strm, [x30, #255] + libdis_test+0x6b0: 35 10 80 f8 prfum pstl3strm, [x1, #1] + libdis_test+0x6b4: 35 f0 9f f8 prfum pstl3strm, [x1, #-1] + libdis_test+0x6b8: 16 00 80 f8 prfum #0x16, [x0] + libdis_test+0x6bc: f6 03 90 f8 prfum #0x16, [sp, #-256] + libdis_test+0x6c0: d6 f3 8f f8 prfum #0x16, [x30, #255] + libdis_test+0x6c4: 36 10 80 f8 prfum #0x16, [x1, #1] + libdis_test+0x6c8: 36 f0 9f f8 prfum #0x16, [x1, #-1] + libdis_test+0x6cc: 17 00 80 f8 prfum #0x17, [x0] + libdis_test+0x6d0: f7 03 90 f8 prfum #0x17, [sp, #-256] + libdis_test+0x6d4: d7 f3 8f f8 prfum #0x17, [x30, #255] + libdis_test+0x6d8: 37 10 80 f8 prfum #0x17, [x1, #1] + libdis_test+0x6dc: 37 f0 9f f8 prfum #0x17, [x1, #-1] + libdis_test+0x6e0: 18 00 80 f8 prfum #0x18, [x0] + libdis_test+0x6e4: f8 03 90 f8 prfum #0x18, [sp, #-256] + libdis_test+0x6e8: d8 f3 8f f8 prfum #0x18, [x30, #255] + libdis_test+0x6ec: 38 10 80 f8 prfum #0x18, [x1, #1] + libdis_test+0x6f0: 38 f0 9f f8 prfum #0x18, [x1, #-1] + libdis_test+0x6f4: 19 00 80 f8 prfum #0x19, [x0] + libdis_test+0x6f8: f9 03 90 f8 prfum #0x19, [sp, #-256] + libdis_test+0x6fc: d9 f3 8f f8 prfum #0x19, [x30, #255] + libdis_test+0x700: 39 10 80 f8 prfum #0x19, [x1, #1] + libdis_test+0x704: 39 f0 9f f8 prfum #0x19, [x1, #-1] + libdis_test+0x708: 1a 00 80 f8 prfum #0x1a, [x0] + libdis_test+0x70c: fa 03 90 f8 prfum #0x1a, [sp, #-256] + libdis_test+0x710: da f3 8f f8 prfum #0x1a, [x30, #255] + libdis_test+0x714: 3a 10 80 f8 prfum #0x1a, [x1, #1] + libdis_test+0x718: 3a f0 9f f8 prfum #0x1a, [x1, #-1] + libdis_test+0x71c: 1b 00 80 f8 prfum #0x1b, [x0] + libdis_test+0x720: fb 03 90 f8 prfum #0x1b, [sp, #-256] + libdis_test+0x724: db f3 8f f8 prfum #0x1b, [x30, #255] + libdis_test+0x728: 3b 10 80 f8 prfum #0x1b, [x1, #1] + libdis_test+0x72c: 3b f0 9f f8 prfum #0x1b, [x1, #-1] + libdis_test+0x730: 1c 00 80 f8 prfum #0x1c, [x0] + libdis_test+0x734: fc 03 90 f8 prfum #0x1c, [sp, #-256] + libdis_test+0x738: dc f3 8f f8 prfum #0x1c, [x30, #255] + libdis_test+0x73c: 3c 10 80 f8 prfum #0x1c, [x1, #1] + libdis_test+0x740: 3c f0 9f f8 prfum #0x1c, [x1, #-1] + libdis_test+0x744: 1d 00 80 f8 prfum #0x1d, [x0] + libdis_test+0x748: fd 03 90 f8 prfum #0x1d, [sp, #-256] + libdis_test+0x74c: dd f3 8f f8 prfum #0x1d, [x30, #255] + libdis_test+0x750: 3d 10 80 f8 prfum #0x1d, [x1, #1] + libdis_test+0x754: 3d f0 9f f8 prfum #0x1d, [x1, #-1] + libdis_test+0x758: 1e 00 80 f8 prfum #0x1e, [x0] + libdis_test+0x75c: fe 03 90 f8 prfum #0x1e, [sp, #-256] + libdis_test+0x760: de f3 8f f8 prfum #0x1e, [x30, #255] + libdis_test+0x764: 3e 10 80 f8 prfum #0x1e, [x1, #1] + libdis_test+0x768: 3e f0 9f f8 prfum #0x1e, [x1, #-1] + libdis_test+0x76c: 1f 00 80 f8 prfum #0x1f, [x0] + libdis_test+0x770: ff 03 90 f8 prfum #0x1f, [sp, #-256] + libdis_test+0x774: df f3 8f f8 prfum #0x1f, [x30, #255] + libdis_test+0x778: 3f 10 80 f8 prfum #0x1f, [x1, #1] + libdis_test+0x77c: 3f f0 9f f8 prfum #0x1f, [x1, #-1] + libdis_test+0x780: 00 00 80 f9 prfm pldl1keep, [x0] + libdis_test+0x784: e0 03 80 f9 prfm pldl1keep, [sp] + libdis_test+0x788: c0 ff bf f9 prfm pldl1keep, [x30, #32760] + libdis_test+0x78c: 20 04 80 f9 prfm pldl1keep, [x1, #8] + libdis_test+0x790: 01 00 80 f9 prfm pldl1strm, [x0] + libdis_test+0x794: e1 03 80 f9 prfm pldl1strm, [sp] + libdis_test+0x798: c1 ff bf f9 prfm pldl1strm, [x30, #32760] + libdis_test+0x79c: 21 04 80 f9 prfm pldl1strm, [x1, #8] + libdis_test+0x7a0: 02 00 80 f9 prfm pldl2keep, [x0] + libdis_test+0x7a4: e2 03 80 f9 prfm pldl2keep, [sp] + libdis_test+0x7a8: c2 ff bf f9 prfm pldl2keep, [x30, #32760] + libdis_test+0x7ac: 22 04 80 f9 prfm pldl2keep, [x1, #8] + libdis_test+0x7b0: 03 00 80 f9 prfm pldl2strm, [x0] + libdis_test+0x7b4: e3 03 80 f9 prfm pldl2strm, [sp] + libdis_test+0x7b8: c3 ff bf f9 prfm pldl2strm, [x30, #32760] + libdis_test+0x7bc: 23 04 80 f9 prfm pldl2strm, [x1, #8] + libdis_test+0x7c0: 04 00 80 f9 prfm pldl3keep, [x0] + libdis_test+0x7c4: e4 03 80 f9 prfm pldl3keep, [sp] + libdis_test+0x7c8: c4 ff bf f9 prfm pldl3keep, [x30, #32760] + libdis_test+0x7cc: 24 04 80 f9 prfm pldl3keep, [x1, #8] + libdis_test+0x7d0: 05 00 80 f9 prfm pldl3strm, [x0] + libdis_test+0x7d4: e5 03 80 f9 prfm pldl3strm, [sp] + libdis_test+0x7d8: c5 ff bf f9 prfm pldl3strm, [x30, #32760] + libdis_test+0x7dc: 25 04 80 f9 prfm pldl3strm, [x1, #8] + libdis_test+0x7e0: 06 00 80 f9 prfm #0x6, [x0] + libdis_test+0x7e4: e6 03 80 f9 prfm #0x6, [sp] + libdis_test+0x7e8: c6 ff bf f9 prfm #0x6, [x30, #32760] + libdis_test+0x7ec: 26 04 80 f9 prfm #0x6, [x1, #8] + libdis_test+0x7f0: 07 00 80 f9 prfm #0x7, [x0] + libdis_test+0x7f4: e7 03 80 f9 prfm #0x7, [sp] + libdis_test+0x7f8: c7 ff bf f9 prfm #0x7, [x30, #32760] + libdis_test+0x7fc: 27 04 80 f9 prfm #0x7, [x1, #8] + libdis_test+0x800: 08 00 80 f9 prfm plil1keep, [x0] + libdis_test+0x804: e8 03 80 f9 prfm plil1keep, [sp] + libdis_test+0x808: c8 ff bf f9 prfm plil1keep, [x30, #32760] + libdis_test+0x80c: 28 04 80 f9 prfm plil1keep, [x1, #8] + libdis_test+0x810: 09 00 80 f9 prfm plil1strm, [x0] + libdis_test+0x814: e9 03 80 f9 prfm plil1strm, [sp] + libdis_test+0x818: c9 ff bf f9 prfm plil1strm, [x30, #32760] + libdis_test+0x81c: 29 04 80 f9 prfm plil1strm, [x1, #8] + libdis_test+0x820: 0a 00 80 f9 prfm plil2keep, [x0] + libdis_test+0x824: ea 03 80 f9 prfm plil2keep, [sp] + libdis_test+0x828: ca ff bf f9 prfm plil2keep, [x30, #32760] + libdis_test+0x82c: 2a 04 80 f9 prfm plil2keep, [x1, #8] + libdis_test+0x830: 0b 00 80 f9 prfm plil2strm, [x0] + libdis_test+0x834: eb 03 80 f9 prfm plil2strm, [sp] + libdis_test+0x838: cb ff bf f9 prfm plil2strm, [x30, #32760] + libdis_test+0x83c: 2b 04 80 f9 prfm plil2strm, [x1, #8] + libdis_test+0x840: 0c 00 80 f9 prfm plil3keep, [x0] + libdis_test+0x844: ec 03 80 f9 prfm plil3keep, [sp] + libdis_test+0x848: cc ff bf f9 prfm plil3keep, [x30, #32760] + libdis_test+0x84c: 2c 04 80 f9 prfm plil3keep, [x1, #8] + libdis_test+0x850: 0d 00 80 f9 prfm plil3strm, [x0] + libdis_test+0x854: ed 03 80 f9 prfm plil3strm, [sp] + libdis_test+0x858: cd ff bf f9 prfm plil3strm, [x30, #32760] + libdis_test+0x85c: 2d 04 80 f9 prfm plil3strm, [x1, #8] + libdis_test+0x860: 0e 00 80 f9 prfm #0xe, [x0] + libdis_test+0x864: ee 03 80 f9 prfm #0xe, [sp] + libdis_test+0x868: ce ff bf f9 prfm #0xe, [x30, #32760] + libdis_test+0x86c: 2e 04 80 f9 prfm #0xe, [x1, #8] + libdis_test+0x870: 0f 00 80 f9 prfm #0xf, [x0] + libdis_test+0x874: ef 03 80 f9 prfm #0xf, [sp] + libdis_test+0x878: cf ff bf f9 prfm #0xf, [x30, #32760] + libdis_test+0x87c: 2f 04 80 f9 prfm #0xf, [x1, #8] + libdis_test+0x880: 10 00 80 f9 prfm pstl1keep, [x0] + libdis_test+0x884: f0 03 80 f9 prfm pstl1keep, [sp] + libdis_test+0x888: d0 ff bf f9 prfm pstl1keep, [x30, #32760] + libdis_test+0x88c: 30 04 80 f9 prfm pstl1keep, [x1, #8] + libdis_test+0x890: 11 00 80 f9 prfm pstl1strm, [x0] + libdis_test+0x894: f1 03 80 f9 prfm pstl1strm, [sp] + libdis_test+0x898: d1 ff bf f9 prfm pstl1strm, [x30, #32760] + libdis_test+0x89c: 31 04 80 f9 prfm pstl1strm, [x1, #8] + libdis_test+0x8a0: 12 00 80 f9 prfm pstl2keep, [x0] + libdis_test+0x8a4: f2 03 80 f9 prfm pstl2keep, [sp] + libdis_test+0x8a8: d2 ff bf f9 prfm pstl2keep, [x30, #32760] + libdis_test+0x8ac: 32 04 80 f9 prfm pstl2keep, [x1, #8] + libdis_test+0x8b0: 13 00 80 f9 prfm pstl2strm, [x0] + libdis_test+0x8b4: f3 03 80 f9 prfm pstl2strm, [sp] + libdis_test+0x8b8: d3 ff bf f9 prfm pstl2strm, [x30, #32760] + libdis_test+0x8bc: 33 04 80 f9 prfm pstl2strm, [x1, #8] + libdis_test+0x8c0: 14 00 80 f9 prfm pstl3keep, [x0] + libdis_test+0x8c4: f4 03 80 f9 prfm pstl3keep, [sp] + libdis_test+0x8c8: d4 ff bf f9 prfm pstl3keep, [x30, #32760] + libdis_test+0x8cc: 34 04 80 f9 prfm pstl3keep, [x1, #8] + libdis_test+0x8d0: 15 00 80 f9 prfm pstl3strm, [x0] + libdis_test+0x8d4: f5 03 80 f9 prfm pstl3strm, [sp] + libdis_test+0x8d8: d5 ff bf f9 prfm pstl3strm, [x30, #32760] + libdis_test+0x8dc: 35 04 80 f9 prfm pstl3strm, [x1, #8] + libdis_test+0x8e0: 16 00 80 f9 prfm #0x16, [x0] + libdis_test+0x8e4: f6 03 80 f9 prfm #0x16, [sp] + libdis_test+0x8e8: d6 ff bf f9 prfm #0x16, [x30, #32760] + libdis_test+0x8ec: 36 04 80 f9 prfm #0x16, [x1, #8] + libdis_test+0x8f0: 17 00 80 f9 prfm #0x17, [x0] + libdis_test+0x8f4: f7 03 80 f9 prfm #0x17, [sp] + libdis_test+0x8f8: d7 ff bf f9 prfm #0x17, [x30, #32760] + libdis_test+0x8fc: 37 04 80 f9 prfm #0x17, [x1, #8] + libdis_test+0x900: 18 00 80 f9 prfm #0x18, [x0] + libdis_test+0x904: f8 03 80 f9 prfm #0x18, [sp] + libdis_test+0x908: d8 ff bf f9 prfm #0x18, [x30, #32760] + libdis_test+0x90c: 38 04 80 f9 prfm #0x18, [x1, #8] + libdis_test+0x910: 19 00 80 f9 prfm #0x19, [x0] + libdis_test+0x914: f9 03 80 f9 prfm #0x19, [sp] + libdis_test+0x918: d9 ff bf f9 prfm #0x19, [x30, #32760] + libdis_test+0x91c: 39 04 80 f9 prfm #0x19, [x1, #8] + libdis_test+0x920: 1a 00 80 f9 prfm #0x1a, [x0] + libdis_test+0x924: fa 03 80 f9 prfm #0x1a, [sp] + libdis_test+0x928: da ff bf f9 prfm #0x1a, [x30, #32760] + libdis_test+0x92c: 3a 04 80 f9 prfm #0x1a, [x1, #8] + libdis_test+0x930: 1b 00 80 f9 prfm #0x1b, [x0] + libdis_test+0x934: fb 03 80 f9 prfm #0x1b, [sp] + libdis_test+0x938: db ff bf f9 prfm #0x1b, [x30, #32760] + libdis_test+0x93c: 3b 04 80 f9 prfm #0x1b, [x1, #8] + libdis_test+0x940: 1c 00 80 f9 prfm #0x1c, [x0] + libdis_test+0x944: fc 03 80 f9 prfm #0x1c, [sp] + libdis_test+0x948: dc ff bf f9 prfm #0x1c, [x30, #32760] + libdis_test+0x94c: 3c 04 80 f9 prfm #0x1c, [x1, #8] + libdis_test+0x950: 1d 00 80 f9 prfm #0x1d, [x0] + libdis_test+0x954: fd 03 80 f9 prfm #0x1d, [sp] + libdis_test+0x958: dd ff bf f9 prfm #0x1d, [x30, #32760] + libdis_test+0x95c: 3d 04 80 f9 prfm #0x1d, [x1, #8] + libdis_test+0x960: 1e 00 80 f9 prfm #0x1e, [x0] + libdis_test+0x964: fe 03 80 f9 prfm #0x1e, [sp] + libdis_test+0x968: de ff bf f9 prfm #0x1e, [x30, #32760] + libdis_test+0x96c: 3e 04 80 f9 prfm #0x1e, [x1, #8] + libdis_test+0x970: 1f 00 80 f9 prfm #0x1f, [x0] + libdis_test+0x974: ff 03 80 f9 prfm #0x1f, [sp] + libdis_test+0x978: df ff bf f9 prfm #0x1f, [x30, #32760] + libdis_test+0x97c: 3f 04 80 f9 prfm #0x1f, [x1, #8] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-prfm.s b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-prfm.s new file mode 100755 index 0000000000..058b37f409 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-prfm.s @@ -0,0 +1,74 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.3.5 Load register (literal) + * C3.3.10 Load/store register (register offset) + * C3.3.12 Load/store register (unscaled immediate) + * C3.3.13 Load/store register (unsigned immediate) + * + * Test just the PRFM/PRFUM instructions from these groups, with minimum + * and maximum values for prfop, registers, immediates and shifts. + */ +.macro prf_lit op, from=0, to=31 +1: + .ifge \from-16 + \op \from, 2f + .else + \op \from, 1b + .endif + .if \to-\from + prf_lit \op "(\from+1)" \to + .endif +2: +.endm + +.macro prf_reg op, from=0, to=31 + \op \from, [x0, x0] + \op \from, [x0, w0, uxtw] + \op \from, [sp, wzr, uxtw #3] + \op \from, [x0, x0, lsl #0] + \op \from, [sp, xzr, lsl #3] + \op \from, [x0, w0, sxtw #0] + \op \from, [sp, wzr, sxtw #3] + \op \from, [x0, x0, sxtx] + \op \from, [sp, xzr, sxtx #3] + .if \to-\from + prf_reg \op "(\from+1)" \to + .endif +.endm + +.macro prf_imm op, min, max, step, from=0, to=31 + \op \from, [x0] + \op \from, [sp, #\min] + \op \from, [x30, #\max] + \op \from, [x1, #(1*\step)] + .iflt \min + \op \from, [x1, #(-1*\step)] + .endif + .if \to-\from + prf_imm \op, \min, \max, \step, "(\from+1)", \to + .endif +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + prf_lit prfm + prf_reg prfm + prf_imm prfum, -256, 255, 1 + prf_imm prfm, 0, 32760, 8 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-imm-post.out b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-imm-post.out new file mode 100755 index 0000000000..a6735d0029 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-imm-post.out @@ -0,0 +1,39 @@ + libdis_test: 00 04 00 38 strb w0, [x0], #0 + libdis_test+0x4: de f7 0f 38 strb w30, [x30], #255 + libdis_test+0x8: ff 07 10 38 strb wzr, [sp], #-256 + libdis_test+0xc: 00 04 40 38 ldrb w0, [x0], #0 + libdis_test+0x10: de f7 4f 38 ldrb w30, [x30], #255 + libdis_test+0x14: ff 07 50 38 ldrb wzr, [sp], #-256 + libdis_test+0x18: 00 04 c0 38 ldrsb w0, [x0], #0 + libdis_test+0x1c: de f7 cf 38 ldrsb w30, [x30], #255 + libdis_test+0x20: ff 07 d0 38 ldrsb wzr, [sp], #-256 + libdis_test+0x24: 00 04 80 38 ldrsb x0, [x0], #0 + libdis_test+0x28: de f7 8f 38 ldrsb x30, [x30], #255 + libdis_test+0x2c: ff 07 90 38 ldrsb xzr, [sp], #-256 + libdis_test+0x30: 00 04 00 b8 str w0, [x0], #0 + libdis_test+0x34: de f7 0f b8 str w30, [x30], #255 + libdis_test+0x38: ff 07 10 b8 str wzr, [sp], #-256 + libdis_test+0x3c: 00 04 00 f8 str x0, [x0], #0 + libdis_test+0x40: de f7 0f f8 str x30, [x30], #255 + libdis_test+0x44: ff 07 10 f8 str xzr, [sp], #-256 + libdis_test+0x48: 00 04 40 b8 ldr w0, [x0], #0 + libdis_test+0x4c: de f7 4f b8 ldr w30, [x30], #255 + libdis_test+0x50: ff 07 50 b8 ldr wzr, [sp], #-256 + libdis_test+0x54: 00 04 40 f8 ldr x0, [x0], #0 + libdis_test+0x58: de f7 4f f8 ldr x30, [x30], #255 + libdis_test+0x5c: ff 07 50 f8 ldr xzr, [sp], #-256 + libdis_test+0x60: 00 04 00 78 strh w0, [x0], #0 + libdis_test+0x64: de f7 0f 78 strh w30, [x30], #255 + libdis_test+0x68: ff 07 10 78 strh wzr, [sp], #-256 + libdis_test+0x6c: 00 04 40 78 ldrh w0, [x0], #0 + libdis_test+0x70: de f7 4f 78 ldrh w30, [x30], #255 + libdis_test+0x74: ff 07 50 78 ldrh wzr, [sp], #-256 + libdis_test+0x78: 00 04 c0 78 ldrsh w0, [x0], #0 + libdis_test+0x7c: de f7 cf 78 ldrsh w30, [x30], #255 + libdis_test+0x80: ff 07 d0 78 ldrsh wzr, [sp], #-256 + libdis_test+0x84: 00 04 80 78 ldrsh x0, [x0], #0 + libdis_test+0x88: de f7 8f 78 ldrsh x30, [x30], #255 + libdis_test+0x8c: ff 07 90 78 ldrsh xzr, [sp], #-256 + libdis_test+0x90: 00 04 80 b8 ldrsw x0, [x0], #0 + libdis_test+0x94: de f7 8f b8 ldrsw x30, [x30], #255 + libdis_test+0x98: ff 07 90 b8 ldrsw xzr, [sp], #-256 diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-imm-post.s b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-imm-post.s new file mode 100755 index 0000000000..4584443d8a --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-imm-post.s @@ -0,0 +1,66 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.3.8 Load/store register (immediate post-indexed) + * + * C5.6.180 STRB <Wt>, [<Xn|SP>], #<simm> + * C5.6.86 LDRB <Wt>, [<Xn|SP>], #<simm> + * C5.6.90 LDRSB <Rt>, [<Xn|SP>], #<simm> + * C6.3.285 STR <Vt>, [<Xn|SP>], #<simm> + * C6.3.166 LDR <Vt>, [<Xn|SP>], #<simm> + * C5.6.182 STRH <Wt>, [<Xn|SP>], #<simm> + * C5.6.88 LDRH <Wt>, [<Xn|SP>], #<simm> + * C5.6.92 LDRSH <Rt>, [<Xn|SP>], #<simm> + * C5.6.178 STR <Rt>, [<Xn|SP>], #<simm> + * C5.6.83 LDR <Rt>, [<Xn|SP>], #<simm> + * C5.6.94 LDRSW <Xt>, [<Xn|SP>], #<simm> + * + * simm is signed 9bit, so test min/max. + */ +.macro ldst_reg_imm_post op, wreg=0, xreg=0, simd=0 + .if \wreg + \op w0, [x0], #0 + \op w30, [x30], #255 + \op wzr, [sp], #-256 + .endif + .if \xreg + \op x0, [x0], #0 + \op x30, [x30], #255 + \op xzr, [sp], #-256 + .endif + .if \simd + \op b0, [x0], #0 + \op h31, [sp], #1 + \op s0, [x0], #-1 + \op d31, [sp], #255 + \op q0, [x0], #-256 + .endif +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + ldst_reg_imm_post strb 1 + ldst_reg_imm_post ldrb 1 + ldst_reg_imm_post ldrsb 1 1 + ldst_reg_imm_post str 1 1 + ldst_reg_imm_post ldr 1 1 + ldst_reg_imm_post strh 1 + ldst_reg_imm_post ldrh 1 + ldst_reg_imm_post ldrsh 1 1 + ldst_reg_imm_post ldrsw 0 1 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-imm-pre.out b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-imm-pre.out new file mode 100755 index 0000000000..3dba4c05b7 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-imm-pre.out @@ -0,0 +1,39 @@ + libdis_test: 00 0c 00 38 strb w0, [x0, #0]! + libdis_test+0x4: de ff 0f 38 strb w30, [x30, #255]! + libdis_test+0x8: ff 0f 10 38 strb wzr, [sp, #-256]! + libdis_test+0xc: 00 0c 40 38 ldrb w0, [x0, #0]! + libdis_test+0x10: de ff 4f 38 ldrb w30, [x30, #255]! + libdis_test+0x14: ff 0f 50 38 ldrb wzr, [sp, #-256]! + libdis_test+0x18: 00 0c c0 38 ldrsb w0, [x0, #0]! + libdis_test+0x1c: de ff cf 38 ldrsb w30, [x30, #255]! + libdis_test+0x20: ff 0f d0 38 ldrsb wzr, [sp, #-256]! + libdis_test+0x24: 00 0c 80 38 ldrsb x0, [x0, #0]! + libdis_test+0x28: de ff 8f 38 ldrsb x30, [x30, #255]! + libdis_test+0x2c: ff 0f 90 38 ldrsb xzr, [sp, #-256]! + libdis_test+0x30: 00 0c 00 b8 str w0, [x0, #0]! + libdis_test+0x34: de ff 0f b8 str w30, [x30, #255]! + libdis_test+0x38: ff 0f 10 b8 str wzr, [sp, #-256]! + libdis_test+0x3c: 00 0c 00 f8 str x0, [x0, #0]! + libdis_test+0x40: de ff 0f f8 str x30, [x30, #255]! + libdis_test+0x44: ff 0f 10 f8 str xzr, [sp, #-256]! + libdis_test+0x48: 00 0c 40 b8 ldr w0, [x0, #0]! + libdis_test+0x4c: de ff 4f b8 ldr w30, [x30, #255]! + libdis_test+0x50: ff 0f 50 b8 ldr wzr, [sp, #-256]! + libdis_test+0x54: 00 0c 40 f8 ldr x0, [x0, #0]! + libdis_test+0x58: de ff 4f f8 ldr x30, [x30, #255]! + libdis_test+0x5c: ff 0f 50 f8 ldr xzr, [sp, #-256]! + libdis_test+0x60: 00 0c 00 78 strh w0, [x0, #0]! + libdis_test+0x64: de ff 0f 78 strh w30, [x30, #255]! + libdis_test+0x68: ff 0f 10 78 strh wzr, [sp, #-256]! + libdis_test+0x6c: 00 0c 40 78 ldrh w0, [x0, #0]! + libdis_test+0x70: de ff 4f 78 ldrh w30, [x30, #255]! + libdis_test+0x74: ff 0f 50 78 ldrh wzr, [sp, #-256]! + libdis_test+0x78: 00 0c c0 78 ldrsh w0, [x0, #0]! + libdis_test+0x7c: de ff cf 78 ldrsh w30, [x30, #255]! + libdis_test+0x80: ff 0f d0 78 ldrsh wzr, [sp, #-256]! + libdis_test+0x84: 00 0c 80 78 ldrsh x0, [x0, #0]! + libdis_test+0x88: de ff 8f 78 ldrsh x30, [x30, #255]! + libdis_test+0x8c: ff 0f 90 78 ldrsh xzr, [sp, #-256]! + libdis_test+0x90: 00 0c 80 b8 ldrsw x0, [x0, #0]! + libdis_test+0x94: de ff 8f b8 ldrsw x30, [x30, #255]! + libdis_test+0x98: ff 0f 90 b8 ldrsw xzr, [sp, #-256]! diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-imm-pre.s b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-imm-pre.s new file mode 100755 index 0000000000..b51e206ec0 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-imm-pre.s @@ -0,0 +1,66 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.3.9 Load/store register (immediate pre-indexed) + * + * C5.6.180 STRB <Wt>, [<Xn|SP>, #<simm>]! + * C5.6.86 LDRB <Wt>, [<Xn|SP>, #<simm>]! + * C5.6.90 LDRSB <Rt>, [<Xn|SP>, #<simm>]! + * C6.3.285 STR <Vt>, [<Xn|SP>, #<simm>]! + * C6.3.166 LDR <Vt>, [<Xn|SP>, #<simm>]! + * C5.6.182 STRH <Wt>, [<Xn|SP>, #<simm>]! + * C5.6.88 LDRH <Wt>, [<Xn|SP>, #<simm>]! + * C5.6.92 LDRSH <Rt>, [<Xn|SP>, #<simm>]! + * C5.6.178 STR <Rt>, [<Xn|SP>, #<simm>]! + * C5.6.83 LDR <Rt>, [<Xn|SP>, #<simm>]! + * C5.6.94 LDRSW <Xt>, [<Xn|SP>, #<simm>]! + * + * simm is signed 9bit, so test min/max. + */ +.macro ldst_reg_imm_pre op, wreg=0, xreg=0, simd=0 + .if \wreg + \op w0, [x0, #0]! + \op w30, [x30, #255]! + \op wzr, [sp, #-256]! + .endif + .if \xreg + \op x0, [x0, #0]! + \op x30, [x30, #255]! + \op xzr, [sp, #-256]! + .endif + .if \simd + \op b0, [x0, #0]! + \op h31, [sp, #1]! + \op s0, [x0, #-1]! + \op d31, [sp, #255]! + \op q0, [x0, #-256]! + .endif +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + ldst_reg_imm_pre strb 1 + ldst_reg_imm_pre ldrb 1 + ldst_reg_imm_pre ldrsb 1 1 + ldst_reg_imm_pre str 1 1 + ldst_reg_imm_pre ldr 1 1 + ldst_reg_imm_pre strh 1 + ldst_reg_imm_pre ldrh 1 + ldst_reg_imm_pre ldrsh 1 1 + ldst_reg_imm_pre ldrsw 0 1 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-offset.out b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-offset.out new file mode 100755 index 0000000000..9f85ada4a5 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-offset.out @@ -0,0 +1,62 @@ + libdis_test: 00 68 20 38 strb w0, [x0, x0] + libdis_test+0x4: de eb 3e 38 strb w30, [x30, x30, sxtx] + libdis_test+0x8: ff fb 3f 38 strb wzr, [sp, xzr, sxtx #0] + libdis_test+0xc: ff 7b 3f 38 strb wzr, [sp, xzr, lsl #0] + libdis_test+0x10: 00 68 60 38 ldrb w0, [x0, x0] + libdis_test+0x14: de eb 7e 38 ldrb w30, [x30, x30, sxtx] + libdis_test+0x18: ff fb 7f 38 ldrb wzr, [sp, xzr, sxtx #0] + libdis_test+0x1c: ff 7b 7f 38 ldrb wzr, [sp, xzr, lsl #0] + libdis_test+0x20: 00 68 e0 38 ldrsb w0, [x0, x0] + libdis_test+0x24: de eb fe 38 ldrsb w30, [x30, x30, sxtx] + libdis_test+0x28: ff fb ff 38 ldrsb wzr, [sp, xzr, sxtx #0] + libdis_test+0x2c: ff 7b ff 38 ldrsb wzr, [sp, xzr, lsl #0] + libdis_test+0x30: 00 68 a0 38 ldrsb x0, [x0, x0] + libdis_test+0x34: de 4b be 38 ldrsb x30, [x30, w30, uxtw] + libdis_test+0x38: ff 5b bf 38 ldrsb xzr, [sp, wzr, uxtw #0] + libdis_test+0x3c: ff 7b bf 38 ldrsb xzr, [sp, xzr, lsl #0] + libdis_test+0x40: ff db bf 38 ldrsb xzr, [sp, wzr, sxtw #0] + libdis_test+0x44: ff fb bf 38 ldrsb xzr, [sp, xzr, sxtx #0] + libdis_test+0x48: 00 68 20 b8 str w0, [x0, x0] + libdis_test+0x4c: de eb 3e b8 str w30, [x30, x30, sxtx] + libdis_test+0x50: ff fb 3f b8 str wzr, [sp, xzr, sxtx #2] + libdis_test+0x54: ff 6b 3f b8 str wzr, [sp, xzr] + libdis_test+0x58: 00 68 20 f8 str x0, [x0, x0] + libdis_test+0x5c: de 4b 3e f8 str x30, [x30, w30, uxtw] + libdis_test+0x60: ff 5b 3f f8 str xzr, [sp, wzr, uxtw #3] + libdis_test+0x64: ff 7b 3f f8 str xzr, [sp, xzr, lsl #3] + libdis_test+0x68: ff db 3f f8 str xzr, [sp, wzr, sxtw #3] + libdis_test+0x6c: ff fb 3f f8 str xzr, [sp, xzr, sxtx #3] + libdis_test+0x70: 00 68 60 b8 ldr w0, [x0, x0] + libdis_test+0x74: de eb 7e b8 ldr w30, [x30, x30, sxtx] + libdis_test+0x78: ff fb 7f b8 ldr wzr, [sp, xzr, sxtx #2] + libdis_test+0x7c: ff 6b 7f b8 ldr wzr, [sp, xzr] + libdis_test+0x80: 00 68 60 f8 ldr x0, [x0, x0] + libdis_test+0x84: de 4b 7e f8 ldr x30, [x30, w30, uxtw] + libdis_test+0x88: ff 5b 7f f8 ldr xzr, [sp, wzr, uxtw #3] + libdis_test+0x8c: ff 7b 7f f8 ldr xzr, [sp, xzr, lsl #3] + libdis_test+0x90: ff db 7f f8 ldr xzr, [sp, wzr, sxtw #3] + libdis_test+0x94: ff fb 7f f8 ldr xzr, [sp, xzr, sxtx #3] + libdis_test+0x98: 00 68 20 78 strh w0, [x0, x0] + libdis_test+0x9c: de eb 3e 78 strh w30, [x30, x30, sxtx] + libdis_test+0xa0: ff fb 3f 78 strh wzr, [sp, xzr, sxtx #1] + libdis_test+0xa4: ff 6b 3f 78 strh wzr, [sp, xzr] + libdis_test+0xa8: 00 68 60 78 ldrh w0, [x0, x0] + libdis_test+0xac: de eb 7e 78 ldrh w30, [x30, x30, sxtx] + libdis_test+0xb0: ff fb 7f 78 ldrh wzr, [sp, xzr, sxtx #1] + libdis_test+0xb4: ff 6b 7f 78 ldrh wzr, [sp, xzr] + libdis_test+0xb8: 00 68 e0 78 ldrsh w0, [x0, x0] + libdis_test+0xbc: de eb fe 78 ldrsh w30, [x30, x30, sxtx] + libdis_test+0xc0: ff fb ff 78 ldrsh wzr, [sp, xzr, sxtx #1] + libdis_test+0xc4: ff 6b ff 78 ldrsh wzr, [sp, xzr] + libdis_test+0xc8: 00 68 a0 78 ldrsh x0, [x0, x0] + libdis_test+0xcc: de 4b be 78 ldrsh x30, [x30, w30, uxtw] + libdis_test+0xd0: ff 5b bf 78 ldrsh xzr, [sp, wzr, uxtw #1] + libdis_test+0xd4: ff 7b bf 78 ldrsh xzr, [sp, xzr, lsl #1] + libdis_test+0xd8: ff db bf 78 ldrsh xzr, [sp, wzr, sxtw #1] + libdis_test+0xdc: ff fb bf 78 ldrsh xzr, [sp, xzr, sxtx #1] + libdis_test+0xe0: 00 68 a0 b8 ldrsw x0, [x0, x0] + libdis_test+0xe4: de 4b be b8 ldrsw x30, [x30, w30, uxtw] + libdis_test+0xe8: ff 5b bf b8 ldrsw xzr, [sp, wzr, uxtw #2] + libdis_test+0xec: ff 7b bf b8 ldrsw xzr, [sp, xzr, lsl #2] + libdis_test+0xf0: ff db bf b8 ldrsw xzr, [sp, wzr, sxtw #2] + libdis_test+0xf4: ff fb bf b8 ldrsw xzr, [sp, xzr, sxtx #2] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-offset.s b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-offset.s new file mode 100755 index 0000000000..f40a3b1a5a --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-offset.s @@ -0,0 +1,70 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.3.10 Load/store register (register offset) + * + * C5.6.145 PRFM is part of this group but is tested in tst.ldst-prfm.s + */ +.macro ldst_reg_offset_simd op, reg, size + \op \reg\()0, [x0, x0] + \op \reg\()31, [sp, wzr, uxtw] + \op \reg\()0, [x30, w30, uxtw #\size] + \op \reg\()31, [sp, xzr, lsl #0] + \op \reg\()0, [x30, x30, lsl #\size] + \op \reg\()31, [sp, wzr, sxtw] + \op \reg\()0, [x30, w30, sxtw #\size] + \op \reg\()31, [sp, xzr, sxtx] + \op \reg\()0, [x30, x30, sxtx #\size] +.endm + +.macro ldst_reg_offset op, wreg=0, xreg=0, simd=0, size32=0, size64=0 + .if \wreg + \op w0, [x0, x0] + \op w30, [x30, x30, sxtx] + \op wzr, [sp, xzr, sxtx #\size32] + \op wzr, [sp, xzr, lsl #0] + .endif + .if \xreg + \op x0, [x0, x0] + \op x30, [x30, w30, uxtw] + \op xzr, [sp, wzr, uxtw #\size64] + \op xzr, [sp, xzr, lsl #\size64] + \op xzr, [sp, wzr, sxtw #\size64] + \op xzr, [sp, xzr, sxtx #\size64] + .endif + .if \simd + ldst_reg_offset_simd \op b 0 + ldst_reg_offset_simd \op h 1 + ldst_reg_offset_simd \op s 2 + ldst_reg_offset_simd \op d 3 + ldst_reg_offset_simd \op q 4 + .endif +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + ldst_reg_offset strb, 1, 0, 0, 0, 0 + ldst_reg_offset ldrb, 1, 0, 0, 0, 0 + ldst_reg_offset ldrsb, 1, 1, 0, 0, 0 + ldst_reg_offset str, 1, 1, 0, 2, 3 + ldst_reg_offset ldr, 1, 1, 0, 2, 3 + ldst_reg_offset strh, 1, 0, 0, 1, 1 + ldst_reg_offset ldrh, 1, 0, 0, 1, 1 + ldst_reg_offset ldrsh, 1, 1, 0, 1, 1 + ldst_reg_offset ldrsw, 0, 1, 0, 2, 2 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-pair.out b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-pair.out new file mode 100755 index 0000000000..54b50cffdf --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-pair.out @@ -0,0 +1,45 @@ + libdis_test: 00 78 00 29 stp w0, w30, [x0] + libdis_test+0x4: 1f 7c 20 29 stp wzr, wzr, [x0, #-256] + libdis_test+0x8: ff fb 1f 29 stp wzr, w30, [sp, #252] + libdis_test+0xc: 00 78 80 28 stp w0, w30, [x0], #0 + libdis_test+0x10: 1f 7c a0 28 stp wzr, wzr, [x0], #-256 + libdis_test+0x14: ff fb 9f 28 stp wzr, w30, [sp], #252 + libdis_test+0x18: 00 78 80 29 stp w0, w30, [x0, #0]! + libdis_test+0x1c: 1f 7c a0 29 stp wzr, wzr, [x0, #-256]! + libdis_test+0x20: ff fb 9f 29 stp wzr, w30, [sp, #252]! + libdis_test+0x24: 00 78 40 29 ldp w0, w30, [x0] + libdis_test+0x28: 1f 7c 60 29 ldp wzr, wzr, [x0, #-256] + libdis_test+0x2c: ff fb 5f 29 ldp wzr, w30, [sp, #252] + libdis_test+0x30: 00 78 c0 28 ldp w0, w30, [x0], #0 + libdis_test+0x34: 1f 7c e0 28 ldp wzr, wzr, [x0], #-256 + libdis_test+0x38: ff fb df 28 ldp wzr, w30, [sp], #252 + libdis_test+0x3c: 00 78 c0 29 ldp w0, w30, [x0, #0]! + libdis_test+0x40: 1f 7c e0 29 ldp wzr, wzr, [x0, #-256]! + libdis_test+0x44: ff fb df 29 ldp wzr, w30, [sp, #252]! + libdis_test+0x48: 00 78 40 69 ldpsw x0, x30, [x0] + libdis_test+0x4c: 1f 7c 60 69 ldpsw xzr, xzr, [x0, #-256] + libdis_test+0x50: ff fb 5f 69 ldpsw xzr, x30, [sp, #252] + libdis_test+0x54: 00 78 c0 68 ldpsw x0, x30, [x0], #0 + libdis_test+0x58: 1f 7c e0 68 ldpsw xzr, xzr, [x0], #-256 + libdis_test+0x5c: ff fb df 68 ldpsw xzr, x30, [sp], #252 + libdis_test+0x60: 00 78 c0 69 ldpsw x0, x30, [x0, #0]! + libdis_test+0x64: 1f 7c e0 69 ldpsw xzr, xzr, [x0, #-256]! + libdis_test+0x68: ff fb df 69 ldpsw xzr, x30, [sp, #252]! + libdis_test+0x6c: 00 78 00 a9 stp x0, x30, [x0] + libdis_test+0x70: 1f 7c 20 a9 stp xzr, xzr, [x0, #-512] + libdis_test+0x74: ff fb 1f a9 stp xzr, x30, [sp, #504] + libdis_test+0x78: 00 78 80 a8 stp x0, x30, [x0], #0 + libdis_test+0x7c: 1f 7c a0 a8 stp xzr, xzr, [x0], #-512 + libdis_test+0x80: ff fb 9f a8 stp xzr, x30, [sp], #504 + libdis_test+0x84: 00 78 80 a9 stp x0, x30, [x0, #0]! + libdis_test+0x88: 1f 7c a0 a9 stp xzr, xzr, [x0, #-512]! + libdis_test+0x8c: ff fb 9f a9 stp xzr, x30, [sp, #504]! + libdis_test+0x90: 00 78 40 a9 ldp x0, x30, [x0] + libdis_test+0x94: 1f 7c 60 a9 ldp xzr, xzr, [x0, #-512] + libdis_test+0x98: ff fb 5f a9 ldp xzr, x30, [sp, #504] + libdis_test+0x9c: 00 78 c0 a8 ldp x0, x30, [x0], #0 + libdis_test+0xa0: 1f 7c e0 a8 ldp xzr, xzr, [x0], #-512 + libdis_test+0xa4: ff fb df a8 ldp xzr, x30, [sp], #504 + libdis_test+0xa8: 00 78 c0 a9 ldp x0, x30, [x0, #0]! + libdis_test+0xac: 1f 7c e0 a9 ldp xzr, xzr, [x0, #-512]! + libdis_test+0xb0: ff fb df a9 ldp xzr, x30, [sp, #504]! diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-pair.s b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-pair.s new file mode 100755 index 0000000000..7bee080fb8 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-pair.s @@ -0,0 +1,70 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.3.14 Load/store register pair (offset) + * C3.3.15 Load/store register pair (post-indexed) + * C3.3.16 Load/store register pair (pre-indexed) + * + * Test the minimum/maximum values for both registers and immediates. + */ + +.macro ldst_reg_pair_32 op + \op w0, w30, [x0] + \op wzr, wzr, [x0, #-256] + \op wzr, w30, [sp, #252] + \op w0, w30, [x0], #0 + \op wzr, wzr, [x0], #-256 + \op wzr, w30, [sp], #252 + \op w0, w30, [x0, #0]! + \op wzr, wzr, [x0, #-256]! + \op wzr, w30, [sp, #252]! +.endm + +.macro ldst_reg_pair_64 op, multi=2 + \op x0, x30, [x0] + \op xzr, xzr, [x0, #(-256*\multi)] + \op xzr, x30, [sp, #(252*\multi)] + \op x0, x30, [x0], #0 + \op xzr, xzr, [x0], #(-256*\multi) + \op xzr, x30, [sp], #(252*\multi) + \op x0, x30, [x0, #0]! + \op xzr, xzr, [x0, #(-256*\multi)]! + \op xzr, x30, [sp, #(252*\multi)]! +.endm + +.macro ldst_reg_pair_simd_multi op, reg, multi + \op \reg\()0, \reg\()0, [x0] + \op \reg\()31, \reg\()30, [x0, #(-256*\multi)] + \op \reg\()30, \reg\()31, [sp, #(252*\multi)] + \op \reg\()0, \reg\()0, [x0], #0 + \op \reg\()31, \reg\()30, [x0], #(-256*\multi) + \op \reg\()30, \reg\()31, [sp], #(252*\multi) + \op \reg\()0, \reg\()0, [x0, #0]! + \op \reg\()31, \reg\()30, [x0, #(-256*\multi)]! + \op \reg\()30, \reg\()31, [sp, #(252*\multi)]! +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + ldst_reg_pair_32 stp + ldst_reg_pair_32 ldp + + ldst_reg_pair_64 ldpsw 1 + ldst_reg_pair_64 stp + ldst_reg_pair_64 ldp +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unpriv.out b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unpriv.out new file mode 100755 index 0000000000..217bc1e7f8 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unpriv.out @@ -0,0 +1,44 @@ + libdis_test: 00 08 00 38 sttrb w0, [x0] + libdis_test+0x4: ff fb 1f 38 sttrb wzr, [sp, #-1] + libdis_test+0x8: de 0b 10 38 sttrb w30, [x30, #-256] + libdis_test+0xc: ff fb 0f 38 sttrb wzr, [sp, #255] + libdis_test+0x10: 00 08 40 38 ldtrb w0, [x0] + libdis_test+0x14: ff fb 5f 38 ldtrb wzr, [sp, #-1] + libdis_test+0x18: de 0b 50 38 ldtrb w30, [x30, #-256] + libdis_test+0x1c: ff fb 4f 38 ldtrb wzr, [sp, #255] + libdis_test+0x20: 00 08 c0 38 ldtrsb w0, [x0] + libdis_test+0x24: ff fb df 38 ldtrsb wzr, [sp, #-1] + libdis_test+0x28: de 0b d0 38 ldtrsb w30, [x30, #-256] + libdis_test+0x2c: ff fb cf 38 ldtrsb wzr, [sp, #255] + libdis_test+0x30: 00 08 80 38 ldtrsb x0, [x0] + libdis_test+0x34: ff fb 9f 38 ldtrsb xzr, [sp, #-1] + libdis_test+0x38: de 0b 90 38 ldtrsb x30, [x30, #-256] + libdis_test+0x3c: ff fb 8f 38 ldtrsb xzr, [sp, #255] + libdis_test+0x40: 00 08 00 78 sttrh w0, [x0] + libdis_test+0x44: ff fb 1f 78 sttrh wzr, [sp, #-1] + libdis_test+0x48: de 0b 10 78 sttrh w30, [x30, #-256] + libdis_test+0x4c: ff fb 0f 78 sttrh wzr, [sp, #255] + libdis_test+0x50: 00 08 40 78 ldtrh w0, [x0] + libdis_test+0x54: ff fb 5f 78 ldtrh wzr, [sp, #-1] + libdis_test+0x58: de 0b 50 78 ldtrh w30, [x30, #-256] + libdis_test+0x5c: ff fb 4f 78 ldtrh wzr, [sp, #255] + libdis_test+0x60: 00 08 c0 78 ldtrsh w0, [x0] + libdis_test+0x64: ff fb df 78 ldtrsh wzr, [sp, #-1] + libdis_test+0x68: de 0b d0 78 ldtrsh w30, [x30, #-256] + libdis_test+0x6c: ff fb cf 78 ldtrsh wzr, [sp, #255] + libdis_test+0x70: 00 08 80 78 ldtrsh x0, [x0] + libdis_test+0x74: ff fb 9f 78 ldtrsh xzr, [sp, #-1] + libdis_test+0x78: de 0b 90 78 ldtrsh x30, [x30, #-256] + libdis_test+0x7c: ff fb 8f 78 ldtrsh xzr, [sp, #255] + libdis_test+0x80: 00 08 00 b8 sttr w0, [x0] + libdis_test+0x84: ff fb 1f b8 sttr wzr, [sp, #-1] + libdis_test+0x88: de 0b 10 b8 sttr w30, [x30, #-256] + libdis_test+0x8c: ff fb 0f b8 sttr wzr, [sp, #255] + libdis_test+0x90: 00 08 40 b8 ldtr w0, [x0] + libdis_test+0x94: ff fb 5f b8 ldtr wzr, [sp, #-1] + libdis_test+0x98: de 0b 50 b8 ldtr w30, [x30, #-256] + libdis_test+0x9c: ff fb 4f b8 ldtr wzr, [sp, #255] + libdis_test+0xa0: 00 08 80 b8 ldtrsw x0, [x0] + libdis_test+0xa4: ff fb 9f b8 ldtrsw xzr, [sp, #-1] + libdis_test+0xa8: de 0b 90 b8 ldtrsw x30, [x30, #-256] + libdis_test+0xac: ff fb 8f b8 ldtrsw xzr, [sp, #255] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unpriv.s b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unpriv.s new file mode 100755 index 0000000000..250a7c6eb8 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unpriv.s @@ -0,0 +1,57 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.3.11 Load/store register (unprivileged) + * + * STTRB <Wt>, [<Xn|SP>{, #<simm>}] + * LDTRB <Wt>, [<Xn|SP>{, #<simm>}] + * LDTRSB <Rt>, [<Xn|SP>{, #<simm>}] + * STTRH <Wt>, [<Xn|SP>{, #<simm>}] + * LDTRH <Wt>, [<Xn|SP>{, #<simm>}] + * LDTRSH <Rt>, [<Xn|SP>{, #<simm>}] + * STTR <Rt>, [<Xn|SP>{, #<simm>}] + * LDTR <Rt>, [<Xn|SP>{, #<simm>}] + * LDTRSW <Xt>, [<Xn|SP>{, #<simm>}] + */ +.macro ldst_reg_unpriv op, wreg=0, xreg=0 + .if \wreg + \op w0, [x0] + \op wzr, [sp, #-1] + \op w30, [x30, #-256] + \op wzr, [sp, #255] + .endif + .if \xreg + \op x0, [x0] + \op xzr, [sp, #-1] + \op x30, [x30, #-256] + \op xzr, [sp, #255] + .endif +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + ldst_reg_unpriv sttrb 1 + ldst_reg_unpriv ldtrb 1 + ldst_reg_unpriv ldtrsb 1 1 + ldst_reg_unpriv sttrh 1 + ldst_reg_unpriv ldtrh 1 + ldst_reg_unpriv ldtrsh 1 1 + ldst_reg_unpriv sttr 1 + ldst_reg_unpriv ldtr 1 + ldst_reg_unpriv ldtrsw 0 1 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unscaled.out b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unscaled.out new file mode 100755 index 0000000000..c5f640d84d --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unscaled.out @@ -0,0 +1,60 @@ + libdis_test: 00 00 00 38 sturb w0, [x0] + libdis_test+0x4: ff f3 1f 38 sturb wzr, [sp, #-1] + libdis_test+0x8: de 03 10 38 sturb w30, [x30, #-256] + libdis_test+0xc: ff f3 0f 38 sturb wzr, [sp, #255] + libdis_test+0x10: 00 00 40 38 ldurb w0, [x0] + libdis_test+0x14: ff f3 5f 38 ldurb wzr, [sp, #-1] + libdis_test+0x18: de 03 50 38 ldurb w30, [x30, #-256] + libdis_test+0x1c: ff f3 4f 38 ldurb wzr, [sp, #255] + libdis_test+0x20: 00 00 c0 38 ldursb w0, [x0] + libdis_test+0x24: ff f3 df 38 ldursb wzr, [sp, #-1] + libdis_test+0x28: de 03 d0 38 ldursb w30, [x30, #-256] + libdis_test+0x2c: ff f3 cf 38 ldursb wzr, [sp, #255] + libdis_test+0x30: 00 00 80 38 ldursb x0, [x0] + libdis_test+0x34: ff f3 9f 38 ldursb xzr, [sp, #-1] + libdis_test+0x38: de 03 90 38 ldursb x30, [x30, #-256] + libdis_test+0x3c: ff f3 8f 38 ldursb xzr, [sp, #255] + libdis_test+0x40: 00 00 00 b8 stur w0, [x0] + libdis_test+0x44: ff f3 1f b8 stur wzr, [sp, #-1] + libdis_test+0x48: de 03 10 b8 stur w30, [x30, #-256] + libdis_test+0x4c: ff f3 0f b8 stur wzr, [sp, #255] + libdis_test+0x50: 00 00 00 f8 stur x0, [x0] + libdis_test+0x54: ff f3 1f f8 stur xzr, [sp, #-1] + libdis_test+0x58: de 03 10 f8 stur x30, [x30, #-256] + libdis_test+0x5c: ff f3 0f f8 stur xzr, [sp, #255] + libdis_test+0x60: 00 00 40 b8 ldur w0, [x0] + libdis_test+0x64: ff f3 5f b8 ldur wzr, [sp, #-1] + libdis_test+0x68: de 03 50 b8 ldur w30, [x30, #-256] + libdis_test+0x6c: ff f3 4f b8 ldur wzr, [sp, #255] + libdis_test+0x70: 00 00 40 f8 ldur x0, [x0] + libdis_test+0x74: ff f3 5f f8 ldur xzr, [sp, #-1] + libdis_test+0x78: de 03 50 f8 ldur x30, [x30, #-256] + libdis_test+0x7c: ff f3 4f f8 ldur xzr, [sp, #255] + libdis_test+0x80: 00 00 00 78 sturh w0, [x0] + libdis_test+0x84: ff f3 1f 78 sturh wzr, [sp, #-1] + libdis_test+0x88: de 03 10 78 sturh w30, [x30, #-256] + libdis_test+0x8c: ff f3 0f 78 sturh wzr, [sp, #255] + libdis_test+0x90: 00 00 40 78 ldurh w0, [x0] + libdis_test+0x94: ff f3 5f 78 ldurh wzr, [sp, #-1] + libdis_test+0x98: de 03 50 78 ldurh w30, [x30, #-256] + libdis_test+0x9c: ff f3 4f 78 ldurh wzr, [sp, #255] + libdis_test+0xa0: 00 00 c0 78 ldursh w0, [x0] + libdis_test+0xa4: ff f3 df 78 ldursh wzr, [sp, #-1] + libdis_test+0xa8: de 03 d0 78 ldursh w30, [x30, #-256] + libdis_test+0xac: ff f3 cf 78 ldursh wzr, [sp, #255] + libdis_test+0xb0: 00 00 80 78 ldursh x0, [x0] + libdis_test+0xb4: ff f3 9f 78 ldursh xzr, [sp, #-1] + libdis_test+0xb8: de 03 90 78 ldursh x30, [x30, #-256] + libdis_test+0xbc: ff f3 8f 78 ldursh xzr, [sp, #255] + libdis_test+0xc0: 00 00 00 b8 stur w0, [x0] + libdis_test+0xc4: ff f3 1f b8 stur wzr, [sp, #-1] + libdis_test+0xc8: de 03 10 b8 stur w30, [x30, #-256] + libdis_test+0xcc: ff f3 0f b8 stur wzr, [sp, #255] + libdis_test+0xd0: 00 00 40 b8 ldur w0, [x0] + libdis_test+0xd4: ff f3 5f b8 ldur wzr, [sp, #-1] + libdis_test+0xd8: de 03 50 b8 ldur w30, [x30, #-256] + libdis_test+0xdc: ff f3 4f b8 ldur wzr, [sp, #255] + libdis_test+0xe0: 00 00 80 b8 ldursw x0, [x0] + libdis_test+0xe4: ff f3 9f b8 ldursw xzr, [sp, #-1] + libdis_test+0xe8: de 03 90 b8 ldursw x30, [x30, #-256] + libdis_test+0xec: ff f3 8f b8 ldursw xzr, [sp, #255] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unscaled.s b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unscaled.s new file mode 100755 index 0000000000..6d823d9383 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unscaled.s @@ -0,0 +1,66 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.3.12 Load/store register (unscaled immediate) + * + * STTRB <Wt>, [<Xn|SP>{, #<simm>}] + * LDTRB <Wt>, [<Xn|SP>{, #<simm>}] + * LDTRSB <Rt>, [<Xn|SP>{, #<simm>}] + * STTRH <Wt>, [<Xn|SP>{, #<simm>}] + * LDTRH <Wt>, [<Xn|SP>{, #<simm>}] + * LDTRSH <Rt>, [<Xn|SP>{, #<simm>}] + * STTR <Rt>, [<Xn|SP>{, #<simm>}] + * LDTR <Rt>, [<Xn|SP>{, #<simm>}] + * LDTRSW <Xt>, [<Xn|SP>{, #<simm>}] + */ +.macro ldst_reg_unpriv op, wreg=0, xreg=0 simd=0 + .if \wreg + \op w0, [x0] + \op wzr, [sp, #-1] + \op w30, [x30, #-256] + \op wzr, [sp, #255] + .endif + .if \xreg + \op x0, [x0] + \op xzr, [sp, #-1] + \op x30, [x30, #-256] + \op xzr, [sp, #255] + .endif + .if \simd + \op b0, [x0] + \op h31, [sp, #0] + \op s0, [x0, #-1] + \op d31, [sp, #-256] + \op q0, [x0, #255] + .endif +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + ldst_reg_unpriv sturb 1 + ldst_reg_unpriv ldurb 1 + ldst_reg_unpriv ldursb 1 1 + ldst_reg_unpriv stur 1 1 + ldst_reg_unpriv ldur 1 1 + ldst_reg_unpriv sturh 1 + ldst_reg_unpriv ldurh 1 + ldst_reg_unpriv ldursh 1 1 + ldst_reg_unpriv stur 1 + ldst_reg_unpriv ldur 1 + ldst_reg_unpriv ldursw 0 1 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unsigned.out b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unsigned.out new file mode 100755 index 0000000000..6581b86a72 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unsigned.out @@ -0,0 +1,26 @@ + libdis_test: 00 00 00 39 strb w0, [x0] + libdis_test+0x4: ff ff 3f 39 strb wzr, [sp, #4095] + libdis_test+0x8: 00 00 40 39 ldrb w0, [x0] + libdis_test+0xc: ff ff 7f 39 ldrb wzr, [sp, #4095] + libdis_test+0x10: 00 00 80 39 ldrsb x0, [x0] + libdis_test+0x14: ff ff bf 39 ldrsb xzr, [sp, #4095] + libdis_test+0x18: 00 00 c0 39 ldrsb w0, [x0] + libdis_test+0x1c: ff ff ff 39 ldrsb wzr, [sp, #4095] + libdis_test+0x20: 00 00 00 79 strh w0, [x0] + libdis_test+0x24: ff ff 3f 79 strh wzr, [sp, #8190] + libdis_test+0x28: 00 00 40 79 ldrh w0, [x0] + libdis_test+0x2c: ff ff 7f 79 ldrh wzr, [sp, #8190] + libdis_test+0x30: 00 00 80 79 ldrsh x0, [x0] + libdis_test+0x34: ff ff bf 79 ldrsh xzr, [sp, #8190] + libdis_test+0x38: 00 00 c0 79 ldrsh w0, [x0] + libdis_test+0x3c: ff ff ff 79 ldrsh wzr, [sp, #8190] + libdis_test+0x40: 00 00 00 b9 str w0, [x0] + libdis_test+0x44: ff ff 3f b9 str wzr, [sp, #16380] + libdis_test+0x48: 00 00 40 b9 ldr w0, [x0] + libdis_test+0x4c: ff ff 7f b9 ldr wzr, [sp, #16380] + libdis_test+0x50: 00 00 80 b9 ldrsw x0, [x0] + libdis_test+0x54: ff ff bf b9 ldrsw xzr, [sp, #16380] + libdis_test+0x58: 00 00 00 f9 str x0, [x0] + libdis_test+0x5c: ff ff 3f f9 str xzr, [sp, #32760] + libdis_test+0x60: 00 00 40 f9 ldr x0, [x0] + libdis_test+0x64: ff ff 7f f9 ldr xzr, [sp, #32760] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unsigned.s b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unsigned.s new file mode 100755 index 0000000000..c74a06ec94 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.ldst-reg-unsigned.s @@ -0,0 +1,63 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.3.13 Load/store register (unsigned immediate) + * + * C5.6.143 PRFM is part of this group but is tested in tst.ldst-prfm.s + * + * Test the minimum/maximum values for both registers and unsigned immediates. + */ +.macro ldst_reg_unsigned_32 op, mult=1 + \op w0, [x0] + \op wzr, [sp, #(4095*\mult)] +.endm + +.macro ldst_reg_unsigned_64 op, mult=1 + \op x0, [x0] + \op xzr, [sp, #(4095*\mult)] +.endm + +.macro ldst_reg_unsigned_simd op + \op b0, [x0] + \op b31, [sp, #4095] + \op h0, [x0] + \op h31, [sp, #8190] + \op s0, [x0] + \op s31, [sp, #16380] + \op d0, [x0] + \op d31, [sp, #32760] + \op q0, [x0] + \op q31, [sp, #65520] +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + ldst_reg_unsigned_32 strb + ldst_reg_unsigned_32 ldrb + ldst_reg_unsigned_64 ldrsb + ldst_reg_unsigned_32 ldrsb + ldst_reg_unsigned_32 strh 2 + ldst_reg_unsigned_32 ldrh 2 + ldst_reg_unsigned_64 ldrsh 2 + ldst_reg_unsigned_32 ldrsh 2 + ldst_reg_unsigned_32 str 4 + ldst_reg_unsigned_32 ldr 4 + ldst_reg_unsigned_64 ldrsw 4 + ldst_reg_unsigned_64 str 8 + ldst_reg_unsigned_64 ldr 8 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.load-store.out b/usr/src/test/util-tests/tests/dis/arm64/tst.load-store.out new file mode 100644 index 0000000000..35fbb8dd18 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.load-store.out @@ -0,0 +1,19 @@ + libdis_test: 5f 02 00 18 ldr wzr, +0x48 <libdis_test+0x48> + libdis_test+0x4: 29 02 00 58 ldr x9, +0x44 <libdis_test+0x48> + libdis_test+0x8: 1f 02 00 98 ldrsw xzr, +0x40 <libdis_test+0x48> + libdis_test+0xc: f3 01 00 98 ldrsw x19, +0x3c <libdis_test+0x48> + libdis_test+0x10: cf 01 00 d8 prfm #0xf, +0x38 <libdis_test+0x48> + libdis_test+0x14: 29 29 82 29 stp w9, w10, [x9, #16]! + libdis_test+0x18: 61 88 c1 29 ldp w1, w2, [x3, #12]! + libdis_test+0x1c: ea 7f c1 69 ldpsw x10, xzr, [sp, #8]! + libdis_test+0x20: e9 37 81 a8 stp x9, x13, [sp], #16 + libdis_test+0x24: 6f aa ff a8 ldp x15, x10, [x19], #-8 + libdis_test+0x28: ea ff c1 68 ldpsw x10, xzr, [sp], #12 + libdis_test+0x2c: e9 37 00 a9 stp x9, x13, [sp] + libdis_test+0x30: e8 93 43 29 ldp w8, w4, [sp, #28] + libdis_test+0x34: e1 7f 7e 69 ldpsw x1, xzr, [sp, #-16] + libdis_test+0x38: 20 91 7f 28 ldnp w0, w4, [x9, #-4] + libdis_test+0x3c: ea 4f 40 a8 ldnp x10, x19, [sp] + libdis_test+0x40: e9 43 03 28 stnp w9, w16, [sp, #24] + libdis_test+0x44: 6a 86 00 a8 stnp x10, x1, [x19, #8] + libdis_test+0x48: 00 00 00 8b add x0, x0, x0 diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.load-store.s b/usr/src/test/util-tests/tests/dis/arm64/tst.load-store.s new file mode 100644 index 0000000000..16d59ea3ab --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.load-store.s @@ -0,0 +1,55 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * Test Data - Immediate group dissassembly + */ + +.text +.align 16 +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* Load Register - literal */ + LDR WZR, PC_TARGET + LDR X9, PC_TARGET + LDRSW XZR, PC_TARGET + LDRSW X19, PC_TARGET + PRFM #0xf, PC_TARGET + + /* Pre-Index */ + STP W9, W10, [X9, #16]! + LDP W1, W2, [X3, #12]! + LDPSW X10, XZR, [SP, #8]! + + /* Post-Index */ + STP X9, X13, [SP], #16 + LDP X15, X10, [X19], #-8 + LDPSW X10, XZR, [SP], #12 + + /* Signed offset */ + STP X9, X13, [SP] + LDP W8, W4, [SP, #28] + LDPSW X1, XZR, [SP, #-16] + + /* Load/store no-allocate pair (offset) */ + LDNP W0, W4, [X9, #-4] + LDNP X10, X19, [SP] + STNP W9, W16, [SP, #24] + STNP X10, X1, [X19, #8] + + PC_TARGET: ADD X0, X0, X0 + +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.logical-imm.out b/usr/src/test/util-tests/tests/dis/arm64/tst.logical-imm.out new file mode 100755 index 0000000000..32117cc093 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.logical-imm.out @@ -0,0 +1,32 @@ + libdis_test: c0 03 00 12 and w0, w30, #0x1 + libdis_test+0x4: c0 7b 00 12 and w0, w30, #0x7fffffff + libdis_test+0x8: c0 03 40 92 and x0, x30, #0x1 + libdis_test+0xc: c0 7f 40 92 and x0, x30, #0xffffffff + libdis_test+0x10: ff 03 00 12 and wsp, wzr, #0x1 + libdis_test+0x14: ff 7b 00 12 and wsp, wzr, #0x7fffffff + libdis_test+0x18: ff 03 40 92 and sp, xzr, #0x1 + libdis_test+0x1c: ff 7f 40 92 and sp, xzr, #0xffffffff + libdis_test+0x20: c0 03 00 32 orr w0, w30, #0x1 + libdis_test+0x24: c0 7b 00 32 orr w0, w30, #0x7fffffff + libdis_test+0x28: c0 03 40 b2 orr x0, x30, #0x1 + libdis_test+0x2c: c0 7f 40 b2 orr x0, x30, #0xffffffff + libdis_test+0x30: ff 03 00 32 orr wsp, wzr, #0x1 + libdis_test+0x34: ff 7b 00 32 orr wsp, wzr, #0x7fffffff + libdis_test+0x38: ff 03 40 b2 orr sp, xzr, #0x1 + libdis_test+0x3c: ff 7f 40 b2 orr sp, xzr, #0xffffffff + libdis_test+0x40: c0 03 00 52 eor w0, w30, #0x1 + libdis_test+0x44: c0 7b 00 52 eor w0, w30, #0x7fffffff + libdis_test+0x48: c0 03 40 d2 eor x0, x30, #0x1 + libdis_test+0x4c: c0 7f 40 d2 eor x0, x30, #0xffffffff + libdis_test+0x50: ff 03 00 52 eor wsp, wzr, #0x1 + libdis_test+0x54: ff 7b 00 52 eor wsp, wzr, #0x7fffffff + libdis_test+0x58: ff 03 40 d2 eor sp, xzr, #0x1 + libdis_test+0x5c: ff 7f 40 d2 eor sp, xzr, #0xffffffff + libdis_test+0x60: c0 03 00 72 ands w0, w30, #0x1 + libdis_test+0x64: c0 7b 00 72 ands w0, w30, #0x7fffffff + libdis_test+0x68: c0 03 40 f2 ands x0, x30, #0x1 + libdis_test+0x6c: c0 7f 40 f2 ands x0, x30, #0xffffffff + libdis_test+0x70: ff 03 00 72 ands wzr, wzr, #0x1 + libdis_test+0x74: ff 7b 00 72 ands wzr, wzr, #0x7fffffff + libdis_test+0x78: ff 03 40 f2 ands xzr, xzr, #0x1 + libdis_test+0x7c: ff 7f 40 f2 ands xzr, xzr, #0xffffffff diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.logical-imm.s b/usr/src/test/util-tests/tests/dis/arm64/tst.logical-imm.s new file mode 100755 index 0000000000..43f8d41c86 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.logical-imm.s @@ -0,0 +1,59 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.4.4 Logical (immediate) + */ +.macro logical_imm op zreg=0 + \op w0, w30, #0x00000001 + \op w0, w30, #0x7fffffff + \op x0, x30, #0x00000001 + \op x0, x30, #0xffffffff + .if \zreg + \op wzr, wzr, #0x00000001 + \op wzr, wzr, #0x7fffffff + \op xzr, xzr, #0x00000001 + \op xzr, xzr, #0xffffffff + .else + \op wsp, wzr, #0x00000001 + \op wsp, wzr, #0x7fffffff + \op sp, xzr, #0x00000001 + \op sp, xzr, #0xffffffff + .endif +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * C5.6.11 AND (immediate) + */ + logical_imm and + /* + * C5.6.141 ORR (immediate) + * C5.6.124 MOV (bitmask immediate) (alias) + */ + logical_imm orr + /* + * C5.6.64 EOR (immediate) + */ + logical_imm eor + /* + * C5.6.13 ANDS (immediate) + * C5.6.209 TST (immediate) (alias) + */ + logical_imm ands 1 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.logical-shiftreg.out b/usr/src/test/util-tests/tests/dis/arm64/tst.logical-shiftreg.out new file mode 100755 index 0000000000..6ab2b0044b --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.logical-shiftreg.out @@ -0,0 +1,80 @@ + libdis_test: e0 01 1e 0a and w0, w15, w30 + libdis_test+0x4: ff 01 1e 0a and wzr, w15, w30 + libdis_test+0x8: e0 7f 5e 0a and w0, wzr, w30, lsr #31 + libdis_test+0xc: e0 01 9f 0a and w0, w15, wzr + libdis_test+0x10: ff 7f df 0a and wzr, wzr, wzr, ror #31 + libdis_test+0x14: e0 01 1e 8a and x0, x15, x30 + libdis_test+0x18: ff 01 1e 8a and xzr, x15, x30 + libdis_test+0x1c: e0 ff 5e 8a and x0, xzr, x30, lsr #63 + libdis_test+0x20: e0 01 9f 8a and x0, x15, xzr + libdis_test+0x24: ff ff df 8a and xzr, xzr, xzr, ror #63 + libdis_test+0x28: e0 01 3e 0a bic w0, w15, w30 + libdis_test+0x2c: ff 01 3e 0a bic wzr, w15, w30 + libdis_test+0x30: e0 7f 7e 0a bic w0, wzr, w30, lsr #31 + libdis_test+0x34: e0 01 bf 0a bic w0, w15, wzr + libdis_test+0x38: ff 7f ff 0a bic wzr, wzr, wzr, ror #31 + libdis_test+0x3c: e0 01 3e 8a bic x0, x15, x30 + libdis_test+0x40: ff 01 3e 8a bic xzr, x15, x30 + libdis_test+0x44: e0 ff 7e 8a bic x0, xzr, x30, lsr #63 + libdis_test+0x48: e0 01 bf 8a bic x0, x15, xzr + libdis_test+0x4c: ff ff ff 8a bic xzr, xzr, xzr, ror #63 + libdis_test+0x50: e0 01 1e 2a orr w0, w15, w30 + libdis_test+0x54: ff 01 1e 2a orr wzr, w15, w30 + libdis_test+0x58: e0 7f 5e 2a orr w0, wzr, w30, lsr #31 + libdis_test+0x5c: e0 01 9f 2a orr w0, w15, wzr + libdis_test+0x60: ff 7f df 2a orr wzr, wzr, wzr, ror #31 + libdis_test+0x64: e0 01 1e aa orr x0, x15, x30 + libdis_test+0x68: ff 01 1e aa orr xzr, x15, x30 + libdis_test+0x6c: e0 ff 5e aa orr x0, xzr, x30, lsr #63 + libdis_test+0x70: e0 01 9f aa orr x0, x15, xzr + libdis_test+0x74: ff ff df aa orr xzr, xzr, xzr, ror #63 + libdis_test+0x78: e0 01 3e 2a orn w0, w15, w30 + libdis_test+0x7c: ff 01 3e 2a orn wzr, w15, w30 + libdis_test+0x80: e0 7f 7e 2a orn w0, wzr, w30, lsr #31 + libdis_test+0x84: e0 01 bf 2a orn w0, w15, wzr + libdis_test+0x88: ff 7f ff 2a orn wzr, wzr, wzr, ror #31 + libdis_test+0x8c: e0 01 3e aa orn x0, x15, x30 + libdis_test+0x90: ff 01 3e aa orn xzr, x15, x30 + libdis_test+0x94: e0 ff 7e aa orn x0, xzr, x30, lsr #63 + libdis_test+0x98: e0 01 bf aa orn x0, x15, xzr + libdis_test+0x9c: ff ff ff aa orn xzr, xzr, xzr, ror #63 + libdis_test+0xa0: e0 01 1e 4a eor w0, w15, w30 + libdis_test+0xa4: ff 01 1e 4a eor wzr, w15, w30 + libdis_test+0xa8: e0 7f 5e 4a eor w0, wzr, w30, lsr #31 + libdis_test+0xac: e0 01 9f 4a eor w0, w15, wzr + libdis_test+0xb0: ff 7f df 4a eor wzr, wzr, wzr, ror #31 + libdis_test+0xb4: e0 01 1e ca eor x0, x15, x30 + libdis_test+0xb8: ff 01 1e ca eor xzr, x15, x30 + libdis_test+0xbc: e0 ff 5e ca eor x0, xzr, x30, lsr #63 + libdis_test+0xc0: e0 01 9f ca eor x0, x15, xzr + libdis_test+0xc4: ff ff df ca eor xzr, xzr, xzr, ror #63 + libdis_test+0xc8: e0 01 3e 4a eon w0, w15, w30 + libdis_test+0xcc: ff 01 3e 4a eon wzr, w15, w30 + libdis_test+0xd0: e0 7f 7e 4a eon w0, wzr, w30, lsr #31 + libdis_test+0xd4: e0 01 bf 4a eon w0, w15, wzr + libdis_test+0xd8: ff 7f ff 4a eon wzr, wzr, wzr, ror #31 + libdis_test+0xdc: e0 01 3e ca eon x0, x15, x30 + libdis_test+0xe0: ff 01 3e ca eon xzr, x15, x30 + libdis_test+0xe4: e0 ff 7e ca eon x0, xzr, x30, lsr #63 + libdis_test+0xe8: e0 01 bf ca eon x0, x15, xzr + libdis_test+0xec: ff ff ff ca eon xzr, xzr, xzr, ror #63 + libdis_test+0xf0: e0 01 1e 6a ands w0, w15, w30 + libdis_test+0xf4: ff 01 1e 6a ands wzr, w15, w30 + libdis_test+0xf8: e0 7f 5e 6a ands w0, wzr, w30, lsr #31 + libdis_test+0xfc: e0 01 9f 6a ands w0, w15, wzr + libdis_test+0x100: ff 7f df 6a ands wzr, wzr, wzr, ror #31 + libdis_test+0x104: e0 01 1e ea ands x0, x15, x30 + libdis_test+0x108: ff 01 1e ea ands xzr, x15, x30 + libdis_test+0x10c: e0 ff 5e ea ands x0, xzr, x30, lsr #63 + libdis_test+0x110: e0 01 9f ea ands x0, x15, xzr + libdis_test+0x114: ff ff df ea ands xzr, xzr, xzr, ror #63 + libdis_test+0x118: e0 01 3e 6a bics w0, w15, w30 + libdis_test+0x11c: ff 01 3e 6a bics wzr, w15, w30 + libdis_test+0x120: e0 7f 7e 6a bics w0, wzr, w30, lsr #31 + libdis_test+0x124: e0 01 bf 6a bics w0, w15, wzr + libdis_test+0x128: ff 7f ff 6a bics wzr, wzr, wzr, ror #31 + libdis_test+0x12c: e0 01 3e ea bics x0, x15, x30 + libdis_test+0x130: ff 01 3e ea bics xzr, x15, x30 + libdis_test+0x134: e0 ff 7e ea bics x0, xzr, x30, lsr #63 + libdis_test+0x138: e0 01 bf ea bics x0, x15, xzr + libdis_test+0x13c: ff ff ff ea bics xzr, xzr, xzr, ror #63 diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.logical-shiftreg.s b/usr/src/test/util-tests/tests/dis/arm64/tst.logical-shiftreg.s new file mode 100755 index 0000000000..05316a5008 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.logical-shiftreg.s @@ -0,0 +1,71 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.5.10 Logical (shifted register) + */ +.macro logical_shift op zreg=0 + \op w0, w15, w30 + \op wzr, w15, w30, lsl #0 + \op w0, wzr, w30, lsr #31 + \op w0, w15, wzr, asr #0 + \op wzr, wzr, wzr, ror #31 + \op x0, x15, x30 + \op xzr, x15, x30, lsl #0 + \op x0, xzr, x30, lsr #63 + \op x0, x15, xzr, asr #0 + \op xzr, xzr, xzr, ror #63 +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * C5.6.11 AND (shifted register) + */ + logical_shift and + /* + * C5.6.24 BIC (shifted register) + */ + logical_shift bic + /* + * C5.6.142 ORR (shifted register) + * C5.6.125 MOV (register) + */ + logical_shift orr + /* + * C5.6.140 ORN (shifted register) + * C5.6.134 MVN + */ + logical_shift orn + /* + * C5.6.65 EOR (shifted register) + */ + logical_shift eor + /* + * C5.6.63 EON (shifted register) + */ + logical_shift eon + /* + * C5.6.14 ANDS (shifted register) + * C5.6.210 TST (shifted register) + */ + logical_shift ands + /* + * C5.6.25 BICS (shifted register) + */ + logical_shift bics +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.movwide-imm.out b/usr/src/test/util-tests/tests/dis/arm64/tst.movwide-imm.out new file mode 100755 index 0000000000..604ff3afbb --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.movwide-imm.out @@ -0,0 +1,48 @@ + libdis_test: 00 00 80 12 movn w0, #0x0 + libdis_test+0x4: 00 00 80 12 movn w0, #0x0 + libdis_test+0x8: 00 00 a0 12 movn w0, #0x0, lsl #16 + libdis_test+0xc: 00 00 80 92 movn x0, #0x0 + libdis_test+0x10: 00 00 80 92 movn x0, #0x0 + libdis_test+0x14: 00 00 a0 92 movn x0, #0x0, lsl #16 + libdis_test+0x18: 00 00 c0 92 movn x0, #0x0, lsl #32 + libdis_test+0x1c: 00 00 e0 92 movn x0, #0x0, lsl #48 + libdis_test+0x20: e0 ff 9f 12 movn w0, #0xffff + libdis_test+0x24: e0 ff 9f 12 movn w0, #0xffff + libdis_test+0x28: e0 ff bf 12 movn w0, #0xffff, lsl #16 + libdis_test+0x2c: e0 ff 9f 92 movn x0, #0xffff + libdis_test+0x30: e0 ff 9f 92 movn x0, #0xffff + libdis_test+0x34: e0 ff bf 92 movn x0, #0xffff, lsl #16 + libdis_test+0x38: e0 ff df 92 movn x0, #0xffff, lsl #32 + libdis_test+0x3c: e0 ff ff 92 movn x0, #0xffff, lsl #48 + libdis_test+0x40: 00 00 80 52 movz w0, #0x0 + libdis_test+0x44: 00 00 80 52 movz w0, #0x0 + libdis_test+0x48: 00 00 a0 52 movz w0, #0x0, lsl #16 + libdis_test+0x4c: 00 00 80 d2 movz x0, #0x0 + libdis_test+0x50: 00 00 80 d2 movz x0, #0x0 + libdis_test+0x54: 00 00 a0 d2 movz x0, #0x0, lsl #16 + libdis_test+0x58: 00 00 c0 d2 movz x0, #0x0, lsl #32 + libdis_test+0x5c: 00 00 e0 d2 movz x0, #0x0, lsl #48 + libdis_test+0x60: e0 ff 9f 52 movz w0, #0xffff + libdis_test+0x64: e0 ff 9f 52 movz w0, #0xffff + libdis_test+0x68: e0 ff bf 52 movz w0, #0xffff, lsl #16 + libdis_test+0x6c: e0 ff 9f d2 movz x0, #0xffff + libdis_test+0x70: e0 ff 9f d2 movz x0, #0xffff + libdis_test+0x74: e0 ff bf d2 movz x0, #0xffff, lsl #16 + libdis_test+0x78: e0 ff df d2 movz x0, #0xffff, lsl #32 + libdis_test+0x7c: e0 ff ff d2 movz x0, #0xffff, lsl #48 + libdis_test+0x80: 00 00 80 72 movk w0, #0x0 + libdis_test+0x84: 00 00 80 72 movk w0, #0x0 + libdis_test+0x88: 00 00 a0 72 movk w0, #0x0, lsl #16 + libdis_test+0x8c: 00 00 80 f2 movk x0, #0x0 + libdis_test+0x90: 00 00 80 f2 movk x0, #0x0 + libdis_test+0x94: 00 00 a0 f2 movk x0, #0x0, lsl #16 + libdis_test+0x98: 00 00 c0 f2 movk x0, #0x0, lsl #32 + libdis_test+0x9c: 00 00 e0 f2 movk x0, #0x0, lsl #48 + libdis_test+0xa0: e0 ff 9f 72 movk w0, #0xffff + libdis_test+0xa4: e0 ff 9f 72 movk w0, #0xffff + libdis_test+0xa8: e0 ff bf 72 movk w0, #0xffff, lsl #16 + libdis_test+0xac: e0 ff 9f f2 movk x0, #0xffff + libdis_test+0xb0: e0 ff 9f f2 movk x0, #0xffff + libdis_test+0xb4: e0 ff bf f2 movk x0, #0xffff, lsl #16 + libdis_test+0xb8: e0 ff df f2 movk x0, #0xffff, lsl #32 + libdis_test+0xbc: e0 ff ff f2 movk x0, #0xffff, lsl #48 diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.movwide-imm.s b/usr/src/test/util-tests/tests/dis/arm64/tst.movwide-imm.s new file mode 100755 index 0000000000..03593d119e --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.movwide-imm.s @@ -0,0 +1,49 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.4.5 Move wide (immediate) + */ +.macro movw_imm op + \op w0, #0x0000 + \op w0, #0x0000, lsl #0 + \op w0, #0x0000, lsl #16 + \op x0, #0x0000 + \op x0, #0x0000, lsl #0 + \op x0, #0x0000, lsl #16 + \op x0, #0x0000, lsl #32 + \op x0, #0x0000, lsl #48 + \op w0, #0xffff + \op w0, #0xffff, lsl #0 + \op w0, #0xffff, lsl #16 + \op x0, #0xffff + \op x0, #0xffff, lsl #0 + \op x0, #0xffff, lsl #16 + \op x0, #0xffff, lsl #32 + \op x0, #0xffff, lsl #48 +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * C5.6.127 MOVN + * C5.6.122 MOV (inverted wide immediate) (alias) + */ + movw_imm movn + movw_imm movz + movw_imm movk +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.regs.out b/usr/src/test/util-tests/tests/dis/arm64/tst.regs.out new file mode 100644 index 0000000000..ab2ae4c126 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.regs.out @@ -0,0 +1,24 @@ + libdis_test: 20 00 02 0b add w0, w1, w2 + libdis_test+0x4: 83 00 05 0b add w3, w4, w5 + libdis_test+0x8: e6 00 08 0b add w6, w7, w8 + libdis_test+0xc: 49 01 0b 0b add w9, w10, w11 + libdis_test+0x10: ac 01 0e 0b add w12, w13, w14 + libdis_test+0x14: 0f 02 11 0b add w15, w16, w17 + libdis_test+0x18: 72 02 14 0b add w18, w19, w20 + libdis_test+0x1c: d5 02 17 0b add w21, w22, w23 + libdis_test+0x20: 38 03 1a 0b add w24, w25, w26 + libdis_test+0x24: 9b 03 1d 0b add w27, w28, w29 + libdis_test+0x28: fe 07 00 11 add w30, wsp, #0x1 + libdis_test+0x2c: 20 00 02 8b add x0, x1, x2 + libdis_test+0x30: 83 00 05 8b add x3, x4, x5 + libdis_test+0x34: e6 00 08 8b add x6, x7, x8 + libdis_test+0x38: 49 01 0b 8b add x9, x10, x11 + libdis_test+0x3c: ac 01 0e 8b add x12, x13, x14 + libdis_test+0x40: 0f 02 11 8b add x15, x16, x17 + libdis_test+0x44: 72 02 14 8b add x18, x19, x20 + libdis_test+0x48: d5 02 17 8b add x21, x22, x23 + libdis_test+0x4c: 38 03 1a 8b add x24, x25, x26 + libdis_test+0x50: 9b 03 1d 8b add x27, x28, x29 + libdis_test+0x54: fe 0b 00 91 add x30, sp, #0x2 + libdis_test+0x58: 1f 00 01 8b add xzr, x0, x1 + libdis_test+0x5c: 3f 00 02 0b add wzr, w1, w2 diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.regs.s b/usr/src/test/util-tests/tests/dis/arm64/tst.regs.s new file mode 100644 index 0000000000..741507752f --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.regs.s @@ -0,0 +1,50 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * Test basic register naming + */ + +.text +.align 16 +.globl libdis_test +.type libdis_test, @function +libdis_test: + ADD W0, W1, W2 + ADD W3, W4, W5 + ADD W6, W7, W8 + ADD W9, W10, W11 + ADD W12, W13, W14 + ADD W15, W16, W17 + ADD W18, W19, W20 + ADD W21, W22, W23 + ADD W24, W25, W26 + ADD W27, W28, W29 + ADD W30, WSP, #1 + ADD X0, X1, X2 + ADD X3, X4, X5 + ADD X6, X7, X8 + ADD X9, X10, X11 + ADD X12, X13, X14 + ADD X15, X16, X17 + ADD X18, X19, X20 + ADD X21, X22, X23 + ADD X24, X25, X26 + ADD X27, X28, X29 + ADD X30, SP, #2 + + ADD XZR, X0, X1 + ADD WZR, W1, W2 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.system.out b/usr/src/test/util-tests/tests/dis/arm64/tst.system.out new file mode 100755 index 0000000000..eab7b784f6 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.system.out @@ -0,0 +1,88 @@ + libdis_test: bf 40 00 d5 msr spsel, #0x0 + libdis_test+0x4: df 47 03 d5 msr daifset, #0x7 + libdis_test+0x8: ff 4f 03 d5 msr daifclr, #0xf + libdis_test+0xc: 1f 20 03 d5 nop + libdis_test+0x10: 3f 20 03 d5 yield + libdis_test+0x14: 5f 20 03 d5 wfe + libdis_test+0x18: 7f 20 03 d5 wfi + libdis_test+0x1c: 9f 20 03 d5 sev + libdis_test+0x20: bf 20 03 d5 sevl + libdis_test+0x24: df 20 03 d5 hint #0x6 + libdis_test+0x28: ff 2f 03 d5 hint #0x7f + libdis_test+0x2c: 5f 30 03 d5 clrex #0x0 + libdis_test+0x30: 5f 3f 03 d5 clrex + libdis_test+0x34: 9f 30 03 d5 dsb #0x0 + libdis_test+0x38: bf 30 03 d5 dmb #0x0 + libdis_test+0x3c: df 30 03 d5 isb #0x0 + libdis_test+0x40: 9f 31 03 d5 dsb oshld + libdis_test+0x44: bf 31 03 d5 dmb oshld + libdis_test+0x48: df 31 03 d5 isb #0x1 + libdis_test+0x4c: 9f 32 03 d5 dsb oshst + libdis_test+0x50: bf 32 03 d5 dmb oshst + libdis_test+0x54: df 32 03 d5 isb #0x2 + libdis_test+0x58: 9f 33 03 d5 dsb osh + libdis_test+0x5c: bf 33 03 d5 dmb osh + libdis_test+0x60: df 33 03 d5 isb #0x3 + libdis_test+0x64: 9f 34 03 d5 dsb #0x4 + libdis_test+0x68: bf 34 03 d5 dmb #0x4 + libdis_test+0x6c: df 34 03 d5 isb #0x4 + libdis_test+0x70: 9f 35 03 d5 dsb nshld + libdis_test+0x74: bf 35 03 d5 dmb nshld + libdis_test+0x78: df 35 03 d5 isb #0x5 + libdis_test+0x7c: 9f 36 03 d5 dsb nshst + libdis_test+0x80: bf 36 03 d5 dmb nshst + libdis_test+0x84: df 36 03 d5 isb #0x6 + libdis_test+0x88: 9f 37 03 d5 dsb nsh + libdis_test+0x8c: bf 37 03 d5 dmb nsh + libdis_test+0x90: df 37 03 d5 isb #0x7 + libdis_test+0x94: 9f 38 03 d5 dsb #0x8 + libdis_test+0x98: bf 38 03 d5 dmb #0x8 + libdis_test+0x9c: df 38 03 d5 isb #0x8 + libdis_test+0xa0: 9f 39 03 d5 dsb ishld + libdis_test+0xa4: bf 39 03 d5 dmb ishld + libdis_test+0xa8: df 39 03 d5 isb #0x9 + libdis_test+0xac: 9f 3a 03 d5 dsb ishst + libdis_test+0xb0: bf 3a 03 d5 dmb ishst + libdis_test+0xb4: df 3a 03 d5 isb #0xa + libdis_test+0xb8: 9f 3b 03 d5 dsb ish + libdis_test+0xbc: bf 3b 03 d5 dmb ish + libdis_test+0xc0: df 3b 03 d5 isb #0xb + libdis_test+0xc4: 9f 3c 03 d5 dsb #0xc + libdis_test+0xc8: bf 3c 03 d5 dmb #0xc + libdis_test+0xcc: df 3c 03 d5 isb #0xc + libdis_test+0xd0: 9f 3d 03 d5 dsb ld + libdis_test+0xd4: bf 3d 03 d5 dmb ld + libdis_test+0xd8: df 3d 03 d5 isb #0xd + libdis_test+0xdc: 9f 3e 03 d5 dsb st + libdis_test+0xe0: bf 3e 03 d5 dmb st + libdis_test+0xe4: df 3e 03 d5 isb #0xe + libdis_test+0xe8: 9f 3f 03 d5 dsb sy + libdis_test+0xec: bf 3f 03 d5 dmb sy + libdis_test+0xf0: df 3f 03 d5 isb + libdis_test+0xf4: 15 78 08 d5 sys #0x0, c7, c8, #0x0, x21 + libdis_test+0xf8: ff 78 0c d5 sys #0x4, c7, c8, #0x7 + libdis_test+0xfc: 35 74 0b d5 sys #0x3, c7, c4, #0x1, x21 + libdis_test+0x100: 5f 7e 08 d5 sys #0x0, c7, c14, #0x2 + libdis_test+0x104: 1f 71 08 d5 sys #0x0, c7, c1, #0x0 + libdis_test+0x108: 35 75 0b d5 sys #0x3, c7, c5, #0x1, x21 + libdis_test+0x10c: 35 80 0c d5 sys #0x4, c8, c0, #0x1, x21 + libdis_test+0x110: ff 87 08 d5 sys #0x0, c8, c7, #0x7 + libdis_test+0x114: 15 00 08 d5 sys #0x0, c0, c0, #0x0, x21 + libdis_test+0x118: ff ff 0f d5 sys #0x7, c15, c15, #0x7 + libdis_test+0x11c: 15 00 10 d5 msr s2_0_c0_c0_0, x21 + libdis_test+0x120: 1f 00 30 d5 mrs xzr, s2_0_c0_c0_0 + libdis_test+0x124: 15 00 18 d5 msr midr_el1, x21 + libdis_test+0x128: 1f 00 38 d5 mrs xzr, midr_el1 + libdis_test+0x12c: 35 00 10 d5 msr s2_0_c0_c0_1, x21 + libdis_test+0x130: 3f 00 30 d5 mrs xzr, s2_0_c0_c0_1 + libdis_test+0x134: 35 00 18 d5 msr s3_0_c0_c0_1, x21 + libdis_test+0x138: 3f 00 38 d5 mrs xzr, s3_0_c0_c0_1 + libdis_test+0x13c: f5 ef 13 d5 msr s2_3_c14_c15_7, x21 + libdis_test+0x140: ff ef 33 d5 mrs xzr, s2_3_c14_c15_7 + libdis_test+0x144: f5 ef 1b d5 msr pmccfiltr_el0, x21 + libdis_test+0x148: ff ef 3b d5 mrs xzr, pmccfiltr_el0 + libdis_test+0x14c: f5 ff 17 d5 msr s2_7_c15_c15_7, x21 + libdis_test+0x150: ff ff 37 d5 mrs xzr, s2_7_c15_c15_7 + libdis_test+0x154: f5 ff 1f d5 msr s3_7_c15_c15_7, x21 + libdis_test+0x158: ff ff 3f d5 mrs xzr, s3_7_c15_c15_7 + libdis_test+0x15c: 15 00 28 d5 sysl x21, #0x0, c0, c0, #0x0 diff --git a/usr/src/test/util-tests/tests/dis/arm64/tst.system.s b/usr/src/test/util-tests/tests/dis/arm64/tst.system.s new file mode 100755 index 0000000000..0a2946b8a5 --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/arm64/tst.system.s @@ -0,0 +1,138 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2018 Joyent, Inc. + */ + +/* + * C3.2.4 System + */ + +/* + * For full testing this macro can be used to generate all possible combations + * of SYS/SYSL instructions, but the resulting output file is 2MB so is not + * enabled by default. + */ +.macro sysops_all + .irp op1,0,1,2,3,4,5,6,7 + .irp crn,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + .irp crm,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + .irp op2,0,1,2,3,4,5,6,7 + sys #\op1, C\crn, C\crm, #\op2, x21 + sys #\op1, C\crn, C\crm, #\op2, xzr + sysl x21, #\op1, C\crn, C\crm, #\op2 + .endr + .endr + .endr + .endr +.endm + +.macro regop op1, crn, crm, op2 + /* + * XXX: gas won't let us use .irp here to iterate s0..s3 which is + * completely ridiculous (the variable does not get expanded), so + * we just have to do it the old fashioned way. + */ + msr s2_\op1\()_c\crn\()_c\crm\()_\op2\(), x21 + mrs xzr, s2_\op1\()_c\crn\()_c\crm\()_\op2\() + msr s3_\op1\()_c\crn\()_c\crm\()_\op2\(), x21 + mrs xzr, s3_\op1\()_c\crn\()_c\crm\()_\op2\() +.endm + +/* + * For full testing this macro can be used to generate all possible combations + * of SYS instructions, but the resulting output file is 2MB so is not enabled + * by default. + */ +.macro regops_all + .irp op1,0,1,2,3,4,5,6,7 + .irp crn,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + .irp crm,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + .irp op2,0,1,2,3,4,5,6,7 + regop \op1, \crn, \crm, \op2 + .endr + .endr + .endr + .endr +.endm + +.text +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* + * Enable these for full testing. + */ + .ifdef SYSTEM_TEST_ALL + sysops_all + regops_all + .endif + /* + * C5.6.130 MSR (immediate) + */ + msr spsel, #0 + msr daifset, #7 + msr daifclr, #15 + /* + * C5.6.68 HINT and its aliases. + */ + nop + yield + wfe + wfi + sev + sevl + hint #6 + hint #127 + /* + * C5.6.38 CLREX + */ + clrex #0 + clrex #15 + /* + * C5.6.62 DSB + * C5.6.60 DMB + * C5.6.72 ISB + */ + .irp imm,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + dsb #\imm + dmb #\imm + isb #\imm + .endr + /* + * C5.6.204 SYS and its aliases. Test the first and last valid + * operration for each. + */ + at s1e1r, x21 + at s12e0w, xzr + dc zva, x21 + dc cisw, xzr + ic ialluis + ic ivau, x21 + tlbi ipas2e1is, x21 + tlbi vaale1, xzr + /* SYS instructions which do not map to an alias. */ + sys #0, C0, C0, #0, x21 + sys #7, C15, C15, #7, xzr + /* + * C5.6.131 MSR (register) + * C5.6.129 MRS + */ + regop 0, 0, 0, 0 // midr_el1 + regop 0, 0, 0, 1 // impl defn + regop 3, 14, 15, 7 // pmccfiltr_el0 + regop 7, 15, 15, 7 // impl defn (last) + /* + * C5.6.205 SYSL + */ + sysl x21, #0, C0, C0, #0 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/distest.ksh b/usr/src/test/util-tests/tests/dis/distest.ksh index 21b39a69bc..7ec935412b 100644..100755 --- a/usr/src/test/util-tests/tests/dis/distest.ksh +++ b/usr/src/test/util-tests/tests/dis/distest.ksh @@ -215,8 +215,16 @@ run_single_file() test_one "-64" $sfile $cmpfile ;; tst) - test_one "-32" $sfile $cmpfile "(32-bit)" - test_one "-64" $sfile $cmpfile "(64-bit)" + case "$arch" in + arm64) + # arm64 gas doesn't work with -64 or -32 flags. + test_one "" $sfile $cmpfile + ;; + *) + test_one "-32" $sfile $cmpfile "(32-bit)" + test_one "-64" $sfile $cmpfile "(64-bit)" + ;; + esac ;; esac } @@ -270,9 +278,10 @@ while getopts ":np:" c $@; do dt_nodefault="y" ;; p) + OLD_IFS=$IFS IFS="=" set -A split $OPTARG - IFS=" " + IFS=$OLD_IFS [[ ${#split[@]} -eq 2 ]] || usage "malformed -p option: $OPTARG" dt_platforms[${split[0]}]=${split[1]} ;; |