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-rw-r--r--usr/src/uts/common/io/scsi/adapters/smrt/smrt_ciss.c16
-rw-r--r--usr/src/uts/common/io/scsi/adapters/smrt/smrt_device.c2
-rw-r--r--usr/src/uts/common/io/scsi/adapters/smrt/smrt_physical.c1
3 files changed, 9 insertions, 10 deletions
diff --git a/usr/src/uts/common/io/scsi/adapters/smrt/smrt_ciss.c b/usr/src/uts/common/io/scsi/adapters/smrt/smrt_ciss.c
index b4cdd5607e..8da9ac9038 100644
--- a/usr/src/uts/common/io/scsi/adapters/smrt/smrt_ciss.c
+++ b/usr/src/uts/common/io/scsi/adapters/smrt/smrt_ciss.c
@@ -123,15 +123,15 @@
* The CISS specification allows for three different kinds of attributes that
* describe how requests are queued to the controller. These are:
*
- * HEAD OF QUEUE The request should go to the head of the
- * controller queue. This is used for resets and
- * aborts to ensure that they're not blocked behind
- * additional I/O.
+ * HEAD OF QUEUE The request should go to the head of the
+ * controller queue. This is used for resets and
+ * aborts to ensure that they're not blocked behind
+ * additional I/O.
*
- * SIMPLE This queues the request for normal processing.
- * Commands queued this way are not special with
- * respect to one another. We use this for all I/O
- * and discovery commands.
+ * SIMPLE This queues the request for normal processing.
+ * Commands queued this way are not special with
+ * respect to one another. We use this for all I/O
+ * and discovery commands.
*
* ORDERED This attribute is used to indicate that commands
* should be submitted and processed in some order.
diff --git a/usr/src/uts/common/io/scsi/adapters/smrt/smrt_device.c b/usr/src/uts/common/io/scsi/adapters/smrt/smrt_device.c
index 9e27448b68..433b2ea2ee 100644
--- a/usr/src/uts/common/io/scsi/adapters/smrt/smrt_device.c
+++ b/usr/src/uts/common/io/scsi/adapters/smrt/smrt_device.c
@@ -58,7 +58,7 @@ smrt_locate_cfgtbl(smrt_t *smrt, pci_regspec_t *regs, unsigned nregs,
/*
* Locate the Configuration Table. Three different values read
* from two I2O registers allow us to determine the location:
- * - the correct PCI BAR offset is in the low 16 bits of
+ * - the correct PCI BAR offset is in the low 16 bits of
* CISS_I2O_CFGTBL_CFG_OFFSET
* - bit 16 is 0 for a 32-bit space, and 1 for 64-bit
* - the memory offset from the base of this BAR is
diff --git a/usr/src/uts/common/io/scsi/adapters/smrt/smrt_physical.c b/usr/src/uts/common/io/scsi/adapters/smrt/smrt_physical.c
index 8ab3927673..88ed57bc7d 100644
--- a/usr/src/uts/common/io/scsi/adapters/smrt/smrt_physical.c
+++ b/usr/src/uts/common/io/scsi/adapters/smrt/smrt_physical.c
@@ -606,7 +606,6 @@ smrt_phys_teardown(smrt_t *smrt)
{
smrt_physical_t *smpt;
- VERIFY(MUTEX_HELD(&smrt->smrt_mutex));
while ((smpt = list_remove_head(&smrt->smrt_physicals)) != NULL) {
smrt_physical_free(smpt);
}