diff options
Diffstat (limited to 'usr/src/uts/common/sys/hotplug/pci')
| -rw-r--r-- | usr/src/uts/common/sys/hotplug/pci/pcicfg.h | 17 | ||||
| -rw-r--r-- | usr/src/uts/common/sys/hotplug/pci/pcie_hp.h | 332 | ||||
| -rw-r--r-- | usr/src/uts/common/sys/hotplug/pci/pciehpc.h | 37 | ||||
| -rw-r--r-- | usr/src/uts/common/sys/hotplug/pci/pciehpc_impl.h | 233 | ||||
| -rw-r--r-- | usr/src/uts/common/sys/hotplug/pci/pcihp.h | 4 | ||||
| -rw-r--r-- | usr/src/uts/common/sys/hotplug/pci/pcishpc.h | 24 | ||||
| -rwxr-xr-x | usr/src/uts/common/sys/hotplug/pci/pcishpc_regs.h | 60 |
7 files changed, 373 insertions, 334 deletions
diff --git a/usr/src/uts/common/sys/hotplug/pci/pcicfg.h b/usr/src/uts/common/sys/hotplug/pci/pcicfg.h index c800f90e5a..943ece4875 100644 --- a/usr/src/uts/common/sys/hotplug/pci/pcicfg.h +++ b/usr/src/uts/common/sys/hotplug/pci/pcicfg.h @@ -20,28 +20,35 @@ */ /* - * Copyright 2006 Sun Microsystems, Inc. All rights reserved. + * Copyright 2009 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ #ifndef _SYS_HOTPLUG_PCI_PCICFG_H #define _SYS_HOTPLUG_PCI_PCICFG_H -#pragma ident "%Z%%M% %I% %E% SMI" - #ifdef __cplusplus extern "C" { #endif +typedef enum pcicfg_flags { + /* No probing; used in case of virtual hotplug */ + PCICFG_FLAG_READ_ONLY = 0x1, + /* Enable ARI; used in case of boot case */ + PCICFG_FLAG_ENABLE_ARI = 0x2 +} pcicfg_flags_t; + /* * Interfaces exported by PCI configurator module, kernel/misc/pcicfg. */ -int pcicfg_configure(dev_info_t *, uint_t); -int pcicfg_unconfigure(dev_info_t *, uint_t); +int pcicfg_configure(dev_info_t *, uint_t, uint_t, pcicfg_flags_t); +int pcicfg_unconfigure(dev_info_t *, uint_t, uint_t, pcicfg_flags_t); #define PCICFG_SUCCESS DDI_SUCCESS #define PCICFG_FAILURE DDI_FAILURE +#define PCICFG_ALL_FUNC 0xffffffff + /* * The following subclass definition for Non Transparent bridge should * be moved to pci.h. diff --git a/usr/src/uts/common/sys/hotplug/pci/pcie_hp.h b/usr/src/uts/common/sys/hotplug/pci/pcie_hp.h new file mode 100644 index 0000000000..8810c5203c --- /dev/null +++ b/usr/src/uts/common/sys/hotplug/pci/pcie_hp.h @@ -0,0 +1,332 @@ +/* + * CDDL HEADER START + * + * The contents of this file are subject to the terms of the + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE + * or http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + * + * When distributing Covered Code, include this CDDL HEADER in each + * file and include the License file at usr/src/OPENSOLARIS.LICENSE. + * If applicable, add the following below this CDDL HEADER, with the + * fields enclosed by brackets "[]" replaced with your own identifying + * information: Portions Copyright [yyyy] [name of copyright owner] + * + * CDDL HEADER END + */ +/* + * Copyright 2009 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms. + */ + +#ifndef _SYS_PCIE_HP_H +#define _SYS_PCIE_HP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef _KERNEL +#include <sys/ddi_hp.h> +#include <sys/pcie_impl.h> +#endif /* _KERNEL */ +#include "../../../../../common/pci/pci_strings.h" +#include <sys/hotplug/pci/pcihp.h> + +#define PCIEHPC_PROP_HELP "help" +#define PCIEHPC_PROP_ALL "all" +#define PCIEHPC_PROP_LED_FAULT "fault_led" +#define PCIEHPC_PROP_LED_POWER "power_led" +#define PCIEHPC_PROP_LED_ATTN "attn_led" +#define PCIEHPC_PROP_LED_ACTIVE "active_led" +#define PCIEHPC_PROP_CARD_TYPE "card_type" +#define PCIEHPC_PROP_BOARD_TYPE "board_type" +#define PCIEHPC_PROP_SLOT_CONDITION "slot_condition" + +#define PCIEHPC_PROP_VALUE_UNKNOWN "unknown" +#define PCIEHPC_PROP_VALUE_ON "on" +#define PCIEHPC_PROP_VALUE_OFF "off" +#define PCIEHPC_PROP_VALUE_BLINK "blink" +#define PCIEHPC_PROP_VALUE_PCIHOTPLUG "pci hotplug" +#define PCIEHPC_PROP_VALUE_OK "ok" +#define PCIEHPC_PROP_VALUE_FAILING "failing" +#define PCIEHPC_PROP_VALUE_FAILED "failed" +#define PCIEHPC_PROP_VALUE_UNUSABLE "unusable" +#define PCIEHPC_PROP_VALUE_LED "<on|off|blink>" +#define PCIEHPC_PROP_VALUE_TYPE "<type description>" +#define PCIEHPC_PROP_VALUE_CONDITION "<unknown|ok|failing|failed|unusable>" + +/* condition */ +#define PCIEHPC_PROP_COND_OK "ok" +#define PCIEHPC_PROP_COND_FAILING "failing" +#define PCIEHPC_PROP_COND_FAILED "failed" +#define PCIEHPC_PROP_COND_UNUSABLE "unusable" +#define PCIEHPC_PROP_COND_UNKNOWN "unknown" + +#ifdef _KERNEL + +#define PCIE_HP_MAX_SLOTS 31 /* Max # of slots */ +#define PCIE_HP_CMD_WAIT_TIME 10000 /* Delay in microseconds */ +#define PCIE_HP_CMD_WAIT_RETRY 100 /* Max retry count */ +#define PCIE_HP_DLL_STATE_CHANGE_TIMEOUT 1 /* Timeout in seconds */ +#define PCIE_HP_POWER_GOOD_WAIT_TIME 220000 /* Wait time after issuing a */ + /* cmd to change slot state */ + +/* definations for PCIEHPC/PCISHPC */ +#define PCIE_NATIVE_HP_TYPE "PCIe-Native" /* PCIe Native type */ +#define PCIE_ACPI_HP_TYPE "PCIe-ACPI" /* PCIe ACPI type */ +#define PCIE_PROP_HP_TYPE "PCIe-Proprietary" /* PCIe Prop type */ +#define PCIE_PCI_HP_TYPE "PCI-SHPC" /* PCI (SHPC) type */ + +#define PCIE_GET_HP_CTRL(dip) \ + (pcie_hp_ctrl_t *)PCIE_DIP2BUS(dip)->bus_hp_ctrl + +#define PCIE_SET_HP_CTRL(dip, ctrl_p) \ + (PCIE_DIP2BUS(dip)->bus_hp_ctrl) = (pcie_hp_ctrl_t *)ctrl_p + +#define PCIE_IS_PCIE_HOTPLUG_CAPABLE(bus_p) \ + ((bus_p->bus_hp_sup_modes & PCIE_ACPI_HP_MODE) || \ + (bus_p->bus_hp_sup_modes & PCIE_NATIVE_HP_MODE)) + +#define PCIE_IS_PCI_HOTPLUG_CAPABLE(bus_p) \ + (bus_p->bus_hp_sup_modes & PCIE_PCI_HP_MODE) + +#define PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p) \ + ((bus_p->bus_hp_curr_mode == PCIE_ACPI_HP_MODE) || \ + (bus_p->bus_hp_curr_mode == PCIE_NATIVE_HP_MODE)) + +#define PCIE_IS_PCI_HOTPLUG_ENABLED(bus_p) \ + (bus_p->bus_hp_curr_mode & PCIE_PCI_HP_MODE) + +typedef struct pcie_hp_ctrl pcie_hp_ctrl_t; +typedef struct pcie_hp_slot pcie_hp_slot_t; + +/* + * Maximum length of the string converted from the digital number of pci device + * number and function number, including the string's end mark. For example, + * device number 0 and function number 255 (ARI case), then the length is + * (1 + 3 + 1). + */ +#define PCIE_HP_DEV_FUNC_NUM_STRING_LEN 5 + +/* + * Length of the characters in a PCI port name. + * The format of the PCI port name is: pci.d,f where d is device number, f is + * function number. The constant string and characters are "pci." and ",". + */ +#define PCIE_HP_PORT_NAME_STRING_LEN 5 + +/* Platform specific ops (Native HP, ACPI, etc.) */ +typedef struct pcie_hp_ops { + /* initialize/setup hot plug controller hw */ + int (*init_hpc_hw)(pcie_hp_ctrl_t *ctrl_p); + + /* uninitialize hot plug controller hw */ + int (*uninit_hpc_hw)(pcie_hp_ctrl_t *ctrl_p); + + /* initialize slot information structure */ + int (*init_hpc_slotinfo)(pcie_hp_ctrl_t *ctrl_p); + + /* uninitialize slot information structure */ + int (*uninit_hpc_slotinfo)(pcie_hp_ctrl_t *ctrl_p); + + /* slot poweron */ + int (*poweron_hpc_slot)(pcie_hp_slot_t *slot_p, + ddi_hp_cn_state_t *result); + + /* slot poweroff */ + /* uninitialize hot plug controller hw */ + int (*poweroff_hpc_slot)(pcie_hp_slot_t *slot_p, + ddi_hp_cn_state_t *result); + + /* enable hot plug interrupts/events */ + int (*enable_hpc_intr)(pcie_hp_ctrl_t *ctrl_p); + + /* disable hot plug interrupts/events */ + int (*disable_hpc_intr)(pcie_hp_ctrl_t *ctrl_p); +} pcie_hp_ops_t; + +/* Slot occupant information structure */ +#define PCIE_HP_MAX_OCCUPANTS 128 +typedef struct pcie_hp_occupant_info { + int i; + char *id[PCIE_HP_MAX_OCCUPANTS]; +} pcie_hp_occupant_info_t; + +/* + * pcie_hp_led_t + * + * Type definitions for LED type + */ +typedef enum { + PCIE_HP_FAULT_LED, + PCIE_HP_POWER_LED, + PCIE_HP_ATTN_LED, + PCIE_HP_ACTIVE_LED +} pcie_hp_led_t; + +/* + * pcie_hp_led_state_t + * + * Type definitions for LED state + */ +typedef enum { + PCIE_HP_LED_OFF, + PCIE_HP_LED_ON, + PCIE_HP_LED_BLINK +} pcie_hp_led_state_t; + +/* + * PCI and PCI Express Hotplug slot structure + */ +struct pcie_hp_slot { + uint32_t hs_num; /* Logical slot number */ + uint32_t hs_phy_slot_num; /* Physical slot number */ + uint32_t hs_device_num; /* PCI device num for slot */ + uint16_t hs_minor; /* Minor num for this slot */ + ddi_hp_cn_info_t hs_info; /* Slot information */ + ddi_hp_cn_state_t hs_state; /* Slot state */ + + pcie_hp_led_state_t hs_power_led_state; /* Power LED state */ + pcie_hp_led_state_t hs_attn_led_state; /* Attn LED state */ + pcie_hp_led_state_t hs_active_led_state; /* Active LED state */ + pcie_hp_led_state_t hs_fault_led_state; /* Fault LED state */ + + ap_condition_t hs_condition; /* Condition of the slot. */ + /* For cfgadm condition. */ + + /* Synchronization variable(s) for hot plug events */ + kcondvar_t hs_attn_btn_cv; /* ATTN button pressed intr */ + boolean_t hs_attn_btn_pending; + kthread_t *hs_attn_btn_threadp; /* ATTN button event thread */ + boolean_t hs_attn_btn_thread_exit; + kcondvar_t hs_dll_active_cv; /* DLL State Changed intr */ + + pcie_hp_ctrl_t *hs_ctrl; /* Hotplug ctrl for this slot */ +}; + +/* + * Register ops for read/write of non-standard HPC (e.g: OPL platform). + */ +typedef struct pcie_hp_regops { + uint_t (*get)(void *cookie, off_t offset); + uint_t (*put)(void *cookie, off_t offset, uint_t val); + void *cookie; +} pcie_hp_regops_t; + +/* + * PCI and PCI Express Hotplug controller structure + */ +struct pcie_hp_ctrl { + dev_info_t *hc_dip; /* DIP for HP controller */ + kmutex_t hc_mutex; /* Mutex for this ctrl */ + uint_t hc_flags; /* Misc flags */ + + /* Slot information */ + pcie_hp_slot_t *hc_slots[PCIE_HP_MAX_SLOTS]; /* Slot pointers */ + boolean_t hc_has_attn; /* Do we have attn btn? */ + boolean_t hc_has_mrl; /* Do we have MRL? */ + kcondvar_t hc_cmd_comp_cv; /* Command Completion intr */ + boolean_t hc_cmd_pending; /* Command completion pending */ + + /* PCI Express Hotplug specific fields */ + boolean_t hc_has_emi_lock; /* Do we have EMI Lock? */ + boolean_t hc_dll_active_rep; /* Report DLL DL_Active state */ + pcie_hp_ops_t hc_ops; /* Platform specific ops */ + /* (Native, ACPI) */ + + /* PCI Hotplug (SHPC) specific fields */ + uint32_t hc_num_slots_impl; /* # of HP Slots Implemented */ + uint32_t hc_num_slots_connected; /* # of HP Slots Connected */ + int hc_curr_bus_speed; /* Current Bus Speed */ + uint32_t hc_device_start; /* 1st PCI Device # */ + uint32_t hc_phys_start; /* 1st Phys Device # */ + uint32_t hc_device_increases; /* Device # Increases */ + boolean_t hc_arbiter_timeout; /* Got a Arb timeout IRQ */ + + /* Register read/write ops for non-standard HPC (e.g: OPL) */ + pcie_hp_regops_t hc_regops; + + /* Platform implementation specific data if any: ACPI, CK804,... */ + void *hc_misc_data; +}; + +/* + * Control structure for tree walk during configure/unconfigure operation. + */ +typedef struct pcie_hp_cn_cfg_t { + void *slotp; + boolean_t flag; /* Flag to ignore errors */ + int rv; /* Return error code */ + dev_info_t *dip; /* dip at which the (first) */ + /* error occurred */ + void *cn_private; /* Connection specific data */ +} pcie_hp_cn_cfg_t; + +/* + * arg for unregistering port of a pci bridge + */ +typedef struct pcie_hp_unreg_port { + /* pci bridge dip to which the port is associated */ + dev_info_t *nexus_dip; + /* + * Connector number of the physical slot whose dependent ports will be + * unregistered. If NULL, then all the ports of the pci bridge dip will + * be unregistered. + */ + int connector_num; + int rv; +} pcie_hp_unreg_port_t; + +/* + * arg for getting a port's state + */ +typedef struct pcie_hp_port_state { + char *cn_name; + ddi_hp_cn_state_t cn_state; + int rv; +} pcie_hp_port_state_t; + +/* hc_flags */ +#define PCIE_HP_INITIALIZED_FLAG (1 << 0) /* HPC initialized */ + +/* PCIe hotplug friendly functions */ +extern int pcie_hp_init(dev_info_t *dip, caddr_t arg); +extern int pcie_hp_uninit(dev_info_t *dip); +extern int pcie_hp_intr(dev_info_t *dip); +extern int pcie_hp_probe(pcie_hp_slot_t *slot_p); +extern int pcie_hp_unprobe(pcie_hp_slot_t *slot_p); +extern int pcie_hp_common_ops(dev_info_t *dip, char *cn_name, ddi_hp_op_t op, + void *arg, void *result); +extern dev_info_t *pcie_hp_devi_find(dev_info_t *dip, uint_t device, + uint_t function); +extern void pcie_hp_create_occupant_props(dev_info_t *self, dev_t dev, + int pci_dev); +extern void pcie_hp_create_occupant_props(dev_info_t *self, dev_t dev, + int pci_dev); +extern void pcie_hp_delete_occupant_props(dev_info_t *dip, dev_t dev); +extern int pcie_copyin_nvlist(char *packed_buf, size_t packed_sz, + nvlist_t **nvlp); +extern int pcie_copyout_nvlist(nvlist_t *nvl, char *packed_buf, + size_t *packed_sz); +extern char *pcie_led_state_text(pcie_hp_led_state_t state); +extern char *pcie_slot_condition_text(ap_condition_t condition); +extern int pcie_create_minor_node(pcie_hp_ctrl_t *, int); +extern void pcie_remove_minor_node(pcie_hp_ctrl_t *, int); +extern void pcie_hp_gen_sysevent_req(char *slot_name, int hint, + dev_info_t *self, int kmflag); + +extern const struct pci_class_strings_s class_pci[]; +extern int class_pci_items; + +#endif /* _KERNEL */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_PCIE_HP_H */ diff --git a/usr/src/uts/common/sys/hotplug/pci/pciehpc.h b/usr/src/uts/common/sys/hotplug/pci/pciehpc.h index dd1ad7c416..1d57720559 100644 --- a/usr/src/uts/common/sys/hotplug/pci/pciehpc.h +++ b/usr/src/uts/common/sys/hotplug/pci/pciehpc.h @@ -2,9 +2,8 @@ * CDDL HEADER START * * The contents of this file are subject to the terms of the - * Common Development and Distribution License, Version 1.0 only - * (the "License"). You may not use this file except in compliance - * with the License. + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. @@ -19,17 +18,14 @@ * * CDDL HEADER END */ - /* - * Copyright 2005 Sun Microsystems, Inc. All rights reserved. + * Copyright 2009 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ #ifndef _SYS_HOTPLUG_PCI_PCIEHPC_H #define _SYS_HOTPLUG_PCI_PCIEHPC_H -#pragma ident "%Z%%M% %I% %E% SMI" - #ifdef __cplusplus extern "C" { #endif @@ -37,17 +33,22 @@ extern "C" { /* * Interfaces exported by PCI-E nexus Hot Plug Controller extension module */ - -/* register ops for read/write of non-standard HPC (e.g: OPL platform) */ -typedef struct pciehpc_regops { - uint_t (*get)(void *cookie, off_t offset); - uint_t (*put)(void *cookie, off_t offset, uint_t val); - void *cookie; -} pciehpc_regops_t; - -int pciehpc_init(dev_info_t *, pciehpc_regops_t *); -int pciehpc_uninit(dev_info_t *); -int pciehpc_intr(dev_info_t *); +int pciehpc_init(dev_info_t *dip, caddr_t arg); +int pciehpc_uninit(dev_info_t *dip); +int pciehpc_intr(dev_info_t *dip); +int pciehpc_hp_ops(dev_info_t *dip, char *cn_name, ddi_hp_op_t op, void *arg, + void *result); +void pciehpc_get_slot_state(pcie_hp_slot_t *slot_p); +void pciehpc_set_slot_name(pcie_hp_ctrl_t *ctrl_p); +uint8_t pciehpc_reg_get8(pcie_hp_ctrl_t *ctrl_p, uint_t off); +uint16_t pciehpc_reg_get16(pcie_hp_ctrl_t *ctrl_p, uint_t off); +uint32_t pciehpc_reg_get32(pcie_hp_ctrl_t *ctrl_p, uint_t off); +void pciehpc_reg_put8(pcie_hp_ctrl_t *ctrl_p, uint_t off, uint8_t val); +void pciehpc_reg_put16(pcie_hp_ctrl_t *ctrl_p, uint_t off, uint16_t val); +void pciehpc_reg_put32(pcie_hp_ctrl_t *ctrl_p, uint_t off, uint32_t val); +#if defined(__i386) || defined(__amd64) +extern void pciehpc_update_ops(pcie_hp_ctrl_t *ctrl_p); +#endif /* defined(__i386) || defined(__amd64) */ #ifdef __cplusplus } diff --git a/usr/src/uts/common/sys/hotplug/pci/pciehpc_impl.h b/usr/src/uts/common/sys/hotplug/pci/pciehpc_impl.h deleted file mode 100644 index b2915d15e9..0000000000 --- a/usr/src/uts/common/sys/hotplug/pci/pciehpc_impl.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * CDDL HEADER START - * - * The contents of this file are subject to the terms of the - * Common Development and Distribution License (the "License"). - * You may not use this file except in compliance with the License. - * - * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE - * or http://www.opensolaris.org/os/licensing. - * See the License for the specific language governing permissions - * and limitations under the License. - * - * When distributing Covered Code, include this CDDL HEADER in each - * file and include the License file at usr/src/OPENSOLARIS.LICENSE. - * If applicable, add the following below this CDDL HEADER, with the - * fields enclosed by brackets "[]" replaced with your own identifying - * information: Portions Copyright [yyyy] [name of copyright owner] - * - * CDDL HEADER END - */ - -/* - * Copyright 2008 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. - */ - -#ifndef _SYS_HOTPLUG_PCI_PCIEHPC_IMPL_H -#define _SYS_HOTPLUG_PCI_PCIEHPC_IMPL_H - -#pragma ident "%Z%%M% %I% %E% SMI" - -#ifdef __cplusplus -extern "C" { -#endif - -#include <sys/disp.h> -#include <sys/stat.h> -#include <sys/condvar.h> -#include <sys/pcie.h> -#include <sys/hotplug/hpcsvc.h> -#include <sys/hotplug/pci/pciehpc.h> - -/* - * PCI Express Hot Plug slot softstate structure - * - */ -typedef struct pciehpc_slot -{ - hpc_slot_info_t slot_info; /* HPS framework slot info */ - hpc_slot_t slot_handle; /* HPS framework handle */ - hpc_slot_ops_t slot_ops; /* HPS framework callbacks */ - uint32_t fault_led_state; /* Fault LED state */ - uint32_t power_led_state; /* Power LED state */ - uint32_t attn_led_state; /* Attn LED state */ - uint32_t active_led_state; /* Active LED state */ - hpc_slot_state_t slot_state; /* Slot State */ - uint32_t slotNum; /* slot number */ - /* synchronization variable(s) for hot plug events */ - kcondvar_t cmd_comp_cv; /* Command Completion intr. */ - boolean_t command_pending; - kcondvar_t attn_btn_cv; /* ATTN button pressed intr */ - boolean_t attn_btn_pending; - kthread_t *attn_btn_threadp; /* ATTN button event thread */ - boolean_t attn_btn_thread_exit; - kcondvar_t dll_active_cv; /* DLL State Changed intr */ -} pciehpc_slot_t; - -typedef enum { - PCIEHPC_NATIVE_HP_MODE, PCIEHPC_ACPI_HP_MODE -} pciehpc_hp_mode_t; - -typedef uint32_t pciehpc_soft_state_t; - -/* init_flags */ -#define PCIEHPC_SOFT_STATE_UNINITIALIZED 0x01 -#define PCIEHPC_SOFT_STATE_INITIALIZED 0x02 -#define PCIEHPC_SOFT_STATE_INIT_HTABLE 0x04 -#define PCIEHPC_SOFT_STATE_INIT_ALLOC 0x08 -#define PCIEHPC_SOFT_STATE_INIT_HANDLER 0x10 -#define PCIEHPC_SOFT_STATE_INIT_ENABLE 0x20 -#define PCIEHPC_SOFT_STATE_INIT_BLOCK 0x40 -#define PCIEHPC_SOFT_STATE_INIT_FM 0x80 -#define PCIEHPC_SOFT_STATE_PCIE_DEV 0x10000 - -/* - * PCI Express Hotplug controller soft state structure - */ -typedef struct pciehpc -{ - dev_info_t *dip; /* DIP for the Nexus */ - uint8_t bus; /* primary bus number */ - uint8_t dev; /* device number */ - uint8_t func; /* function number */ - kmutex_t pciehpc_mutex; /* Mutex for this ctrl */ - pciehpc_soft_state_t soft_state; /* soft state flags */ - pciehpc_hp_mode_t hp_mode; /* HP mode (Native, ACPI) */ - struct pciehpc *nextp; /* Linked list pointer */ - - /* PCIE Hot Plug Controller register access */ - ddi_acc_handle_t cfghdl; /* PCI cfg access handle */ - caddr_t regs_base; /* config regs base */ - uint_t pcie_caps_reg_offset; /* offset to PCIE Cap regs */ - - /* slot information */ - pciehpc_slot_t slot; /* Slot info */ - boolean_t has_attn; /* Do we have attn btn? */ - boolean_t has_mrl; /* Do we have MRL? */ - boolean_t has_emi_lock; /* Do we have EMI Lock? */ - - /* link capablities */ - boolean_t dll_active_rep; /* Do we report DLL DL_Active state? */ - - /* register read/write ops for non-standard HPC (e.g: OPL) */ - pciehpc_regops_t regops; - - /* platform specific ops (Native HP, ACPI, etc.) */ - struct pciehpc_ops { - /* initialize/setup hot plug controller hw */ - int (*init_hpc_hw)(struct pciehpc *ctrl_p); - /* initialize slot information structure */ - int (*init_hpc_slotinfo)(struct pciehpc *ctrl_p); - /* disable hot plug interrupts/events */ - int (*disable_hpc_intr)(struct pciehpc *ctrl_p); - /* enable hot plug interrupts/events */ - int (*enable_hpc_intr)(struct pciehpc *ctrl_p); - /* uninitialize hot plug controller hw */ - int (*uninit_hpc_hw)(struct pciehpc *ctrl_p); - /* uninitialize slot information structure */ - int (*uninit_hpc_slotinfo)(struct pciehpc *ctrl_p); - /* probe for HPC */ - int (*probe_hpc)(struct pciehpc *ctrl_p); - } ops; - - /* platform implementation specific data if any: ACPI, CK804,... */ - void *misc_data; -} pciehpc_t; - -typedef struct pciehpc_ops pciehpc_ops_t; - -/* - * PCI-E HPC Command Completion delay in microseconds and the max retry - * count. - */ -#define PCIEHPC_CMD_WAIT_TIME 10000 -#define PCIEHPC_CMD_WAIT_RETRY 100 - -/* - * PCI-E HPC Dll State Change time out in seconds - */ -#define PCIEHPC_DLL_STATE_CHANGE_TIMEOUT 1 - -#define SLOTCTL_SUPPORTED_INTRS_MASK \ - (PCIE_SLOTCTL_ATTN_BTN_EN \ - | PCIE_SLOTCTL_PWR_FAULT_EN \ - | PCIE_SLOTCTL_MRL_SENSOR_EN \ - | PCIE_SLOTCTL_PRESENCE_CHANGE_EN \ - | PCIE_SLOTCTL_CMD_INTR_EN \ - | PCIE_SLOTCTL_HP_INTR_EN \ - | PCIE_SLOTCTL_DLL_STATE_EN) - -#define SLOT_STATUS_EVENTS \ - (PCIE_SLOTSTS_ATTN_BTN_PRESSED \ - | PCIE_SLOTSTS_PWR_FAULT_DETECTED \ - | PCIE_SLOTSTS_MRL_SENSOR_CHANGED \ - | PCIE_SLOTSTS_COMMAND_COMPLETED \ - | PCIE_SLOTSTS_PRESENCE_CHANGED \ - | PCIE_SLOTSTS_DLL_STATE_CHANGED) - -/* - * function prototype defintions for common native mode functions in - * PCIEHPC module. - */ -int pciehpc_hpc_init(pciehpc_t *ctrl_p); -int pciehpc_hpc_uninit(pciehpc_t *ctrl_p); -int pciehpc_slotinfo_init(pciehpc_t *ctrl_p); -int pciehpc_enable_intr(pciehpc_t *ctrl_p); -int pciehpc_disable_intr(pciehpc_t *ctrl_p); -int pciehpc_slotinfo_uninit(pciehpc_t *ctrl_p); -int pciehpc_probe_hpc(pciehpc_t *ctrl_p); -hpc_led_state_t pciehpc_led_state_to_hpc(uint16_t state); -uint16_t pciehpc_led_state_to_pciehpc(hpc_led_state_t state); -hpc_led_state_t pciehpc_get_led_state(pciehpc_t *ctrl_p, hpc_led_t led); -void pciehpc_set_led_state(pciehpc_t *ctrl_p, hpc_led_t led, - hpc_led_state_t state); -int pciehpc_slot_connect(caddr_t ops_arg, hpc_slot_t slot_hdl, - void *data, uint_t flags); -int pciehpc_slot_disconnect(caddr_t ops_arg, hpc_slot_t slot_hdl, - void *data, uint_t flags); -int pciehpc_slot_control(caddr_t ops_arg, hpc_slot_t slot_hdl, - int request, caddr_t arg); -void pciehpc_get_slot_state(pciehpc_t *ctrl_p); -void pciehpc_issue_hpc_command(pciehpc_t *ctrl_p, uint16_t control); -int pciehpc_regs_setup(dev_info_t *dip, uint_t rnum, offset_t off, - caddr_t *addrp, ddi_acc_handle_t *handle); -void pciehpc_regs_teardown(ddi_acc_handle_t *handle); -int pciehpc_register_slot(pciehpc_t *ctrl_p); -int pciehpc_unregister_slot(pciehpc_t *ctrl_p); -uint8_t pciehpc_reg_get8(pciehpc_t *ctrl_p, uint_t off); -uint16_t pciehpc_reg_get16(pciehpc_t *ctrl_p, uint_t off); -uint32_t pciehpc_reg_get32(pciehpc_t *ctrl_p, uint_t off); -void pciehpc_reg_put8(pciehpc_t *ctrl_p, uint_t off, uint8_t val); -void pciehpc_reg_put16(pciehpc_t *ctrl_p, uint_t off, uint16_t val); -void pciehpc_reg_put32(pciehpc_t *ctrl_p, uint_t off, uint32_t val); -void pciehpc_set_slot_name(pciehpc_t *ctrl_p); - -#if defined(__i386) || defined(__amd64) -void pciehpc_update_ops(pciehpc_t *ctrl_p); -#endif /* defined(__i386) || defined(__amd64) */ - -#ifdef DEBUG -extern int pciehpc_debug; -#define PCIEHPC_DEBUG(args) if (pciehpc_debug >= 1) cmn_err args -#define PCIEHPC_DEBUG2(args) if (pciehpc_debug >= 2) cmn_err args -#define PCIEHPC_DEBUG3(args) if (pciehpc_debug >= 3) cmn_err args -#else -#define PCIEHPC_DEBUG(args) -#define PCIEHPC_DEBUG2(args) -#define PCIEHPC_DEBUG3(args) -#endif - -/* default interrupt priority for Hot Plug interrupts */ -#define PCIEHPC_INTR_PRI 1 - -#define PCIE_ENABLE_ERRORS(arg1) \ - pcie_enable_errors(arg1); \ - (void) pcie_enable_ce(arg1) -#define PCIE_DISABLE_ERRORS(arg1) pcie_disable_errors(arg1) - -#ifdef __cplusplus -} -#endif - -#endif /* _SYS_HOTPLUG_PCI_PCIEHPC_IMPL_H */ diff --git a/usr/src/uts/common/sys/hotplug/pci/pcihp.h b/usr/src/uts/common/sys/hotplug/pci/pcihp.h index 75a4ee0c2d..eb96e924bd 100644 --- a/usr/src/uts/common/sys/hotplug/pci/pcihp.h +++ b/usr/src/uts/common/sys/hotplug/pci/pcihp.h @@ -19,15 +19,13 @@ * CDDL HEADER END */ /* - * Copyright 2006 Sun Microsystems, Inc. All rights reserved. + * Copyright 2009 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ #ifndef _SYS_HOTPLUG_PCI_PCIHP_H #define _SYS_HOTPLUG_PCI_PCIHP_H -#pragma ident "%Z%%M% %I% %E% SMI" - #ifdef __cplusplus extern "C" { #endif diff --git a/usr/src/uts/common/sys/hotplug/pci/pcishpc.h b/usr/src/uts/common/sys/hotplug/pci/pcishpc.h index 81443bbaa4..12b9afd30a 100644 --- a/usr/src/uts/common/sys/hotplug/pci/pcishpc.h +++ b/usr/src/uts/common/sys/hotplug/pci/pcishpc.h @@ -18,32 +18,26 @@ * * CDDL HEADER END */ - /* - * Copyright 2006 Sun Microsystems, Inc. All rights reserved. + * Copyright 2009 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ -#ifndef _SYS_PCISHPC_H -#define _SYS_PCISHPC_H - -#pragma ident "%Z%%M% %I% %E% SMI" +#ifndef _SYS_HOTPLUG_PCI_PCISHPC_H +#define _SYS_HOTPLUG_PCI_PCISHPC_H #ifdef __cplusplus extern "C" { #endif -/* - * Interfaces exported by SHPC Nexus extension module - */ - -int pcishpc_init(dev_info_t *); -int pcishpc_uninit(dev_info_t *); -int pcishpc_intr(dev_info_t *); +int pcishpc_init(dev_info_t *dip); +int pcishpc_uninit(dev_info_t *dip); +int pcishpc_intr(dev_info_t *dip); +int pcishpc_hp_ops(dev_info_t *dip, char *cn_name, ddi_hp_op_t op, void *arg, + void *result); -#define PCISHPC_INTR_PRI (LOCK_LEVEL - 1) #ifdef __cplusplus } #endif -#endif /* _SYS_PCISHPC_H */ +#endif /* _SYS_HOTPLUG_PCI_PCISHPC_H */ diff --git a/usr/src/uts/common/sys/hotplug/pci/pcishpc_regs.h b/usr/src/uts/common/sys/hotplug/pci/pcishpc_regs.h deleted file mode 100755 index d487067f59..0000000000 --- a/usr/src/uts/common/sys/hotplug/pci/pcishpc_regs.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * CDDL HEADER START - * - * The contents of this file are subject to the terms of the - * Common Development and Distribution License (the "License"). - * You may not use this file except in compliance with the License. - * - * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE - * or http://www.opensolaris.org/os/licensing. - * See the License for the specific language governing permissions - * and limitations under the License. - * - * When distributing Covered Code, include this CDDL HEADER in each - * file and include the License file at usr/src/OPENSOLARIS.LICENSE. - * If applicable, add the following below this CDDL HEADER, with the - * fields enclosed by brackets "[]" replaced with your own identifying - * information: Portions Copyright [yyyy] [name of copyright owner] - * - * CDDL HEADER END - */ - -/* - * Copyright 2006 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. - */ - -#ifndef _SYS_HOTPLUG_PCI_PCISHPC_REGS_H -#define _SYS_HOTPLUG_PCI_PCISHPC_REGS_H - -#pragma ident "%Z%%M% %I% %E% SMI" - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * SHPC controller registers accessed via the SHPC DWORD select and DATA - * registers in PCI configuration space relative to the SHPC capibility - * pointer. - */ -#define SHPC_DWORD_SELECT_OFF 0x2 -#define SHPC_DWORD_DATA_OFF 0x4 - -#define SHPC_BASE_OFFSET_REG 0x00 -#define SHPC_SLOTS_AVAIL_I_REG 0x01 -#define SHPC_SLOTS_AVAIL_II_REG 0x02 -#define SHPC_SLOT_CONFIGURATION_REG 0x03 -#define SHPC_PROF_IF_SBCR_REG 0x04 -#define SHPC_COMMAND_STATUS_REG 0x05 -#define SHPC_IRQ_LOCATOR_REG 0x06 -#define SHPC_SERR_LOCATOR_REG 0x07 -#define SHPC_CTRL_SERR_INT_REG 0x08 -#define SHPC_LOGICAL_SLOT_REGS 0x09 -#define SHPC_VENDOR_SPECIFIC 0x28 - -#ifdef __cplusplus -} -#endif - -#endif /* _SYS_HOTPLUG_PCI_PCISHPC_REGS_H */ |