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-rw-r--r--usr/src/uts/intel/io/amdzen/amdzen.c96
-rw-r--r--usr/src/uts/intel/io/amdzen/amdzen_client.h4
-rw-r--r--usr/src/uts/intel/io/amdzen/smntemp.c2
-rw-r--r--usr/src/uts/intel/io/amdzen/usmn.c13
-rw-r--r--usr/src/uts/intel/io/amdzen/usmn.h3
-rw-r--r--usr/src/uts/intel/io/amdzen/zen_umc.c72
6 files changed, 134 insertions, 56 deletions
diff --git a/usr/src/uts/intel/io/amdzen/amdzen.c b/usr/src/uts/intel/io/amdzen/amdzen.c
index 8f430a6f6a..62f45ce057 100644
--- a/usr/src/uts/intel/io/amdzen/amdzen.c
+++ b/usr/src/uts/intel/io/amdzen/amdzen.c
@@ -193,6 +193,18 @@ static const amdzen_child_data_t amdzen_children[] = {
{ "zen_umc", AMDZEN_C_ZEN_UMC }
};
+static uint8_t
+amdzen_stub_get8(amdzen_stub_t *stub, off_t reg)
+{
+ return (pci_config_get8(stub->azns_cfgspace, reg));
+}
+
+static uint16_t
+amdzen_stub_get16(amdzen_stub_t *stub, off_t reg)
+{
+ return (pci_config_get16(stub->azns_cfgspace, reg));
+}
+
static uint32_t
amdzen_stub_get32(amdzen_stub_t *stub, off_t reg)
{
@@ -206,6 +218,18 @@ amdzen_stub_get64(amdzen_stub_t *stub, off_t reg)
}
static void
+amdzen_stub_put8(amdzen_stub_t *stub, off_t reg, uint8_t val)
+{
+ pci_config_put8(stub->azns_cfgspace, reg, val);
+}
+
+static void
+amdzen_stub_put16(amdzen_stub_t *stub, off_t reg, uint16_t val)
+{
+ pci_config_put16(stub->azns_cfgspace, reg, val);
+}
+
+static void
amdzen_stub_put32(amdzen_stub_t *stub, off_t reg, uint32_t val)
{
pci_config_put32(stub->azns_cfgspace, reg, val);
@@ -281,22 +305,59 @@ amdzen_df_read32_bcast(amdzen_t *azn, amdzen_df_t *df, const df_reg_def_t def)
return (amdzen_stub_get32(df->adf_funcs[def.drd_func], def.drd_reg));
}
-
static uint32_t
-amdzen_smn_read32(amdzen_t *azn, amdzen_df_t *df, const smn_reg_t reg)
+amdzen_smn_read(amdzen_t *azn, amdzen_df_t *df, const smn_reg_t reg)
{
+ const uint32_t base_addr = SMN_REG_ADDR_BASE(reg);
+ const uint32_t addr_off = SMN_REG_ADDR_OFF(reg);
+
+ VERIFY(SMN_REG_IS_NATURALLY_ALIGNED(reg));
VERIFY(MUTEX_HELD(&azn->azn_mutex));
- amdzen_stub_put32(df->adf_nb, AMDZEN_NB_SMN_ADDR, SMN_REG_ADDR(reg));
- return (amdzen_stub_get32(df->adf_nb, AMDZEN_NB_SMN_DATA));
+ amdzen_stub_put32(df->adf_nb, AMDZEN_NB_SMN_ADDR, base_addr);
+
+ switch (SMN_REG_SIZE(reg)) {
+ case 1:
+ return ((uint32_t)amdzen_stub_get8(df->adf_nb,
+ AMDZEN_NB_SMN_DATA + addr_off));
+ case 2:
+ return ((uint32_t)amdzen_stub_get16(df->adf_nb,
+ AMDZEN_NB_SMN_DATA + addr_off));
+ case 4:
+ return (amdzen_stub_get32(df->adf_nb, AMDZEN_NB_SMN_DATA));
+ default:
+ panic("unreachable invalid SMN register size %u",
+ SMN_REG_SIZE(reg));
+ }
}
static void
-amdzen_smn_write32(amdzen_t *azn, amdzen_df_t *df, const smn_reg_t reg,
+amdzen_smn_write(amdzen_t *azn, amdzen_df_t *df, const smn_reg_t reg,
const uint32_t val)
{
+ const uint32_t base_addr = SMN_REG_ADDR_BASE(reg);
+ const uint32_t addr_off = SMN_REG_ADDR_OFF(reg);
+
+ VERIFY(SMN_REG_IS_NATURALLY_ALIGNED(reg));
+ VERIFY(SMN_REG_VALUE_FITS(reg, val));
VERIFY(MUTEX_HELD(&azn->azn_mutex));
- amdzen_stub_put32(df->adf_nb, AMDZEN_NB_SMN_ADDR, SMN_REG_ADDR(reg));
- amdzen_stub_put32(df->adf_nb, AMDZEN_NB_SMN_DATA, val);
+ amdzen_stub_put32(df->adf_nb, AMDZEN_NB_SMN_ADDR, base_addr);
+
+ switch (SMN_REG_SIZE(reg)) {
+ case 1:
+ amdzen_stub_put8(df->adf_nb, AMDZEN_NB_SMN_DATA + addr_off,
+ (uint8_t)val);
+ break;
+ case 2:
+ amdzen_stub_put16(df->adf_nb, AMDZEN_NB_SMN_DATA + addr_off,
+ (uint16_t)val);
+ break;
+ case 4:
+ amdzen_stub_put32(df->adf_nb, AMDZEN_NB_SMN_DATA, val);
+ break;
+ default:
+ panic("unreachable invalid SMN register size %u",
+ SMN_REG_SIZE(reg));
+ }
}
static amdzen_df_t *
@@ -328,11 +389,16 @@ amdzen_df_find(amdzen_t *azn, uint_t dfno)
* Client functions that are used by nexus children.
*/
int
-amdzen_c_smn_read32(uint_t dfno, const smn_reg_t reg, uint32_t *valp)
+amdzen_c_smn_read(uint_t dfno, const smn_reg_t reg, uint32_t *valp)
{
amdzen_df_t *df;
amdzen_t *azn = amdzen_data;
+ if (!SMN_REG_SIZE_IS_VALID(reg))
+ return (EINVAL);
+ if (!SMN_REG_IS_NATURALLY_ALIGNED(reg))
+ return (EINVAL);
+
mutex_enter(&azn->azn_mutex);
df = amdzen_df_find(azn, dfno);
if (df == NULL) {
@@ -345,17 +411,24 @@ amdzen_c_smn_read32(uint_t dfno, const smn_reg_t reg, uint32_t *valp)
return (ENXIO);
}
- *valp = amdzen_smn_read32(azn, df, reg);
+ *valp = amdzen_smn_read(azn, df, reg);
mutex_exit(&azn->azn_mutex);
return (0);
}
int
-amdzen_c_smn_write32(uint_t dfno, const smn_reg_t reg, const uint32_t val)
+amdzen_c_smn_write(uint_t dfno, const smn_reg_t reg, const uint32_t val)
{
amdzen_df_t *df;
amdzen_t *azn = amdzen_data;
+ if (!SMN_REG_SIZE_IS_VALID(reg))
+ return (EINVAL);
+ if (!SMN_REG_IS_NATURALLY_ALIGNED(reg))
+ return (EINVAL);
+ if (!SMN_REG_VALUE_FITS(reg, val))
+ return (EOVERFLOW);
+
mutex_enter(&azn->azn_mutex);
df = amdzen_df_find(azn, dfno);
if (df == NULL) {
@@ -368,12 +441,11 @@ amdzen_c_smn_write32(uint_t dfno, const smn_reg_t reg, const uint32_t val)
return (ENXIO);
}
- amdzen_smn_write32(azn, df, reg, val);
+ amdzen_smn_write(azn, df, reg, val);
mutex_exit(&azn->azn_mutex);
return (0);
}
-
uint_t
amdzen_c_df_count(void)
{
diff --git a/usr/src/uts/intel/io/amdzen/amdzen_client.h b/usr/src/uts/intel/io/amdzen/amdzen_client.h
index fc82c1039e..d7e2edbb74 100644
--- a/usr/src/uts/intel/io/amdzen/amdzen_client.h
+++ b/usr/src/uts/intel/io/amdzen/amdzen_client.h
@@ -52,8 +52,8 @@ extern int amdzen_c_df_fabric_decomp(df_fabric_decomp_t *);
/*
* SMN and DF access routines.
*/
-extern int amdzen_c_smn_read32(uint_t, const smn_reg_t, uint32_t *);
-extern int amdzen_c_smn_write32(uint_t, const smn_reg_t, const uint32_t);
+extern int amdzen_c_smn_read(uint_t, const smn_reg_t, uint32_t *);
+extern int amdzen_c_smn_write(uint_t, const smn_reg_t, const uint32_t);
extern int amdzen_c_df_read32(uint_t, uint8_t, const df_reg_def_t, uint32_t *);
extern int amdzen_c_df_read64(uint_t, uint8_t, const df_reg_def_t, uint64_t *);
diff --git a/usr/src/uts/intel/io/amdzen/smntemp.c b/usr/src/uts/intel/io/amdzen/smntemp.c
index 94b7aa8b83..43ef57f34e 100644
--- a/usr/src/uts/intel/io/amdzen/smntemp.c
+++ b/usr/src/uts/intel/io/amdzen/smntemp.c
@@ -116,7 +116,7 @@ smntemp_temp_update(smntemp_t *smn, smntemp_temp_t *stt)
ASSERT(MUTEX_HELD((&stt->stt_mutex)));
- if ((ret = amdzen_c_smn_read32(stt->stt_dfno, SMN_SMU_THERMAL_CURTEMP,
+ if ((ret = amdzen_c_smn_read(stt->stt_dfno, SMN_SMU_THERMAL_CURTEMP,
&reg)) != 0) {
return (ret);
}
diff --git a/usr/src/uts/intel/io/amdzen/usmn.c b/usr/src/uts/intel/io/amdzen/usmn.c
index 789e15830e..c9e1608b19 100644
--- a/usr/src/uts/intel/io/amdzen/usmn.c
+++ b/usr/src/uts/intel/io/amdzen/usmn.c
@@ -94,6 +94,13 @@ usmn_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
return (EFAULT);
}
+ /*
+ * We don't need to check size and alignment here; the client access
+ * routines do so for us and return EINVAL if violated. The same goes
+ * for the value to be written in the USMN_WRITE case below.
+ */
+ const smn_reg_t reg = SMN_MAKE_REG_SIZED(usr.usr_addr, usr.usr_size);
+
if (cmd == USMN_READ) {
int ret;
@@ -101,8 +108,7 @@ usmn_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
return (EINVAL);
}
- ret = amdzen_c_smn_read32(dfno, SMN_MAKE_REG(usr.usr_addr),
- &usr.usr_data);
+ ret = amdzen_c_smn_read(dfno, reg, &usr.usr_data);
if (ret != 0) {
return (ret);
}
@@ -113,8 +119,7 @@ usmn_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
return (EINVAL);
}
- ret = amdzen_c_smn_write32(dfno, SMN_MAKE_REG(usr.usr_addr),
- usr.usr_data);
+ ret = amdzen_c_smn_write(dfno, reg, usr.usr_data);
if (ret != 0) {
return (ret);
}
diff --git a/usr/src/uts/intel/io/amdzen/usmn.h b/usr/src/uts/intel/io/amdzen/usmn.h
index 10f057525d..0ee86ff7d3 100644
--- a/usr/src/uts/intel/io/amdzen/usmn.h
+++ b/usr/src/uts/intel/io/amdzen/usmn.h
@@ -10,7 +10,7 @@
*/
/*
- * Copyright 2020 Oxide Computer Company
+ * Copyright 2022 Oxide Computer Company
*/
#ifndef _USMN_H
@@ -32,6 +32,7 @@ extern "C" {
typedef struct usmn_reg {
uint32_t usr_addr;
uint32_t usr_data;
+ uint32_t usr_size;
} usmn_reg_t;
#ifdef __cplusplus
diff --git a/usr/src/uts/intel/io/amdzen/zen_umc.c b/usr/src/uts/intel/io/amdzen/zen_umc.c
index 947c17b4ff..1a00ec29c3 100644
--- a/usr/src/uts/intel/io/amdzen/zen_umc.c
+++ b/usr/src/uts/intel/io/amdzen/zen_umc.c
@@ -1863,7 +1863,7 @@ zen_umc_fill_dimm_common(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
} else {
reg = UMC_DIMMCFG_DDR5(id, dimmno);
}
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read DIMM "
"configuration register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -1939,7 +1939,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
uint64_t addr;
const uint16_t reginst = i + dimmno * 2;
reg = UMC_BASE(id, reginst);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read base "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -1950,7 +1950,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
dimm->ud_cs[i].ucs_base.udb_valid = UMC_BASE_GET_EN(val);
reg = UMC_BASE_SEC(id, reginst);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"secondary base register %x: %d", SMN_REG_ADDR(reg),
ret);
@@ -1963,7 +1963,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
}
reg = UMC_MASK_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read mask register "
"%x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -1979,7 +1979,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
cs1->ucs_base_mask = cs0->ucs_base_mask;
reg = UMC_MASK_SEC_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read secondary mask "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -1990,7 +1990,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
cs1->ucs_sec_mask = cs0->ucs_sec_mask;
reg = UMC_ADDRCFG_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read address config "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2026,7 +2026,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
}
reg = UMC_ADDRSEL_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read bank address "
"select register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2051,7 +2051,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
sizeof (cs0->ucs_bank_bits));
reg = UMC_COLSEL_LO_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read column address "
"select low register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2062,7 +2062,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
}
reg = UMC_COLSEL_HI_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read column address "
"select high register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2081,7 +2081,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
* zero.
*/
reg = UMC_RMSEL_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read rank address "
"select register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2097,7 +2097,7 @@ zen_umc_fill_chan_dimm_ddr4(zen_umc_t *umc, zen_umc_df_t *df,
bcopy(cs0->ucs_rm_bits, cs1->ucs_rm_bits, sizeof (cs0->ucs_rm_bits));
reg = UMC_RMSEL_SEC_DDR4(id, dimmno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read secondary rank "
"address select register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2137,7 +2137,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
cs = &chan->chan_dimms[dimmno].ud_cs[rankno];
reg = UMC_BASE(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read base "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2149,7 +2149,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
uint64_t addr;
reg = UMC_BASE_EXT_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) !=
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) !=
0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"extended base register %x: %d", SMN_REG_ADDR(reg),
@@ -2163,7 +2163,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
}
reg = UMC_BASE_SEC(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read secondary base "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2175,7 +2175,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
uint64_t addr;
reg = UMC_BASE_EXT_SEC_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) !=
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) !=
0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"extended secondary base register %x: %d",
@@ -2189,7 +2189,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
}
reg = UMC_MASK_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read mask "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2201,7 +2201,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
uint64_t addr;
reg = UMC_MASK_EXT_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) !=
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) !=
0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"extended mask register %x: %d", SMN_REG_ADDR(reg),
@@ -2216,7 +2216,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
reg = UMC_MASK_SEC_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read secondary mask "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2228,7 +2228,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
uint64_t addr;
reg = UMC_MASK_EXT_SEC_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) !=
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) !=
0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"extended mask register %x: %d", SMN_REG_ADDR(reg),
@@ -2242,7 +2242,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
}
reg = UMC_ADDRCFG_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read address config "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2263,7 +2263,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
cs->ucs_nbank_groups = UMC_ADDRCFG_GET_NBANKGRP_BITS(val);
reg = UMC_ADDRSEL_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read address select "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2283,7 +2283,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
UMC_ADDRSEL_BANK_BASE;
reg = UMC_COLSEL_LO_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read column address "
"select low register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2294,7 +2294,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
}
reg = UMC_COLSEL_HI_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read column address "
"select high register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2311,7 +2311,7 @@ zen_umc_fill_chan_rank_ddr5(zen_umc_t *umc, zen_umc_df_t *df,
* unless something actually points us there.
*/
reg = UMC_RMSEL_DDR5(id, regno);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read rank multiply "
"select register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2408,7 +2408,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
reg = UMC_BANK_HASH_DDR5(id, i);
}
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg,
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg,
&val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"bank hash register %x: %d",
@@ -2433,7 +2433,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
reg = UMC_RANK_HASH_DDR5(id, i);
}
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg,
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg,
&val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"rm hash register %x: %d",
@@ -2451,7 +2451,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
}
reg = UMC_RANK_HASH_EXT_DDR5(id, i);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg,
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg,
&val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"rm hash ext register %x: %d",
@@ -2474,7 +2474,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
reg = UMC_PC_HASH_DDR5(id);
}
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read pc hash "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2490,7 +2490,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
reg = UMC_PC_HASH2_DDR5(id);
}
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read pc hash "
"2 register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2510,7 +2510,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
reg = UMC_CS_HASH_DDR5(id, i);
}
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg,
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg,
&val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"cs hash register %x", SMN_REG_ADDR(reg));
@@ -2527,7 +2527,7 @@ zen_umc_fill_chan_hash(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan,
}
reg = UMC_CS_HASH_EXT_DDR5(id, i);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg,
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg,
&val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read "
"cs hash ext register %x",
@@ -2573,7 +2573,7 @@ zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
}
reg = UMC_UMCCFG(id);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read UMC "
"configuration register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2596,7 +2596,7 @@ zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
* encrypting regions of memory.
*/
reg = UMC_DATACTL(id);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read data control "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2617,7 +2617,7 @@ zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
* cache it for future us and observability.
*/
reg = UMC_ECCCTL(id);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read ECC control "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2629,7 +2629,7 @@ zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
* future.
*/
reg = UMC_UMCCAP(id);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read UMC cap"
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
@@ -2637,7 +2637,7 @@ zen_umc_fill_chan(zen_umc_t *umc, zen_umc_df_t *df, zen_umc_chan_t *chan)
chan->chan_umccap_raw = val;
reg = UMC_UMCCAP_HI(id);
- if ((ret = amdzen_c_smn_read32(df->zud_dfno, reg, &val)) != 0) {
+ if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
dev_err(umc->umc_dip, CE_WARN, "failed to read UMC cap high "
"register %x: %d", SMN_REG_ADDR(reg), ret);
return (B_FALSE);
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-01 17:16:30 +0000