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-rw-r--r--usr/src/uts/sun4/io/px/px.c13
-rw-r--r--usr/src/uts/sun4/io/px/px_intr.c47
-rw-r--r--usr/src/uts/sun4/io/px/px_pci.c14
-rw-r--r--usr/src/uts/sun4/io/px/px_pec.c33
4 files changed, 44 insertions, 63 deletions
diff --git a/usr/src/uts/sun4/io/px/px.c b/usr/src/uts/sun4/io/px/px.c
index 43c306fc7e..67ccc3ca95 100644
--- a/usr/src/uts/sun4/io/px/px.c
+++ b/usr/src/uts/sun4/io/px/px.c
@@ -444,6 +444,8 @@ px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
ddi_remove_minor_node(dip, "devctl");
px_err_rem_intr(&px_p->px_fault);
px_pec_detach(px_p);
+ px_pwr_teardown(dip);
+ pwr_common_teardown(dip);
px_msi_detach(px_p);
px_msiq_detach(px_p);
px_mmu_detach(px_p);
@@ -457,8 +459,6 @@ px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
* resources it's using.
*/
px_free_props(px_p);
- px_pwr_teardown(dip);
- pwr_common_teardown(dip);
mutex_exit(&px_p->px_mutex);
mutex_destroy(&px_p->px_mutex);
ddi_soft_state_free(px_state_p, instance);
@@ -1295,9 +1295,6 @@ px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
/* Process DDI_INTROP_SUPPORTED_TYPES request here */
if (intr_op == DDI_INTROP_SUPPORTED_TYPES) {
- px_t *px_p = DIP_TO_STATE(dip);
- px_msi_state_t *msi_state_p = &px_p->px_ib_p->ib_msi_state;
-
*(int *)result = i_ddi_get_nintrs(rdip) ?
DDI_INTR_TYPE_FIXED : 0;
@@ -1306,8 +1303,12 @@ px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
/*
* Double check supported interrupt types vs.
* what the host bridge supports.
+ *
+ * NOTE:
+ * Currently MSI-X is disabled since px driver
+ * don't fully support this feature.
*/
- *(int *)result |= (intr_types & msi_state_p->msi_type);
+ *(int *)result |= (intr_types & DDI_INTR_TYPE_MSI);
}
return (ret);
diff --git a/usr/src/uts/sun4/io/px/px_intr.c b/usr/src/uts/sun4/io/px/px_intr.c
index 7261709dd8..c4b9a23323 100644
--- a/usr/src/uts/sun4/io/px/px_intr.c
+++ b/usr/src/uts/sun4/io/px/px_intr.c
@@ -582,9 +582,6 @@ px_intx_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
case DDI_INTROP_NAVAIL:
*(int *)result = i_ddi_get_nintrs(rdip);
break;
- case DDI_INTROP_SUPPORTED_TYPES:
- *(int *)result = DDI_INTR_TYPE_FIXED;
- break;
default:
ret = DDI_ENOTSUP;
break;
@@ -600,6 +597,9 @@ px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
{
px_t *px_p = DIP_TO_STATE(dip);
px_msi_state_t *msi_state_p = &px_p->px_ib_p->ib_msi_state;
+ msiq_rec_type_t msiq_rec_type;
+ msi_type_t msi_type;
+ uint64_t msi_addr;
msinum_t msi_num;
msiqid_t msiq_id;
uint_t nintrs;
@@ -608,6 +608,18 @@ px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
DBG(DBG_INTROPS, dip, "px_msix_ops: dip=%x rdip=%x intr_op=%x "
"handle=%p\n", dip, rdip, intr_op, hdlp);
+ /* Check for MSI64 support */
+ if (hdlp->ih_cap & DDI_INTR_FLAG_MSI64) {
+ msiq_rec_type = MSI64_REC;
+ msi_type = MSI64_TYPE;
+ msi_addr = msi_state_p->msi_addr64 ?
+ msi_state_p->msi_addr64:msi_state_p->msi_addr32;
+ } else {
+ msiq_rec_type = MSI32_REC;
+ msi_type = MSI32_TYPE;
+ msi_addr = msi_state_p->msi_addr32;
+ }
+
switch (intr_op) {
case DDI_INTROP_GETCAP:
ret = pci_msi_get_cap(rdip, hdlp->ih_type, (int *)result);
@@ -650,7 +662,7 @@ px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
return (ret);
if ((ret = px_add_msiq_intr(dip, rdip, hdlp,
- MSI32_REC, msi_num, &msiq_id)) != DDI_SUCCESS) {
+ msiq_rec_type, msi_num, &msiq_id)) != DDI_SUCCESS) {
DBG(DBG_INTROPS, dip, "px_msix_ops: Add MSI handler "
"failed, rdip 0x%p msi 0x%x\n", rdip, msi_num);
return (ret);
@@ -659,16 +671,16 @@ px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
DBG(DBG_INTROPS, dip, "px_msix_ops: msiq used 0x%x\n", msiq_id);
if ((ret = px_lib_msi_setmsiq(dip, msi_num,
- msiq_id, MSI32_TYPE)) != DDI_SUCCESS) {
+ msiq_id, msi_type)) != DDI_SUCCESS) {
(void) px_rem_msiq_intr(dip, rdip,
- hdlp, MSI32_REC, msi_num, msiq_id);
+ hdlp, msiq_rec_type, msi_num, msiq_id);
return (ret);
}
if ((ret = px_lib_msi_setstate(dip, msi_num,
PCI_MSI_STATE_IDLE)) != DDI_SUCCESS) {
(void) px_rem_msiq_intr(dip, rdip,
- hdlp, MSI32_REC, msi_num, msiq_id);
+ hdlp, msiq_rec_type, msi_num, msiq_id);
return (ret);
}
@@ -686,11 +698,11 @@ px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
return (ret);
if ((ret = px_lib_msi_setstate(dip, msi_num,
- PCI_MSI_STATE_DELIVERED)) != DDI_SUCCESS)
+ PCI_MSI_STATE_IDLE)) != DDI_SUCCESS)
return (ret);
ret = px_rem_msiq_intr(dip, rdip,
- hdlp, MSI32_REC, msi_num, msiq_id);
+ hdlp, msiq_rec_type, msi_num, msiq_id);
hdlp->ih_vector = 0;
break;
@@ -705,7 +717,7 @@ px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip);
if ((ret = pci_msi_configure(rdip, hdlp->ih_type,
- nintrs, hdlp->ih_inum, msi_state_p->msi_addr32,
+ nintrs, hdlp->ih_inum, msi_addr,
msi_num & ~(nintrs - 1))) != DDI_SUCCESS)
return (ret);
@@ -724,7 +736,7 @@ px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum,
px_msiqid_to_devino(px_p, msiq_id), PX_INTR_STATE_ENABLE,
- MSI32_REC, msi_num);
+ msiq_rec_type, msi_num);
break;
case DDI_INTROP_DISABLE:
@@ -744,7 +756,7 @@ px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
ret = px_ib_update_intr_state(px_p, rdip,
hdlp->ih_inum, px_msiqid_to_devino(px_p, msiq_id),
- PX_INTR_STATE_DISABLE, MSI32_REC, msi_num);
+ PX_INTR_STATE_DISABLE, msiq_rec_type, msi_num);
break;
case DDI_INTROP_BLOCKENABLE:
@@ -752,7 +764,7 @@ px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
msi_num = hdlp->ih_vector;
if ((ret = pci_msi_configure(rdip, hdlp->ih_type,
- nintrs, hdlp->ih_inum, msi_state_p->msi_addr32,
+ nintrs, hdlp->ih_inum, msi_addr,
msi_num & ~(nintrs - 1))) != DDI_SUCCESS)
return (ret);
@@ -767,8 +779,8 @@ px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
if ((ret = px_ib_update_intr_state(px_p, rdip,
hdlp->ih_inum + i, px_msiqid_to_devino(px_p,
- msiq_id), PX_INTR_STATE_ENABLE, MSI32_REC, msi_num))
- != DDI_SUCCESS)
+ msiq_id), PX_INTR_STATE_ENABLE, msiq_rec_type,
+ msi_num)) != DDI_SUCCESS)
return (ret);
}
@@ -793,7 +805,7 @@ px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
if ((ret = px_ib_update_intr_state(px_p, rdip,
hdlp->ih_inum + i, px_msiqid_to_devino(px_p,
- msiq_id), PX_INTR_STATE_DISABLE, MSI32_REC,
+ msiq_id), PX_INTR_STATE_DISABLE, msiq_rec_type,
msi_num)) != DDI_SUCCESS)
return (ret);
}
@@ -816,9 +828,6 @@ px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
/* XXX - a new interface may be needed */
ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result);
break;
- case DDI_INTROP_SUPPORTED_TYPES:
- ret = pci_msi_get_supported_type(rdip, (int *)result);
- break;
default:
ret = DDI_ENOTSUP;
break;
diff --git a/usr/src/uts/sun4/io/px/px_pci.c b/usr/src/uts/sun4/io/px/px_pci.c
index c3f6ac5e0b..02be175437 100644
--- a/usr/src/uts/sun4/io/px/px_pci.c
+++ b/usr/src/uts/sun4/io/px/px_pci.c
@@ -50,6 +50,13 @@
#include "px_pci.h"
#include "px_debug.h"
+/*
+ * PXB MSI tunable:
+ *
+ * By default MSI is enabled on all supported platforms.
+ */
+boolean_t pxb_enable_msi = B_TRUE;
+
static int pxb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *,
off_t, off_t, caddr_t *);
static int pxb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t,
@@ -370,10 +377,7 @@ pxb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
goto fail;
}
- /* Do not support FIXED interrupts at this time, only MSI */
- intr_types &= ~DDI_INTR_TYPE_FIXED;
-
- if (intr_types & DDI_INTR_TYPE_MSI) {
+ if ((intr_types & DDI_INTR_TYPE_MSI) && pxb_enable_msi) {
if (pxb_intr_init(pxb, DDI_INTR_TYPE_MSI) == DDI_SUCCESS)
intr_types = DDI_INTR_TYPE_MSI;
else
@@ -935,7 +939,7 @@ pxb_intr_init(pxb_devstate_t *pxb, int intr_type) {
pxb->pxb_init_flags |= PXB_INIT_HTABLE;
ret = ddi_intr_alloc(dip, pxb->pxb_htable, intr_type,
- 0, request, &count, 0);
+ 0, request, &count, DDI_INTR_ALLOC_NORMAL);
if ((ret != DDI_SUCCESS) || (count == 0)) {
DBG(DBG_ATTACH, dip,
"ddi_intr_alloc() ret: %d ask: %d actual: %d\n",
diff --git a/usr/src/uts/sun4/io/px/px_pec.c b/usr/src/uts/sun4/io/px/px_pec.c
index 173e906d15..8da111855d 100644
--- a/usr/src/uts/sun4/io/px/px_pec.c
+++ b/usr/src/uts/sun4/io/px/px_pec.c
@@ -121,38 +121,17 @@ px_pec_attach(px_t *px_p)
*pfnlp = mmu_btop(rng_addr + rng_size);
}
- /*
- * Register a function to disable pec error interrupts during a panic.
- * do in px_attach. bus_func_register(BF_TYPE_ERRDIS,
- * (busfunc_t)pec_disable_pci_errors, pec_p);
- */
-
mutex_init(&pec_p->pec_pokefault_mutex, NULL, MUTEX_DRIVER,
(void *)px_p->px_fm_ibc);
return (DDI_SUCCESS);
}
-uint_t
-pec_disable_px_errors(px_pec_t *pec_p)
-{
- px_t *px_p = pec_p->pec_px_p;
- px_ib_t *ib_p = px_p->px_ib_p;
-
- /*
- * Disable error interrupts via the interrupt mapping register.
- */
- px_ib_intr_disable(ib_p, px_p->px_inos[PX_INTR_PEC], IB_INTR_NOWAIT);
- return (BF_NONE);
-}
-
void
px_pec_detach(px_t *px_p)
{
dev_info_t *dip = px_p->px_dip;
px_pec_t *pec_p = px_p->px_pec_p;
- px_ib_t *ib_p = px_p->px_ib_p;
- devino_t ino = px_p->px_inos[PX_INTR_PEC];
/*
* Free the pokefault mutex.
@@ -161,18 +140,6 @@ px_pec_detach(px_t *px_p)
mutex_destroy(&pec_p->pec_pokefault_mutex);
/*
- * Remove the pci error interrupt handler.
- */
- px_ib_intr_disable(ib_p, ino, IB_INTR_WAIT);
- ddi_remove_intr(dip, 0, NULL);
-
- /*
- * Remove the error disable function.
- */
- bus_func_unregister(BF_TYPE_ERRDIS,
- (busfunc_t)pec_disable_px_errors, pec_p);
-
- /*
* Remove interrupt handlers to process correctable/fatal/non fatal
* PCIE messages.
*/
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-18 02:54:40 +0000