diff options
Diffstat (limited to 'usr/src/uts/sun4u/io/pci/pci_iommu.c')
| -rw-r--r-- | usr/src/uts/sun4u/io/pci/pci_iommu.c | 134 |
1 files changed, 67 insertions, 67 deletions
diff --git a/usr/src/uts/sun4u/io/pci/pci_iommu.c b/usr/src/uts/sun4u/io/pci/pci_iommu.c index 0ae6e22e96..cc225aa0dc 100644 --- a/usr/src/uts/sun4u/io/pci/pci_iommu.c +++ b/usr/src/uts/sun4u/io/pci/pci_iommu.c @@ -22,8 +22,9 @@ * Copyright 2006 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ - -#pragma ident "%Z%%M% %I% %E% SMI" +/* + * Copyright 2012 Garrett D'Amore <garrett@damore.org>. All rights reserved. + */ /* * PCI iommu initialization and configuration @@ -78,26 +79,26 @@ iommu_create(pci_t *pci_p) * Determine the virtual address of iommu registers. */ iommu_p->iommu_ctrl_reg = - (uint64_t *)(a + COMMON_IOMMU_CTRL_REG_OFFSET); + (uint64_t *)(a + COMMON_IOMMU_CTRL_REG_OFFSET); iommu_p->iommu_tsb_base_addr_reg = - (uint64_t *)(a + COMMON_IOMMU_TSB_BASE_ADDR_REG_OFFSET); + (uint64_t *)(a + COMMON_IOMMU_TSB_BASE_ADDR_REG_OFFSET); iommu_p->iommu_flush_page_reg = - (uint64_t *)(a + COMMON_IOMMU_FLUSH_PAGE_REG_OFFSET); + (uint64_t *)(a + COMMON_IOMMU_FLUSH_PAGE_REG_OFFSET); /* * Configure the rest of the iommu parameters according to: * tsb_size and dvma_end */ iommu_p->iommu_tsb_vaddr = /* retrieve TSB VA reserved by system */ - iommu_tsb_cookie_to_va(pci_p->pci_tsb_cookie); + iommu_tsb_cookie_to_va(pci_p->pci_tsb_cookie); iommu_p->iommu_tsb_entries = tsb_entries = - IOMMU_TSBSIZE_TO_TSBENTRIES(iommu_p->iommu_tsb_size); + IOMMU_TSBSIZE_TO_TSBENTRIES(iommu_p->iommu_tsb_size); iommu_p->iommu_tsb_paddr = va_to_pa((caddr_t)iommu_p->iommu_tsb_vaddr); iommu_p->iommu_dvma_cache_locks = - kmem_zalloc(pci_dvma_page_cache_entries, KM_SLEEP); + kmem_zalloc(pci_dvma_page_cache_entries, KM_SLEEP); iommu_p->iommu_dvma_base = iommu_p->iommu_dvma_end + 1 - - (tsb_entries * IOMMU_PAGE_SIZE); + - (tsb_entries * IOMMU_PAGE_SIZE); iommu_p->dvma_base_pg = IOMMU_BTOP(iommu_p->iommu_dvma_base); iommu_p->iommu_dvma_reserve = tsb_entries >> 1; iommu_p->dvma_end_pg = IOMMU_BTOP(iommu_p->iommu_dvma_end); @@ -110,29 +111,29 @@ iommu_create(pci_t *pci_p) */ pci_dvma_range.dvma_base = (uint32_t)iommu_p->iommu_dvma_base; pci_dvma_range.dvma_len = (uint32_t) - iommu_p->iommu_dvma_end - iommu_p->iommu_dvma_base + 1; + iommu_p->iommu_dvma_end - iommu_p->iommu_dvma_base + 1; (void) ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP, - "virtual-dma", (caddr_t)&pci_dvma_range, - sizeof (pci_dvma_range)); + "virtual-dma", (caddr_t)&pci_dvma_range, + sizeof (pci_dvma_range)); DEBUG2(DBG_ATTACH, dip, "iommu_create: ctrl=%p, tsb=%p\n", - iommu_p->iommu_ctrl_reg, iommu_p->iommu_tsb_base_addr_reg); + iommu_p->iommu_ctrl_reg, iommu_p->iommu_tsb_base_addr_reg); DEBUG2(DBG_ATTACH, dip, "iommu_create: page_flush=%p, ctx_flush=%p\n", - iommu_p->iommu_flush_page_reg, iommu_p->iommu_flush_ctx_reg); + iommu_p->iommu_flush_page_reg, iommu_p->iommu_flush_ctx_reg); DEBUG2(DBG_ATTACH, dip, "iommu_create: tsb vaddr=%p tsb_paddr=%p\n", - iommu_p->iommu_tsb_vaddr, iommu_p->iommu_tsb_paddr); + iommu_p->iommu_tsb_vaddr, iommu_p->iommu_tsb_paddr); DEBUG1(DBG_ATTACH, dip, "iommu_create: allocated size=%x\n", - iommu_tsb_cookie_to_size(pci_p->pci_tsb_cookie)); + iommu_tsb_cookie_to_size(pci_p->pci_tsb_cookie)); DEBUG2(DBG_ATTACH, dip, "iommu_create: fast tsb tte addr: %x + %x\n", - iommu_p->iommu_tsb_vaddr, - pci_dvma_page_cache_entries * pci_dvma_page_cache_clustsz); + iommu_p->iommu_tsb_vaddr, + pci_dvma_page_cache_entries * pci_dvma_page_cache_clustsz); DEBUG3(DBG_ATTACH, dip, - "iommu_create: tsb size=%x, tsb entries=%x, dvma base=%x\n", - iommu_p->iommu_tsb_size, iommu_p->iommu_tsb_entries, - iommu_p->iommu_dvma_base); + "iommu_create: tsb size=%x, tsb entries=%x, dvma base=%x\n", + iommu_p->iommu_tsb_size, iommu_p->iommu_tsb_entries, + iommu_p->iommu_dvma_base); DEBUG2(DBG_ATTACH, dip, - "iommu_create: dvma_cache_locks=%x cache_entries=%x\n", - iommu_p->iommu_dvma_cache_locks, pci_dvma_page_cache_entries); + "iommu_create: dvma_cache_locks=%x cache_entries=%x\n", + iommu_p->iommu_dvma_cache_locks, pci_dvma_page_cache_entries); /* * zero out the area to be used for iommu tsb @@ -144,16 +145,16 @@ iommu_create(pci_t *pci_p) * Reserve 'size' bytes of low dvma space for fast track cache. */ (void) snprintf(map_name, sizeof (map_name), "%s%d_dvma", - ddi_driver_name(dip), ddi_get_instance(dip)); + ddi_driver_name(dip), ddi_get_instance(dip)); cache_size = IOMMU_PTOB(pci_dvma_page_cache_entries * - pci_dvma_page_cache_clustsz); + pci_dvma_page_cache_clustsz); iommu_p->iommu_dvma_fast_end = iommu_p->iommu_dvma_base + - cache_size - 1; + cache_size - 1; iommu_p->iommu_dvma_map = vmem_create(map_name, - (void *)(iommu_p->iommu_dvma_fast_end + 1), - IOMMU_PTOB(tsb_entries) - cache_size, IOMMU_PAGE_SIZE, - NULL, NULL, NULL, IOMMU_PAGE_SIZE, VM_SLEEP); + (void *)(iommu_p->iommu_dvma_fast_end + 1), + IOMMU_PTOB(tsb_entries) - cache_size, IOMMU_PAGE_SIZE, + NULL, NULL, NULL, IOMMU_PAGE_SIZE, VM_SLEEP); mutex_init(&iommu_p->dvma_debug_lock, NULL, MUTEX_DRIVER, NULL); @@ -229,14 +230,13 @@ iommu_configure(iommu_t *iommu_p) dev_info_t *dip = iommu_p->iommu_pci_p->pci_dip; dev_info_t *cdip = NULL; volatile uint64_t ctl_val = (uint64_t) - ((iommu_p->iommu_tsb_size << COMMON_IOMMU_CTRL_TSB_SZ_SHIFT) | - (0 /* 8k page */ << COMMON_IOMMU_CTRL_TBW_SZ_SHIFT) | - COMMON_IOMMU_CTRL_ENABLE | - COMMON_IOMMU_CTRL_DIAG_ENABLE | - (pci_lock_tlb ? COMMON_IOMMU_CTRL_LCK_ENABLE : 0)); + ((iommu_p->iommu_tsb_size << COMMON_IOMMU_CTRL_TSB_SZ_SHIFT) | + (0 /* 8k page */ << COMMON_IOMMU_CTRL_TBW_SZ_SHIFT) | + COMMON_IOMMU_CTRL_ENABLE | COMMON_IOMMU_CTRL_DIAG_ENABLE | + (pci_lock_tlb ? COMMON_IOMMU_CTRL_LCK_ENABLE : 0)); DEBUG2(DBG_ATTACH, dip, "iommu_configure: iommu_ctl=%08x.%08x\n", - HI32(ctl_val), LO32(ctl_val)); + HI32(ctl_val), LO32(ctl_val)); if (!pci_preserve_iommu_tsb || !(*iommu_p->iommu_tsb_base_addr_reg)) { *iommu_p->iommu_ctrl_reg = COMMON_IOMMU_CTRL_DIAG_ENABLE; iommu_tlb_flushall(iommu_p); @@ -247,7 +247,7 @@ iommu_configure(iommu_t *iommu_p) uint32_t *reg_p; int reg_len; if (ddi_getlongprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, - "reg", (caddr_t)®_p, ®_len) != DDI_PROP_SUCCESS) + "reg", (caddr_t)®_p, ®_len) != DDI_PROP_SUCCESS) continue; cfgpa += (*reg_p) & (PCI_CONF_ADDR_MASK ^ PCI_REG_REG_M); kmem_free(reg_p, reg_len); @@ -274,45 +274,45 @@ iommu_map_pages(iommu_t *iommu_p, ddi_dma_impl_t *mp, ASSERT(pfn_last <= mp->dmai_ndvmapages); DEBUG5(DBG_MAP_WIN, dip, - "iommu_map_pages:%x+%x=%x npages=0x%x pfn_index=0x%x\n", - (uint_t)iommu_p->dvma_base_pg, (uint_t)pg_index, dvma_pg, - (uint_t)npages, (uint_t)pfn_index); + "iommu_map_pages:%x+%x=%x npages=0x%x pfn_index=0x%x\n", + (uint_t)iommu_p->dvma_base_pg, (uint_t)pg_index, dvma_pg, + (uint_t)npages, (uint_t)pfn_index); for (i = pfn_index; i < pfn_last; i++, pg_index++, tte_addr++) { iopfn_t pfn = PCI_GET_MP_PFN(mp, i); volatile uint64_t cur_tte = IOMMU_PTOB(pfn) | tte; DEBUG3(DBG_MAP_WIN, dip, "iommu_map_pages: mp=%p pg[%x]=%x\n", - mp, i, (uint_t)pfn); + mp, i, (uint_t)pfn); DEBUG3(DBG_MAP_WIN, dip, - "iommu_map_pages: pg_index=%x tte=%08x.%08x\n", - pg_index, HI32(cur_tte), LO32(cur_tte)); + "iommu_map_pages: pg_index=%x tte=%08x.%08x\n", + pg_index, HI32(cur_tte), LO32(cur_tte)); ASSERT(TTE_IS_INVALID(*tte_addr)); *tte_addr = cur_tte; #ifdef DEBUG if (pfn == 0 && pci_warn_pp0) cmn_err(CE_WARN, "%s%d <%p> doing DMA to pp0\n", - ddi_driver_name(mp->dmai_rdip), - ddi_get_instance(mp->dmai_rdip), mp); + ddi_driver_name(mp->dmai_rdip), + ddi_get_instance(mp->dmai_rdip), mp); #endif } ASSERT(tte_addr == iommu_p->iommu_tsb_vaddr + pg_index); #ifdef DEBUG if (HAS_REDZONE(mp)) { DEBUG1(DBG_MAP_WIN, dip, "iommu_map_pages: redzone pg=%x\n", - pg_index); + pg_index); ASSERT(TTE_IS_INVALID(iommu_p->iommu_tsb_vaddr[pg_index])); } #endif if (DVMA_DBG_ON(iommu_p)) pci_dvma_alloc_debug(iommu_p, (char *)mp->dmai_mapping, - mp->dmai_size, mp); + mp->dmai_size, mp); } /* * iommu_map_window - map a dvma window into the iommu * - * used by: pci_dma_win(), pci_dma_ctlops() - DDI_DMA_MOVWIN, DDI_DMA_NEXTWIN + * used by: pci_dma_win(), pci_dma_ctlops() - DDI_DMA_MOVWIN * * return value: none */ @@ -404,7 +404,7 @@ iommu_unmap_window(iommu_t *iommu_p, ddi_dma_impl_t *mp) if (DVMA_DBG_ON(iommu_p)) pci_dvma_free_debug(iommu_p, (char *)mp->dmai_mapping, - mp->dmai_size, mp); + mp->dmai_size, mp); } int @@ -465,11 +465,11 @@ iommu_tlb_flushall(iommu_t *iommu_p) { int i; uint64_t base = (uint64_t)(iommu_p->iommu_ctrl_reg) - - COMMON_IOMMU_CTRL_REG_OFFSET; + COMMON_IOMMU_CTRL_REG_OFFSET; volatile uint64_t *tlb_tag = (volatile uint64_t *) - (base + COMMON_IOMMU_TLB_TAG_DIAG_ACC_OFFSET); + (base + COMMON_IOMMU_TLB_TAG_DIAG_ACC_OFFSET); volatile uint64_t *tlb_data = (volatile uint64_t *) - (base + COMMON_IOMMU_TLB_DATA_DIAG_ACC_OFFSET); + (base + COMMON_IOMMU_TLB_DATA_DIAG_ACC_OFFSET); for (i = 0; i < IOMMU_TLB_ENTRIES; i++) tlb_tag[i] = tlb_data[i] = 0ull; } @@ -486,32 +486,32 @@ iommu_preserve_tsb(iommu_t *iommu_p) uint64_t *base_tte_addr; DEBUG3(DBG_ATTACH, dip, - "iommu_tsb_base_addr_reg=0x%08x (0x%08x.0x%08x)\n", - iommu_p->iommu_tsb_base_addr_reg, - (uint32_t)(*iommu_p->iommu_tsb_base_addr_reg >> 32), - (uint32_t)(*iommu_p->iommu_tsb_base_addr_reg & 0xffffffff)); + "iommu_tsb_base_addr_reg=0x%08x (0x%08x.0x%08x)\n", + iommu_p->iommu_tsb_base_addr_reg, + (uint32_t)(*iommu_p->iommu_tsb_base_addr_reg >> 32), + (uint32_t)(*iommu_p->iommu_tsb_base_addr_reg & 0xffffffff)); obp_tsb_size = IOMMU_CTL_TO_TSBSIZE(ctl); obp_tsb_entries = IOMMU_TSBSIZE_TO_TSBENTRIES(obp_tsb_size); base_pg_index = iommu_p->dvma_end_pg - obp_tsb_entries + 1; base_tte_addr = iommu_p->iommu_tsb_vaddr + - (iommu_p->iommu_tsb_entries - obp_tsb_entries); + (iommu_p->iommu_tsb_entries - obp_tsb_entries); /* * old darwin prom does not set tsb size correctly, bail out. */ if ((obp_tsb_size == IOMMU_DARWIN_BOGUS_TSBSIZE) && - (CHIP_TYPE(iommu_p->iommu_pci_p) == PCI_CHIP_SABRE)) - return; + (CHIP_TYPE(iommu_p->iommu_pci_p) == PCI_CHIP_SABRE)) + return; DEBUG3(DBG_ATTACH, dip, "iommu_preserve_tsb: kernel info\n" - "iommu_tsb_vaddr=%08x copy to base_tte_addr=%08x " - "base_pg_index=%x\n", iommu_p->iommu_tsb_vaddr, - base_tte_addr, base_pg_index); + "iommu_tsb_vaddr=%08x copy to base_tte_addr=%08x " + "base_pg_index=%x\n", iommu_p->iommu_tsb_vaddr, + base_tte_addr, base_pg_index); DEBUG3(DBG_ATTACH | DBG_CONT, dip, "iommu_preserve_tsb: obp info " - "obp_tsb_entries=0x%x obp_tsb_pa=%08x.%08x\n", obp_tsb_entries, - (uint32_t)(obp_tsb_pa >> 32), (uint32_t)obp_tsb_pa); + "obp_tsb_entries=0x%x obp_tsb_pa=%08x.%08x\n", obp_tsb_entries, + (uint32_t)(obp_tsb_pa >> 32), (uint32_t)obp_tsb_pa); for (i = 0; i < obp_tsb_entries; i++) { uint64_t tte = lddphys(obp_tsb_pa + i * 8); @@ -524,8 +524,8 @@ iommu_preserve_tsb(iommu_t *iommu_p) base_tte_addr[i] = tte; DEBUG3(DBG_ATTACH | DBG_CONT, dip, - "\npreserve_tsb: (%x)=%08x.%08x\n", base_tte_addr + i, - (uint_t)(tte >> 32), (uint_t)(tte & 0xffffffff)); + "\npreserve_tsb: (%x)=%08x.%08x\n", base_tte_addr + i, + (uint_t)(tte >> 32), (uint_t)(tte & 0xffffffff)); /* * permanantly reserve this page from dvma address space @@ -534,7 +534,7 @@ iommu_preserve_tsb(iommu_t *iommu_p) va = (caddr_t)(IOMMU_PTOB(base_pg_index + i)); (void) vmem_xalloc(iommu_p->iommu_dvma_map, IOMMU_PAGE_SIZE, - IOMMU_PAGE_SIZE, 0, 0, va, va + IOMMU_PAGE_SIZE, - VM_NOSLEEP | VM_BESTFIT | VM_PANIC); + IOMMU_PAGE_SIZE, 0, 0, va, va + IOMMU_PAGE_SIZE, + VM_NOSLEEP | VM_BESTFIT | VM_PANIC); } } |