1 files changed, 4 insertions, 37 deletions
diff --git a/usr/src/uts/sun4v/cpu/niagara2_asm.s b/usr/src/uts/sun4v/cpu/niagara2_asm.s
index da80b8b590..c780fae4be 100644
--- a/usr/src/uts/sun4v/cpu/niagara2_asm.s
+++ b/usr/src/uts/sun4v/cpu/niagara2_asm.s
@@ -23,9 +23,7 @@
  * Use is subject to license terms.
  */
 
-#if !defined(lint)
 #include "assym.h"
-#endif
 
 /*
  * Niagara2 processor specific assembly routines
@@ -40,19 +38,6 @@
 #include <sys/niagaraasi.h>
 #include <vm/hat_sfmmu.h>
 
-#if defined(lint)
-/*ARGSUSED*/
-uint64_t
-hv_niagara_getperf(uint64_t perfreg, uint64_t *datap)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niagara_setperf(uint64_t perfreg, uint64_t data)
-{ return (0); }
-
-#else   /* lint */
-
 	/*
 	 * hv_niagara_getperf(uint64_t perfreg, uint64_t *datap)
 	 */
@@ -89,9 +74,6 @@ hv_niagara_setperf(uint64_t perfreg, uint64_t data)
 	nop
 	SET_SIZE(hv_niagara_setperf)
 
-#endif /* !lint */
-
-#if defined (lint)
 /*
  * Invalidate all of the entries within the TSB, by setting the inv bit
  * in the tte_tag field of each tsbe.
@@ -103,13 +85,6 @@ hv_niagara_setperf(uint64_t perfreg, uint64_t data)
  * (in short, we set all bits in the upper word of the tag, and we give the
  * invalid bit precedence over other tag bits in both places).
  */
-/*ARGSUSED*/
-void
-cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes)
-{}
-
-#else /* lint */
-
 	ENTRY(cpu_inv_tsb)
 
 	/*
@@ -151,22 +126,14 @@ cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes)
 	nop
 
 	SET_SIZE(cpu_inv_tsb)
-#endif /* lint */
 
-#if defined (lint)
-/*
- * This is CPU specific delay routine for atomic backoff. It is used in case
- * of Niagara2 and VF CPUs. The rd instruction uses less resources than casx
- * on these CPUs.
- */
-void
-cpu_atomic_delay(void)
-{}
-#else	/* lint */
+	/*
+	 * The rd instruction uses less resources than casx on Niagara2 and VF
+	 * CPUs.
+	 */
 	ENTRY(cpu_atomic_delay)
 	rd	%ccr, %g0
 	rd	%ccr, %g0
 	retl
 	rd	%ccr, %g0
 	SET_SIZE(cpu_atomic_delay)
-#endif	/* lint */