1 files changed, 0 insertions, 42 deletions
diff --git a/usr/src/uts/sun4v/cpu/niagara_asm.s b/usr/src/uts/sun4v/cpu/niagara_asm.s
index f19102a19d..9aaeb54004 100644
--- a/usr/src/uts/sun4v/cpu/niagara_asm.s
+++ b/usr/src/uts/sun4v/cpu/niagara_asm.s
@@ -23,11 +23,7 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if !defined(lint)
 #include "assym.h"
-#endif
 
 /*
  * Niagara processor specific assembly routines
@@ -42,19 +38,6 @@
 #include <sys/niagaraasi.h>
 #include <vm/hat_sfmmu.h>
 
-#if defined(lint)
-/*ARGSUSED*/
-uint64_t
-hv_niagara_getperf(uint64_t perfreg, uint64_t *datap)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niagara_setperf(uint64_t perfreg, uint64_t data)
-{ return (0); }
-
-#else   /* lint */
-
 	/*
 	 * hv_niagara_getperf(uint64_t perfreg, uint64_t *datap)
 	 */
@@ -79,9 +62,6 @@ hv_niagara_setperf(uint64_t perfreg, uint64_t data)
 	nop
 	SET_SIZE(hv_niagara_setperf)
 
-#endif /* !lint */
-
-#if defined (lint)
 /*
  * Invalidate all of the entries within the TSB, by setting the inv bit
  * in the tte_tag field of each tsbe.
@@ -93,13 +73,6 @@ hv_niagara_setperf(uint64_t perfreg, uint64_t data)
  * (in short, we set all bits in the upper word of the tag, and we give the
  * invalid bit precedence over other tag bits in both places).
  */
-/*ARGSUSED*/
-void
-cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes)
-{}
-
-#else /* lint */
-
 	ENTRY(cpu_inv_tsb)
 
 	/*
@@ -141,20 +114,6 @@ cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes)
 	nop
 
 	SET_SIZE(cpu_inv_tsb)
-#endif /* lint */
-
-#if defined(lint)
-/*ARGSUSED*/
-uint64_t
-hv_niagara_mmustat_conf(uint64_t buf, uint64_t *prev_buf)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niagara_mmustat_info(uint64_t *buf)
-{ return (0); }
-
-#else   /* lint */
 
 	/*
 	 * hv_niagara_mmustat_conf(uint64_t buf, uint64_t *prev_buf)
@@ -178,4 +137,3 @@ hv_niagara_mmustat_info(uint64_t *buf)
 	stx	%o1, [%o4]
 	SET_SIZE(hv_niagara_mmustat_info)
 
-#endif /* !lint */