diff options
Diffstat (limited to 'usr/src')
| -rw-r--r-- | usr/src/uts/intel/io/vmm/amd/svm.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/usr/src/uts/intel/io/vmm/amd/svm.c b/usr/src/uts/intel/io/vmm/amd/svm.c index de4a492ae9..a00b7d4c1d 100644 --- a/usr/src/uts/intel/io/vmm/amd/svm.c +++ b/usr/src/uts/intel/io/vmm/amd/svm.c @@ -2135,6 +2135,23 @@ svm_getreg(void *arg, int vcpu, int ident, uint64_t *val) /* GDTR and IDTR don't have segment selectors */ return (EINVAL); + case VM_REG_GUEST_PDPTE0: + case VM_REG_GUEST_PDPTE1: + case VM_REG_GUEST_PDPTE2: + case VM_REG_GUEST_PDPTE3: + /* + * Unlike VMX, where the PDPTEs are explicitly cached as part of + * several well-defined events related to paging (such as + * loading %cr3), SVM walks the PDPEs (their PDPTE) as part of + * nested paging lookups. This makes these registers + * effectively irrelevant on SVM. + * + * Rather than tossing an error, emit zeroed values so casual + * consumers do not need to be as careful about that difference. + */ + *val = 0; + break; + default: return (EINVAL); } @@ -2208,6 +2225,17 @@ svm_setreg(void *arg, int vcpu, int ident, uint64_t val) /* GDTR and IDTR don't have segment selectors */ return (EINVAL); + case VM_REG_GUEST_PDPTE0: + case VM_REG_GUEST_PDPTE1: + case VM_REG_GUEST_PDPTE2: + case VM_REG_GUEST_PDPTE3: + /* + * PDPEs (AMD's PDPTE) are not cached under SVM, so we can + * ignore attempts to set them. See handler in svm_getreg() for + * more details. + */ + break; + default: return (EINVAL); } |