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-rw-r--r--usr/src/uts/common/io/ixgbe/ixgbe_82598.c16
-rw-r--r--usr/src/uts/common/io/ixgbe/ixgbe_82599.c32
-rw-r--r--usr/src/uts/common/io/ixgbe/ixgbe_api.c33
-rw-r--r--usr/src/uts/common/io/ixgbe/ixgbe_common.c160
-rw-r--r--usr/src/uts/common/io/ixgbe/ixgbe_common.h5
-rw-r--r--usr/src/uts/common/io/ixgbe/ixgbe_mbx.c16
-rw-r--r--usr/src/uts/common/io/ixgbe/ixgbe_osdep.h5
-rw-r--r--usr/src/uts/common/io/ixgbe/ixgbe_phy.c36
-rw-r--r--usr/src/uts/common/io/ixgbe/ixgbe_x540.c28
9 files changed, 200 insertions, 131 deletions
diff --git a/usr/src/uts/common/io/ixgbe/ixgbe_82598.c b/usr/src/uts/common/io/ixgbe/ixgbe_82598.c
index 725293452a..bf29a43afa 100644
--- a/usr/src/uts/common/io/ixgbe/ixgbe_82598.c
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_82598.c
@@ -720,7 +720,7 @@ static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
ixgbe_link_speed speed, bool autoneg,
bool autoneg_wait_to_complete)
{
- s32 status = IXGBE_SUCCESS;
+ s32 status;
ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
u32 autoc = curr_autoc;
@@ -729,7 +729,9 @@ static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
DEBUGFUNC("ixgbe_setup_mac_link_82598");
/* Check to see if speed passed in is supported. */
- ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
+ status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
+ if (status != IXGBE_SUCCESS)
+ return (status);
speed &= link_capabilities;
if (speed == IXGBE_LINK_SPEED_UNKNOWN)
@@ -782,8 +784,11 @@ static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
/* Setup the PHY according to input speed */
status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
autoneg_wait_to_complete);
- /* Set up MAC */
- ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
+ if (status == IXGBE_SUCCESS) {
+ /* Set up MAC */
+ status =
+ ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
+ }
return status;
}
@@ -1357,6 +1362,7 @@ static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
/* Setup the last four at 48KB...don't re-init i */
rxpktsize = IXGBE_RXPBSIZE_48KB;
/* Fall Through */
+ /* FALLTHRU */
case PBA_STRATEGY_EQUAL:
default:
/* Divide the remaining Rx packet buffer evenly among the TCs */
@@ -1368,6 +1374,4 @@ static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
/* Setup Tx packet buffer sizes */
for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
-
- return;
}
diff --git a/usr/src/uts/common/io/ixgbe/ixgbe_82599.c b/usr/src/uts/common/io/ixgbe/ixgbe_82599.c
index d5b742d73f..15c59d4891 100644
--- a/usr/src/uts/common/io/ixgbe/ixgbe_82599.c
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_82599.c
@@ -952,8 +952,11 @@ static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
/* Setup the PHY according to input speed */
status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
autoneg_wait_to_complete);
- /* Set up MAC */
- ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
+ if (status == IXGBE_SUCCESS) {
+ /* Set up MAC */
+ status =
+ ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
+ }
return status;
}
@@ -1174,11 +1177,11 @@ s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
}
/* Clear FDIR statistics registers (read to clear) */
- IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
- IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
- IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
- IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
- IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
+ (void) IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
+ (void) IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
+ (void) IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
+ (void) IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
+ (void) IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
return IXGBE_SUCCESS;
}
@@ -1289,6 +1292,9 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
*/
#define IXGBE_ATR_COMMON_HASH_KEY \
(IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
+#if lint
+#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n)
+#else
#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
do { \
u32 n = (_n); \
@@ -1305,6 +1311,7 @@ do { \
else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
sig_hash ^= hi_hash_dword << (16 - n); \
} while (0);
+#endif
/**
* ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
@@ -1425,6 +1432,9 @@ s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
return IXGBE_SUCCESS;
}
+#if lint
+#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n)
+#else
#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
do { \
u32 n = (_n); \
@@ -1433,7 +1443,7 @@ do { \
if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
bucket_hash ^= hi_hash_dword >> n; \
} while (0);
-
+#endif
/**
* ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
* @atr_input: input bitstream to compute the hash on
@@ -1584,6 +1594,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
switch (input_mask->formatted.vm_pool & 0x7F) {
case 0x0:
fdirm |= IXGBE_FDIRM_POOL;
+ /* FALLTHRU */
case 0x7F:
break;
default:
@@ -1599,6 +1610,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
DEBUGOUT(" Error on src/dst port mask\n");
return IXGBE_ERR_CONFIG;
}
+ /* FALLTHRU */
case IXGBE_ATR_L4TYPE_MASK:
break;
default:
@@ -1610,6 +1622,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
case 0x0000:
/* mask VLAN ID, fall through to mask VLAN priority */
fdirm |= IXGBE_FDIRM_VLANID;
+ /* FALLTHRU */
case 0x0FFF:
/* mask VLAN priority */
fdirm |= IXGBE_FDIRM_VLANP;
@@ -1617,6 +1630,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
case 0xE000:
/* mask VLAN ID only, fall through */
fdirm |= IXGBE_FDIRM_VLANID;
+ /* FALLTHRU */
case 0xEFFF:
/* no VLAN fields masked */
break;
@@ -1629,6 +1643,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
case 0x0000:
/* Mask Flex Bytes, fall through */
fdirm |= IXGBE_FDIRM_FLEX;
+ /* FALLTHRU */
case 0xFFFF:
break;
default:
@@ -1794,6 +1809,7 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
DEBUGOUT(" Error on src/dst port\n");
return IXGBE_ERR_CONFIG;
}
+ /* FALLTHRU */
case IXGBE_ATR_FLOW_TYPE_TCPV4:
case IXGBE_ATR_FLOW_TYPE_UDPV4:
input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
diff --git a/usr/src/uts/common/io/ixgbe/ixgbe_api.c b/usr/src/uts/common/io/ixgbe/ixgbe_api.c
index 77ae70d3d7..c70ccb701b 100644
--- a/usr/src/uts/common/io/ixgbe/ixgbe_api.c
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_api.c
@@ -56,7 +56,9 @@ s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
/*
* Set the mac type
*/
- ixgbe_set_mac_type(hw);
+ status = ixgbe_set_mac_type(hw);
+ if (status != IXGBE_SUCCESS)
+ return (status);
switch (hw->mac.type) {
case ixgbe_mac_82598EB:
@@ -448,11 +450,19 @@ s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)
s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 *phy_data)
{
+ s32 status;
+
if (hw->phy.id == 0)
- ixgbe_identify_phy(hw);
+ status = ixgbe_identify_phy(hw);
+ else
+ status = IXGBE_SUCCESS;
- return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,
- device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
+ if (status == IXGBE_SUCCESS) {
+ status = ixgbe_call_func(hw, hw->phy.ops.read_reg,
+ (hw, reg_addr, device_type, phy_data),
+ IXGBE_NOT_IMPLEMENTED);
+ }
+ return (status);
}
/**
@@ -466,11 +476,20 @@ s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 phy_data)
{
+ s32 status;
+
if (hw->phy.id == 0)
- ixgbe_identify_phy(hw);
+ status = ixgbe_identify_phy(hw);
+ else
+ status = IXGBE_SUCCESS;
- return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
- device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
+ if (status == IXGBE_SUCCESS) {
+ status = ixgbe_call_func(hw, hw->phy.ops.write_reg,
+ (hw, reg_addr, device_type, phy_data),
+ IXGBE_NOT_IMPLEMENTED);
+ }
+
+ return status;
}
/**
diff --git a/usr/src/uts/common/io/ixgbe/ixgbe_common.c b/usr/src/uts/common/io/ixgbe/ixgbe_common.c
index a39e71fefc..bc0d4f6c69 100644
--- a/usr/src/uts/common/io/ixgbe/ixgbe_common.c
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_common.c
@@ -432,94 +432,94 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
- IXGBE_READ_REG(hw, IXGBE_CRCERRS);
- IXGBE_READ_REG(hw, IXGBE_ILLERRC);
- IXGBE_READ_REG(hw, IXGBE_ERRBC);
- IXGBE_READ_REG(hw, IXGBE_MSPDC);
+ (void) IXGBE_READ_REG(hw, IXGBE_CRCERRS);
+ (void) IXGBE_READ_REG(hw, IXGBE_ILLERRC);
+ (void) IXGBE_READ_REG(hw, IXGBE_ERRBC);
+ (void) IXGBE_READ_REG(hw, IXGBE_MSPDC);
for (i = 0; i < 8; i++)
- IXGBE_READ_REG(hw, IXGBE_MPC(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_MPC(i));
- IXGBE_READ_REG(hw, IXGBE_MLFC);
- IXGBE_READ_REG(hw, IXGBE_MRFC);
- IXGBE_READ_REG(hw, IXGBE_RLEC);
- IXGBE_READ_REG(hw, IXGBE_LXONTXC);
- IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
+ (void) IXGBE_READ_REG(hw, IXGBE_MLFC);
+ (void) IXGBE_READ_REG(hw, IXGBE_MRFC);
+ (void) IXGBE_READ_REG(hw, IXGBE_RLEC);
+ (void) IXGBE_READ_REG(hw, IXGBE_LXONTXC);
+ (void) IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
if (hw->mac.type >= ixgbe_mac_82599EB) {
- IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
- IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
+ (void) IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
+ (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
} else {
- IXGBE_READ_REG(hw, IXGBE_LXONRXC);
- IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
+ (void) IXGBE_READ_REG(hw, IXGBE_LXONRXC);
+ (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
}
for (i = 0; i < 8; i++) {
- IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
- IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
if (hw->mac.type >= ixgbe_mac_82599EB) {
- IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
- IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
} else {
- IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
- IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
}
}
if (hw->mac.type >= ixgbe_mac_82599EB)
for (i = 0; i < 8; i++)
- IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
- IXGBE_READ_REG(hw, IXGBE_PRC64);
- IXGBE_READ_REG(hw, IXGBE_PRC127);
- IXGBE_READ_REG(hw, IXGBE_PRC255);
- IXGBE_READ_REG(hw, IXGBE_PRC511);
- IXGBE_READ_REG(hw, IXGBE_PRC1023);
- IXGBE_READ_REG(hw, IXGBE_PRC1522);
- IXGBE_READ_REG(hw, IXGBE_GPRC);
- IXGBE_READ_REG(hw, IXGBE_BPRC);
- IXGBE_READ_REG(hw, IXGBE_MPRC);
- IXGBE_READ_REG(hw, IXGBE_GPTC);
- IXGBE_READ_REG(hw, IXGBE_GORCL);
- IXGBE_READ_REG(hw, IXGBE_GORCH);
- IXGBE_READ_REG(hw, IXGBE_GOTCL);
- IXGBE_READ_REG(hw, IXGBE_GOTCH);
+ (void) IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_PRC64);
+ (void) IXGBE_READ_REG(hw, IXGBE_PRC127);
+ (void) IXGBE_READ_REG(hw, IXGBE_PRC255);
+ (void) IXGBE_READ_REG(hw, IXGBE_PRC511);
+ (void) IXGBE_READ_REG(hw, IXGBE_PRC1023);
+ (void) IXGBE_READ_REG(hw, IXGBE_PRC1522);
+ (void) IXGBE_READ_REG(hw, IXGBE_GPRC);
+ (void) IXGBE_READ_REG(hw, IXGBE_BPRC);
+ (void) IXGBE_READ_REG(hw, IXGBE_MPRC);
+ (void) IXGBE_READ_REG(hw, IXGBE_GPTC);
+ (void) IXGBE_READ_REG(hw, IXGBE_GORCL);
+ (void) IXGBE_READ_REG(hw, IXGBE_GORCH);
+ (void) IXGBE_READ_REG(hw, IXGBE_GOTCL);
+ (void) IXGBE_READ_REG(hw, IXGBE_GOTCH);
if (hw->mac.type == ixgbe_mac_82598EB)
for (i = 0; i < 8; i++)
- IXGBE_READ_REG(hw, IXGBE_RNBC(i));
- IXGBE_READ_REG(hw, IXGBE_RUC);
- IXGBE_READ_REG(hw, IXGBE_RFC);
- IXGBE_READ_REG(hw, IXGBE_ROC);
- IXGBE_READ_REG(hw, IXGBE_RJC);
- IXGBE_READ_REG(hw, IXGBE_MNGPRC);
- IXGBE_READ_REG(hw, IXGBE_MNGPDC);
- IXGBE_READ_REG(hw, IXGBE_MNGPTC);
- IXGBE_READ_REG(hw, IXGBE_TORL);
- IXGBE_READ_REG(hw, IXGBE_TORH);
- IXGBE_READ_REG(hw, IXGBE_TPR);
- IXGBE_READ_REG(hw, IXGBE_TPT);
- IXGBE_READ_REG(hw, IXGBE_PTC64);
- IXGBE_READ_REG(hw, IXGBE_PTC127);
- IXGBE_READ_REG(hw, IXGBE_PTC255);
- IXGBE_READ_REG(hw, IXGBE_PTC511);
- IXGBE_READ_REG(hw, IXGBE_PTC1023);
- IXGBE_READ_REG(hw, IXGBE_PTC1522);
- IXGBE_READ_REG(hw, IXGBE_MPTC);
- IXGBE_READ_REG(hw, IXGBE_BPTC);
+ (void) IXGBE_READ_REG(hw, IXGBE_RNBC(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_RUC);
+ (void) IXGBE_READ_REG(hw, IXGBE_RFC);
+ (void) IXGBE_READ_REG(hw, IXGBE_ROC);
+ (void) IXGBE_READ_REG(hw, IXGBE_RJC);
+ (void) IXGBE_READ_REG(hw, IXGBE_MNGPRC);
+ (void) IXGBE_READ_REG(hw, IXGBE_MNGPDC);
+ (void) IXGBE_READ_REG(hw, IXGBE_MNGPTC);
+ (void) IXGBE_READ_REG(hw, IXGBE_TORL);
+ (void) IXGBE_READ_REG(hw, IXGBE_TORH);
+ (void) IXGBE_READ_REG(hw, IXGBE_TPR);
+ (void) IXGBE_READ_REG(hw, IXGBE_TPT);
+ (void) IXGBE_READ_REG(hw, IXGBE_PTC64);
+ (void) IXGBE_READ_REG(hw, IXGBE_PTC127);
+ (void) IXGBE_READ_REG(hw, IXGBE_PTC255);
+ (void) IXGBE_READ_REG(hw, IXGBE_PTC511);
+ (void) IXGBE_READ_REG(hw, IXGBE_PTC1023);
+ (void) IXGBE_READ_REG(hw, IXGBE_PTC1522);
+ (void) IXGBE_READ_REG(hw, IXGBE_MPTC);
+ (void) IXGBE_READ_REG(hw, IXGBE_BPTC);
for (i = 0; i < 16; i++) {
- IXGBE_READ_REG(hw, IXGBE_QPRC(i));
- IXGBE_READ_REG(hw, IXGBE_QPTC(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_QPRC(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_QPTC(i));
if (hw->mac.type >= ixgbe_mac_82599EB) {
- IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
- IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
- IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
- IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
- IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
} else {
- IXGBE_READ_REG(hw, IXGBE_QBRC(i));
- IXGBE_READ_REG(hw, IXGBE_QBTC(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_QBRC(i));
+ (void) IXGBE_READ_REG(hw, IXGBE_QBTC(i));
}
}
if (hw->mac.type == ixgbe_mac_X540) {
if (hw->phy.id == 0)
- ixgbe_identify_phy(hw);
+ (void) ixgbe_identify_phy(hw);
hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
IXGBE_MDIO_PCS_DEV_TYPE, &i);
hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
@@ -816,7 +816,7 @@ s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
/* Clear any pending interrupts, flush previous writes */
- IXGBE_READ_REG(hw, IXGBE_EICR);
+ (void) IXGBE_READ_REG(hw, IXGBE_EICR);
/* Disable the transmit unit. Each queue must be disabled. */
for (i = 0; i < hw->mac.max_tx_queues; i++)
@@ -969,7 +969,9 @@ s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
*/
if ((hw->eeprom.word_page_size == 0) &&
(words > IXGBE_EEPROM_PAGE_SIZE_MAX))
- ixgbe_detect_eeprom_page_size_generic(hw, offset);
+ status = ixgbe_detect_eeprom_page_size_generic(hw, offset);
+ if (status != IXGBE_SUCCESS)
+ goto out;
/*
* We cannot hold synchronization semaphores for too long
@@ -2136,9 +2138,8 @@ s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
for (i = 0; i < hw->mac.mcft_size; i++)
IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
- ixgbe_init_uta_tables(hw);
-
- return IXGBE_SUCCESS;
+ /* Should always be IXGBE_SUCCESS. */
+ return ixgbe_init_uta_tables(hw);
}
/**
@@ -2350,7 +2351,8 @@ s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
/* Clear mta_shadow */
if (clear) {
DEBUGOUT(" Clearing MTA\n");
- memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
+ (void) memset(&hw->mac.mta_shadow, 0,
+ sizeof(hw->mac.mta_shadow));
}
/* Update mta_shadow */
@@ -2870,7 +2872,7 @@ void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
DEBUGFUNC("ixgbe_release_swfw_sync");
- ixgbe_get_eeprom_semaphore(hw);
+ (void) ixgbe_get_eeprom_semaphore(hw);
gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
gssr &= ~swmask;
@@ -3058,7 +3060,7 @@ s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
* First read the EEPROM pointer to see if the MAC addresses are
* available. If they're not, no point in calling set_lan_id() here.
*/
- ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
+ (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
/*
@@ -3103,7 +3105,7 @@ s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
/* Look for SAN mac address pointer. If not defined, return */
- ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
+ (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
status = IXGBE_ERR_NO_SAN_ADDR_PTR;
@@ -3213,14 +3215,14 @@ s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
if (rar < hw->mac.rar_highwater) {
/* already there so just add to the pool bits */
- ixgbe_set_vmdq(hw, rar, vmdq);
+ (void) ixgbe_set_vmdq(hw, rar, vmdq);
} else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
/* stick it into first empty RAR slot we found */
rar = first_empty_rar;
- ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
+ (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
} else if (rar == hw->mac.rar_highwater) {
/* add it to the top of the list and inc the highwater mark */
- ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
+ (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
hw->mac.rar_highwater++;
} else if (rar >= hw->mac.num_rar_entries) {
return IXGBE_ERR_INVALID_MAC_ADDR;
@@ -3231,7 +3233,7 @@ s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
* remains cleared to be sure default pool packets will get delivered
*/
if (rar == 0)
- ixgbe_clear_vmdq(hw, rar, 0);
+ (void) ixgbe_clear_vmdq(hw, rar, 0);
return rar;
}
@@ -4037,6 +4039,7 @@ s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
fw_cmd.pad2 = 0;
for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
+ /* LINTED */
ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
sizeof(fw_cmd));
if (ret_val != IXGBE_SUCCESS)
@@ -4090,6 +4093,7 @@ void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
for (; i < (num_pb / 2); i++)
IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
/* Fall through to configure remaining packet buffers */
+ /* FALLTHRU */
case PBA_STRATEGY_EQUAL:
rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
for (; i < num_pb; i++)
diff --git a/usr/src/uts/common/io/ixgbe/ixgbe_common.h b/usr/src/uts/common/io/ixgbe/ixgbe_common.h
index 0dad30e2a6..9cf7ab6f2a 100644
--- a/usr/src/uts/common/io/ixgbe/ixgbe_common.h
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_common.h
@@ -36,11 +36,16 @@
#define _IXGBE_COMMON_H_
#include "ixgbe_type.h"
+#if lint
+/* Use "hw" somehow... */
+#define IXGBE_WRITE_REG64(hw, reg, value) hw = hw
+#else
#define IXGBE_WRITE_REG64(hw, reg, value) \
do { \
IXGBE_WRITE_REG(hw, reg, (u32) value); \
IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \
} while (0)
+#endif
u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
diff --git a/usr/src/uts/common/io/ixgbe/ixgbe_mbx.c b/usr/src/uts/common/io/ixgbe/ixgbe_mbx.c
index f9c1efab51..d59daf7f09 100644
--- a/usr/src/uts/common/io/ixgbe/ixgbe_mbx.c
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_mbx.c
@@ -429,8 +429,12 @@ static s32 ixgbe_write_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size,
goto out_no_write;
/* flush msg and acks as we are overwriting the message buffer */
- ixgbe_check_for_msg_vf(hw, 0);
- ixgbe_check_for_ack_vf(hw, 0);
+ ret_val = ixgbe_check_for_msg_vf(hw, 0);
+ if (ret_val)
+ goto out_no_write;
+ ret_val = ixgbe_check_for_ack_vf(hw, 0);
+ if (ret_val)
+ goto out_no_write;
/* copy the caller specified message to the mailbox memory buffer */
for (i = 0; i < size; i++)
@@ -660,8 +664,12 @@ static s32 ixgbe_write_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size,
goto out_no_write;
/* flush msg and acks as we are overwriting the message buffer */
- ixgbe_check_for_msg_pf(hw, vf_number);
- ixgbe_check_for_ack_pf(hw, vf_number);
+ ret_val = ixgbe_check_for_msg_vf(hw, 0);
+ if (ret_val)
+ goto out_no_write;
+ ret_val = ixgbe_check_for_ack_vf(hw, 0);
+ if (ret_val)
+ goto out_no_write;
/* copy the caller specified message to the mailbox memory buffer */
for (i = 0; i < size; i++)
diff --git a/usr/src/uts/common/io/ixgbe/ixgbe_osdep.h b/usr/src/uts/common/io/ixgbe/ixgbe_osdep.h
index afd0706f06..f3b7e23fb3 100644
--- a/usr/src/uts/common/io/ixgbe/ixgbe_osdep.h
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_osdep.h
@@ -111,7 +111,12 @@ void ixgbe_write_pci_cfg(struct ixgbe_hw *, uint32_t, uint32_t);
#define IXGBE_LE32_TO_CPUS BSWAP_32
#else
#define IXGBE_CPU_TO_LE32(x) (x)
+#if lint
+/* Use lint-happy operation... */
+#define IXGBE_LE32_TO_CPUS(x)
+#else
#define IXGBE_LE32_TO_CPUS(x) (x)
+#endif /* lint */
#endif /* _BIG_ENDIAN */
#define UNREFERENCED_PARAMETER(x) _NOTE(ARGUNUSED(x))
diff --git a/usr/src/uts/common/io/ixgbe/ixgbe_phy.c b/usr/src/uts/common/io/ixgbe/ixgbe_phy.c
index 9277eb0c15..ef5bb644ae 100644
--- a/usr/src/uts/common/io/ixgbe/ixgbe_phy.c
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_phy.c
@@ -98,7 +98,7 @@ s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
if (ixgbe_validate_phy_addr(hw, phy_addr)) {
hw->phy.addr = phy_addr;
- ixgbe_get_phy_id(hw);
+ (void) ixgbe_get_phy_id(hw);
hw->phy.type =
ixgbe_get_phy_type_from_id(hw->phy.id);
@@ -470,7 +470,7 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
**/
s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
{
- s32 status = IXGBE_SUCCESS;
+ s32 status;
u32 time_out;
u32 max_time_out = 10;
u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
@@ -479,7 +479,10 @@ s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
DEBUGFUNC("ixgbe_setup_phy_link_generic");
- ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
+ status =
+ ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
+ if (status != IXGBE_SUCCESS)
+ return status;
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
/* Set or unset auto-negotiation 10G advertisement */
@@ -688,7 +691,7 @@ s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
**/
s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
{
- s32 status = IXGBE_SUCCESS;
+ s32 status;
u32 time_out;
u32 max_time_out = 10;
u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
@@ -697,7 +700,10 @@ s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
DEBUGFUNC("ixgbe_setup_phy_link_tnx");
- ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
+ status =
+ ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
+ if (status != IXGBE_SUCCESS)
+ return status;
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
/* Set or unset auto-negotiation 10G advertisement */
@@ -1185,7 +1191,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
goto out;
}
- ixgbe_get_device_caps(hw, &enforce_sfp);
+ (void) ixgbe_get_device_caps(hw, &enforce_sfp);
if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
!((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
@@ -1529,13 +1535,13 @@ static void ixgbe_i2c_start(struct ixgbe_hw *hw)
DEBUGFUNC("ixgbe_i2c_start");
/* Start condition must begin with data and clock high */
- ixgbe_set_i2c_data(hw, &i2cctl, 1);
+ (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
ixgbe_raise_i2c_clk(hw, &i2cctl);
/* Setup time for start condition (4.7us) */
usec_delay(IXGBE_I2C_T_SU_STA);
- ixgbe_set_i2c_data(hw, &i2cctl, 0);
+ (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
/* Hold time for start condition (4us) */
usec_delay(IXGBE_I2C_T_HD_STA);
@@ -1560,13 +1566,13 @@ static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
DEBUGFUNC("ixgbe_i2c_stop");
/* Stop condition must begin with data low and clock high */
- ixgbe_set_i2c_data(hw, &i2cctl, 0);
+ (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
ixgbe_raise_i2c_clk(hw, &i2cctl);
/* Setup time for stop condition (4us) */
usec_delay(IXGBE_I2C_T_SU_STO);
- ixgbe_set_i2c_data(hw, &i2cctl, 1);
+ (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
/* bus free time between stop and start (4.7us)*/
usec_delay(IXGBE_I2C_T_BUF);
@@ -1581,17 +1587,19 @@ static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
**/
static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
{
- s32 i;
+ s32 i, status = IXGBE_SUCCESS;
bool bit = 0;
DEBUGFUNC("ixgbe_clock_in_i2c_byte");
for (i = 7; i >= 0; i--) {
- ixgbe_clock_in_i2c_bit(hw, &bit);
+ status = ixgbe_clock_in_i2c_bit(hw, &bit);
+ if (status != IXGBE_SUCCESS)
+ break;
*data |= bit << i;
}
- return IXGBE_SUCCESS;
+ return status;
}
/**
@@ -1858,7 +1866,7 @@ void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
ixgbe_i2c_start(hw);
- ixgbe_set_i2c_data(hw, &i2cctl, 1);
+ (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
for (i = 0; i < 9; i++) {
ixgbe_raise_i2c_clk(hw, &i2cctl);
diff --git a/usr/src/uts/common/io/ixgbe/ixgbe_x540.c b/usr/src/uts/common/io/ixgbe/ixgbe_x540.c
index f662c76cf9..5b7377460e 100644
--- a/usr/src/uts/common/io/ixgbe/ixgbe_x540.c
+++ b/usr/src/uts/common/io/ixgbe/ixgbe_x540.c
@@ -156,9 +156,7 @@ s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
ixgbe_link_speed *speed,
bool *autoneg)
{
- ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
-
- return IXGBE_SUCCESS;
+ return ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
}
/**
@@ -572,19 +570,21 @@ s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
* Do not use hw->eeprom.ops.read because we do not want to take
* the synchronization semaphores twice here.
*/
- ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
+ status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
&read_checksum);
- /*
- * Verify read checksum from EEPROM is the same as
- * calculated checksum
- */
- if (read_checksum != checksum)
- status = IXGBE_ERR_EEPROM_CHECKSUM;
+ if (status == IXGBE_SUCCESS) {
+ /*
+ * Verify read checksum from EEPROM is the same as
+ * calculated checksum
+ */
+ if (read_checksum != checksum)
+ status = IXGBE_ERR_EEPROM_CHECKSUM;
- /* If the user cares, return the calculated checksum */
- if (checksum_val)
- *checksum_val = checksum;
+ /* If the user cares, return the calculated checksum */
+ if (checksum_val)
+ *checksum_val = checksum;
+ }
} else {
status = IXGBE_ERR_SWFW_SYNC;
}
@@ -812,7 +812,7 @@ void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
DEBUGFUNC("ixgbe_release_swfw_sync_X540");
- ixgbe_get_swfw_sync_semaphore(hw);
+ (void) ixgbe_get_swfw_sync_semaphore(hw);
swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
swfw_sync &= ~swmask;
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-30 06:15:55 +0000