1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
|
'\" te
.\" Copyright (c) 2005, Sun Microsystems, Inc. All Rights Reserved
.\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License.
.\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License.
.\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner]
.TH DDI_DMA_LIM_SPARC 9S "Oct 12, 2005"
.SH NAME
ddi_dma_lim_sparc, ddi_dma_lim \- SPARC DMA limits structure
.SH SYNOPSIS
.LP
.nf
#include <sys/ddidmareq.h>
.fi
.SH INTERFACE LEVEL
.sp
.LP
Solaris SPARC DDI specific (Solaris SPARC DDI). These interfaces are obsolete.
.SH DESCRIPTION
.sp
.LP
This page describes the SPARC version of the \fBddi_dma_lim\fR structure. See
\fBddi_dma_lim_x86\fR(9S) for a description of the x86 version of this
structure.
.sp
.LP
A \fBddi_dma_lim\fR structure describes in a generic fashion the possible
limitations of a device's \fBDMA\fR engine. This information is used by the
system when it attempts to set up \fBDMA\fR resources for a device.
.SH STRUCTURE MEMBERS
.sp
.in +2
.nf
uint_t dlim_addr_lo; /* low range of 32 bit
addressing capability */
uint_t dlim_addr_hi; /* inclusive upper bound of address.
capability */
uint_t dlim_cntr_max; /* inclusive upper bound of
dma engine address limit * /
uint_t dlim_burstsizes; /* binary encoded dma burst sizes */
uint_t dlim_minxfer; /* minimum effective dma xfer size */
uint_t dlim_dmaspeed; /* average dma data rate (kb/s) */
.fi
.in -2
.sp
.LP
The \fBdlim_addr_lo\fR and \fBdlim_addr_hi\fR fields specify the address range
the device's \fBDMA\fR engine can access. The \fBdlim_addr_lo\fR field
describes the lower 32-bit boundary of the device's \fBDMA\fR engine, the
\fBdlim_addr_hi\fR describes the inclusive upper 32-bit boundary. The system
allocates \fBDMA\fR resources in a way that the address for programming the
device's \fBDMA\fR engine (see \fBddi_dma_cookie\fR(9S) or
\fBddi_dma_htoc\fR(9F)) is within this range. For example, if your device can
access the whole 32-bit address range, you may use [\fB0\fR,\fB0xFFFFFFFF\fR].
If your device has just a 16-bit address register but will access the top of
the 32-bit address range, then [\fB0xFFFF0000\fR,\fB0xFFFFFFFF\fR] is the
right limit.
.sp
.LP
The \fBdlim_cntr_max\fR field describes an inclusive upper bound for the
device's \fBDMA\fR engine address register. This handles a fairly common case
where a portion of the address register is only a latch rather than a full
register. For example, the upper 8 bits of a 32-bit address register can be a
latch. This splits the address register into a portion that acts as a true
address register (24 bits) for a 16 Mbyte segment and a latch (8 bits) to hold
a segment number. To describe these limits, specify \fB0xFFFFFF\fR in the
\fBdlim_cntr_max\fR structure.
.sp
.LP
The \fBdlim_burstsizes\fR field describes the possible burst sizes the device's
\fBDMA\fR engine can accept. At the time of a \fBDMA\fR resource request, this
element defines the possible \fBDMA\fR burst cycle sizes that the requester's
\fBDMA\fR engine can handle. The format of the data is binary encoding of burst
sizes assumed to be powers of two. That is, if a \fBDMA\fR engine is capable of
doing 1-, 2-, 4-, and 16-byte transfers, the encoding ix 0x17. If the device is
an SBus device and can take advantage of a 64-bit SBus, the lower 16 bits are
used to specify the burst size for 32-bit transfers and the upper 16 bits are
used to specify the burst size for 64-bit transfers. As the resource request is
handled by the system, the \fBburstsizes\fR value can be modified. Prior to
enabling \fBDMA\fR for the specific device, the driver that owns the \fBDMA\fR
engine should check (using \fBddi_dma_burstsizes\fR(9F)) what the allowed
\fBburstsizes\fR have become and program the \fBDMA\fR engine appropriately.
.sp
.LP
The \fBdlim_minxfer\fR field describes the minimum effective \fBDMA\fR transfer
size (in units of bytes). It must be a power of two. This value specifies the
minimum effective granularity of the \fBDMA\fR engine. It is distinct from
\fBdlim_burstsizes\fR in that it describes the minimum amount of access a
\fBDMA\fR transfer will effect. \fBdlim_burstsizes\fR describes in what
electrical fashion the \fBDMA\fR engine might perform its accesses, while
\fBdlim_minxfer\fR describes the minimum amount of memory that can be touched
by the \fBDMA\fR transfer. As a resource request is handled by the system, the
\fBdlim_minxfer\fR value can be modified contingent upon the presence (and use)
of \fBI/O \fRcaches and \fBDMA\fR write buffers in between the \fBDMA\fR engine
and the object that \fBDMA\fR is being performed on. After \fBDMA\fR resources
have been allocated, the resultant minimum transfer value can be gotten using
\fBddi_dma_devalign\fR(9F).
.sp
.LP
The field \fBdlim_dmaspeed\fR is the expected average data rate for the
\fBDMA\fR engine (in units of kilobytes per second). Note that this should not
be the maximum, or peak, burst data rate, but a reasonable guess as to the
average throughput. This field is entirely optional and can be left as zero.
Its intended use is to provide some hints about how much of the \fBDMA\fR
resource this device might need.
.SH ATTRIBUTES
.sp
.LP
See \fBattributes\fR(5) for descriptions of the following attributes:
.sp
.sp
.TS
box;
c | c
l | l .
ATTRIBUTE TYPE ATTRIBUTE VALUE
_
Interface Stability Obsolete
.TE
.SH SEE ALSO
.sp
.LP
\fBddi_dma_addr_setup\fR(9F), \fBddi_dma_buf_setup\fR(9F),
\fBddi_dma_burstsizes\fR(9F), \fBddi_dma_devalign\fR(9F),
\fBddi_dma_htoc\fR(9F), \fBddi_dma_setup\fR(9F), \fBddi_dma_cookie\fR(9S),
\fBddi_dma_lim_x86\fR(9S), \fBddi_dma_req\fR(9S)
|
