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author | kamil <kamil@pkgsrc.org> | 2016-10-08 23:01:45 +0000 |
---|---|---|
committer | kamil <kamil@pkgsrc.org> | 2016-10-08 23:01:45 +0000 |
commit | 1029f7734433ebf65f31aabffa8e5a5793713e5e (patch) | |
tree | b3e3b1db4897f683ffb8ef7f55903e48444a6e38 | |
parent | 8dd798ffa37058256242bbd0ec8ba622c0270095 (diff) | |
download | pkgsrc-1029f7734433ebf65f31aabffa8e5a5793713e5e.tar.gz |
Import iverilog (Icarus Verilog) 10.1.1 as cad/iverilog
It's a rename of cad/verilog to a better name.
Updated DESCR for new package:
Icarus Verilog is intended to compile ALL of the Verilog HDL as described in
the IEEE-1364 standard. Of course, it's not quite there yet. It does currently
handle a mix of structural and behavioral constructs.
Icarus Verilog is not aimed at being a simulator in the traditional sense, but
a compiler that generates code employed by back-end tools.
No objections to rename from <gdt>
-rw-r--r-- | cad/iverilog/DESCR | 6 | ||||
-rw-r--r-- | cad/iverilog/Makefile | 37 | ||||
-rw-r--r-- | cad/iverilog/PLIST | 58 | ||||
-rw-r--r-- | cad/iverilog/buildlink3.mk | 16 | ||||
-rw-r--r-- | cad/iverilog/distinfo | 9 | ||||
-rw-r--r-- | cad/iverilog/patches/patch-aa | 14 | ||||
-rw-r--r-- | cad/iverilog/patches/patch-ad | 25 | ||||
-rw-r--r-- | cad/iverilog/patches/patch-cadpli_Makefile | 17 |
8 files changed, 182 insertions, 0 deletions
diff --git a/cad/iverilog/DESCR b/cad/iverilog/DESCR new file mode 100644 index 00000000000..6e1388e2795 --- /dev/null +++ b/cad/iverilog/DESCR @@ -0,0 +1,6 @@ +Icarus Verilog is intended to compile ALL of the Verilog HDL as described in +the IEEE-1364 standard. Of course, it's not quite there yet. It does currently +handle a mix of structural and behavioral constructs. + +Icarus Verilog is not aimed at being a simulator in the traditional sense, but +a compiler that generates code employed by back-end tools. diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile new file mode 100644 index 00000000000..540816e3a11 --- /dev/null +++ b/cad/iverilog/Makefile @@ -0,0 +1,37 @@ +# $NetBSD: Makefile,v 1.1 2016/10/08 23:01:45 kamil Exp $ +# + +DISTNAME= verilog-10.1.1 +# There is confision in naming of this software, use iverilog as it's saner +PKGNAME= i${DISTNAME} +CATEGORIES= cad +MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v10/ +# FTP has newer release than GitHub tag +#MASTER_SITES= ${MASTER_SITE_GITHUB:=steveicarus/} +#GITHUB_TAG= v${PKGVERSION_NOREV:S/./_/} + +MAINTAINER= dmcmahill@NetBSD.org +HOMEPAGE= http://iverilog.icarus.com/ +COMMENT= Verilog simulation and synthesis tool (stable release version) +LICENSE= gnu-gpl-v2 + +USE_LANGUAGES= c c++ + +GNU_CONFIGURE= yes +USE_TOOLS+= gmake bison lex +TEST_TARGET= check + +INSTALLATION_DIRS+= share/doc/ivl + +# Additional files +post-install: + cd ${WRKSRC}; ${INSTALL_DATA} \ + QUICK_START.txt \ + README.txt \ + ${DESTDIR}${PREFIX}/share/doc/ivl + +.include "../../devel/gperf/buildlink3.mk" +.include "../../devel/zlib/buildlink3.mk" +.include "../../archivers/bzip2/buildlink3.mk" +.include "../../mk/readline.buildlink3.mk" +.include "../../mk/bsd.pkg.mk" diff --git a/cad/iverilog/PLIST b/cad/iverilog/PLIST new file mode 100644 index 00000000000..feae41259fd --- /dev/null +++ b/cad/iverilog/PLIST @@ -0,0 +1,58 @@ +@comment $NetBSD: PLIST,v 1.1 2016/10/08 23:01:45 kamil Exp $ +bin/iverilog +bin/iverilog-vpi +bin/vvp +include/iverilog/_pli_types.h +include/iverilog/acc_user.h +include/iverilog/ivl_target.h +include/iverilog/sv_vpi_user.h +include/iverilog/veriuser.h +include/iverilog/vpi_user.h +lib/ivl/blif-s.conf +lib/ivl/blif.conf +lib/ivl/blif.tgt +lib/ivl/cadpli.vpl +lib/ivl/include/constants.vams +lib/ivl/include/disciplines.vams +lib/ivl/ivl +lib/ivl/ivlpp +lib/ivl/null-s.conf +lib/ivl/null.conf +lib/ivl/null.tgt +lib/ivl/pcb-s.conf +lib/ivl/pcb.conf +lib/ivl/pcb.tgt +lib/ivl/sizer-s.conf +lib/ivl/sizer.conf +lib/ivl/sizer.tgt +lib/ivl/stub-s.conf +lib/ivl/stub.conf +lib/ivl/stub.tgt +lib/ivl/system.sft +lib/ivl/system.vpi +lib/ivl/v2005_math.sft +lib/ivl/v2005_math.vpi +lib/ivl/v2009.sft +lib/ivl/v2009.vpi +lib/ivl/va_math.sft +lib/ivl/va_math.vpi +lib/ivl/vhdl-s.conf +lib/ivl/vhdl.conf +lib/ivl/vhdl.tgt +lib/ivl/vhdl_sys.sft +lib/ivl/vhdl_sys.vpi +lib/ivl/vhdlpp +lib/ivl/vlog95-s.conf +lib/ivl/vlog95.conf +lib/ivl/vlog95.tgt +lib/ivl/vpi_debug.vpi +lib/ivl/vvp-s.conf +lib/ivl/vvp.conf +lib/ivl/vvp.tgt +lib/libveriuser.a +lib/libvpi.a +man/man1/iverilog-vpi.1 +man/man1/iverilog.1 +man/man1/vvp.1 +share/doc/ivl/QUICK_START.txt +share/doc/ivl/README.txt diff --git a/cad/iverilog/buildlink3.mk b/cad/iverilog/buildlink3.mk new file mode 100644 index 00000000000..46d2a367554 --- /dev/null +++ b/cad/iverilog/buildlink3.mk @@ -0,0 +1,16 @@ +# $NetBSD: buildlink3.mk,v 1.1 2016/10/08 23:01:45 kamil Exp $ + +BUILDLINK_TREE+= iverilog + +.if !defined(IVERILOG_BUILDLINK3_MK) +IVERILOG_BUILDLINK3_MK:= + +BUILDLINK_API_DEPENDS.iverilog+= iverilog>=10.1.1 +BUILDLINK_PKGSRCDIR.iverilog?= ../../cad/iverilog + +.include "../../devel/gperf/buildlink3.mk" +.include "../../devel/zlib/buildlink3.mk" +.include "../../archivers/bzip2/buildlink3.mk" +.endif # IVERILOG_BUILDLINK3_MK + +BUILDLINK_TREE+= -iverilog diff --git a/cad/iverilog/distinfo b/cad/iverilog/distinfo new file mode 100644 index 00000000000..cbed907c14e --- /dev/null +++ b/cad/iverilog/distinfo @@ -0,0 +1,9 @@ +$NetBSD: distinfo,v 1.1 2016/10/08 23:01:45 kamil Exp $ + +SHA1 (verilog-10.1.1.tar.gz) = 7f4cead8cabb90cc4525951357c43866ca710749 +RMD160 (verilog-10.1.1.tar.gz) = 77c933b712ab027b13a81e3eead7ee4f565741b7 +SHA512 (verilog-10.1.1.tar.gz) = a57fdce3d870be8ce39eb3050dabd5a2d4d491c657b85ccbf775bef7fa9a6889a18bf4d2508341ef2cc17d872b5d6c802d4fd8585e4ec7952526699ebb24bfac +Size (verilog-10.1.1.tar.gz) = 1684925 bytes +SHA1 (patch-aa) = cf075110416f6db0892129796cd83b8ae8de55fa +SHA1 (patch-ad) = bf7d227ed3b321021d8aff54cd008f4b2a1557b9 +SHA1 (patch-cadpli_Makefile) = ed21a5f529ac449c26b831cbd5fde052d9ed5466 diff --git a/cad/iverilog/patches/patch-aa b/cad/iverilog/patches/patch-aa new file mode 100644 index 00000000000..0c5a42d550d --- /dev/null +++ b/cad/iverilog/patches/patch-aa @@ -0,0 +1,14 @@ +$NetBSD: patch-aa,v 1.1 2016/10/08 23:01:45 kamil Exp $ + +gcc44 fixes + +--- elab_net.cc.orig 2010-09-27 17:42:32.000000000 +0000 ++++ elab_net.cc +@@ -26,6 +26,7 @@ + + # include <cstdlib> + # include <cstring> ++# include <memory> + # include <iostream> + # include "ivl_assert.h" + diff --git a/cad/iverilog/patches/patch-ad b/cad/iverilog/patches/patch-ad new file mode 100644 index 00000000000..bbbd15f287a --- /dev/null +++ b/cad/iverilog/patches/patch-ad @@ -0,0 +1,25 @@ +$NetBSD: patch-ad,v 1.1 2016/10/08 23:01:45 kamil Exp $ + +make sure no one sneaks a -O* in on us via one of these variables +set in the environment + +--- Makefile.in.orig 2013-08-20 04:10:31.000000000 +0900 ++++ Makefile.in 2013-12-20 11:35:09.000000000 +0900 +@@ -222,6 +222,17 @@ + + lexor.o: lexor.cc parse.h + ++# make sure no one sneaks a -O* in on us via one of these variables ++# set in the environment ++CXX_NOOPT=$(CXX:-O%=) ++CPPFLAGS_NOOPT=$(CPPFLAGS:-O%=) ++CXXFLAGS_NOOPT=$(CXXFLAGS:-O%=) ++ ++parse.o: parse.cc ++ @[ -d dep ] || mkdir dep ++ $(CXX_NOOPT) $(CPPFLAGS_NOOPT) $(CXXFLAGS_NOOPT) -MD -c $< -o $*.o ++ mv $*.d dep/$*.d ++ + parse.o: parse.cc + + # Build this in two steps to avoid parallel build issues (see pr3462585) diff --git a/cad/iverilog/patches/patch-cadpli_Makefile b/cad/iverilog/patches/patch-cadpli_Makefile new file mode 100644 index 00000000000..690208cd46a --- /dev/null +++ b/cad/iverilog/patches/patch-cadpli_Makefile @@ -0,0 +1,17 @@ +$NetBSD: patch-cadpli_Makefile,v 1.1 2016/10/08 23:01:45 kamil Exp $ + +gcc -std=gnu99 -shared -L/usr/lib -Wl,-R/usr/lib -L/usr/pkg/lib -Wl,-R/usr/pkg/lib -o cadpli.vpl cadpli.o ../libveriuser/libveriuser.o -L../vvp -lvpi +mkdir: dep: Not a directory +Makefile:52: recipe for target 'dep' failed + +--- cadpli/Makefile.in~ 2013-08-20 04:10:31.000000000 +0900 ++++ cadpli/Makefile.in 2013-12-20 22:03:29.000000000 +0900 +@@ -51,7 +51,7 @@ check: all + dep: + mkdir dep + +-%.o: %.c ++%.o: %.c dep + $(CC) $(CPPFLAGS) $(CFLAGS) @DEPENDENCY_FLAG@ -c $< + mv $*.d dep + |