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| author | dmcmahill <dmcmahill@pkgsrc.org> | 2002-10-17 01:38:42 +0000 |
|---|---|---|
| committer | dmcmahill <dmcmahill@pkgsrc.org> | 2002-10-17 01:38:42 +0000 |
| commit | cbf80901b694d2006c79613807e825b3640e3981 (patch) | |
| tree | 08c1cdce49c9ffdc86cebd63b454c4608f4c453c | |
| parent | 0442b0d350e2f75c82ac59f369865ee42e9bc945 (diff) | |
| download | pkgsrc-cbf80901b694d2006c79613807e825b3640e3981.tar.gz | |
fix the iverilog-vpi shell script (bash-isms)
| -rw-r--r-- | cad/verilog-current/Makefile | 3 | ||||
| -rw-r--r-- | cad/verilog-current/distinfo | 3 | ||||
| -rw-r--r-- | cad/verilog-current/patches/patch-aa | 24 |
3 files changed, 28 insertions, 2 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile index 7a252359f42..348daec56e7 100644 --- a/cad/verilog-current/Makefile +++ b/cad/verilog-current/Makefile @@ -1,8 +1,9 @@ -# $NetBSD: Makefile,v 1.29 2002/10/13 23:01:27 dmcmahill Exp $ +# $NetBSD: Makefile,v 1.30 2002/10/17 01:38:42 dmcmahill Exp $ # DISTNAME= verilog-${SNAPDATE} PKGNAME= verilog-current-${SNAPDATE} +PKGREVISION= 1 CATEGORIES= cad MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/ diff --git a/cad/verilog-current/distinfo b/cad/verilog-current/distinfo index ebb9941a4ae..93621c30868 100644 --- a/cad/verilog-current/distinfo +++ b/cad/verilog-current/distinfo @@ -1,5 +1,6 @@ -$NetBSD: distinfo,v 1.13 2002/10/13 23:01:27 dmcmahill Exp $ +$NetBSD: distinfo,v 1.14 2002/10/17 01:38:43 dmcmahill Exp $ SHA1 (verilog-20020921.tar.gz) = 8bd1461ad676194b37c7ba74d3a714eaacf264c9 Size (verilog-20020921.tar.gz) = 822496 bytes +SHA1 (patch-aa) = 15a15c8c85739bacbd0a85504596be023e9d97c5 SHA1 (patch-ad) = 610a4b597b056f4e951cb75bdb13a9370efec300 diff --git a/cad/verilog-current/patches/patch-aa b/cad/verilog-current/patches/patch-aa new file mode 100644 index 00000000000..bd83951479f --- /dev/null +++ b/cad/verilog-current/patches/patch-aa @@ -0,0 +1,24 @@ +$NetBSD: patch-aa,v 1.10 2002/10/17 01:38:43 dmcmahill Exp $ + +--- iverilog-vpi.sh.orig Wed Sep 18 19:25:18 2002 ++++ iverilog-vpi.sh +@@ -84,8 +84,7 @@ OUT=$OUT".vpi" + compile_errors=0 + + # Compile all the source files into object files +-for src +-in $CCSRC ++for src in $CCSRC + do + base=`basename $src .c` + obj=$base".o" +@@ -95,8 +94,7 @@ do + OBJ="$OBJ $obj" + done + +-for src +-in $CXSRC ++for src in $CXSRC + do + base=`basename $src .cc` + obj=$base".o" |