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authorkamil <kamil>2016-10-08 23:01:45 +0000
committerkamil <kamil>2016-10-08 23:01:45 +0000
commiteeb160d0d8cf4ea5d94f218d038c2eb202f7b93f (patch)
treef04061b412172945ea59734611cbafef888f1874 /cad/Makefile
parentdff261dedd56f67fb27e833759f42086452ccb28 (diff)
downloadpkgsrc-eeb160d0d8cf4ea5d94f218d038c2eb202f7b93f.tar.gz
Import iverilog (Icarus Verilog) 10.1.1 as cad/iverilog
It's a rename of cad/verilog to a better name. Updated DESCR for new package: Icarus Verilog is intended to compile ALL of the Verilog HDL as described in the IEEE-1364 standard. Of course, it's not quite there yet. It does currently handle a mix of structural and behavioral constructs. Icarus Verilog is not aimed at being a simulator in the traditional sense, but a compiler that generates code employed by back-end tools. No objections to rename from <gdt>
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