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| author | drochner <drochner@pkgsrc.org> | 2011-04-13 16:14:10 +0000 |
|---|---|---|
| committer | drochner <drochner@pkgsrc.org> | 2011-04-13 16:14:10 +0000 |
| commit | 8e62ec8decdf87351a93e47a0c31749f9156ea51 (patch) | |
| tree | 7ece6a0de30f3e0a816aa0c1d9fc5e520d12c0fa /cad/MyHDL-iverilog/Makefile | |
| parent | 9c876f9e4392ac018f96becff1f6c1c7294a3beb (diff) | |
| download | pkgsrc-8e62ec8decdf87351a93e47a0c31749f9156ea51.tar.gz | |
sync w/ base pkg
Diffstat (limited to 'cad/MyHDL-iverilog/Makefile')
| -rw-r--r-- | cad/MyHDL-iverilog/Makefile | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/cad/MyHDL-iverilog/Makefile b/cad/MyHDL-iverilog/Makefile index 1b89b0cd81f..4ddd817601d 100644 --- a/cad/MyHDL-iverilog/Makefile +++ b/cad/MyHDL-iverilog/Makefile @@ -1,8 +1,8 @@ -# $NetBSD: Makefile,v 1.5 2009/04/01 17:26:06 drochner Exp $ +# $NetBSD: Makefile,v 1.6 2011/04/13 16:14:10 drochner Exp $ # -DISTNAME= myhdl-0.5.1 -PKGNAME= MyHDL-iverilog-0.5.1 +DISTNAME= myhdl-0.7 +PKGNAME= MyHDL-iverilog-0.7 CATEGORIES= cad python MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=myhdl/} @@ -19,5 +19,9 @@ do-install: ${INSTALL_DATA} ${WRKSRC}/cosimulation/icarus/myhdl.vpi \ ${DESTDIR}${PREFIX}/lib/ivl -.include "../../cad/verilog-current/buildlink3.mk" +# XXX would require Python dependency +#do-test: +# (cd ${WRKSRC}/cosimulation/icarus/test && ${PYTHONBIN} test_all.py) + +.include "../../cad/verilog/buildlink3.mk" .include "../../mk/bsd.pkg.mk" |