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| author | dmcmahill <dmcmahill> | 2002-12-08 04:21:43 +0000 |
|---|---|---|
| committer | dmcmahill <dmcmahill> | 2002-12-08 04:21:43 +0000 |
| commit | 0ede5a4e448f6562588c6de9e403b77e4512afcd (patch) | |
| tree | 88587b039b93e57336b4aa3101214b5da789d3b3 /cad/covered-current/Makefile | |
| parent | 653f502dd72c02f15a124584d2a028273ed604af (diff) | |
| download | pkgsrc-0ede5a4e448f6562588c6de9e403b77e4512afcd.tar.gz | |
initial import of covered-current-20021127.
This is a development snapshot. Packages of the released/stable
versions will be imported as 'cad/covered' when available.
Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?". When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.
Please note that this package is a development snapshot and while it
contains the latest and greatest features, it may be buggy as well.
There is a seperate package which is made of the stable releases.
Diffstat (limited to 'cad/covered-current/Makefile')
| -rw-r--r-- | cad/covered-current/Makefile | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/cad/covered-current/Makefile b/cad/covered-current/Makefile new file mode 100644 index 00000000000..6a408cf7cfa --- /dev/null +++ b/cad/covered-current/Makefile @@ -0,0 +1,26 @@ +# $NetBSD: Makefile,v 1.1.1.1 2002/12/08 04:21:43 dmcmahill Exp $ +# + +DISTNAME= covered-${SNAPDATE} +PKGNAME= covered-current-${SNAPDATE} +CATEGORIES= cad +MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=covered/} + +MAINTAINER= dmcmahill@netbsd.org +HOMEPAGE= http://covered.sourceforge.net +COMMENT= Verilog code coverage analyzer + +BUILD_DEPENDS+= bison-[0-9]*:../../devel/bison +BUILD_DEPENDS+= gperf-2.7.2:../../devel/gperf +DEPENDS+= verilog{,-current}-[0-9]*:../../cad/verilog + +SNAPDATE= 20021127 +GNU_CONFIGURE= YES +USE_GMAKE= YES +TEST_DIRS= ${WRKSRC}/diags/regress +TEST_TARGET= #defined + +post-patch: + ${CHMOD} 755 ${WRKSRC}/missing + +.include "../../mk/bsd.pkg.mk" |