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| author | jmmv <jmmv> | 2003-05-06 17:40:18 +0000 |
|---|---|---|
| committer | jmmv <jmmv> | 2003-05-06 17:40:18 +0000 |
| commit | f4ab4bfd7ecc3cdfad69293a69f2c92d7ae60161 (patch) | |
| tree | 37ae7d212f46ef8018a7bd8c13edba7da1a47ed9 /cad/ipal-current | |
| parent | 4f4f1b81d13abc86b32673c726b70d17a6202d29 (diff) | |
| download | pkgsrc-f4ab4bfd7ecc3cdfad69293a69f2c92d7ae60161.tar.gz | |
Drop trailing whitespace. Ok'ed by wiz.
Diffstat (limited to 'cad/ipal-current')
| -rw-r--r-- | cad/ipal-current/DESCR | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/ipal-current/DESCR b/cad/ipal-current/DESCR index cf16d952999..fd5ed8a80b6 100644 --- a/cad/ipal-current/DESCR +++ b/cad/ipal-current/DESCR @@ -19,6 +19,6 @@ it, producing a Verilog program that logically describes the design. This use useful for moving old designs to new tools. Please note that this package is a development snapshot and while it contains -the latest and greatest features, it may be buggy as well. When +the latest and greatest features, it may be buggy as well. When available there will be a seperate ipal package which will be made of the stable releases. |