diff options
| author | drochner <drochner> | 2005-01-05 15:20:10 +0000 |
|---|---|---|
| committer | drochner <drochner> | 2005-01-05 15:20:10 +0000 |
| commit | e2b2c95676baa23f1153003d8c122affa029bb13 (patch) | |
| tree | fbf8a4e75b09174b530c71d67084f5fb6acf013c /cad/py-MyHDL/Makefile | |
| parent | 08610f71cdecb434939c02cc747a12458f99f48c (diff) | |
| download | pkgsrc-e2b2c95676baa23f1153003d8c122affa029bb13.tar.gz | |
update to 0.4.1
changes:
* VCD output for waveform viewing
- function additions
- needs Python 2.3, 2.4 is OK
* Conversion to Verilog to provide a path to implementation
* Added cosimulation support for the cver Verilog simulator.
- bugfixes
Diffstat (limited to 'cad/py-MyHDL/Makefile')
| -rw-r--r-- | cad/py-MyHDL/Makefile | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/cad/py-MyHDL/Makefile b/cad/py-MyHDL/Makefile index 0000cf62f00..8829273af8d 100644 --- a/cad/py-MyHDL/Makefile +++ b/cad/py-MyHDL/Makefile @@ -1,10 +1,10 @@ -# $NetBSD: Makefile,v 1.6 2004/07/22 09:16:00 recht Exp $ +# $NetBSD: Makefile,v 1.7 2005/01/05 15:20:10 drochner Exp $ # -DISTNAME= myhdl-0.2 -PKGNAME= ${PYPKGPREFIX}-MyHDL-0.2 +DISTNAME= myhdl-0.4.1 +PKGNAME= ${PYPKGPREFIX}-MyHDL-0.4.1 CATEGORIES= cad python -MASTER_SITES= http://jandecaluwe.com/Tools/MyHDL/ +MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=myhdl/} MAINTAINER= tech-pkg@NetBSD.org HOMEPAGE= http://jandecaluwe.com/Tools/MyHDL/Overview.html @@ -12,7 +12,7 @@ COMMENT= Hardware description in Python USE_BUILDLINK3= YES PYDISTUTILSPKG= yes -PYTHON_VERSIONS_ACCEPTED= 22 22pth 23 23pth +PYTHON_VERSIONS_ACCEPTED= 23 23pth 24 24pth .include "../../lang/python/extension.mk" .include "../../mk/bsd.pkg.mk" |