diff options
| author | drochner <drochner> | 2011-04-13 14:47:18 +0000 |
|---|---|---|
| committer | drochner <drochner> | 2011-04-13 14:47:18 +0000 |
| commit | 8c0e0dfff4c1207b0644834300f89e0f7ecf2baf (patch) | |
| tree | 478e3bcb3442e37a57db50e0e298fa86d5aae2be /cad/py-MyHDL/PLIST | |
| parent | bc4be43cda472163e309ae68950e85f73df4e08a (diff) | |
| download | pkgsrc-8c0e0dfff4c1207b0644834300f89e0f7ecf2baf.tar.gz | |
update to 0.7
too many changes to list here, see the release notes
Diffstat (limited to 'cad/py-MyHDL/PLIST')
| -rw-r--r-- | cad/py-MyHDL/PLIST | 41 |
1 files changed, 28 insertions, 13 deletions
diff --git a/cad/py-MyHDL/PLIST b/cad/py-MyHDL/PLIST index bd5b64eda0e..c3197760143 100644 --- a/cad/py-MyHDL/PLIST +++ b/cad/py-MyHDL/PLIST @@ -1,7 +1,10 @@ -@comment $NetBSD: PLIST,v 1.6 2009/06/14 17:35:55 joerg Exp $ +@comment $NetBSD: PLIST,v 1.7 2011/04/13 14:47:18 drochner Exp $ ${PYSITELIB}/myhdl/_Cosimulation.py ${PYSITELIB}/myhdl/_Cosimulation.pyc ${PYSITELIB}/myhdl/_Cosimulation.pyo +${PYSITELIB}/myhdl/_ShadowSignal.py +${PYSITELIB}/myhdl/_ShadowSignal.pyc +${PYSITELIB}/myhdl/_ShadowSignal.pyo ${PYSITELIB}/myhdl/_Signal.py ${PYSITELIB}/myhdl/_Signal.pyc ${PYSITELIB}/myhdl/_Signal.pyo @@ -44,9 +47,6 @@ ${PYSITELIB}/myhdl/_instance.pyo ${PYSITELIB}/myhdl/_intbv.py ${PYSITELIB}/myhdl/_intbv.pyc ${PYSITELIB}/myhdl/_intbv.pyo -${PYSITELIB}/myhdl/_isGenSeq.py -${PYSITELIB}/myhdl/_isGenSeq.pyc -${PYSITELIB}/myhdl/_isGenSeq.pyo ${PYSITELIB}/myhdl/_join.py ${PYSITELIB}/myhdl/_join.pyc ${PYSITELIB}/myhdl/_join.pyo @@ -56,21 +56,36 @@ ${PYSITELIB}/myhdl/_misc.pyo ${PYSITELIB}/myhdl/_simulator.py ${PYSITELIB}/myhdl/_simulator.pyc ${PYSITELIB}/myhdl/_simulator.pyo -${PYSITELIB}/myhdl/_toVerilog/__init__.py -${PYSITELIB}/myhdl/_toVerilog/__init__.pyc -${PYSITELIB}/myhdl/_toVerilog/__init__.pyo -${PYSITELIB}/myhdl/_toVerilog/_analyze.py -${PYSITELIB}/myhdl/_toVerilog/_analyze.pyc -${PYSITELIB}/myhdl/_toVerilog/_analyze.pyo -${PYSITELIB}/myhdl/_toVerilog/_convert.py -${PYSITELIB}/myhdl/_toVerilog/_convert.pyc -${PYSITELIB}/myhdl/_toVerilog/_convert.pyo ${PYSITELIB}/myhdl/_traceSignals.py ${PYSITELIB}/myhdl/_traceSignals.pyc ${PYSITELIB}/myhdl/_traceSignals.pyo +${PYSITELIB}/myhdl/_tristate.py +${PYSITELIB}/myhdl/_tristate.pyc +${PYSITELIB}/myhdl/_tristate.pyo ${PYSITELIB}/myhdl/_unparse.py ${PYSITELIB}/myhdl/_unparse.pyc ${PYSITELIB}/myhdl/_unparse.pyo ${PYSITELIB}/myhdl/_util.py ${PYSITELIB}/myhdl/_util.pyc ${PYSITELIB}/myhdl/_util.pyo +${PYSITELIB}/myhdl/conversion/__init__.py +${PYSITELIB}/myhdl/conversion/__init__.pyc +${PYSITELIB}/myhdl/conversion/__init__.pyo +${PYSITELIB}/myhdl/conversion/_analyze.py +${PYSITELIB}/myhdl/conversion/_analyze.pyc +${PYSITELIB}/myhdl/conversion/_analyze.pyo +${PYSITELIB}/myhdl/conversion/_misc.py +${PYSITELIB}/myhdl/conversion/_misc.pyc +${PYSITELIB}/myhdl/conversion/_misc.pyo +${PYSITELIB}/myhdl/conversion/_toVHDL.py +${PYSITELIB}/myhdl/conversion/_toVHDL.pyc +${PYSITELIB}/myhdl/conversion/_toVHDL.pyo +${PYSITELIB}/myhdl/conversion/_toVHDLPackage.py +${PYSITELIB}/myhdl/conversion/_toVHDLPackage.pyc +${PYSITELIB}/myhdl/conversion/_toVHDLPackage.pyo +${PYSITELIB}/myhdl/conversion/_toVerilog.py +${PYSITELIB}/myhdl/conversion/_toVerilog.pyc +${PYSITELIB}/myhdl/conversion/_toVerilog.pyo +${PYSITELIB}/myhdl/conversion/_verify.py +${PYSITELIB}/myhdl/conversion/_verify.pyc +${PYSITELIB}/myhdl/conversion/_verify.pyo |