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| author | drochner <drochner@pkgsrc.org> | 2003-06-05 18:50:54 +0000 |
|---|---|---|
| committer | drochner <drochner@pkgsrc.org> | 2003-06-05 18:50:54 +0000 |
| commit | dfe2fe099e0431a71e9315f116a7d2e93d99cfed (patch) | |
| tree | 8ec2cc33e54efd8d5bc7ef0e689ac0c11227c763 /cad/py-MyHDL | |
| parent | d32bf503811656ed47bd0054f87bbd6106bd3b17 (diff) | |
| download | pkgsrc-dfe2fe099e0431a71e9315f116a7d2e93d99cfed.tar.gz | |
a library which uses Python as a hardware description language, using
the new generator constructs (like pysim, at a first glance)
Diffstat (limited to 'cad/py-MyHDL')
| -rw-r--r-- | cad/py-MyHDL/DESCR | 7 | ||||
| -rw-r--r-- | cad/py-MyHDL/Makefile | 18 | ||||
| -rw-r--r-- | cad/py-MyHDL/PLIST | 28 | ||||
| -rw-r--r-- | cad/py-MyHDL/distinfo | 4 |
4 files changed, 57 insertions, 0 deletions
diff --git a/cad/py-MyHDL/DESCR b/cad/py-MyHDL/DESCR new file mode 100644 index 00000000000..fd819237dc9 --- /dev/null +++ b/cad/py-MyHDL/DESCR @@ -0,0 +1,7 @@ +MyHDL is a Python package for using Python as a hardware +description language. Popular hardware description languages, like +Verilog and VHDL, are compiled languages. MyHDL with Python +can be viewed as a "scripting language" counterpart of such +languages. However, Python is more accurately described as a very +high level language (VHLL). MyHDL users have access to the +amazing power and elegance of Python for their modeling work. diff --git a/cad/py-MyHDL/Makefile b/cad/py-MyHDL/Makefile new file mode 100644 index 00000000000..e9e5c0738bc --- /dev/null +++ b/cad/py-MyHDL/Makefile @@ -0,0 +1,18 @@ +# $NetBSD: Makefile,v 1.1.1.1 2003/06/05 18:50:54 drochner Exp $ +# + +DISTNAME= myhdl-0.2 +PKGNAME= ${PYPKGPREFIX}-MyHDL-0.2 +CATEGORIES= cad +MASTER_SITES= http://jandecaluwe.com/Tools/MyHDL/ + +MAINTAINER= packages@netbsd.org +HOMEPAGE= http://jandecaluwe.com/Tools/MyHDL/Overview.html +COMMENT= Hardware description in Python + +USE_BUILDLINK2= YES +PYDISTUTILSPKG= yes +PYTHON_VERSIONS_ACCEPTED= 22 22pth + +.include "../../lang/python/extension.mk" +.include "../../mk/bsd.pkg.mk" diff --git a/cad/py-MyHDL/PLIST b/cad/py-MyHDL/PLIST new file mode 100644 index 00000000000..2d4c6ee10f8 --- /dev/null +++ b/cad/py-MyHDL/PLIST @@ -0,0 +1,28 @@ +@comment $NetBSD: PLIST,v 1.1.1.1 2003/06/05 18:50:54 drochner Exp $ +${PYSITELIB}/myhdl/Cosimulation.py +${PYSITELIB}/myhdl/Cosimulation.pyc +${PYSITELIB}/myhdl/Signal.py +${PYSITELIB}/myhdl/Signal.pyc +${PYSITELIB}/myhdl/Simulation.py +${PYSITELIB}/myhdl/Simulation.pyc +${PYSITELIB}/myhdl/__init__.py +${PYSITELIB}/myhdl/__init__.pyc +${PYSITELIB}/myhdl/_simulator.py +${PYSITELIB}/myhdl/_simulator.pyc +${PYSITELIB}/myhdl/delay.py +${PYSITELIB}/myhdl/delay.pyc +${PYSITELIB}/myhdl/intbv.py +${PYSITELIB}/myhdl/intbv.pyc +${PYSITELIB}/myhdl/test_Cosimulation.py +${PYSITELIB}/myhdl/test_Cosimulation.pyc +${PYSITELIB}/myhdl/test_Signal.py +${PYSITELIB}/myhdl/test_Signal.pyc +${PYSITELIB}/myhdl/test_Simulation.py +${PYSITELIB}/myhdl/test_Simulation.pyc +${PYSITELIB}/myhdl/test_all.py +${PYSITELIB}/myhdl/test_all.pyc +${PYSITELIB}/myhdl/test_intbv.py +${PYSITELIB}/myhdl/test_intbv.pyc +${PYSITELIB}/myhdl/util.py +${PYSITELIB}/myhdl/util.pyc +@dirrm ${PYSITELIB}/myhdl diff --git a/cad/py-MyHDL/distinfo b/cad/py-MyHDL/distinfo new file mode 100644 index 00000000000..9fdab523298 --- /dev/null +++ b/cad/py-MyHDL/distinfo @@ -0,0 +1,4 @@ +$NetBSD: distinfo,v 1.1.1.1 2003/06/05 18:50:54 drochner Exp $ + +SHA1 (myhdl-0.2.tar.gz) = e9c09d8cac1478eec4986f7a159e2af506a286a8 +Size (myhdl-0.2.tar.gz) = 358159 bytes |