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| author | drochner <drochner> | 2003-08-25 11:21:50 +0000 |
|---|---|---|
| committer | drochner <drochner> | 2003-08-25 11:21:50 +0000 |
| commit | f81abfaae55b187d581ce0a89974b4560d104c1e (patch) | |
| tree | 311c13f5c482acf3b942bd5a62625a6267f55ef2 /cad/verilog-current/Makefile | |
| parent | 28224fcf8e9ec721e453c6a62c089d10fd1f38fd (diff) | |
| download | pkgsrc-f81abfaae55b187d581ce0a89974b4560d104c1e.tar.gz | |
update to the 20030815 shapshot
changes are basically bugfixes, and improvements in the FPGA synthesis
area
Diffstat (limited to 'cad/verilog-current/Makefile')
| -rw-r--r-- | cad/verilog-current/Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile index b00f04c20bc..60d88455ac8 100644 --- a/cad/verilog-current/Makefile +++ b/cad/verilog-current/Makefile @@ -1,4 +1,4 @@ -# $NetBSD: Makefile,v 1.34 2003/07/17 21:25:27 grant Exp $ +# $NetBSD: Makefile,v 1.35 2003/08/25 11:21:50 drochner Exp $ # DISTNAME= verilog-${SNAPDATE} @@ -17,7 +17,7 @@ BUILD_DEPENDS+= gperf-2.7.2:../../devel/gperf CONFLICTS+= verilog-[0-9]* -SNAPDATE= 20030705 +SNAPDATE= 20030815 USE_BUILDLINK2= yes GNU_CONFIGURE= yes USE_GMAKE= yes |