update to verilog-current-20001119

changes since the last packaged version (from the authors announcements):

Icarus Verilog snapshot 20001119
--------------------------------
The big change here (code wise) is improved and corrected constant
propagation. I was missing OR, NOR, NAND and XOR propagations, and
got some of the AND calculations wrong. This fixes this shortcoming
and in some cases this actually may speed up your compile a tiny bit.
Some more dangling signals are also eliminated.

supply nets are now working (PR#17). They also will trigger constant
propagation (as they have constant values) in certain cases.

Those of you doing cygwin compiles have trouble compiling parse.cc. I've
put into the cygwin.txt some slightly better instructions for dealing with
this situation, when it comes up.

I've also added missing symbols to ivl.def, so that tgt-stub properly
links.

Icarus Verilog snapshot 20001112
--------------------------------
This snapshot includes support for MOS et al devices as contributed
by Tim Leight. It appears to actually work as advertised, and I also
have from him a collection of tests that I'll be adding to the test
suite as soon as I get copyright information from him. So if you have
been dreaming of simulating MOS devices with Icarus Verilog, give this
a try. This update also fixed PR#27.

I've also cleared up a few bugs related to unconnected module ports.
Module port syntax is pretty byzantine, as PR#38 shows.

The loadable target API has gained access to flip-flops. This is required
for PLD code generation to work. I think the ivl_target API now supports
the minimum devices needed to generate PLD files, and I'm on to the task
of getting ancillary PAL support working.

Icarus Verilog snapshot 20001104
--------------------------------
Yes, I've managed to find the right bits to get Icarus Verilog to compile
on RedHat 7.0, and this snapshot includes those fixes. It took some back-
and-forth with tech support at RedHat to get it going.

I've also fixed up make check so that it works in general. If you use
"make check" after building, the makefile will run the examples/hello.vl
program through the local parts to make sure they minimally work.

I've added support for the "time" data time and more complete support
for the $time system function. These should work properly in all cases
now, so cases of not working are worthy of a bug report.

I've also integrated a re-implementation of sequential UDPs from Stephan
Boettcher, so I would appreciate it if all you folks using primitives
give this a fresh test. (It should be an improvement.)

This is a relatively small message, which doesn't reflect the complexity
of the changes. The "time" support in particular caused a lot of threads
to be pulled. Also, I've been doing some PLD stuff on the side, so I've
been busy.

I've also knocked of PR#11, 14, 33, 34, 39 and a few other bugs.

1 files changed, 3 insertions, 3 deletions

diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index 558f4066f39..8d7863858ad 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,8 +1,8 @@
-# $NetBSD: Makefile,v 1.8 2000/10/27 03:59:47 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.9 2000/11/24 18:03:58 dmcmahill Exp $
 #
 
-DISTNAME=	verilog-20001021
-PKGNAME=	verilog-current-20001021
+DISTNAME=	verilog-20001119
+PKGNAME=	verilog-current-20001119
 CATEGORIES=	cad
 MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/snapshots/