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| author | dmcmahill <dmcmahill> | 2004-09-21 02:23:19 +0000 |
|---|---|---|
| committer | dmcmahill <dmcmahill> | 2004-09-21 02:23:19 +0000 |
| commit | 8b0ca8fcd1a6197ba4f87997293346a84c35f2f8 (patch) | |
| tree | 1657be59557cd90343f4b0764e42b4cf75a168c0 /cad/verilog-current | |
| parent | e1a1a863b5d0926cbd1a86534bb67d351a0ab926 (diff) | |
| download | pkgsrc-8b0ca8fcd1a6197ba4f87997293346a84c35f2f8.tar.gz | |
update to verilog-current-20040915. Changes in this snapshot:
The big news is that module instance arrays now work. Gate and UDP
instance arrays have worked for a while, but module instance arrays
were more tricky because of the scope arrys they create. The issues
have been dealt with, and module instance arrays are now supported.
An interesting but subtle set of bugs in the evaluation of ternary
expressions has been fixed. The problems expressed themselves when the
condition expression was constant.
Degenerate wait statements now work properly.
The @* syntax apparently missed sensitivities in l-value expressions
of assignment statements. This led to subtle bugs in carefully crafted
bits of code.
Verilog attributes are properly parsed in a few more contexts. Also,
some specify syntax cases have been fixed.
Some minor spelling and documentation errors have been fixed, along
with assorted compiler warnings.
Diffstat (limited to 'cad/verilog-current')
| -rw-r--r-- | cad/verilog-current/Makefile | 4 | ||||
| -rw-r--r-- | cad/verilog-current/distinfo | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile index 508e2107162..7169c3911f6 100644 --- a/cad/verilog-current/Makefile +++ b/cad/verilog-current/Makefile @@ -1,4 +1,4 @@ -# $NetBSD: Makefile,v 1.41 2004/09/02 01:55:47 dmcmahill Exp $ +# $NetBSD: Makefile,v 1.42 2004/09/21 02:23:19 dmcmahill Exp $ # DISTNAME= verilog-${SNAPDATE} @@ -17,7 +17,7 @@ CONFLICTS+= verilog-[0-9]* USE_BUILDLINK3= yes BUILD_DEPENDS+= bison-[0-9]*:../../devel/bison -SNAPDATE= 20040828 +SNAPDATE= 20040915 GNU_CONFIGURE= yes USE_GNU_TOOLS+= lex make CONFIGURE_ARGS+= --without-ipal diff --git a/cad/verilog-current/distinfo b/cad/verilog-current/distinfo index 6c100866632..e17bc3a3559 100644 --- a/cad/verilog-current/distinfo +++ b/cad/verilog-current/distinfo @@ -1,5 +1,5 @@ -$NetBSD: distinfo,v 1.21 2004/09/02 01:55:47 dmcmahill Exp $ +$NetBSD: distinfo,v 1.22 2004/09/21 02:23:19 dmcmahill Exp $ -SHA1 (verilog-20040828.tar.gz) = b6e44dc0556247687d068c913bcd4080edfc0285 -Size (verilog-20040828.tar.gz) = 1368773 bytes +SHA1 (verilog-20040915.tar.gz) = 44bf7d444fa2dac6b598d133c3e86557662679c4 +Size (verilog-20040915.tar.gz) = 1371319 bytes SHA1 (patch-ad) = ef3fe90fb096b96807b2e5766f3ac6849867352a |