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| author | mef <mef> | 2016-10-17 13:33:57 +0000 |
|---|---|---|
| committer | mef <mef> | 2016-10-17 13:33:57 +0000 |
| commit | 901479cd77d6ab824b41587a7bc59fac4be9fc0c (patch) | |
| tree | d36b00d99b694ee890a989e13feb1f2cc782d833 /cad/verilog-mode | |
| parent | a4ee0d879557eefd1e90e166be1811e0085a9db0 (diff) | |
| download | pkgsrc-901479cd77d6ab824b41587a7bc59fac4be9fc0c.tar.gz | |
Updated cad/gtkwave to 3.3.77
-----------------------------
3.3.77 03oct16 Updated documentation to include an appendix on FST
implementation details.
Removed '!A || (A && B)' is equivalent to '!A || B' redundant
condition checks where found in source.
Added hier_ignore_escapes rc variable.
Dynamic resizing tweaks for when it is turned off.
Added HUWL-? value types to signal_change_list() to keep GHW
files from crashing Tcl scripts.
Diffstat (limited to 'cad/verilog-mode')
0 files changed, 0 insertions, 0 deletions