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| author | rillig <rillig> | 2005-05-23 08:26:03 +0000 |
|---|---|---|
| committer | rillig <rillig> | 2005-05-23 08:26:03 +0000 |
| commit | 88fbe0b4f045070c1d74e80e2ff7448527e556e4 (patch) | |
| tree | a88b53a484071e09249ef5ae57e9f69b5ffb0a67 /cad/verilog | |
| parent | 7caf0db822a5ebc4e6dc7732d45fa9bd3e9dea13 (diff) | |
| download | pkgsrc-88fbe0b4f045070c1d74e80e2ff7448527e556e4.tar.gz | |
Removed trailing white-space.
Diffstat (limited to 'cad/verilog')
| -rw-r--r-- | cad/verilog/DESCR | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/verilog/DESCR b/cad/verilog/DESCR index a1f488afa95..b59d099759e 100644 --- a/cad/verilog/DESCR +++ b/cad/verilog/DESCR @@ -4,7 +4,7 @@ format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. - + The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and complex standard, so it will take some time for it to get there, but that's |