update to covered-current-20021214 as part of fixing compile problems noted

in recent bulk builds.

Release covered-20021214 made.  This release is a bug fix release.  See list below
for details.  Bugs that lead to infinite looping in the score command and segmentation
faults should now be cleared up.  Please let me know if there are any other bugs that
need to be addressed before first stable release.  Development documentation updated
to match changes in files.  Regression suite has been updated quite a bit from last
time.  There are now over 125 diagnostics in the regression suite (my goal was to
write about 100 before first stable release).

  - Segmentation fault fixes in report command
  - Parser can now handle all net types (not just wire).  Diagnostics added to regression
    suite to verify their proper handling.
  - Parser updated to handle net declaration assignments (e.g., wire a = b & c;).
    Diagnostics added to verify proper handling.
  - Added human-understandable error messages in parser to help identify file and
    line number along with a quasi-helpful error message description.
  - When parser error is found, Covered exits after parsing phase without continuing
    to write CDD file.
  - Fixed bug where a multi-bit select expression existed in a module that was
    instantiated more than once.  Assertion error fired in this case.
  - Updated regression suite for VCS testing.
  - Fixed bug where parameters were used in modules that were instantiated more than
    once.
  - Fixed bug that dealt with parameters (see param6.1.v for test case).
  - Fixed bug where a delay statement was the last statement in a statement block used
    by Covered.  Added diagnostics to verify correct behavior.
  - Fixed infinite loop problem with db_add_statement function.
  - Fixed infinite loop problem with statement_set_stop function.
  - Fixed bug with parsing order.  When an instance is found for a module that has
    already been parsed, the instance was incorrectly being handled.  Bug replicated
    with instance6.v diagnostic.
  - Fixed output of edge-triggered events to add @(...) around the expression (they
    were easily confused with other code that could exist on the same line).
  - Fixed bug in parser to not allow module to be parsed more than once.
  - Fixed bug that lead to an assertion error (see instance6.1.v for test case).
  - Fixing bug with calculating list and concatenation lengths when MBIT_SEL
    expressions were included.
  - Changed Covered's handling of -y directories.  Before, all files in these directories
    were fed into the parser to look for missing modules.  Now, when a module is needed,
    the module name is used to find the matching filename in the -y list (basically,
    the -y option works like the -y option in Icarus Verilog and VCS).  This fix really
    streamlined the parsing phase and fixed several bugs.
  - Memory declarations are now properly ignored (produced segmentation fault previously).
  - Fixed report command to display all lines and expressions in order according to
    their line number (the problem is REALLY fixed now).
  - Removed hierarchical references from being scored.

All in all, you should notice a huge improvement in the parsing speed, syntax errors are
reported better, more Verilog syntax should be handled properly, the score command will
run a bit faster than before, and the reports should be a bit easier to read.  Segmentation
faults and assertion errors should become lesser in number (if not gone altogether?).
I am feeling pretty confident that we are getting close to a stable release as I have
been able to generate a CDD file for a chip that is millions of gates in size (CDD file
was created in the range of 30 - 45 seconds!)  Keep the bug reports coming.  I have some
things to work on for next release already.

5 files changed, 58 insertions, 5 deletions

diff --git a/cad/covered-current/Makefile b/cad/covered-current/Makefile
index 6a408cf7cfa..4152e53a52c 100644
--- a/cad/covered-current/Makefile
+++ b/cad/covered-current/Makefile
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.1.1.1 2002/12/08 04:21:43 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.2 2003/02/04 02:42:21 dmcmahill Exp $
 #
 
 DISTNAME=	covered-${SNAPDATE}
@@ -14,7 +14,7 @@ BUILD_DEPENDS+=	bison-[0-9]*:../../devel/bison
 BUILD_DEPENDS+=	gperf-2.7.2:../../devel/gperf
 DEPENDS+=	verilog{,-current}-[0-9]*:../../cad/verilog
 
-SNAPDATE=	20021127
+SNAPDATE=	20021214
 GNU_CONFIGURE=	YES
 USE_GMAKE=	YES
 TEST_DIRS=	${WRKSRC}/diags/regress
diff --git a/cad/covered-current/distinfo b/cad/covered-current/distinfo
index 1c331e5c582..446025781d5 100644
--- a/cad/covered-current/distinfo
+++ b/cad/covered-current/distinfo
@@ -1,4 +1,7 @@
-$NetBSD: distinfo,v 1.1.1.1 2002/12/08 04:21:43 dmcmahill Exp $
+$NetBSD: distinfo,v 1.2 2003/02/04 02:42:21 dmcmahill Exp $
 
-SHA1 (covered-20021127.tar.gz) = d80e5b3bce539eea57c7566f84c5f6b88d37c17b
-Size (covered-20021127.tar.gz) = 818998 bytes
+SHA1 (covered-20021214.tar.gz) = ce50b83beb52967f69842eaac605a68cb89a6198
+Size (covered-20021214.tar.gz) = 843925 bytes
+SHA1 (patch-aa) = e5b4e0f81899610c766879744010e885d2eec84a
+SHA1 (patch-ab) = 711dc0e2fe7f391c47195a7171daf3564db0fe18
+SHA1 (patch-ac) = 5174c7a46494063ced93eaf9cc2aeea1eaf1b8be
diff --git a/cad/covered-current/patches/patch-aa b/cad/covered-current/patches/patch-aa
new file mode 100644
index 00000000000..2320478ceb4
--- /dev/null
+++ b/cad/covered-current/patches/patch-aa
@@ -0,0 +1,14 @@
+$NetBSD: patch-aa,v 1.1 2003/02/04 02:42:21 dmcmahill Exp $
+
+--- src/parser_misc.h.orig	Mon Nov  4 19:20:08 2002
++++ src/parser_misc.h	Mon Feb  3 21:19:22 2003
+@@ -23,4 +23,9 @@
+ 
+ #define YYLTYPE struct vlltype
++
++/* This for compatibility with new and older bison versions. */
++#ifndef yylloc
++# define yylloc VLlloc
++#endif
+ extern YYLTYPE yylloc;
+ 
diff --git a/cad/covered-current/patches/patch-ab b/cad/covered-current/patches/patch-ab
new file mode 100644
index 00000000000..043d604f55c
--- /dev/null
+++ b/cad/covered-current/patches/patch-ab
@@ -0,0 +1,15 @@
+$NetBSD: patch-ab,v 1.1 2003/02/04 02:42:21 dmcmahill Exp $
+
+--- src/lexer.l.orig	Thu Dec  5 21:18:59 2002
++++ src/lexer.l	Mon Feb  3 21:28:36 2003
+@@ -15,9 +15,9 @@
+ #include "defines.h"
+ #include "signal.h"
++#include "parser_misc.h"
+ #include "parser.h"
+ #include "util.h"
+ #include "link.h"
+ #include "vector.h"
+-#include "parser_misc.h"
+ #include "keywords.h"
+ 
diff --git a/cad/covered-current/patches/patch-ac b/cad/covered-current/patches/patch-ac
new file mode 100644
index 00000000000..a114933c4e0
--- /dev/null
+++ b/cad/covered-current/patches/patch-ac
@@ -0,0 +1,21 @@
+$NetBSD: patch-ac,v 1.1 2003/02/04 02:42:22 dmcmahill Exp $
+
+--- src/parser.y.orig	Fri Dec 13 11:49:50 2002
++++ src/parser.y	Mon Feb  3 21:26:01 2003
+@@ -46,4 +46,16 @@
+ int yydebug = 1; 
+ */
++
++/* Recent version of bison expect that the user supply a
++   YYLLOC_DEFAULT macro that makes up a yylloc value from existing
++   values. I need to supply an explicit version to account for the
++   text field, that otherwise won't be copied. */
++# define YYLLOC_DEFAULT(Current, Rhs, N)         \
++  Current.first_line   = Rhs[1].first_line;      \
++  Current.first_column = Rhs[1].first_column;    \
++  Current.last_line    = Rhs[N].last_line;       \
++  Current.last_column  = Rhs[N].last_column;     \
++  Current.text         = Rhs[1].text;
++
+ %}
+