Update MyHDL from 0.8.1 to 0.9.0

pkgsrc packages altered:
 - cad/MyHDL-gplcver
 - cad/MyHDL-iverilog
 - cad/py-MyHDL

pkgsrc changes:
 - Add common Makefile.common for MyHDL packages
 - 0.9.0 supports now Python 3.x
 - update LICENSE to gnu-lgpl-v2.1
 - replace local patch in MyHDL-gplcver and use MAKE_FLAGS to enforce INCS
 - set CC in MyHDL-gplcver
 - setup test target in cad/py-MyHDL
 - share common distinfo
 - replace AUTO_MKDIRS with INSTALLATION_DIRS
 - switch MASTER_SITES to GitHub

upstream changelog
==================
What’s new in MyHDL 0.9
Python 3 support

Experimental Python 3 support has been added to MyHDL 0.9. This was a major effort to modernize the code. As a result, Python 2 and 3 are supported from a single codebase.

See Python 3 Support for more info.
Interfaces (Conversion of attribute accesses)
Rationale

Complex designs often have many signals that are passed to different levels of hierarchy. Typically, many signals logically belong together. This can be modelled by an interface: an object that has a number of Signal objects as its attributes. Grouping signals into an interface simplifies the code, improves efficiency, and reduces errors.

The following is an example of an interface definition:

class Complex:
    def __init__(self, min=-2, max=2):
        self.real = Signal(intbv(0, min=min, max=max))
        self.imag = Signal(intbv(0, min=min, max=max))

Although previous versions supported interfaces for modeling, they were not convertible. MyHDL 0.9 now supports conversion of designs that use interfaces.

The following is an example using the above Complex interface definition:

a,b = Complex(-8,8), Complex(-8,8)
c = Complex(-128,128)

def complex_multiply(clock, reset, a, b, c):

    @always_seq(clock.posedge, reset=reset)
    def cmult():
        c.real.next = (a.real*b.real) - (a.imag*b.imag)
        c.imag.next = (a.real*b.imag) + (a.imag*b.real)

    return cmult

Solution

The proposed solution is to create unique names for attributes which are used by MyHDL generators. The converter will create a unique name by using the name of the parent and the name of the attribute along with the name of the MyHDL module instance. The converter will essentially replace the ”.” with an “_” for each interface element. In essence, interfaces are supported using hierarchical name expansion and name mangling.

Note that the MyHDL convertor supports interfaces, even though the target HDLs do not. This is another great example where the convertor supports a high-level feature that is not available in the target HDLs.
See also

For additional information see the original proposal mep-107.
Other noteworthy improvements
ConcatSignal interface

The interface of ConcatSignal was enhanced. In addition to signals, you can now also use constant values in the concatenation.
std_logic type ports

toVHDL() has a new attibute std_logic_ports. When set, only std_logic type ports are used in the interface of the top-level VHDL module.
Development flow

The MyHDL development flow has been modernized by moving to git and github for version control. In addition, travis has set up so that all pull requests are tested automatically, enabling continuous intergration.
Acknowledgments

The Python 3 support effort was coordinated by Keerthan Jaic, who also implemented most of if. Convertible interfaces were championed by Chris Felton, and implemented by Keerthan Jaic.

MyHDL development is a collaborative effort, as can be seen on github. Thanks to all who contributed with suggestions, issues and pull requests.

10 files changed, 106 insertions, 73 deletions

diff --git a/cad/MyHDL-gplcver/Makefile b/cad/MyHDL-gplcver/Makefile
index c9b34d1051b..a88bcb4a741 100644
--- a/cad/MyHDL-gplcver/Makefile
+++ b/cad/MyHDL-gplcver/Makefile
@@ -1,27 +1,22 @@
-# $NetBSD: Makefile,v 1.8 2015/01/04 02:51:44 mef Exp $
-#
+# $NetBSD: Makefile,v 1.9 2016/10/09 03:15:57 kamil Exp $
+
+.include "../../cad/py-MyHDL/Makefile.common"
 
-DISTNAME=	myhdl-0.8.1
 PKGNAME=	${DISTNAME:S/myhdl/MyHDL-gplcver/}
-CATEGORIES=	cad python
-MASTER_SITES=	${MASTER_SITE_SOURCEFORGE:=myhdl/}
 
 MAINTAINER=	pkgsrc-users@NetBSD.org
-HOMEPAGE=	http://jandecaluwe.com/Tools/MyHDL/Overview.html
 COMMENT=	GPL Cver cosimulation support for py-MyHDL
-LICENSE=	gnu-gpl-v2
 
 BUILD_DIRS+=	cosimulation/cver
-MAKE_FILE=	makefile.lnx
-AUTO_MKDIRS=	yes
+MAKE_FILE=	Makefile.lnx
+MAKE_FLAGS+=	INCS=-I${BUILDLINK_PREFIX.gplcver}/lib/gplcver/pli_incs/
+MAKE_FLAGS+=	CC=${CC:Q}
+
+INSTALLATION_DIRS+=	lib/gplcver
 
 do-install:
 	${INSTALL_DATA} ${WRKSRC}/cosimulation/cver/myhdl_vpi.so \
 		${DESTDIR}${PREFIX}/lib/gplcver
 
-# XXX would require Python dependency
-#do-test:
-#	(cd ${WRKSRC}/cosimulation/cver/test && ${PYTHONBIN} test_all.py)
-
 .include "../../cad/gplcver/buildlink3.mk"
 .include "../../mk/bsd.pkg.mk"
diff --git a/cad/MyHDL-gplcver/distinfo b/cad/MyHDL-gplcver/distinfo
deleted file mode 100644
index fcaa278de02..00000000000
--- a/cad/MyHDL-gplcver/distinfo
+++ /dev/null
@@ -1,7 +0,0 @@
-$NetBSD: distinfo,v 1.5 2015/11/03 00:21:15 agc Exp $
-
-SHA1 (myhdl-0.8.1.tar.gz) = 9b34a04c57166d99df4eec74bd8c2201e8736cd0
-RMD160 (myhdl-0.8.1.tar.gz) = da08bb105e58a13a5fa22320c8d4e7efda5d1b02
-SHA512 (myhdl-0.8.1.tar.gz) = 760d4e2e6dc6973879bb65485c281b9d69af0e650702e820efd7d86d07a21916a8af8c519348df0082ee5fe7bdf6dcbb4f584033846f89599e39751abd7ae726
-Size (myhdl-0.8.1.tar.gz) = 579332 bytes
-SHA1 (patch-aa) = 7ed6848aa47394cf714cc9521b1a7e4e456c80a9
diff --git a/cad/MyHDL-gplcver/patches/patch-aa b/cad/MyHDL-gplcver/patches/patch-aa
deleted file mode 100644
index 1839423f2ad..00000000000
--- a/cad/MyHDL-gplcver/patches/patch-aa
+++ /dev/null
@@ -1,13 +0,0 @@
-$NetBSD: patch-aa,v 1.3 2011/04/13 16:14:10 drochner Exp $
-
---- cosimulation/cver/makefile.lnx.orig	2010-10-14 17:58:48.000000000 +0000
-+++ cosimulation/cver/makefile.lnx
-@@ -2,7 +2,7 @@
- WARNS=-Wall
- 
- # change this path to point to the pli include files directory for cver
--INCS=-I$(HOME)/Tools/gplcver-2.12a.src/pli_incs
-+INCS=-I$(LOCALBASE)/lib/gplcver/pli_incs
- 
- # maybe want -O<something> and/or -g
- # -fno-stack-protector apparently needed with newer gcc's
diff --git a/cad/MyHDL-iverilog/Makefile b/cad/MyHDL-iverilog/Makefile
index 22584367e3b..ee2f8d211e2 100644
--- a/cad/MyHDL-iverilog/Makefile
+++ b/cad/MyHDL-iverilog/Makefile
@@ -1,28 +1,18 @@
-# $NetBSD: Makefile,v 1.9 2016/10/08 23:11:23 kamil Exp $
-#
+# $NetBSD: Makefile,v 1.10 2016/10/09 03:15:57 kamil Exp $
+
+.include "../../cad/py-MyHDL/Makefile.common"
 
-DISTNAME=	myhdl-0.8.1
-PKGNAME=	MyHDL-iverilog-0.7
-PKGREVISION=	1
 PKGNAME=	${DISTNAME:C/myhdl/MyHDL-iverilog/}
-CATEGORIES=	cad python
-MASTER_SITES=	${MASTER_SITE_SOURCEFORGE:=myhdl/}
 
 MAINTAINER=	pkgsrc-users@NetBSD.org
-HOMEPAGE=	http://jandecaluwe.com/Tools/MyHDL/Overview.html
 COMMENT=	Icarus Verilog cosimulation support for py-MyHDL
-LICENSE=	gnu-gpl-v2
 
-BUILD_DIRS+=	cosimulation/icarus
-AUTO_MKDIRS=	yes
+BUILD_DIRS+=		cosimulation/icarus
+INSTALLATION_DIRS+=	lib/ivl
 
 do-install:
 	${INSTALL_DATA} ${WRKSRC}/cosimulation/icarus/myhdl.vpi \
 		${DESTDIR}${PREFIX}/lib/ivl
 
-# XXX would require Python dependency
-#do-test:
-#	(cd ${WRKSRC}/cosimulation/icarus/test && ${PYTHONBIN} test_all.py)
-
 .include "../../cad/iverilog/buildlink3.mk"
 .include "../../mk/bsd.pkg.mk"
diff --git a/cad/MyHDL-iverilog/PLIST b/cad/MyHDL-iverilog/PLIST
index f18708e6adb..58ac604ccd9 100644
--- a/cad/MyHDL-iverilog/PLIST
+++ b/cad/MyHDL-iverilog/PLIST
@@ -1,2 +1,2 @@
-@comment $NetBSD: PLIST,v 1.1.1.1 2006/02/10 17:05:03 drochner Exp $
+@comment $NetBSD: PLIST,v 1.2 2016/10/09 03:15:57 kamil Exp $
 lib/ivl/myhdl.vpi
diff --git a/cad/MyHDL-iverilog/distinfo b/cad/MyHDL-iverilog/distinfo
deleted file mode 100644
index a111ddfa9c2..00000000000
--- a/cad/MyHDL-iverilog/distinfo
+++ /dev/null
@@ -1,6 +0,0 @@
-$NetBSD: distinfo,v 1.5 2015/11/03 00:21:15 agc Exp $
-
-SHA1 (myhdl-0.8.1.tar.gz) = 9b34a04c57166d99df4eec74bd8c2201e8736cd0
-RMD160 (myhdl-0.8.1.tar.gz) = da08bb105e58a13a5fa22320c8d4e7efda5d1b02
-SHA512 (myhdl-0.8.1.tar.gz) = 760d4e2e6dc6973879bb65485c281b9d69af0e650702e820efd7d86d07a21916a8af8c519348df0082ee5fe7bdf6dcbb4f584033846f89599e39751abd7ae726
-Size (myhdl-0.8.1.tar.gz) = 579332 bytes
diff --git a/cad/py-MyHDL/Makefile b/cad/py-MyHDL/Makefile
index 11b5044828b..2bc99da007d 100644
--- a/cad/py-MyHDL/Makefile
+++ b/cad/py-MyHDL/Makefile
@@ -1,19 +1,27 @@
-# $NetBSD: Makefile,v 1.23 2016/07/09 13:03:32 wiz Exp $
+# $NetBSD: Makefile,v 1.24 2016/10/09 03:15:57 kamil Exp $
+
+.include "Makefile.common"
 
-DISTNAME=	myhdl-0.8.1
 PKGNAME=	${PYPKGPREFIX}-${DISTNAME:S/myhdl/MyHDL/}
-CATEGORIES=	cad python
-MASTER_SITES=	${MASTER_SITE_SOURCEFORGE:=myhdl/}
 
 MAINTAINER=	pkgsrc-users@NetBSD.org
-HOMEPAGE=	http://jandecaluwe.com/Tools/MyHDL/Overview.html
 COMMENT=	Hardware description in Python
-LICENSE=	gnu-gpl-v2
 
-PYTHON_VERSIONS_INCOMPATIBLE=	34 35 # not yet ported as of 0.7
+# TEST_DEPENDS
+BUILD_DEPENDS+=	${PYPKGPREFIX}-test-[0-9]*:../../devel/py-test
+
+.include "../../lang/python/pyversion.mk"
+
+# Python 2.x only -- subprocess is part of Python 3.x
+.if ${_PYTHON_VERSION} < 32
+BUILD_DEPENDS+=	${PYPKGPREFIX}-subprocess32-[0-9]*:../../devel/py-subprocess32
+.endif
 
 do-test:
-	cd ${WRKSRC}/myhdl/test/core && ${PYTHONBIN} test_all.py
+	${RUN} cd ${WRKSRC}/myhdl/test/core && \
+		${SETENV} ${TEST_ENV} \
+		PYTHONPATH=${DESTDIR}${PREFIX}/${PYSITELIB} \
+			py.test-${PYVERSSUFFIX}
 
 .include "../../lang/python/distutils.mk"
 .include "../../mk/bsd.pkg.mk"
diff --git a/cad/py-MyHDL/Makefile.common b/cad/py-MyHDL/Makefile.common
new file mode 100644
index 00000000000..0694a39164a
--- /dev/null
+++ b/cad/py-MyHDL/Makefile.common
@@ -0,0 +1,15 @@
+# $NetBSD: Makefile.common,v 1.1 2016/10/09 03:15:57 kamil Exp $
+#
+# used by cad/MyHDL-gplcver/Makefile
+# used by cad/MyHDL-iverilog/Makefile
+
+GITHUB_PROJECT=	myhdl
+DISTNAME=	myhdl-0.9.0
+CATEGORIES=	cad python
+MASTER_SITES=	${MASTER_SITE_GITHUB:=jandecaluwe/}
+
+HOMEPAGE=	http://myhdl.org/
+LICENSE=	gnu-lgpl-v2.1
+
+DISTINFO_FILE=	${.CURDIR}/../../cad/py-MyHDL/distinfo
+PATCHDIR=	${.CURDIR}/../../cad/py-MyHDL/patches
diff --git a/cad/py-MyHDL/PLIST b/cad/py-MyHDL/PLIST
index a4d4a172bc9..66e42328f22 100644
--- a/cad/py-MyHDL/PLIST
+++ b/cad/py-MyHDL/PLIST
@@ -1,5 +1,8 @@
-@comment $NetBSD: PLIST,v 1.9 2015/01/04 02:21:53 mef Exp $
-${PYSITELIB}/${EGG_FILE}
+@comment $NetBSD: PLIST,v 1.10 2016/10/09 03:15:57 kamil Exp $
+${PYSITELIB}/${EGG_FILE}/PKG-INFO
+${PYSITELIB}/${EGG_FILE}/SOURCES.txt
+${PYSITELIB}/${EGG_FILE}/dependency_links.txt
+${PYSITELIB}/${EGG_FILE}/top_level.txt
 ${PYSITELIB}/myhdl/_Cosimulation.py
 ${PYSITELIB}/myhdl/_Cosimulation.pyc
 ${PYSITELIB}/myhdl/_Cosimulation.pyo
@@ -33,6 +36,9 @@ ${PYSITELIB}/myhdl/_bin.pyo
 ${PYSITELIB}/myhdl/_cell_deref.py
 ${PYSITELIB}/myhdl/_cell_deref.pyc
 ${PYSITELIB}/myhdl/_cell_deref.pyo
+${PYSITELIB}/myhdl/_compat.py
+${PYSITELIB}/myhdl/_compat.pyc
+${PYSITELIB}/myhdl/_compat.pyo
 ${PYSITELIB}/myhdl/_concat.py
 ${PYSITELIB}/myhdl/_concat.pyc
 ${PYSITELIB}/myhdl/_concat.pyo
@@ -60,6 +66,9 @@ ${PYSITELIB}/myhdl/_misc.pyo
 ${PYSITELIB}/myhdl/_modbv.py
 ${PYSITELIB}/myhdl/_modbv.pyc
 ${PYSITELIB}/myhdl/_modbv.pyo
+${PYSITELIB}/myhdl/_resolverefs.py
+${PYSITELIB}/myhdl/_resolverefs.pyc
+${PYSITELIB}/myhdl/_resolverefs.pyo
 ${PYSITELIB}/myhdl/_simulator.py
 ${PYSITELIB}/myhdl/_simulator.pyc
 ${PYSITELIB}/myhdl/_simulator.pyo
@@ -69,9 +78,6 @@ ${PYSITELIB}/myhdl/_traceSignals.pyo
 ${PYSITELIB}/myhdl/_tristate.py
 ${PYSITELIB}/myhdl/_tristate.pyc
 ${PYSITELIB}/myhdl/_tristate.pyo
-${PYSITELIB}/myhdl/_unparse.py
-${PYSITELIB}/myhdl/_unparse.pyc
-${PYSITELIB}/myhdl/_unparse.pyo
 ${PYSITELIB}/myhdl/_util.py
 ${PYSITELIB}/myhdl/_util.pyc
 ${PYSITELIB}/myhdl/_util.pyo
@@ -96,3 +102,48 @@ ${PYSITELIB}/myhdl/conversion/_toVerilog.pyo
 ${PYSITELIB}/myhdl/conversion/_verify.py
 ${PYSITELIB}/myhdl/conversion/_verify.pyc
 ${PYSITELIB}/myhdl/conversion/_verify.pyo
+share/myhdl/cosimulation/cver/Makefile.lnx
+share/myhdl/cosimulation/cver/Makefile.lnx64
+share/myhdl/cosimulation/cver/Makefile.osx
+share/myhdl/cosimulation/cver/README.txt
+share/myhdl/cosimulation/cver/myhdl_vpi.c
+share/myhdl/cosimulation/cver/test/bin2gray.py
+share/myhdl/cosimulation/cver/test/dff.py
+share/myhdl/cosimulation/cver/test/dff_clkout.py
+share/myhdl/cosimulation/cver/test/inc.py
+share/myhdl/cosimulation/cver/test/test_all.py
+share/myhdl/cosimulation/icarus/Makefile
+share/myhdl/cosimulation/icarus/README.txt
+share/myhdl/cosimulation/icarus/myhdl.c
+share/myhdl/cosimulation/icarus/myhdl_20030518.c
+share/myhdl/cosimulation/icarus/myhdl_table.c
+share/myhdl/cosimulation/icarus/test/bin2gray.py
+share/myhdl/cosimulation/icarus/test/dff.py
+share/myhdl/cosimulation/icarus/test/dff_clkout.py
+share/myhdl/cosimulation/icarus/test/inc.py
+share/myhdl/cosimulation/icarus/test/tb_test.v
+share/myhdl/cosimulation/icarus/test/test.py
+share/myhdl/cosimulation/icarus/test/test_all.py
+share/myhdl/cosimulation/modelsim/Makefile
+share/myhdl/cosimulation/modelsim/myhdl_vpi.c
+share/myhdl/cosimulation/modelsim/test/bin2gray.py
+share/myhdl/cosimulation/modelsim/test/dff.py
+share/myhdl/cosimulation/modelsim/test/dff_clkout.py
+share/myhdl/cosimulation/modelsim/test/inc.py
+share/myhdl/cosimulation/modelsim/test/test_all.py
+share/myhdl/cosimulation/test/bin2gray.py
+share/myhdl/cosimulation/test/dff.py
+share/myhdl/cosimulation/test/dff_clkout.py
+share/myhdl/cosimulation/test/inc.py
+share/myhdl/cosimulation/test/test_all.py
+share/myhdl/cosimulation/test/test_bin2gray.py
+share/myhdl/cosimulation/test/test_dff.py
+share/myhdl/cosimulation/test/test_inc.py
+share/myhdl/cosimulation/test/verilog/bin2gray.v
+share/myhdl/cosimulation/test/verilog/dff.v
+share/myhdl/cosimulation/test/verilog/dff_clkout.v
+share/myhdl/cosimulation/test/verilog/dut_bin2gray.v
+share/myhdl/cosimulation/test/verilog/dut_dff.v
+share/myhdl/cosimulation/test/verilog/dut_dff_clkout.v
+share/myhdl/cosimulation/test/verilog/dut_inc.v
+share/myhdl/cosimulation/test/verilog/inc.v
diff --git a/cad/py-MyHDL/distinfo b/cad/py-MyHDL/distinfo
index 29d98ca5317..826a5d218b1 100644
--- a/cad/py-MyHDL/distinfo
+++ b/cad/py-MyHDL/distinfo
@@ -1,6 +1,6 @@
-$NetBSD: distinfo,v 1.8 2015/11/03 00:21:18 agc Exp $
+$NetBSD: distinfo,v 1.9 2016/10/09 03:15:57 kamil Exp $
 
-SHA1 (myhdl-0.8.1.tar.gz) = 9b34a04c57166d99df4eec74bd8c2201e8736cd0
-RMD160 (myhdl-0.8.1.tar.gz) = da08bb105e58a13a5fa22320c8d4e7efda5d1b02
-SHA512 (myhdl-0.8.1.tar.gz) = 760d4e2e6dc6973879bb65485c281b9d69af0e650702e820efd7d86d07a21916a8af8c519348df0082ee5fe7bdf6dcbb4f584033846f89599e39751abd7ae726
-Size (myhdl-0.8.1.tar.gz) = 579332 bytes
+SHA1 (myhdl-0.9.0.tar.gz) = 90ee6ab6983d4c11a30a6cca5c749e4affdd8ff1
+RMD160 (myhdl-0.9.0.tar.gz) = 1aac0472829b8a3b171364ed3c85fd9e87a41537
+SHA512 (myhdl-0.9.0.tar.gz) = 6204b1dec7bf16e44e313eff5a76243f64b7f08639a7ca81d621785f022120be37e85e4f8f35a4bb19f05bbfcceb7933f5acbacd71981bd05a87d34fdd71d32d
+Size (myhdl-0.9.0.tar.gz) = 463038 bytes