Update to 20060809 snapshot. There have been several changes since the

last packaged snapshot.  Those are:

--------------------------------------------------
Release Notes for Icarus Verilog Snapshot 20060215
--------------------------------------------------

* Part select of memory words should now work according to
  Verilog-2001. This also led to some cleanup of the handling of types
  internally, as well as some infrastructure for general arrays.

* Minor fix to parsing of (* *) attributes.

* Fix rounding of reals to integers.

* Clean up some of the vvp engine related to memories. Remove some
  dead instructions.

--------------------------------------------------
Release Notes for Icarus Verilog Snapshot 20060409
--------------------------------------------------

the most substantial difference in this snapshot the first signs of
generate support. The compiler now supports generate loops and has
been tested with examples that include wires and gates within the
generate scheme. The regression test suite has very few generate
tests, so any concise self-testing test programs that use generate
would be helpful.

Also, instance arrays that use overridden parameters now work
properly.

Task arguments are a bit more flexible in order to support vendor
(notably Xilinx) models that use more interesting task arguments.

Runtime support for bi-directional ports had some bugs fixed, along
with some other minor run-time bugs. Also, the runtime gains support
for typed parameters. And also, there are some new runtime callbacks
for events and memories.

Parameters had a few types related bugs fixed. They are a bit more
flexible now.

And various minor compilation errors have been fixed. This includes
C/C++ compilation errors fixes, and some configure/Makefile tweaks.

--------------------------------------------------
Release Notes for Icarus Verilog Snapshot 20060618
--------------------------------------------------

Add support for system functions in continuous assignments.

Allow concatenations as arguments to inout ports. This comes with a
small variety of internal part select and concatenation bug fixes.

Fix some bugs in constant propagation through ternary expressions.
Fix broken subtraction if small constants in certain cases.
Fix a few datatype mismatch errors.

Make $readmem give warning when input is inadequate for requested
range.

Fix runtime of nand in continuous assignments.

Fix synchronous user defined primiteves to only follow edges.

Fix a runtime error in some thread delays processing.

Improve limited genvar expression handling.

Start a rework of expression elaboration. Make elaboration aware of
the expression context width when appropriate in order to better
handle expression width and padding.

Fix the make rules for parse.cc to reflect that they come from the
same source. Fix the autoconf.sh to configure the stub target.

Fix portability of the lexor source files on Windows systems. Get rid
of the isatty references.

Make a stub lround when the system version is missing.

--------------------------------------------------
* Release Notes for Snapshot 20060809
--------------------------------------------------

Some handling of real values is improved. Real valued literals are
handled in net contexts (continuous assignment, etc.). Also, modulus
of real operands now works. (This is an extension to the Verilog
standard.)

The power operator (**) now works.

Signed right shift works properly now.

The $sscanf and $fscanf are introduced, and work at least for basic
numeric values.

The release function now works to undo general force statements, and
not just contant force statements.

Delay constants up to 64 bits are supported. This at first doesn't
seem like an issue, but when precisions are mixed, it becomes
surprisingly easy to overflow 32bit delays.

The driver is reworked to pass many preprocessor details through a
temporary file instead of on the command line of a system(3)
call. This prevents confusing and incorrect shell processing of
complex strings passed as values to -D flags.

Various other little fixes.

5 files changed, 19 insertions, 21 deletions

diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index a3024f097e0..25bb87b5bc9 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,9 +1,8 @@
-# $NetBSD: Makefile,v 1.51 2006/02/05 23:08:23 joerg Exp $
+# $NetBSD: Makefile,v 1.52 2006/08/11 13:28:08 dmcmahill Exp $
 #
 
 DISTNAME=	verilog-${SNAPDATE}
 PKGNAME=	verilog-current-${SNAPDATE}
-PKGREVISION=	1
 CATEGORIES=	cad
 MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/snapshots/
 
@@ -18,11 +17,11 @@ CONFLICTS+=	verilog-[0-9]*
 GCC_REQD+=	3.0
 USE_LANGUAGES=	c c++
 
-SNAPDATE=		20060124
+SNAPDATE=		20060809
 GNU_CONFIGURE=		yes
 USE_TOOLS+=		bison gmake lex
 CONFIGURE_ARGS+=	--without-ipal
-TEST_DIRS=		${WRKSRC}
+TEST_DIRS=		.
 TEST_TARGET=		check
 
 .include "../../devel/zlib/buildlink3.mk"
diff --git a/cad/verilog-current/PLIST b/cad/verilog-current/PLIST
index edceef6ce75..b9b4371f717 100644
--- a/cad/verilog-current/PLIST
+++ b/cad/verilog-current/PLIST
@@ -1,4 +1,4 @@
-@comment $NetBSD: PLIST,v 1.8 2006/01/25 12:11:01 dmcmahill Exp $
+@comment $NetBSD: PLIST,v 1.9 2006/08/11 13:28:08 dmcmahill Exp $
 bin/iverilog
 bin/iverilog-vpi
 bin/vvp
@@ -15,13 +15,14 @@ lib/ivl/ivlpp
 lib/ivl/null-s.conf
 lib/ivl/null.conf
 lib/ivl/null.tgt
+lib/ivl/stub-s.conf
+lib/ivl/stub.conf
+lib/ivl/stub.tgt
 lib/ivl/system.sft
 lib/ivl/system.vpi
 lib/ivl/vvp-s.conf
 lib/ivl/vvp.conf
 lib/ivl/vvp.tgt
-lib/ivl/xnf-s.conf
-lib/ivl/xnf.conf
 man/man1/iverilog.1
 man/man1/iverilog-vpi.1
 man/man1/vvp.1
diff --git a/cad/verilog-current/buildlink3.mk b/cad/verilog-current/buildlink3.mk
index 1a85358111a..cf053840531 100644
--- a/cad/verilog-current/buildlink3.mk
+++ b/cad/verilog-current/buildlink3.mk
@@ -1,4 +1,4 @@
-# $NetBSD: buildlink3.mk,v 1.7 2006/07/08 23:10:38 jlam Exp $
+# $NetBSD: buildlink3.mk,v 1.8 2006/08/11 13:28:08 dmcmahill Exp $
 
 BUILDLINK_DEPTH:=		${BUILDLINK_DEPTH}+
 VERILOG_CURRENT_BUILDLINK3_MK:=	${VERILOG_CURRENT_BUILDLINK3_MK}+
@@ -13,7 +13,7 @@ BUILDLINK_ORDER:=	${BUILDLINK_ORDER} ${BUILDLINK_DEPTH}verilog-current
 
 .if !empty(VERILOG_CURRENT_BUILDLINK3_MK:M+)
 BUILDLINK_API_DEPENDS.verilog-current+=	verilog-current>=20021019
-BUILDLINK_ABI_DEPENDS.verilog-current?=	verilog-current>=20060124nb1
+BUILDLINK_ABI_DEPENDS.verilog-current?=	verilog-current>=20060809
 BUILDLINK_PKGSRCDIR.verilog-current?=	../../cad/verilog-current
 .endif	# VERILOG_CURRENT_BUILDLINK3_MK
 
diff --git a/cad/verilog-current/distinfo b/cad/verilog-current/distinfo
index b9709dd2946..c99eb5fb4e8 100644
--- a/cad/verilog-current/distinfo
+++ b/cad/verilog-current/distinfo
@@ -1,6 +1,6 @@
-$NetBSD: distinfo,v 1.25 2006/01/25 12:11:01 dmcmahill Exp $
+$NetBSD: distinfo,v 1.26 2006/08/11 13:28:08 dmcmahill Exp $
 
-SHA1 (verilog-20060124.tar.gz) = 4b3784aeb5b91c0672522cd420dd96e73bd4e33c
-RMD160 (verilog-20060124.tar.gz) = de536f3d9c811dbbeea36bb64007aa26355dddcb
-Size (verilog-20060124.tar.gz) = 1507887 bytes
-SHA1 (patch-ad) = ef3fe90fb096b96807b2e5766f3ac6849867352a
+SHA1 (verilog-20060809.tar.gz) = a24c822230472df69c646366f5a6a8ff79386965
+RMD160 (verilog-20060809.tar.gz) = b34fe487677aaf4f417649b7cad7e7bf994d16be
+Size (verilog-20060809.tar.gz) = 1584583 bytes
+SHA1 (patch-ad) = 9492af75153405c49076f2dcd11d2dc338640514
diff --git a/cad/verilog-current/patches/patch-ad b/cad/verilog-current/patches/patch-ad
index 994781c9ebb..f6c2be77b90 100644
--- a/cad/verilog-current/patches/patch-ad
+++ b/cad/verilog-current/patches/patch-ad
@@ -1,9 +1,8 @@
-$NetBSD: patch-ad,v 1.12 2003/07/14 09:51:49 drochner Exp $
+$NetBSD: patch-ad,v 1.13 2006/08/11 13:28:08 dmcmahill Exp $
 
---- Makefile.in.orig	2003-06-25 03:48:39.000000000 +0200
-+++ Makefile.in	2003-07-12 19:11:41.000000000 +0200
-@@ -170,7 +170,17 @@
- 
+--- Makefile.in.orig	2006-05-01 20:47:29.000000000 +0000
++++ Makefile.in	2006-08-10 18:21:19.000000000 +0000
+@@ -160,5 +160,15 @@
  lexor.o: lexor.cc parse.h
  
 +# work around buggy compilers when compiling the parser with optimization
@@ -18,5 +17,4 @@ $NetBSD: patch-ad,v 1.12 2003/07/14 09:51:49 drochner Exp $
 +	$(CXX_NOOPT) $(CPPFLAGS_NOOPT) $(CXXFLAGS_NOOPT) -MD -c $< -o $*.o
 +	mv $*.d dep/$*.d
  
- parse.cc: $(srcdir)/parse.y
- 	$(YACC) --verbose -t -p VL -d -o parse.cc $(srcdir)/parse.y
+ parse.cc parse.h: $(srcdir)/parse.y