Fix qemu/amd64 gub regarding signal4

Closes PR port-amd64/51934
thanks to hannken@ for the pointer to the upstream fixes

5 files changed, 155 insertions, 3 deletions

diff --git a/emulators/qemu/Makefile b/emulators/qemu/Makefile
index c5f515b6d07..4ec94adc09c 100644
--- a/emulators/qemu/Makefile
+++ b/emulators/qemu/Makefile
@@ -1,7 +1,7 @@
-# $NetBSD: Makefile,v 1.165 2017/02/27 05:19:29 adam Exp $
+# $NetBSD: Makefile,v 1.166 2017/03/04 15:11:10 spz Exp $
 
 DISTNAME=	qemu-2.8.0
-PKGREVISION=	2
+PKGREVISION=	3
 CATEGORIES=	emulators
 MASTER_SITES=	http://download.qemu-project.org/
 EXTRACT_SUFX=	.tar.bz2
diff --git a/emulators/qemu/distinfo b/emulators/qemu/distinfo
index 4acc0b7ecaf..74b0a35a82a 100644
--- a/emulators/qemu/distinfo
+++ b/emulators/qemu/distinfo
@@ -1,4 +1,4 @@
-$NetBSD: distinfo,v 1.121 2017/02/27 05:19:29 adam Exp $
+$NetBSD: distinfo,v 1.122 2017/03/04 15:11:10 spz Exp $
 
 SHA1 (qemu-2.8.0.tar.bz2) = a5602f2ddb51d61b4c0e618b779fdb0dbdc9cc1f
 RMD160 (qemu-2.8.0.tar.bz2) = da1e640443a15f36a242fe803c65a39f85b06fcc
@@ -20,4 +20,7 @@ SHA1 (patch-hw_ppc_mac__oldworld.c) = b71667ab281dc23c9d971dc8754eeefc879bd1d7
 SHA1 (patch-memory.c) = 9f94de7799ef80931fb1de572e5603894f3fb328
 SHA1 (patch-scripts_qemu-binfmt-conf.sh) = a59c227e5891efe201eb2b8af15fb0832a1b20d0
 SHA1 (patch-slirp_tcp__subr.c) = f011c9dc58282e61b26017547a9884f30a6e6154
+SHA1 (patch-target-i386_bpt__helper.c) = c2aacda7cabb4dcc507e260c0d74a976733a2114
+SHA1 (patch-target-i386_helper.h) = af5316b8796f1d9bf70becea9f09245ec0e6e36c
+SHA1 (patch-target-i386_translate.c) = 837c8f348cfd6e027a6292df7d95381020f90825
 SHA1 (patch-tests_Makefile.include) = 42345d697cb2e324dccf1d68bd8d61e8001c6162
diff --git a/emulators/qemu/patches/patch-target-i386_bpt__helper.c b/emulators/qemu/patches/patch-target-i386_bpt__helper.c
new file mode 100644
index 00000000000..b10e1165be3
--- /dev/null
+++ b/emulators/qemu/patches/patch-target-i386_bpt__helper.c
@@ -0,0 +1,31 @@
+$NetBSD: patch-target-i386_bpt__helper.c,v 1.1 2017/03/04 15:11:11 spz Exp $
+
+from upstream:
+ commit c52ab08aee6f7d4717fc6b517174043126bd302f
+ Author: Doug Evans <dje@google.com>
+ Date:   Tue Dec 6 23:06:30 2016 +0000
+
+     target-i386: Fix eflags.TF/#DB handling of syscall/sysret insns
+
+     The syscall and sysret instructions behave a bit differently:
+     TF is checked after the instruction completes.
+     This allows the o/s to disable #DB at a syscall by adding TF to FMASK.
+     And then when the sysret is executed the #DB is taken "as if" the
+     syscall insn just completed.
+
+--- target-i386/bpt_helper.c.orig	2016-12-20 20:16:49.000000000 +0000
++++ target-i386/bpt_helper.c	2017-03-03 04:30:46.000000000 +0000
+@@ -244,6 +244,13 @@ void helper_single_step(CPUX86State *env
+     raise_exception(env, EXCP01_DB);
+ }
+ 
++void helper_rechecking_single_step(CPUX86State *env)
++{
++    if ((env->eflags & TF_MASK) != 0) {
++        helper_single_step(env);
++    }
++}
++
+ void helper_set_dr(CPUX86State *env, int reg, target_ulong t0)
+ {
+ #ifndef CONFIG_USER_ONLY
diff --git a/emulators/qemu/patches/patch-target-i386_helper.h b/emulators/qemu/patches/patch-target-i386_helper.h
new file mode 100644
index 00000000000..9c0396aaa72
--- /dev/null
+++ b/emulators/qemu/patches/patch-target-i386_helper.h
@@ -0,0 +1,25 @@
+$NetBSD: patch-target-i386_helper.h,v 1.1 2017/03/04 15:11:11 spz Exp $
+
+from upstream:
+ commit c52ab08aee6f7d4717fc6b517174043126bd302f
+ Author: Doug Evans <dje@google.com>
+ Date:   Tue Dec 6 23:06:30 2016 +0000
+
+     target-i386: Fix eflags.TF/#DB handling of syscall/sysret insns
+
+     The syscall and sysret instructions behave a bit differently:
+     TF is checked after the instruction completes.
+     This allows the o/s to disable #DB at a syscall by adding TF to FMASK.
+     And then when the sysret is executed the #DB is taken "as if" the
+     syscall insn just completed.
+
+--- target-i386/helper.h.orig	2016-12-20 20:16:50.000000000 +0000
++++ target-i386/helper.h	2017-03-03 04:41:00.000000000 +0000
+@@ -79,6 +79,7 @@ DEF_HELPER_2(cmpxchg16b_unlocked, void, 
+ DEF_HELPER_2(cmpxchg16b, void, env, tl)
+ #endif
+ DEF_HELPER_1(single_step, void, env)
++DEF_HELPER_1(rechecking_single_step, void, env)
+ DEF_HELPER_1(cpuid, void, env)
+ DEF_HELPER_1(rdtsc, void, env)
+ DEF_HELPER_1(rdtscp, void, env)
diff --git a/emulators/qemu/patches/patch-target-i386_translate.c b/emulators/qemu/patches/patch-target-i386_translate.c
new file mode 100644
index 00000000000..65db0c4018e
--- /dev/null
+++ b/emulators/qemu/patches/patch-target-i386_translate.c
@@ -0,0 +1,93 @@
+$NetBSD: patch-target-i386_translate.c,v 1.1 2017/03/04 15:11:11 spz Exp $
+
+from upstream:
+ commit c52ab08aee6f7d4717fc6b517174043126bd302f
+ Author: Doug Evans <dje@google.com>
+ Date:   Tue Dec 6 23:06:30 2016 +0000
+
+     target-i386: Fix eflags.TF/#DB handling of syscall/sysret insns
+
+     The syscall and sysret instructions behave a bit differently:
+     TF is checked after the instruction completes.
+     This allows the o/s to disable #DB at a syscall by adding TF to FMASK.
+     And then when the sysret is executed the #DB is taken "as if" the
+     syscall insn just completed.
+
+ commit 410e98146ffde201ab4c778823ac8beaa74c4c3f
+ Author: Doug Evans <dje@google.com>
+ Date:   Sat Dec 24 20:29:33 2016 +0000
+
+     target/i386: Fix bad patch application to translate.c
+
+     In commit c52ab08aee6f7d4717fc6b517174043126bd302f,
+     the patch snippet for the "syscall" insn got applied to "iret".
+
+--- target-i386/translate.c.orig	2016-12-20 20:16:50.000000000 +0000
++++ target-i386/translate.c	2017-03-03 04:39:24.000000000 +0000
+@@ -2500,8 +2500,10 @@ static void gen_bnd_jmp(DisasContext *s)
+ }
+ 
+ /* Generate an end of block. Trace exception is also generated if needed.
+-   If IIM, set HF_INHIBIT_IRQ_MASK if it isn't already set.  */
+-static void gen_eob_inhibit_irq(DisasContext *s, bool inhibit)
++   If INHIBIT, set HF_INHIBIT_IRQ_MASK if it isn't already set.
++   If RECHECK_TF, emit a rechecking helper for #DB, ignoring the state of
++   S->TF.  This is used by the syscall/sysret insns.  */
++static void gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf)
+ {
+     gen_update_cc_op(s);
+ 
+@@ -2517,6 +2519,9 @@ static void gen_eob_inhibit_irq(DisasCon
+     }
+     if (s->singlestep_enabled) {
+         gen_helper_debug(cpu_env);
++   } else if (recheck_tf) {
++        gen_helper_rechecking_single_step(cpu_env);
++        tcg_gen_exit_tb(0);
+     } else if (s->tf) {
+         gen_helper_single_step(cpu_env);
+     } else {
+@@ -2525,10 +2530,17 @@ static void gen_eob_inhibit_irq(DisasCon
+     s->is_jmp = DISAS_TB_JUMP;
+ }
+ 
++/* End of block.
++   If INHIBIT, set HF_INHIBIT_IRQ_MASK if it isn't already set.  */
++static void gen_eob_inhibit_irq(DisasContext *s, bool inhibit)
++{
++    gen_eob_worker(s, inhibit, false);
++}
++
+ /* End of block, resetting the inhibit irq flag.  */
+ static void gen_eob(DisasContext *s)
+ {
+-    gen_eob_inhibit_irq(s, false);
++    gen_eob_worker(s, false, false);
+ }
+ 
+ /* generate a jump to eip. No segment change must happen before as a
+@@ -7104,7 +7116,10 @@ static target_ulong disas_insn(CPUX86Sta
+         gen_update_cc_op(s);
+         gen_jmp_im(pc_start - s->cs_base);
+         gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - pc_start));
+-        gen_eob(s);
++        /* TF handling for the syscall insn is different. The TF bit is  checked
++           after the syscall insn completes. This allows #DB to not be
++           generated after one has entered CPL0 if TF is set in FMASK.  */
++        gen_eob_worker(s, false, true);
+         break;
+     case 0x107: /* sysret */
+         if (!s->pe) {
+@@ -7115,7 +7130,11 @@ static target_ulong disas_insn(CPUX86Sta
+             if (s->lma) {
+                 set_cc_op(s, CC_OP_EFLAGS);
+             }
+-            gen_eob(s);
++            /* TF handling for the sysret insn is different. The TF bit is
++               checked after the sysret insn completes. This allows #DB to be
++               generated "as if" the syscall insn in userspace has just
++               completed.  */
++            gen_eob_worker(s, false, true);
+         }
+         break;
+ #endif